xhci.c revision 1.24
1 /* $NetBSD: xhci.c,v 1.24 2014/08/11 10:37:59 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.24 2014/08/11 10:37:59 skrll Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/kmem.h> 36 #include <sys/malloc.h> 37 #include <sys/device.h> 38 #include <sys/select.h> 39 #include <sys/proc.h> 40 #include <sys/queue.h> 41 #include <sys/mutex.h> 42 #include <sys/condvar.h> 43 #include <sys/bus.h> 44 #include <sys/cpu.h> 45 46 #include <machine/endian.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 #include <dev/usb/usbdivar.h> 51 #include <dev/usb/usb_mem.h> 52 #include <dev/usb/usb_quirks.h> 53 54 #include <dev/usb/xhcireg.h> 55 #include <dev/usb/xhcivar.h> 56 #include <dev/usb/usbroothub_subr.h> 57 58 #ifdef XHCI_DEBUG 59 int xhcidebug = 0; 60 #define DPRINTF(x) do { if (xhcidebug) printf x; } while(0) 61 #define DPRINTFN(n,x) do { if (xhcidebug>(n)) printf x; } while (0) 62 #else 63 #define DPRINTF(x) 64 #define DPRINTFN(n,x) 65 #endif 66 67 #define XHCI_DCI_SLOT 0 68 #define XHCI_DCI_EP_CONTROL 1 69 70 #define XHCI_ICI_INPUT_CONTROL 0 71 72 struct xhci_pipe { 73 struct usbd_pipe xp_pipe; 74 }; 75 76 #define XHCI_INTR_ENDPT 1 77 #define XHCI_COMMAND_RING_TRBS 256 78 #define XHCI_EVENT_RING_TRBS 256 79 #define XHCI_EVENT_RING_SEGMENTS 1 80 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 81 82 static usbd_status xhci_open(usbd_pipe_handle); 83 static int xhci_intr1(struct xhci_softc * const); 84 static void xhci_softintr(void *); 85 static void xhci_poll(struct usbd_bus *); 86 static usbd_status xhci_allocm(struct usbd_bus *, usb_dma_t *, uint32_t); 87 static void xhci_freem(struct usbd_bus *, usb_dma_t *); 88 static usbd_xfer_handle xhci_allocx(struct usbd_bus *); 89 static void xhci_freex(struct usbd_bus *, usbd_xfer_handle); 90 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 91 static usbd_status xhci_new_device(device_t, usbd_bus_handle, int, int, int, 92 struct usbd_port *); 93 94 static usbd_status xhci_configure_endpoint(usbd_pipe_handle); 95 static usbd_status xhci_unconfigure_endpoint(usbd_pipe_handle); 96 static usbd_status xhci_reset_endpoint(usbd_pipe_handle); 97 //static usbd_status xhci_stop_endpoint(usbd_pipe_handle); 98 99 static usbd_status xhci_set_dequeue(usbd_pipe_handle); 100 101 static usbd_status xhci_do_command(struct xhci_softc * const, 102 struct xhci_trb * const, int); 103 static usbd_status xhci_init_slot(struct xhci_softc * const, uint32_t, 104 int, int, int, int); 105 static usbd_status xhci_enable_slot(struct xhci_softc * const, 106 uint8_t * const); 107 static usbd_status xhci_address_device(struct xhci_softc * const, 108 uint64_t, uint8_t, bool); 109 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 110 struct xhci_slot * const, u_int); 111 static usbd_status xhci_ring_init(struct xhci_softc * const, 112 struct xhci_ring * const, size_t, size_t); 113 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 114 115 static void xhci_noop(usbd_pipe_handle); 116 117 static usbd_status xhci_root_ctrl_transfer(usbd_xfer_handle); 118 static usbd_status xhci_root_ctrl_start(usbd_xfer_handle); 119 static void xhci_root_ctrl_abort(usbd_xfer_handle); 120 static void xhci_root_ctrl_close(usbd_pipe_handle); 121 static void xhci_root_ctrl_done(usbd_xfer_handle); 122 123 static usbd_status xhci_root_intr_transfer(usbd_xfer_handle); 124 static usbd_status xhci_root_intr_start(usbd_xfer_handle); 125 static void xhci_root_intr_abort(usbd_xfer_handle); 126 static void xhci_root_intr_close(usbd_pipe_handle); 127 static void xhci_root_intr_done(usbd_xfer_handle); 128 129 static usbd_status xhci_device_ctrl_transfer(usbd_xfer_handle); 130 static usbd_status xhci_device_ctrl_start(usbd_xfer_handle); 131 static void xhci_device_ctrl_abort(usbd_xfer_handle); 132 static void xhci_device_ctrl_close(usbd_pipe_handle); 133 static void xhci_device_ctrl_done(usbd_xfer_handle); 134 135 static usbd_status xhci_device_intr_transfer(usbd_xfer_handle); 136 static usbd_status xhci_device_intr_start(usbd_xfer_handle); 137 static void xhci_device_intr_abort(usbd_xfer_handle); 138 static void xhci_device_intr_close(usbd_pipe_handle); 139 static void xhci_device_intr_done(usbd_xfer_handle); 140 141 static usbd_status xhci_device_bulk_transfer(usbd_xfer_handle); 142 static usbd_status xhci_device_bulk_start(usbd_xfer_handle); 143 static void xhci_device_bulk_abort(usbd_xfer_handle); 144 static void xhci_device_bulk_close(usbd_pipe_handle); 145 static void xhci_device_bulk_done(usbd_xfer_handle); 146 147 static void xhci_timeout(void *); 148 static void xhci_timeout_task(void *); 149 150 static const struct usbd_bus_methods xhci_bus_methods = { 151 .open_pipe = xhci_open, 152 .soft_intr = xhci_softintr, 153 .do_poll = xhci_poll, 154 .allocm = xhci_allocm, 155 .freem = xhci_freem, 156 .allocx = xhci_allocx, 157 .freex = xhci_freex, 158 .get_lock = xhci_get_lock, 159 .new_device = xhci_new_device, 160 }; 161 162 static const struct usbd_pipe_methods xhci_root_ctrl_methods = { 163 .transfer = xhci_root_ctrl_transfer, 164 .start = xhci_root_ctrl_start, 165 .abort = xhci_root_ctrl_abort, 166 .close = xhci_root_ctrl_close, 167 .cleartoggle = xhci_noop, 168 .done = xhci_root_ctrl_done, 169 }; 170 171 static const struct usbd_pipe_methods xhci_root_intr_methods = { 172 .transfer = xhci_root_intr_transfer, 173 .start = xhci_root_intr_start, 174 .abort = xhci_root_intr_abort, 175 .close = xhci_root_intr_close, 176 .cleartoggle = xhci_noop, 177 .done = xhci_root_intr_done, 178 }; 179 180 181 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 182 .transfer = xhci_device_ctrl_transfer, 183 .start = xhci_device_ctrl_start, 184 .abort = xhci_device_ctrl_abort, 185 .close = xhci_device_ctrl_close, 186 .cleartoggle = xhci_noop, 187 .done = xhci_device_ctrl_done, 188 }; 189 190 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 191 .cleartoggle = xhci_noop, 192 }; 193 194 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 195 .transfer = xhci_device_bulk_transfer, 196 .start = xhci_device_bulk_start, 197 .abort = xhci_device_bulk_abort, 198 .close = xhci_device_bulk_close, 199 .cleartoggle = xhci_noop, 200 .done = xhci_device_bulk_done, 201 }; 202 203 static const struct usbd_pipe_methods xhci_device_intr_methods = { 204 .transfer = xhci_device_intr_transfer, 205 .start = xhci_device_intr_start, 206 .abort = xhci_device_intr_abort, 207 .close = xhci_device_intr_close, 208 .cleartoggle = xhci_noop, 209 .done = xhci_device_intr_done, 210 }; 211 212 static inline uint32_t 213 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 214 { 215 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 216 } 217 218 #if 0 /* unused */ 219 static inline void 220 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 221 uint32_t value) 222 { 223 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 224 } 225 #endif /* unused */ 226 227 static inline uint32_t 228 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 229 { 230 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 231 } 232 233 static inline uint32_t 234 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 235 { 236 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 237 } 238 239 static inline void 240 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 241 uint32_t value) 242 { 243 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 244 } 245 246 #if 0 /* unused */ 247 static inline uint64_t 248 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 249 { 250 uint64_t value; 251 252 if (sc->sc_ac64) { 253 #ifdef XHCI_USE_BUS_SPACE_8 254 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 255 #else 256 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 257 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 258 offset + 4) << 32; 259 #endif 260 } else { 261 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 262 } 263 264 return value; 265 } 266 #endif /* unused */ 267 268 static inline void 269 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 270 uint64_t value) 271 { 272 if (sc->sc_ac64) { 273 #ifdef XHCI_USE_BUS_SPACE_8 274 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 275 #else 276 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 277 (value >> 0) & 0xffffffff); 278 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 279 (value >> 32) & 0xffffffff); 280 #endif 281 } else { 282 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 283 } 284 } 285 286 static inline uint32_t 287 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 288 { 289 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 290 } 291 292 static inline void 293 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 294 uint32_t value) 295 { 296 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 297 } 298 299 #if 0 /* unused */ 300 static inline uint64_t 301 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 302 { 303 uint64_t value; 304 305 if (sc->sc_ac64) { 306 #ifdef XHCI_USE_BUS_SPACE_8 307 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 308 #else 309 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 310 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 311 offset + 4) << 32; 312 #endif 313 } else { 314 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 315 } 316 317 return value; 318 } 319 #endif /* unused */ 320 321 static inline void 322 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 336 } 337 } 338 339 #if 0 /* unused */ 340 static inline uint32_t 341 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 342 { 343 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 344 } 345 #endif /* unused */ 346 347 static inline void 348 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 349 uint32_t value) 350 { 351 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 352 } 353 354 /* --- */ 355 356 static inline uint8_t 357 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 358 { 359 u_int eptype; 360 361 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 362 case UE_CONTROL: 363 eptype = 0x0; 364 break; 365 case UE_ISOCHRONOUS: 366 eptype = 0x1; 367 break; 368 case UE_BULK: 369 eptype = 0x2; 370 break; 371 case UE_INTERRUPT: 372 eptype = 0x3; 373 break; 374 } 375 376 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 377 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 378 return eptype | 0x4; 379 else 380 return eptype; 381 } 382 383 static u_int 384 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 385 { 386 /* xHCI 1.0 section 4.5.1 */ 387 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 388 u_int in = 0; 389 390 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 391 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 392 in = 1; 393 394 return epaddr * 2 + in; 395 } 396 397 static inline u_int 398 xhci_dci_to_ici(const u_int i) 399 { 400 return i + 1; 401 } 402 403 static inline void * 404 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 405 const u_int dci) 406 { 407 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 408 } 409 410 #if 0 /* unused */ 411 static inline bus_addr_t 412 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 413 const u_int dci) 414 { 415 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 416 } 417 #endif /* unused */ 418 419 static inline void * 420 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 421 const u_int ici) 422 { 423 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 424 } 425 426 static inline bus_addr_t 427 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 428 const u_int ici) 429 { 430 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 431 } 432 433 static inline struct xhci_trb * 434 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 435 { 436 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 437 } 438 439 static inline bus_addr_t 440 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 441 { 442 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 443 } 444 445 static inline void 446 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 447 uint32_t control) 448 { 449 trb->trb_0 = parameter; 450 trb->trb_2 = status; 451 trb->trb_3 = control; 452 } 453 454 /* --- */ 455 456 void 457 xhci_childdet(device_t self, device_t child) 458 { 459 struct xhci_softc * const sc = device_private(self); 460 461 KASSERT(sc->sc_child == child); 462 if (child == sc->sc_child) 463 sc->sc_child = NULL; 464 } 465 466 int 467 xhci_detach(struct xhci_softc *sc, int flags) 468 { 469 int rv = 0; 470 471 if (sc->sc_child != NULL) 472 rv = config_detach(sc->sc_child, flags); 473 474 if (rv != 0) 475 return (rv); 476 477 /* XXX unconfigure/free slots */ 478 479 /* verify: */ 480 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 481 xhci_op_write_4(sc, XHCI_USBCMD, 0); 482 /* do we need to wait for stop? */ 483 484 xhci_op_write_8(sc, XHCI_CRCR, 0); 485 xhci_ring_free(sc, &sc->sc_cr); 486 cv_destroy(&sc->sc_command_cv); 487 488 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 489 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 490 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 491 xhci_ring_free(sc, &sc->sc_er); 492 493 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 494 495 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 496 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 497 498 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 499 500 mutex_destroy(&sc->sc_lock); 501 mutex_destroy(&sc->sc_intr_lock); 502 503 pool_cache_destroy(sc->sc_xferpool); 504 505 return rv; 506 } 507 508 int 509 xhci_activate(device_t self, enum devact act) 510 { 511 struct xhci_softc * const sc = device_private(self); 512 513 switch (act) { 514 case DVACT_DEACTIVATE: 515 sc->sc_dying = true; 516 return 0; 517 default: 518 return EOPNOTSUPP; 519 } 520 } 521 522 bool 523 xhci_suspend(device_t dv, const pmf_qual_t *qual) 524 { 525 return false; 526 } 527 528 bool 529 xhci_resume(device_t dv, const pmf_qual_t *qual) 530 { 531 return false; 532 } 533 534 bool 535 xhci_shutdown(device_t self, int flags) 536 { 537 return false; 538 } 539 540 541 static void 542 hexdump(const char *msg, const void *base, size_t len) 543 { 544 #if 0 545 size_t cnt; 546 const uint32_t *p; 547 extern paddr_t vtophys(vaddr_t); 548 549 p = base; 550 cnt = 0; 551 552 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 553 (void *)vtophys((vaddr_t)base)); 554 555 while (cnt < len) { 556 if (cnt % 16 == 0) 557 printf("%p: ", p); 558 else if (cnt % 8 == 0) 559 printf(" |"); 560 printf(" %08x", *p++); 561 cnt += 4; 562 if (cnt % 16 == 0) 563 printf("\n"); 564 } 565 #endif 566 } 567 568 569 int 570 xhci_init(struct xhci_softc *sc) 571 { 572 bus_size_t bsz; 573 uint32_t cap, hcs1, hcs2, hcc, dboff, rtsoff; 574 uint32_t ecp, ecr; 575 uint32_t usbcmd, usbsts, pagesize, config; 576 int i; 577 uint16_t hciversion; 578 uint8_t caplength; 579 580 DPRINTF(("%s\n", __func__)); 581 582 /* XXX Low/Full/High speeds for now */ 583 sc->sc_bus.usbrev = USBREV_2_0; 584 585 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 586 caplength = XHCI_CAP_CAPLENGTH(cap); 587 hciversion = XHCI_CAP_HCIVERSION(cap); 588 589 if ((hciversion < 0x0096) || (hciversion > 0x0100)) { 590 aprint_normal_dev(sc->sc_dev, 591 "xHCI version %x.%x not known to be supported\n", 592 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 593 } else { 594 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 595 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 596 } 597 598 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 599 &sc->sc_cbh) != 0) { 600 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 601 return ENOMEM; 602 } 603 604 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 605 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 606 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 607 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 608 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 609 (void)xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 610 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 611 612 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 613 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 614 aprint_debug_dev(sc->sc_dev, "ac64 %d ctxsz %d\n", sc->sc_ac64, 615 sc->sc_ctxsz); 616 617 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 618 ecp = XHCI_HCC_XECP(hcc) * 4; 619 while (ecp != 0) { 620 ecr = xhci_read_4(sc, ecp); 621 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 622 switch (XHCI_XECP_ID(ecr)) { 623 case XHCI_ID_PROTOCOLS: { 624 uint32_t w0, w4, w8; 625 uint16_t w2; 626 w0 = xhci_read_4(sc, ecp + 0); 627 w2 = (w0 >> 16) & 0xffff; 628 w4 = xhci_read_4(sc, ecp + 4); 629 w8 = xhci_read_4(sc, ecp + 8); 630 aprint_debug_dev(sc->sc_dev, "SP: %08x %08x %08x\n", 631 w0, w4, w8); 632 if (w4 == 0x20425355 && w2 == 0x0300) { 633 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 634 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 635 } 636 if (w4 == 0x20425355 && w2 == 0x0200) { 637 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 638 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 639 } 640 break; 641 } 642 default: 643 break; 644 } 645 ecr = xhci_read_4(sc, ecp); 646 if (XHCI_XECP_NEXT(ecr) == 0) { 647 ecp = 0; 648 } else { 649 ecp += XHCI_XECP_NEXT(ecr) * 4; 650 } 651 } 652 653 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 654 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 655 &sc->sc_obh) != 0) { 656 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 657 return ENOMEM; 658 } 659 660 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 661 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 662 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 663 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 664 return ENOMEM; 665 } 666 667 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 668 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 669 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 670 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 671 return ENOMEM; 672 } 673 674 for (i = 0; i < 100; i++) { 675 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 676 if ((usbsts & XHCI_STS_CNR) == 0) 677 break; 678 usb_delay_ms(&sc->sc_bus, 1); 679 } 680 if (i >= 100) 681 return EIO; 682 683 usbcmd = 0; 684 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 685 usb_delay_ms(&sc->sc_bus, 1); 686 687 usbcmd = XHCI_CMD_HCRST; 688 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 689 for (i = 0; i < 100; i++) { 690 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 691 if ((usbcmd & XHCI_CMD_HCRST) == 0) 692 break; 693 usb_delay_ms(&sc->sc_bus, 1); 694 } 695 if (i >= 100) 696 return EIO; 697 698 for (i = 0; i < 100; i++) { 699 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 700 if ((usbsts & XHCI_STS_CNR) == 0) 701 break; 702 usb_delay_ms(&sc->sc_bus, 1); 703 } 704 if (i >= 100) 705 return EIO; 706 707 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 708 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 709 pagesize = ffs(pagesize); 710 if (pagesize == 0) 711 return EIO; 712 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 713 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 714 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 715 (uint32_t)sc->sc_maxslots); 716 717 usbd_status err; 718 719 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 720 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 721 if (sc->sc_maxspbuf != 0) { 722 err = usb_allocmem(&sc->sc_bus, 723 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 724 &sc->sc_spbufarray_dma); 725 if (err) 726 return err; 727 728 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * sc->sc_maxspbuf, KM_SLEEP); 729 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 730 for (i = 0; i < sc->sc_maxspbuf; i++) { 731 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 732 /* allocate contexts */ 733 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 734 sc->sc_pgsz, dma); 735 if (err) 736 return err; 737 spbufarray[i] = htole64(DMAADDR(dma, 0)); 738 usb_syncmem(dma, 0, sc->sc_pgsz, 739 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 740 } 741 742 usb_syncmem(&sc->sc_spbufarray_dma, 0, 743 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 744 } 745 746 config = xhci_op_read_4(sc, XHCI_CONFIG); 747 config &= ~0xFF; 748 config |= sc->sc_maxslots & 0xFF; 749 xhci_op_write_4(sc, XHCI_CONFIG, config); 750 751 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 752 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 753 if (err) { 754 aprint_error_dev(sc->sc_dev, "command ring init fail\n"); 755 return err; 756 } 757 758 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 759 XHCI_EVENT_RING_SEGMENTS_ALIGN); 760 if (err) { 761 aprint_error_dev(sc->sc_dev, "event ring init fail\n"); 762 return err; 763 } 764 765 usb_dma_t *dma; 766 size_t size; 767 size_t align; 768 769 dma = &sc->sc_eventst_dma; 770 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 771 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 772 KASSERT(size <= (512 * 1024)); 773 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 774 err = usb_allocmem(&sc->sc_bus, size, align, dma); 775 776 memset(KERNADDR(dma, 0), 0, size); 777 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 778 aprint_debug_dev(sc->sc_dev, "eventst: %s %016jx %p %zx\n", 779 usbd_errstr(err), 780 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 781 KERNADDR(&sc->sc_eventst_dma, 0), 782 sc->sc_eventst_dma.block->size); 783 784 dma = &sc->sc_dcbaa_dma; 785 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 786 KASSERT(size <= 2048); 787 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 788 err = usb_allocmem(&sc->sc_bus, size, align, dma); 789 790 memset(KERNADDR(dma, 0), 0, size); 791 if (sc->sc_maxspbuf != 0) { 792 /* 793 * DCBA entry 0 hold the scratchbuf array pointer. 794 */ 795 *(uint64_t *)KERNADDR(dma, 0) = 796 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 797 } 798 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 799 aprint_debug_dev(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n", 800 usbd_errstr(err), 801 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 802 KERNADDR(&sc->sc_dcbaa_dma, 0), 803 sc->sc_dcbaa_dma.block->size); 804 805 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 806 KM_SLEEP); 807 808 cv_init(&sc->sc_command_cv, "xhcicmd"); 809 810 struct xhci_erste *erst; 811 erst = KERNADDR(&sc->sc_eventst_dma, 0); 812 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 813 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 814 erst[0].erste_3 = htole32(0); 815 usb_syncmem(&sc->sc_eventst_dma, 0, 816 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 817 818 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 819 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 820 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 821 XHCI_ERDP_LO_BUSY); 822 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 823 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 824 sc->sc_cr.xr_cs); 825 826 #if 0 827 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 828 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 829 #endif 830 831 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 832 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 833 834 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 835 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 836 xhci_op_read_4(sc, XHCI_USBCMD)); 837 838 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 839 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 840 cv_init(&sc->sc_softwake_cv, "xhciab"); 841 842 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 843 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 844 845 /* Set up the bus struct. */ 846 sc->sc_bus.methods = &xhci_bus_methods; 847 sc->sc_bus.pipe_size = sizeof(struct xhci_pipe); 848 849 return USBD_NORMAL_COMPLETION; 850 } 851 852 int 853 xhci_intr(void *v) 854 { 855 struct xhci_softc * const sc = v; 856 857 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev)) 858 return 0; 859 860 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 861 862 /* If we get an interrupt while polling, then just ignore it. */ 863 if (sc->sc_bus.use_polling) { 864 #ifdef DIAGNOSTIC 865 DPRINTFN(16, ("xhci_intr: ignored interrupt while polling\n")); 866 #endif 867 return 0; 868 } 869 870 return xhci_intr1(sc); 871 } 872 873 int 874 xhci_intr1(struct xhci_softc * const sc) 875 { 876 uint32_t usbsts; 877 uint32_t iman; 878 879 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 880 //device_printf(sc->sc_dev, "%s USBSTS %08x\n", __func__, usbsts); 881 #if 0 882 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 883 return 0; 884 } 885 #endif 886 xhci_op_write_4(sc, XHCI_USBSTS, 887 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 888 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 889 //device_printf(sc->sc_dev, "%s USBSTS %08x\n", __func__, usbsts); 890 891 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 892 //device_printf(sc->sc_dev, "%s IMAN0 %08x\n", __func__, iman); 893 if ((iman & XHCI_IMAN_INTR_PEND) == 0) { 894 return 0; 895 } 896 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 897 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 898 //device_printf(sc->sc_dev, "%s IMAN0 %08x\n", __func__, iman); 899 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 900 //device_printf(sc->sc_dev, "%s USBSTS %08x\n", __func__, usbsts); 901 902 sc->sc_bus.no_intrs++; 903 usb_schedsoftintr(&sc->sc_bus); 904 905 return 1; 906 } 907 908 static usbd_status 909 xhci_configure_endpoint(usbd_pipe_handle pipe) 910 { 911 struct xhci_softc * const sc = pipe->device->bus->hci_private; 912 struct xhci_slot * const xs = pipe->device->hci_private; 913 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 914 usb_endpoint_descriptor_t * const ed = pipe->endpoint->edesc; 915 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 916 struct xhci_trb trb; 917 usbd_status err; 918 uint32_t *cp; 919 920 device_printf(sc->sc_dev, "%s dci %u (0x%x)\n", __func__, dci, 921 pipe->endpoint->edesc->bEndpointAddress); 922 923 /* XXX ensure input context is available? */ 924 925 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 926 927 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 928 cp[0] = htole32(0); 929 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 930 931 /* set up input slot context */ 932 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 933 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 934 cp[1] = htole32(0); 935 cp[2] = htole32(0); 936 cp[3] = htole32(0); 937 938 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 939 if (xfertype == UE_INTERRUPT) { 940 cp[0] = htole32( 941 XHCI_EPCTX_0_IVAL_SET(3) /* XXX */ 942 ); 943 cp[1] = htole32( 944 XHCI_EPCTX_1_CERR_SET(3) | 945 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(pipe->endpoint->edesc)) | 946 XHCI_EPCTX_1_MAXB_SET(0) | 947 XHCI_EPCTX_1_MAXP_SIZE_SET(8) /* XXX */ 948 ); 949 cp[4] = htole32( 950 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 951 ); 952 } else { 953 cp[0] = htole32(0); 954 cp[1] = htole32( 955 XHCI_EPCTX_1_CERR_SET(3) | 956 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(pipe->endpoint->edesc)) | 957 XHCI_EPCTX_1_MAXB_SET(0) | 958 XHCI_EPCTX_1_MAXP_SIZE_SET(512) /* XXX */ 959 ); 960 } 961 *(uint64_t *)(&cp[2]) = htole64( 962 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 963 XHCI_EPCTX_2_DCS_SET(1)); 964 965 /* sync input contexts before they are read from memory */ 966 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 967 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 968 sc->sc_ctxsz * 1); 969 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 970 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 971 972 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 973 trb.trb_2 = 0; 974 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 975 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 976 977 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 978 979 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 980 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 981 sc->sc_ctxsz * 1); 982 983 return err; 984 } 985 986 static usbd_status 987 xhci_unconfigure_endpoint(usbd_pipe_handle pipe) 988 { 989 return USBD_NORMAL_COMPLETION; 990 } 991 992 static usbd_status 993 xhci_reset_endpoint(usbd_pipe_handle pipe) 994 { 995 struct xhci_softc * const sc = pipe->device->bus->hci_private; 996 struct xhci_slot * const xs = pipe->device->hci_private; 997 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 998 struct xhci_trb trb; 999 usbd_status err; 1000 1001 device_printf(sc->sc_dev, "%s\n", __func__); 1002 1003 trb.trb_0 = 0; 1004 trb.trb_2 = 0; 1005 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1006 XHCI_TRB_3_EP_SET(dci) | 1007 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1008 1009 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1010 1011 return err; 1012 } 1013 1014 #if 0 1015 static usbd_status 1016 xhci_stop_endpoint(usbd_pipe_handle pipe) 1017 { 1018 struct xhci_softc * const sc = pipe->device->bus->hci_private; 1019 struct xhci_slot * const xs = pipe->device->hci_private; 1020 struct xhci_trb trb; 1021 usbd_status err; 1022 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 1023 1024 device_printf(sc->sc_dev, "%s\n", __func__); 1025 1026 trb.trb_0 = 0; 1027 trb.trb_2 = 0; 1028 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1029 XHCI_TRB_3_EP_SET(dci) | 1030 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1031 1032 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1033 1034 return err; 1035 } 1036 #endif 1037 1038 static usbd_status 1039 xhci_set_dequeue(usbd_pipe_handle pipe) 1040 { 1041 struct xhci_softc * const sc = pipe->device->bus->hci_private; 1042 struct xhci_slot * const xs = pipe->device->hci_private; 1043 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 1044 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1045 struct xhci_trb trb; 1046 usbd_status err; 1047 1048 device_printf(sc->sc_dev, "%s\n", __func__); 1049 1050 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1051 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1052 BUS_DMASYNC_PREWRITE); 1053 1054 xr->xr_ep = 0; 1055 xr->xr_cs = 1; 1056 1057 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1058 trb.trb_2 = 0; 1059 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1060 XHCI_TRB_3_EP_SET(dci) | 1061 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1062 1063 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1064 1065 return err; 1066 } 1067 1068 static usbd_status 1069 xhci_open(usbd_pipe_handle pipe) 1070 { 1071 usbd_device_handle const dev = pipe->device; 1072 struct xhci_softc * const sc = dev->bus->hci_private; 1073 usb_endpoint_descriptor_t * const ed = pipe->endpoint->edesc; 1074 const int8_t addr = dev->address; 1075 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1076 1077 DPRINTF(("%s\n", __func__)); 1078 DPRINTF(("addr %d\n", addr)); 1079 device_printf(sc->sc_dev, "%s addr %d depth %d port %d speed %d\n", 1080 __func__, addr, dev->depth, dev->powersrc->portno, dev->speed); 1081 1082 if (sc->sc_dying) 1083 return USBD_IOERROR; 1084 1085 /* Root Hub */ 1086 if (dev->depth == 0 && dev->powersrc->portno == 0 && 1087 dev->speed != USB_SPEED_SUPER) { 1088 switch (ed->bEndpointAddress) { 1089 case USB_CONTROL_ENDPOINT: 1090 pipe->methods = &xhci_root_ctrl_methods; 1091 break; 1092 case UE_DIR_IN | XHCI_INTR_ENDPT: 1093 pipe->methods = &xhci_root_intr_methods; 1094 break; 1095 default: 1096 pipe->methods = NULL; 1097 DPRINTF(("xhci_open: bad bEndpointAddress 0x%02x\n", 1098 ed->bEndpointAddress)); 1099 return USBD_INVAL; 1100 } 1101 return USBD_NORMAL_COMPLETION; 1102 } 1103 1104 switch (xfertype) { 1105 case UE_CONTROL: 1106 pipe->methods = &xhci_device_ctrl_methods; 1107 break; 1108 case UE_ISOCHRONOUS: 1109 pipe->methods = &xhci_device_isoc_methods; 1110 return USBD_INVAL; 1111 break; 1112 case UE_BULK: 1113 pipe->methods = &xhci_device_bulk_methods; 1114 break; 1115 case UE_INTERRUPT: 1116 pipe->methods = &xhci_device_intr_methods; 1117 break; 1118 default: 1119 return USBD_IOERROR; 1120 break; 1121 } 1122 1123 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1124 xhci_configure_endpoint(pipe); 1125 1126 return USBD_NORMAL_COMPLETION; 1127 } 1128 1129 static void 1130 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1131 { 1132 usbd_xfer_handle const xfer = sc->sc_intrxfer; 1133 uint8_t *p; 1134 1135 device_printf(sc->sc_dev, "port %u status change\n", port); 1136 1137 if (xfer == NULL) 1138 return; 1139 1140 if (!(port >= sc->sc_hs_port_start && 1141 port < sc->sc_hs_port_start + sc->sc_hs_port_count)) 1142 return; 1143 1144 port -= sc->sc_hs_port_start; 1145 port += 1; 1146 device_printf(sc->sc_dev, "hs port %u status change\n", port); 1147 1148 p = KERNADDR(&xfer->dmabuf, 0); 1149 memset(p, 0, xfer->length); 1150 p[port/NBBY] |= 1 << (port%NBBY); 1151 xfer->actlen = xfer->length; 1152 xfer->status = USBD_NORMAL_COMPLETION; 1153 usb_transfer_complete(xfer); 1154 } 1155 1156 static void 1157 xhci_handle_event(struct xhci_softc * const sc, const struct xhci_trb * const trb) 1158 { 1159 uint64_t trb_0; 1160 uint32_t trb_2, trb_3; 1161 1162 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1163 1164 trb_0 = le64toh(trb->trb_0); 1165 trb_2 = le32toh(trb->trb_2); 1166 trb_3 = le32toh(trb->trb_3); 1167 1168 #if 0 1169 device_printf(sc->sc_dev, 1170 "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"\n", trb, 1171 trb_0, trb_2, trb_3); 1172 #endif 1173 1174 switch (XHCI_TRB_3_TYPE_GET(trb_3)){ 1175 case XHCI_TRB_EVENT_TRANSFER: { 1176 u_int slot, dci; 1177 struct xhci_slot *xs; 1178 struct xhci_ring *xr; 1179 struct xhci_xfer *xx; 1180 usbd_xfer_handle xfer; 1181 usbd_status err; 1182 1183 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1184 dci = XHCI_TRB_3_EP_GET(trb_3); 1185 1186 xs = &sc->sc_slots[slot]; 1187 xr = &xs->xs_ep[dci].xe_tr; 1188 1189 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1190 xx = xr->xr_cookies[(trb_0 - xhci_ring_trbp(xr, 0))/ 1191 sizeof(struct xhci_trb)]; 1192 } else { 1193 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1194 } 1195 xfer = &xx->xx_xfer; 1196 #if 0 1197 device_printf(sc->sc_dev, "%s xfer %p\n", __func__, xfer); 1198 #endif 1199 1200 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1201 #if 0 1202 device_printf(sc->sc_dev, "transfer event data: " 1203 "0x%016"PRIx64" 0x%08"PRIx32" %02x\n", 1204 trb_0, XHCI_TRB_2_REM_GET(trb_2), 1205 XHCI_TRB_2_ERROR_GET(trb_2)); 1206 #endif 1207 if ((trb_0 & 0x3) == 0x3) { 1208 xfer->actlen = XHCI_TRB_2_REM_GET(trb_2); 1209 } 1210 } 1211 1212 if (XHCI_TRB_2_ERROR_GET(trb_2) == 1213 XHCI_TRB_ERROR_SUCCESS) { 1214 xfer->actlen = xfer->length - XHCI_TRB_2_REM_GET(trb_2); 1215 err = USBD_NORMAL_COMPLETION; 1216 } else if (XHCI_TRB_2_ERROR_GET(trb_2) == 1217 XHCI_TRB_ERROR_SHORT_PKT) { 1218 xfer->actlen = xfer->length - XHCI_TRB_2_REM_GET(trb_2); 1219 err = USBD_NORMAL_COMPLETION; 1220 } else if (XHCI_TRB_2_ERROR_GET(trb_2) == 1221 XHCI_TRB_ERROR_STALL) { 1222 err = USBD_STALLED; 1223 xr->is_halted = true; 1224 } else { 1225 err = USBD_IOERROR; 1226 } 1227 xfer->status = err; 1228 1229 //mutex_enter(&sc->sc_lock); /* XXX ??? */ 1230 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1231 if ((trb_0 & 0x3) == 0x0) { 1232 usb_transfer_complete(xfer); 1233 } 1234 } else { 1235 usb_transfer_complete(xfer); 1236 } 1237 //mutex_exit(&sc->sc_lock); /* XXX ??? */ 1238 1239 } 1240 break; 1241 case XHCI_TRB_EVENT_CMD_COMPLETE: 1242 if (trb_0 == sc->sc_command_addr) { 1243 sc->sc_result_trb.trb_0 = trb_0; 1244 sc->sc_result_trb.trb_2 = trb_2; 1245 sc->sc_result_trb.trb_3 = trb_3; 1246 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1247 XHCI_TRB_ERROR_SUCCESS) { 1248 device_printf(sc->sc_dev, "command completion " 1249 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1250 "0x%08"PRIx32"\n", trb_0, trb_2, trb_3); 1251 } 1252 cv_signal(&sc->sc_command_cv); 1253 } else { 1254 device_printf(sc->sc_dev, "event: %p 0x%016"PRIx64" " 1255 "0x%08"PRIx32" 0x%08"PRIx32"\n", trb, trb_0, 1256 trb_2, trb_3); 1257 } 1258 break; 1259 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1260 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1261 break; 1262 default: 1263 break; 1264 } 1265 } 1266 1267 static void 1268 xhci_softintr(void *v) 1269 { 1270 struct usbd_bus * const bus = v; 1271 struct xhci_softc * const sc = bus->hci_private; 1272 struct xhci_ring * const er = &sc->sc_er; 1273 struct xhci_trb *trb; 1274 int i, j, k; 1275 1276 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1277 1278 i = er->xr_ep; 1279 j = er->xr_cs; 1280 1281 while (1) { 1282 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 1283 BUS_DMASYNC_POSTREAD); 1284 trb = &er->xr_trb[i]; 1285 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1286 1287 if (j != k) 1288 break; 1289 1290 xhci_handle_event(sc, trb); 1291 1292 i++; 1293 if (i == XHCI_EVENT_RING_TRBS) { 1294 i = 0; 1295 j ^= 1; 1296 } 1297 } 1298 1299 er->xr_ep = i; 1300 er->xr_cs = j; 1301 1302 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 1303 XHCI_ERDP_LO_BUSY); 1304 1305 DPRINTF(("%s: %s ends\n", __func__, device_xname(sc->sc_dev))); 1306 1307 return; 1308 } 1309 1310 static void 1311 xhci_poll(struct usbd_bus *bus) 1312 { 1313 struct xhci_softc * const sc = bus->hci_private; 1314 1315 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1316 1317 xhci_intr1(sc); 1318 1319 return; 1320 } 1321 1322 static usbd_status 1323 xhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, uint32_t size) 1324 { 1325 struct xhci_softc * const sc = bus->hci_private; 1326 usbd_status err; 1327 1328 DPRINTF(("%s\n", __func__)); 1329 1330 err = usb_allocmem_flags(&sc->sc_bus, size, 0, dma, 0); 1331 #if 0 1332 if (err == USBD_NOMEM) 1333 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1334 #endif 1335 #ifdef XHCI_DEBUG 1336 if (err) 1337 device_printf(sc->sc_dev, "xhci_allocm: usb_allocmem()=%d\n", 1338 err); 1339 #endif 1340 1341 return err; 1342 } 1343 1344 static void 1345 xhci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1346 { 1347 struct xhci_softc * const sc = bus->hci_private; 1348 1349 // DPRINTF(("%s\n", __func__)); 1350 1351 #if 0 1352 if (dma->block->flags & USB_DMA_RESERVE) { 1353 usb_reserve_freem(&sc->sc_dma_reserve, dma); 1354 return; 1355 } 1356 #endif 1357 usb_freemem(&sc->sc_bus, dma); 1358 } 1359 1360 static usbd_xfer_handle 1361 xhci_allocx(struct usbd_bus *bus) 1362 { 1363 struct xhci_softc * const sc = bus->hci_private; 1364 usbd_xfer_handle xfer; 1365 1366 // DPRINTF(("%s\n", __func__)); 1367 1368 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1369 if (xfer != NULL) { 1370 memset(xfer, 0, sizeof(struct xhci_xfer)); 1371 #ifdef DIAGNOSTIC 1372 xfer->busy_free = XFER_BUSY; 1373 #endif 1374 } 1375 1376 return xfer; 1377 } 1378 1379 static void 1380 xhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1381 { 1382 struct xhci_softc * const sc = bus->hci_private; 1383 1384 // DPRINTF(("%s\n", __func__)); 1385 1386 #ifdef DIAGNOSTIC 1387 if (xfer->busy_free != XFER_BUSY) { 1388 device_printf(sc->sc_dev, "xhci_freex: xfer=%p " 1389 "not busy, 0x%08x\n", xfer, xfer->busy_free); 1390 } 1391 xfer->busy_free = XFER_FREE; 1392 #endif 1393 pool_cache_put(sc->sc_xferpool, xfer); 1394 } 1395 1396 static void 1397 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1398 { 1399 struct xhci_softc * const sc = bus->hci_private; 1400 1401 *lock = &sc->sc_lock; 1402 } 1403 1404 extern u_int32_t usb_cookie_no; 1405 1406 static usbd_status 1407 xhci_new_device(device_t parent, usbd_bus_handle bus, int depth, 1408 int speed, int port, struct usbd_port *up) 1409 { 1410 struct xhci_softc * const sc = bus->hci_private; 1411 usbd_device_handle dev; 1412 usbd_status err; 1413 usb_device_descriptor_t *dd; 1414 struct usbd_device *hub; 1415 struct usbd_device *adev; 1416 int rhport = 0; 1417 struct xhci_slot *xs; 1418 uint32_t *cp; 1419 uint8_t slot; 1420 uint8_t addr; 1421 1422 dev = malloc(sizeof *dev, M_USB, M_NOWAIT|M_ZERO); 1423 if (dev == NULL) 1424 return USBD_NOMEM; 1425 1426 dev->bus = bus; 1427 1428 /* Set up default endpoint handle. */ 1429 dev->def_ep.edesc = &dev->def_ep_desc; 1430 1431 /* Set up default endpoint descriptor. */ 1432 dev->def_ep_desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 1433 dev->def_ep_desc.bDescriptorType = UDESC_ENDPOINT; 1434 dev->def_ep_desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 1435 dev->def_ep_desc.bmAttributes = UE_CONTROL; 1436 /* XXX */ 1437 USETW(dev->def_ep_desc.wMaxPacketSize, 64); 1438 dev->def_ep_desc.bInterval = 0; 1439 1440 /* doesn't matter, just don't let it uninitialized */ 1441 dev->def_ep.datatoggle = 0; 1442 1443 device_printf(sc->sc_dev, "%s up %p portno %d\n", __func__, up, 1444 up->portno); 1445 1446 dev->quirks = &usbd_no_quirk; 1447 dev->address = 0; 1448 dev->ddesc.bMaxPacketSize = 0; 1449 dev->depth = depth; 1450 dev->powersrc = up; 1451 dev->myhub = up->parent; 1452 1453 up->device = dev; 1454 1455 /* Locate root hub port */ 1456 for (adev = dev, hub = dev; 1457 hub != NULL; 1458 adev = hub, hub = hub->myhub) { 1459 device_printf(sc->sc_dev, "%s hub %p\n", __func__, hub); 1460 } 1461 device_printf(sc->sc_dev, "%s hub %p\n", __func__, hub); 1462 1463 if (hub != NULL) { 1464 for (int p = 0; p < hub->hub->hubdesc.bNbrPorts; p++) { 1465 if (hub->hub->ports[p].device == adev) { 1466 rhport = p; 1467 } 1468 } 1469 } else { 1470 rhport = port; 1471 } 1472 if (speed == USB_SPEED_SUPER) { 1473 rhport += sc->sc_ss_port_start - 1; 1474 } else { 1475 rhport += sc->sc_hs_port_start - 1; 1476 } 1477 device_printf(sc->sc_dev, "%s rhport %d\n", __func__, rhport); 1478 1479 dev->speed = speed; 1480 dev->langid = USBD_NOLANG; 1481 dev->cookie.cookie = ++usb_cookie_no; 1482 1483 /* Establish the default pipe. */ 1484 err = usbd_setup_pipe(dev, 0, &dev->def_ep, USBD_DEFAULT_INTERVAL, 1485 &dev->default_pipe); 1486 if (err) { 1487 usbd_remove_device(dev, up); 1488 return (err); 1489 } 1490 1491 dd = &dev->ddesc; 1492 1493 if ((depth == 0) && (port == 0)) { 1494 KASSERT(bus->devices[dev->address] == NULL); 1495 bus->devices[dev->address] = dev; 1496 err = usbd_get_initial_ddesc(dev, dd); 1497 if (err) 1498 return err; 1499 err = usbd_reload_device_desc(dev); 1500 if (err) 1501 return err; 1502 } else { 1503 err = xhci_enable_slot(sc, &slot); 1504 if (err) 1505 return err; 1506 err = xhci_init_slot(sc, slot, depth, speed, port, rhport); 1507 if (err) 1508 return err; 1509 xs = &sc->sc_slots[slot]; 1510 dev->hci_private = xs; 1511 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 1512 //hexdump("slot context", cp, sc->sc_ctxsz); 1513 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 1514 device_printf(sc->sc_dev, "%s device address %u\n", 1515 __func__, addr); 1516 /* XXX ensure we know when the hardware does something 1517 we can't yet cope with */ 1518 KASSERT(addr >= 1 && addr <= 127); 1519 dev->address = addr; 1520 /* XXX dev->address not necessarily unique on bus */ 1521 KASSERT(bus->devices[dev->address] == NULL); 1522 bus->devices[dev->address] = dev; 1523 1524 err = usbd_get_initial_ddesc(dev, dd); 1525 if (err) 1526 return err; 1527 /* 4.8.2.1 */ 1528 if (speed == USB_SPEED_SUPER) 1529 USETW(dev->def_ep_desc.wMaxPacketSize, 1530 (1 << dd->bMaxPacketSize)); 1531 else 1532 USETW(dev->def_ep_desc.wMaxPacketSize, 1533 dd->bMaxPacketSize); 1534 device_printf(sc->sc_dev, "%s bMaxPacketSize %u\n", __func__, 1535 dd->bMaxPacketSize); 1536 xhci_update_ep0_mps(sc, xs, 1537 UGETW(dev->def_ep_desc.wMaxPacketSize)); 1538 err = usbd_reload_device_desc(dev); 1539 if (err) 1540 return err; 1541 1542 usbd_kill_pipe(dev->default_pipe); 1543 err = usbd_setup_pipe(dev, 0, &dev->def_ep, 1544 USBD_DEFAULT_INTERVAL, &dev->default_pipe); 1545 } 1546 1547 DPRINTF(("usbd_new_device: adding unit addr=%d, rev=%02x, class=%d, " 1548 "subclass=%d, protocol=%d, maxpacket=%d, len=%d, noconf=%d, " 1549 "speed=%d\n", dev->address,UGETW(dd->bcdUSB), 1550 dd->bDeviceClass, dd->bDeviceSubClass, dd->bDeviceProtocol, 1551 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 1552 dev->speed)); 1553 1554 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 1555 1556 if ((depth == 0) && (port == 0)) { 1557 usbd_attach_roothub(parent, dev); 1558 device_printf(sc->sc_dev, "root_hub %p\n", bus->root_hub); 1559 return USBD_NORMAL_COMPLETION; 1560 } 1561 1562 1563 err = usbd_probe_and_attach(parent, dev, port, dev->address); 1564 if (err) { 1565 usbd_remove_device(dev, up); 1566 return (err); 1567 } 1568 1569 return USBD_NORMAL_COMPLETION; 1570 } 1571 1572 static usbd_status 1573 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 1574 size_t ntrb, size_t align) 1575 { 1576 usbd_status err; 1577 size_t size = ntrb * XHCI_TRB_SIZE; 1578 1579 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 1580 if (err) 1581 return err; 1582 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1583 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 1584 xr->xr_trb = xhci_ring_trbv(xr, 0); 1585 xr->xr_ntrb = ntrb; 1586 xr->xr_ep = 0; 1587 xr->xr_cs = 1; 1588 memset(xr->xr_trb, 0, size); 1589 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 1590 xr->is_halted = false; 1591 1592 return USBD_NORMAL_COMPLETION; 1593 } 1594 1595 static void 1596 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 1597 { 1598 usb_freemem(&sc->sc_bus, &xr->xr_dma); 1599 mutex_destroy(&xr->xr_lock); 1600 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 1601 } 1602 1603 static void 1604 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 1605 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 1606 { 1607 size_t i; 1608 u_int ri; 1609 u_int cs; 1610 uint64_t parameter; 1611 uint32_t status; 1612 uint32_t control; 1613 1614 for (i = 0; i < ntrbs; i++) { 1615 #if 0 1616 device_printf(sc->sc_dev, "%s %p %p %zu " 1617 "%016"PRIx64" %08"PRIx32" %08"PRIx32"\n", __func__, xr, 1618 trbs, i, trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3); 1619 #endif 1620 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 1621 XHCI_TRB_TYPE_LINK); 1622 } 1623 1624 #if 0 1625 device_printf(sc->sc_dev, "%s %p xr_ep 0x%x xr_cs %u\n", __func__, 1626 xr, xr->xr_ep, xr->xr_cs); 1627 #endif 1628 1629 ri = xr->xr_ep; 1630 cs = xr->xr_cs; 1631 1632 /* 1633 * Although the xhci hardware can do scatter/gather dma from 1634 * arbitrary sized buffers, there is a non-obvious restriction 1635 * that a LINK trb is only allowed at the end of a burst of 1636 * transfers - which might be 16kB. 1637 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 1638 * The simple solution is not to allow a LINK trb in the middle 1639 * of anything - as here. 1640 * XXX: (dsl) There are xhci controllers out there (eg some made by 1641 * ASMedia) that seem to lock up if they process a LINK trb but 1642 * cannot process the linked-to trb yet. 1643 * The code should write the 'cycle' bit on the link trb AFTER 1644 * adding the other trb. 1645 */ 1646 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 1647 parameter = xhci_ring_trbp(xr, 0); 1648 status = 0; 1649 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1650 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 1651 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 1652 htole32(status), htole32(control)); 1653 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1654 BUS_DMASYNC_PREWRITE); 1655 xr->xr_cookies[ri] = NULL; 1656 xr->xr_ep = 0; 1657 xr->xr_cs ^= 1; 1658 ri = xr->xr_ep; 1659 cs = xr->xr_cs; 1660 } 1661 1662 ri++; 1663 1664 /* Write any subsequent TRB first */ 1665 for (i = 1; i < ntrbs; i++) { 1666 parameter = trbs[i].trb_0; 1667 status = trbs[i].trb_2; 1668 control = trbs[i].trb_3; 1669 1670 if (cs) { 1671 control |= XHCI_TRB_3_CYCLE_BIT; 1672 } else { 1673 control &= ~XHCI_TRB_3_CYCLE_BIT; 1674 } 1675 1676 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 1677 htole32(status), htole32(control)); 1678 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1679 BUS_DMASYNC_PREWRITE); 1680 xr->xr_cookies[ri] = cookie; 1681 ri++; 1682 } 1683 1684 /* Write the first TRB last */ 1685 i = 0; 1686 { 1687 parameter = trbs[i].trb_0; 1688 status = trbs[i].trb_2; 1689 control = trbs[i].trb_3; 1690 1691 if (xr->xr_cs) { 1692 control |= XHCI_TRB_3_CYCLE_BIT; 1693 } else { 1694 control &= ~XHCI_TRB_3_CYCLE_BIT; 1695 } 1696 1697 xhci_trb_put(&xr->xr_trb[xr->xr_ep], htole64(parameter), 1698 htole32(status), htole32(control)); 1699 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1700 BUS_DMASYNC_PREWRITE); 1701 xr->xr_cookies[xr->xr_ep] = cookie; 1702 } 1703 1704 xr->xr_ep = ri; 1705 xr->xr_cs = cs; 1706 1707 #if 0 1708 device_printf(sc->sc_dev, "%s %p xr_ep 0x%x xr_cs %u\n", __func__, 1709 xr, xr->xr_ep, xr->xr_cs); 1710 #endif 1711 } 1712 1713 static usbd_status 1714 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 1715 int timeout) 1716 { 1717 struct xhci_ring * const cr = &sc->sc_cr; 1718 usbd_status err; 1719 1720 device_printf(sc->sc_dev, "%s input: " 1721 "0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"\n", __func__, 1722 trb->trb_0, trb->trb_2, trb->trb_3); 1723 1724 mutex_enter(&sc->sc_lock); 1725 1726 KASSERT(sc->sc_command_addr == 0); 1727 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 1728 1729 mutex_enter(&cr->xr_lock); 1730 xhci_ring_put(sc, cr, NULL, trb, 1); 1731 mutex_exit(&cr->xr_lock); 1732 1733 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 1734 1735 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 1736 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 1737 err = USBD_TIMEOUT; 1738 goto timedout; 1739 } 1740 1741 trb->trb_0 = sc->sc_result_trb.trb_0; 1742 trb->trb_2 = sc->sc_result_trb.trb_2; 1743 trb->trb_3 = sc->sc_result_trb.trb_3; 1744 1745 device_printf(sc->sc_dev, "%s output: " 1746 "0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"\n", __func__, 1747 trb->trb_0, trb->trb_2, trb->trb_3); 1748 1749 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 1750 case XHCI_TRB_ERROR_SUCCESS: 1751 err = USBD_NORMAL_COMPLETION; 1752 break; 1753 default: 1754 case 192 ... 223: 1755 err = USBD_IOERROR; 1756 break; 1757 case 224 ... 255: 1758 err = USBD_NORMAL_COMPLETION; 1759 break; 1760 } 1761 1762 timedout: 1763 sc->sc_command_addr = 0; 1764 mutex_exit(&sc->sc_lock); 1765 return err; 1766 } 1767 1768 static usbd_status 1769 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 1770 { 1771 struct xhci_trb trb; 1772 usbd_status err; 1773 1774 trb.trb_0 = 0; 1775 trb.trb_2 = 0; 1776 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 1777 1778 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1779 if (err != USBD_NORMAL_COMPLETION) { 1780 return err; 1781 } 1782 1783 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 1784 1785 return err; 1786 } 1787 1788 static usbd_status 1789 xhci_address_device(struct xhci_softc * const sc, 1790 uint64_t icp, uint8_t slot_id, bool bsr) 1791 { 1792 struct xhci_trb trb; 1793 usbd_status err; 1794 1795 trb.trb_0 = icp; 1796 trb.trb_2 = 0; 1797 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 1798 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1799 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 1800 1801 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1802 return err; 1803 } 1804 1805 static usbd_status 1806 xhci_update_ep0_mps(struct xhci_softc * const sc, 1807 struct xhci_slot * const xs, u_int mps) 1808 { 1809 struct xhci_trb trb; 1810 usbd_status err; 1811 uint32_t * cp; 1812 1813 device_printf(sc->sc_dev, "%s\n", __func__); 1814 1815 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1816 cp[0] = htole32(0); 1817 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 1818 1819 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 1820 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1821 1822 /* sync input contexts before they are read from memory */ 1823 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1824 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 1825 sc->sc_ctxsz * 4); 1826 1827 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1828 trb.trb_2 = 0; 1829 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1830 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 1831 1832 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1833 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 1834 return err; 1835 } 1836 1837 static void 1838 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 1839 { 1840 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 1841 1842 device_printf(sc->sc_dev, "dcbaa %p dc %016"PRIx64" slot %d\n", 1843 &dcbaa[si], dcba, si); 1844 1845 dcbaa[si] = htole64(dcba); 1846 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 1847 BUS_DMASYNC_PREWRITE); 1848 } 1849 1850 static usbd_status 1851 xhci_init_slot(struct xhci_softc * const sc, uint32_t slot, int depth, 1852 int speed, int port, int rhport) 1853 { 1854 struct xhci_slot *xs; 1855 usbd_status err; 1856 u_int dci; 1857 uint32_t *cp; 1858 uint32_t mps; 1859 uint32_t xspeed; 1860 1861 switch (speed) { 1862 case USB_SPEED_LOW: 1863 xspeed = 2; 1864 mps = USB_MAX_IPACKET; 1865 break; 1866 case USB_SPEED_FULL: 1867 xspeed = 1; 1868 mps = 64; 1869 break; 1870 case USB_SPEED_HIGH: 1871 xspeed = 3; 1872 mps = USB_2_MAX_CTRL_PACKET; 1873 break; 1874 case USB_SPEED_SUPER: 1875 xspeed = 4; 1876 mps = USB_3_MAX_CTRL_PACKET; 1877 break; 1878 default: 1879 device_printf(sc->sc_dev, "%s: impossible speed: %x", 1880 __func__, speed); 1881 return USBD_INVAL; 1882 } 1883 1884 xs = &sc->sc_slots[slot]; 1885 xs->xs_idx = slot; 1886 1887 /* allocate contexts */ 1888 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 1889 &xs->xs_dc_dma); 1890 if (err) 1891 return err; 1892 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 1893 1894 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 1895 &xs->xs_ic_dma); 1896 if (err) 1897 return err; 1898 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 1899 1900 for (dci = 0; dci < 32; dci++) { 1901 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 1902 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 1903 if (dci == XHCI_DCI_SLOT) 1904 continue; 1905 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 1906 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 1907 if (err) { 1908 device_printf(sc->sc_dev, "ring init failure\n"); 1909 return err; 1910 } 1911 } 1912 1913 /* set up initial input control context */ 1914 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1915 cp[0] = htole32(0); 1916 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 1917 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 1918 1919 /* set up input slot context */ 1920 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1921 cp[0] = htole32( 1922 XHCI_SCTX_0_CTX_NUM_SET(1) | 1923 XHCI_SCTX_0_SPEED_SET(xspeed) 1924 ); 1925 cp[1] = htole32( 1926 XHCI_SCTX_1_RH_PORT_SET(rhport) 1927 ); 1928 cp[2] = htole32( 1929 XHCI_SCTX_2_IRQ_TARGET_SET(0) 1930 ); 1931 cp[3] = htole32(0); 1932 1933 /* set up input EP0 context */ 1934 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 1935 cp[0] = htole32(0); 1936 cp[1] = htole32( 1937 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 1938 XHCI_EPCTX_1_EPTYPE_SET(4) | 1939 XHCI_EPCTX_1_CERR_SET(3) 1940 ); 1941 /* can't use xhci_ep_get_dci() yet? */ 1942 *(uint64_t *)(&cp[2]) = htole64( 1943 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 1944 XHCI_EPCTX_2_DCS_SET(1)); 1945 cp[4] = htole32( 1946 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 1947 ); 1948 1949 /* sync input contexts before they are read from memory */ 1950 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1951 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 1952 sc->sc_ctxsz * 3); 1953 1954 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 1955 1956 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 1957 false); 1958 1959 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1960 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 1961 sc->sc_ctxsz * 2); 1962 1963 return err; 1964 } 1965 1966 /* ----- */ 1967 1968 static void 1969 xhci_noop(usbd_pipe_handle pipe) 1970 { 1971 DPRINTF(("%s\n", __func__)); 1972 } 1973 1974 /* root hub descriptors */ 1975 1976 static const usb_device_descriptor_t xhci_devd = { 1977 USB_DEVICE_DESCRIPTOR_SIZE, 1978 UDESC_DEVICE, /* type */ 1979 {0x00, 0x02}, /* USB version */ 1980 UDCLASS_HUB, /* class */ 1981 UDSUBCLASS_HUB, /* subclass */ 1982 UDPROTO_HSHUBSTT, /* protocol */ 1983 64, /* max packet */ 1984 {0},{0},{0x00,0x01}, /* device id */ 1985 1,2,0, /* string indexes */ 1986 1 /* # of configurations */ 1987 }; 1988 1989 static const usb_device_qualifier_t xhci_odevd = { 1990 USB_DEVICE_DESCRIPTOR_SIZE, 1991 UDESC_DEVICE_QUALIFIER, /* type */ 1992 {0x00, 0x02}, /* USB version */ 1993 UDCLASS_HUB, /* class */ 1994 UDSUBCLASS_HUB, /* subclass */ 1995 UDPROTO_FSHUB, /* protocol */ 1996 64, /* max packet */ 1997 1, /* # of configurations */ 1998 0 1999 }; 2000 2001 static const usb_config_descriptor_t xhci_confd = { 2002 USB_CONFIG_DESCRIPTOR_SIZE, 2003 UDESC_CONFIG, 2004 {USB_CONFIG_DESCRIPTOR_SIZE + 2005 USB_INTERFACE_DESCRIPTOR_SIZE + 2006 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2007 1, 2008 1, 2009 0, 2010 UC_ATTR_MBO | UC_SELF_POWERED, 2011 0 /* max power */ 2012 }; 2013 2014 static const usb_interface_descriptor_t xhci_ifcd = { 2015 USB_INTERFACE_DESCRIPTOR_SIZE, 2016 UDESC_INTERFACE, 2017 0, 2018 0, 2019 1, 2020 UICLASS_HUB, 2021 UISUBCLASS_HUB, 2022 UIPROTO_HSHUBSTT, 2023 0 2024 }; 2025 2026 static const usb_endpoint_descriptor_t xhci_endpd = { 2027 USB_ENDPOINT_DESCRIPTOR_SIZE, 2028 UDESC_ENDPOINT, 2029 UE_DIR_IN | XHCI_INTR_ENDPT, 2030 UE_INTERRUPT, 2031 {8, 0}, /* max packet */ 2032 12 2033 }; 2034 2035 static const usb_hub_descriptor_t xhci_hubd = { 2036 USB_HUB_DESCRIPTOR_SIZE, 2037 UDESC_HUB, 2038 0, 2039 {0,0}, 2040 0, 2041 0, 2042 {""}, 2043 {""}, 2044 }; 2045 2046 /* root hub control */ 2047 2048 static usbd_status 2049 xhci_root_ctrl_transfer(usbd_xfer_handle xfer) 2050 { 2051 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2052 usbd_status err; 2053 2054 DPRINTF(("%s\n", __func__)); 2055 2056 /* Insert last in queue. */ 2057 mutex_enter(&sc->sc_lock); 2058 err = usb_insert_transfer(xfer); 2059 mutex_exit(&sc->sc_lock); 2060 if (err) 2061 return err; 2062 2063 /* Pipe isn't running, start first */ 2064 return (xhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2065 } 2066 2067 static usbd_status 2068 xhci_root_ctrl_start(usbd_xfer_handle xfer) 2069 { 2070 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2071 usb_port_status_t ps; 2072 usb_device_request_t *req; 2073 void *buf = NULL; 2074 usb_hub_descriptor_t hubd; 2075 usbd_status err; 2076 int len, value, index; 2077 int l, totlen = 0; 2078 int port, i; 2079 uint32_t v; 2080 2081 DPRINTF(("%s\n", __func__)); 2082 2083 if (sc->sc_dying) 2084 return USBD_IOERROR; 2085 2086 req = &xfer->request; 2087 2088 value = UGETW(req->wValue); 2089 index = UGETW(req->wIndex); 2090 len = UGETW(req->wLength); 2091 2092 if (len != 0) 2093 buf = KERNADDR(&xfer->dmabuf, 0); 2094 2095 DPRINTF(("root req: %02x %02x %04x %04x %04x\n", req->bmRequestType, 2096 req->bRequest, value, index, len)); 2097 2098 #define C(x,y) ((x) | ((y) << 8)) 2099 switch(C(req->bRequest, req->bmRequestType)) { 2100 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2101 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2102 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2103 /* 2104 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2105 * for the integrated root hub. 2106 */ 2107 break; 2108 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2109 if (len > 0) { 2110 *(uint8_t *)buf = sc->sc_conf; 2111 totlen = 1; 2112 } 2113 break; 2114 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2115 DPRINTFN(8,("xhci_root_ctrl_start: wValue=0x%04x\n", value)); 2116 if (len == 0) 2117 break; 2118 switch(value >> 8) { 2119 case UDESC_DEVICE: 2120 if ((value & 0xff) != 0) { 2121 err = USBD_IOERROR; 2122 goto ret; 2123 } 2124 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2125 memcpy(buf, &xhci_devd, min(l, sizeof(xhci_devd))); 2126 break; 2127 case UDESC_DEVICE_QUALIFIER: 2128 if ((value & 0xff) != 0) { 2129 } 2130 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2131 memcpy(buf, &xhci_odevd, min(l, sizeof(xhci_odevd))); 2132 break; 2133 case UDESC_OTHER_SPEED_CONFIGURATION: 2134 case UDESC_CONFIG: 2135 if ((value & 0xff) != 0) { 2136 err = USBD_IOERROR; 2137 goto ret; 2138 } 2139 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2140 memcpy(buf, &xhci_confd, min(l, sizeof(xhci_confd))); 2141 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2142 value >> 8; 2143 buf = (char *)buf + l; 2144 len -= l; 2145 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2146 totlen += l; 2147 memcpy(buf, &xhci_ifcd, min(l, sizeof(xhci_ifcd))); 2148 buf = (char *)buf + l; 2149 len -= l; 2150 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2151 totlen += l; 2152 memcpy(buf, &xhci_endpd, min(l, sizeof(xhci_endpd))); 2153 break; 2154 case UDESC_STRING: 2155 #define sd ((usb_string_descriptor_t *)buf) 2156 switch (value & 0xff) { 2157 case 0: /* Language table */ 2158 totlen = usb_makelangtbl(sd, len); 2159 break; 2160 case 1: /* Vendor */ 2161 totlen = usb_makestrdesc(sd, len, "NetBSD"); 2162 break; 2163 case 2: /* Product */ 2164 totlen = usb_makestrdesc(sd, len, 2165 "xHCI Root Hub"); 2166 break; 2167 } 2168 #undef sd 2169 break; 2170 default: 2171 err = USBD_IOERROR; 2172 goto ret; 2173 } 2174 break; 2175 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2176 if (len > 0) { 2177 *(uint8_t *)buf = 0; 2178 totlen = 1; 2179 } 2180 break; 2181 case C(UR_GET_STATUS, UT_READ_DEVICE): 2182 if (len > 1) { 2183 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2184 totlen = 2; 2185 } 2186 break; 2187 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2188 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2189 if (len > 1) { 2190 USETW(((usb_status_t *)buf)->wStatus, 0); 2191 totlen = 2; 2192 } 2193 break; 2194 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2195 if (value >= USB_MAX_DEVICES) { 2196 err = USBD_IOERROR; 2197 goto ret; 2198 } 2199 //sc->sc_addr = value; 2200 break; 2201 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2202 if (value != 0 && value != 1) { 2203 err = USBD_IOERROR; 2204 goto ret; 2205 } 2206 sc->sc_conf = value; 2207 break; 2208 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2209 break; 2210 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2211 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2212 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2213 err = USBD_IOERROR; 2214 goto ret; 2215 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2216 break; 2217 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2218 break; 2219 /* Hub requests */ 2220 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2221 break; 2222 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2223 DPRINTFN(4, ("xhci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2224 "port=%d feature=%d\n", 2225 index, value)); 2226 if (index < 1 || index > sc->sc_hs_port_count) { 2227 err = USBD_IOERROR; 2228 goto ret; 2229 } 2230 port = XHCI_PORTSC(sc->sc_hs_port_start - 1 + index); 2231 v = xhci_op_read_4(sc, port); 2232 DPRINTFN(4, ("xhci_root_ctrl_start: portsc=0x%08x\n", v)); 2233 v &= ~XHCI_PS_CLEAR; 2234 switch (value) { 2235 case UHF_PORT_ENABLE: 2236 xhci_op_write_4(sc, port, v &~ XHCI_PS_PED); 2237 break; 2238 case UHF_PORT_SUSPEND: 2239 err = USBD_IOERROR; 2240 goto ret; 2241 case UHF_PORT_POWER: 2242 break; 2243 case UHF_PORT_TEST: 2244 case UHF_PORT_INDICATOR: 2245 err = USBD_IOERROR; 2246 goto ret; 2247 case UHF_C_PORT_CONNECTION: 2248 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2249 break; 2250 case UHF_C_PORT_ENABLE: 2251 case UHF_C_PORT_SUSPEND: 2252 case UHF_C_PORT_OVER_CURRENT: 2253 err = USBD_IOERROR; 2254 goto ret; 2255 case UHF_C_PORT_RESET: 2256 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2257 break; 2258 default: 2259 err = USBD_IOERROR; 2260 goto ret; 2261 } 2262 2263 break; 2264 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2265 if (len == 0) 2266 break; 2267 if ((value & 0xff) != 0) { 2268 err = USBD_IOERROR; 2269 goto ret; 2270 } 2271 hubd = xhci_hubd; 2272 hubd.bNbrPorts = sc->sc_hs_port_count; 2273 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2274 hubd.bPwrOn2PwrGood = 200; 2275 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 2276 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2277 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2278 l = min(len, hubd.bDescLength); 2279 totlen = l; 2280 memcpy(buf, &hubd, l); 2281 break; 2282 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2283 if (len != 4) { 2284 err = USBD_IOERROR; 2285 goto ret; 2286 } 2287 memset(buf, 0, len); /* ? XXX */ 2288 totlen = len; 2289 break; 2290 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2291 DPRINTFN(8,("xhci_root_ctrl_start: get port status i=%d\n", 2292 index)); 2293 if (index < 1 || index > sc->sc_maxports) { 2294 err = USBD_IOERROR; 2295 goto ret; 2296 } 2297 if (len != 4) { 2298 err = USBD_IOERROR; 2299 goto ret; 2300 } 2301 v = xhci_op_read_4(sc, XHCI_PORTSC(sc->sc_hs_port_start - 1 + 2302 index)); 2303 DPRINTF(("%s READ_CLASS_OTHER GET_STATUS PORTSC %d (%d) %08x\n", 2304 __func__, index, sc->sc_hs_port_start - 1 + index, v)); 2305 switch (XHCI_PS_SPEED_GET(v)) { 2306 case 1: 2307 i = UPS_FULL_SPEED; 2308 break; 2309 case 2: 2310 i = UPS_LOW_SPEED; 2311 break; 2312 case 3: 2313 i = UPS_HIGH_SPEED; 2314 break; 2315 default: 2316 i = 0; 2317 break; 2318 } 2319 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2320 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2321 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2322 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 2323 if (v & XHCI_PS_PR) i |= UPS_RESET; 2324 if (v & XHCI_PS_PP) i |= UPS_PORT_POWER; 2325 USETW(ps.wPortStatus, i); 2326 i = 0; 2327 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2328 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2329 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2330 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2331 USETW(ps.wPortChange, i); 2332 l = min(len, sizeof ps); 2333 memcpy(buf, &ps, l); 2334 totlen = l; 2335 break; 2336 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2337 err = USBD_IOERROR; 2338 goto ret; 2339 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2340 break; 2341 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2342 if (index < 1 || index > sc->sc_hs_port_count) { 2343 err = USBD_IOERROR; 2344 goto ret; 2345 } 2346 port = XHCI_PORTSC(sc->sc_hs_port_start - 1 + index); 2347 v = xhci_op_read_4(sc, port); 2348 DPRINTFN(4, ("xhci_root_ctrl_start: portsc=0x%08x\n", v)); 2349 v &= ~XHCI_PS_CLEAR; 2350 switch (value) { 2351 case UHF_PORT_ENABLE: 2352 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 2353 break; 2354 case UHF_PORT_SUSPEND: 2355 /* XXX suspend */ 2356 break; 2357 case UHF_PORT_RESET: 2358 v &= ~ (XHCI_PS_PED | XHCI_PS_PR); 2359 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 2360 /* Wait for reset to complete. */ 2361 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2362 if (sc->sc_dying) { 2363 err = USBD_IOERROR; 2364 goto ret; 2365 } 2366 v = xhci_op_read_4(sc, port); 2367 if (v & XHCI_PS_PR) { 2368 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 2369 usb_delay_ms(&sc->sc_bus, 10); 2370 /* XXX */ 2371 } 2372 break; 2373 case UHF_PORT_POWER: 2374 /* XXX power control */ 2375 break; 2376 /* XXX more */ 2377 case UHF_C_PORT_RESET: 2378 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2379 break; 2380 default: 2381 err = USBD_IOERROR; 2382 goto ret; 2383 } 2384 break; 2385 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2386 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2387 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2388 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2389 break; 2390 default: 2391 err = USBD_IOERROR; 2392 goto ret; 2393 } 2394 xfer->actlen = totlen; 2395 err = USBD_NORMAL_COMPLETION; 2396 ret: 2397 xfer->status = err; 2398 mutex_enter(&sc->sc_lock); 2399 usb_transfer_complete(xfer); 2400 mutex_exit(&sc->sc_lock); 2401 return USBD_IN_PROGRESS; 2402 } 2403 2404 2405 static void 2406 xhci_root_ctrl_abort(usbd_xfer_handle xfer) 2407 { 2408 /* Nothing to do, all transfers are synchronous. */ 2409 } 2410 2411 2412 static void 2413 xhci_root_ctrl_close(usbd_pipe_handle pipe) 2414 { 2415 DPRINTF(("%s\n", __func__)); 2416 /* Nothing to do. */ 2417 } 2418 2419 static void 2420 xhci_root_ctrl_done(usbd_xfer_handle xfer) 2421 { 2422 xfer->hcpriv = NULL; 2423 } 2424 2425 /* root hub intrerrupt */ 2426 2427 static usbd_status 2428 xhci_root_intr_transfer(usbd_xfer_handle xfer) 2429 { 2430 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2431 usbd_status err; 2432 2433 /* Insert last in queue. */ 2434 mutex_enter(&sc->sc_lock); 2435 err = usb_insert_transfer(xfer); 2436 mutex_exit(&sc->sc_lock); 2437 if (err) 2438 return err; 2439 2440 /* Pipe isn't running, start first */ 2441 return (xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2442 } 2443 2444 static usbd_status 2445 xhci_root_intr_start(usbd_xfer_handle xfer) 2446 { 2447 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2448 2449 if (sc->sc_dying) 2450 return USBD_IOERROR; 2451 2452 mutex_enter(&sc->sc_lock); 2453 sc->sc_intrxfer = xfer; 2454 mutex_exit(&sc->sc_lock); 2455 2456 return USBD_IN_PROGRESS; 2457 } 2458 2459 static void 2460 xhci_root_intr_abort(usbd_xfer_handle xfer) 2461 { 2462 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2463 2464 KASSERT(mutex_owned(&sc->sc_lock)); 2465 KASSERT(xfer->pipe->intrxfer == xfer); 2466 2467 DPRINTF(("%s: remove\n", __func__)); 2468 2469 sc->sc_intrxfer = NULL; 2470 2471 xfer->status = USBD_CANCELLED; 2472 usb_transfer_complete(xfer); 2473 } 2474 2475 static void 2476 xhci_root_intr_close(usbd_pipe_handle pipe) 2477 { 2478 struct xhci_softc * const sc = pipe->device->bus->hci_private; 2479 2480 KASSERT(mutex_owned(&sc->sc_lock)); 2481 2482 DPRINTF(("%s\n", __func__)); 2483 2484 sc->sc_intrxfer = NULL; 2485 } 2486 2487 static void 2488 xhci_root_intr_done(usbd_xfer_handle xfer) 2489 { 2490 xfer->hcpriv = NULL; 2491 } 2492 2493 /* -------------- */ 2494 /* device control */ 2495 2496 static usbd_status 2497 xhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2498 { 2499 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2500 usbd_status err; 2501 2502 /* Insert last in queue. */ 2503 mutex_enter(&sc->sc_lock); 2504 err = usb_insert_transfer(xfer); 2505 mutex_exit(&sc->sc_lock); 2506 if (err) 2507 return (err); 2508 2509 /* Pipe isn't running, start first */ 2510 return (xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2511 } 2512 2513 static usbd_status 2514 xhci_device_ctrl_start(usbd_xfer_handle xfer) 2515 { 2516 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2517 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2518 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2519 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2520 struct xhci_xfer * const xx = (void *)xfer; 2521 usb_device_request_t * const req = &xfer->request; 2522 const bool isread = UT_GET_DIR(req->bmRequestType) == UT_READ; 2523 const uint32_t len = UGETW(req->wLength); 2524 usb_dma_t * const dma = &xfer->dmabuf; 2525 uint64_t parameter; 2526 uint32_t status; 2527 uint32_t control; 2528 u_int i; 2529 2530 DPRINTF(("%s\n", __func__)); 2531 DPRINTF(("req: %02x %02x %04x %04x %04x\n", req->bmRequestType, 2532 req->bRequest, UGETW(req->wValue), UGETW(req->wIndex), 2533 UGETW(req->wLength))); 2534 2535 /* XXX */ 2536 if (tr->is_halted) { 2537 xhci_reset_endpoint(xfer->pipe); 2538 tr->is_halted = false; 2539 xhci_set_dequeue(xfer->pipe); 2540 } 2541 2542 /* we rely on the bottom bits for extra info */ 2543 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 2544 2545 KASSERT((xfer->rqflags & URQ_REQUEST) != 0); 2546 2547 i = 0; 2548 2549 /* setup phase */ 2550 memcpy(¶meter, req, sizeof(*req)); 2551 parameter = le64toh(parameter); 2552 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 2553 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 2554 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 2555 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 2556 XHCI_TRB_3_IDT_BIT; 2557 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2558 2559 if (len == 0) 2560 goto no_data; 2561 2562 /* data phase */ 2563 parameter = DMAADDR(dma, 0); 2564 KASSERT(len <= 0x10000); 2565 status = XHCI_TRB_2_IRQ_SET(0) | 2566 XHCI_TRB_2_TDSZ_SET(1) | 2567 XHCI_TRB_2_BYTES_SET(len); 2568 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 2569 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 2570 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 2571 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2572 2573 parameter = (uintptr_t)xfer | 0x3; 2574 status = XHCI_TRB_2_IRQ_SET(0); 2575 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 2576 XHCI_TRB_3_IOC_BIT; 2577 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2578 2579 no_data: 2580 parameter = 0; 2581 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_TDSZ_SET(1); 2582 /* the status stage has inverted direction */ 2583 control = (isread ? 0 : XHCI_TRB_3_DIR_IN) | 2584 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 2585 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 2586 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2587 2588 parameter = (uintptr_t)xfer | 0x0; 2589 status = XHCI_TRB_2_IRQ_SET(0); 2590 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 2591 XHCI_TRB_3_IOC_BIT; 2592 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2593 2594 mutex_enter(&tr->xr_lock); 2595 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2596 mutex_exit(&tr->xr_lock); 2597 2598 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2599 2600 if (xfer->timeout && !sc->sc_bus.use_polling) { 2601 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2602 xhci_timeout, xfer); 2603 } 2604 2605 if (sc->sc_bus.use_polling) { 2606 device_printf(sc->sc_dev, "%s polling\n", __func__); 2607 //xhci_waitintr(sc, xfer); 2608 } 2609 2610 return USBD_IN_PROGRESS; 2611 } 2612 2613 static void 2614 xhci_device_ctrl_done(usbd_xfer_handle xfer) 2615 { 2616 DPRINTF(("%s\n", __func__)); 2617 2618 callout_stop(&xfer->timeout_handle); /* XXX wrong place */ 2619 2620 } 2621 2622 static void 2623 xhci_device_ctrl_abort(usbd_xfer_handle xfer) 2624 { 2625 DPRINTF(("%s\n", __func__)); 2626 } 2627 2628 static void 2629 xhci_device_ctrl_close(usbd_pipe_handle pipe) 2630 { 2631 DPRINTF(("%s\n", __func__)); 2632 } 2633 2634 /* ----------------- */ 2635 /* device isochronus */ 2636 2637 /* ----------- */ 2638 /* device bulk */ 2639 2640 static usbd_status 2641 xhci_device_bulk_transfer(usbd_xfer_handle xfer) 2642 { 2643 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2644 usbd_status err; 2645 2646 /* Insert last in queue. */ 2647 mutex_enter(&sc->sc_lock); 2648 err = usb_insert_transfer(xfer); 2649 mutex_exit(&sc->sc_lock); 2650 if (err) 2651 return err; 2652 2653 /* 2654 * Pipe isn't running (otherwise err would be USBD_INPROG), 2655 * so start it first. 2656 */ 2657 return (xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2658 } 2659 2660 static usbd_status 2661 xhci_device_bulk_start(usbd_xfer_handle xfer) 2662 { 2663 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2664 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2665 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2666 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2667 struct xhci_xfer * const xx = (void *)xfer; 2668 const uint32_t len = xfer->length; 2669 usb_dma_t * const dma = &xfer->dmabuf; 2670 uint64_t parameter; 2671 uint32_t status; 2672 uint32_t control; 2673 u_int i = 0; 2674 2675 #if 0 2676 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2677 xs->xs_idx, dci); 2678 #endif 2679 2680 if (sc->sc_dying) 2681 return USBD_IOERROR; 2682 2683 KASSERT((xfer->rqflags & URQ_REQUEST) == 0); 2684 2685 parameter = DMAADDR(dma, 0); 2686 /* 2687 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 2688 * If the user supplied buffer crosses such a boundary then 2 2689 * (or more) TRB should be used. 2690 * If multiple TRB are used the td_size field must be set correctly. 2691 * For v1.0 devices (like ivy bridge) this is the number of usb data 2692 * blocks needed to complete the transfer. 2693 * Setting it to 1 in the last TRB causes an extra zero-length 2694 * data block be sent. 2695 * The earlier documentation differs, I don't know how it behaves. 2696 */ 2697 KASSERT(len <= 0x10000); 2698 status = XHCI_TRB_2_IRQ_SET(0) | 2699 XHCI_TRB_2_TDSZ_SET(1) | 2700 XHCI_TRB_2_BYTES_SET(len); 2701 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 2702 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 2703 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2704 2705 mutex_enter(&tr->xr_lock); 2706 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2707 mutex_exit(&tr->xr_lock); 2708 2709 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2710 2711 if (sc->sc_bus.use_polling) { 2712 device_printf(sc->sc_dev, "%s polling\n", __func__); 2713 //xhci_waitintr(sc, xfer); 2714 } 2715 2716 return USBD_IN_PROGRESS; 2717 } 2718 2719 static void 2720 xhci_device_bulk_done(usbd_xfer_handle xfer) 2721 { 2722 //struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2723 //struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2724 //const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2725 const u_int endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 2726 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2727 2728 DPRINTF(("%s\n", __func__)); 2729 2730 #if 0 2731 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2732 xs->xs_idx, dci); 2733 #endif 2734 2735 callout_stop(&xfer->timeout_handle); /* XXX wrong place */ 2736 2737 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 2738 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2739 2740 2741 } 2742 2743 static void 2744 xhci_device_bulk_abort(usbd_xfer_handle xfer) 2745 { 2746 DPRINTF(("%s\n", __func__)); 2747 } 2748 2749 static void 2750 xhci_device_bulk_close(usbd_pipe_handle pipe) 2751 { 2752 DPRINTF(("%s\n", __func__)); 2753 } 2754 2755 /* --------------- */ 2756 /* device intrrupt */ 2757 2758 static usbd_status 2759 xhci_device_intr_transfer(usbd_xfer_handle xfer) 2760 { 2761 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2762 usbd_status err; 2763 2764 /* Insert last in queue. */ 2765 mutex_enter(&sc->sc_lock); 2766 err = usb_insert_transfer(xfer); 2767 mutex_exit(&sc->sc_lock); 2768 if (err) 2769 return err; 2770 2771 /* 2772 * Pipe isn't running (otherwise err would be USBD_INPROG), 2773 * so start it first. 2774 */ 2775 return (xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2776 } 2777 2778 static usbd_status 2779 xhci_device_intr_start(usbd_xfer_handle xfer) 2780 { 2781 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2782 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2783 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2784 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2785 struct xhci_xfer * const xx = (void *)xfer; 2786 const uint32_t len = xfer->length; 2787 usb_dma_t * const dma = &xfer->dmabuf; 2788 uint64_t parameter; 2789 uint32_t status; 2790 uint32_t control; 2791 u_int i = 0; 2792 2793 #if 0 2794 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2795 xs->xs_idx, dci); 2796 #endif 2797 2798 if (sc->sc_dying) 2799 return USBD_IOERROR; 2800 2801 KASSERT((xfer->rqflags & URQ_REQUEST) == 0); 2802 2803 parameter = DMAADDR(dma, 0); 2804 KASSERT(len <= 0x10000); 2805 status = XHCI_TRB_2_IRQ_SET(0) | 2806 XHCI_TRB_2_TDSZ_SET(1) | 2807 XHCI_TRB_2_BYTES_SET(len); 2808 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 2809 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 2810 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2811 2812 mutex_enter(&tr->xr_lock); 2813 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2814 mutex_exit(&tr->xr_lock); 2815 2816 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2817 2818 if (sc->sc_bus.use_polling) { 2819 #ifdef XHCI_DEBUG 2820 device_printf(sc->sc_dev, "%s polling\n", __func__); 2821 #endif 2822 //xhci_waitintr(sc, xfer); 2823 } 2824 2825 return USBD_IN_PROGRESS; 2826 } 2827 2828 static void 2829 xhci_device_intr_done(usbd_xfer_handle xfer) 2830 { 2831 struct xhci_softc * const sc __diagused = 2832 xfer->pipe->device->bus->hci_private; 2833 #ifdef XHCI_DEBUG 2834 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2835 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2836 #endif 2837 const u_int endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 2838 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2839 DPRINTF(("%s\n", __func__)); 2840 2841 #ifdef XHCI_DEBUG 2842 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2843 xs->xs_idx, dci); 2844 #endif 2845 2846 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 2847 2848 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 2849 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2850 2851 #if 0 2852 device_printf(sc->sc_dev, ""); 2853 for (size_t i = 0; i < xfer->length; i++) { 2854 printf(" %02x", ((uint8_t const *)xfer->buffer)[i]); 2855 } 2856 printf("\n"); 2857 #endif 2858 2859 if (xfer->pipe->repeat) { 2860 xfer->status = xhci_device_intr_start(xfer); 2861 } else { 2862 callout_stop(&xfer->timeout_handle); /* XXX */ 2863 } 2864 2865 } 2866 2867 static void 2868 xhci_device_intr_abort(usbd_xfer_handle xfer) 2869 { 2870 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2871 DPRINTF(("%s\n", __func__)); 2872 2873 KASSERT(mutex_owned(&sc->sc_lock)); 2874 device_printf(sc->sc_dev, "%s %p\n", __func__, xfer); 2875 KASSERT(xfer->pipe->intrxfer == xfer); 2876 xfer->status = USBD_CANCELLED; 2877 usb_transfer_complete(xfer); 2878 } 2879 2880 static void 2881 xhci_device_intr_close(usbd_pipe_handle pipe) 2882 { 2883 struct xhci_softc * const sc = pipe->device->bus->hci_private; 2884 DPRINTF(("%s\n", __func__)); 2885 device_printf(sc->sc_dev, "%s %p\n", __func__, pipe); 2886 xhci_unconfigure_endpoint(pipe); 2887 } 2888 2889 /* ------------ */ 2890 2891 static void 2892 xhci_timeout(void *addr) 2893 { 2894 struct xhci_xfer * const xx = addr; 2895 usbd_xfer_handle const xfer = &xx->xx_xfer; 2896 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2897 2898 if (sc->sc_dying) { 2899 return; 2900 } 2901 2902 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 2903 USB_TASKQ_MPSAFE); 2904 usb_add_task(xx->xx_xfer.pipe->device, &xx->xx_abort_task, 2905 USB_TASKQ_HC); 2906 } 2907 2908 static void 2909 xhci_timeout_task(void *addr) 2910 { 2911 usbd_xfer_handle const xfer = addr; 2912 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2913 2914 mutex_enter(&sc->sc_lock); 2915 #if 0 2916 xhci_abort_xfer(xfer, USBD_TIMEOUT); 2917 #else 2918 xfer->status = USBD_TIMEOUT; 2919 usb_transfer_complete(xfer); 2920 #endif 2921 mutex_exit(&sc->sc_lock); 2922 } 2923
Indexes created Mon Sep 22 10:09:38 GMT 2025