xhci.c revision 1.26.2.3
1 /* $NetBSD: xhci.c,v 1.26.2.3 2017/12/03 11:37:36 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.26.2.3 2017/12/03 11:37:36 jdolecek Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static void xhci_host_dequeue(struct xhci_ring * const); 146 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 147 148 static usbd_status xhci_do_command(struct xhci_softc * const, 149 struct xhci_trb * const, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 153 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 154 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 155 static usbd_status xhci_enable_slot(struct xhci_softc * const, 156 uint8_t * const); 157 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 158 static usbd_status xhci_address_device(struct xhci_softc * const, 159 uint64_t, uint8_t, bool); 160 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 161 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 162 struct xhci_slot * const, u_int); 163 static usbd_status xhci_ring_init(struct xhci_softc * const, 164 struct xhci_ring * const, size_t, size_t); 165 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 166 167 static void xhci_setup_ctx(struct usbd_pipe *); 168 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 169 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 170 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 171 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 172 173 static void xhci_noop(struct usbd_pipe *); 174 175 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 176 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 177 static void xhci_root_intr_abort(struct usbd_xfer *); 178 static void xhci_root_intr_close(struct usbd_pipe *); 179 static void xhci_root_intr_done(struct usbd_xfer *); 180 181 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 182 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 183 static void xhci_device_ctrl_abort(struct usbd_xfer *); 184 static void xhci_device_ctrl_close(struct usbd_pipe *); 185 static void xhci_device_ctrl_done(struct usbd_xfer *); 186 187 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 188 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 189 static void xhci_device_intr_abort(struct usbd_xfer *); 190 static void xhci_device_intr_close(struct usbd_pipe *); 191 static void xhci_device_intr_done(struct usbd_xfer *); 192 193 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 194 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 195 static void xhci_device_bulk_abort(struct usbd_xfer *); 196 static void xhci_device_bulk_close(struct usbd_pipe *); 197 static void xhci_device_bulk_done(struct usbd_xfer *); 198 199 static void xhci_timeout(void *); 200 static void xhci_timeout_task(void *); 201 202 static const struct usbd_bus_methods xhci_bus_methods = { 203 .ubm_open = xhci_open, 204 .ubm_softint = xhci_softintr, 205 .ubm_dopoll = xhci_poll, 206 .ubm_allocx = xhci_allocx, 207 .ubm_freex = xhci_freex, 208 .ubm_getlock = xhci_get_lock, 209 .ubm_newdev = xhci_new_device, 210 .ubm_rhctrl = xhci_roothub_ctrl, 211 }; 212 213 static const struct usbd_pipe_methods xhci_root_intr_methods = { 214 .upm_transfer = xhci_root_intr_transfer, 215 .upm_start = xhci_root_intr_start, 216 .upm_abort = xhci_root_intr_abort, 217 .upm_close = xhci_root_intr_close, 218 .upm_cleartoggle = xhci_noop, 219 .upm_done = xhci_root_intr_done, 220 }; 221 222 223 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 224 .upm_transfer = xhci_device_ctrl_transfer, 225 .upm_start = xhci_device_ctrl_start, 226 .upm_abort = xhci_device_ctrl_abort, 227 .upm_close = xhci_device_ctrl_close, 228 .upm_cleartoggle = xhci_noop, 229 .upm_done = xhci_device_ctrl_done, 230 }; 231 232 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 233 .upm_cleartoggle = xhci_noop, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 237 .upm_transfer = xhci_device_bulk_transfer, 238 .upm_start = xhci_device_bulk_start, 239 .upm_abort = xhci_device_bulk_abort, 240 .upm_close = xhci_device_bulk_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_bulk_done, 243 }; 244 245 static const struct usbd_pipe_methods xhci_device_intr_methods = { 246 .upm_transfer = xhci_device_intr_transfer, 247 .upm_start = xhci_device_intr_start, 248 .upm_abort = xhci_device_intr_abort, 249 .upm_close = xhci_device_intr_close, 250 .upm_cleartoggle = xhci_noop, 251 .upm_done = xhci_device_intr_done, 252 }; 253 254 static inline uint32_t 255 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 256 { 257 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 258 } 259 260 static inline uint32_t 261 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 262 { 263 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 264 } 265 266 static inline void 267 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 268 uint32_t value) 269 { 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 271 } 272 273 #if 0 /* unused */ 274 static inline void 275 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 276 uint32_t value) 277 { 278 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 279 } 280 #endif /* unused */ 281 282 static inline uint32_t 283 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 284 { 285 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 286 } 287 288 static inline uint32_t 289 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 290 { 291 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 292 } 293 294 static inline void 295 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 296 uint32_t value) 297 { 298 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 299 } 300 301 static inline uint64_t 302 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 303 { 304 uint64_t value; 305 306 if (sc->sc_ac64) { 307 #ifdef XHCI_USE_BUS_SPACE_8 308 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 309 #else 310 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 311 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 312 offset + 4) << 32; 313 #endif 314 } else { 315 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 316 } 317 318 return value; 319 } 320 321 static inline void 322 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 336 } 337 } 338 339 static inline uint32_t 340 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 341 { 342 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 343 } 344 345 static inline void 346 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 347 uint32_t value) 348 { 349 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 350 } 351 352 #if 0 /* unused */ 353 static inline uint64_t 354 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 355 { 356 uint64_t value; 357 358 if (sc->sc_ac64) { 359 #ifdef XHCI_USE_BUS_SPACE_8 360 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 361 #else 362 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 363 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 364 offset + 4) << 32; 365 #endif 366 } else { 367 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 368 } 369 370 return value; 371 } 372 #endif /* unused */ 373 374 static inline void 375 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 376 uint64_t value) 377 { 378 if (sc->sc_ac64) { 379 #ifdef XHCI_USE_BUS_SPACE_8 380 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 381 #else 382 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 383 (value >> 0) & 0xffffffff); 384 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 385 (value >> 32) & 0xffffffff); 386 #endif 387 } else { 388 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 389 } 390 } 391 392 #if 0 /* unused */ 393 static inline uint32_t 394 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 395 { 396 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 397 } 398 #endif /* unused */ 399 400 static inline void 401 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 402 uint32_t value) 403 { 404 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 405 } 406 407 /* --- */ 408 409 static inline uint8_t 410 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 411 { 412 u_int eptype = 0; 413 414 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 415 case UE_CONTROL: 416 eptype = 0x0; 417 break; 418 case UE_ISOCHRONOUS: 419 eptype = 0x1; 420 break; 421 case UE_BULK: 422 eptype = 0x2; 423 break; 424 case UE_INTERRUPT: 425 eptype = 0x3; 426 break; 427 } 428 429 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 430 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 431 return eptype | 0x4; 432 else 433 return eptype; 434 } 435 436 static u_int 437 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 438 { 439 /* xHCI 1.0 section 4.5.1 */ 440 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 441 u_int in = 0; 442 443 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 444 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 445 in = 1; 446 447 return epaddr * 2 + in; 448 } 449 450 static inline u_int 451 xhci_dci_to_ici(const u_int i) 452 { 453 return i + 1; 454 } 455 456 static inline void * 457 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 458 const u_int dci) 459 { 460 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 461 } 462 463 #if 0 /* unused */ 464 static inline bus_addr_t 465 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 466 const u_int dci) 467 { 468 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 469 } 470 #endif /* unused */ 471 472 static inline void * 473 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline bus_addr_t 480 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 481 const u_int ici) 482 { 483 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 484 } 485 486 static inline struct xhci_trb * 487 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 488 { 489 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 490 } 491 492 static inline bus_addr_t 493 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 494 { 495 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 496 } 497 498 static inline void 499 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 500 uint32_t control) 501 { 502 trb->trb_0 = htole64(parameter); 503 trb->trb_2 = htole32(status); 504 trb->trb_3 = htole32(control); 505 } 506 507 static int 508 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 509 { 510 /* base address of TRBs */ 511 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 512 513 /* trb_0 range sanity check */ 514 if (trb_0 == 0 || trb_0 < trbp || 515 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 516 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 517 return 1; 518 } 519 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 520 return 0; 521 } 522 523 static unsigned int 524 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 525 u_int dci) 526 { 527 uint32_t *cp; 528 529 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 530 cp = xhci_slot_get_dcv(sc, xs, dci); 531 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 532 } 533 534 static inline unsigned int 535 xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport) 536 { 537 const unsigned int port = ctlrport - 1; 538 const uint8_t bit = __BIT(port % NBBY); 539 540 return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit); 541 } 542 543 /* 544 * Return the roothub port for a controller port. Both are 1..n. 545 */ 546 static inline unsigned int 547 xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport) 548 { 549 550 return sc->sc_ctlrportmap[ctrlport - 1]; 551 } 552 553 /* 554 * Return the controller port for a bus roothub port. Both are 1..n. 555 */ 556 static inline unsigned int 557 xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn, 558 unsigned int rhport) 559 { 560 561 return sc->sc_rhportmap[bn][rhport - 1]; 562 } 563 564 /* --- */ 565 566 void 567 xhci_childdet(device_t self, device_t child) 568 { 569 struct xhci_softc * const sc = device_private(self); 570 571 KASSERT(sc->sc_child == child); 572 if (child == sc->sc_child) 573 sc->sc_child = NULL; 574 } 575 576 int 577 xhci_detach(struct xhci_softc *sc, int flags) 578 { 579 int rv = 0; 580 581 if (sc->sc_child2 != NULL) { 582 rv = config_detach(sc->sc_child2, flags); 583 if (rv != 0) 584 return rv; 585 } 586 587 if (sc->sc_child != NULL) { 588 rv = config_detach(sc->sc_child, flags); 589 if (rv != 0) 590 return rv; 591 } 592 593 /* XXX unconfigure/free slots */ 594 595 /* verify: */ 596 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 597 xhci_op_write_4(sc, XHCI_USBCMD, 0); 598 /* do we need to wait for stop? */ 599 600 xhci_op_write_8(sc, XHCI_CRCR, 0); 601 xhci_ring_free(sc, &sc->sc_cr); 602 cv_destroy(&sc->sc_command_cv); 603 cv_destroy(&sc->sc_cmdbusy_cv); 604 605 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 606 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 607 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 608 xhci_ring_free(sc, &sc->sc_er); 609 610 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 611 612 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 613 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 614 615 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 616 617 kmem_free(sc->sc_ctlrportbus, 618 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY)); 619 kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int)); 620 621 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 622 kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int)); 623 } 624 625 mutex_destroy(&sc->sc_lock); 626 mutex_destroy(&sc->sc_intr_lock); 627 628 pool_cache_destroy(sc->sc_xferpool); 629 630 return rv; 631 } 632 633 int 634 xhci_activate(device_t self, enum devact act) 635 { 636 struct xhci_softc * const sc = device_private(self); 637 638 switch (act) { 639 case DVACT_DEACTIVATE: 640 sc->sc_dying = true; 641 return 0; 642 default: 643 return EOPNOTSUPP; 644 } 645 } 646 647 bool 648 xhci_suspend(device_t dv, const pmf_qual_t *qual) 649 { 650 return false; 651 } 652 653 bool 654 xhci_resume(device_t dv, const pmf_qual_t *qual) 655 { 656 return false; 657 } 658 659 bool 660 xhci_shutdown(device_t self, int flags) 661 { 662 return false; 663 } 664 665 static int 666 xhci_hc_reset(struct xhci_softc * const sc) 667 { 668 uint32_t usbcmd, usbsts; 669 int i; 670 671 /* Check controller not ready */ 672 for (i = 0; i < XHCI_WAIT_CNR; i++) { 673 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 674 if ((usbsts & XHCI_STS_CNR) == 0) 675 break; 676 usb_delay_ms(&sc->sc_bus, 1); 677 } 678 if (i >= XHCI_WAIT_CNR) { 679 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 680 return EIO; 681 } 682 683 /* Halt controller */ 684 usbcmd = 0; 685 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 686 usb_delay_ms(&sc->sc_bus, 1); 687 688 /* Reset controller */ 689 usbcmd = XHCI_CMD_HCRST; 690 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 691 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 692 /* 693 * Wait 1ms first. Existing Intel xHCI requies 1ms delay to 694 * prevent system hang (Errata). 695 */ 696 usb_delay_ms(&sc->sc_bus, 1); 697 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 698 if ((usbcmd & XHCI_CMD_HCRST) == 0) 699 break; 700 } 701 if (i >= XHCI_WAIT_HCRST) { 702 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 703 return EIO; 704 } 705 706 /* Check controller not ready */ 707 for (i = 0; i < XHCI_WAIT_CNR; i++) { 708 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 709 if ((usbsts & XHCI_STS_CNR) == 0) 710 break; 711 usb_delay_ms(&sc->sc_bus, 1); 712 } 713 if (i >= XHCI_WAIT_CNR) { 714 aprint_error_dev(sc->sc_dev, 715 "controller not ready timeout after reset\n"); 716 return EIO; 717 } 718 719 return 0; 720 } 721 722 723 static void 724 hexdump(const char *msg, const void *base, size_t len) 725 { 726 #if 0 727 size_t cnt; 728 const uint32_t *p; 729 extern paddr_t vtophys(vaddr_t); 730 731 p = base; 732 cnt = 0; 733 734 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 735 (void *)vtophys((vaddr_t)base)); 736 737 while (cnt < len) { 738 if (cnt % 16 == 0) 739 printf("%p: ", p); 740 else if (cnt % 8 == 0) 741 printf(" |"); 742 printf(" %08x", *p++); 743 cnt += 4; 744 if (cnt % 16 == 0) 745 printf("\n"); 746 } 747 if (cnt % 16 != 0) 748 printf("\n"); 749 #endif 750 } 751 752 /* 7.2 xHCI Support Protocol Capability */ 753 static void 754 xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp) 755 { 756 /* XXX Cache this lot */ 757 758 const uint32_t w0 = xhci_read_4(sc, ecp); 759 const uint32_t w4 = xhci_read_4(sc, ecp + 4); 760 const uint32_t w8 = xhci_read_4(sc, ecp + 8); 761 const uint32_t wc = xhci_read_4(sc, ecp + 0xc); 762 763 aprint_debug_dev(sc->sc_dev, 764 " SP: %08x %08x %08x %08x\n", w0, w4, w8, wc); 765 766 if (w4 != XHCI_XECP_USBID) 767 return; 768 769 const int major = XHCI_XECP_SP_W0_MAJOR(w0); 770 const int minor = XHCI_XECP_SP_W0_MINOR(w0); 771 const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8); 772 const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8); 773 774 const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16)); 775 switch (mm) { 776 case 0x0200: 777 case 0x0300: 778 case 0x0301: 779 aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n", 780 major == 3 ? "ss" : "hs", cpo, cpo + cpc -1); 781 break; 782 default: 783 aprint_debug_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n", 784 major, minor); 785 return; 786 } 787 788 const size_t bus = (major == 3) ? 0 : 1; 789 790 /* Index arrays with 0..n-1 where ports are numbered 1..n */ 791 for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) { 792 if (sc->sc_ctlrportmap[cp] != 0) { 793 aprint_error_dev(sc->sc_dev, "contoller port %zu " 794 "already assigned", cp); 795 continue; 796 } 797 798 sc->sc_ctlrportbus[cp / NBBY] |= 799 bus == 0 ? 0 : __BIT(cp % NBBY); 800 801 const size_t rhp = sc->sc_rhportcount[bus]++; 802 803 KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0, 804 "bus %zu rhp %zu is %d", bus, rhp, 805 sc->sc_rhportmap[bus][rhp]); 806 807 sc->sc_rhportmap[bus][rhp] = cp + 1; 808 sc->sc_ctlrportmap[cp] = rhp + 1; 809 } 810 } 811 812 /* Process extended capabilities */ 813 static void 814 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 815 { 816 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 817 818 bus_size_t ecp = XHCI_HCC_XECP(hcc) * 4; 819 while (ecp != 0) { 820 uint32_t ecr = xhci_read_4(sc, ecp); 821 aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr); 822 switch (XHCI_XECP_ID(ecr)) { 823 case XHCI_ID_PROTOCOLS: { 824 xhci_id_protocols(sc, ecp); 825 break; 826 } 827 case XHCI_ID_USB_LEGACY: { 828 uint8_t bios_sem; 829 830 /* Take host controller ownership from BIOS */ 831 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 832 if (bios_sem) { 833 /* sets xHCI to be owned by OS */ 834 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 835 aprint_debug_dev(sc->sc_dev, 836 "waiting for BIOS to give up control\n"); 837 for (int i = 0; i < 5000; i++) { 838 bios_sem = xhci_read_1(sc, ecp + 839 XHCI_XECP_BIOS_SEM); 840 if (bios_sem == 0) 841 break; 842 DELAY(1000); 843 } 844 if (bios_sem) { 845 aprint_error_dev(sc->sc_dev, 846 "timed out waiting for BIOS\n"); 847 } 848 } 849 break; 850 } 851 default: 852 break; 853 } 854 ecr = xhci_read_4(sc, ecp); 855 if (XHCI_XECP_NEXT(ecr) == 0) { 856 ecp = 0; 857 } else { 858 ecp += XHCI_XECP_NEXT(ecr) * 4; 859 } 860 } 861 } 862 863 #define XHCI_HCCPREV1_BITS \ 864 "\177\020" /* New bitmask */ \ 865 "f\020\020XECP\0" \ 866 "f\014\4MAXPSA\0" \ 867 "b\013CFC\0" \ 868 "b\012SEC\0" \ 869 "b\011SBD\0" \ 870 "b\010FSE\0" \ 871 "b\7NSS\0" \ 872 "b\6LTC\0" \ 873 "b\5LHRC\0" \ 874 "b\4PIND\0" \ 875 "b\3PPC\0" \ 876 "b\2CZC\0" \ 877 "b\1BNC\0" \ 878 "b\0AC64\0" \ 879 "\0" 880 #define XHCI_HCCV1_x_BITS \ 881 "\177\020" /* New bitmask */ \ 882 "f\020\020XECP\0" \ 883 "f\014\4MAXPSA\0" \ 884 "b\013CFC\0" \ 885 "b\012SEC\0" \ 886 "b\011SPC\0" \ 887 "b\010PAE\0" \ 888 "b\7NSS\0" \ 889 "b\6LTC\0" \ 890 "b\5LHRC\0" \ 891 "b\4PIND\0" \ 892 "b\3PPC\0" \ 893 "b\2CSZ\0" \ 894 "b\1BNC\0" \ 895 "b\0AC64\0" \ 896 "\0" 897 898 void 899 xhci_start(struct xhci_softc *sc) 900 { 901 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 902 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 903 /* Intel xhci needs interrupt rate moderated. */ 904 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 905 else 906 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 907 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 908 xhci_rt_read_4(sc, XHCI_IMOD(0))); 909 910 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 911 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 912 xhci_op_read_4(sc, XHCI_USBCMD)); 913 } 914 915 int 916 xhci_init(struct xhci_softc *sc) 917 { 918 bus_size_t bsz; 919 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 920 uint32_t pagesize, config; 921 int i = 0; 922 uint16_t hciversion; 923 uint8_t caplength; 924 925 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 926 927 /* Set up the bus struct for the usb 3 and usb 2 buses */ 928 sc->sc_bus.ub_methods = &xhci_bus_methods; 929 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 930 sc->sc_bus.ub_revision = USBREV_3_0; 931 sc->sc_bus.ub_usedma = true; 932 sc->sc_bus.ub_hcpriv = sc; 933 934 sc->sc_bus2.ub_methods = &xhci_bus_methods; 935 sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe); 936 sc->sc_bus2.ub_revision = USBREV_2_0; 937 sc->sc_bus2.ub_usedma = true; 938 sc->sc_bus2.ub_hcpriv = sc; 939 sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag; 940 941 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 942 caplength = XHCI_CAP_CAPLENGTH(cap); 943 hciversion = XHCI_CAP_HCIVERSION(cap); 944 945 if (hciversion < XHCI_HCIVERSION_0_96 || 946 hciversion > XHCI_HCIVERSION_1_0) { 947 aprint_normal_dev(sc->sc_dev, 948 "xHCI version %x.%x not known to be supported\n", 949 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 950 } else { 951 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 952 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 953 } 954 955 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 956 &sc->sc_cbh) != 0) { 957 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 958 return ENOMEM; 959 } 960 961 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 962 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 963 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 964 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 965 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 966 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 967 aprint_debug_dev(sc->sc_dev, 968 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 969 970 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 971 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 972 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 973 974 char sbuf[128]; 975 if (hciversion < XHCI_HCIVERSION_1_0) 976 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 977 else 978 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 979 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 980 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 981 982 /* default all ports to bus 0, i.e. usb 3 */ 983 sc->sc_ctlrportbus = kmem_zalloc( 984 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP); 985 sc->sc_ctlrportmap = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 986 987 /* controller port to bus roothub port map */ 988 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 989 sc->sc_rhportmap[j] = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 990 } 991 992 /* 993 * Process all Extended Capabilities 994 */ 995 xhci_ecp(sc, hcc); 996 997 bsz = XHCI_PORTSC(sc->sc_maxports); 998 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 999 &sc->sc_obh) != 0) { 1000 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 1001 return ENOMEM; 1002 } 1003 1004 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 1005 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 1006 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 1007 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 1008 return ENOMEM; 1009 } 1010 1011 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 1012 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 1013 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 1014 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 1015 return ENOMEM; 1016 } 1017 1018 int rv; 1019 rv = xhci_hc_reset(sc); 1020 if (rv != 0) { 1021 return rv; 1022 } 1023 1024 if (sc->sc_vendor_init) 1025 sc->sc_vendor_init(sc); 1026 1027 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 1028 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 1029 pagesize = ffs(pagesize); 1030 if (pagesize == 0) { 1031 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 1032 return EIO; 1033 } 1034 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 1035 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 1036 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 1037 (uint32_t)sc->sc_maxslots); 1038 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 1039 1040 usbd_status err; 1041 1042 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 1043 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 1044 if (sc->sc_maxspbuf != 0) { 1045 err = usb_allocmem(&sc->sc_bus, 1046 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 1047 &sc->sc_spbufarray_dma); 1048 if (err) { 1049 aprint_error_dev(sc->sc_dev, 1050 "spbufarray init fail, err %d\n", err); 1051 return ENOMEM; 1052 } 1053 1054 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 1055 sc->sc_maxspbuf, KM_SLEEP); 1056 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 1057 for (i = 0; i < sc->sc_maxspbuf; i++) { 1058 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 1059 /* allocate contexts */ 1060 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 1061 sc->sc_pgsz, dma); 1062 if (err) { 1063 aprint_error_dev(sc->sc_dev, 1064 "spbufarray_dma init fail, err %d\n", err); 1065 rv = ENOMEM; 1066 goto bad1; 1067 } 1068 spbufarray[i] = htole64(DMAADDR(dma, 0)); 1069 usb_syncmem(dma, 0, sc->sc_pgsz, 1070 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1071 } 1072 1073 usb_syncmem(&sc->sc_spbufarray_dma, 0, 1074 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 1075 } 1076 1077 config = xhci_op_read_4(sc, XHCI_CONFIG); 1078 config &= ~0xFF; 1079 config |= sc->sc_maxslots & 0xFF; 1080 xhci_op_write_4(sc, XHCI_CONFIG, config); 1081 1082 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 1083 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 1084 if (err) { 1085 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 1086 err); 1087 rv = ENOMEM; 1088 goto bad1; 1089 } 1090 1091 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 1092 XHCI_EVENT_RING_SEGMENTS_ALIGN); 1093 if (err) { 1094 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 1095 err); 1096 rv = ENOMEM; 1097 goto bad2; 1098 } 1099 1100 usb_dma_t *dma; 1101 size_t size; 1102 size_t align; 1103 1104 dma = &sc->sc_eventst_dma; 1105 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 1106 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 1107 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 1108 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 1109 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1110 if (err) { 1111 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 1112 err); 1113 rv = ENOMEM; 1114 goto bad3; 1115 } 1116 1117 memset(KERNADDR(dma, 0), 0, size); 1118 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1119 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 1120 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 1121 KERNADDR(&sc->sc_eventst_dma, 0), 1122 sc->sc_eventst_dma.udma_block->size); 1123 1124 dma = &sc->sc_dcbaa_dma; 1125 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 1126 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 1127 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 1128 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1129 if (err) { 1130 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1131 rv = ENOMEM; 1132 goto bad4; 1133 } 1134 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 1135 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1136 KERNADDR(&sc->sc_dcbaa_dma, 0), 1137 sc->sc_dcbaa_dma.udma_block->size); 1138 1139 memset(KERNADDR(dma, 0), 0, size); 1140 if (sc->sc_maxspbuf != 0) { 1141 /* 1142 * DCBA entry 0 hold the scratchbuf array pointer. 1143 */ 1144 *(uint64_t *)KERNADDR(dma, 0) = 1145 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1146 } 1147 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1148 1149 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1150 KM_SLEEP); 1151 if (sc->sc_slots == NULL) { 1152 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1153 rv = ENOMEM; 1154 goto bad; 1155 } 1156 1157 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1158 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1159 if (sc->sc_xferpool == NULL) { 1160 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1161 err); 1162 rv = ENOMEM; 1163 goto bad; 1164 } 1165 1166 cv_init(&sc->sc_command_cv, "xhcicmd"); 1167 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1168 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1169 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1170 1171 struct xhci_erste *erst; 1172 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1173 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1174 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1175 erst[0].erste_3 = htole32(0); 1176 usb_syncmem(&sc->sc_eventst_dma, 0, 1177 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1178 1179 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1180 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1181 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1182 XHCI_ERDP_LO_BUSY); 1183 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1184 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1185 sc->sc_cr.xr_cs); 1186 1187 #if 0 1188 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1189 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1190 #endif 1191 1192 if ((sc->sc_quirks & XHCI_DEFERRED_START) == 0) 1193 xhci_start(sc); 1194 1195 return 0; 1196 1197 bad: 1198 if (sc->sc_xferpool) { 1199 pool_cache_destroy(sc->sc_xferpool); 1200 sc->sc_xferpool = NULL; 1201 } 1202 1203 if (sc->sc_slots) { 1204 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1205 sc->sc_maxslots); 1206 sc->sc_slots = NULL; 1207 } 1208 1209 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1210 bad4: 1211 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1212 bad3: 1213 xhci_ring_free(sc, &sc->sc_er); 1214 bad2: 1215 xhci_ring_free(sc, &sc->sc_cr); 1216 i = sc->sc_maxspbuf; 1217 bad1: 1218 for (int j = 0; j < i; j++) 1219 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1220 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1221 1222 return rv; 1223 } 1224 1225 static inline bool 1226 xhci_polling_p(struct xhci_softc * const sc) 1227 { 1228 return sc->sc_bus.ub_usepolling || sc->sc_bus2.ub_usepolling; 1229 } 1230 1231 int 1232 xhci_intr(void *v) 1233 { 1234 struct xhci_softc * const sc = v; 1235 int ret = 0; 1236 1237 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1238 1239 if (sc == NULL) 1240 return 0; 1241 1242 mutex_spin_enter(&sc->sc_intr_lock); 1243 1244 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1245 goto done; 1246 1247 /* If we get an interrupt while polling, then just ignore it. */ 1248 if (xhci_polling_p(sc)) { 1249 #ifdef DIAGNOSTIC 1250 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1251 #endif 1252 goto done; 1253 } 1254 1255 ret = xhci_intr1(sc); 1256 if (ret) { 1257 usb_schedsoftintr(&sc->sc_bus); 1258 } 1259 done: 1260 mutex_spin_exit(&sc->sc_intr_lock); 1261 return ret; 1262 } 1263 1264 int 1265 xhci_intr1(struct xhci_softc * const sc) 1266 { 1267 uint32_t usbsts; 1268 uint32_t iman; 1269 1270 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1271 1272 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1273 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1274 #if 0 1275 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1276 return 0; 1277 } 1278 #endif 1279 xhci_op_write_4(sc, XHCI_USBSTS, 1280 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1281 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1282 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1283 1284 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1285 DPRINTFN(16, "IMAN0 %08jx", iman, 0, 0, 0); 1286 iman |= XHCI_IMAN_INTR_PEND; 1287 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1288 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1289 DPRINTFN(16, "IMAN0 %08jx", iman, 0, 0, 0); 1290 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1291 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1292 1293 return 1; 1294 } 1295 1296 /* 1297 * 3 port speed types used in USB stack 1298 * 1299 * usbdi speed 1300 * definition: USB_SPEED_* in usb.h 1301 * They are used in struct usbd_device in USB stack. 1302 * ioctl interface uses these values too. 1303 * port_status speed 1304 * definition: UPS_*_SPEED in usb.h 1305 * They are used in usb_port_status_t and valid only for USB 2.0. 1306 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1307 * of usb_port_status_ext_t indicates port speed. 1308 * Note that some 3.0 values overlap with 2.0 values. 1309 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1310 * means UPS_LOW_SPEED in HS.) 1311 * port status returned from hub also uses these values. 1312 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1313 * or more. 1314 * xspeed: 1315 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1316 * They are used in only slot context and PORTSC reg of xhci. 1317 * The difference between usbdi speed and xspeed is 1318 * that FS and LS values are swapped. 1319 */ 1320 1321 /* convert usbdi speed to xspeed */ 1322 static int 1323 xhci_speed2xspeed(int speed) 1324 { 1325 switch (speed) { 1326 case USB_SPEED_LOW: return 2; 1327 case USB_SPEED_FULL: return 1; 1328 default: return speed; 1329 } 1330 } 1331 1332 #if 0 1333 /* convert xspeed to usbdi speed */ 1334 static int 1335 xhci_xspeed2speed(int xspeed) 1336 { 1337 switch (xspeed) { 1338 case 1: return USB_SPEED_FULL; 1339 case 2: return USB_SPEED_LOW; 1340 default: return xspeed; 1341 } 1342 } 1343 #endif 1344 1345 /* convert xspeed to port status speed */ 1346 static int 1347 xhci_xspeed2psspeed(int xspeed) 1348 { 1349 switch (xspeed) { 1350 case 0: return 0; 1351 case 1: return UPS_FULL_SPEED; 1352 case 2: return UPS_LOW_SPEED; 1353 case 3: return UPS_HIGH_SPEED; 1354 default: return UPS_OTHER_SPEED; 1355 } 1356 } 1357 1358 /* 1359 * Construct input contexts and issue TRB to open pipe. 1360 */ 1361 static usbd_status 1362 xhci_configure_endpoint(struct usbd_pipe *pipe) 1363 { 1364 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1365 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1366 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1367 struct xhci_trb trb; 1368 usbd_status err; 1369 1370 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1371 DPRINTFN(4, "slot %ju dci %ju epaddr 0x%02jx attr 0x%02jx", 1372 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1373 pipe->up_endpoint->ue_edesc->bmAttributes); 1374 1375 /* XXX ensure input context is available? */ 1376 1377 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1378 1379 /* set up context */ 1380 xhci_setup_ctx(pipe); 1381 1382 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1383 sc->sc_ctxsz * 1); 1384 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1385 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1386 1387 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1388 trb.trb_2 = 0; 1389 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1390 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1391 1392 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1393 1394 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1395 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1396 sc->sc_ctxsz * 1); 1397 1398 return err; 1399 } 1400 1401 #if 0 1402 static usbd_status 1403 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1404 { 1405 #ifdef USB_DEBUG 1406 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1407 #endif 1408 1409 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1410 DPRINTFN(4, "slot %ju", xs->xs_idx, 0, 0, 0); 1411 1412 return USBD_NORMAL_COMPLETION; 1413 } 1414 #endif 1415 1416 /* 4.6.8, 6.4.3.7 */ 1417 static usbd_status 1418 xhci_reset_endpoint_locked(struct usbd_pipe *pipe) 1419 { 1420 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1421 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1422 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1423 struct xhci_trb trb; 1424 usbd_status err; 1425 1426 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1427 DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1428 1429 KASSERT(mutex_owned(&sc->sc_lock)); 1430 1431 trb.trb_0 = 0; 1432 trb.trb_2 = 0; 1433 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1434 XHCI_TRB_3_EP_SET(dci) | 1435 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1436 1437 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1438 1439 return err; 1440 } 1441 1442 static usbd_status 1443 xhci_reset_endpoint(struct usbd_pipe *pipe) 1444 { 1445 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1446 1447 mutex_enter(&sc->sc_lock); 1448 usbd_status ret = xhci_reset_endpoint_locked(pipe); 1449 mutex_exit(&sc->sc_lock); 1450 1451 return ret; 1452 } 1453 1454 /* 1455 * 4.6.9, 6.4.3.8 1456 * Stop execution of TDs on xfer ring. 1457 * Should be called with sc_lock held. 1458 */ 1459 static usbd_status 1460 xhci_stop_endpoint(struct usbd_pipe *pipe) 1461 { 1462 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1463 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1464 struct xhci_trb trb; 1465 usbd_status err; 1466 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1467 1468 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1469 DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1470 1471 KASSERT(mutex_owned(&sc->sc_lock)); 1472 1473 trb.trb_0 = 0; 1474 trb.trb_2 = 0; 1475 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1476 XHCI_TRB_3_EP_SET(dci) | 1477 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1478 1479 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1480 1481 return err; 1482 } 1483 1484 /* 1485 * Set TR Dequeue Pointer. 1486 * xHCI 1.1 4.6.10 6.4.3.9 1487 * Purge all of the TRBs on ring and reinitialize ring. 1488 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1489 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1490 * error will be generated. 1491 */ 1492 static usbd_status 1493 xhci_set_dequeue_locked(struct usbd_pipe *pipe) 1494 { 1495 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1496 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1497 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1498 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1499 struct xhci_trb trb; 1500 usbd_status err; 1501 1502 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1503 DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1504 1505 KASSERT(mutex_owned(&sc->sc_lock)); 1506 1507 xhci_host_dequeue(xr); 1508 1509 /* set DCS */ 1510 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1511 trb.trb_2 = 0; 1512 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1513 XHCI_TRB_3_EP_SET(dci) | 1514 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1515 1516 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1517 1518 return err; 1519 } 1520 1521 static usbd_status 1522 xhci_set_dequeue(struct usbd_pipe *pipe) 1523 { 1524 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1525 1526 mutex_enter(&sc->sc_lock); 1527 usbd_status ret = xhci_set_dequeue_locked(pipe); 1528 mutex_exit(&sc->sc_lock); 1529 1530 return ret; 1531 } 1532 1533 /* 1534 * Open new pipe: called from usbd_setup_pipe_flags. 1535 * Fills methods of pipe. 1536 * If pipe is not for ep0, calls configure_endpoint. 1537 */ 1538 static usbd_status 1539 xhci_open(struct usbd_pipe *pipe) 1540 { 1541 struct usbd_device * const dev = pipe->up_dev; 1542 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1543 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1544 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1545 1546 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1547 DPRINTFN(1, "addr %jd depth %jd port %jd speed %jd", dev->ud_addr, 1548 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1549 DPRINTFN(1, " dci %ju type 0x%02jx epaddr 0x%02jx attr 0x%02jx", 1550 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1551 ed->bmAttributes); 1552 DPRINTFN(1, " mps %ju ival %ju", UGETW(ed->wMaxPacketSize), 1553 ed->bInterval, 0, 0); 1554 1555 if (sc->sc_dying) 1556 return USBD_IOERROR; 1557 1558 /* Root Hub */ 1559 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1560 switch (ed->bEndpointAddress) { 1561 case USB_CONTROL_ENDPOINT: 1562 pipe->up_methods = &roothub_ctrl_methods; 1563 break; 1564 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1565 pipe->up_methods = &xhci_root_intr_methods; 1566 break; 1567 default: 1568 pipe->up_methods = NULL; 1569 DPRINTFN(0, "bad bEndpointAddress 0x%02jx", 1570 ed->bEndpointAddress, 0, 0, 0); 1571 return USBD_INVAL; 1572 } 1573 return USBD_NORMAL_COMPLETION; 1574 } 1575 1576 switch (xfertype) { 1577 case UE_CONTROL: 1578 pipe->up_methods = &xhci_device_ctrl_methods; 1579 break; 1580 case UE_ISOCHRONOUS: 1581 pipe->up_methods = &xhci_device_isoc_methods; 1582 return USBD_INVAL; 1583 break; 1584 case UE_BULK: 1585 pipe->up_methods = &xhci_device_bulk_methods; 1586 break; 1587 case UE_INTERRUPT: 1588 pipe->up_methods = &xhci_device_intr_methods; 1589 break; 1590 default: 1591 return USBD_IOERROR; 1592 break; 1593 } 1594 1595 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1596 return xhci_configure_endpoint(pipe); 1597 1598 return USBD_NORMAL_COMPLETION; 1599 } 1600 1601 /* 1602 * Closes pipe, called from usbd_kill_pipe via close methods. 1603 * If the endpoint to be closed is ep0, disable_slot. 1604 * Should be called with sc_lock held. 1605 */ 1606 static void 1607 xhci_close_pipe(struct usbd_pipe *pipe) 1608 { 1609 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1610 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1611 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1612 const u_int dci = xhci_ep_get_dci(ed); 1613 struct xhci_trb trb; 1614 uint32_t *cp; 1615 1616 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1617 1618 if (sc->sc_dying) 1619 return; 1620 1621 /* xs is uninitialized before xhci_init_slot */ 1622 if (xs == NULL || xs->xs_idx == 0) 1623 return; 1624 1625 DPRINTFN(4, "pipe %#jx slot %ju dci %ju", (uintptr_t)pipe, xs->xs_idx, 1626 dci, 0); 1627 1628 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1629 KASSERT(mutex_owned(&sc->sc_lock)); 1630 1631 if (pipe->up_dev->ud_depth == 0) 1632 return; 1633 1634 if (dci == XHCI_DCI_EP_CONTROL) { 1635 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1636 xhci_disable_slot(sc, xs->xs_idx); 1637 return; 1638 } 1639 1640 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED) 1641 (void)xhci_stop_endpoint(pipe); 1642 1643 /* 1644 * set appropriate bit to be dropped. 1645 * don't set DC bit to 1, otherwise all endpoints 1646 * would be deconfigured. 1647 */ 1648 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1649 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1650 cp[1] = htole32(0); 1651 1652 /* XXX should be most significant one, not dci? */ 1653 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1654 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1655 1656 /* configure ep context performs an implicit dequeue */ 1657 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 1658 1659 /* sync input contexts before they are read from memory */ 1660 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1661 1662 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1663 trb.trb_2 = 0; 1664 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1665 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1666 1667 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1668 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1669 } 1670 1671 /* 1672 * Abort transfer. 1673 * Should be called with sc_lock held. 1674 */ 1675 static void 1676 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1677 { 1678 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1679 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1680 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1681 1682 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1683 DPRINTFN(4, "xfer %#jx pipe %#jx status %jd", 1684 (uintptr_t)xfer, (uintptr_t)xfer->ux_pipe, status, 0); 1685 1686 KASSERT(mutex_owned(&sc->sc_lock)); 1687 1688 if (sc->sc_dying) { 1689 /* If we're dying, just do the software part. */ 1690 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 1691 xfer->ux_status, 0, 0); 1692 xfer->ux_status = status; 1693 callout_stop(&xfer->ux_callout); 1694 usb_transfer_complete(xfer); 1695 return; 1696 } 1697 1698 /* 1699 * If an abort is already in progress then just wait for it to 1700 * complete and return. 1701 */ 1702 if (xfer->ux_hcflags & UXFER_ABORTING) { 1703 DPRINTFN(4, "already aborting", 0, 0, 0, 0); 1704 #ifdef DIAGNOSTIC 1705 if (status == USBD_TIMEOUT) 1706 DPRINTFN(4, "TIMEOUT while aborting", 0, 0, 0, 0); 1707 #endif 1708 /* Override the status which might be USBD_TIMEOUT. */ 1709 xfer->ux_status = status; 1710 DPRINTFN(4, "xfer %#jx waiting for abort to finish", 1711 (uintptr_t)xfer, 0, 0, 0); 1712 xfer->ux_hcflags |= UXFER_ABORTWAIT; 1713 while (xfer->ux_hcflags & UXFER_ABORTING) 1714 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 1715 return; 1716 } 1717 xfer->ux_hcflags |= UXFER_ABORTING; 1718 1719 /* 1720 * Step 1: Stop xfer timeout timer. 1721 */ 1722 xfer->ux_status = status; 1723 callout_stop(&xfer->ux_callout); 1724 1725 /* 1726 * Step 2: Stop execution of TD on the ring. 1727 */ 1728 switch (xhci_get_epstate(sc, xs, dci)) { 1729 case XHCI_EPSTATE_HALTED: 1730 (void)xhci_reset_endpoint_locked(xfer->ux_pipe); 1731 break; 1732 case XHCI_EPSTATE_STOPPED: 1733 break; 1734 default: 1735 (void)xhci_stop_endpoint(xfer->ux_pipe); 1736 break; 1737 } 1738 #ifdef DIAGNOSTIC 1739 uint32_t epst = xhci_get_epstate(sc, xs, dci); 1740 if (epst != XHCI_EPSTATE_STOPPED) 1741 DPRINTFN(4, "dci %ju not stopped %ju", dci, epst, 0, 0); 1742 #endif 1743 1744 /* 1745 * Step 3: Remove any vestiges of the xfer from the ring. 1746 */ 1747 xhci_set_dequeue_locked(xfer->ux_pipe); 1748 1749 /* 1750 * Step 4: Notify completion to waiting xfers. 1751 */ 1752 int wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 1753 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 1754 usb_transfer_complete(xfer); 1755 if (wake) { 1756 cv_broadcast(&xfer->ux_hccv); 1757 } 1758 DPRINTFN(14, "end", 0, 0, 0, 0); 1759 1760 KASSERT(mutex_owned(&sc->sc_lock)); 1761 } 1762 1763 static void 1764 xhci_host_dequeue(struct xhci_ring * const xr) 1765 { 1766 /* When dequeueing the controller, update our struct copy too */ 1767 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1768 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1769 BUS_DMASYNC_PREWRITE); 1770 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1771 1772 xr->xr_ep = 0; 1773 xr->xr_cs = 1; 1774 } 1775 1776 /* 1777 * Recover STALLed endpoint. 1778 * xHCI 1.1 sect 4.10.2.1 1779 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1780 * all transfers on transfer ring. 1781 * These are done in thread context asynchronously. 1782 */ 1783 static void 1784 xhci_clear_endpoint_stall_async_task(void *cookie) 1785 { 1786 struct usbd_xfer * const xfer = cookie; 1787 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1788 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1789 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1790 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1791 1792 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1793 DPRINTFN(4, "xfer %#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, 1794 dci, 0); 1795 1796 xhci_reset_endpoint(xfer->ux_pipe); 1797 xhci_set_dequeue(xfer->ux_pipe); 1798 1799 mutex_enter(&sc->sc_lock); 1800 tr->is_halted = false; 1801 usb_transfer_complete(xfer); 1802 mutex_exit(&sc->sc_lock); 1803 DPRINTFN(4, "ends", 0, 0, 0, 0); 1804 } 1805 1806 static usbd_status 1807 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1808 { 1809 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1810 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1811 1812 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1813 DPRINTFN(4, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 1814 1815 if (sc->sc_dying) { 1816 return USBD_IOERROR; 1817 } 1818 1819 usb_init_task(&xp->xp_async_task, 1820 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1821 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1822 DPRINTFN(4, "ends", 0, 0, 0, 0); 1823 1824 return USBD_NORMAL_COMPLETION; 1825 } 1826 1827 /* Process roothub port status/change events and notify to uhub_intr. */ 1828 static void 1829 xhci_rhpsc(struct xhci_softc * const sc, u_int ctlrport) 1830 { 1831 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1832 DPRINTFN(4, "xhci%jd: port %ju status change", device_unit(sc->sc_dev), 1833 ctlrport, 0, 0); 1834 1835 if (ctlrport > sc->sc_maxports) 1836 return; 1837 1838 const size_t bn = xhci_ctlrport2bus(sc, ctlrport); 1839 const size_t rhp = xhci_ctlrport2rhport(sc, ctlrport); 1840 struct usbd_xfer * const xfer = sc->sc_intrxfer[bn]; 1841 1842 DPRINTFN(4, "xhci%jd: bus %jd bp %ju xfer %#jx status change", 1843 device_unit(sc->sc_dev), bn, rhp, (uintptr_t)xfer); 1844 1845 if (xfer == NULL) 1846 return; 1847 1848 uint8_t *p = xfer->ux_buf; 1849 memset(p, 0, xfer->ux_length); 1850 p[rhp / NBBY] |= 1 << (rhp % NBBY); 1851 xfer->ux_actlen = xfer->ux_length; 1852 xfer->ux_status = USBD_NORMAL_COMPLETION; 1853 usb_transfer_complete(xfer); 1854 } 1855 1856 /* Process Transfer Events */ 1857 static void 1858 xhci_event_transfer(struct xhci_softc * const sc, 1859 const struct xhci_trb * const trb) 1860 { 1861 uint64_t trb_0; 1862 uint32_t trb_2, trb_3; 1863 uint8_t trbcode; 1864 u_int slot, dci; 1865 struct xhci_slot *xs; 1866 struct xhci_ring *xr; 1867 struct xhci_xfer *xx; 1868 struct usbd_xfer *xfer; 1869 usbd_status err; 1870 1871 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1872 1873 trb_0 = le64toh(trb->trb_0); 1874 trb_2 = le32toh(trb->trb_2); 1875 trb_3 = le32toh(trb->trb_3); 1876 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1877 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1878 dci = XHCI_TRB_3_EP_GET(trb_3); 1879 xs = &sc->sc_slots[slot]; 1880 xr = &xs->xs_ep[dci].xe_tr; 1881 1882 /* sanity check */ 1883 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1884 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1885 1886 int idx = 0; 1887 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1888 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1889 DPRINTFN(0, "invalid trb_0 0x%jx", trb_0, 0, 0, 0); 1890 return; 1891 } 1892 xx = xr->xr_cookies[idx]; 1893 1894 /* clear cookie of consumed TRB */ 1895 xr->xr_cookies[idx] = NULL; 1896 1897 /* 1898 * xx is NULL if pipe is opened but xfer is not started. 1899 * It happens when stopping idle pipe. 1900 */ 1901 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1902 DPRINTFN(1, "Ignore #%ju: cookie %#jx cc %ju dci %ju", 1903 idx, (uintptr_t)xx, trbcode, dci); 1904 DPRINTFN(1, " orig TRB %jx type %ju", trb_0, 1905 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1906 0, 0); 1907 return; 1908 } 1909 } else { 1910 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1911 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1912 } 1913 /* XXX this may not happen */ 1914 if (xx == NULL) { 1915 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1916 return; 1917 } 1918 xfer = &xx->xx_xfer; 1919 /* XXX this may happen when detaching */ 1920 if (xfer == NULL) { 1921 DPRINTFN(1, "xx(%#jx)->xx_xfer is NULL trb_0 %#jx", 1922 (uintptr_t)xx, trb_0, 0, 0); 1923 return; 1924 } 1925 DPRINTFN(14, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 1926 /* XXX I dunno why this happens */ 1927 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1928 1929 if (!xfer->ux_pipe->up_repeat && 1930 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1931 DPRINTFN(1, "xfer(%#jx)->pipe not queued", (uintptr_t)xfer, 1932 0, 0, 0); 1933 return; 1934 } 1935 1936 /* 4.11.5.2 Event Data TRB */ 1937 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1938 DPRINTFN(14, "transfer Event Data: 0x%016jx 0x%08jx" 1939 " %02jx", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1940 if ((trb_0 & 0x3) == 0x3) { 1941 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1942 } 1943 } 1944 1945 switch (trbcode) { 1946 case XHCI_TRB_ERROR_SHORT_PKT: 1947 case XHCI_TRB_ERROR_SUCCESS: 1948 /* 1949 * A ctrl transfer can generate two events if it has a Data 1950 * stage. A short data stage can be OK and should not 1951 * complete the transfer as the status stage needs to be 1952 * performed. 1953 * 1954 * Note: Data and Status stage events point at same xfer. 1955 * ux_actlen and ux_dmabuf will be passed to 1956 * usb_transfer_complete after the Status stage event. 1957 * 1958 * It can be distingished which stage generates the event: 1959 * + by checking least 3 bits of trb_0 if ED==1. 1960 * (see xhci_device_ctrl_start). 1961 * + by checking the type of original TRB if ED==0. 1962 * 1963 * In addition, intr, bulk, and isoc transfer currently 1964 * consists of single TD, so the "skip" is not needed. 1965 * ctrl xfer uses EVENT_DATA, and others do not. 1966 * Thus driver can switch the flow by checking ED bit. 1967 */ 1968 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1969 if (xfer->ux_actlen == 0) 1970 xfer->ux_actlen = xfer->ux_length - 1971 XHCI_TRB_2_REM_GET(trb_2); 1972 if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)) 1973 == XHCI_TRB_TYPE_DATA_STAGE) { 1974 return; 1975 } 1976 } else if ((trb_0 & 0x3) == 0x3) { 1977 return; 1978 } 1979 err = USBD_NORMAL_COMPLETION; 1980 break; 1981 case XHCI_TRB_ERROR_STOPPED: 1982 case XHCI_TRB_ERROR_LENGTH: 1983 case XHCI_TRB_ERROR_STOPPED_SHORT: 1984 /* 1985 * don't complete the transfer being aborted 1986 * as abort_xfer does instead. 1987 */ 1988 if (xfer->ux_hcflags & UXFER_ABORTING) { 1989 DPRINTFN(14, "ignore aborting xfer %#jx", 1990 (uintptr_t)xfer, 0, 0, 0); 1991 return; 1992 } 1993 err = USBD_CANCELLED; 1994 break; 1995 case XHCI_TRB_ERROR_STALL: 1996 case XHCI_TRB_ERROR_BABBLE: 1997 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 1998 xr->is_halted = true; 1999 err = USBD_STALLED; 2000 /* 2001 * Stalled endpoints can be recoverd by issuing 2002 * command TRB TYPE_RESET_EP on xHCI instead of 2003 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 2004 * on the endpoint. However, this function may be 2005 * called from softint context (e.g. from umass), 2006 * in that case driver gets KASSERT in cv_timedwait 2007 * in xhci_do_command. 2008 * To avoid this, this runs reset_endpoint and 2009 * usb_transfer_complete in usb task thread 2010 * asynchronously (and then umass issues clear 2011 * UF_ENDPOINT_HALT). 2012 */ 2013 xfer->ux_status = err; 2014 callout_stop(&xfer->ux_callout); 2015 xhci_clear_endpoint_stall_async(xfer); 2016 return; 2017 default: 2018 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 2019 err = USBD_IOERROR; 2020 break; 2021 } 2022 xfer->ux_status = err; 2023 2024 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 2025 if ((trb_0 & 0x3) == 0x0) { 2026 callout_stop(&xfer->ux_callout); 2027 usb_transfer_complete(xfer); 2028 } 2029 } else { 2030 callout_stop(&xfer->ux_callout); 2031 usb_transfer_complete(xfer); 2032 } 2033 } 2034 2035 /* Process Command complete events */ 2036 static void 2037 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 2038 { 2039 uint64_t trb_0; 2040 uint32_t trb_2, trb_3; 2041 2042 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2043 2044 KASSERT(mutex_owned(&sc->sc_lock)); 2045 2046 trb_0 = le64toh(trb->trb_0); 2047 trb_2 = le32toh(trb->trb_2); 2048 trb_3 = le32toh(trb->trb_3); 2049 2050 if (trb_0 == sc->sc_command_addr) { 2051 sc->sc_resultpending = false; 2052 2053 sc->sc_result_trb.trb_0 = trb_0; 2054 sc->sc_result_trb.trb_2 = trb_2; 2055 sc->sc_result_trb.trb_3 = trb_3; 2056 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2057 XHCI_TRB_ERROR_SUCCESS) { 2058 DPRINTFN(1, "command completion " 2059 "failure: 0x%016jx 0x%08jx 0x%08jx", 2060 trb_0, trb_2, trb_3, 0); 2061 } 2062 cv_signal(&sc->sc_command_cv); 2063 } else { 2064 DPRINTFN(1, "spurious event: %#jx 0x%016jx " 2065 "0x%08jx 0x%08jx", (uintptr_t)trb, trb_0, trb_2, trb_3); 2066 } 2067 } 2068 2069 /* 2070 * Process events. 2071 * called from xhci_softintr 2072 */ 2073 static void 2074 xhci_handle_event(struct xhci_softc * const sc, 2075 const struct xhci_trb * const trb) 2076 { 2077 uint64_t trb_0; 2078 uint32_t trb_2, trb_3; 2079 2080 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2081 2082 trb_0 = le64toh(trb->trb_0); 2083 trb_2 = le32toh(trb->trb_2); 2084 trb_3 = le32toh(trb->trb_3); 2085 2086 DPRINTFN(14, "event: %#jx 0x%016jx 0x%08jx 0x%08jx", 2087 (uintptr_t)trb, trb_0, trb_2, trb_3); 2088 2089 /* 2090 * 4.11.3.1, 6.4.2.1 2091 * TRB Pointer is invalid for these completion codes. 2092 */ 2093 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2094 case XHCI_TRB_ERROR_RING_UNDERRUN: 2095 case XHCI_TRB_ERROR_RING_OVERRUN: 2096 case XHCI_TRB_ERROR_VF_RING_FULL: 2097 return; 2098 default: 2099 if (trb_0 == 0) { 2100 return; 2101 } 2102 break; 2103 } 2104 2105 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2106 case XHCI_TRB_EVENT_TRANSFER: 2107 xhci_event_transfer(sc, trb); 2108 break; 2109 case XHCI_TRB_EVENT_CMD_COMPLETE: 2110 xhci_event_cmd(sc, trb); 2111 break; 2112 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2113 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2114 break; 2115 default: 2116 break; 2117 } 2118 } 2119 2120 static void 2121 xhci_softintr(void *v) 2122 { 2123 struct usbd_bus * const bus = v; 2124 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2125 struct xhci_ring * const er = &sc->sc_er; 2126 struct xhci_trb *trb; 2127 int i, j, k; 2128 2129 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2130 2131 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 2132 2133 i = er->xr_ep; 2134 j = er->xr_cs; 2135 2136 DPRINTFN(16, "er: xr_ep %jd xr_cs %jd", i, j, 0, 0); 2137 2138 while (1) { 2139 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2140 BUS_DMASYNC_POSTREAD); 2141 trb = &er->xr_trb[i]; 2142 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2143 2144 if (j != k) 2145 break; 2146 2147 xhci_handle_event(sc, trb); 2148 2149 i++; 2150 if (i == er->xr_ntrb) { 2151 i = 0; 2152 j ^= 1; 2153 } 2154 } 2155 2156 er->xr_ep = i; 2157 er->xr_cs = j; 2158 2159 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2160 XHCI_ERDP_LO_BUSY); 2161 2162 DPRINTFN(16, "ends", 0, 0, 0, 0); 2163 2164 return; 2165 } 2166 2167 static void 2168 xhci_poll(struct usbd_bus *bus) 2169 { 2170 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2171 2172 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2173 2174 mutex_spin_enter(&sc->sc_intr_lock); 2175 int ret = xhci_intr1(sc); 2176 if (ret) { 2177 xhci_softintr(bus); 2178 } 2179 mutex_spin_exit(&sc->sc_intr_lock); 2180 2181 return; 2182 } 2183 2184 static struct usbd_xfer * 2185 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2186 { 2187 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2188 struct usbd_xfer *xfer; 2189 2190 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2191 2192 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 2193 if (xfer != NULL) { 2194 memset(xfer, 0, sizeof(struct xhci_xfer)); 2195 #ifdef DIAGNOSTIC 2196 xfer->ux_state = XFER_BUSY; 2197 #endif 2198 } 2199 2200 return xfer; 2201 } 2202 2203 static void 2204 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2205 { 2206 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2207 2208 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2209 2210 #ifdef DIAGNOSTIC 2211 if (xfer->ux_state != XFER_BUSY) { 2212 DPRINTFN(0, "xfer=%#jx not busy, 0x%08jx", 2213 (uintptr_t)xfer, xfer->ux_state, 0, 0); 2214 } 2215 xfer->ux_state = XFER_FREE; 2216 #endif 2217 pool_cache_put(sc->sc_xferpool, xfer); 2218 } 2219 2220 static void 2221 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2222 { 2223 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2224 2225 *lock = &sc->sc_lock; 2226 } 2227 2228 extern uint32_t usb_cookie_no; 2229 2230 /* 2231 * xHCI 4.3 2232 * Called when uhub_explore finds a new device (via usbd_new_device). 2233 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2234 * This function does: 2235 * Allocate and construct dev structure of default endpoint (ep0). 2236 * Allocate and open pipe of ep0. 2237 * Enable slot and initialize slot context. 2238 * Set Address. 2239 * Read initial device descriptor. 2240 * Determine initial MaxPacketSize (mps) by speed. 2241 * Read full device descriptor. 2242 * Register this device. 2243 * Finally state of device transitions ADDRESSED. 2244 */ 2245 static usbd_status 2246 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2247 int speed, int port, struct usbd_port *up) 2248 { 2249 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2250 struct usbd_device *dev; 2251 usbd_status err; 2252 usb_device_descriptor_t *dd; 2253 struct xhci_slot *xs; 2254 uint32_t *cp; 2255 2256 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2257 DPRINTFN(4, "port %ju depth %ju speed %ju up %#jx", 2258 port, depth, speed, (uintptr_t)up); 2259 2260 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2261 dev->ud_bus = bus; 2262 dev->ud_quirks = &usbd_no_quirk; 2263 dev->ud_addr = 0; 2264 dev->ud_ddesc.bMaxPacketSize = 0; 2265 dev->ud_depth = depth; 2266 dev->ud_powersrc = up; 2267 dev->ud_myhub = up->up_parent; 2268 dev->ud_speed = speed; 2269 dev->ud_langid = USBD_NOLANG; 2270 dev->ud_cookie.cookie = ++usb_cookie_no; 2271 2272 /* Set up default endpoint handle. */ 2273 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2274 /* doesn't matter, just don't let it uninitialized */ 2275 dev->ud_ep0.ue_toggle = 0; 2276 2277 /* Set up default endpoint descriptor. */ 2278 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2279 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2280 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2281 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2282 dev->ud_ep0desc.bInterval = 0; 2283 2284 /* 4.3, 4.8.2.1 */ 2285 switch (speed) { 2286 case USB_SPEED_SUPER: 2287 case USB_SPEED_SUPER_PLUS: 2288 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2289 break; 2290 case USB_SPEED_FULL: 2291 /* XXX using 64 as initial mps of ep0 in FS */ 2292 case USB_SPEED_HIGH: 2293 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2294 break; 2295 case USB_SPEED_LOW: 2296 default: 2297 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2298 break; 2299 } 2300 2301 up->up_dev = dev; 2302 2303 /* Establish the default pipe. */ 2304 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2305 &dev->ud_pipe0); 2306 if (err) { 2307 goto bad; 2308 } 2309 2310 dd = &dev->ud_ddesc; 2311 2312 if (depth == 0 && port == 0) { 2313 KASSERT(bus->ub_devices[USB_ROOTHUB_INDEX] == NULL); 2314 bus->ub_devices[USB_ROOTHUB_INDEX] = dev; 2315 err = usbd_get_initial_ddesc(dev, dd); 2316 if (err) { 2317 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2318 goto bad; 2319 } 2320 2321 err = usbd_reload_device_desc(dev); 2322 if (err) { 2323 DPRINTFN(1, "reload desc %ju", err, 0, 0, 0); 2324 goto bad; 2325 } 2326 } else { 2327 uint8_t slot = 0; 2328 2329 /* 4.3.2 */ 2330 err = xhci_enable_slot(sc, &slot); 2331 if (err) { 2332 DPRINTFN(1, "enable slot %ju", err, 0, 0, 0); 2333 goto bad; 2334 } 2335 2336 xs = &sc->sc_slots[slot]; 2337 dev->ud_hcpriv = xs; 2338 2339 /* 4.3.3 initialize slot structure */ 2340 err = xhci_init_slot(dev, slot); 2341 if (err) { 2342 DPRINTFN(1, "init slot %ju", err, 0, 0, 0); 2343 dev->ud_hcpriv = NULL; 2344 /* 2345 * We have to disable_slot here because 2346 * xs->xs_idx == 0 when xhci_init_slot fails, 2347 * in that case usbd_remove_dev won't work. 2348 */ 2349 mutex_enter(&sc->sc_lock); 2350 xhci_disable_slot(sc, slot); 2351 mutex_exit(&sc->sc_lock); 2352 goto bad; 2353 } 2354 2355 /* 4.3.4 Address Assignment */ 2356 err = xhci_set_address(dev, slot, false); 2357 if (err) { 2358 DPRINTFN(1, "set address w/o bsr %ju", err, 0, 0, 0); 2359 goto bad; 2360 } 2361 2362 /* Allow device time to set new address */ 2363 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2364 2365 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2366 //hexdump("slot context", cp, sc->sc_ctxsz); 2367 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3])); 2368 DPRINTFN(4, "device address %ju", addr, 0, 0, 0); 2369 /* 2370 * XXX ensure we know when the hardware does something 2371 * we can't yet cope with 2372 */ 2373 KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr); 2374 dev->ud_addr = addr; 2375 2376 KASSERTMSG(bus->ub_devices[usb_addr2dindex(dev->ud_addr)] == NULL, 2377 "addr %d already allocated", dev->ud_addr); 2378 /* 2379 * The root hub is given its own slot 2380 */ 2381 bus->ub_devices[usb_addr2dindex(dev->ud_addr)] = dev; 2382 2383 err = usbd_get_initial_ddesc(dev, dd); 2384 if (err) { 2385 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2386 goto bad; 2387 } 2388 2389 /* 4.8.2.1 */ 2390 if (USB_IS_SS(speed)) { 2391 if (dd->bMaxPacketSize != 9) { 2392 printf("%s: invalid mps 2^%u for SS ep0," 2393 " using 512\n", 2394 device_xname(sc->sc_dev), 2395 dd->bMaxPacketSize); 2396 dd->bMaxPacketSize = 9; 2397 } 2398 USETW(dev->ud_ep0desc.wMaxPacketSize, 2399 (1 << dd->bMaxPacketSize)); 2400 } else 2401 USETW(dev->ud_ep0desc.wMaxPacketSize, 2402 dd->bMaxPacketSize); 2403 DPRINTFN(4, "bMaxPacketSize %ju", dd->bMaxPacketSize, 0, 0, 0); 2404 err = xhci_update_ep0_mps(sc, xs, 2405 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2406 if (err) { 2407 DPRINTFN(1, "update mps of ep0 %ju", err, 0, 0, 0); 2408 goto bad; 2409 } 2410 2411 err = usbd_reload_device_desc(dev); 2412 if (err) { 2413 DPRINTFN(1, "reload desc %ju", err, 0, 0, 0); 2414 goto bad; 2415 } 2416 } 2417 2418 DPRINTFN(1, "adding unit addr=%jd, rev=%02jx,", 2419 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2420 DPRINTFN(1, " class=%jd, subclass=%jd, protocol=%jd,", 2421 dd->bDeviceClass, dd->bDeviceSubClass, 2422 dd->bDeviceProtocol, 0); 2423 DPRINTFN(1, " mps=%jd, len=%jd, noconf=%jd, speed=%jd", 2424 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2425 dev->ud_speed); 2426 2427 usbd_get_device_strings(dev); 2428 2429 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2430 2431 if (depth == 0 && port == 0) { 2432 usbd_attach_roothub(parent, dev); 2433 DPRINTFN(1, "root hub %#jx", (uintptr_t)dev, 0, 0, 0); 2434 return USBD_NORMAL_COMPLETION; 2435 } 2436 2437 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2438 bad: 2439 if (err != USBD_NORMAL_COMPLETION) { 2440 usbd_remove_device(dev, up); 2441 } 2442 2443 return err; 2444 } 2445 2446 static usbd_status 2447 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2448 size_t ntrb, size_t align) 2449 { 2450 usbd_status err; 2451 size_t size = ntrb * XHCI_TRB_SIZE; 2452 2453 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2454 2455 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2456 if (err) 2457 return err; 2458 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2459 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2460 xr->xr_trb = xhci_ring_trbv(xr, 0); 2461 xr->xr_ntrb = ntrb; 2462 xr->is_halted = false; 2463 xhci_host_dequeue(xr); 2464 2465 return USBD_NORMAL_COMPLETION; 2466 } 2467 2468 static void 2469 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2470 { 2471 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2472 mutex_destroy(&xr->xr_lock); 2473 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2474 } 2475 2476 static void 2477 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2478 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2479 { 2480 size_t i; 2481 u_int ri; 2482 u_int cs; 2483 uint64_t parameter; 2484 uint32_t status; 2485 uint32_t control; 2486 2487 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2488 2489 KASSERTMSG(ntrbs <= XHCI_XFER_NTRB, "ntrbs %zu", ntrbs); 2490 for (i = 0; i < ntrbs; i++) { 2491 DPRINTFN(12, "xr %#jx trbs %#jx num %ju", (uintptr_t)xr, 2492 (uintptr_t)trbs, i, 0); 2493 DPRINTFN(12, " %016jx %08jx %08jx", 2494 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2495 KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2496 XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3); 2497 } 2498 2499 DPRINTFN(12, "%#jx xr_ep 0x%jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep, 2500 xr->xr_cs, 0); 2501 2502 ri = xr->xr_ep; 2503 cs = xr->xr_cs; 2504 2505 /* 2506 * Although the xhci hardware can do scatter/gather dma from 2507 * arbitrary sized buffers, there is a non-obvious restriction 2508 * that a LINK trb is only allowed at the end of a burst of 2509 * transfers - which might be 16kB. 2510 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2511 * The simple solution is not to allow a LINK trb in the middle 2512 * of anything - as here. 2513 * XXX: (dsl) There are xhci controllers out there (eg some made by 2514 * ASMedia) that seem to lock up if they process a LINK trb but 2515 * cannot process the linked-to trb yet. 2516 * The code should write the 'cycle' bit on the link trb AFTER 2517 * adding the other trb. 2518 */ 2519 u_int firstep = xr->xr_ep; 2520 u_int firstcs = xr->xr_cs; 2521 2522 for (i = 0; i < ntrbs; ) { 2523 u_int oldri = ri; 2524 u_int oldcs = cs; 2525 2526 if (ri >= (xr->xr_ntrb - 1)) { 2527 /* Put Link TD at the end of ring */ 2528 parameter = xhci_ring_trbp(xr, 0); 2529 status = 0; 2530 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2531 XHCI_TRB_3_TC_BIT; 2532 xr->xr_cookies[ri] = NULL; 2533 xr->xr_ep = 0; 2534 xr->xr_cs ^= 1; 2535 ri = xr->xr_ep; 2536 cs = xr->xr_cs; 2537 } else { 2538 parameter = trbs[i].trb_0; 2539 status = trbs[i].trb_2; 2540 control = trbs[i].trb_3; 2541 2542 xr->xr_cookies[ri] = cookie; 2543 ri++; 2544 i++; 2545 } 2546 /* 2547 * If this is a first TRB, mark it invalid to prevent 2548 * xHC from running it immediately. 2549 */ 2550 if (oldri == firstep) { 2551 if (oldcs) { 2552 control &= ~XHCI_TRB_3_CYCLE_BIT; 2553 } else { 2554 control |= XHCI_TRB_3_CYCLE_BIT; 2555 } 2556 } else { 2557 if (oldcs) { 2558 control |= XHCI_TRB_3_CYCLE_BIT; 2559 } else { 2560 control &= ~XHCI_TRB_3_CYCLE_BIT; 2561 } 2562 } 2563 xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control); 2564 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri, 2565 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2566 } 2567 2568 /* Now invert cycle bit of first TRB */ 2569 if (firstcs) { 2570 xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 2571 } else { 2572 xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 2573 } 2574 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep, 2575 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2576 2577 xr->xr_ep = ri; 2578 xr->xr_cs = cs; 2579 2580 DPRINTFN(12, "%#jx xr_ep 0x%jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep, 2581 xr->xr_cs, 0); 2582 } 2583 2584 /* 2585 * Stop execution commands, purge all commands on command ring, and 2586 * rewind dequeue pointer. 2587 */ 2588 static void 2589 xhci_abort_command(struct xhci_softc *sc) 2590 { 2591 struct xhci_ring * const cr = &sc->sc_cr; 2592 uint64_t crcr; 2593 int i; 2594 2595 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2596 DPRINTFN(14, "command %#jx timeout, aborting", 2597 sc->sc_command_addr, 0, 0, 0); 2598 2599 mutex_enter(&cr->xr_lock); 2600 2601 /* 4.6.1.2 Aborting a Command */ 2602 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2603 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2604 2605 for (i = 0; i < 500; i++) { 2606 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2607 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2608 break; 2609 usb_delay_ms(&sc->sc_bus, 1); 2610 } 2611 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2612 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2613 /* reset HC here? */ 2614 } 2615 2616 /* reset command ring dequeue pointer */ 2617 cr->xr_ep = 0; 2618 cr->xr_cs = 1; 2619 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2620 2621 mutex_exit(&cr->xr_lock); 2622 } 2623 2624 /* 2625 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2626 * Command completion is notified by cv_signal from xhci_event_cmd() 2627 * (called from xhci_softint), or timed-out. 2628 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2629 * then do_command examines it. 2630 */ 2631 static usbd_status 2632 xhci_do_command_locked(struct xhci_softc * const sc, 2633 struct xhci_trb * const trb, int timeout) 2634 { 2635 struct xhci_ring * const cr = &sc->sc_cr; 2636 usbd_status err; 2637 2638 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2639 DPRINTFN(12, "input: 0x%016jx 0x%08jx 0x%08jx", 2640 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2641 2642 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2643 KASSERT(mutex_owned(&sc->sc_lock)); 2644 2645 while (sc->sc_command_addr != 0) 2646 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 2647 2648 /* 2649 * If enqueue pointer points at last of ring, it's Link TRB, 2650 * command TRB will be stored in 0th TRB. 2651 */ 2652 if (cr->xr_ep == cr->xr_ntrb - 1) 2653 sc->sc_command_addr = xhci_ring_trbp(cr, 0); 2654 else 2655 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2656 2657 sc->sc_resultpending = true; 2658 2659 mutex_enter(&cr->xr_lock); 2660 xhci_ring_put(sc, cr, NULL, trb, 1); 2661 mutex_exit(&cr->xr_lock); 2662 2663 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2664 2665 while (sc->sc_resultpending) { 2666 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2667 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2668 xhci_abort_command(sc); 2669 err = USBD_TIMEOUT; 2670 goto timedout; 2671 } 2672 } 2673 2674 trb->trb_0 = sc->sc_result_trb.trb_0; 2675 trb->trb_2 = sc->sc_result_trb.trb_2; 2676 trb->trb_3 = sc->sc_result_trb.trb_3; 2677 2678 DPRINTFN(12, "output: 0x%016jx 0x%08jx 0x%08jx", 2679 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2680 2681 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2682 case XHCI_TRB_ERROR_SUCCESS: 2683 err = USBD_NORMAL_COMPLETION; 2684 break; 2685 default: 2686 case 192 ... 223: 2687 err = USBD_IOERROR; 2688 break; 2689 case 224 ... 255: 2690 err = USBD_NORMAL_COMPLETION; 2691 break; 2692 } 2693 2694 timedout: 2695 sc->sc_resultpending = false; 2696 sc->sc_command_addr = 0; 2697 cv_broadcast(&sc->sc_cmdbusy_cv); 2698 2699 return err; 2700 } 2701 2702 static usbd_status 2703 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2704 int timeout) 2705 { 2706 2707 mutex_enter(&sc->sc_lock); 2708 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2709 mutex_exit(&sc->sc_lock); 2710 2711 return ret; 2712 } 2713 2714 static usbd_status 2715 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2716 { 2717 struct xhci_trb trb; 2718 usbd_status err; 2719 2720 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2721 2722 trb.trb_0 = 0; 2723 trb.trb_2 = 0; 2724 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2725 2726 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2727 if (err != USBD_NORMAL_COMPLETION) { 2728 return err; 2729 } 2730 2731 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2732 2733 return err; 2734 } 2735 2736 /* 2737 * xHCI 4.6.4 2738 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2739 * All endpoints in the slot should be stopped. 2740 * Should be called with sc_lock held. 2741 */ 2742 static usbd_status 2743 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2744 { 2745 struct xhci_trb trb; 2746 struct xhci_slot *xs; 2747 usbd_status err; 2748 2749 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2750 2751 if (sc->sc_dying) 2752 return USBD_IOERROR; 2753 2754 trb.trb_0 = 0; 2755 trb.trb_2 = 0; 2756 trb.trb_3 = htole32( 2757 XHCI_TRB_3_SLOT_SET(slot) | 2758 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2759 2760 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2761 2762 if (!err) { 2763 xs = &sc->sc_slots[slot]; 2764 if (xs->xs_idx != 0) { 2765 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2766 xhci_set_dcba(sc, 0, slot); 2767 memset(xs, 0, sizeof(*xs)); 2768 } 2769 } 2770 2771 return err; 2772 } 2773 2774 /* 2775 * Set address of device and transition slot state from ENABLED to ADDRESSED 2776 * if Block Setaddress Request (BSR) is false. 2777 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2778 * see xHCI 1.1 4.5.3, 3.3.4 2779 * Should be called without sc_lock held. 2780 */ 2781 static usbd_status 2782 xhci_address_device(struct xhci_softc * const sc, 2783 uint64_t icp, uint8_t slot_id, bool bsr) 2784 { 2785 struct xhci_trb trb; 2786 usbd_status err; 2787 2788 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2789 2790 trb.trb_0 = icp; 2791 trb.trb_2 = 0; 2792 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2793 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2794 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2795 2796 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2797 2798 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2799 err = USBD_NO_ADDR; 2800 2801 return err; 2802 } 2803 2804 static usbd_status 2805 xhci_update_ep0_mps(struct xhci_softc * const sc, 2806 struct xhci_slot * const xs, u_int mps) 2807 { 2808 struct xhci_trb trb; 2809 usbd_status err; 2810 uint32_t * cp; 2811 2812 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2813 DPRINTFN(4, "slot %ju mps %ju", xs->xs_idx, mps, 0, 0); 2814 2815 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2816 cp[0] = htole32(0); 2817 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2818 2819 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2820 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2821 2822 /* sync input contexts before they are read from memory */ 2823 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2824 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2825 sc->sc_ctxsz * 4); 2826 2827 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2828 trb.trb_2 = 0; 2829 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2830 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2831 2832 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2833 return err; 2834 } 2835 2836 static void 2837 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2838 { 2839 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2840 2841 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2842 DPRINTFN(4, "dcbaa %#jx dc %016jx slot %jd", 2843 (uintptr_t)&dcbaa[si], dcba, si, 0); 2844 2845 dcbaa[si] = htole64(dcba); 2846 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2847 BUS_DMASYNC_PREWRITE); 2848 } 2849 2850 /* 2851 * Allocate device and input context DMA buffer, and 2852 * TRB DMA buffer for each endpoint. 2853 */ 2854 static usbd_status 2855 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2856 { 2857 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2858 struct xhci_slot *xs; 2859 usbd_status err; 2860 u_int dci; 2861 2862 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2863 DPRINTFN(4, "slot %ju", slot, 0, 0, 0); 2864 2865 xs = &sc->sc_slots[slot]; 2866 2867 /* allocate contexts */ 2868 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2869 &xs->xs_dc_dma); 2870 if (err) 2871 return err; 2872 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2873 2874 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2875 &xs->xs_ic_dma); 2876 if (err) 2877 goto bad1; 2878 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2879 2880 for (dci = 0; dci < 32; dci++) { 2881 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2882 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2883 if (dci == XHCI_DCI_SLOT) 2884 continue; 2885 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2886 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2887 if (err) { 2888 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2889 goto bad2; 2890 } 2891 } 2892 2893 bad2: 2894 if (err == USBD_NORMAL_COMPLETION) { 2895 xs->xs_idx = slot; 2896 } else { 2897 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2898 } 2899 2900 return err; 2901 2902 bad1: 2903 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2904 xs->xs_idx = 0; 2905 return err; 2906 } 2907 2908 static void 2909 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2910 int end_dci) 2911 { 2912 u_int dci; 2913 2914 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2915 DPRINTFN(4, "slot %ju start %ju end %ju", xs->xs_idx, start_dci, 2916 end_dci, 0); 2917 2918 for (dci = start_dci; dci < end_dci; dci++) { 2919 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2920 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2921 } 2922 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2923 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2924 xs->xs_idx = 0; 2925 } 2926 2927 /* 2928 * Setup slot context, set Device Context Base Address, and issue 2929 * Set Address Device command. 2930 */ 2931 static usbd_status 2932 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 2933 { 2934 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2935 struct xhci_slot *xs; 2936 usbd_status err; 2937 2938 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2939 DPRINTFN(4, "slot %ju bsr %ju", slot, bsr, 0, 0); 2940 2941 xs = &sc->sc_slots[slot]; 2942 2943 xhci_setup_ctx(dev->ud_pipe0); 2944 2945 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2946 sc->sc_ctxsz * 3); 2947 2948 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2949 2950 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 2951 2952 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2953 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2954 sc->sc_ctxsz * 2); 2955 2956 return err; 2957 } 2958 2959 /* 2960 * 4.8.2, 6.2.3.2 2961 * construct slot/endpoint context parameters and do syncmem 2962 */ 2963 static void 2964 xhci_setup_ctx(struct usbd_pipe *pipe) 2965 { 2966 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2967 struct usbd_device *dev = pipe->up_dev; 2968 struct xhci_slot * const xs = dev->ud_hcpriv; 2969 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2970 const u_int dci = xhci_ep_get_dci(ed); 2971 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2972 uint32_t *cp; 2973 uint16_t mps = UGETW(ed->wMaxPacketSize); 2974 uint8_t speed = dev->ud_speed; 2975 uint8_t ival = ed->bInterval; 2976 2977 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2978 DPRINTFN(4, "pipe %#jx: slot %ju dci %ju speed %ju", 2979 (uintptr_t)pipe, xs->xs_idx, dci, speed); 2980 2981 /* set up initial input control context */ 2982 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2983 cp[0] = htole32(0); 2984 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 2985 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2986 cp[7] = htole32(0); 2987 2988 /* set up input slot context */ 2989 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2990 cp[0] = 2991 XHCI_SCTX_0_CTX_NUM_SET(dci) | 2992 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 2993 cp[1] = 0; 2994 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2995 cp[3] = 0; 2996 xhci_setup_route(pipe, cp); 2997 xhci_setup_tthub(pipe, cp); 2998 2999 cp[0] = htole32(cp[0]); 3000 cp[1] = htole32(cp[1]); 3001 cp[2] = htole32(cp[2]); 3002 cp[3] = htole32(cp[3]); 3003 3004 /* set up input endpoint context */ 3005 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 3006 cp[0] = 3007 XHCI_EPCTX_0_EPSTATE_SET(0) | 3008 XHCI_EPCTX_0_MULT_SET(0) | 3009 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 3010 XHCI_EPCTX_0_LSA_SET(0) | 3011 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 3012 cp[1] = 3013 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 3014 XHCI_EPCTX_1_HID_SET(0) | 3015 XHCI_EPCTX_1_MAXB_SET(0); 3016 3017 if (xfertype != UE_ISOCHRONOUS) 3018 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 3019 3020 if (xfertype == UE_CONTROL) 3021 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 3022 else if (USB_IS_SS(speed)) 3023 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 3024 else 3025 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 3026 3027 xhci_setup_maxburst(pipe, cp); 3028 3029 switch (xfertype) { 3030 case UE_CONTROL: 3031 break; 3032 case UE_BULK: 3033 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 3034 break; 3035 case UE_INTERRUPT: 3036 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3037 ival = pipe->up_interval; 3038 3039 ival = xhci_bival2ival(ival, speed); 3040 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3041 break; 3042 case UE_ISOCHRONOUS: 3043 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3044 ival = pipe->up_interval; 3045 3046 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 3047 if (speed == USB_SPEED_FULL) 3048 ival += 3; /* 1ms -> 125us */ 3049 ival--; 3050 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3051 break; 3052 default: 3053 break; 3054 } 3055 DPRINTFN(4, "setting ival %ju MaxBurst %#jx", 3056 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 3057 3058 /* rewind TR dequeue pointer in xHC */ 3059 /* can't use xhci_ep_get_dci() yet? */ 3060 *(uint64_t *)(&cp[2]) = htole64( 3061 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 3062 XHCI_EPCTX_2_DCS_SET(1)); 3063 3064 cp[0] = htole32(cp[0]); 3065 cp[1] = htole32(cp[1]); 3066 cp[4] = htole32(cp[4]); 3067 3068 /* rewind TR dequeue pointer in driver */ 3069 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 3070 mutex_enter(&xr->xr_lock); 3071 xhci_host_dequeue(xr); 3072 mutex_exit(&xr->xr_lock); 3073 3074 /* sync input contexts before they are read from memory */ 3075 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3076 } 3077 3078 /* 3079 * Setup route string and roothub port of given device for slot context 3080 */ 3081 static void 3082 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 3083 { 3084 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3085 struct usbd_device *dev = pipe->up_dev; 3086 struct usbd_port *up = dev->ud_powersrc; 3087 struct usbd_device *hub; 3088 struct usbd_device *adev; 3089 uint8_t rhport = 0; 3090 uint32_t route = 0; 3091 3092 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3093 3094 /* Locate root hub port and Determine route string */ 3095 /* 4.3.3 route string does not include roothub port */ 3096 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 3097 uint32_t dep; 3098 3099 DPRINTFN(4, "hub %#jx depth %jd upport %jp upportno %jd", 3100 (uintptr_t)hub, hub->ud_depth, (uintptr_t)hub->ud_powersrc, 3101 hub->ud_powersrc ? (uintptr_t)hub->ud_powersrc->up_portno : 3102 -1); 3103 3104 if (hub->ud_powersrc == NULL) 3105 break; 3106 dep = hub->ud_depth; 3107 if (dep == 0) 3108 break; 3109 rhport = hub->ud_powersrc->up_portno; 3110 if (dep > USB_HUB_MAX_DEPTH) 3111 continue; 3112 3113 route |= 3114 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 3115 << ((dep - 1) * 4); 3116 } 3117 route = route >> 4; 3118 size_t bn = hub == sc->sc_bus.ub_roothub ? 0 : 1; 3119 3120 /* Locate port on upstream high speed hub */ 3121 for (adev = dev, hub = up->up_parent; 3122 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 3123 adev = hub, hub = hub->ud_myhub) 3124 ; 3125 if (hub) { 3126 int p; 3127 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 3128 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 3129 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 3130 goto found; 3131 } 3132 } 3133 panic("%s: cannot find HS port", __func__); 3134 found: 3135 DPRINTFN(4, "high speed port %jd", p, 0, 0, 0); 3136 } else { 3137 dev->ud_myhsport = NULL; 3138 } 3139 3140 const size_t ctlrport = xhci_rhport2ctlrport(sc, bn, rhport); 3141 3142 DPRINTFN(4, "rhport %ju ctlrport %ju Route %05jx hub %#jx", rhport, 3143 ctlrport, route, (uintptr_t)hub); 3144 3145 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 3146 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(ctlrport); 3147 } 3148 3149 /* 3150 * Setup whether device is hub, whether device uses MTT, and 3151 * TT informations if it uses MTT. 3152 */ 3153 static void 3154 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 3155 { 3156 struct usbd_device *dev = pipe->up_dev; 3157 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 3158 uint32_t speed = dev->ud_speed; 3159 uint8_t tthubslot, ttportnum; 3160 bool ishub; 3161 bool usemtt; 3162 3163 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3164 3165 /* 3166 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 3167 * tthubslot: 3168 * This is the slot ID of parent HS hub 3169 * if LS/FS device is connected && connected through HS hub. 3170 * This is 0 if device is not LS/FS device || 3171 * parent hub is not HS hub || 3172 * attached to root hub. 3173 * ttportnum: 3174 * This is the downstream facing port of parent HS hub 3175 * if LS/FS device is connected. 3176 * This is 0 if device is not LS/FS device || 3177 * parent hub is not HS hub || 3178 * attached to root hub. 3179 */ 3180 if (dev->ud_myhsport != NULL && 3181 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3182 (dev->ud_myhub != NULL && 3183 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3184 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 3185 ttportnum = dev->ud_myhsport->up_portno; 3186 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 3187 } else { 3188 ttportnum = 0; 3189 tthubslot = 0; 3190 } 3191 DPRINTFN(4, "myhsport %#jx ttportnum=%jd tthubslot=%jd", 3192 (uintptr_t)dev->ud_myhsport, ttportnum, tthubslot, 0); 3193 3194 /* ishub is valid after reading UDESC_DEVICE */ 3195 ishub = (dd->bDeviceClass == UDCLASS_HUB); 3196 3197 /* dev->ud_hub is valid after reading UDESC_HUB */ 3198 if (ishub && dev->ud_hub) { 3199 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 3200 uint8_t ttt = 3201 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 3202 3203 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 3204 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 3205 DPRINTFN(4, "nports=%jd ttt=%jd", hd->bNbrPorts, ttt, 0, 0); 3206 } 3207 3208 #define IS_TTHUB(dd) \ 3209 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 3210 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 3211 3212 /* 3213 * MTT flag is set if 3214 * 1. this is HS hub && MTT is enabled 3215 * or 3216 * 2. this is not hub && this is LS or FS device && 3217 * MTT of parent HS hub (and its parent, too) is enabled 3218 */ 3219 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 3220 usemtt = true; 3221 else if (!ishub && 3222 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 3223 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3224 (dev->ud_myhub != NULL && 3225 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3226 dev->ud_myhsport != NULL && 3227 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 3228 usemtt = true; 3229 else 3230 usemtt = false; 3231 DPRINTFN(4, "class %ju proto %ju ishub %jd usemtt %jd", 3232 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 3233 3234 #undef IS_TTHUB 3235 3236 cp[0] |= 3237 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 3238 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 3239 cp[2] |= 3240 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 3241 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 3242 } 3243 3244 /* set up params for periodic endpoint */ 3245 static void 3246 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 3247 { 3248 struct usbd_device *dev = pipe->up_dev; 3249 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3250 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3251 usbd_desc_iter_t iter; 3252 const usb_cdc_descriptor_t *cdcd; 3253 uint32_t maxb = 0; 3254 uint16_t mps = UGETW(ed->wMaxPacketSize); 3255 uint8_t speed = dev->ud_speed; 3256 uint8_t ep; 3257 3258 /* config desc is NULL when opening ep0 */ 3259 if (dev == NULL || dev->ud_cdesc == NULL) 3260 goto no_cdcd; 3261 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 3262 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 3263 if (cdcd == NULL) 3264 goto no_cdcd; 3265 usb_desc_iter_init(dev, &iter); 3266 iter.cur = (const void *)cdcd; 3267 3268 /* find endpoint_ss_comp desc for ep of this pipe */ 3269 for (ep = 0;;) { 3270 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 3271 if (cdcd == NULL) 3272 break; 3273 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 3274 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 3275 bEndpointAddress; 3276 if (UE_GET_ADDR(ep) == 3277 UE_GET_ADDR(ed->bEndpointAddress)) { 3278 cdcd = (const usb_cdc_descriptor_t *) 3279 usb_desc_iter_next(&iter); 3280 break; 3281 } 3282 ep = 0; 3283 } 3284 } 3285 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 3286 const usb_endpoint_ss_comp_descriptor_t * esscd = 3287 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3288 maxb = esscd->bMaxBurst; 3289 } 3290 3291 no_cdcd: 3292 /* 6.2.3.4, 4.8.2.4 */ 3293 if (USB_IS_SS(speed)) { 3294 /* USB 3.1 9.6.6 */ 3295 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3296 /* USB 3.1 9.6.7 */ 3297 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3298 #ifdef notyet 3299 if (xfertype == UE_ISOCHRONOUS) { 3300 } 3301 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3302 /* use ESIT */ 3303 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3304 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3305 3306 /* XXX if LEC = 1, set ESIT instead */ 3307 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3308 } else { 3309 /* use ival */ 3310 } 3311 #endif 3312 } else { 3313 /* USB 2.0 9.6.6 */ 3314 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3315 3316 /* 6.2.3.4 */ 3317 if (speed == USB_SPEED_HIGH && 3318 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3319 maxb = UE_GET_TRANS(mps); 3320 } else { 3321 /* LS/FS or HS CTRL or HS BULK */ 3322 maxb = 0; 3323 } 3324 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3325 } 3326 } 3327 3328 /* 3329 * Convert endpoint bInterval value to endpoint context interval value 3330 * for Interrupt pipe. 3331 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3332 */ 3333 static uint32_t 3334 xhci_bival2ival(uint32_t ival, uint32_t speed) 3335 { 3336 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3337 int i; 3338 3339 /* 3340 * round ival down to "the nearest base 2 multiple of 3341 * bInterval * 8". 3342 * bInterval is at most 255 as its type is uByte. 3343 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3344 */ 3345 for (i = 10; i > 0; i--) { 3346 if ((ival * 8) >= (1 << i)) 3347 break; 3348 } 3349 ival = i; 3350 } else { 3351 /* Interval = bInterval-1 for SS/HS */ 3352 ival--; 3353 } 3354 3355 return ival; 3356 } 3357 3358 /* ----- */ 3359 3360 static void 3361 xhci_noop(struct usbd_pipe *pipe) 3362 { 3363 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3364 } 3365 3366 /* 3367 * Process root hub request. 3368 */ 3369 static int 3370 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3371 void *buf, int buflen) 3372 { 3373 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3374 usb_port_status_t ps; 3375 int l, totlen = 0; 3376 uint16_t len, value, index; 3377 int port, i; 3378 uint32_t v; 3379 3380 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3381 3382 if (sc->sc_dying) 3383 return -1; 3384 3385 size_t bn = bus == &sc->sc_bus ? 0 : 1; 3386 3387 len = UGETW(req->wLength); 3388 value = UGETW(req->wValue); 3389 index = UGETW(req->wIndex); 3390 3391 DPRINTFN(12, "rhreq: %04jx %04jx %04jx %04jx", 3392 req->bmRequestType | (req->bRequest << 8), value, index, len); 3393 3394 #define C(x,y) ((x) | ((y) << 8)) 3395 switch (C(req->bRequest, req->bmRequestType)) { 3396 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3397 DPRINTFN(8, "getdesc: wValue=0x%04jx", value, 0, 0, 0); 3398 if (len == 0) 3399 break; 3400 switch (value) { 3401 case C(0, UDESC_DEVICE): { 3402 usb_device_descriptor_t devd; 3403 totlen = min(buflen, sizeof(devd)); 3404 memcpy(&devd, buf, totlen); 3405 USETW(devd.idVendor, sc->sc_id_vendor); 3406 memcpy(buf, &devd, totlen); 3407 break; 3408 } 3409 #define sd ((usb_string_descriptor_t *)buf) 3410 case C(1, UDESC_STRING): 3411 /* Vendor */ 3412 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3413 break; 3414 case C(2, UDESC_STRING): 3415 /* Product */ 3416 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3417 break; 3418 #undef sd 3419 default: 3420 /* default from usbroothub */ 3421 return buflen; 3422 } 3423 break; 3424 3425 /* Hub requests */ 3426 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3427 break; 3428 /* Clear Port Feature request */ 3429 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): { 3430 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3431 3432 DPRINTFN(4, "UR_CLEAR_PORT_FEAT bp=%jd feat=%jd bus=%jd cp=%jd", 3433 index, value, bn, cp); 3434 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3435 return -1; 3436 } 3437 port = XHCI_PORTSC(cp); 3438 v = xhci_op_read_4(sc, port); 3439 DPRINTFN(4, "portsc=0x%08jx", v, 0, 0, 0); 3440 v &= ~XHCI_PS_CLEAR; 3441 switch (value) { 3442 case UHF_PORT_ENABLE: 3443 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3444 break; 3445 case UHF_PORT_SUSPEND: 3446 return -1; 3447 case UHF_PORT_POWER: 3448 break; 3449 case UHF_PORT_TEST: 3450 case UHF_PORT_INDICATOR: 3451 return -1; 3452 case UHF_C_PORT_CONNECTION: 3453 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3454 break; 3455 case UHF_C_PORT_ENABLE: 3456 case UHF_C_PORT_SUSPEND: 3457 case UHF_C_PORT_OVER_CURRENT: 3458 return -1; 3459 case UHF_C_BH_PORT_RESET: 3460 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3461 break; 3462 case UHF_C_PORT_RESET: 3463 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3464 break; 3465 case UHF_C_PORT_LINK_STATE: 3466 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3467 break; 3468 case UHF_C_PORT_CONFIG_ERROR: 3469 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3470 break; 3471 default: 3472 return -1; 3473 } 3474 break; 3475 } 3476 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3477 if (len == 0) 3478 break; 3479 if ((value & 0xff) != 0) { 3480 return -1; 3481 } 3482 usb_hub_descriptor_t hubd; 3483 3484 totlen = min(buflen, sizeof(hubd)); 3485 memcpy(&hubd, buf, totlen); 3486 hubd.bNbrPorts = sc->sc_rhportcount[bn]; 3487 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3488 hubd.bPwrOn2PwrGood = 200; 3489 for (i = 0, l = sc->sc_rhportcount[bn]; l > 0; i++, l -= 8) { 3490 /* XXX can't find out? */ 3491 hubd.DeviceRemovable[i++] = 0; 3492 } 3493 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3494 totlen = min(totlen, hubd.bDescLength); 3495 memcpy(buf, &hubd, totlen); 3496 break; 3497 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3498 if (len != 4) { 3499 return -1; 3500 } 3501 memset(buf, 0, len); /* ? XXX */ 3502 totlen = len; 3503 break; 3504 /* Get Port Status request */ 3505 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): { 3506 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3507 3508 DPRINTFN(8, "get port status bn=%jd i=%jd cp=%ju", 3509 bn, index, cp, 0); 3510 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3511 return -1; 3512 } 3513 if (len != 4) { 3514 return -1; 3515 } 3516 v = xhci_op_read_4(sc, XHCI_PORTSC(cp)); 3517 DPRINTFN(4, "getrhportsc %jd %08jx", cp, v, 0, 0); 3518 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3519 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3520 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3521 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3522 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3523 if (v & XHCI_PS_PR) i |= UPS_RESET; 3524 if (v & XHCI_PS_PP) { 3525 if (i & UPS_OTHER_SPEED) 3526 i |= UPS_PORT_POWER_SS; 3527 else 3528 i |= UPS_PORT_POWER; 3529 } 3530 if (i & UPS_OTHER_SPEED) 3531 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3532 if (sc->sc_vendor_port_status) 3533 i = sc->sc_vendor_port_status(sc, v, i); 3534 USETW(ps.wPortStatus, i); 3535 i = 0; 3536 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3537 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3538 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3539 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3540 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3541 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3542 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3543 USETW(ps.wPortChange, i); 3544 totlen = min(len, sizeof(ps)); 3545 memcpy(buf, &ps, totlen); 3546 break; 3547 } 3548 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3549 return -1; 3550 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3551 break; 3552 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3553 break; 3554 /* Set Port Feature request */ 3555 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3556 int optval = (index >> 8) & 0xff; 3557 index &= 0xff; 3558 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3559 return -1; 3560 } 3561 3562 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3563 3564 port = XHCI_PORTSC(cp); 3565 v = xhci_op_read_4(sc, port); 3566 DPRINTFN(4, "index %jd cp %jd portsc=0x%08jx", index, cp, v, 0); 3567 v &= ~XHCI_PS_CLEAR; 3568 switch (value) { 3569 case UHF_PORT_ENABLE: 3570 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3571 break; 3572 case UHF_PORT_SUSPEND: 3573 /* XXX suspend */ 3574 break; 3575 case UHF_PORT_RESET: 3576 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3577 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3578 /* Wait for reset to complete. */ 3579 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3580 if (sc->sc_dying) { 3581 return -1; 3582 } 3583 v = xhci_op_read_4(sc, port); 3584 if (v & XHCI_PS_PR) { 3585 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3586 usb_delay_ms(&sc->sc_bus, 10); 3587 /* XXX */ 3588 } 3589 break; 3590 case UHF_PORT_POWER: 3591 /* XXX power control */ 3592 break; 3593 /* XXX more */ 3594 case UHF_C_PORT_RESET: 3595 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3596 break; 3597 case UHF_PORT_U1_TIMEOUT: 3598 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3599 return -1; 3600 } 3601 port = XHCI_PORTPMSC(cp); 3602 v = xhci_op_read_4(sc, port); 3603 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 3604 index, cp, v, 0); 3605 v &= ~XHCI_PM3_U1TO_SET(0xff); 3606 v |= XHCI_PM3_U1TO_SET(optval); 3607 xhci_op_write_4(sc, port, v); 3608 break; 3609 case UHF_PORT_U2_TIMEOUT: 3610 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3611 return -1; 3612 } 3613 port = XHCI_PORTPMSC(cp); 3614 v = xhci_op_read_4(sc, port); 3615 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 3616 index, cp, v, 0); 3617 v &= ~XHCI_PM3_U2TO_SET(0xff); 3618 v |= XHCI_PM3_U2TO_SET(optval); 3619 xhci_op_write_4(sc, port, v); 3620 break; 3621 default: 3622 return -1; 3623 } 3624 } 3625 break; 3626 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3627 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3628 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3629 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3630 break; 3631 default: 3632 /* default from usbroothub */ 3633 return buflen; 3634 } 3635 3636 return totlen; 3637 } 3638 3639 /* root hub interrupt */ 3640 3641 static usbd_status 3642 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3643 { 3644 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3645 usbd_status err; 3646 3647 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3648 3649 /* Insert last in queue. */ 3650 mutex_enter(&sc->sc_lock); 3651 err = usb_insert_transfer(xfer); 3652 mutex_exit(&sc->sc_lock); 3653 if (err) 3654 return err; 3655 3656 /* Pipe isn't running, start first */ 3657 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3658 } 3659 3660 /* Wait for roothub port status/change */ 3661 static usbd_status 3662 xhci_root_intr_start(struct usbd_xfer *xfer) 3663 { 3664 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3665 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3666 3667 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3668 3669 if (sc->sc_dying) 3670 return USBD_IOERROR; 3671 3672 mutex_enter(&sc->sc_lock); 3673 sc->sc_intrxfer[bn] = xfer; 3674 mutex_exit(&sc->sc_lock); 3675 3676 return USBD_IN_PROGRESS; 3677 } 3678 3679 static void 3680 xhci_root_intr_abort(struct usbd_xfer *xfer) 3681 { 3682 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3683 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3684 3685 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3686 3687 KASSERT(mutex_owned(&sc->sc_lock)); 3688 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3689 3690 sc->sc_intrxfer[bn] = NULL; 3691 3692 xfer->ux_status = USBD_CANCELLED; 3693 usb_transfer_complete(xfer); 3694 } 3695 3696 static void 3697 xhci_root_intr_close(struct usbd_pipe *pipe) 3698 { 3699 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3700 const struct usbd_xfer *xfer = pipe->up_intrxfer; 3701 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3702 3703 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3704 3705 KASSERT(mutex_owned(&sc->sc_lock)); 3706 3707 sc->sc_intrxfer[bn] = NULL; 3708 } 3709 3710 static void 3711 xhci_root_intr_done(struct usbd_xfer *xfer) 3712 { 3713 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3714 3715 } 3716 3717 /* -------------- */ 3718 /* device control */ 3719 3720 static usbd_status 3721 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3722 { 3723 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3724 usbd_status err; 3725 3726 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3727 3728 /* Insert last in queue. */ 3729 mutex_enter(&sc->sc_lock); 3730 err = usb_insert_transfer(xfer); 3731 mutex_exit(&sc->sc_lock); 3732 if (err) 3733 return err; 3734 3735 /* Pipe isn't running, start first */ 3736 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3737 } 3738 3739 static usbd_status 3740 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3741 { 3742 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3743 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3744 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3745 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3746 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3747 usb_device_request_t * const req = &xfer->ux_request; 3748 const int isread = usbd_xfer_isread(xfer); 3749 const uint32_t len = UGETW(req->wLength); 3750 usb_dma_t * const dma = &xfer->ux_dmabuf; 3751 uint64_t parameter; 3752 uint32_t status; 3753 uint32_t control; 3754 u_int i; 3755 3756 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3757 DPRINTFN(12, "req: %04jx %04jx %04jx %04jx", 3758 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3759 UGETW(req->wIndex), UGETW(req->wLength)); 3760 3761 /* we rely on the bottom bits for extra info */ 3762 KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx", 3763 (uintptr_t) xfer); 3764 3765 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3766 3767 i = 0; 3768 3769 /* setup phase */ 3770 memcpy(¶meter, req, sizeof(parameter)); 3771 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3772 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3773 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3774 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3775 XHCI_TRB_3_IDT_BIT; 3776 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3777 3778 if (len != 0) { 3779 /* data phase */ 3780 parameter = DMAADDR(dma, 0); 3781 KASSERTMSG(len <= 0x10000, "len %d", len); 3782 status = XHCI_TRB_2_IRQ_SET(0) | 3783 XHCI_TRB_2_TDSZ_SET(1) | 3784 XHCI_TRB_2_BYTES_SET(len); 3785 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3786 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3787 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3788 XHCI_TRB_3_IOC_BIT; 3789 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3790 } 3791 3792 parameter = 0; 3793 status = XHCI_TRB_2_IRQ_SET(0); 3794 /* the status stage has inverted direction */ 3795 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3796 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3797 XHCI_TRB_3_IOC_BIT; 3798 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3799 3800 mutex_enter(&tr->xr_lock); 3801 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3802 mutex_exit(&tr->xr_lock); 3803 3804 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3805 3806 if (xfer->ux_timeout && !xhci_polling_p(sc)) { 3807 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3808 xhci_timeout, xfer); 3809 } 3810 3811 return USBD_IN_PROGRESS; 3812 } 3813 3814 static void 3815 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3816 { 3817 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3818 usb_device_request_t *req = &xfer->ux_request; 3819 int len = UGETW(req->wLength); 3820 int rd = req->bmRequestType & UT_READ; 3821 3822 if (len) 3823 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3824 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3825 } 3826 3827 static void 3828 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3829 { 3830 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3831 3832 xhci_abort_xfer(xfer, USBD_CANCELLED); 3833 } 3834 3835 static void 3836 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3837 { 3838 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3839 3840 xhci_close_pipe(pipe); 3841 } 3842 3843 /* ------------------ */ 3844 /* device isochronous */ 3845 3846 /* ----------- */ 3847 /* device bulk */ 3848 3849 static usbd_status 3850 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3851 { 3852 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3853 usbd_status err; 3854 3855 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3856 3857 /* Insert last in queue. */ 3858 mutex_enter(&sc->sc_lock); 3859 err = usb_insert_transfer(xfer); 3860 mutex_exit(&sc->sc_lock); 3861 if (err) 3862 return err; 3863 3864 /* 3865 * Pipe isn't running (otherwise err would be USBD_INPROG), 3866 * so start it first. 3867 */ 3868 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3869 } 3870 3871 static usbd_status 3872 xhci_device_bulk_start(struct usbd_xfer *xfer) 3873 { 3874 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3875 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3876 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3877 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3878 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3879 const uint32_t len = xfer->ux_length; 3880 usb_dma_t * const dma = &xfer->ux_dmabuf; 3881 uint64_t parameter; 3882 uint32_t status; 3883 uint32_t control; 3884 u_int i = 0; 3885 3886 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3887 3888 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 3889 0); 3890 3891 if (sc->sc_dying) 3892 return USBD_IOERROR; 3893 3894 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3895 3896 parameter = DMAADDR(dma, 0); 3897 /* 3898 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3899 * If the user supplied buffer crosses such a boundary then 2 3900 * (or more) TRB should be used. 3901 * If multiple TRB are used the td_size field must be set correctly. 3902 * For v1.0 devices (like ivy bridge) this is the number of usb data 3903 * blocks needed to complete the transfer. 3904 * Setting it to 1 in the last TRB causes an extra zero-length 3905 * data block be sent. 3906 * The earlier documentation differs, I don't know how it behaves. 3907 */ 3908 KASSERTMSG(len <= 0x10000, "len %d", len); 3909 status = XHCI_TRB_2_IRQ_SET(0) | 3910 XHCI_TRB_2_TDSZ_SET(1) | 3911 XHCI_TRB_2_BYTES_SET(len); 3912 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3913 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3914 XHCI_TRB_3_IOC_BIT; 3915 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3916 3917 mutex_enter(&tr->xr_lock); 3918 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3919 mutex_exit(&tr->xr_lock); 3920 3921 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3922 3923 if (xfer->ux_timeout && !xhci_polling_p(sc)) { 3924 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3925 xhci_timeout, xfer); 3926 } 3927 3928 return USBD_IN_PROGRESS; 3929 } 3930 3931 static void 3932 xhci_device_bulk_done(struct usbd_xfer *xfer) 3933 { 3934 #ifdef USB_DEBUG 3935 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3936 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3937 #endif 3938 const int isread = usbd_xfer_isread(xfer); 3939 3940 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3941 3942 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 3943 0); 3944 3945 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3946 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3947 } 3948 3949 static void 3950 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3951 { 3952 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3953 3954 xhci_abort_xfer(xfer, USBD_CANCELLED); 3955 } 3956 3957 static void 3958 xhci_device_bulk_close(struct usbd_pipe *pipe) 3959 { 3960 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3961 3962 xhci_close_pipe(pipe); 3963 } 3964 3965 /* ---------------- */ 3966 /* device interrupt */ 3967 3968 static usbd_status 3969 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3970 { 3971 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3972 usbd_status err; 3973 3974 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3975 3976 /* Insert last in queue. */ 3977 mutex_enter(&sc->sc_lock); 3978 err = usb_insert_transfer(xfer); 3979 mutex_exit(&sc->sc_lock); 3980 if (err) 3981 return err; 3982 3983 /* 3984 * Pipe isn't running (otherwise err would be USBD_INPROG), 3985 * so start it first. 3986 */ 3987 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3988 } 3989 3990 static usbd_status 3991 xhci_device_intr_start(struct usbd_xfer *xfer) 3992 { 3993 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3994 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3995 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3996 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3997 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3998 const uint32_t len = xfer->ux_length; 3999 usb_dma_t * const dma = &xfer->ux_dmabuf; 4000 uint64_t parameter; 4001 uint32_t status; 4002 uint32_t control; 4003 u_int i = 0; 4004 4005 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4006 4007 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 4008 0); 4009 4010 if (sc->sc_dying) 4011 return USBD_IOERROR; 4012 4013 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 4014 4015 parameter = DMAADDR(dma, 0); 4016 KASSERTMSG(len <= 0x10000, "len %d", len); 4017 status = XHCI_TRB_2_IRQ_SET(0) | 4018 XHCI_TRB_2_TDSZ_SET(1) | 4019 XHCI_TRB_2_BYTES_SET(len); 4020 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 4021 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 4022 XHCI_TRB_3_IOC_BIT; 4023 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 4024 4025 mutex_enter(&tr->xr_lock); 4026 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 4027 mutex_exit(&tr->xr_lock); 4028 4029 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4030 4031 if (xfer->ux_timeout && !xhci_polling_p(sc)) { 4032 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4033 xhci_timeout, xfer); 4034 } 4035 4036 return USBD_IN_PROGRESS; 4037 } 4038 4039 static void 4040 xhci_device_intr_done(struct usbd_xfer *xfer) 4041 { 4042 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4043 #ifdef USB_DEBUG 4044 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4045 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4046 #endif 4047 const int isread = usbd_xfer_isread(xfer); 4048 4049 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4050 4051 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 4052 0); 4053 4054 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 4055 4056 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4057 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4058 } 4059 4060 static void 4061 xhci_device_intr_abort(struct usbd_xfer *xfer) 4062 { 4063 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4064 4065 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4066 4067 KASSERT(mutex_owned(&sc->sc_lock)); 4068 DPRINTFN(15, "%#jx", (uintptr_t)xfer, 0, 0, 0); 4069 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4070 xhci_abort_xfer(xfer, USBD_CANCELLED); 4071 } 4072 4073 static void 4074 xhci_device_intr_close(struct usbd_pipe *pipe) 4075 { 4076 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 4077 4078 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4079 DPRINTFN(15, "%#jx", (uintptr_t)pipe, 0, 0, 0); 4080 4081 xhci_close_pipe(pipe); 4082 } 4083 4084 /* ------------ */ 4085 4086 static void 4087 xhci_timeout(void *addr) 4088 { 4089 struct xhci_xfer * const xx = addr; 4090 struct usbd_xfer * const xfer = &xx->xx_xfer; 4091 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4092 4093 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4094 4095 if (sc->sc_dying) { 4096 return; 4097 } 4098 4099 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 4100 USB_TASKQ_MPSAFE); 4101 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 4102 USB_TASKQ_HC); 4103 } 4104 4105 static void 4106 xhci_timeout_task(void *addr) 4107 { 4108 struct usbd_xfer * const xfer = addr; 4109 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4110 4111 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4112 4113 mutex_enter(&sc->sc_lock); 4114 xhci_abort_xfer(xfer, USBD_TIMEOUT); 4115 mutex_exit(&sc->sc_lock); 4116 } 4117
Indexes created Wed Oct 01 18:09:54 GMT 2025