xhci.c revision 1.28.2.10
1 /* $NetBSD: xhci.c,v 1.28.2.10 2014/12/03 22:40:55 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.28.2.10 2014/12/03 22:40:55 skrll Exp $"); 31 32 #include "opt_usb.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/kmem.h> 38 #include <sys/device.h> 39 #include <sys/select.h> 40 #include <sys/proc.h> 41 #include <sys/queue.h> 42 #include <sys/mutex.h> 43 #include <sys/condvar.h> 44 #include <sys/bus.h> 45 #include <sys/cpu.h> 46 #include <sys/sysctl.h> 47 48 #include <machine/endian.h> 49 50 #include <dev/usb/usb.h> 51 #include <dev/usb/usbdi.h> 52 #include <dev/usb/usbdivar.h> 53 #include <dev/usb/usbhist.h> 54 #include <dev/usb/usb_mem.h> 55 #include <dev/usb/usb_quirks.h> 56 57 #include <dev/usb/xhcireg.h> 58 #include <dev/usb/xhcivar.h> 59 #include <dev/usb/usbroothub_subr.h> 60 61 62 #ifdef USB_DEBUG 63 #ifndef XHCI_DEBUG 64 #define xhcidebug 0 65 #else 66 static int xhcidebug = 0; 67 68 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 69 { 70 int err; 71 const struct sysctlnode *rnode; 72 const struct sysctlnode *cnode; 73 74 err = sysctl_createv(clog, 0, NULL, &rnode, 75 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 76 SYSCTL_DESCR("xhci global controls"), 77 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 78 79 if (err) 80 goto fail; 81 82 /* control debugging printfs */ 83 err = sysctl_createv(clog, 0, &rnode, &cnode, 84 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 85 "debug", SYSCTL_DESCR("Enable debugging output"), 86 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 87 if (err) 88 goto fail; 89 90 return; 91 fail: 92 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 93 } 94 95 #endif /* XHCI_DEBUG */ 96 #endif /* USB_DEBUG */ 97 98 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 99 #define XHCIHIST_FUNC() USBHIST_FUNC() 100 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 101 102 #define XHCI_DCI_SLOT 0 103 #define XHCI_DCI_EP_CONTROL 1 104 105 #define XHCI_ICI_INPUT_CONTROL 0 106 107 struct xhci_pipe { 108 struct usbd_pipe xp_pipe; 109 }; 110 111 #define XHCI_INTR_ENDPT 1 112 #define XHCI_COMMAND_RING_TRBS 256 113 #define XHCI_EVENT_RING_TRBS 256 114 #define XHCI_EVENT_RING_SEGMENTS 1 115 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 116 117 static usbd_status xhci_open(usbd_pipe_handle); 118 static int xhci_intr1(struct xhci_softc * const); 119 static void xhci_softintr(void *); 120 static void xhci_poll(struct usbd_bus *); 121 static usbd_xfer_handle xhci_allocx(struct usbd_bus *); 122 static void xhci_freex(struct usbd_bus *, usbd_xfer_handle); 123 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 124 static usbd_status xhci_new_device(device_t, usbd_bus_handle, int, int, int, 125 struct usbd_port *); 126 127 static usbd_status xhci_configure_endpoint(usbd_pipe_handle); 128 static usbd_status xhci_unconfigure_endpoint(usbd_pipe_handle); 129 static usbd_status xhci_reset_endpoint(usbd_pipe_handle); 130 //static usbd_status xhci_stop_endpoint(usbd_pipe_handle); 131 132 static usbd_status xhci_set_dequeue(usbd_pipe_handle); 133 134 static usbd_status xhci_do_command(struct xhci_softc * const, 135 struct xhci_trb * const, int); 136 static usbd_status xhci_init_slot(struct xhci_softc * const, uint32_t, 137 int, int, int, int); 138 static usbd_status xhci_enable_slot(struct xhci_softc * const, 139 uint8_t * const); 140 static usbd_status xhci_address_device(struct xhci_softc * const, 141 uint64_t, uint8_t, bool); 142 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 143 struct xhci_slot * const, u_int); 144 static usbd_status xhci_ring_init(struct xhci_softc * const, 145 struct xhci_ring * const, size_t, size_t); 146 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 147 148 static void xhci_noop(usbd_pipe_handle); 149 150 static usbd_status xhci_root_ctrl_transfer(usbd_xfer_handle); 151 static usbd_status xhci_root_ctrl_start(usbd_xfer_handle); 152 static void xhci_root_ctrl_abort(usbd_xfer_handle); 153 static void xhci_root_ctrl_close(usbd_pipe_handle); 154 static void xhci_root_ctrl_done(usbd_xfer_handle); 155 156 static usbd_status xhci_root_intr_transfer(usbd_xfer_handle); 157 static usbd_status xhci_root_intr_start(usbd_xfer_handle); 158 static void xhci_root_intr_abort(usbd_xfer_handle); 159 static void xhci_root_intr_close(usbd_pipe_handle); 160 static void xhci_root_intr_done(usbd_xfer_handle); 161 162 static usbd_status xhci_device_ctrl_transfer(usbd_xfer_handle); 163 static usbd_status xhci_device_ctrl_start(usbd_xfer_handle); 164 static void xhci_device_ctrl_abort(usbd_xfer_handle); 165 static void xhci_device_ctrl_close(usbd_pipe_handle); 166 static void xhci_device_ctrl_done(usbd_xfer_handle); 167 168 static usbd_status xhci_device_intr_transfer(usbd_xfer_handle); 169 static usbd_status xhci_device_intr_start(usbd_xfer_handle); 170 static void xhci_device_intr_abort(usbd_xfer_handle); 171 static void xhci_device_intr_close(usbd_pipe_handle); 172 static void xhci_device_intr_done(usbd_xfer_handle); 173 174 static usbd_status xhci_device_bulk_transfer(usbd_xfer_handle); 175 static usbd_status xhci_device_bulk_start(usbd_xfer_handle); 176 static void xhci_device_bulk_abort(usbd_xfer_handle); 177 static void xhci_device_bulk_close(usbd_pipe_handle); 178 static void xhci_device_bulk_done(usbd_xfer_handle); 179 180 static void xhci_timeout(void *); 181 static void xhci_timeout_task(void *); 182 183 static const struct usbd_bus_methods xhci_bus_methods = { 184 .ubm_open = xhci_open, 185 .ubm_softint = xhci_softintr, 186 .ubm_dopoll = xhci_poll, 187 .ubm_allocx = xhci_allocx, 188 .ubm_freex = xhci_freex, 189 .ubm_getlock = xhci_get_lock, 190 .ubm_newdev = xhci_new_device, 191 }; 192 193 static const struct usbd_pipe_methods xhci_root_ctrl_methods = { 194 .upm_transfer = xhci_root_ctrl_transfer, 195 .upm_start = xhci_root_ctrl_start, 196 .upm_abort = xhci_root_ctrl_abort, 197 .upm_close = xhci_root_ctrl_close, 198 .upm_cleartoggle = xhci_noop, 199 .upm_done = xhci_root_ctrl_done, 200 }; 201 202 static const struct usbd_pipe_methods xhci_root_intr_methods = { 203 .upm_transfer = xhci_root_intr_transfer, 204 .upm_start = xhci_root_intr_start, 205 .upm_abort = xhci_root_intr_abort, 206 .upm_close = xhci_root_intr_close, 207 .upm_cleartoggle = xhci_noop, 208 .upm_done = xhci_root_intr_done, 209 }; 210 211 212 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 213 .upm_transfer = xhci_device_ctrl_transfer, 214 .upm_start = xhci_device_ctrl_start, 215 .upm_abort = xhci_device_ctrl_abort, 216 .upm_close = xhci_device_ctrl_close, 217 .upm_cleartoggle = xhci_noop, 218 .upm_done = xhci_device_ctrl_done, 219 }; 220 221 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 222 .upm_cleartoggle = xhci_noop, 223 }; 224 225 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 226 .upm_transfer = xhci_device_bulk_transfer, 227 .upm_start = xhci_device_bulk_start, 228 .upm_abort = xhci_device_bulk_abort, 229 .upm_close = xhci_device_bulk_close, 230 .upm_cleartoggle = xhci_noop, 231 .upm_done = xhci_device_bulk_done, 232 }; 233 234 static const struct usbd_pipe_methods xhci_device_intr_methods = { 235 .upm_transfer = xhci_device_intr_transfer, 236 .upm_start = xhci_device_intr_start, 237 .upm_abort = xhci_device_intr_abort, 238 .upm_close = xhci_device_intr_close, 239 .upm_cleartoggle = xhci_noop, 240 .upm_done = xhci_device_intr_done, 241 }; 242 243 static inline uint32_t 244 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 245 { 246 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 247 } 248 249 #if 0 /* unused */ 250 static inline void 251 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 252 uint32_t value) 253 { 254 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 255 } 256 #endif /* unused */ 257 258 static inline uint32_t 259 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 260 { 261 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 262 } 263 264 static inline uint32_t 265 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 266 { 267 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 268 } 269 270 static inline void 271 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 272 uint32_t value) 273 { 274 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 275 } 276 277 #if 0 /* unused */ 278 static inline uint64_t 279 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 280 { 281 uint64_t value; 282 283 if (sc->sc_ac64) { 284 #ifdef XHCI_USE_BUS_SPACE_8 285 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 286 #else 287 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 288 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 289 offset + 4) << 32; 290 #endif 291 } else { 292 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 293 } 294 295 return value; 296 } 297 #endif /* unused */ 298 299 static inline void 300 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 301 uint64_t value) 302 { 303 if (sc->sc_ac64) { 304 #ifdef XHCI_USE_BUS_SPACE_8 305 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 306 #else 307 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 308 (value >> 0) & 0xffffffff); 309 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 310 (value >> 32) & 0xffffffff); 311 #endif 312 } else { 313 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 314 } 315 } 316 317 static inline uint32_t 318 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 319 { 320 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 321 } 322 323 static inline void 324 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 325 uint32_t value) 326 { 327 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 328 } 329 330 #if 0 /* unused */ 331 static inline uint64_t 332 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 333 { 334 uint64_t value; 335 336 if (sc->sc_ac64) { 337 #ifdef XHCI_USE_BUS_SPACE_8 338 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 339 #else 340 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 341 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 342 offset + 4) << 32; 343 #endif 344 } else { 345 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 346 } 347 348 return value; 349 } 350 #endif /* unused */ 351 352 static inline void 353 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 354 uint64_t value) 355 { 356 if (sc->sc_ac64) { 357 #ifdef XHCI_USE_BUS_SPACE_8 358 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 359 #else 360 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 361 (value >> 0) & 0xffffffff); 362 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 363 (value >> 32) & 0xffffffff); 364 #endif 365 } else { 366 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 367 } 368 } 369 370 #if 0 /* unused */ 371 static inline uint32_t 372 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 373 { 374 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 375 } 376 #endif /* unused */ 377 378 static inline void 379 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 380 uint32_t value) 381 { 382 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 383 } 384 385 /* --- */ 386 387 static inline uint8_t 388 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 389 { 390 u_int eptype; 391 392 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 393 case UE_CONTROL: 394 eptype = 0x0; 395 break; 396 case UE_ISOCHRONOUS: 397 eptype = 0x1; 398 break; 399 case UE_BULK: 400 eptype = 0x2; 401 break; 402 case UE_INTERRUPT: 403 eptype = 0x3; 404 break; 405 } 406 407 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 408 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 409 return eptype | 0x4; 410 else 411 return eptype; 412 } 413 414 static u_int 415 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 416 { 417 /* xHCI 1.0 section 4.5.1 */ 418 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 419 u_int in = 0; 420 421 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 422 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 423 in = 1; 424 425 return epaddr * 2 + in; 426 } 427 428 static inline u_int 429 xhci_dci_to_ici(const u_int i) 430 { 431 return i + 1; 432 } 433 434 static inline void * 435 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 436 const u_int dci) 437 { 438 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 439 } 440 441 #if 0 /* unused */ 442 static inline bus_addr_t 443 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 444 const u_int dci) 445 { 446 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 447 } 448 #endif /* unused */ 449 450 static inline void * 451 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 452 const u_int ici) 453 { 454 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 455 } 456 457 static inline bus_addr_t 458 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 459 const u_int ici) 460 { 461 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 462 } 463 464 static inline struct xhci_trb * 465 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 466 { 467 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 468 } 469 470 static inline bus_addr_t 471 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 472 { 473 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 474 } 475 476 static inline void 477 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 478 uint32_t control) 479 { 480 trb->trb_0 = parameter; 481 trb->trb_2 = status; 482 trb->trb_3 = control; 483 } 484 485 /* --- */ 486 487 void 488 xhci_childdet(device_t self, device_t child) 489 { 490 struct xhci_softc * const sc = device_private(self); 491 492 KASSERT(sc->sc_child == child); 493 if (child == sc->sc_child) 494 sc->sc_child = NULL; 495 } 496 497 int 498 xhci_detach(struct xhci_softc *sc, int flags) 499 { 500 int rv = 0; 501 502 if (sc->sc_child != NULL) 503 rv = config_detach(sc->sc_child, flags); 504 505 if (rv != 0) 506 return (rv); 507 508 /* XXX unconfigure/free slots */ 509 510 /* verify: */ 511 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 512 xhci_op_write_4(sc, XHCI_USBCMD, 0); 513 /* do we need to wait for stop? */ 514 515 xhci_op_write_8(sc, XHCI_CRCR, 0); 516 xhci_ring_free(sc, &sc->sc_cr); 517 cv_destroy(&sc->sc_command_cv); 518 519 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 520 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 521 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 522 xhci_ring_free(sc, &sc->sc_er); 523 524 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 525 526 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 527 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 528 529 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 530 531 mutex_destroy(&sc->sc_lock); 532 mutex_destroy(&sc->sc_intr_lock); 533 534 pool_cache_destroy(sc->sc_xferpool); 535 536 return rv; 537 } 538 539 int 540 xhci_activate(device_t self, enum devact act) 541 { 542 struct xhci_softc * const sc = device_private(self); 543 544 switch (act) { 545 case DVACT_DEACTIVATE: 546 sc->sc_dying = true; 547 return 0; 548 default: 549 return EOPNOTSUPP; 550 } 551 } 552 553 bool 554 xhci_suspend(device_t dv, const pmf_qual_t *qual) 555 { 556 return false; 557 } 558 559 bool 560 xhci_resume(device_t dv, const pmf_qual_t *qual) 561 { 562 return false; 563 } 564 565 bool 566 xhci_shutdown(device_t self, int flags) 567 { 568 return false; 569 } 570 571 572 static void 573 hexdump(const char *msg, const void *base, size_t len) 574 { 575 #if 0 576 size_t cnt; 577 const uint32_t *p; 578 extern paddr_t vtophys(vaddr_t); 579 580 p = base; 581 cnt = 0; 582 583 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 584 (void *)vtophys((vaddr_t)base)); 585 586 while (cnt < len) { 587 if (cnt % 16 == 0) 588 printf("%p: ", p); 589 else if (cnt % 8 == 0) 590 printf(" |"); 591 printf(" %08x", *p++); 592 cnt += 4; 593 if (cnt % 16 == 0) 594 printf("\n"); 595 } 596 #endif 597 } 598 599 600 int 601 xhci_init(struct xhci_softc *sc) 602 { 603 bus_size_t bsz; 604 uint32_t cap, hcs1, hcs2, hcc, dboff, rtsoff; 605 uint32_t ecp, ecr; 606 uint32_t usbcmd, usbsts, pagesize, config; 607 int i; 608 uint16_t hciversion; 609 uint8_t caplength; 610 611 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 612 613 /* XXX Low/Full/High speeds for now */ 614 sc->sc_bus.ub_revision = USBREV_2_0; 615 sc->sc_bus.ub_usedma = true; 616 617 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 618 caplength = XHCI_CAP_CAPLENGTH(cap); 619 hciversion = XHCI_CAP_HCIVERSION(cap); 620 621 if ((hciversion < 0x0096) || (hciversion > 0x0100)) { 622 aprint_normal_dev(sc->sc_dev, 623 "xHCI version %x.%x not known to be supported\n", 624 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 625 } else { 626 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 627 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 628 } 629 630 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 631 &sc->sc_cbh) != 0) { 632 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 633 return ENOMEM; 634 } 635 636 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 637 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 638 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 639 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 640 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 641 (void)xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 642 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 643 644 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 645 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 646 aprint_debug_dev(sc->sc_dev, "ac64 %d ctxsz %d\n", sc->sc_ac64, 647 sc->sc_ctxsz); 648 649 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 650 ecp = XHCI_HCC_XECP(hcc) * 4; 651 while (ecp != 0) { 652 ecr = xhci_read_4(sc, ecp); 653 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 654 switch (XHCI_XECP_ID(ecr)) { 655 case XHCI_ID_PROTOCOLS: { 656 uint32_t w0, w4, w8; 657 uint16_t w2; 658 w0 = xhci_read_4(sc, ecp + 0); 659 w2 = (w0 >> 16) & 0xffff; 660 w4 = xhci_read_4(sc, ecp + 4); 661 w8 = xhci_read_4(sc, ecp + 8); 662 aprint_debug_dev(sc->sc_dev, "SP: %08x %08x %08x\n", 663 w0, w4, w8); 664 if (w4 == 0x20425355 && w2 == 0x0300) { 665 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 666 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 667 } 668 if (w4 == 0x20425355 && w2 == 0x0200) { 669 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 670 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 671 } 672 break; 673 } 674 default: 675 break; 676 } 677 ecr = xhci_read_4(sc, ecp); 678 if (XHCI_XECP_NEXT(ecr) == 0) { 679 ecp = 0; 680 } else { 681 ecp += XHCI_XECP_NEXT(ecr) * 4; 682 } 683 } 684 685 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 686 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 687 &sc->sc_obh) != 0) { 688 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 689 return ENOMEM; 690 } 691 692 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 693 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 694 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 695 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 696 return ENOMEM; 697 } 698 699 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 700 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 701 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 702 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 703 return ENOMEM; 704 } 705 706 for (i = 0; i < 100; i++) { 707 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 708 if ((usbsts & XHCI_STS_CNR) == 0) 709 break; 710 usb_delay_ms(&sc->sc_bus, 1); 711 } 712 if (i >= 100) 713 return EIO; 714 715 usbcmd = 0; 716 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 717 usb_delay_ms(&sc->sc_bus, 1); 718 719 usbcmd = XHCI_CMD_HCRST; 720 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 721 for (i = 0; i < 100; i++) { 722 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 723 if ((usbcmd & XHCI_CMD_HCRST) == 0) 724 break; 725 usb_delay_ms(&sc->sc_bus, 1); 726 } 727 if (i >= 100) 728 return EIO; 729 730 for (i = 0; i < 100; i++) { 731 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 732 if ((usbsts & XHCI_STS_CNR) == 0) 733 break; 734 usb_delay_ms(&sc->sc_bus, 1); 735 } 736 if (i >= 100) 737 return EIO; 738 739 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 740 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 741 pagesize = ffs(pagesize); 742 if (pagesize == 0) 743 return EIO; 744 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 745 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 746 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 747 (uint32_t)sc->sc_maxslots); 748 749 usbd_status err; 750 751 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 752 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 753 if (sc->sc_maxspbuf != 0) { 754 err = usb_allocmem(&sc->sc_bus, 755 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 756 &sc->sc_spbufarray_dma); 757 if (err) 758 return err; 759 760 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * sc->sc_maxspbuf, KM_SLEEP); 761 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 762 for (i = 0; i < sc->sc_maxspbuf; i++) { 763 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 764 /* allocate contexts */ 765 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 766 sc->sc_pgsz, dma); 767 if (err) 768 return err; 769 spbufarray[i] = htole64(DMAADDR(dma, 0)); 770 usb_syncmem(dma, 0, sc->sc_pgsz, 771 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 772 } 773 774 usb_syncmem(&sc->sc_spbufarray_dma, 0, 775 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 776 } 777 778 config = xhci_op_read_4(sc, XHCI_CONFIG); 779 config &= ~0xFF; 780 config |= sc->sc_maxslots & 0xFF; 781 xhci_op_write_4(sc, XHCI_CONFIG, config); 782 783 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 784 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 785 if (err) { 786 aprint_error_dev(sc->sc_dev, "command ring init fail\n"); 787 return err; 788 } 789 790 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 791 XHCI_EVENT_RING_SEGMENTS_ALIGN); 792 if (err) { 793 aprint_error_dev(sc->sc_dev, "event ring init fail\n"); 794 return err; 795 } 796 797 usb_dma_t *dma; 798 size_t size; 799 size_t align; 800 801 dma = &sc->sc_eventst_dma; 802 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 803 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 804 KASSERT(size <= (512 * 1024)); 805 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 806 err = usb_allocmem(&sc->sc_bus, size, align, dma); 807 808 memset(KERNADDR(dma, 0), 0, size); 809 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 810 aprint_debug_dev(sc->sc_dev, "eventst: %s %016jx %p %zx\n", 811 usbd_errstr(err), 812 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 813 KERNADDR(&sc->sc_eventst_dma, 0), 814 sc->sc_eventst_dma.udma_block->size); 815 816 dma = &sc->sc_dcbaa_dma; 817 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 818 KASSERT(size <= 2048); 819 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 820 err = usb_allocmem(&sc->sc_bus, size, align, dma); 821 822 memset(KERNADDR(dma, 0), 0, size); 823 if (sc->sc_maxspbuf != 0) { 824 /* 825 * DCBA entry 0 hold the scratchbuf array pointer. 826 */ 827 *(uint64_t *)KERNADDR(dma, 0) = 828 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 829 } 830 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 831 aprint_debug_dev(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n", 832 usbd_errstr(err), 833 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 834 KERNADDR(&sc->sc_dcbaa_dma, 0), 835 sc->sc_dcbaa_dma.udma_block->size); 836 837 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 838 KM_SLEEP); 839 840 cv_init(&sc->sc_command_cv, "xhcicmd"); 841 842 struct xhci_erste *erst; 843 erst = KERNADDR(&sc->sc_eventst_dma, 0); 844 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 845 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 846 erst[0].erste_3 = htole32(0); 847 usb_syncmem(&sc->sc_eventst_dma, 0, 848 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 849 850 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 851 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 852 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 853 XHCI_ERDP_LO_BUSY); 854 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 855 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 856 sc->sc_cr.xr_cs); 857 858 #if 0 859 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 860 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 861 #endif 862 863 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 864 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 865 866 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 867 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 868 xhci_op_read_4(sc, XHCI_USBCMD)); 869 870 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 871 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 872 cv_init(&sc->sc_softwake_cv, "xhciab"); 873 874 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 875 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 876 877 /* Set up the bus struct. */ 878 sc->sc_bus.ub_methods = &xhci_bus_methods; 879 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 880 881 return USBD_NORMAL_COMPLETION; 882 } 883 884 int 885 xhci_intr(void *v) 886 { 887 struct xhci_softc * const sc = v; 888 int ret = 0; 889 890 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 891 892 if (sc == NULL) 893 return 0; 894 895 mutex_spin_enter(&sc->sc_intr_lock); 896 897 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 898 goto done; 899 900 /* If we get an interrupt while polling, then just ignore it. */ 901 if (sc->sc_bus.ub_usepolling) { 902 #ifdef DIAGNOSTIC 903 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 904 #endif 905 goto done; 906 } 907 908 ret = xhci_intr1(sc); 909 done: 910 mutex_spin_exit(&sc->sc_intr_lock); 911 return ret; 912 } 913 914 int 915 xhci_intr1(struct xhci_softc * const sc) 916 { 917 uint32_t usbsts; 918 uint32_t iman; 919 920 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 921 922 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 923 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 924 #if 0 925 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 926 return 0; 927 } 928 #endif 929 xhci_op_write_4(sc, XHCI_USBSTS, 930 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 931 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 932 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 933 934 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 935 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 936 if ((iman & XHCI_IMAN_INTR_PEND) == 0) { 937 return 0; 938 } 939 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 940 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 941 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 942 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 943 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 944 945 usb_schedsoftintr(&sc->sc_bus); 946 947 return 1; 948 } 949 950 static usbd_status 951 xhci_configure_endpoint(usbd_pipe_handle pipe) 952 { 953 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 954 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 955 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 956 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 957 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 958 struct xhci_trb trb; 959 usbd_status err; 960 uint32_t *cp; 961 962 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 963 DPRINTFN(4, "dci %u epaddr 0x%02x attr 0x%02x", 964 dci, ed->bEndpointAddress, ed->bmAttributes, 0); 965 966 /* XXX ensure input context is available? */ 967 968 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 969 970 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 971 cp[0] = htole32(0); 972 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 973 974 /* set up input slot context */ 975 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 976 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 977 cp[1] = htole32(0); 978 cp[2] = htole32(0); 979 cp[3] = htole32(0); 980 981 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 982 if (xfertype == UE_INTERRUPT) { 983 cp[0] = htole32( 984 XHCI_EPCTX_0_IVAL_SET(3) /* XXX */ 985 ); 986 cp[1] = htole32( 987 XHCI_EPCTX_1_CERR_SET(3) | 988 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(pipe->up_endpoint->ue_edesc)) | 989 XHCI_EPCTX_1_MAXB_SET(0) | 990 XHCI_EPCTX_1_MAXP_SIZE_SET(8) /* XXX */ 991 ); 992 cp[4] = htole32( 993 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 994 ); 995 } else { 996 cp[0] = htole32(0); 997 cp[1] = htole32( 998 XHCI_EPCTX_1_CERR_SET(3) | 999 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(pipe->up_endpoint->ue_edesc)) | 1000 XHCI_EPCTX_1_MAXB_SET(0) | 1001 XHCI_EPCTX_1_MAXP_SIZE_SET(512) /* XXX */ 1002 ); 1003 } 1004 *(uint64_t *)(&cp[2]) = htole64( 1005 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 1006 XHCI_EPCTX_2_DCS_SET(1)); 1007 1008 /* sync input contexts before they are read from memory */ 1009 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1010 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1011 sc->sc_ctxsz * 1); 1012 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1013 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1014 1015 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1016 trb.trb_2 = 0; 1017 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1018 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1019 1020 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1021 1022 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1023 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1024 sc->sc_ctxsz * 1); 1025 1026 return err; 1027 } 1028 1029 static usbd_status 1030 xhci_unconfigure_endpoint(usbd_pipe_handle pipe) 1031 { 1032 #ifdef USB_DEBUG 1033 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1034 #endif 1035 1036 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1037 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1038 1039 return USBD_NORMAL_COMPLETION; 1040 } 1041 1042 static usbd_status 1043 xhci_reset_endpoint(usbd_pipe_handle pipe) 1044 { 1045 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1046 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1047 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1048 struct xhci_trb trb; 1049 usbd_status err; 1050 1051 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1052 DPRINTFN(4, "dci %u", dci, 0, 0, 0); 1053 1054 trb.trb_0 = 0; 1055 trb.trb_2 = 0; 1056 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1057 XHCI_TRB_3_EP_SET(dci) | 1058 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1059 1060 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1061 1062 return err; 1063 } 1064 1065 #if 0 1066 static usbd_status 1067 xhci_stop_endpoint(usbd_pipe_handle pipe) 1068 { 1069 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1070 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1071 struct xhci_trb trb; 1072 usbd_status err; 1073 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1074 1075 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1076 DPRINTFN(4, "dci %u", dci, 0, 0, 0); 1077 1078 trb.trb_0 = 0; 1079 trb.trb_2 = 0; 1080 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1081 XHCI_TRB_3_EP_SET(dci) | 1082 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1083 1084 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1085 1086 return err; 1087 } 1088 #endif 1089 1090 static usbd_status 1091 xhci_set_dequeue(usbd_pipe_handle pipe) 1092 { 1093 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1094 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1095 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1096 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1097 struct xhci_trb trb; 1098 usbd_status err; 1099 1100 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1101 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1102 1103 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1104 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1105 BUS_DMASYNC_PREWRITE); 1106 1107 xr->xr_ep = 0; 1108 xr->xr_cs = 1; 1109 1110 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1111 trb.trb_2 = 0; 1112 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1113 XHCI_TRB_3_EP_SET(dci) | 1114 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1115 1116 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1117 1118 return err; 1119 } 1120 1121 static usbd_status 1122 xhci_open(usbd_pipe_handle pipe) 1123 { 1124 usbd_device_handle const dev = pipe->up_dev; 1125 struct xhci_softc * const sc = dev->ud_bus->ub_hcpriv; 1126 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1127 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1128 1129 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1130 DPRINTFN(1, "addr %d depth %d port %d speed %d", 1131 dev->ud_addr, dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1132 1133 if (sc->sc_dying) 1134 return USBD_IOERROR; 1135 1136 /* Root Hub */ 1137 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0 && 1138 dev->ud_speed != USB_SPEED_SUPER) { 1139 switch (ed->bEndpointAddress) { 1140 case USB_CONTROL_ENDPOINT: 1141 pipe->up_methods = &xhci_root_ctrl_methods; 1142 break; 1143 case UE_DIR_IN | XHCI_INTR_ENDPT: 1144 pipe->up_methods = &xhci_root_intr_methods; 1145 break; 1146 default: 1147 pipe->up_methods = NULL; 1148 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1149 ed->bEndpointAddress, 0, 0, 0); 1150 return USBD_INVAL; 1151 } 1152 return USBD_NORMAL_COMPLETION; 1153 } 1154 1155 switch (xfertype) { 1156 case UE_CONTROL: 1157 pipe->up_methods = &xhci_device_ctrl_methods; 1158 break; 1159 case UE_ISOCHRONOUS: 1160 pipe->up_methods = &xhci_device_isoc_methods; 1161 return USBD_INVAL; 1162 break; 1163 case UE_BULK: 1164 pipe->up_methods = &xhci_device_bulk_methods; 1165 break; 1166 case UE_INTERRUPT: 1167 pipe->up_methods = &xhci_device_intr_methods; 1168 break; 1169 default: 1170 return USBD_IOERROR; 1171 break; 1172 } 1173 1174 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1175 xhci_configure_endpoint(pipe); 1176 1177 return USBD_NORMAL_COMPLETION; 1178 } 1179 1180 static void 1181 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1182 { 1183 usbd_xfer_handle const xfer = sc->sc_intrxfer; 1184 uint8_t *p; 1185 1186 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1187 DPRINTFN(4, "port %u status change", port, 0, 0, 0); 1188 1189 if (xfer == NULL) 1190 return; 1191 1192 if (!(port >= sc->sc_hs_port_start && 1193 port < sc->sc_hs_port_start + sc->sc_hs_port_count)) 1194 return; 1195 1196 port -= sc->sc_hs_port_start; 1197 port += 1; 1198 DPRINTFN(4, "hs port %u status change", port, 0, 0, 0); 1199 1200 p = xfer->ux_buf; 1201 memset(p, 0, xfer->ux_length); 1202 p[port/NBBY] |= 1 << (port%NBBY); 1203 xfer->ux_actlen = xfer->ux_length; 1204 xfer->ux_status = USBD_NORMAL_COMPLETION; 1205 usb_transfer_complete(xfer); 1206 } 1207 1208 static void 1209 xhci_handle_event(struct xhci_softc * const sc, 1210 const struct xhci_trb * const trb) 1211 { 1212 uint64_t trb_0; 1213 uint32_t trb_2, trb_3; 1214 1215 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1216 1217 trb_0 = le64toh(trb->trb_0); 1218 trb_2 = le32toh(trb->trb_2); 1219 trb_3 = le32toh(trb->trb_3); 1220 1221 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1222 trb, trb_0, trb_2, trb_3); 1223 1224 switch (XHCI_TRB_3_TYPE_GET(trb_3)){ 1225 case XHCI_TRB_EVENT_TRANSFER: { 1226 u_int slot, dci; 1227 struct xhci_slot *xs; 1228 struct xhci_ring *xr; 1229 struct xhci_xfer *xx; 1230 usbd_xfer_handle xfer; 1231 usbd_status err; 1232 1233 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1234 dci = XHCI_TRB_3_EP_GET(trb_3); 1235 1236 xs = &sc->sc_slots[slot]; 1237 xr = &xs->xs_ep[dci].xe_tr; 1238 1239 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1240 xx = xr->xr_cookies[(trb_0 - xhci_ring_trbp(xr, 0))/ 1241 sizeof(struct xhci_trb)]; 1242 } else { 1243 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1244 } 1245 xfer = &xx->xx_xfer; 1246 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1247 1248 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1249 DPRINTFN(14, "transfer event data: " 1250 "0x%016"PRIx64" 0x%08"PRIx32" %02x", 1251 trb_0, XHCI_TRB_2_REM_GET(trb_2), 1252 XHCI_TRB_2_ERROR_GET(trb_2), 0); 1253 if ((trb_0 & 0x3) == 0x3) { 1254 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1255 } 1256 } 1257 1258 if (XHCI_TRB_2_ERROR_GET(trb_2) == 1259 XHCI_TRB_ERROR_SUCCESS) { 1260 xfer->ux_actlen = xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1261 err = USBD_NORMAL_COMPLETION; 1262 } else if (XHCI_TRB_2_ERROR_GET(trb_2) == 1263 XHCI_TRB_ERROR_SHORT_PKT) { 1264 xfer->ux_actlen = xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1265 err = USBD_NORMAL_COMPLETION; 1266 } else if (XHCI_TRB_2_ERROR_GET(trb_2) == 1267 XHCI_TRB_ERROR_STALL) { 1268 err = USBD_STALLED; 1269 xr->is_halted = true; 1270 DPRINTFN(1, "ev: xfer done: err %u slot %u dci %u", 1271 XHCI_TRB_2_ERROR_GET(trb_2), slot, dci, 0); 1272 } else { 1273 err = USBD_IOERROR; 1274 } 1275 xfer->ux_status = err; 1276 1277 //mutex_enter(&sc->sc_lock); /* XXX ??? */ 1278 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1279 if ((trb_0 & 0x3) == 0x0) { 1280 usb_transfer_complete(xfer); 1281 } 1282 } else { 1283 usb_transfer_complete(xfer); 1284 } 1285 //mutex_exit(&sc->sc_lock); /* XXX ??? */ 1286 1287 } 1288 break; 1289 case XHCI_TRB_EVENT_CMD_COMPLETE: 1290 if (trb_0 == sc->sc_command_addr) { 1291 sc->sc_result_trb.trb_0 = trb_0; 1292 sc->sc_result_trb.trb_2 = trb_2; 1293 sc->sc_result_trb.trb_3 = trb_3; 1294 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1295 XHCI_TRB_ERROR_SUCCESS) { 1296 DPRINTFN(1, "command completion " 1297 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1298 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1299 } 1300 cv_signal(&sc->sc_command_cv); 1301 } else { 1302 DPRINTFN(1, "event: %p 0x%016"PRIx64" " 1303 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1304 trb_2, trb_3); 1305 } 1306 break; 1307 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1308 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1309 break; 1310 default: 1311 break; 1312 } 1313 } 1314 1315 static void 1316 xhci_softintr(void *v) 1317 { 1318 struct usbd_bus * const bus = v; 1319 struct xhci_softc * const sc = bus->ub_hcpriv; 1320 struct xhci_ring * const er = &sc->sc_er; 1321 struct xhci_trb *trb; 1322 int i, j, k; 1323 1324 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1325 1326 i = er->xr_ep; 1327 j = er->xr_cs; 1328 1329 DPRINTFN(16, "xr_ep %d xr_cs %d", i, j, 0, 0); 1330 1331 while (1) { 1332 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 1333 BUS_DMASYNC_POSTREAD); 1334 trb = &er->xr_trb[i]; 1335 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1336 1337 if (j != k) 1338 break; 1339 1340 xhci_handle_event(sc, trb); 1341 1342 i++; 1343 if (i == XHCI_EVENT_RING_TRBS) { 1344 i = 0; 1345 j ^= 1; 1346 } 1347 } 1348 1349 er->xr_ep = i; 1350 er->xr_cs = j; 1351 1352 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 1353 XHCI_ERDP_LO_BUSY); 1354 1355 DPRINTFN(16, "ends", 0, 0, 0, 0); 1356 1357 return; 1358 } 1359 1360 static void 1361 xhci_poll(struct usbd_bus *bus) 1362 { 1363 struct xhci_softc * const sc = bus->ub_hcpriv; 1364 1365 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1366 1367 mutex_spin_enter(&sc->sc_intr_lock); 1368 xhci_intr1(sc); 1369 mutex_spin_exit(&sc->sc_intr_lock); 1370 1371 return; 1372 } 1373 1374 static usbd_xfer_handle 1375 xhci_allocx(struct usbd_bus *bus) 1376 { 1377 struct xhci_softc * const sc = bus->ub_hcpriv; 1378 usbd_xfer_handle xfer; 1379 1380 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1381 1382 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1383 if (xfer != NULL) { 1384 memset(xfer, 0, sizeof(struct xhci_xfer)); 1385 #ifdef DIAGNOSTIC 1386 xfer->ux_state = XFER_BUSY; 1387 #endif 1388 } 1389 1390 return xfer; 1391 } 1392 1393 static void 1394 xhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1395 { 1396 struct xhci_softc * const sc = bus->ub_hcpriv; 1397 1398 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1399 1400 #ifdef DIAGNOSTIC 1401 if (xfer->ux_state != XFER_BUSY) { 1402 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 1403 xfer, xfer->ux_state, 0, 0); 1404 } 1405 xfer->ux_state = XFER_FREE; 1406 #endif 1407 pool_cache_put(sc->sc_xferpool, xfer); 1408 } 1409 1410 static void 1411 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1412 { 1413 struct xhci_softc * const sc = bus->ub_hcpriv; 1414 1415 *lock = &sc->sc_lock; 1416 } 1417 1418 extern uint32_t usb_cookie_no; 1419 1420 static usbd_status 1421 xhci_new_device(device_t parent, usbd_bus_handle bus, int depth, 1422 int speed, int port, struct usbd_port *up) 1423 { 1424 struct xhci_softc * const sc = bus->ub_hcpriv; 1425 usbd_device_handle dev; 1426 usbd_status err; 1427 usb_device_descriptor_t *dd; 1428 struct usbd_device *hub; 1429 struct usbd_device *adev; 1430 int rhport = 0; 1431 struct xhci_slot *xs; 1432 uint32_t *cp; 1433 uint8_t slot; 1434 uint8_t addr; 1435 1436 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1437 DPRINTFN(4, "port=%d depth=%d speed=%d upport %d", 1438 port, depth, speed, up->up_portno); 1439 1440 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 1441 if (dev == NULL) 1442 return USBD_NOMEM; 1443 1444 dev->ud_bus = bus; 1445 1446 /* Set up default endpoint handle. */ 1447 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 1448 1449 /* Set up default endpoint descriptor. */ 1450 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 1451 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 1452 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 1453 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 1454 /* XXX */ 1455 if (speed == USB_SPEED_LOW) 1456 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 1457 else 1458 USETW(dev->ud_ep0desc.wMaxPacketSize, 64); 1459 dev->ud_ep0desc.bInterval = 0; 1460 1461 /* doesn't matter, just don't let it uninitialized */ 1462 dev->ud_ep0.ue_toggle = 0; 1463 1464 DPRINTFN(4, "up %p portno %d", up, up->up_portno, 0, 0); 1465 1466 dev->ud_quirks = &usbd_no_quirk; 1467 dev->ud_addr = 0; 1468 dev->ud_ddesc.bMaxPacketSize = 0; 1469 dev->ud_depth = depth; 1470 dev->ud_powersrc = up; 1471 dev->ud_myhub = up->up_parent; 1472 1473 up->up_dev = dev; 1474 1475 /* Locate root hub port */ 1476 for (adev = dev, hub = dev; 1477 hub != NULL; 1478 adev = hub, hub = hub->ud_myhub) { 1479 DPRINTFN(4, "hub %p", hub, 0, 0, 0); 1480 } 1481 DPRINTFN(4, "hub %p", hub, 0, 0, 0); 1482 1483 if (hub != NULL) { 1484 for (int p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 1485 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 1486 rhport = p; 1487 } 1488 } 1489 } else { 1490 rhport = port; 1491 } 1492 if (speed == USB_SPEED_SUPER) { 1493 rhport += sc->sc_ss_port_start - 1; 1494 } else { 1495 rhport += sc->sc_hs_port_start - 1; 1496 } 1497 DPRINTFN(4, "rhport %d", rhport, 0, 0, 0); 1498 1499 dev->ud_speed = speed; 1500 dev->ud_langid = USBD_NOLANG; 1501 dev->ud_cookie.cookie = ++usb_cookie_no; 1502 1503 /* Establish the default pipe. */ 1504 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 1505 &dev->ud_pipe0); 1506 if (err) { 1507 usbd_remove_device(dev, up); 1508 return (err); 1509 } 1510 1511 dd = &dev->ud_ddesc; 1512 1513 if ((depth == 0) && (port == 0)) { 1514 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 1515 bus->ub_devices[dev->ud_addr] = dev; 1516 err = usbd_get_initial_ddesc(dev, dd); 1517 if (err) 1518 return err; 1519 err = usbd_reload_device_desc(dev); 1520 if (err) 1521 return err; 1522 } else { 1523 err = xhci_enable_slot(sc, &slot); 1524 if (err) 1525 return err; 1526 err = xhci_init_slot(sc, slot, depth, speed, port, rhport); 1527 if (err) 1528 return err; 1529 xs = &sc->sc_slots[slot]; 1530 dev->ud_hcpriv = xs; 1531 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 1532 //hexdump("slot context", cp, sc->sc_ctxsz); 1533 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 1534 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 1535 /* XXX ensure we know when the hardware does something 1536 we can't yet cope with */ 1537 KASSERT(addr >= 1 && addr <= 127); 1538 dev->ud_addr = addr; 1539 /* XXX dev->ud_addr not necessarily unique on bus */ 1540 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 1541 bus->ub_devices[dev->ud_addr] = dev; 1542 1543 err = usbd_get_initial_ddesc(dev, dd); 1544 if (err) 1545 return err; 1546 /* 4.8.2.1 */ 1547 if (speed == USB_SPEED_SUPER) 1548 USETW(dev->ud_ep0desc.wMaxPacketSize, 1549 (1 << dd->bMaxPacketSize)); 1550 else 1551 USETW(dev->ud_ep0desc.wMaxPacketSize, 1552 dd->bMaxPacketSize); 1553 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 1554 xhci_update_ep0_mps(sc, xs, 1555 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 1556 err = usbd_reload_device_desc(dev); 1557 if (err) 1558 return err; 1559 1560 usbd_kill_pipe(dev->ud_pipe0); 1561 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 1562 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 1563 } 1564 1565 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 1566 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 1567 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 1568 dd->bDeviceClass, dd->bDeviceSubClass, 1569 dd->bDeviceProtocol, 0); 1570 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 1571 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 1572 dev->ud_speed); 1573 1574 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 1575 1576 if ((depth == 0) && (port == 0)) { 1577 usbd_attach_roothub(parent, dev); 1578 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 1579 return USBD_NORMAL_COMPLETION; 1580 } 1581 1582 1583 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 1584 if (err) { 1585 usbd_remove_device(dev, up); 1586 return (err); 1587 } 1588 1589 return USBD_NORMAL_COMPLETION; 1590 } 1591 1592 static usbd_status 1593 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 1594 size_t ntrb, size_t align) 1595 { 1596 usbd_status err; 1597 size_t size = ntrb * XHCI_TRB_SIZE; 1598 1599 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1600 1601 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 1602 if (err) 1603 return err; 1604 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1605 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 1606 xr->xr_trb = xhci_ring_trbv(xr, 0); 1607 xr->xr_ntrb = ntrb; 1608 xr->xr_ep = 0; 1609 xr->xr_cs = 1; 1610 memset(xr->xr_trb, 0, size); 1611 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 1612 xr->is_halted = false; 1613 1614 return USBD_NORMAL_COMPLETION; 1615 } 1616 1617 static void 1618 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 1619 { 1620 usb_freemem(&sc->sc_bus, &xr->xr_dma); 1621 mutex_destroy(&xr->xr_lock); 1622 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 1623 } 1624 1625 static void 1626 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 1627 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 1628 { 1629 size_t i; 1630 u_int ri; 1631 u_int cs; 1632 uint64_t parameter; 1633 uint32_t status; 1634 uint32_t control; 1635 1636 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1637 1638 for (i = 0; i < ntrbs; i++) { 1639 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 1640 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 1641 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 1642 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 1643 XHCI_TRB_TYPE_LINK); 1644 } 1645 1646 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 1647 1648 ri = xr->xr_ep; 1649 cs = xr->xr_cs; 1650 1651 /* 1652 * Although the xhci hardware can do scatter/gather dma from 1653 * arbitrary sized buffers, there is a non-obvious restriction 1654 * that a LINK trb is only allowed at the end of a burst of 1655 * transfers - which might be 16kB. 1656 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 1657 * The simple solution is not to allow a LINK trb in the middle 1658 * of anything - as here. 1659 * XXX: (dsl) There are xhci controllers out there (eg some made by 1660 * ASMedia) that seem to lock up if they process a LINK trb but 1661 * cannot process the linked-to trb yet. 1662 * The code should write the 'cycle' bit on the link trb AFTER 1663 * adding the other trb. 1664 */ 1665 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 1666 parameter = xhci_ring_trbp(xr, 0); 1667 status = 0; 1668 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1669 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 1670 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 1671 htole32(status), htole32(control)); 1672 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1673 BUS_DMASYNC_PREWRITE); 1674 xr->xr_cookies[ri] = NULL; 1675 xr->xr_ep = 0; 1676 xr->xr_cs ^= 1; 1677 ri = xr->xr_ep; 1678 cs = xr->xr_cs; 1679 } 1680 1681 ri++; 1682 1683 /* Write any subsequent TRB first */ 1684 for (i = 1; i < ntrbs; i++) { 1685 parameter = trbs[i].trb_0; 1686 status = trbs[i].trb_2; 1687 control = trbs[i].trb_3; 1688 1689 if (cs) { 1690 control |= XHCI_TRB_3_CYCLE_BIT; 1691 } else { 1692 control &= ~XHCI_TRB_3_CYCLE_BIT; 1693 } 1694 1695 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 1696 htole32(status), htole32(control)); 1697 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1698 BUS_DMASYNC_PREWRITE); 1699 xr->xr_cookies[ri] = cookie; 1700 ri++; 1701 } 1702 1703 /* Write the first TRB last */ 1704 i = 0; 1705 { 1706 parameter = trbs[i].trb_0; 1707 status = trbs[i].trb_2; 1708 control = trbs[i].trb_3; 1709 1710 if (xr->xr_cs) { 1711 control |= XHCI_TRB_3_CYCLE_BIT; 1712 } else { 1713 control &= ~XHCI_TRB_3_CYCLE_BIT; 1714 } 1715 1716 xhci_trb_put(&xr->xr_trb[xr->xr_ep], htole64(parameter), 1717 htole32(status), htole32(control)); 1718 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1719 BUS_DMASYNC_PREWRITE); 1720 xr->xr_cookies[xr->xr_ep] = cookie; 1721 } 1722 1723 xr->xr_ep = ri; 1724 xr->xr_cs = cs; 1725 1726 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 1727 } 1728 1729 static usbd_status 1730 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 1731 int timeout) 1732 { 1733 struct xhci_ring * const cr = &sc->sc_cr; 1734 usbd_status err; 1735 1736 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1737 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1738 trb->trb_0, trb->trb_2, trb->trb_3, 0); 1739 1740 mutex_enter(&sc->sc_lock); 1741 1742 KASSERT(sc->sc_command_addr == 0); 1743 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 1744 1745 mutex_enter(&cr->xr_lock); 1746 xhci_ring_put(sc, cr, NULL, trb, 1); 1747 mutex_exit(&cr->xr_lock); 1748 1749 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 1750 1751 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 1752 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 1753 err = USBD_TIMEOUT; 1754 goto timedout; 1755 } 1756 1757 trb->trb_0 = sc->sc_result_trb.trb_0; 1758 trb->trb_2 = sc->sc_result_trb.trb_2; 1759 trb->trb_3 = sc->sc_result_trb.trb_3; 1760 1761 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 1762 trb->trb_0, trb->trb_2, trb->trb_3, 0); 1763 1764 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 1765 case XHCI_TRB_ERROR_SUCCESS: 1766 err = USBD_NORMAL_COMPLETION; 1767 break; 1768 default: 1769 case 192 ... 223: 1770 err = USBD_IOERROR; 1771 break; 1772 case 224 ... 255: 1773 err = USBD_NORMAL_COMPLETION; 1774 break; 1775 } 1776 1777 timedout: 1778 sc->sc_command_addr = 0; 1779 mutex_exit(&sc->sc_lock); 1780 return err; 1781 } 1782 1783 static usbd_status 1784 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 1785 { 1786 struct xhci_trb trb; 1787 usbd_status err; 1788 1789 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1790 1791 trb.trb_0 = 0; 1792 trb.trb_2 = 0; 1793 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 1794 1795 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1796 if (err != USBD_NORMAL_COMPLETION) { 1797 return err; 1798 } 1799 1800 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 1801 1802 return err; 1803 } 1804 1805 static usbd_status 1806 xhci_address_device(struct xhci_softc * const sc, 1807 uint64_t icp, uint8_t slot_id, bool bsr) 1808 { 1809 struct xhci_trb trb; 1810 usbd_status err; 1811 1812 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1813 1814 trb.trb_0 = icp; 1815 trb.trb_2 = 0; 1816 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 1817 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1818 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 1819 1820 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1821 return err; 1822 } 1823 1824 static usbd_status 1825 xhci_update_ep0_mps(struct xhci_softc * const sc, 1826 struct xhci_slot * const xs, u_int mps) 1827 { 1828 struct xhci_trb trb; 1829 usbd_status err; 1830 uint32_t * cp; 1831 1832 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1833 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 1834 1835 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1836 cp[0] = htole32(0); 1837 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 1838 1839 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 1840 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1841 1842 /* sync input contexts before they are read from memory */ 1843 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1844 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 1845 sc->sc_ctxsz * 4); 1846 1847 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1848 trb.trb_2 = 0; 1849 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1850 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 1851 1852 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1853 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 1854 return err; 1855 } 1856 1857 static void 1858 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 1859 { 1860 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 1861 1862 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1863 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 1864 &dcbaa[si], dcba, si, 0); 1865 1866 dcbaa[si] = htole64(dcba); 1867 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 1868 BUS_DMASYNC_PREWRITE); 1869 } 1870 1871 static usbd_status 1872 xhci_init_slot(struct xhci_softc * const sc, uint32_t slot, int depth, 1873 int speed, int port, int rhport) 1874 { 1875 struct xhci_slot *xs; 1876 usbd_status err; 1877 u_int dci; 1878 uint32_t *cp; 1879 uint32_t mps; 1880 uint32_t xspeed; 1881 1882 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1883 DPRINTFN(4, "slot %u depth %d speed %d", 1884 slot, depth, speed, 0); 1885 DPRINTFN(4, " port %d rhport %d", 1886 port, rhport, 0, 0); 1887 1888 switch (speed) { 1889 case USB_SPEED_LOW: 1890 xspeed = 2; 1891 mps = USB_MAX_IPACKET; 1892 break; 1893 case USB_SPEED_FULL: 1894 xspeed = 1; 1895 mps = 64; 1896 break; 1897 case USB_SPEED_HIGH: 1898 xspeed = 3; 1899 mps = USB_2_MAX_CTRL_PACKET; 1900 break; 1901 case USB_SPEED_SUPER: 1902 xspeed = 4; 1903 mps = USB_3_MAX_CTRL_PACKET; 1904 break; 1905 default: 1906 DPRINTFN(0, "impossible speed: %x", speed, 0, 0, 0); 1907 return USBD_INVAL; 1908 } 1909 1910 xs = &sc->sc_slots[slot]; 1911 xs->xs_idx = slot; 1912 1913 /* allocate contexts */ 1914 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 1915 &xs->xs_dc_dma); 1916 if (err) 1917 return err; 1918 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 1919 1920 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 1921 &xs->xs_ic_dma); 1922 if (err) 1923 return err; 1924 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 1925 1926 for (dci = 0; dci < 32; dci++) { 1927 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 1928 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 1929 if (dci == XHCI_DCI_SLOT) 1930 continue; 1931 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 1932 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 1933 if (err) { 1934 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 1935 return err; 1936 } 1937 } 1938 1939 /* set up initial input control context */ 1940 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1941 cp[0] = htole32(0); 1942 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 1943 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 1944 1945 /* set up input slot context */ 1946 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1947 cp[0] = htole32( 1948 XHCI_SCTX_0_CTX_NUM_SET(1) | 1949 XHCI_SCTX_0_SPEED_SET(xspeed) 1950 ); 1951 cp[1] = htole32( 1952 XHCI_SCTX_1_RH_PORT_SET(rhport) 1953 ); 1954 cp[2] = htole32( 1955 XHCI_SCTX_2_IRQ_TARGET_SET(0) 1956 ); 1957 cp[3] = htole32(0); 1958 1959 /* set up input EP0 context */ 1960 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 1961 cp[0] = htole32(0); 1962 cp[1] = htole32( 1963 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 1964 XHCI_EPCTX_1_EPTYPE_SET(4) | 1965 XHCI_EPCTX_1_CERR_SET(3) 1966 ); 1967 /* can't use xhci_ep_get_dci() yet? */ 1968 *(uint64_t *)(&cp[2]) = htole64( 1969 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 1970 XHCI_EPCTX_2_DCS_SET(1)); 1971 cp[4] = htole32( 1972 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 1973 ); 1974 1975 /* sync input contexts before they are read from memory */ 1976 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1977 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 1978 sc->sc_ctxsz * 3); 1979 1980 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 1981 1982 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 1983 false); 1984 1985 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1986 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 1987 sc->sc_ctxsz * 2); 1988 1989 return err; 1990 } 1991 1992 /* ----- */ 1993 1994 static void 1995 xhci_noop(usbd_pipe_handle pipe) 1996 { 1997 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1998 } 1999 2000 /* root hub descriptors */ 2001 2002 static const usb_device_descriptor_t xhci_devd = { 2003 .bLength = USB_DEVICE_DESCRIPTOR_SIZE, 2004 .bDescriptorType = UDESC_DEVICE, 2005 .bcdUSB = {0x00, 0x02}, 2006 .bDeviceClass = UDCLASS_HUB, 2007 .bDeviceSubClass = UDSUBCLASS_HUB, 2008 .bDeviceProtocol = UDPROTO_HSHUBSTT, 2009 .bMaxPacketSize = 64, 2010 .idVendor = {0}, 2011 .idProduct = {0}, 2012 .bcdDevice = {0x00,0x01}, 2013 .iManufacturer = 1, 2014 .iProduct = 2, 2015 .iSerialNumber = 0, 2016 .bNumConfigurations = 1 2017 }; 2018 2019 static const usb_device_qualifier_t xhci_odevd = { 2020 .bLength = USB_DEVICE_DESCRIPTOR_SIZE, 2021 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 2022 .bcdUSB = {0x00, 0x02}, 2023 .bDeviceClass = UDCLASS_HUB, 2024 .bDeviceSubClass = UDSUBCLASS_HUB, 2025 .bDeviceProtocol = UDPROTO_FSHUB, 2026 .bMaxPacketSize0 = 64, 2027 .bNumConfigurations = 1, 2028 }; 2029 2030 static const usb_config_descriptor_t xhci_confd = { 2031 .bLength = USB_CONFIG_DESCRIPTOR_SIZE, 2032 .bDescriptorType = UDESC_CONFIG, 2033 .wTotalLength = USETWD( 2034 USB_CONFIG_DESCRIPTOR_SIZE + 2035 USB_INTERFACE_DESCRIPTOR_SIZE + 2036 USB_ENDPOINT_DESCRIPTOR_SIZE), 2037 .bNumInterface = 1, 2038 .bConfigurationValue = 1, 2039 .iConfiguration = 0, 2040 .bmAttributes = UC_ATTR_MBO | UC_SELF_POWERED, 2041 .bMaxPower = 0 2042 }; 2043 2044 static const usb_interface_descriptor_t xhci_ifcd = { 2045 .bLength = USB_INTERFACE_DESCRIPTOR_SIZE, 2046 .bDescriptorType = UDESC_INTERFACE, 2047 .bInterfaceNumber = 0, 2048 .bAlternateSetting = 0, 2049 .bNumEndpoints = 1, 2050 .bInterfaceClass = UICLASS_HUB, 2051 .bInterfaceSubClass = UISUBCLASS_HUB, 2052 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 2053 .iInterface = 0 2054 }; 2055 2056 static const usb_endpoint_descriptor_t xhci_endpd = { 2057 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 2058 .bDescriptorType = UDESC_ENDPOINT, 2059 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 2060 .bmAttributes = UE_INTERRUPT, 2061 .wMaxPacketSize = USETWD(8), 2062 .bInterval = 12 2063 }; 2064 2065 static const usb_hub_descriptor_t xhci_hubd = { 2066 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 2067 .bDescriptorType = UDESC_HUB, 2068 .bNbrPorts = 0, 2069 .wHubCharacteristics = USETWD(0), 2070 .bPwrOn2PwrGood = 0, 2071 .bHubContrCurrent = 0, 2072 .DeviceRemovable = {""}, 2073 .PortPowerCtrlMask = {""}, 2074 }; 2075 2076 /* root hub control */ 2077 2078 static usbd_status 2079 xhci_root_ctrl_transfer(usbd_xfer_handle xfer) 2080 { 2081 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2082 usbd_status err; 2083 2084 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2085 2086 /* Insert last in queue. */ 2087 mutex_enter(&sc->sc_lock); 2088 err = usb_insert_transfer(xfer); 2089 mutex_exit(&sc->sc_lock); 2090 if (err) 2091 return err; 2092 2093 /* Pipe isn't running, start first */ 2094 return (xhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 2095 } 2096 2097 static usbd_status 2098 xhci_root_ctrl_start(usbd_xfer_handle xfer) 2099 { 2100 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2101 usb_port_status_t ps; 2102 usb_device_request_t *req; 2103 void *buf = NULL; 2104 usb_hub_descriptor_t hubd; 2105 usbd_status err; 2106 int len, value, index; 2107 int l, totlen = 0; 2108 int port, i; 2109 uint32_t v; 2110 2111 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2112 2113 if (sc->sc_dying) 2114 return USBD_IOERROR; 2115 2116 req = &xfer->ux_request; 2117 2118 value = UGETW(req->wValue); 2119 index = UGETW(req->wIndex); 2120 len = UGETW(req->wLength); 2121 2122 if (len != 0) 2123 buf = xfer->ux_buf; 2124 2125 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 2126 req->bmRequestType | (req->bRequest << 8), value, index, len); 2127 2128 #define C(x,y) ((x) | ((y) << 8)) 2129 switch(C(req->bRequest, req->bmRequestType)) { 2130 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2131 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2132 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2133 /* 2134 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2135 * for the integrated root hub. 2136 */ 2137 break; 2138 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2139 if (len > 0) { 2140 *(uint8_t *)buf = sc->sc_conf; 2141 totlen = 1; 2142 } 2143 break; 2144 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2145 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 2146 if (len == 0) 2147 break; 2148 switch(value >> 8) { 2149 case UDESC_DEVICE: 2150 if ((value & 0xff) != 0) { 2151 err = USBD_IOERROR; 2152 goto ret; 2153 } 2154 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2155 memcpy(buf, &xhci_devd, min(l, sizeof(xhci_devd))); 2156 break; 2157 case UDESC_DEVICE_QUALIFIER: 2158 if ((value & 0xff) != 0) { 2159 } 2160 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2161 memcpy(buf, &xhci_odevd, min(l, sizeof(xhci_odevd))); 2162 break; 2163 case UDESC_OTHER_SPEED_CONFIGURATION: 2164 case UDESC_CONFIG: 2165 if ((value & 0xff) != 0) { 2166 err = USBD_IOERROR; 2167 goto ret; 2168 } 2169 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2170 memcpy(buf, &xhci_confd, min(l, sizeof(xhci_confd))); 2171 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2172 value >> 8; 2173 buf = (char *)buf + l; 2174 len -= l; 2175 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2176 totlen += l; 2177 memcpy(buf, &xhci_ifcd, min(l, sizeof(xhci_ifcd))); 2178 buf = (char *)buf + l; 2179 len -= l; 2180 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2181 totlen += l; 2182 memcpy(buf, &xhci_endpd, min(l, sizeof(xhci_endpd))); 2183 break; 2184 case UDESC_STRING: 2185 #define sd ((usb_string_descriptor_t *)buf) 2186 switch (value & 0xff) { 2187 case 0: /* Language table */ 2188 totlen = usb_makelangtbl(sd, len); 2189 break; 2190 case 1: /* Vendor */ 2191 totlen = usb_makestrdesc(sd, len, "NetBSD"); 2192 break; 2193 case 2: /* Product */ 2194 totlen = usb_makestrdesc(sd, len, 2195 "xHCI Root Hub"); 2196 break; 2197 } 2198 #undef sd 2199 break; 2200 default: 2201 err = USBD_IOERROR; 2202 goto ret; 2203 } 2204 break; 2205 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2206 if (len > 0) { 2207 *(uint8_t *)buf = 0; 2208 totlen = 1; 2209 } 2210 break; 2211 case C(UR_GET_STATUS, UT_READ_DEVICE): 2212 if (len > 1) { 2213 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2214 totlen = 2; 2215 } 2216 break; 2217 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2218 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2219 if (len > 1) { 2220 USETW(((usb_status_t *)buf)->wStatus, 0); 2221 totlen = 2; 2222 } 2223 break; 2224 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2225 if (value >= USB_MAX_DEVICES) { 2226 err = USBD_IOERROR; 2227 goto ret; 2228 } 2229 //sc->sc_addr = value; 2230 break; 2231 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2232 if (value != 0 && value != 1) { 2233 err = USBD_IOERROR; 2234 goto ret; 2235 } 2236 sc->sc_conf = value; 2237 break; 2238 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2239 break; 2240 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2241 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2242 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2243 err = USBD_IOERROR; 2244 goto ret; 2245 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2246 break; 2247 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2248 break; 2249 /* Hub requests */ 2250 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2251 break; 2252 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2253 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2254 index, value, 0, 0); 2255 if (index < 1 || index > sc->sc_hs_port_count) { 2256 err = USBD_IOERROR; 2257 goto ret; 2258 } 2259 port = XHCI_PORTSC(sc->sc_hs_port_start - 1 + index); 2260 v = xhci_op_read_4(sc, port); 2261 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2262 v &= ~XHCI_PS_CLEAR; 2263 switch (value) { 2264 case UHF_PORT_ENABLE: 2265 xhci_op_write_4(sc, port, v &~ XHCI_PS_PED); 2266 break; 2267 case UHF_PORT_SUSPEND: 2268 err = USBD_IOERROR; 2269 goto ret; 2270 case UHF_PORT_POWER: 2271 break; 2272 case UHF_PORT_TEST: 2273 case UHF_PORT_INDICATOR: 2274 err = USBD_IOERROR; 2275 goto ret; 2276 case UHF_C_PORT_CONNECTION: 2277 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2278 break; 2279 case UHF_C_PORT_ENABLE: 2280 case UHF_C_PORT_SUSPEND: 2281 case UHF_C_PORT_OVER_CURRENT: 2282 err = USBD_IOERROR; 2283 goto ret; 2284 case UHF_C_PORT_RESET: 2285 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2286 break; 2287 default: 2288 err = USBD_IOERROR; 2289 goto ret; 2290 } 2291 2292 break; 2293 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2294 if (len == 0) 2295 break; 2296 if ((value & 0xff) != 0) { 2297 err = USBD_IOERROR; 2298 goto ret; 2299 } 2300 hubd = xhci_hubd; 2301 hubd.bNbrPorts = sc->sc_hs_port_count; 2302 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2303 hubd.bPwrOn2PwrGood = 200; 2304 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 2305 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2306 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2307 l = min(len, hubd.bDescLength); 2308 totlen = l; 2309 memcpy(buf, &hubd, l); 2310 break; 2311 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2312 if (len != 4) { 2313 err = USBD_IOERROR; 2314 goto ret; 2315 } 2316 memset(buf, 0, len); /* ? XXX */ 2317 totlen = len; 2318 break; 2319 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2320 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2321 if (index < 1 || index > sc->sc_maxports) { 2322 err = USBD_IOERROR; 2323 goto ret; 2324 } 2325 if (len != 4) { 2326 err = USBD_IOERROR; 2327 goto ret; 2328 } 2329 v = xhci_op_read_4(sc, XHCI_PORTSC(sc->sc_hs_port_start - 1 + 2330 index)); 2331 DPRINTFN(4, "READ_CLASS_OTHER GET_STATUS PORTSC %d (%d) %08x", 2332 index, sc->sc_hs_port_start - 1 + index, v, 0); 2333 switch (XHCI_PS_SPEED_GET(v)) { 2334 case 1: 2335 i = UPS_FULL_SPEED; 2336 break; 2337 case 2: 2338 i = UPS_LOW_SPEED; 2339 break; 2340 case 3: 2341 i = UPS_HIGH_SPEED; 2342 break; 2343 default: 2344 i = 0; 2345 break; 2346 } 2347 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2348 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2349 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2350 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 2351 if (v & XHCI_PS_PR) i |= UPS_RESET; 2352 if (v & XHCI_PS_PP) i |= UPS_PORT_POWER; 2353 USETW(ps.wPortStatus, i); 2354 i = 0; 2355 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2356 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2357 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2358 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2359 USETW(ps.wPortChange, i); 2360 l = min(len, sizeof ps); 2361 memcpy(buf, &ps, l); 2362 totlen = l; 2363 break; 2364 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2365 err = USBD_IOERROR; 2366 goto ret; 2367 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2368 break; 2369 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2370 if (index < 1 || index > sc->sc_hs_port_count) { 2371 err = USBD_IOERROR; 2372 goto ret; 2373 } 2374 port = XHCI_PORTSC(sc->sc_hs_port_start - 1 + index); 2375 v = xhci_op_read_4(sc, port); 2376 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2377 v &= ~XHCI_PS_CLEAR; 2378 switch (value) { 2379 case UHF_PORT_ENABLE: 2380 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 2381 break; 2382 case UHF_PORT_SUSPEND: 2383 /* XXX suspend */ 2384 break; 2385 case UHF_PORT_RESET: 2386 v &= ~ (XHCI_PS_PED | XHCI_PS_PR); 2387 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 2388 /* Wait for reset to complete. */ 2389 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2390 if (sc->sc_dying) { 2391 err = USBD_IOERROR; 2392 goto ret; 2393 } 2394 v = xhci_op_read_4(sc, port); 2395 if (v & XHCI_PS_PR) { 2396 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 2397 usb_delay_ms(&sc->sc_bus, 10); 2398 /* XXX */ 2399 } 2400 break; 2401 case UHF_PORT_POWER: 2402 /* XXX power control */ 2403 break; 2404 /* XXX more */ 2405 case UHF_C_PORT_RESET: 2406 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2407 break; 2408 default: 2409 err = USBD_IOERROR; 2410 goto ret; 2411 } 2412 break; 2413 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2414 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2415 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2416 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2417 break; 2418 default: 2419 err = USBD_IOERROR; 2420 goto ret; 2421 } 2422 xfer->ux_actlen = totlen; 2423 err = USBD_NORMAL_COMPLETION; 2424 ret: 2425 xfer->ux_status = err; 2426 mutex_enter(&sc->sc_lock); 2427 usb_transfer_complete(xfer); 2428 mutex_exit(&sc->sc_lock); 2429 return USBD_IN_PROGRESS; 2430 } 2431 2432 2433 static void 2434 xhci_root_ctrl_abort(usbd_xfer_handle xfer) 2435 { 2436 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2437 /* Nothing to do, all transfers are synchronous. */ 2438 } 2439 2440 2441 static void 2442 xhci_root_ctrl_close(usbd_pipe_handle pipe) 2443 { 2444 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2445 /* Nothing to do. */ 2446 } 2447 2448 static void 2449 xhci_root_ctrl_done(usbd_xfer_handle xfer) 2450 { 2451 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2452 2453 xfer->ux_hcpriv = NULL; 2454 } 2455 2456 /* root hub interrupt */ 2457 2458 static usbd_status 2459 xhci_root_intr_transfer(usbd_xfer_handle xfer) 2460 { 2461 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2462 usbd_status err; 2463 2464 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2465 2466 /* Insert last in queue. */ 2467 mutex_enter(&sc->sc_lock); 2468 err = usb_insert_transfer(xfer); 2469 mutex_exit(&sc->sc_lock); 2470 if (err) 2471 return err; 2472 2473 /* Pipe isn't running, start first */ 2474 return (xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 2475 } 2476 2477 static usbd_status 2478 xhci_root_intr_start(usbd_xfer_handle xfer) 2479 { 2480 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2481 2482 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2483 2484 if (sc->sc_dying) 2485 return USBD_IOERROR; 2486 2487 mutex_enter(&sc->sc_lock); 2488 sc->sc_intrxfer = xfer; 2489 mutex_exit(&sc->sc_lock); 2490 2491 return USBD_IN_PROGRESS; 2492 } 2493 2494 static void 2495 xhci_root_intr_abort(usbd_xfer_handle xfer) 2496 { 2497 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2498 2499 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2500 2501 KASSERT(mutex_owned(&sc->sc_lock)); 2502 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2503 2504 DPRINTFN(1, "remove", 0, 0, 0, 0); 2505 2506 sc->sc_intrxfer = NULL; 2507 2508 xfer->ux_status = USBD_CANCELLED; 2509 usb_transfer_complete(xfer); 2510 } 2511 2512 static void 2513 xhci_root_intr_close(usbd_pipe_handle pipe) 2514 { 2515 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 2516 2517 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2518 2519 KASSERT(mutex_owned(&sc->sc_lock)); 2520 2521 sc->sc_intrxfer = NULL; 2522 } 2523 2524 static void 2525 xhci_root_intr_done(usbd_xfer_handle xfer) 2526 { 2527 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2528 2529 xfer->ux_hcpriv = NULL; 2530 } 2531 2532 /* -------------- */ 2533 /* device control */ 2534 2535 static usbd_status 2536 xhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2537 { 2538 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2539 usbd_status err; 2540 2541 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2542 2543 /* Insert last in queue. */ 2544 mutex_enter(&sc->sc_lock); 2545 err = usb_insert_transfer(xfer); 2546 mutex_exit(&sc->sc_lock); 2547 if (err) 2548 return (err); 2549 2550 /* Pipe isn't running, start first */ 2551 return (xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 2552 } 2553 2554 static usbd_status 2555 xhci_device_ctrl_start(usbd_xfer_handle xfer) 2556 { 2557 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2558 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 2559 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 2560 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2561 struct xhci_xfer * const xx = (void *)xfer; 2562 usb_device_request_t * const req = &xfer->ux_request; 2563 const bool isread = UT_GET_DIR(req->bmRequestType) == UT_READ; 2564 const uint32_t len = UGETW(req->wLength); 2565 usb_dma_t * const dma = &xfer->ux_dmabuf; 2566 uint64_t parameter; 2567 uint32_t status; 2568 uint32_t control; 2569 u_int i; 2570 2571 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2572 DPRINTFN(12, "req: %04x %04x %04x %04x", 2573 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 2574 UGETW(req->wIndex), UGETW(req->wLength)); 2575 2576 /* XXX */ 2577 if (tr->is_halted) { 2578 xhci_reset_endpoint(xfer->ux_pipe); 2579 tr->is_halted = false; 2580 xhci_set_dequeue(xfer->ux_pipe); 2581 } 2582 2583 /* we rely on the bottom bits for extra info */ 2584 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 2585 2586 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 2587 2588 i = 0; 2589 2590 /* setup phase */ 2591 memcpy(¶meter, req, sizeof(*req)); 2592 parameter = le64toh(parameter); 2593 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 2594 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 2595 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 2596 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 2597 XHCI_TRB_3_IDT_BIT; 2598 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2599 2600 if (len == 0) 2601 goto no_data; 2602 2603 /* data phase */ 2604 parameter = DMAADDR(dma, 0); 2605 KASSERT(len <= 0x10000); 2606 status = XHCI_TRB_2_IRQ_SET(0) | 2607 XHCI_TRB_2_TDSZ_SET(1) | 2608 XHCI_TRB_2_BYTES_SET(len); 2609 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 2610 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 2611 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 2612 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2613 2614 parameter = (uintptr_t)xfer | 0x3; 2615 status = XHCI_TRB_2_IRQ_SET(0); 2616 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 2617 XHCI_TRB_3_IOC_BIT; 2618 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2619 2620 no_data: 2621 parameter = 0; 2622 status = XHCI_TRB_2_IRQ_SET(0); 2623 /* the status stage has inverted direction */ 2624 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 2625 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 2626 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 2627 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2628 2629 parameter = (uintptr_t)xfer | 0x0; 2630 status = XHCI_TRB_2_IRQ_SET(0); 2631 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 2632 XHCI_TRB_3_IOC_BIT; 2633 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2634 2635 mutex_enter(&tr->xr_lock); 2636 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2637 mutex_exit(&tr->xr_lock); 2638 2639 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2640 2641 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2642 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2643 xhci_timeout, xfer); 2644 } 2645 2646 if (sc->sc_bus.ub_usepolling) { 2647 DPRINTFN(1, "polling", 0, 0, 0, 0); 2648 //xhci_waitintr(sc, xfer); 2649 } 2650 2651 return USBD_IN_PROGRESS; 2652 } 2653 2654 static void 2655 xhci_device_ctrl_done(usbd_xfer_handle xfer) 2656 { 2657 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2658 2659 callout_stop(&xfer->ux_callout); /* XXX wrong place */ 2660 2661 } 2662 2663 static void 2664 xhci_device_ctrl_abort(usbd_xfer_handle xfer) 2665 { 2666 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2667 } 2668 2669 static void 2670 xhci_device_ctrl_close(usbd_pipe_handle pipe) 2671 { 2672 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2673 } 2674 2675 /* ----------------- */ 2676 /* device isochronus */ 2677 2678 /* ----------- */ 2679 /* device bulk */ 2680 2681 static usbd_status 2682 xhci_device_bulk_transfer(usbd_xfer_handle xfer) 2683 { 2684 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2685 usbd_status err; 2686 2687 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2688 2689 /* Insert last in queue. */ 2690 mutex_enter(&sc->sc_lock); 2691 err = usb_insert_transfer(xfer); 2692 mutex_exit(&sc->sc_lock); 2693 if (err) 2694 return err; 2695 2696 /* 2697 * Pipe isn't running (otherwise err would be USBD_INPROG), 2698 * so start it first. 2699 */ 2700 return (xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 2701 } 2702 2703 static usbd_status 2704 xhci_device_bulk_start(usbd_xfer_handle xfer) 2705 { 2706 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2707 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 2708 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 2709 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2710 struct xhci_xfer * const xx = (void *)xfer; 2711 const uint32_t len = xfer->ux_length; 2712 usb_dma_t * const dma = &xfer->ux_dmabuf; 2713 uint64_t parameter; 2714 uint32_t status; 2715 uint32_t control; 2716 u_int i = 0; 2717 2718 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2719 2720 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 2721 2722 if (sc->sc_dying) 2723 return USBD_IOERROR; 2724 2725 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 2726 2727 parameter = DMAADDR(dma, 0); 2728 /* 2729 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 2730 * If the user supplied buffer crosses such a boundary then 2 2731 * (or more) TRB should be used. 2732 * If multiple TRB are used the td_size field must be set correctly. 2733 * For v1.0 devices (like ivy bridge) this is the number of usb data 2734 * blocks needed to complete the transfer. 2735 * Setting it to 1 in the last TRB causes an extra zero-length 2736 * data block be sent. 2737 * The earlier documentation differs, I don't know how it behaves. 2738 */ 2739 KASSERT(len <= 0x10000); 2740 status = XHCI_TRB_2_IRQ_SET(0) | 2741 XHCI_TRB_2_TDSZ_SET(1) | 2742 XHCI_TRB_2_BYTES_SET(len); 2743 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 2744 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 2745 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2746 2747 mutex_enter(&tr->xr_lock); 2748 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2749 mutex_exit(&tr->xr_lock); 2750 2751 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2752 2753 if (sc->sc_bus.ub_usepolling) { 2754 DPRINTFN(1, "polling", 0, 0, 0, 0); 2755 //xhci_waitintr(sc, xfer); 2756 } 2757 2758 return USBD_IN_PROGRESS; 2759 } 2760 2761 static void 2762 xhci_device_bulk_done(usbd_xfer_handle xfer) 2763 { 2764 #ifdef USB_DEBUG 2765 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 2766 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 2767 #endif 2768 const u_int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2769 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2770 2771 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2772 2773 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 2774 2775 callout_stop(&xfer->ux_callout); /* XXX wrong place */ 2776 2777 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 2778 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2779 2780 2781 } 2782 2783 static void 2784 xhci_device_bulk_abort(usbd_xfer_handle xfer) 2785 { 2786 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2787 } 2788 2789 static void 2790 xhci_device_bulk_close(usbd_pipe_handle pipe) 2791 { 2792 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2793 } 2794 2795 /* --------------- */ 2796 /* device intrrupt */ 2797 2798 static usbd_status 2799 xhci_device_intr_transfer(usbd_xfer_handle xfer) 2800 { 2801 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2802 usbd_status err; 2803 2804 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2805 2806 /* Insert last in queue. */ 2807 mutex_enter(&sc->sc_lock); 2808 err = usb_insert_transfer(xfer); 2809 mutex_exit(&sc->sc_lock); 2810 if (err) 2811 return err; 2812 2813 /* 2814 * Pipe isn't running (otherwise err would be USBD_INPROG), 2815 * so start it first. 2816 */ 2817 return (xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 2818 } 2819 2820 static usbd_status 2821 xhci_device_intr_start(usbd_xfer_handle xfer) 2822 { 2823 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2824 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 2825 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 2826 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2827 struct xhci_xfer * const xx = (void *)xfer; 2828 const uint32_t len = xfer->ux_length; 2829 usb_dma_t * const dma = &xfer->ux_dmabuf; 2830 uint64_t parameter; 2831 uint32_t status; 2832 uint32_t control; 2833 u_int i = 0; 2834 2835 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2836 2837 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 2838 2839 if (sc->sc_dying) 2840 return USBD_IOERROR; 2841 2842 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 2843 2844 parameter = DMAADDR(dma, 0); 2845 KASSERT(len <= 0x10000); 2846 status = XHCI_TRB_2_IRQ_SET(0) | 2847 XHCI_TRB_2_TDSZ_SET(1) | 2848 XHCI_TRB_2_BYTES_SET(len); 2849 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 2850 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 2851 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2852 2853 mutex_enter(&tr->xr_lock); 2854 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2855 mutex_exit(&tr->xr_lock); 2856 2857 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2858 2859 if (sc->sc_bus.ub_usepolling) { 2860 DPRINTFN(1, "polling", 0, 0, 0, 0); 2861 //xhci_waitintr(sc, xfer); 2862 } 2863 2864 return USBD_IN_PROGRESS; 2865 } 2866 2867 static void 2868 xhci_device_intr_done(usbd_xfer_handle xfer) 2869 { 2870 struct xhci_softc * const sc __diagused = 2871 xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2872 #ifdef USB_DEBUG 2873 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 2874 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 2875 #endif 2876 const u_int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2877 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2878 2879 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2880 2881 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 2882 2883 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2884 2885 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 2886 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2887 2888 #if 0 2889 device_printf(sc->sc_dev, ""); 2890 for (size_t i = 0; i < xfer->ux_length; i++) { 2891 printf(" %02x", ((uint8_t const *)xfer->ux_buffer)[i]); 2892 } 2893 printf("\n"); 2894 #endif 2895 2896 if (xfer->ux_pipe->up_repeat) { 2897 xfer->ux_status = xhci_device_intr_start(xfer); 2898 } else { 2899 callout_stop(&xfer->ux_callout); /* XXX */ 2900 } 2901 2902 } 2903 2904 static void 2905 xhci_device_intr_abort(usbd_xfer_handle xfer) 2906 { 2907 struct xhci_softc * const sc __diagused = 2908 xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2909 2910 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2911 2912 KASSERT(mutex_owned(&sc->sc_lock)); 2913 DPRINTFN(15, "%p", xfer, 0, 0, 0); 2914 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2915 xfer->ux_status = USBD_CANCELLED; 2916 usb_transfer_complete(xfer); 2917 } 2918 2919 static void 2920 xhci_device_intr_close(usbd_pipe_handle pipe) 2921 { 2922 //struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 2923 2924 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2925 DPRINTFN(15, "%p", pipe, 0, 0, 0); 2926 2927 xhci_unconfigure_endpoint(pipe); 2928 } 2929 2930 /* ------------ */ 2931 2932 static void 2933 xhci_timeout(void *addr) 2934 { 2935 struct xhci_xfer * const xx = addr; 2936 usbd_xfer_handle const xfer = &xx->xx_xfer; 2937 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2938 2939 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2940 2941 if (sc->sc_dying) { 2942 return; 2943 } 2944 2945 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 2946 USB_TASKQ_MPSAFE); 2947 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 2948 USB_TASKQ_HC); 2949 } 2950 2951 static void 2952 xhci_timeout_task(void *addr) 2953 { 2954 usbd_xfer_handle const xfer = addr; 2955 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2956 2957 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2958 2959 mutex_enter(&sc->sc_lock); 2960 #if 0 2961 xhci_abort_xfer(xfer, USBD_TIMEOUT); 2962 #else 2963 xfer->ux_status = USBD_TIMEOUT; 2964 usb_transfer_complete(xfer); 2965 #endif 2966 mutex_exit(&sc->sc_lock); 2967 } 2968
Indexes created Wed Oct 01 18:09:54 GMT 2025