xhci.c revision 1.28.2.20
1 /* $NetBSD: xhci.c,v 1.28.2.20 2015/04/07 06:52:03 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.28.2.20 2015/04/07 06:52:03 skrll Exp $"); 31 32 #include "opt_usb.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/kmem.h> 38 #include <sys/device.h> 39 #include <sys/select.h> 40 #include <sys/proc.h> 41 #include <sys/queue.h> 42 #include <sys/mutex.h> 43 #include <sys/condvar.h> 44 #include <sys/bus.h> 45 #include <sys/cpu.h> 46 #include <sys/sysctl.h> 47 48 #include <machine/endian.h> 49 50 #include <dev/usb/usb.h> 51 #include <dev/usb/usbdi.h> 52 #include <dev/usb/usbdivar.h> 53 #include <dev/usb/usbdi_util.h> 54 #include <dev/usb/usbhist.h> 55 #include <dev/usb/usb_mem.h> 56 #include <dev/usb/usb_quirks.h> 57 58 #include <dev/usb/xhcireg.h> 59 #include <dev/usb/xhcivar.h> 60 #include <dev/usb/usbroothub.h> 61 62 63 #ifdef USB_DEBUG 64 #ifndef XHCI_DEBUG 65 #define xhcidebug 0 66 #else /* !XHCI_DEBUG */ 67 static int xhcidebug = 0; 68 69 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 70 { 71 int err; 72 const struct sysctlnode *rnode; 73 const struct sysctlnode *cnode; 74 75 err = sysctl_createv(clog, 0, NULL, &rnode, 76 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 77 SYSCTL_DESCR("xhci global controls"), 78 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 79 80 if (err) 81 goto fail; 82 83 /* control debugging printfs */ 84 err = sysctl_createv(clog, 0, &rnode, &cnode, 85 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 86 "debug", SYSCTL_DESCR("Enable debugging output"), 87 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 88 if (err) 89 goto fail; 90 91 return; 92 fail: 93 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 94 } 95 96 #endif /* !XHCI_DEBUG */ 97 #endif /* USB_DEBUG */ 98 99 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 100 #define XHCIHIST_FUNC() USBHIST_FUNC() 101 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 102 103 #define XHCI_DCI_SLOT 0 104 #define XHCI_DCI_EP_CONTROL 1 105 106 #define XHCI_ICI_INPUT_CONTROL 0 107 108 struct xhci_pipe { 109 struct usbd_pipe xp_pipe; 110 }; 111 112 #define XHCI_COMMAND_RING_TRBS 256 113 #define XHCI_EVENT_RING_TRBS 256 114 #define XHCI_EVENT_RING_SEGMENTS 1 115 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 116 117 static usbd_status xhci_open(struct usbd_pipe *); 118 static int xhci_intr1(struct xhci_softc * const); 119 static void xhci_softintr(void *); 120 static void xhci_poll(struct usbd_bus *); 121 static struct usbd_xfer *xhci_allocx(struct usbd_bus *); 122 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 123 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 124 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 125 struct usbd_port *); 126 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 127 void *, int); 128 129 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 130 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 131 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 132 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 133 134 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 135 136 static usbd_status xhci_do_command(struct xhci_softc * const, 137 struct xhci_trb * const, int); 138 static usbd_status xhci_do_command1(struct xhci_softc * const, 139 struct xhci_trb * const, int, int); 140 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 141 struct xhci_trb * const, int); 142 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t, int, int); 143 static usbd_status xhci_enable_slot(struct xhci_softc * const, 144 uint8_t * const); 145 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 146 static usbd_status xhci_address_device(struct xhci_softc * const, 147 uint64_t, uint8_t, bool); 148 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 149 struct xhci_slot * const, u_int); 150 static usbd_status xhci_ring_init(struct xhci_softc * const, 151 struct xhci_ring * const, size_t, size_t); 152 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 153 154 static void xhci_noop(struct usbd_pipe *); 155 156 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 157 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 158 static void xhci_root_intr_abort(struct usbd_xfer *); 159 static void xhci_root_intr_close(struct usbd_pipe *); 160 static void xhci_root_intr_done(struct usbd_xfer *); 161 162 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 163 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 164 static void xhci_device_ctrl_abort(struct usbd_xfer *); 165 static void xhci_device_ctrl_close(struct usbd_pipe *); 166 static void xhci_device_ctrl_done(struct usbd_xfer *); 167 168 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 169 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 170 static void xhci_device_intr_abort(struct usbd_xfer *); 171 static void xhci_device_intr_close(struct usbd_pipe *); 172 static void xhci_device_intr_done(struct usbd_xfer *); 173 174 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 175 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 176 static void xhci_device_bulk_abort(struct usbd_xfer *); 177 static void xhci_device_bulk_close(struct usbd_pipe *); 178 static void xhci_device_bulk_done(struct usbd_xfer *); 179 180 static void xhci_timeout(void *); 181 static void xhci_timeout_task(void *); 182 183 static const struct usbd_bus_methods xhci_bus_methods = { 184 .ubm_open = xhci_open, 185 .ubm_softint = xhci_softintr, 186 .ubm_dopoll = xhci_poll, 187 .ubm_allocx = xhci_allocx, 188 .ubm_freex = xhci_freex, 189 .ubm_getlock = xhci_get_lock, 190 .ubm_newdev = xhci_new_device, 191 .ubm_rhctrl = xhci_roothub_ctrl, 192 }; 193 194 static const struct usbd_pipe_methods xhci_root_intr_methods = { 195 .upm_transfer = xhci_root_intr_transfer, 196 .upm_start = xhci_root_intr_start, 197 .upm_abort = xhci_root_intr_abort, 198 .upm_close = xhci_root_intr_close, 199 .upm_cleartoggle = xhci_noop, 200 .upm_done = xhci_root_intr_done, 201 }; 202 203 204 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 205 .upm_transfer = xhci_device_ctrl_transfer, 206 .upm_start = xhci_device_ctrl_start, 207 .upm_abort = xhci_device_ctrl_abort, 208 .upm_close = xhci_device_ctrl_close, 209 .upm_cleartoggle = xhci_noop, 210 .upm_done = xhci_device_ctrl_done, 211 }; 212 213 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 214 .upm_cleartoggle = xhci_noop, 215 }; 216 217 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 218 .upm_transfer = xhci_device_bulk_transfer, 219 .upm_start = xhci_device_bulk_start, 220 .upm_abort = xhci_device_bulk_abort, 221 .upm_close = xhci_device_bulk_close, 222 .upm_cleartoggle = xhci_noop, 223 .upm_done = xhci_device_bulk_done, 224 }; 225 226 static const struct usbd_pipe_methods xhci_device_intr_methods = { 227 .upm_transfer = xhci_device_intr_transfer, 228 .upm_start = xhci_device_intr_start, 229 .upm_abort = xhci_device_intr_abort, 230 .upm_close = xhci_device_intr_close, 231 .upm_cleartoggle = xhci_noop, 232 .upm_done = xhci_device_intr_done, 233 }; 234 235 static inline uint32_t 236 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 237 { 238 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 239 } 240 241 static inline uint32_t 242 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 243 { 244 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 245 } 246 247 static inline void 248 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 249 uint32_t value) 250 { 251 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 252 } 253 254 #if 0 /* unused */ 255 static inline void 256 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 257 uint32_t value) 258 { 259 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 260 } 261 #endif /* unused */ 262 263 static inline uint32_t 264 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 265 { 266 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 267 } 268 269 static inline uint32_t 270 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 271 { 272 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 273 } 274 275 static inline void 276 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 277 uint32_t value) 278 { 279 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 280 } 281 282 #if 0 /* unused */ 283 static inline uint64_t 284 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 285 { 286 uint64_t value; 287 288 if (sc->sc_ac64) { 289 #ifdef XHCI_USE_BUS_SPACE_8 290 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 291 #else 292 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 293 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 294 offset + 4) << 32; 295 #endif 296 } else { 297 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 298 } 299 300 return value; 301 } 302 #endif /* unused */ 303 304 static inline void 305 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 306 uint64_t value) 307 { 308 if (sc->sc_ac64) { 309 #ifdef XHCI_USE_BUS_SPACE_8 310 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 311 #else 312 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 313 (value >> 0) & 0xffffffff); 314 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 315 (value >> 32) & 0xffffffff); 316 #endif 317 } else { 318 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 319 } 320 } 321 322 static inline uint32_t 323 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 324 { 325 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 326 } 327 328 static inline void 329 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 330 uint32_t value) 331 { 332 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 333 } 334 335 #if 0 /* unused */ 336 static inline uint64_t 337 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 338 { 339 uint64_t value; 340 341 if (sc->sc_ac64) { 342 #ifdef XHCI_USE_BUS_SPACE_8 343 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 344 #else 345 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 346 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 347 offset + 4) << 32; 348 #endif 349 } else { 350 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 351 } 352 353 return value; 354 } 355 #endif /* unused */ 356 357 static inline void 358 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 359 uint64_t value) 360 { 361 if (sc->sc_ac64) { 362 #ifdef XHCI_USE_BUS_SPACE_8 363 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 364 #else 365 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 366 (value >> 0) & 0xffffffff); 367 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 368 (value >> 32) & 0xffffffff); 369 #endif 370 } else { 371 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 372 } 373 } 374 375 #if 0 /* unused */ 376 static inline uint32_t 377 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 378 { 379 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 380 } 381 #endif /* unused */ 382 383 static inline void 384 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 385 uint32_t value) 386 { 387 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 388 } 389 390 /* --- */ 391 392 static inline uint8_t 393 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 394 { 395 u_int eptype = 0; 396 397 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 398 case UE_CONTROL: 399 eptype = 0x0; 400 break; 401 case UE_ISOCHRONOUS: 402 eptype = 0x1; 403 break; 404 case UE_BULK: 405 eptype = 0x2; 406 break; 407 case UE_INTERRUPT: 408 eptype = 0x3; 409 break; 410 } 411 412 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 413 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 414 return eptype | 0x4; 415 else 416 return eptype; 417 } 418 419 static u_int 420 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 421 { 422 /* xHCI 1.0 section 4.5.1 */ 423 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 424 u_int in = 0; 425 426 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 427 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 428 in = 1; 429 430 return epaddr * 2 + in; 431 } 432 433 static inline u_int 434 xhci_dci_to_ici(const u_int i) 435 { 436 return i + 1; 437 } 438 439 static inline void * 440 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 441 const u_int dci) 442 { 443 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 444 } 445 446 #if 0 /* unused */ 447 static inline bus_addr_t 448 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 449 const u_int dci) 450 { 451 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 452 } 453 #endif /* unused */ 454 455 static inline void * 456 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 457 const u_int ici) 458 { 459 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 460 } 461 462 static inline bus_addr_t 463 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 464 const u_int ici) 465 { 466 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 467 } 468 469 static inline struct xhci_trb * 470 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 471 { 472 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 473 } 474 475 static inline bus_addr_t 476 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 477 { 478 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 479 } 480 481 static inline void 482 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 483 uint32_t control) 484 { 485 trb->trb_0 = parameter; 486 trb->trb_2 = status; 487 trb->trb_3 = control; 488 } 489 490 /* --- */ 491 492 void 493 xhci_childdet(device_t self, device_t child) 494 { 495 struct xhci_softc * const sc = device_private(self); 496 497 KASSERT(sc->sc_child == child); 498 if (child == sc->sc_child) 499 sc->sc_child = NULL; 500 } 501 502 int 503 xhci_detach(struct xhci_softc *sc, int flags) 504 { 505 int rv = 0; 506 507 if (sc->sc_child != NULL) 508 rv = config_detach(sc->sc_child, flags); 509 510 if (rv != 0) 511 return rv; 512 513 /* XXX unconfigure/free slots */ 514 515 /* verify: */ 516 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 517 xhci_op_write_4(sc, XHCI_USBCMD, 0); 518 /* do we need to wait for stop? */ 519 520 xhci_op_write_8(sc, XHCI_CRCR, 0); 521 xhci_ring_free(sc, &sc->sc_cr); 522 cv_destroy(&sc->sc_command_cv); 523 524 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 525 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 526 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 527 xhci_ring_free(sc, &sc->sc_er); 528 529 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 530 531 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 532 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 533 534 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 535 536 mutex_destroy(&sc->sc_lock); 537 mutex_destroy(&sc->sc_intr_lock); 538 cv_destroy(&sc->sc_softwake_cv); 539 540 pool_cache_destroy(sc->sc_xferpool); 541 542 return rv; 543 } 544 545 int 546 xhci_activate(device_t self, enum devact act) 547 { 548 struct xhci_softc * const sc = device_private(self); 549 550 switch (act) { 551 case DVACT_DEACTIVATE: 552 sc->sc_dying = true; 553 return 0; 554 default: 555 return EOPNOTSUPP; 556 } 557 } 558 559 bool 560 xhci_suspend(device_t dv, const pmf_qual_t *qual) 561 { 562 return false; 563 } 564 565 bool 566 xhci_resume(device_t dv, const pmf_qual_t *qual) 567 { 568 return false; 569 } 570 571 bool 572 xhci_shutdown(device_t self, int flags) 573 { 574 return false; 575 } 576 577 578 static void 579 hexdump(const char *msg, const void *base, size_t len) 580 { 581 #if 0 582 size_t cnt; 583 const uint32_t *p; 584 extern paddr_t vtophys(vaddr_t); 585 586 p = base; 587 cnt = 0; 588 589 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 590 (void *)vtophys((vaddr_t)base)); 591 592 while (cnt < len) { 593 if (cnt % 16 == 0) 594 printf("%p: ", p); 595 else if (cnt % 8 == 0) 596 printf(" |"); 597 printf(" %08x", *p++); 598 cnt += 4; 599 if (cnt % 16 == 0) 600 printf("\n"); 601 } 602 #endif 603 } 604 605 606 int 607 xhci_init(struct xhci_softc *sc) 608 { 609 bus_size_t bsz; 610 uint32_t cap, hcs1, hcs2, hcc, dboff, rtsoff; 611 uint32_t ecp, ecr; 612 uint32_t usbcmd, usbsts, pagesize, config; 613 int i; 614 uint16_t hciversion; 615 uint8_t caplength; 616 617 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 618 619 /* XXX Low/Full/High speeds for now */ 620 sc->sc_bus.ub_revision = USBREV_2_0; 621 sc->sc_bus.ub_usedma = true; 622 623 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 624 caplength = XHCI_CAP_CAPLENGTH(cap); 625 hciversion = XHCI_CAP_HCIVERSION(cap); 626 627 if ((hciversion < 0x0096) || (hciversion > 0x0100)) { 628 aprint_normal_dev(sc->sc_dev, 629 "xHCI version %x.%x not known to be supported\n", 630 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 631 } else { 632 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 633 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 634 } 635 636 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 637 &sc->sc_cbh) != 0) { 638 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 639 return ENOMEM; 640 } 641 642 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 643 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 644 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 645 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 646 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 647 (void)xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 648 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 649 650 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 651 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 652 aprint_debug_dev(sc->sc_dev, "ac64 %d ctxsz %d\n", sc->sc_ac64, 653 sc->sc_ctxsz); 654 655 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 656 ecp = XHCI_HCC_XECP(hcc) * 4; 657 while (ecp != 0) { 658 ecr = xhci_read_4(sc, ecp); 659 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 660 switch (XHCI_XECP_ID(ecr)) { 661 case XHCI_ID_PROTOCOLS: { 662 uint32_t w0, w4, w8; 663 uint16_t w2; 664 w0 = xhci_read_4(sc, ecp + 0); 665 w2 = (w0 >> 16) & 0xffff; 666 w4 = xhci_read_4(sc, ecp + 4); 667 w8 = xhci_read_4(sc, ecp + 8); 668 aprint_debug_dev(sc->sc_dev, "SP: %08x %08x %08x\n", 669 w0, w4, w8); 670 if (w4 == 0x20425355 && w2 == 0x0300) { 671 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 672 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 673 } 674 if (w4 == 0x20425355 && w2 == 0x0200) { 675 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 676 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 677 } 678 break; 679 } 680 case XHCI_ID_USB_LEGACY: { 681 uint8_t bios_sem; 682 683 /* Take host controller from BIOS */ 684 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 685 if (bios_sem) { 686 /* sets xHCI to be owned by OS */ 687 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 688 aprint_debug( 689 "waiting for BIOS to give up control\n"); 690 for (i = 0; i < 5000; i++) { 691 bios_sem = xhci_read_1(sc, ecp + 692 XHCI_XECP_BIOS_SEM); 693 if (bios_sem == 0) 694 break; 695 DELAY(1000); 696 } 697 if (bios_sem) 698 printf("timed out waiting for BIOS\n"); 699 } 700 break; 701 } 702 default: 703 break; 704 } 705 ecr = xhci_read_4(sc, ecp); 706 if (XHCI_XECP_NEXT(ecr) == 0) { 707 ecp = 0; 708 } else { 709 ecp += XHCI_XECP_NEXT(ecr) * 4; 710 } 711 } 712 713 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 714 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 715 &sc->sc_obh) != 0) { 716 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 717 return ENOMEM; 718 } 719 720 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 721 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 722 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 723 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 724 return ENOMEM; 725 } 726 727 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 728 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 729 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 730 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 731 return ENOMEM; 732 } 733 734 for (i = 0; i < 100; i++) { 735 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 736 if ((usbsts & XHCI_STS_CNR) == 0) 737 break; 738 usb_delay_ms(&sc->sc_bus, 1); 739 } 740 if (i >= 100) 741 return EIO; 742 743 usbcmd = 0; 744 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 745 usb_delay_ms(&sc->sc_bus, 1); 746 747 usbcmd = XHCI_CMD_HCRST; 748 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 749 for (i = 0; i < 100; i++) { 750 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 751 if ((usbcmd & XHCI_CMD_HCRST) == 0) 752 break; 753 usb_delay_ms(&sc->sc_bus, 1); 754 } 755 if (i >= 100) 756 return EIO; 757 758 for (i = 0; i < 100; i++) { 759 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 760 if ((usbsts & XHCI_STS_CNR) == 0) 761 break; 762 usb_delay_ms(&sc->sc_bus, 1); 763 } 764 if (i >= 100) 765 return EIO; 766 767 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 768 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 769 pagesize = ffs(pagesize); 770 if (pagesize == 0) 771 return EIO; 772 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 773 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 774 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 775 (uint32_t)sc->sc_maxslots); 776 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 777 778 usbd_status err; 779 780 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 781 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 782 if (sc->sc_maxspbuf != 0) { 783 err = usb_allocmem(&sc->sc_bus, 784 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 785 &sc->sc_spbufarray_dma); 786 if (err) 787 return err; 788 789 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * sc->sc_maxspbuf, KM_SLEEP); 790 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 791 for (i = 0; i < sc->sc_maxspbuf; i++) { 792 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 793 /* allocate contexts */ 794 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 795 sc->sc_pgsz, dma); 796 if (err) 797 return err; 798 spbufarray[i] = htole64(DMAADDR(dma, 0)); 799 usb_syncmem(dma, 0, sc->sc_pgsz, 800 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 801 } 802 803 usb_syncmem(&sc->sc_spbufarray_dma, 0, 804 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 805 } 806 807 config = xhci_op_read_4(sc, XHCI_CONFIG); 808 config &= ~0xFF; 809 config |= sc->sc_maxslots & 0xFF; 810 xhci_op_write_4(sc, XHCI_CONFIG, config); 811 812 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 813 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 814 if (err) { 815 aprint_error_dev(sc->sc_dev, "command ring init fail\n"); 816 return err; 817 } 818 819 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 820 XHCI_EVENT_RING_SEGMENTS_ALIGN); 821 if (err) { 822 aprint_error_dev(sc->sc_dev, "event ring init fail\n"); 823 return err; 824 } 825 826 usb_dma_t *dma; 827 size_t size; 828 size_t align; 829 830 dma = &sc->sc_eventst_dma; 831 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 832 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 833 KASSERT(size <= (512 * 1024)); 834 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 835 err = usb_allocmem(&sc->sc_bus, size, align, dma); 836 837 memset(KERNADDR(dma, 0), 0, size); 838 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 839 aprint_debug_dev(sc->sc_dev, "eventst: %s %016jx %p %zx\n", 840 usbd_errstr(err), 841 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 842 KERNADDR(&sc->sc_eventst_dma, 0), 843 sc->sc_eventst_dma.udma_block->size); 844 845 dma = &sc->sc_dcbaa_dma; 846 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 847 KASSERT(size <= 2048); 848 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 849 err = usb_allocmem(&sc->sc_bus, size, align, dma); 850 851 memset(KERNADDR(dma, 0), 0, size); 852 if (sc->sc_maxspbuf != 0) { 853 /* 854 * DCBA entry 0 hold the scratchbuf array pointer. 855 */ 856 *(uint64_t *)KERNADDR(dma, 0) = 857 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 858 } 859 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 860 aprint_debug_dev(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n", 861 usbd_errstr(err), 862 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 863 KERNADDR(&sc->sc_dcbaa_dma, 0), 864 sc->sc_dcbaa_dma.udma_block->size); 865 866 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 867 KM_SLEEP); 868 869 cv_init(&sc->sc_command_cv, "xhcicmd"); 870 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 871 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 872 cv_init(&sc->sc_softwake_cv, "xhciab"); 873 874 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 875 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 876 877 /* Set up the bus struct. */ 878 sc->sc_bus.ub_methods = &xhci_bus_methods; 879 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 880 881 struct xhci_erste *erst; 882 erst = KERNADDR(&sc->sc_eventst_dma, 0); 883 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 884 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 885 erst[0].erste_3 = htole32(0); 886 usb_syncmem(&sc->sc_eventst_dma, 0, 887 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 888 889 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 890 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 891 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 892 XHCI_ERDP_LO_BUSY); 893 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 894 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 895 sc->sc_cr.xr_cs); 896 897 #if 0 898 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 899 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 900 #endif 901 902 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 903 #ifdef XHCI_QUIRK_INTEL 904 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 905 /* Intel xhci needs interrupt rate moderated. */ 906 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 907 else 908 #endif /* XHCI_QUIRK_INTEL */ 909 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 910 911 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 912 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 913 xhci_op_read_4(sc, XHCI_USBCMD)); 914 915 return USBD_NORMAL_COMPLETION; 916 } 917 918 int 919 xhci_intr(void *v) 920 { 921 struct xhci_softc * const sc = v; 922 int ret = 0; 923 924 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 925 926 if (sc == NULL) 927 return 0; 928 929 mutex_spin_enter(&sc->sc_intr_lock); 930 931 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 932 goto done; 933 934 /* If we get an interrupt while polling, then just ignore it. */ 935 if (sc->sc_bus.ub_usepolling) { 936 #ifdef DIAGNOSTIC 937 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 938 #endif 939 goto done; 940 } 941 942 ret = xhci_intr1(sc); 943 done: 944 mutex_spin_exit(&sc->sc_intr_lock); 945 return ret; 946 } 947 948 int 949 xhci_intr1(struct xhci_softc * const sc) 950 { 951 uint32_t usbsts; 952 uint32_t iman; 953 954 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 955 956 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 957 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 958 #if 0 959 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 960 return 0; 961 } 962 #endif 963 xhci_op_write_4(sc, XHCI_USBSTS, 964 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 965 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 966 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 967 968 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 969 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 970 #ifdef XHCI_QUIRK_FORCE_INTR 971 972 if (!(sc->sc_quirks & XHCI_QUIRK_FORCE_INTR)) { 973 if ((iman & XHCI_IMAN_INTR_PEND) == 0) { 974 return 0; 975 } 976 } 977 978 #else 979 if ((iman & XHCI_IMAN_INTR_PEND) == 0) { 980 return 0; 981 } 982 #endif /* XHCI_QUIRK_FORCE_INTR */ 983 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 984 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 985 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 986 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 987 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 988 989 usb_schedsoftintr(&sc->sc_bus); 990 991 return 1; 992 } 993 994 /* 995 * 3 port speed types used in USB stack 996 * 997 * usbdi speed 998 * definition: USB_SPEED_* in usb.h 999 * They are used in struct usbd_device in USB stack. 1000 * ioctl interface uses these values too. 1001 * port_status speed 1002 * definition: UPS_*_SPEED in usb.h 1003 * They are used in usb_port_status_t. 1004 * Some 3.0 values overlap with 2.0 values. 1005 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1006 * means UPS_LOW_SPEED in HS.) 1007 * port status sent from hub also uses these values. 1008 * (but I've never seen UPS_SUPER_SPEED in port_status from hub.) 1009 * xspeed: 1010 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1011 * They are used in only slot context and PORTSC reg of xhci. 1012 * The difference between usbdi speed and them are that 1013 * FS and LS values are swapped. 1014 */ 1015 1016 static int 1017 xhci_speed2xspeed(int speed) 1018 { 1019 switch (speed) { 1020 case USB_SPEED_LOW: return 2; 1021 case USB_SPEED_FULL: return 1; 1022 case USB_SPEED_HIGH: return 3; 1023 case USB_SPEED_SUPER: return 4; 1024 default: 1025 break; 1026 } 1027 return 0; 1028 } 1029 1030 /* construct slot context */ 1031 static void 1032 xhci_setup_sctx(struct usbd_device *dev, uint32_t *cp) 1033 { 1034 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 1035 int speed = dev->ud_speed; 1036 int tthubslot, ttportnum; 1037 bool ishub; 1038 bool usemtt; 1039 1040 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1041 1042 /* 6.2.2 */ 1043 /* 1044 * tthubslot: 1045 * This is the slot ID of parent HS hub 1046 * if LS/FS device is connected && connected through HS hub. 1047 * This is 0 if device is not LS/FS device || 1048 * parent hub is not HS hub || 1049 * attached to root hub. 1050 * ttportnum: 1051 * This is the downstream facing port of parent HS hub 1052 * if LS/FS device is connected. 1053 * This is 0 if device is not LS/FS device || 1054 * parent hub is not HS hub || 1055 * attached to root hub. 1056 */ 1057 if (dev->ud_myhsport != NULL && 1058 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1059 (dev->ud_myhub != NULL && 1060 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1061 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 1062 ttportnum = dev->ud_myhsport->up_portno; 1063 /* XXX addr == slot ? */ 1064 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 1065 } else { 1066 ttportnum = 0; 1067 tthubslot = 0; 1068 } 1069 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 1070 dev->ud_myhsport, ttportnum, tthubslot, 0); 1071 1072 /* ishub is valid after reading UDESC_DEVICE */ 1073 ishub = (dd->bDeviceClass == UDCLASS_HUB); 1074 1075 /* dev->ud_hub is valid after reading UDESC_HUB */ 1076 if (ishub && dev->ud_hub) { 1077 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 1078 1079 cp[1] |= htole32(XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts)); 1080 cp[2] |= htole32(XHCI_SCTX_2_TT_THINK_TIME_SET( 1081 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK))); 1082 DPRINTFN(4, "nports=%d ttt=%d", 1083 hd->bNbrPorts, XHCI_SCTX_2_TT_THINK_TIME_GET(cp[2]), 0, 0); 1084 } 1085 1086 #define IS_TTHUB(dd) \ 1087 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 1088 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 1089 1090 /* 1091 * MTT flag is set if 1092 * 1. this is HS hub && MTT is enabled 1093 * or 1094 * 2. this is not hub && this is LS or FS device && 1095 * MTT of parent HS hub (and its parent, too) is enabled 1096 */ 1097 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 1098 usemtt = true; 1099 else if (!ishub && 1100 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 1101 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1102 (dev->ud_myhub != NULL && 1103 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1104 dev->ud_myhsport != NULL && 1105 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 1106 usemtt = true; 1107 else 1108 usemtt = false; 1109 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 1110 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 1111 1112 cp[0] |= htole32( 1113 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)) | 1114 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 1115 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0) 1116 ); 1117 cp[1] |= htole32(0); 1118 cp[2] |= htole32( 1119 XHCI_SCTX_2_IRQ_TARGET_SET(0) | 1120 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 1121 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum) 1122 ); 1123 cp[3] |= htole32(0); 1124 } 1125 1126 /* 1127 * called 1128 * from xhci_open 1129 * from usbd_setup_pipe_flags 1130 * from usbd_open_pipe_ival 1131 */ 1132 static usbd_status 1133 xhci_configure_endpoint(struct usbd_pipe *pipe) 1134 { 1135 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1136 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1137 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1138 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1139 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1140 struct xhci_trb trb; 1141 usbd_status err; 1142 uint32_t *cp; 1143 uint32_t mps = UGETW(ed->wMaxPacketSize); 1144 uint32_t maxb = 0; 1145 int speed = pipe->up_dev->ud_speed; 1146 uint32_t ival = ed->bInterval; 1147 1148 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1149 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1150 xs->xs_idx, dci, ed->bEndpointAddress, ed->bmAttributes); 1151 1152 /* XXX ensure input context is available? */ 1153 1154 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1155 1156 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1157 cp[0] = htole32(0); 1158 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 1159 1160 /* set up input slot context */ 1161 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1162 xhci_setup_sctx(pipe->up_dev, cp); 1163 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1164 1165 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 1166 cp[0] = htole32( 1167 XHCI_EPCTX_0_EPSTATE_SET(0) | 1168 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 1169 XHCI_EPCTX_0_LSA_SET(0) 1170 ); 1171 cp[1] = htole32( 1172 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 1173 XHCI_EPCTX_1_MAXB_SET(0) 1174 ); 1175 if (xfertype != UE_ISOCHRONOUS) 1176 cp[1] |= htole32(XHCI_EPCTX_1_CERR_SET(3)); 1177 1178 if (speed == USB_SPEED_SUPER) { 1179 usbd_desc_iter_t iter; 1180 const usb_cdc_descriptor_t *cdcd; 1181 const usb_endpoint_ss_comp_descriptor_t * esscd = NULL; 1182 uint8_t ep; 1183 1184 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc( 1185 pipe->up_dev, UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 1186 usb_desc_iter_init(pipe->up_dev, &iter); 1187 iter.cur = (const void *)cdcd; 1188 1189 /* find endpoint_ss_comp desc for ep of this pipe */ 1190 for(ep = 0;;) { 1191 cdcd = (const usb_cdc_descriptor_t *) 1192 usb_desc_iter_next(&iter); 1193 if (cdcd == NULL) 1194 break; 1195 if (ep == 0 && 1196 cdcd->bDescriptorType == UDESC_ENDPOINT) { 1197 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 1198 bEndpointAddress; 1199 if (UE_GET_ADDR(ep) == 1200 UE_GET_ADDR(ed->bEndpointAddress)) { 1201 cdcd = (const usb_cdc_descriptor_t *) 1202 usb_desc_iter_next(&iter); 1203 break; 1204 } 1205 ep = 0; 1206 } 1207 } 1208 if (cdcd != NULL && 1209 cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 1210 esscd = (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 1211 maxb = esscd->bMaxBurst; 1212 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1213 DPRINTFN(4, "setting SS MaxBurst %u", maxb, 0, 0, 0); 1214 } 1215 } 1216 if (speed == USB_SPEED_HIGH && 1217 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 1218 maxb = UE_GET_TRANS(UGETW(ed->wMaxPacketSize)); 1219 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1220 DPRINTFN(4, "setting HS MaxBurst %u", maxb, 0, 0, 0); 1221 } 1222 1223 switch (xfertype) { 1224 case UE_INTERRUPT: 1225 /* 6.2.3.6 */ 1226 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 1227 ival = ival > 10 ? 10 : ival; 1228 ival = ival < 3 ? 3 : ival; 1229 } else { 1230 ival = ival > 15 ? 15 : ival; 1231 } 1232 if (speed == USB_SPEED_SUPER) { 1233 if (maxb > 0) 1234 mps = 1024; 1235 } else { 1236 mps = mps ? mps : 8; 1237 } 1238 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1239 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1240 cp[4] = htole32( 1241 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) /* XXX */ 1242 ); 1243 break; 1244 case UE_CONTROL: 1245 if (speed == USB_SPEED_SUPER) 1246 mps = 512; 1247 else 1248 mps = mps ? mps : 8; 1249 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1250 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(8)); /* XXX */ 1251 break; 1252 #ifdef notyet 1253 case UE_ISOCHRONOUS: 1254 if (speed == USB_SPEED_FULL) { 1255 ival = ival > 18 ? 18 : ival; 1256 ival = ival < 3 ? 3 : ival; 1257 } else { 1258 ival = ival > 15 ? 15 : ival; 1259 } 1260 if (speed == USB_SPEED_SUPER) { 1261 mps = 1024; 1262 } else { 1263 mps = mps ? mps : 1024; 1264 } 1265 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1266 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(1024)); /* XXX */ 1267 break; 1268 #endif 1269 default: 1270 if (speed == USB_SPEED_SUPER) 1271 mps = 1024; 1272 else 1273 mps = mps ? mps : 512; 1274 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1275 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(1024)); /* XXX */ 1276 break; 1277 } 1278 *(uint64_t *)(&cp[2]) = htole64( 1279 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 1280 XHCI_EPCTX_2_DCS_SET(1)); 1281 1282 /* sync input contexts before they are read from memory */ 1283 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1284 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1285 sc->sc_ctxsz * 1); 1286 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1287 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1288 1289 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1290 trb.trb_2 = 0; 1291 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1292 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1293 1294 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1295 1296 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1297 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1298 sc->sc_ctxsz * 1); 1299 1300 return err; 1301 } 1302 1303 #if 0 1304 static usbd_status 1305 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1306 { 1307 #ifdef USB_DEBUG 1308 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1309 #endif 1310 1311 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1312 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1313 1314 return USBD_NORMAL_COMPLETION; 1315 } 1316 #endif 1317 1318 /* 4.6.8, 6.4.3.7 */ 1319 static usbd_status 1320 xhci_reset_endpoint(struct usbd_pipe *pipe) 1321 { 1322 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1323 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1324 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1325 struct xhci_trb trb; 1326 usbd_status err; 1327 1328 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1329 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1330 1331 KASSERT(!mutex_owned(&sc->sc_lock)); 1332 1333 trb.trb_0 = 0; 1334 trb.trb_2 = 0; 1335 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1336 XHCI_TRB_3_EP_SET(dci) | 1337 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1338 1339 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1340 1341 return err; 1342 } 1343 1344 /* 1345 * 4.6.9, 6.4.3.8 1346 * Stop execution of TDs on xfer ring. 1347 * Should be called with sc_lock held. 1348 */ 1349 static usbd_status 1350 xhci_stop_endpoint(struct usbd_pipe *pipe) 1351 { 1352 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1353 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1354 struct xhci_trb trb; 1355 usbd_status err; 1356 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1357 1358 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1359 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1360 1361 KASSERT(mutex_owned(&sc->sc_lock)); 1362 1363 trb.trb_0 = 0; 1364 trb.trb_2 = 0; 1365 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1366 XHCI_TRB_3_EP_SET(dci) | 1367 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1368 1369 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1370 1371 return err; 1372 } 1373 1374 /* 1375 * Set TR Dequeue Pointer. 1376 * xCHI 1.1 4.6.10 6.4.3.9 1377 * Purge all of transfer requests in ring. 1378 * EPSTATE of endpoint must be ERROR or STOPPED, or CONTEXT_STATE error. 1379 */ 1380 static usbd_status 1381 xhci_set_dequeue(struct usbd_pipe *pipe) 1382 { 1383 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1384 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1385 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1386 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1387 struct xhci_trb trb; 1388 usbd_status err; 1389 1390 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1391 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1392 1393 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1394 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1395 BUS_DMASYNC_PREWRITE); 1396 1397 xr->xr_ep = 0; 1398 xr->xr_cs = 1; 1399 1400 /* set DCS */ 1401 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1402 trb.trb_2 = 0; 1403 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1404 XHCI_TRB_3_EP_SET(dci) | 1405 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1406 1407 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1408 1409 return err; 1410 } 1411 1412 /* 1413 * Open new pipe: called from usbd_setup_pipe_flags. 1414 * Fills methods of pipe. 1415 * If pipe is not for ep0, calls configure_endpoint. 1416 */ 1417 static usbd_status 1418 xhci_open(struct usbd_pipe *pipe) 1419 { 1420 struct usbd_device * const dev = pipe->up_dev; 1421 struct xhci_softc * const sc = dev->ud_bus->ub_hcpriv; 1422 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1423 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1424 1425 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1426 DPRINTFN(1, "addr %d depth %d port %d speed %d", 1427 dev->ud_addr, dev->ud_depth, dev->ud_powersrc->up_portno, 1428 dev->ud_speed); 1429 1430 if (sc->sc_dying) 1431 return USBD_IOERROR; 1432 1433 /* Root Hub */ 1434 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1435 switch (ed->bEndpointAddress) { 1436 case USB_CONTROL_ENDPOINT: 1437 pipe->up_methods = &roothub_ctrl_methods; 1438 break; 1439 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1440 pipe->up_methods = &xhci_root_intr_methods; 1441 break; 1442 default: 1443 pipe->up_methods = NULL; 1444 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1445 ed->bEndpointAddress, 0, 0, 0); 1446 return USBD_INVAL; 1447 } 1448 return USBD_NORMAL_COMPLETION; 1449 } 1450 1451 switch (xfertype) { 1452 case UE_CONTROL: 1453 pipe->up_methods = &xhci_device_ctrl_methods; 1454 break; 1455 case UE_ISOCHRONOUS: 1456 pipe->up_methods = &xhci_device_isoc_methods; 1457 return USBD_INVAL; 1458 break; 1459 case UE_BULK: 1460 pipe->up_methods = &xhci_device_bulk_methods; 1461 break; 1462 case UE_INTERRUPT: 1463 pipe->up_methods = &xhci_device_intr_methods; 1464 break; 1465 default: 1466 return USBD_IOERROR; 1467 break; 1468 } 1469 1470 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1471 return xhci_configure_endpoint(pipe); 1472 1473 return USBD_NORMAL_COMPLETION; 1474 } 1475 1476 /* 1477 * Closes pipe, called from usbd_kill_pipe via close methods. 1478 * If the endpoint to be closed is ep0, disable_slot. 1479 * Should be called with sc_lock held. 1480 */ 1481 static usbd_status 1482 xhci_close_pipe(struct usbd_pipe *pipe) 1483 { 1484 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1485 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1486 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1487 const u_int dci = xhci_ep_get_dci(ed); 1488 struct xhci_trb trb; 1489 usbd_status err; 1490 uint32_t *cp; 1491 1492 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1493 1494 if (sc->sc_dying) 1495 return USBD_IOERROR; 1496 1497 if (xs == NULL || xs->xs_idx == 0) 1498 /* xs is uninitialized before xhci_init_slot */ 1499 return USBD_IOERROR; 1500 1501 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1502 1503 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1504 KASSERT(mutex_owned(&sc->sc_lock)); 1505 1506 if (pipe->up_dev->ud_depth == 0) 1507 return USBD_NORMAL_COMPLETION; 1508 1509 if (dci == XHCI_DCI_EP_CONTROL) { 1510 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1511 return xhci_disable_slot(sc, xs->xs_idx); 1512 } 1513 1514 /* 1515 * This may fail in the case that xhci_close_pipe is called after 1516 * xhci_abort_xfer e.g. usbd_kill_pipe. 1517 */ 1518 (void)xhci_stop_endpoint(pipe); 1519 1520 /* 1521 * set appropriate bit to be dropped. 1522 * don't set DC bit to 1, otherwise all endpoints 1523 * would be deconfigured. 1524 */ 1525 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1526 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1527 cp[1] = htole32(0); 1528 1529 /* XXX should be most significant one, not dci? */ 1530 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1531 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1532 1533 /* sync input contexts before they are read from memory */ 1534 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1535 1536 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1537 trb.trb_2 = 0; 1538 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1539 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1540 1541 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1542 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1543 1544 return err; 1545 } 1546 1547 /* 1548 * Abort transfer. 1549 * Called with sc_lock held. 1550 * May be called from softintr context. 1551 */ 1552 static void 1553 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1554 { 1555 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1556 1557 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1558 DPRINTFN(4, "xfer %p pipe %p status %d", 1559 xfer, xfer->ux_pipe, status, 0); 1560 1561 KASSERT(mutex_owned(&sc->sc_lock)); 1562 1563 if (sc->sc_dying) { 1564 /* If we're dying, just do the software part. */ 1565 DPRINTFN(4, "dying", 0, 0, 0, 0); 1566 xfer->ux_status = status; /* make software ignore it */ 1567 callout_stop(&xfer->ux_callout); 1568 usb_transfer_complete(xfer); 1569 return; 1570 } 1571 1572 /* XXX need more stuff */ 1573 xfer->ux_status = status; 1574 callout_stop(&xfer->ux_callout); 1575 usb_transfer_complete(xfer); 1576 1577 KASSERT(mutex_owned(&sc->sc_lock)); 1578 } 1579 1580 #if 1 /* XXX experimental */ 1581 /* issue reset_ep and set_dequeue in thread context */ 1582 static void 1583 xhci_clear_endpoint_stall_async_task(void *cookie) 1584 { 1585 struct usbd_xfer * const xfer = cookie; 1586 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1587 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1588 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1589 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1590 1591 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1592 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1593 1594 xhci_reset_endpoint(xfer->ux_pipe); 1595 xhci_set_dequeue(xfer->ux_pipe); 1596 1597 mutex_enter(&sc->sc_lock); 1598 tr->is_halted = false; 1599 usb_transfer_complete(xfer); 1600 mutex_exit(&sc->sc_lock); 1601 DPRINTFN(4, "ends", 0, 0, 0, 0); 1602 } 1603 1604 static usbd_status 1605 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1606 { 1607 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1608 1609 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1610 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1611 1612 if (sc->sc_dying) { 1613 return USBD_IOERROR; 1614 } 1615 1616 /* XXX never use up_async_task for incompatible type of function */ 1617 usb_init_task(&xfer->ux_pipe->up_async_task, 1618 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1619 usb_add_task(xfer->ux_pipe->up_dev, &xfer->ux_pipe->up_async_task, 1620 USB_TASKQ_HC); 1621 DPRINTFN(4, "ends", 0, 0, 0, 0); 1622 1623 return USBD_NORMAL_COMPLETION; 1624 } 1625 1626 #endif /* XXX experimental */ 1627 1628 /* 1629 * Notify roothub port status/change to uhub_intr. 1630 */ 1631 static void 1632 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1633 { 1634 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1635 uint8_t *p; 1636 1637 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1638 DPRINTFN(4, "port %u status change", port, 0, 0, 0); 1639 1640 if (xfer == NULL) 1641 return; 1642 1643 p = xfer->ux_buf; 1644 memset(p, 0, xfer->ux_length); 1645 p[port/NBBY] |= 1 << (port%NBBY); 1646 xfer->ux_actlen = xfer->ux_length; 1647 xfer->ux_status = USBD_NORMAL_COMPLETION; 1648 usb_transfer_complete(xfer); 1649 } 1650 1651 /* 1652 * Process events: 1653 * + Transfer comeplete 1654 * + Command complete 1655 * + Roothub Port status/change 1656 */ 1657 static void 1658 xhci_handle_event(struct xhci_softc * const sc, 1659 const struct xhci_trb * const trb) 1660 { 1661 uint64_t trb_0; 1662 uint32_t trb_2, trb_3; 1663 uint8_t trberr; 1664 1665 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1666 1667 trb_0 = le64toh(trb->trb_0); 1668 trb_2 = le32toh(trb->trb_2); 1669 trb_3 = le32toh(trb->trb_3); 1670 trberr = XHCI_TRB_2_ERROR_GET(trb_2); 1671 1672 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1673 trb, trb_0, trb_2, trb_3); 1674 1675 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 1676 case XHCI_TRB_EVENT_TRANSFER: { 1677 u_int slot, dci; 1678 struct xhci_slot *xs; 1679 struct xhci_ring *xr; 1680 struct xhci_xfer *xx; 1681 struct usbd_xfer *xfer; 1682 usbd_status err; 1683 1684 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1685 dci = XHCI_TRB_3_EP_GET(trb_3); 1686 1687 xs = &sc->sc_slots[slot]; 1688 xr = &xs->xs_ep[dci].xe_tr; 1689 /* sanity check */ 1690 KASSERT(xs->xs_idx != 0); 1691 1692 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1693 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 1694 1695 /* trb_0 range sanity check */ 1696 if (trb_0 < trbp || 1697 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 1698 (trb_0 - trbp) / sizeof(struct xhci_trb) >= 1699 xr->xr_ntrb) { 1700 DPRINTFN(1, 1701 "invalid trb_0 0x%"PRIx64" trbp 0x%"PRIx64, 1702 trb_0, trbp, 0, 0); 1703 break; 1704 } 1705 int idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 1706 xx = xr->xr_cookies[idx]; 1707 } else { 1708 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1709 } 1710 xfer = &xx->xx_xfer; 1711 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1712 1713 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1714 DPRINTFN(14, "transfer event data: " 1715 "0x%016"PRIx64" 0x%08"PRIx32" %02x", 1716 trb_0, XHCI_TRB_2_REM_GET(trb_2), 1717 XHCI_TRB_2_ERROR_GET(trb_2), 0); 1718 if ((trb_0 & 0x3) == 0x3) { 1719 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1720 } 1721 } 1722 1723 if (trberr == XHCI_TRB_ERROR_SUCCESS || 1724 trberr == XHCI_TRB_ERROR_SHORT_PKT) { 1725 xfer->ux_actlen = 1726 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1727 err = USBD_NORMAL_COMPLETION; 1728 } else if (trberr == XHCI_TRB_ERROR_STALL || 1729 trberr == XHCI_TRB_ERROR_BABBLE) { 1730 err = USBD_STALLED; 1731 xr->is_halted = true; 1732 DPRINTFN(1, "evh: xfer done: ERR %u slot %u dci %u", 1733 trberr, slot, dci, 0); 1734 #if 1 /* XXX experimental */ 1735 /* 1736 * Stalled endpoints can be recoverd by issuing 1737 * command TRB TYPE_RESET_EP on xHCI instead of 1738 * issuing request CLEAR_PORT_FEATURE UF_ENDPOINT_HALT 1739 * on the endpoint. However, this function may be 1740 * called from softint context (e.g. from umass), 1741 * in that case driver gets KASSERT in cv_timedwait 1742 * in xhci_do_command. 1743 * To avoid this, this runs reset_endpoint and 1744 * usb_transfer_complete in usb task thread 1745 * asynchronously (and then umass issues clear 1746 * UF_ENDPOINT_HALT). 1747 */ 1748 xfer->ux_status = err; 1749 xhci_clear_endpoint_stall_async(xfer); 1750 break; 1751 #endif 1752 } else { 1753 DPRINTFN(1, "evh: xfer done: ERR %u slot %u dci %u", 1754 trberr, slot, dci, 0); 1755 err = USBD_IOERROR; 1756 } 1757 xfer->ux_status = err; 1758 1759 //mutex_enter(&sc->sc_lock); /* XXX ??? */ 1760 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1761 if ((trb_0 & 0x3) == 0x0) { 1762 usb_transfer_complete(xfer); 1763 } 1764 } else { 1765 usb_transfer_complete(xfer); 1766 } 1767 //mutex_exit(&sc->sc_lock); /* XXX ??? */ 1768 1769 } 1770 break; 1771 case XHCI_TRB_EVENT_CMD_COMPLETE: 1772 if (trb_0 == sc->sc_command_addr) { 1773 sc->sc_result_trb.trb_0 = trb_0; 1774 sc->sc_result_trb.trb_2 = trb_2; 1775 sc->sc_result_trb.trb_3 = trb_3; 1776 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1777 XHCI_TRB_ERROR_SUCCESS) { 1778 DPRINTFN(1, "command completion " 1779 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1780 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1781 } 1782 cv_signal(&sc->sc_command_cv); 1783 } else { 1784 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 1785 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1786 trb_2, trb_3); 1787 } 1788 break; 1789 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1790 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1791 break; 1792 default: 1793 break; 1794 } 1795 } 1796 1797 static void 1798 xhci_softintr(void *v) 1799 { 1800 struct usbd_bus * const bus = v; 1801 struct xhci_softc * const sc = bus->ub_hcpriv; 1802 struct xhci_ring * const er = &sc->sc_er; 1803 struct xhci_trb *trb; 1804 int i, j, k; 1805 1806 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1807 1808 i = er->xr_ep; 1809 j = er->xr_cs; 1810 1811 DPRINTFN(16, "xr_ep %d xr_cs %d", i, j, 0, 0); 1812 1813 while (1) { 1814 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 1815 BUS_DMASYNC_POSTREAD); 1816 trb = &er->xr_trb[i]; 1817 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1818 1819 if (j != k) 1820 break; 1821 1822 xhci_handle_event(sc, trb); 1823 1824 i++; 1825 if (i == XHCI_EVENT_RING_TRBS) { 1826 i = 0; 1827 j ^= 1; 1828 } 1829 } 1830 1831 er->xr_ep = i; 1832 er->xr_cs = j; 1833 1834 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 1835 XHCI_ERDP_LO_BUSY); 1836 1837 DPRINTFN(16, "ends", 0, 0, 0, 0); 1838 1839 return; 1840 } 1841 1842 static void 1843 xhci_poll(struct usbd_bus *bus) 1844 { 1845 struct xhci_softc * const sc = bus->ub_hcpriv; 1846 1847 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1848 1849 mutex_spin_enter(&sc->sc_intr_lock); 1850 xhci_intr1(sc); 1851 mutex_spin_exit(&sc->sc_intr_lock); 1852 1853 return; 1854 } 1855 1856 static struct usbd_xfer * 1857 xhci_allocx(struct usbd_bus *bus) 1858 { 1859 struct xhci_softc * const sc = bus->ub_hcpriv; 1860 struct usbd_xfer *xfer; 1861 1862 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1863 1864 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1865 if (xfer != NULL) { 1866 memset(xfer, 0, sizeof(struct xhci_xfer)); 1867 #ifdef DIAGNOSTIC 1868 xfer->ux_state = XFER_BUSY; 1869 #endif 1870 } 1871 1872 return xfer; 1873 } 1874 1875 static void 1876 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1877 { 1878 struct xhci_softc * const sc = bus->ub_hcpriv; 1879 1880 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1881 1882 #ifdef DIAGNOSTIC 1883 if (xfer->ux_state != XFER_BUSY) { 1884 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 1885 xfer, xfer->ux_state, 0, 0); 1886 } 1887 xfer->ux_state = XFER_FREE; 1888 #endif 1889 pool_cache_put(sc->sc_xferpool, xfer); 1890 } 1891 1892 static void 1893 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1894 { 1895 struct xhci_softc * const sc = bus->ub_hcpriv; 1896 1897 *lock = &sc->sc_lock; 1898 } 1899 1900 extern uint32_t usb_cookie_no; 1901 1902 /* 1903 * Called if uhub_explore find new device (via usbd_new_device). 1904 * Allocate and construct dev structure of default endpoint (ep0). 1905 * Determine initial MaxPacketSize (mps) by speed. 1906 * Determine route string and roothub port for slot of dev. 1907 * Allocate pipe of ep0. 1908 * Enable and initialize slot and Set Address. 1909 * Read device descriptor. 1910 * Register this device. 1911 */ 1912 static usbd_status 1913 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 1914 int speed, int port, struct usbd_port *up) 1915 { 1916 struct xhci_softc * const sc = bus->ub_hcpriv; 1917 struct usbd_device *dev; 1918 usbd_status err; 1919 usb_device_descriptor_t *dd; 1920 struct usbd_device *hub; 1921 struct usbd_device *adev; 1922 int rhport = 0; 1923 struct xhci_slot *xs; 1924 uint32_t *cp; 1925 uint32_t route = 0; 1926 uint8_t slot = 0; 1927 uint8_t addr; 1928 1929 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1930 DPRINTFN(4, "port=%d depth=%d speed=%d upport %d", 1931 port, depth, speed, up->up_portno); 1932 1933 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 1934 if (dev == NULL) 1935 return USBD_NOMEM; 1936 1937 dev->ud_bus = bus; 1938 1939 /* Set up default endpoint handle. */ 1940 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 1941 1942 /* Set up default endpoint descriptor. */ 1943 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 1944 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 1945 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 1946 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 1947 /* 4.3, 4.8.2.1 */ 1948 switch (speed) { 1949 case USB_SPEED_SUPER: 1950 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 1951 break; 1952 case USB_SPEED_FULL: 1953 /* XXX using 64 as initial mps of ep0 in FS */ 1954 case USB_SPEED_HIGH: 1955 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 1956 break; 1957 case USB_SPEED_LOW: 1958 default: 1959 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 1960 break; 1961 } 1962 dev->ud_ep0desc.bInterval = 0; 1963 1964 /* doesn't matter, just don't let it uninitialized */ 1965 dev->ud_ep0.ue_toggle = 0; 1966 1967 DPRINTFN(4, "up %p portno %d", up, up->up_portno, 0, 0); 1968 1969 dev->ud_quirks = &usbd_no_quirk; 1970 dev->ud_addr = 0; 1971 dev->ud_ddesc.bMaxPacketSize = 0; 1972 dev->ud_depth = depth; 1973 dev->ud_powersrc = up; 1974 dev->ud_myhub = up->up_parent; 1975 1976 up->up_dev = dev; 1977 1978 /* Locate root hub port */ 1979 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 1980 uint32_t dep; 1981 1982 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 1983 hub, hub->ud_depth, hub->ud_powersrc, 1984 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 1985 1986 if (hub->ud_powersrc == NULL) 1987 break; 1988 dep = hub->ud_depth; 1989 if (dep == 0) 1990 break; 1991 rhport = hub->ud_powersrc->up_portno; 1992 if (dep > USB_HUB_MAX_DEPTH) 1993 continue; 1994 1995 route |= 1996 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 1997 << ((dep - 1) * 4); 1998 } 1999 route = route >> 4; 2000 DPRINTFN(4, "rhport %d Route %05x hub %p", rhport, route, hub, 0); 2001 2002 /* Locate port on upstream high speed hub */ 2003 for (adev = dev, hub = up->up_parent; 2004 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2005 adev = hub, hub = hub->ud_myhub) 2006 ; 2007 if (hub) { 2008 int p; 2009 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2010 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2011 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2012 goto found; 2013 } 2014 } 2015 panic("xhci_new_device: cannot find HS port"); 2016 found: 2017 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2018 } else { 2019 dev->ud_myhsport = NULL; 2020 } 2021 2022 dev->ud_speed = speed; 2023 dev->ud_langid = USBD_NOLANG; 2024 dev->ud_cookie.cookie = ++usb_cookie_no; 2025 2026 /* Establish the default pipe. */ 2027 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2028 &dev->ud_pipe0); 2029 if (err) { 2030 goto bad; 2031 } 2032 2033 dd = &dev->ud_ddesc; 2034 2035 if ((depth == 0) && (port == 0)) { 2036 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2037 bus->ub_devices[dev->ud_addr] = dev; 2038 err = usbd_get_initial_ddesc(dev, dd); 2039 if (err) 2040 goto bad; 2041 err = usbd_reload_device_desc(dev); 2042 if (err) 2043 goto bad; 2044 } else { 2045 err = xhci_enable_slot(sc, &slot); 2046 if (err) 2047 goto bad; 2048 xs = &sc->sc_slots[slot]; 2049 dev->ud_hcpriv = xs; 2050 err = xhci_init_slot(dev, slot, route, rhport); 2051 if (err) { 2052 dev->ud_hcpriv = NULL; 2053 goto bad; 2054 } 2055 2056 /* Allow device time to set new address */ 2057 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2058 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2059 //hexdump("slot context", cp, sc->sc_ctxsz); 2060 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2061 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2062 /* XXX ensure we know when the hardware does something 2063 we can't yet cope with */ 2064 KASSERT(addr >= 1 && addr <= 127); 2065 dev->ud_addr = addr; 2066 /* XXX dev->ud_addr not necessarily unique on bus */ 2067 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2068 bus->ub_devices[dev->ud_addr] = dev; 2069 2070 err = usbd_get_initial_ddesc(dev, dd); 2071 if (err) 2072 goto bad; 2073 /* 4.8.2.1 */ 2074 if (speed == USB_SPEED_SUPER) { 2075 if (dd->bMaxPacketSize != 9) { 2076 printf("%s: invalid mps 2^%u for SS ep0," 2077 " using 512\n", 2078 device_xname(sc->sc_dev), 2079 dd->bMaxPacketSize); 2080 dd->bMaxPacketSize = 9; 2081 } 2082 USETW(dev->ud_ep0desc.wMaxPacketSize, 2083 (1 << dd->bMaxPacketSize)); 2084 } else 2085 USETW(dev->ud_ep0desc.wMaxPacketSize, 2086 dd->bMaxPacketSize); 2087 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2088 xhci_update_ep0_mps(sc, xs, 2089 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2090 err = usbd_reload_device_desc(dev); 2091 if (err) 2092 goto bad; 2093 2094 #if 0 2095 /* Re-establish the default pipe with the new MPS. */ 2096 /* In xhci this is done by xhci_update_ep0_mps. */ 2097 usbd_kill_pipe(dev->ud_pipe0); 2098 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2099 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2100 #endif 2101 } 2102 2103 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2104 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2105 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2106 dd->bDeviceClass, dd->bDeviceSubClass, 2107 dd->bDeviceProtocol, 0); 2108 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2109 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2110 dev->ud_speed); 2111 2112 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2113 2114 if ((depth == 0) && (port == 0)) { 2115 usbd_attach_roothub(parent, dev); 2116 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2117 return USBD_NORMAL_COMPLETION; 2118 } 2119 2120 2121 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2122 bad: 2123 if (err != USBD_NORMAL_COMPLETION) { 2124 usbd_remove_device(dev, up); 2125 } 2126 2127 return err; 2128 } 2129 2130 static usbd_status 2131 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2132 size_t ntrb, size_t align) 2133 { 2134 usbd_status err; 2135 size_t size = ntrb * XHCI_TRB_SIZE; 2136 2137 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2138 2139 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2140 if (err) 2141 return err; 2142 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2143 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2144 xr->xr_trb = xhci_ring_trbv(xr, 0); 2145 xr->xr_ntrb = ntrb; 2146 xr->xr_ep = 0; 2147 xr->xr_cs = 1; 2148 memset(xr->xr_trb, 0, size); 2149 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 2150 xr->is_halted = false; 2151 2152 return USBD_NORMAL_COMPLETION; 2153 } 2154 2155 static void 2156 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2157 { 2158 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2159 mutex_destroy(&xr->xr_lock); 2160 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2161 } 2162 2163 static void 2164 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2165 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2166 { 2167 size_t i; 2168 u_int ri; 2169 u_int cs; 2170 uint64_t parameter; 2171 uint32_t status; 2172 uint32_t control; 2173 2174 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2175 2176 for (i = 0; i < ntrbs; i++) { 2177 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2178 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2179 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2180 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2181 XHCI_TRB_TYPE_LINK); 2182 } 2183 2184 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2185 2186 ri = xr->xr_ep; 2187 cs = xr->xr_cs; 2188 2189 /* 2190 * Although the xhci hardware can do scatter/gather dma from 2191 * arbitrary sized buffers, there is a non-obvious restriction 2192 * that a LINK trb is only allowed at the end of a burst of 2193 * transfers - which might be 16kB. 2194 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2195 * The simple solution is not to allow a LINK trb in the middle 2196 * of anything - as here. 2197 * XXX: (dsl) There are xhci controllers out there (eg some made by 2198 * ASMedia) that seem to lock up if they process a LINK trb but 2199 * cannot process the linked-to trb yet. 2200 * The code should write the 'cycle' bit on the link trb AFTER 2201 * adding the other trb. 2202 */ 2203 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2204 parameter = xhci_ring_trbp(xr, 0); 2205 status = 0; 2206 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2207 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2208 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 2209 htole32(status), htole32(control)); 2210 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2211 BUS_DMASYNC_PREWRITE); 2212 xr->xr_cookies[ri] = NULL; 2213 xr->xr_ep = 0; 2214 xr->xr_cs ^= 1; 2215 ri = xr->xr_ep; 2216 cs = xr->xr_cs; 2217 } 2218 2219 ri++; 2220 2221 /* Write any subsequent TRB first */ 2222 for (i = 1; i < ntrbs; i++) { 2223 parameter = trbs[i].trb_0; 2224 status = trbs[i].trb_2; 2225 control = trbs[i].trb_3; 2226 2227 if (cs) { 2228 control |= XHCI_TRB_3_CYCLE_BIT; 2229 } else { 2230 control &= ~XHCI_TRB_3_CYCLE_BIT; 2231 } 2232 2233 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 2234 htole32(status), htole32(control)); 2235 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2236 BUS_DMASYNC_PREWRITE); 2237 xr->xr_cookies[ri] = cookie; 2238 ri++; 2239 } 2240 2241 /* Write the first TRB last */ 2242 i = 0; 2243 parameter = trbs[i].trb_0; 2244 status = trbs[i].trb_2; 2245 control = trbs[i].trb_3; 2246 2247 if (xr->xr_cs) { 2248 control |= XHCI_TRB_3_CYCLE_BIT; 2249 } else { 2250 control &= ~XHCI_TRB_3_CYCLE_BIT; 2251 } 2252 2253 xhci_trb_put(&xr->xr_trb[xr->xr_ep], htole64(parameter), 2254 htole32(status), htole32(control)); 2255 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2256 BUS_DMASYNC_PREWRITE); 2257 xr->xr_cookies[xr->xr_ep] = cookie; 2258 2259 xr->xr_ep = ri; 2260 xr->xr_cs = cs; 2261 2262 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2263 } 2264 2265 /* 2266 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2267 * Command completion is notified by cv_signal from xhci_handle_event 2268 * (called from interrupt from xHCI), or timed-out. 2269 * Command validation is performed in xhci_handle_event by checking if 2270 * trb_0 in CMD_COMPLETE TRB and sc->sc_command_addr are identical. 2271 */ 2272 static usbd_status 2273 xhci_do_command1(struct xhci_softc * const sc, struct xhci_trb * const trb, 2274 int timeout, int locked) 2275 { 2276 struct xhci_ring * const cr = &sc->sc_cr; 2277 usbd_status err; 2278 2279 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2280 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2281 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2282 2283 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2284 2285 if (!locked) 2286 mutex_enter(&sc->sc_lock); 2287 2288 /* XXX KASSERT may fire when cv_timedwait unlocks sc_lock */ 2289 KASSERT(sc->sc_command_addr == 0); 2290 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2291 2292 mutex_enter(&cr->xr_lock); 2293 xhci_ring_put(sc, cr, NULL, trb, 1); 2294 mutex_exit(&cr->xr_lock); 2295 2296 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2297 2298 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2299 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2300 err = USBD_TIMEOUT; 2301 goto timedout; 2302 } 2303 2304 trb->trb_0 = sc->sc_result_trb.trb_0; 2305 trb->trb_2 = sc->sc_result_trb.trb_2; 2306 trb->trb_3 = sc->sc_result_trb.trb_3; 2307 2308 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2309 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2310 2311 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2312 case XHCI_TRB_ERROR_SUCCESS: 2313 err = USBD_NORMAL_COMPLETION; 2314 break; 2315 default: 2316 case 192 ... 223: 2317 err = USBD_IOERROR; 2318 break; 2319 case 224 ... 255: 2320 err = USBD_NORMAL_COMPLETION; 2321 break; 2322 } 2323 2324 timedout: 2325 sc->sc_command_addr = 0; 2326 if (!locked) 2327 mutex_exit(&sc->sc_lock); 2328 return err; 2329 } 2330 2331 static usbd_status 2332 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2333 int timeout) 2334 { 2335 return xhci_do_command1(sc, trb, timeout, 0); 2336 } 2337 2338 /* 2339 * This allows xhci_do_command with already sc_lock held. 2340 * This is needed as USB stack calls close methods with sc_lock_held. 2341 * (see usbdivar.h) 2342 */ 2343 static usbd_status 2344 xhci_do_command_locked(struct xhci_softc * const sc, 2345 struct xhci_trb * const trb, int timeout) 2346 { 2347 return xhci_do_command1(sc, trb, timeout, 1); 2348 } 2349 2350 static usbd_status 2351 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2352 { 2353 struct xhci_trb trb; 2354 usbd_status err; 2355 2356 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2357 2358 trb.trb_0 = 0; 2359 trb.trb_2 = 0; 2360 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2361 2362 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2363 if (err != USBD_NORMAL_COMPLETION) { 2364 return err; 2365 } 2366 2367 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2368 2369 return err; 2370 } 2371 2372 /* 2373 * Deallocate DMA buffer and ring buffer, and disable_slot. 2374 * Should be called with sc_lock held. 2375 */ 2376 static usbd_status 2377 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2378 { 2379 struct xhci_trb trb; 2380 struct xhci_slot *xs; 2381 2382 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2383 2384 if (sc->sc_dying) 2385 return USBD_IOERROR; 2386 2387 xs = &sc->sc_slots[slot]; 2388 if (xs->xs_idx != 0) { 2389 for (int i = XHCI_DCI_SLOT + 1; i < 32; i++) { 2390 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2391 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2392 } 2393 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2394 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2395 } 2396 2397 trb.trb_0 = 0; 2398 trb.trb_2 = 0; 2399 trb.trb_3 = htole32( 2400 XHCI_TRB_3_SLOT_SET(slot) | 2401 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2402 2403 return xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2404 } 2405 2406 /* 2407 * Change slot state. 2408 * bsr=0: ENABLED -> ADDRESSED 2409 * bsr=1: ENABLED -> DEFAULT 2410 * see xHCI 1.1 4.5.3, 3.3.4 2411 */ 2412 static usbd_status 2413 xhci_address_device(struct xhci_softc * const sc, 2414 uint64_t icp, uint8_t slot_id, bool bsr) 2415 { 2416 struct xhci_trb trb; 2417 usbd_status err; 2418 2419 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2420 2421 trb.trb_0 = icp; 2422 trb.trb_2 = 0; 2423 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2424 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2425 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2426 2427 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2428 return err; 2429 } 2430 2431 static usbd_status 2432 xhci_update_ep0_mps(struct xhci_softc * const sc, 2433 struct xhci_slot * const xs, u_int mps) 2434 { 2435 struct xhci_trb trb; 2436 usbd_status err; 2437 uint32_t * cp; 2438 2439 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2440 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2441 2442 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2443 cp[0] = htole32(0); 2444 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2445 2446 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2447 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2448 2449 /* sync input contexts before they are read from memory */ 2450 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2451 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2452 sc->sc_ctxsz * 4); 2453 2454 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2455 trb.trb_2 = 0; 2456 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2457 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2458 2459 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2460 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2461 return err; 2462 } 2463 2464 static void 2465 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2466 { 2467 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2468 2469 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2470 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2471 &dcbaa[si], dcba, si, 0); 2472 2473 dcbaa[si] = htole64(dcba); 2474 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2475 BUS_DMASYNC_PREWRITE); 2476 } 2477 2478 /* 2479 * Allocate DMA buffer and ring buffer for specified slot 2480 * and set Device Context Base Address 2481 * and issue Set Address device command. 2482 */ 2483 static usbd_status 2484 xhci_init_slot(struct usbd_device *dev, uint32_t slot, int route, int rhport) 2485 { 2486 struct xhci_softc * const sc = dev->ud_bus->ub_hcpriv; 2487 struct xhci_slot *xs; 2488 usbd_status err; 2489 u_int dci; 2490 uint32_t *cp; 2491 uint32_t mps = UGETW(dev->ud_ep0desc.wMaxPacketSize); 2492 2493 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2494 DPRINTFN(4, "slot %u speed %d rhport %d route %05x", 2495 slot, dev->ud_speed, route, rhport); 2496 2497 xs = &sc->sc_slots[slot]; 2498 2499 /* allocate contexts */ 2500 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2501 &xs->xs_dc_dma); 2502 if (err) 2503 return err; 2504 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2505 2506 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2507 &xs->xs_ic_dma); 2508 if (err) 2509 goto bad1; 2510 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2511 2512 for (dci = 0; dci < 32; dci++) { 2513 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2514 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2515 if (dci == XHCI_DCI_SLOT) 2516 continue; 2517 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2518 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2519 if (err) { 2520 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2521 goto bad2; 2522 } 2523 } 2524 2525 /* set up initial input control context */ 2526 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2527 cp[0] = htole32(0); 2528 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 2529 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2530 2531 /* set up input slot context */ 2532 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2533 xhci_setup_sctx(dev, cp); 2534 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(1)); 2535 cp[0] |= htole32(XHCI_SCTX_0_ROUTE_SET(route)); 2536 cp[1] |= htole32(XHCI_SCTX_1_RH_PORT_SET(rhport)); 2537 2538 /* set up input EP0 context */ 2539 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2540 cp[0] = htole32(0); 2541 cp[1] = htole32( 2542 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 2543 XHCI_EPCTX_1_EPTYPE_SET(4) | 2544 XHCI_EPCTX_1_CERR_SET(3) 2545 ); 2546 /* can't use xhci_ep_get_dci() yet? */ 2547 *(uint64_t *)(&cp[2]) = htole64( 2548 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 2549 XHCI_EPCTX_2_DCS_SET(1)); 2550 cp[4] = htole32( 2551 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 2552 ); 2553 2554 /* sync input contexts before they are read from memory */ 2555 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2556 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2557 sc->sc_ctxsz * 3); 2558 2559 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2560 2561 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 2562 false); 2563 2564 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2565 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2566 sc->sc_ctxsz * 2); 2567 2568 bad2: 2569 if (err == USBD_NORMAL_COMPLETION) { 2570 xs->xs_idx = slot; 2571 } else { 2572 for (int i = 1; i < dci; i++) { 2573 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2574 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2575 } 2576 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2577 bad1: 2578 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2579 xs->xs_idx = 0; 2580 } 2581 2582 return err; 2583 } 2584 2585 /* ----- */ 2586 2587 static void 2588 xhci_noop(struct usbd_pipe *pipe) 2589 { 2590 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2591 } 2592 2593 /* 2594 * Process root hub request. 2595 */ 2596 static int 2597 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2598 void *buf, int buflen) 2599 { 2600 struct xhci_softc * const sc = bus->ub_hcpriv; 2601 usb_port_status_t ps; 2602 int l, totlen = 0; 2603 uint16_t len, value, index; 2604 int port, i; 2605 uint32_t v; 2606 2607 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2608 2609 if (sc->sc_dying) 2610 return -1; 2611 2612 len = UGETW(req->wLength); 2613 value = UGETW(req->wValue); 2614 index = UGETW(req->wIndex); 2615 2616 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 2617 req->bmRequestType | (req->bRequest << 8), value, index, len); 2618 2619 #define C(x,y) ((x) | ((y) << 8)) 2620 switch (C(req->bRequest, req->bmRequestType)) { 2621 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2622 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 2623 if (len == 0) 2624 break; 2625 switch (value) { 2626 #define sd ((usb_string_descriptor_t *)buf) 2627 case C(2, UDESC_STRING): 2628 /* Product */ 2629 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 2630 break; 2631 #undef sd 2632 default: 2633 /* default from usbroothub */ 2634 return buflen; 2635 } 2636 break; 2637 2638 /* Hub requests */ 2639 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2640 break; 2641 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2642 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2643 index, value, 0, 0); 2644 if (index < 1 || index > sc->sc_maxports) { 2645 return -1; 2646 } 2647 port = XHCI_PORTSC(index); 2648 v = xhci_op_read_4(sc, port); 2649 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2650 v &= ~XHCI_PS_CLEAR; 2651 switch (value) { 2652 case UHF_PORT_ENABLE: 2653 xhci_op_write_4(sc, port, v &~ XHCI_PS_PED); 2654 break; 2655 case UHF_PORT_SUSPEND: 2656 return -1; 2657 case UHF_PORT_POWER: 2658 break; 2659 case UHF_PORT_TEST: 2660 case UHF_PORT_INDICATOR: 2661 return -1; 2662 case UHF_C_PORT_CONNECTION: 2663 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2664 break; 2665 case UHF_C_PORT_ENABLE: 2666 case UHF_C_PORT_SUSPEND: 2667 case UHF_C_PORT_OVER_CURRENT: 2668 return -1; 2669 case UHF_C_BH_PORT_RESET: 2670 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 2671 break; 2672 case UHF_C_PORT_RESET: 2673 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2674 break; 2675 case UHF_C_PORT_LINK_STATE: 2676 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 2677 break; 2678 case UHF_C_PORT_CONFIG_ERROR: 2679 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 2680 break; 2681 default: 2682 return -1; 2683 } 2684 break; 2685 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2686 if (len == 0) 2687 break; 2688 if ((value & 0xff) != 0) { 2689 return -1; 2690 } 2691 usb_hub_descriptor_t hubd; 2692 2693 totlen = min(buflen, sizeof(hubd)); 2694 memcpy(&hubd, buf, totlen); 2695 hubd.bNbrPorts = sc->sc_maxports; 2696 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2697 hubd.bPwrOn2PwrGood = 200; 2698 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 2699 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2700 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2701 totlen = min(totlen, hubd.bDescLength); 2702 memcpy(buf, &hubd, totlen); 2703 break; 2704 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2705 if (len != 4) { 2706 return -1; 2707 } 2708 memset(buf, 0, len); /* ? XXX */ 2709 totlen = len; 2710 break; 2711 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2712 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2713 if (index < 1 || index > sc->sc_maxports) { 2714 return -1; 2715 } 2716 if (len != 4) { 2717 return -1; 2718 } 2719 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 2720 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 2721 switch (XHCI_PS_SPEED_GET(v)) { 2722 case 1: 2723 i = UPS_FULL_SPEED; 2724 break; 2725 case 2: 2726 i = UPS_LOW_SPEED; 2727 break; 2728 case 3: 2729 i = UPS_HIGH_SPEED; 2730 break; 2731 case 4: 2732 i = UPS_SUPER_SPEED; 2733 break; 2734 default: 2735 i = 0; 2736 break; 2737 } 2738 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2739 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2740 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2741 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 2742 if (v & XHCI_PS_PR) i |= UPS_RESET; 2743 if (v & XHCI_PS_PP) { 2744 if (i & UPS_SUPER_SPEED) 2745 i |= UPS_PORT_POWER_SS; 2746 else 2747 i |= UPS_PORT_POWER; 2748 } 2749 USETW(ps.wPortStatus, i); 2750 i = 0; 2751 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2752 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2753 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2754 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2755 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 2756 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 2757 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 2758 USETW(ps.wPortChange, i); 2759 totlen = min(len, sizeof(ps)); 2760 memcpy(buf, &ps, totlen); 2761 break; 2762 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2763 return -1; 2764 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 2765 break; 2766 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2767 break; 2768 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2769 { 2770 int optval = (index >> 8) & 0xff; 2771 index &= 0xff; 2772 if (index < 1 || index > sc->sc_maxports) { 2773 return -1; 2774 } 2775 port = XHCI_PORTSC(index); 2776 v = xhci_op_read_4(sc, port); 2777 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2778 v &= ~XHCI_PS_CLEAR; 2779 switch (value) { 2780 case UHF_PORT_ENABLE: 2781 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 2782 break; 2783 case UHF_PORT_SUSPEND: 2784 /* XXX suspend */ 2785 break; 2786 case UHF_PORT_RESET: 2787 v &= ~ (XHCI_PS_PED | XHCI_PS_PR); 2788 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 2789 /* Wait for reset to complete. */ 2790 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2791 if (sc->sc_dying) { 2792 return -1; 2793 } 2794 v = xhci_op_read_4(sc, port); 2795 if (v & XHCI_PS_PR) { 2796 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 2797 usb_delay_ms(&sc->sc_bus, 10); 2798 /* XXX */ 2799 } 2800 break; 2801 case UHF_PORT_POWER: 2802 /* XXX power control */ 2803 break; 2804 /* XXX more */ 2805 case UHF_C_PORT_RESET: 2806 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2807 break; 2808 case UHF_PORT_U1_TIMEOUT: 2809 if (XHCI_PS_SPEED_GET(v) != 4) { 2810 return -1; 2811 } 2812 port = XHCI_PORTPMSC(index); 2813 v = xhci_op_read_4(sc, port); 2814 v &= ~XHCI_PM3_U1TO_SET(0xff); 2815 v |= XHCI_PM3_U1TO_SET(optval); 2816 xhci_op_write_4(sc, port, v); 2817 break; 2818 case UHF_PORT_U2_TIMEOUT: 2819 if (XHCI_PS_SPEED_GET(v) != 4) { 2820 return -1; 2821 } 2822 port = XHCI_PORTPMSC(index); 2823 v = xhci_op_read_4(sc, port); 2824 v &= ~XHCI_PM3_U2TO_SET(0xff); 2825 v |= XHCI_PM3_U2TO_SET(optval); 2826 xhci_op_write_4(sc, port, v); 2827 break; 2828 default: 2829 return -1; 2830 } 2831 } 2832 break; 2833 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2834 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2835 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2836 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2837 break; 2838 default: 2839 /* default from usbroothub */ 2840 return buflen; 2841 } 2842 2843 return totlen; 2844 } 2845 2846 /* root hub interrupt */ 2847 2848 static usbd_status 2849 xhci_root_intr_transfer(struct usbd_xfer *xfer) 2850 { 2851 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2852 usbd_status err; 2853 2854 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2855 2856 /* Insert last in queue. */ 2857 mutex_enter(&sc->sc_lock); 2858 err = usb_insert_transfer(xfer); 2859 mutex_exit(&sc->sc_lock); 2860 if (err) 2861 return err; 2862 2863 /* Pipe isn't running, start first */ 2864 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2865 } 2866 2867 /* Wait for roothub port status/change */ 2868 static usbd_status 2869 xhci_root_intr_start(struct usbd_xfer *xfer) 2870 { 2871 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2872 2873 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2874 2875 if (sc->sc_dying) 2876 return USBD_IOERROR; 2877 2878 mutex_enter(&sc->sc_lock); 2879 sc->sc_intrxfer = xfer; 2880 mutex_exit(&sc->sc_lock); 2881 2882 return USBD_IN_PROGRESS; 2883 } 2884 2885 static void 2886 xhci_root_intr_abort(struct usbd_xfer *xfer) 2887 { 2888 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2889 2890 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2891 2892 KASSERT(mutex_owned(&sc->sc_lock)); 2893 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2894 2895 sc->sc_intrxfer = NULL; 2896 2897 xfer->ux_status = USBD_CANCELLED; 2898 usb_transfer_complete(xfer); 2899 } 2900 2901 static void 2902 xhci_root_intr_close(struct usbd_pipe *pipe) 2903 { 2904 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 2905 2906 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2907 2908 KASSERT(mutex_owned(&sc->sc_lock)); 2909 2910 sc->sc_intrxfer = NULL; 2911 } 2912 2913 static void 2914 xhci_root_intr_done(struct usbd_xfer *xfer) 2915 { 2916 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2917 2918 xfer->ux_hcpriv = NULL; 2919 } 2920 2921 /* -------------- */ 2922 /* device control */ 2923 2924 static usbd_status 2925 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2926 { 2927 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2928 usbd_status err; 2929 2930 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2931 2932 /* Insert last in queue. */ 2933 mutex_enter(&sc->sc_lock); 2934 err = usb_insert_transfer(xfer); 2935 mutex_exit(&sc->sc_lock); 2936 if (err) 2937 return err; 2938 2939 /* Pipe isn't running, start first */ 2940 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2941 } 2942 2943 static usbd_status 2944 xhci_device_ctrl_start(struct usbd_xfer *xfer) 2945 { 2946 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2947 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 2948 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 2949 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2950 struct xhci_xfer * const xx = (void *)xfer; 2951 usb_device_request_t * const req = &xfer->ux_request; 2952 const bool isread = UT_GET_DIR(req->bmRequestType) == UT_READ; 2953 const uint32_t len = UGETW(req->wLength); 2954 usb_dma_t * const dma = &xfer->ux_dmabuf; 2955 uint64_t parameter; 2956 uint32_t status; 2957 uint32_t control; 2958 u_int i; 2959 2960 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2961 DPRINTFN(12, "req: %04x %04x %04x %04x", 2962 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 2963 UGETW(req->wIndex), UGETW(req->wLength)); 2964 2965 /* XXX */ 2966 if (tr->is_halted) { 2967 DPRINTFN(1, "ctrl xfer %p halted: slot %u dci %u", 2968 xfer, xs->xs_idx, dci, 0); 2969 xhci_reset_endpoint(xfer->ux_pipe); 2970 tr->is_halted = false; 2971 xhci_set_dequeue(xfer->ux_pipe); 2972 } 2973 2974 /* we rely on the bottom bits for extra info */ 2975 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 2976 2977 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 2978 2979 i = 0; 2980 2981 /* setup phase */ 2982 memcpy(¶meter, req, sizeof(*req)); 2983 parameter = le64toh(parameter); 2984 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 2985 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 2986 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 2987 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 2988 XHCI_TRB_3_IDT_BIT; 2989 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2990 2991 if (len == 0) 2992 goto no_data; 2993 2994 /* data phase */ 2995 parameter = DMAADDR(dma, 0); 2996 KASSERT(len <= 0x10000); 2997 status = XHCI_TRB_2_IRQ_SET(0) | 2998 XHCI_TRB_2_TDSZ_SET(1) | 2999 XHCI_TRB_2_BYTES_SET(len); 3000 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3001 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3002 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3003 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3004 3005 parameter = (uintptr_t)xfer | 0x3; 3006 status = XHCI_TRB_2_IRQ_SET(0); 3007 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3008 XHCI_TRB_3_IOC_BIT; 3009 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3010 3011 no_data: 3012 parameter = 0; 3013 status = XHCI_TRB_2_IRQ_SET(0); 3014 /* the status stage has inverted direction */ 3015 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3016 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3017 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3018 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3019 3020 parameter = (uintptr_t)xfer | 0x0; 3021 status = XHCI_TRB_2_IRQ_SET(0); 3022 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3023 XHCI_TRB_3_IOC_BIT; 3024 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3025 3026 mutex_enter(&tr->xr_lock); 3027 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3028 mutex_exit(&tr->xr_lock); 3029 3030 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3031 3032 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3033 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3034 xhci_timeout, xfer); 3035 } 3036 3037 if (sc->sc_bus.ub_usepolling) { 3038 DPRINTFN(1, "polling", 0, 0, 0, 0); 3039 //xhci_waitintr(sc, xfer); 3040 } 3041 3042 return USBD_IN_PROGRESS; 3043 } 3044 3045 static void 3046 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3047 { 3048 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3049 3050 callout_stop(&xfer->ux_callout); /* XXX wrong place */ 3051 3052 } 3053 3054 static void 3055 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3056 { 3057 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3058 3059 xhci_abort_xfer(xfer, USBD_CANCELLED); 3060 } 3061 3062 static void 3063 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3064 { 3065 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3066 3067 (void)xhci_close_pipe(pipe); 3068 } 3069 3070 /* ------------------ */ 3071 /* device isochronous */ 3072 3073 /* ----------- */ 3074 /* device bulk */ 3075 3076 static usbd_status 3077 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3078 { 3079 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3080 usbd_status err; 3081 3082 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3083 3084 /* Insert last in queue. */ 3085 mutex_enter(&sc->sc_lock); 3086 err = usb_insert_transfer(xfer); 3087 mutex_exit(&sc->sc_lock); 3088 if (err) 3089 return err; 3090 3091 /* 3092 * Pipe isn't running (otherwise err would be USBD_INPROG), 3093 * so start it first. 3094 */ 3095 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3096 } 3097 3098 static usbd_status 3099 xhci_device_bulk_start(struct usbd_xfer *xfer) 3100 { 3101 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3102 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3103 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3104 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3105 struct xhci_xfer * const xx = (void *)xfer; 3106 const uint32_t len = xfer->ux_length; 3107 usb_dma_t * const dma = &xfer->ux_dmabuf; 3108 uint64_t parameter; 3109 uint32_t status; 3110 uint32_t control; 3111 u_int i = 0; 3112 3113 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3114 3115 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3116 3117 if (sc->sc_dying) 3118 return USBD_IOERROR; 3119 3120 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3121 3122 parameter = DMAADDR(dma, 0); 3123 /* 3124 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3125 * If the user supplied buffer crosses such a boundary then 2 3126 * (or more) TRB should be used. 3127 * If multiple TRB are used the td_size field must be set correctly. 3128 * For v1.0 devices (like ivy bridge) this is the number of usb data 3129 * blocks needed to complete the transfer. 3130 * Setting it to 1 in the last TRB causes an extra zero-length 3131 * data block be sent. 3132 * The earlier documentation differs, I don't know how it behaves. 3133 */ 3134 KASSERT(len <= 0x10000); 3135 status = XHCI_TRB_2_IRQ_SET(0) | 3136 XHCI_TRB_2_TDSZ_SET(1) | 3137 XHCI_TRB_2_BYTES_SET(len); 3138 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3139 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3140 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3141 3142 mutex_enter(&tr->xr_lock); 3143 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3144 mutex_exit(&tr->xr_lock); 3145 3146 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3147 3148 if (sc->sc_bus.ub_usepolling) { 3149 DPRINTFN(1, "polling", 0, 0, 0, 0); 3150 //xhci_waitintr(sc, xfer); 3151 } 3152 3153 return USBD_IN_PROGRESS; 3154 } 3155 3156 static void 3157 xhci_device_bulk_done(struct usbd_xfer *xfer) 3158 { 3159 #ifdef USB_DEBUG 3160 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3161 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3162 #endif 3163 const u_int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3164 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3165 3166 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3167 3168 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3169 3170 callout_stop(&xfer->ux_callout); /* XXX wrong place */ 3171 3172 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3173 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3174 } 3175 3176 static void 3177 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3178 { 3179 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3180 3181 xhci_abort_xfer(xfer, USBD_CANCELLED); 3182 } 3183 3184 static void 3185 xhci_device_bulk_close(struct usbd_pipe *pipe) 3186 { 3187 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3188 3189 (void)xhci_close_pipe(pipe); 3190 } 3191 3192 /* ---------------- */ 3193 /* device interrupt */ 3194 3195 static usbd_status 3196 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3197 { 3198 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3199 usbd_status err; 3200 3201 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3202 3203 /* Insert last in queue. */ 3204 mutex_enter(&sc->sc_lock); 3205 err = usb_insert_transfer(xfer); 3206 mutex_exit(&sc->sc_lock); 3207 if (err) 3208 return err; 3209 3210 /* 3211 * Pipe isn't running (otherwise err would be USBD_INPROG), 3212 * so start it first. 3213 */ 3214 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3215 } 3216 3217 static usbd_status 3218 xhci_device_intr_start(struct usbd_xfer *xfer) 3219 { 3220 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3221 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3222 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3223 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3224 struct xhci_xfer * const xx = (void *)xfer; 3225 const uint32_t len = xfer->ux_length; 3226 usb_dma_t * const dma = &xfer->ux_dmabuf; 3227 uint64_t parameter; 3228 uint32_t status; 3229 uint32_t control; 3230 u_int i = 0; 3231 3232 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3233 3234 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3235 3236 if (sc->sc_dying) 3237 return USBD_IOERROR; 3238 3239 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3240 3241 parameter = DMAADDR(dma, 0); 3242 KASSERT(len <= 0x10000); 3243 status = XHCI_TRB_2_IRQ_SET(0) | 3244 XHCI_TRB_2_TDSZ_SET(1) | 3245 XHCI_TRB_2_BYTES_SET(len); 3246 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3247 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3248 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3249 3250 mutex_enter(&tr->xr_lock); 3251 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3252 mutex_exit(&tr->xr_lock); 3253 3254 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3255 3256 if (sc->sc_bus.ub_usepolling) { 3257 DPRINTFN(1, "polling", 0, 0, 0, 0); 3258 //xhci_waitintr(sc, xfer); 3259 } 3260 3261 return USBD_IN_PROGRESS; 3262 } 3263 3264 static void 3265 xhci_device_intr_done(struct usbd_xfer *xfer) 3266 { 3267 struct xhci_softc * const sc __diagused = 3268 xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3269 #ifdef USB_DEBUG 3270 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3271 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3272 #endif 3273 const u_int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3274 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3275 3276 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3277 3278 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3279 3280 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3281 3282 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3283 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3284 3285 #if 0 3286 device_printf(sc->sc_dev, ""); 3287 for (size_t i = 0; i < xfer->ux_length; i++) { 3288 printf(" %02x", ((uint8_t const *)xfer->ux_buffer)[i]); 3289 } 3290 printf("\n"); 3291 #endif 3292 3293 if (xfer->ux_pipe->up_repeat) { 3294 xfer->ux_status = xhci_device_intr_start(xfer); 3295 } else { 3296 callout_stop(&xfer->ux_callout); /* XXX */ 3297 } 3298 3299 } 3300 3301 static void 3302 xhci_device_intr_abort(struct usbd_xfer *xfer) 3303 { 3304 struct xhci_softc * const sc __diagused = 3305 xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3306 3307 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3308 3309 KASSERT(mutex_owned(&sc->sc_lock)); 3310 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3311 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3312 xhci_abort_xfer(xfer, USBD_CANCELLED); 3313 } 3314 3315 static void 3316 xhci_device_intr_close(struct usbd_pipe *pipe) 3317 { 3318 //struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 3319 3320 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3321 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3322 3323 (void)xhci_close_pipe(pipe); 3324 } 3325 3326 /* ------------ */ 3327 3328 static void 3329 xhci_timeout(void *addr) 3330 { 3331 struct xhci_xfer * const xx = addr; 3332 struct usbd_xfer * const xfer = &xx->xx_xfer; 3333 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3334 3335 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3336 3337 if (sc->sc_dying) { 3338 return; 3339 } 3340 3341 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 3342 USB_TASKQ_MPSAFE); 3343 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 3344 USB_TASKQ_HC); 3345 } 3346 3347 static void 3348 xhci_timeout_task(void *addr) 3349 { 3350 struct usbd_xfer * const xfer = addr; 3351 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3352 3353 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3354 3355 mutex_enter(&sc->sc_lock); 3356 #if 0 3357 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3358 #else 3359 xfer->ux_status = USBD_TIMEOUT; 3360 usb_transfer_complete(xfer); 3361 #endif 3362 mutex_exit(&sc->sc_lock); 3363 } 3364
Indexes created Wed Oct 01 18:09:54 GMT 2025