xhci.c revision 1.28.2.21
1 /* $NetBSD: xhci.c,v 1.28.2.21 2015/05/27 06:54:18 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 3.1 specification 31 * http://www.usb.org/developers/docs/usb_31_040315.zip 32 * USB rev 2.0 specification 33 * http://www.usb.org/developers/docs/usb20_docs/usb_20_031815.zip 34 * xHCI rev 1.1 specification 35 * http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.28.2.21 2015/05/27 06:54:18 skrll Exp $"); 40 41 #include "opt_usb.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 }; 120 121 #define XHCI_COMMAND_RING_TRBS 256 122 #define XHCI_EVENT_RING_TRBS 256 123 #define XHCI_EVENT_RING_SEGMENTS 1 124 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 125 126 static usbd_status xhci_open(struct usbd_pipe *); 127 static int xhci_intr1(struct xhci_softc * const); 128 static void xhci_softintr(void *); 129 static void xhci_poll(struct usbd_bus *); 130 static struct usbd_xfer *xhci_allocx(struct usbd_bus *); 131 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 132 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 133 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 134 struct usbd_port *); 135 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 136 void *, int); 137 138 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 139 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 140 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 141 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 142 143 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 144 145 static usbd_status xhci_do_command(struct xhci_softc * const, 146 struct xhci_trb * const, int); 147 static usbd_status xhci_do_command1(struct xhci_softc * const, 148 struct xhci_trb * const, int, int); 149 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 150 struct xhci_trb * const, int); 151 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t, int, int); 152 static usbd_status xhci_enable_slot(struct xhci_softc * const, 153 uint8_t * const); 154 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 155 static usbd_status xhci_address_device(struct xhci_softc * const, 156 uint64_t, uint8_t, bool); 157 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 158 struct xhci_slot * const, u_int); 159 static usbd_status xhci_ring_init(struct xhci_softc * const, 160 struct xhci_ring * const, size_t, size_t); 161 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 162 163 static void xhci_noop(struct usbd_pipe *); 164 165 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 166 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 167 static void xhci_root_intr_abort(struct usbd_xfer *); 168 static void xhci_root_intr_close(struct usbd_pipe *); 169 static void xhci_root_intr_done(struct usbd_xfer *); 170 171 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 172 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 173 static void xhci_device_ctrl_abort(struct usbd_xfer *); 174 static void xhci_device_ctrl_close(struct usbd_pipe *); 175 static void xhci_device_ctrl_done(struct usbd_xfer *); 176 177 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 178 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 179 static void xhci_device_intr_abort(struct usbd_xfer *); 180 static void xhci_device_intr_close(struct usbd_pipe *); 181 static void xhci_device_intr_done(struct usbd_xfer *); 182 183 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 184 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 185 static void xhci_device_bulk_abort(struct usbd_xfer *); 186 static void xhci_device_bulk_close(struct usbd_pipe *); 187 static void xhci_device_bulk_done(struct usbd_xfer *); 188 189 static void xhci_timeout(void *); 190 static void xhci_timeout_task(void *); 191 192 static const struct usbd_bus_methods xhci_bus_methods = { 193 .ubm_open = xhci_open, 194 .ubm_softint = xhci_softintr, 195 .ubm_dopoll = xhci_poll, 196 .ubm_allocx = xhci_allocx, 197 .ubm_freex = xhci_freex, 198 .ubm_getlock = xhci_get_lock, 199 .ubm_newdev = xhci_new_device, 200 .ubm_rhctrl = xhci_roothub_ctrl, 201 }; 202 203 static const struct usbd_pipe_methods xhci_root_intr_methods = { 204 .upm_transfer = xhci_root_intr_transfer, 205 .upm_start = xhci_root_intr_start, 206 .upm_abort = xhci_root_intr_abort, 207 .upm_close = xhci_root_intr_close, 208 .upm_cleartoggle = xhci_noop, 209 .upm_done = xhci_root_intr_done, 210 }; 211 212 213 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 214 .upm_transfer = xhci_device_ctrl_transfer, 215 .upm_start = xhci_device_ctrl_start, 216 .upm_abort = xhci_device_ctrl_abort, 217 .upm_close = xhci_device_ctrl_close, 218 .upm_cleartoggle = xhci_noop, 219 .upm_done = xhci_device_ctrl_done, 220 }; 221 222 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 223 .upm_cleartoggle = xhci_noop, 224 }; 225 226 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 227 .upm_transfer = xhci_device_bulk_transfer, 228 .upm_start = xhci_device_bulk_start, 229 .upm_abort = xhci_device_bulk_abort, 230 .upm_close = xhci_device_bulk_close, 231 .upm_cleartoggle = xhci_noop, 232 .upm_done = xhci_device_bulk_done, 233 }; 234 235 static const struct usbd_pipe_methods xhci_device_intr_methods = { 236 .upm_transfer = xhci_device_intr_transfer, 237 .upm_start = xhci_device_intr_start, 238 .upm_abort = xhci_device_intr_abort, 239 .upm_close = xhci_device_intr_close, 240 .upm_cleartoggle = xhci_noop, 241 .upm_done = xhci_device_intr_done, 242 }; 243 244 static inline uint32_t 245 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 246 { 247 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 248 } 249 250 static inline uint32_t 251 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 252 { 253 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 254 } 255 256 static inline void 257 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 258 uint32_t value) 259 { 260 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 261 } 262 263 #if 0 /* unused */ 264 static inline void 265 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 266 uint32_t value) 267 { 268 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 269 } 270 #endif /* unused */ 271 272 static inline uint32_t 273 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 274 { 275 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 276 } 277 278 static inline uint32_t 279 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 280 { 281 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 282 } 283 284 static inline void 285 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 286 uint32_t value) 287 { 288 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 289 } 290 291 #if 0 /* unused */ 292 static inline uint64_t 293 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 294 { 295 uint64_t value; 296 297 if (sc->sc_ac64) { 298 #ifdef XHCI_USE_BUS_SPACE_8 299 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 300 #else 301 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 302 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 303 offset + 4) << 32; 304 #endif 305 } else { 306 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 307 } 308 309 return value; 310 } 311 #endif /* unused */ 312 313 static inline void 314 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 315 uint64_t value) 316 { 317 if (sc->sc_ac64) { 318 #ifdef XHCI_USE_BUS_SPACE_8 319 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 320 #else 321 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 322 (value >> 0) & 0xffffffff); 323 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 324 (value >> 32) & 0xffffffff); 325 #endif 326 } else { 327 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 328 } 329 } 330 331 static inline uint32_t 332 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 333 { 334 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 335 } 336 337 static inline void 338 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 339 uint32_t value) 340 { 341 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 342 } 343 344 #if 0 /* unused */ 345 static inline uint64_t 346 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 347 { 348 uint64_t value; 349 350 if (sc->sc_ac64) { 351 #ifdef XHCI_USE_BUS_SPACE_8 352 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 353 #else 354 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 355 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 356 offset + 4) << 32; 357 #endif 358 } else { 359 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 360 } 361 362 return value; 363 } 364 #endif /* unused */ 365 366 static inline void 367 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 368 uint64_t value) 369 { 370 if (sc->sc_ac64) { 371 #ifdef XHCI_USE_BUS_SPACE_8 372 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 373 #else 374 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 375 (value >> 0) & 0xffffffff); 376 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 377 (value >> 32) & 0xffffffff); 378 #endif 379 } else { 380 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 381 } 382 } 383 384 #if 0 /* unused */ 385 static inline uint32_t 386 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 387 { 388 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 389 } 390 #endif /* unused */ 391 392 static inline void 393 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 394 uint32_t value) 395 { 396 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 397 } 398 399 /* --- */ 400 401 static inline uint8_t 402 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 403 { 404 u_int eptype = 0; 405 406 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 407 case UE_CONTROL: 408 eptype = 0x0; 409 break; 410 case UE_ISOCHRONOUS: 411 eptype = 0x1; 412 break; 413 case UE_BULK: 414 eptype = 0x2; 415 break; 416 case UE_INTERRUPT: 417 eptype = 0x3; 418 break; 419 } 420 421 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 422 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 423 return eptype | 0x4; 424 else 425 return eptype; 426 } 427 428 static u_int 429 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 430 { 431 /* xHCI 1.0 section 4.5.1 */ 432 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 433 u_int in = 0; 434 435 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 436 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 437 in = 1; 438 439 return epaddr * 2 + in; 440 } 441 442 static inline u_int 443 xhci_dci_to_ici(const u_int i) 444 { 445 return i + 1; 446 } 447 448 static inline void * 449 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 450 const u_int dci) 451 { 452 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 453 } 454 455 #if 0 /* unused */ 456 static inline bus_addr_t 457 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 458 const u_int dci) 459 { 460 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 461 } 462 #endif /* unused */ 463 464 static inline void * 465 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 466 const u_int ici) 467 { 468 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 469 } 470 471 static inline bus_addr_t 472 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 473 const u_int ici) 474 { 475 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 476 } 477 478 static inline struct xhci_trb * 479 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 480 { 481 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 482 } 483 484 static inline bus_addr_t 485 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 486 { 487 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 488 } 489 490 static inline void 491 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 492 uint32_t control) 493 { 494 trb->trb_0 = parameter; 495 trb->trb_2 = status; 496 trb->trb_3 = control; 497 } 498 499 /* --- */ 500 501 void 502 xhci_childdet(device_t self, device_t child) 503 { 504 struct xhci_softc * const sc = device_private(self); 505 506 KASSERT(sc->sc_child == child); 507 if (child == sc->sc_child) 508 sc->sc_child = NULL; 509 } 510 511 int 512 xhci_detach(struct xhci_softc *sc, int flags) 513 { 514 int rv = 0; 515 516 if (sc->sc_child != NULL) 517 rv = config_detach(sc->sc_child, flags); 518 519 if (rv != 0) 520 return rv; 521 522 /* XXX unconfigure/free slots */ 523 524 /* verify: */ 525 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 526 xhci_op_write_4(sc, XHCI_USBCMD, 0); 527 /* do we need to wait for stop? */ 528 529 xhci_op_write_8(sc, XHCI_CRCR, 0); 530 xhci_ring_free(sc, &sc->sc_cr); 531 cv_destroy(&sc->sc_command_cv); 532 533 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 534 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 535 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 536 xhci_ring_free(sc, &sc->sc_er); 537 538 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 539 540 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 541 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 542 543 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 544 545 mutex_destroy(&sc->sc_lock); 546 mutex_destroy(&sc->sc_intr_lock); 547 cv_destroy(&sc->sc_softwake_cv); 548 549 pool_cache_destroy(sc->sc_xferpool); 550 551 return rv; 552 } 553 554 int 555 xhci_activate(device_t self, enum devact act) 556 { 557 struct xhci_softc * const sc = device_private(self); 558 559 switch (act) { 560 case DVACT_DEACTIVATE: 561 sc->sc_dying = true; 562 return 0; 563 default: 564 return EOPNOTSUPP; 565 } 566 } 567 568 bool 569 xhci_suspend(device_t dv, const pmf_qual_t *qual) 570 { 571 return false; 572 } 573 574 bool 575 xhci_resume(device_t dv, const pmf_qual_t *qual) 576 { 577 return false; 578 } 579 580 bool 581 xhci_shutdown(device_t self, int flags) 582 { 583 return false; 584 } 585 586 587 static void 588 hexdump(const char *msg, const void *base, size_t len) 589 { 590 #if 0 591 size_t cnt; 592 const uint32_t *p; 593 extern paddr_t vtophys(vaddr_t); 594 595 p = base; 596 cnt = 0; 597 598 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 599 (void *)vtophys((vaddr_t)base)); 600 601 while (cnt < len) { 602 if (cnt % 16 == 0) 603 printf("%p: ", p); 604 else if (cnt % 8 == 0) 605 printf(" |"); 606 printf(" %08x", *p++); 607 cnt += 4; 608 if (cnt % 16 == 0) 609 printf("\n"); 610 } 611 #endif 612 } 613 614 615 int 616 xhci_init(struct xhci_softc *sc) 617 { 618 bus_size_t bsz; 619 uint32_t cap, hcs1, hcs2, hcc, dboff, rtsoff; 620 uint32_t ecp, ecr; 621 uint32_t usbcmd, usbsts, pagesize, config; 622 int i; 623 uint16_t hciversion; 624 uint8_t caplength; 625 626 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 627 628 /* XXX Low/Full/High speeds for now */ 629 sc->sc_bus.ub_revision = USBREV_2_0; 630 sc->sc_bus.ub_usedma = true; 631 632 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 633 caplength = XHCI_CAP_CAPLENGTH(cap); 634 hciversion = XHCI_CAP_HCIVERSION(cap); 635 636 if ((hciversion < 0x0096) || (hciversion > 0x0100)) { 637 aprint_normal_dev(sc->sc_dev, 638 "xHCI version %x.%x not known to be supported\n", 639 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 640 } else { 641 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 642 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 643 } 644 645 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 646 &sc->sc_cbh) != 0) { 647 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 648 return ENOMEM; 649 } 650 651 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 652 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 653 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 654 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 655 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 656 (void)xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 657 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 658 659 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 660 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 661 aprint_debug_dev(sc->sc_dev, "ac64 %d ctxsz %d\n", sc->sc_ac64, 662 sc->sc_ctxsz); 663 664 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 665 ecp = XHCI_HCC_XECP(hcc) * 4; 666 while (ecp != 0) { 667 ecr = xhci_read_4(sc, ecp); 668 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 669 switch (XHCI_XECP_ID(ecr)) { 670 case XHCI_ID_PROTOCOLS: { 671 uint32_t w0, w4, w8; 672 uint16_t w2; 673 w0 = xhci_read_4(sc, ecp + 0); 674 w2 = (w0 >> 16) & 0xffff; 675 w4 = xhci_read_4(sc, ecp + 4); 676 w8 = xhci_read_4(sc, ecp + 8); 677 aprint_debug_dev(sc->sc_dev, "SP: %08x %08x %08x\n", 678 w0, w4, w8); 679 if (w4 == 0x20425355 && w2 == 0x0300) { 680 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 681 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 682 } 683 if (w4 == 0x20425355 && w2 == 0x0200) { 684 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 685 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 686 } 687 break; 688 } 689 case XHCI_ID_USB_LEGACY: { 690 uint8_t bios_sem; 691 692 /* Take host controller from BIOS */ 693 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 694 if (bios_sem) { 695 /* sets xHCI to be owned by OS */ 696 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 697 aprint_debug( 698 "waiting for BIOS to give up control\n"); 699 for (i = 0; i < 5000; i++) { 700 bios_sem = xhci_read_1(sc, ecp + 701 XHCI_XECP_BIOS_SEM); 702 if (bios_sem == 0) 703 break; 704 DELAY(1000); 705 } 706 if (bios_sem) 707 printf("timed out waiting for BIOS\n"); 708 } 709 break; 710 } 711 default: 712 break; 713 } 714 ecr = xhci_read_4(sc, ecp); 715 if (XHCI_XECP_NEXT(ecr) == 0) { 716 ecp = 0; 717 } else { 718 ecp += XHCI_XECP_NEXT(ecr) * 4; 719 } 720 } 721 722 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 723 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 724 &sc->sc_obh) != 0) { 725 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 726 return ENOMEM; 727 } 728 729 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 730 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 731 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 732 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 733 return ENOMEM; 734 } 735 736 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 737 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 738 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 739 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 740 return ENOMEM; 741 } 742 743 for (i = 0; i < 100; i++) { 744 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 745 if ((usbsts & XHCI_STS_CNR) == 0) 746 break; 747 usb_delay_ms(&sc->sc_bus, 1); 748 } 749 if (i >= 100) 750 return EIO; 751 752 usbcmd = 0; 753 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 754 usb_delay_ms(&sc->sc_bus, 1); 755 756 usbcmd = XHCI_CMD_HCRST; 757 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 758 for (i = 0; i < 100; i++) { 759 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 760 if ((usbcmd & XHCI_CMD_HCRST) == 0) 761 break; 762 usb_delay_ms(&sc->sc_bus, 1); 763 } 764 if (i >= 100) 765 return EIO; 766 767 for (i = 0; i < 100; i++) { 768 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 769 if ((usbsts & XHCI_STS_CNR) == 0) 770 break; 771 usb_delay_ms(&sc->sc_bus, 1); 772 } 773 if (i >= 100) 774 return EIO; 775 776 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 777 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 778 pagesize = ffs(pagesize); 779 if (pagesize == 0) 780 return EIO; 781 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 782 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 783 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 784 (uint32_t)sc->sc_maxslots); 785 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 786 787 usbd_status err; 788 789 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 790 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 791 if (sc->sc_maxspbuf != 0) { 792 err = usb_allocmem(&sc->sc_bus, 793 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 794 &sc->sc_spbufarray_dma); 795 if (err) 796 return err; 797 798 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * sc->sc_maxspbuf, KM_SLEEP); 799 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 800 for (i = 0; i < sc->sc_maxspbuf; i++) { 801 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 802 /* allocate contexts */ 803 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 804 sc->sc_pgsz, dma); 805 if (err) 806 return err; 807 spbufarray[i] = htole64(DMAADDR(dma, 0)); 808 usb_syncmem(dma, 0, sc->sc_pgsz, 809 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 810 } 811 812 usb_syncmem(&sc->sc_spbufarray_dma, 0, 813 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 814 } 815 816 config = xhci_op_read_4(sc, XHCI_CONFIG); 817 config &= ~0xFF; 818 config |= sc->sc_maxslots & 0xFF; 819 xhci_op_write_4(sc, XHCI_CONFIG, config); 820 821 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 822 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 823 if (err) { 824 aprint_error_dev(sc->sc_dev, "command ring init fail\n"); 825 return err; 826 } 827 828 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 829 XHCI_EVENT_RING_SEGMENTS_ALIGN); 830 if (err) { 831 aprint_error_dev(sc->sc_dev, "event ring init fail\n"); 832 return err; 833 } 834 835 usb_dma_t *dma; 836 size_t size; 837 size_t align; 838 839 dma = &sc->sc_eventst_dma; 840 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 841 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 842 KASSERT(size <= (512 * 1024)); 843 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 844 err = usb_allocmem(&sc->sc_bus, size, align, dma); 845 846 memset(KERNADDR(dma, 0), 0, size); 847 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 848 aprint_debug_dev(sc->sc_dev, "eventst: %s %016jx %p %zx\n", 849 usbd_errstr(err), 850 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 851 KERNADDR(&sc->sc_eventst_dma, 0), 852 sc->sc_eventst_dma.udma_block->size); 853 854 dma = &sc->sc_dcbaa_dma; 855 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 856 KASSERT(size <= 2048); 857 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 858 err = usb_allocmem(&sc->sc_bus, size, align, dma); 859 860 memset(KERNADDR(dma, 0), 0, size); 861 if (sc->sc_maxspbuf != 0) { 862 /* 863 * DCBA entry 0 hold the scratchbuf array pointer. 864 */ 865 *(uint64_t *)KERNADDR(dma, 0) = 866 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 867 } 868 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 869 aprint_debug_dev(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n", 870 usbd_errstr(err), 871 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 872 KERNADDR(&sc->sc_dcbaa_dma, 0), 873 sc->sc_dcbaa_dma.udma_block->size); 874 875 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 876 KM_SLEEP); 877 878 cv_init(&sc->sc_command_cv, "xhcicmd"); 879 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 880 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 881 cv_init(&sc->sc_softwake_cv, "xhciab"); 882 883 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 884 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 885 886 /* Set up the bus struct. */ 887 sc->sc_bus.ub_methods = &xhci_bus_methods; 888 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 889 890 struct xhci_erste *erst; 891 erst = KERNADDR(&sc->sc_eventst_dma, 0); 892 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 893 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 894 erst[0].erste_3 = htole32(0); 895 usb_syncmem(&sc->sc_eventst_dma, 0, 896 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 897 898 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 899 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 900 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 901 XHCI_ERDP_LO_BUSY); 902 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 903 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 904 sc->sc_cr.xr_cs); 905 906 #if 0 907 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 908 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 909 #endif 910 911 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 912 #ifdef XHCI_QUIRK_INTEL 913 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 914 /* Intel xhci needs interrupt rate moderated. */ 915 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 916 else 917 #endif /* XHCI_QUIRK_INTEL */ 918 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 919 920 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 921 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 922 xhci_op_read_4(sc, XHCI_USBCMD)); 923 924 return USBD_NORMAL_COMPLETION; 925 } 926 927 int 928 xhci_intr(void *v) 929 { 930 struct xhci_softc * const sc = v; 931 int ret = 0; 932 933 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 934 935 if (sc == NULL) 936 return 0; 937 938 mutex_spin_enter(&sc->sc_intr_lock); 939 940 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 941 goto done; 942 943 /* If we get an interrupt while polling, then just ignore it. */ 944 if (sc->sc_bus.ub_usepolling) { 945 #ifdef DIAGNOSTIC 946 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 947 #endif 948 goto done; 949 } 950 951 ret = xhci_intr1(sc); 952 done: 953 mutex_spin_exit(&sc->sc_intr_lock); 954 return ret; 955 } 956 957 int 958 xhci_intr1(struct xhci_softc * const sc) 959 { 960 uint32_t usbsts; 961 uint32_t iman; 962 963 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 964 965 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 966 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 967 #if 0 968 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 969 return 0; 970 } 971 #endif 972 xhci_op_write_4(sc, XHCI_USBSTS, 973 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 974 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 975 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 976 977 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 978 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 979 #ifdef XHCI_QUIRK_FORCE_INTR 980 981 if (!(sc->sc_quirks & XHCI_QUIRK_FORCE_INTR)) { 982 if ((iman & XHCI_IMAN_INTR_PEND) == 0) { 983 return 0; 984 } 985 } 986 987 #else 988 if ((iman & XHCI_IMAN_INTR_PEND) == 0) { 989 return 0; 990 } 991 #endif /* XHCI_QUIRK_FORCE_INTR */ 992 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 993 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 994 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 995 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 996 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 997 998 usb_schedsoftintr(&sc->sc_bus); 999 1000 return 1; 1001 } 1002 1003 /* 1004 * 3 port speed types used in USB stack 1005 * 1006 * usbdi speed 1007 * definition: USB_SPEED_* in usb.h 1008 * They are used in struct usbd_device in USB stack. 1009 * ioctl interface uses these values too. 1010 * port_status speed 1011 * definition: UPS_*_SPEED in usb.h 1012 * They are used in usb_port_status_t. 1013 * Some 3.0 values overlap with 2.0 values. 1014 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1015 * means UPS_LOW_SPEED in HS.) 1016 * port status sent from hub also uses these values. 1017 * (but I've never seen UPS_SUPER_SPEED in port_status from hub.) 1018 * xspeed: 1019 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1020 * They are used in only slot context and PORTSC reg of xhci. 1021 * The difference between usbdi speed and them are that 1022 * FS and LS values are swapped. 1023 */ 1024 1025 static int 1026 xhci_speed2xspeed(int speed) 1027 { 1028 switch (speed) { 1029 case USB_SPEED_LOW: return 2; 1030 case USB_SPEED_FULL: return 1; 1031 case USB_SPEED_HIGH: return 3; 1032 case USB_SPEED_SUPER: return 4; 1033 default: 1034 break; 1035 } 1036 return 0; 1037 } 1038 1039 /* construct slot context */ 1040 static void 1041 xhci_setup_sctx(struct usbd_device *dev, uint32_t *cp) 1042 { 1043 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 1044 int speed = dev->ud_speed; 1045 int tthubslot, ttportnum; 1046 bool ishub; 1047 bool usemtt; 1048 1049 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1050 1051 /* 6.2.2 */ 1052 /* 1053 * tthubslot: 1054 * This is the slot ID of parent HS hub 1055 * if LS/FS device is connected && connected through HS hub. 1056 * This is 0 if device is not LS/FS device || 1057 * parent hub is not HS hub || 1058 * attached to root hub. 1059 * ttportnum: 1060 * This is the downstream facing port of parent HS hub 1061 * if LS/FS device is connected. 1062 * This is 0 if device is not LS/FS device || 1063 * parent hub is not HS hub || 1064 * attached to root hub. 1065 */ 1066 if (dev->ud_myhsport != NULL && 1067 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1068 (dev->ud_myhub != NULL && 1069 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1070 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 1071 ttportnum = dev->ud_myhsport->up_portno; 1072 /* XXX addr == slot ? */ 1073 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 1074 } else { 1075 ttportnum = 0; 1076 tthubslot = 0; 1077 } 1078 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 1079 dev->ud_myhsport, ttportnum, tthubslot, 0); 1080 1081 /* ishub is valid after reading UDESC_DEVICE */ 1082 ishub = (dd->bDeviceClass == UDCLASS_HUB); 1083 1084 /* dev->ud_hub is valid after reading UDESC_HUB */ 1085 if (ishub && dev->ud_hub) { 1086 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 1087 1088 cp[1] |= htole32(XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts)); 1089 cp[2] |= htole32(XHCI_SCTX_2_TT_THINK_TIME_SET( 1090 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK))); 1091 DPRINTFN(4, "nports=%d ttt=%d", 1092 hd->bNbrPorts, XHCI_SCTX_2_TT_THINK_TIME_GET(cp[2]), 0, 0); 1093 } 1094 1095 #define IS_TTHUB(dd) \ 1096 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 1097 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 1098 1099 /* 1100 * MTT flag is set if 1101 * 1. this is HS hub && MTT is enabled 1102 * or 1103 * 2. this is not hub && this is LS or FS device && 1104 * MTT of parent HS hub (and its parent, too) is enabled 1105 */ 1106 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 1107 usemtt = true; 1108 else if (!ishub && 1109 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 1110 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1111 (dev->ud_myhub != NULL && 1112 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1113 dev->ud_myhsport != NULL && 1114 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 1115 usemtt = true; 1116 else 1117 usemtt = false; 1118 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 1119 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 1120 1121 cp[0] |= htole32( 1122 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)) | 1123 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 1124 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0) 1125 ); 1126 cp[1] |= htole32(0); 1127 cp[2] |= htole32( 1128 XHCI_SCTX_2_IRQ_TARGET_SET(0) | 1129 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 1130 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum) 1131 ); 1132 cp[3] |= htole32(0); 1133 } 1134 1135 /* 1136 * called 1137 * from xhci_open 1138 * from usbd_setup_pipe_flags 1139 * from usbd_open_pipe_ival 1140 */ 1141 static usbd_status 1142 xhci_configure_endpoint(struct usbd_pipe *pipe) 1143 { 1144 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1145 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1146 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1147 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1148 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1149 struct xhci_trb trb; 1150 usbd_status err; 1151 uint32_t *cp; 1152 uint32_t mps = UGETW(ed->wMaxPacketSize); 1153 uint32_t maxb = 0; 1154 int speed = pipe->up_dev->ud_speed; 1155 uint32_t ival = ed->bInterval; 1156 1157 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1158 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1159 xs->xs_idx, dci, ed->bEndpointAddress, ed->bmAttributes); 1160 1161 /* XXX ensure input context is available? */ 1162 1163 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1164 1165 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1166 cp[0] = htole32(0); 1167 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 1168 1169 /* set up input slot context */ 1170 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1171 xhci_setup_sctx(pipe->up_dev, cp); 1172 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1173 1174 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 1175 cp[0] = htole32( 1176 XHCI_EPCTX_0_EPSTATE_SET(0) | 1177 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 1178 XHCI_EPCTX_0_LSA_SET(0) 1179 ); 1180 cp[1] = htole32( 1181 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 1182 XHCI_EPCTX_1_MAXB_SET(0) 1183 ); 1184 if (xfertype != UE_ISOCHRONOUS) 1185 cp[1] |= htole32(XHCI_EPCTX_1_CERR_SET(3)); 1186 1187 if (speed == USB_SPEED_SUPER) { 1188 usbd_desc_iter_t iter; 1189 const usb_cdc_descriptor_t *cdcd; 1190 const usb_endpoint_ss_comp_descriptor_t * esscd = NULL; 1191 uint8_t ep; 1192 1193 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc( 1194 pipe->up_dev, UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 1195 usb_desc_iter_init(pipe->up_dev, &iter); 1196 iter.cur = (const void *)cdcd; 1197 1198 /* find endpoint_ss_comp desc for ep of this pipe */ 1199 for(ep = 0;;) { 1200 cdcd = (const usb_cdc_descriptor_t *) 1201 usb_desc_iter_next(&iter); 1202 if (cdcd == NULL) 1203 break; 1204 if (ep == 0 && 1205 cdcd->bDescriptorType == UDESC_ENDPOINT) { 1206 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 1207 bEndpointAddress; 1208 if (UE_GET_ADDR(ep) == 1209 UE_GET_ADDR(ed->bEndpointAddress)) { 1210 cdcd = (const usb_cdc_descriptor_t *) 1211 usb_desc_iter_next(&iter); 1212 break; 1213 } 1214 ep = 0; 1215 } 1216 } 1217 if (cdcd != NULL && 1218 cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 1219 esscd = (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 1220 maxb = esscd->bMaxBurst; 1221 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1222 DPRINTFN(4, "setting SS MaxBurst %u", maxb, 0, 0, 0); 1223 } 1224 } 1225 if (speed == USB_SPEED_HIGH && 1226 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 1227 maxb = UE_GET_TRANS(UGETW(ed->wMaxPacketSize)); 1228 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1229 DPRINTFN(4, "setting HS MaxBurst %u", maxb, 0, 0, 0); 1230 } 1231 1232 switch (xfertype) { 1233 case UE_INTERRUPT: 1234 /* 6.2.3.6 */ 1235 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 1236 ival = ival > 10 ? 10 : ival; 1237 ival = ival < 3 ? 3 : ival; 1238 } else { 1239 ival = ival > 15 ? 15 : ival; 1240 } 1241 if (speed == USB_SPEED_SUPER) { 1242 if (maxb > 0) 1243 mps = 1024; 1244 } else { 1245 mps = mps ? mps : 8; 1246 } 1247 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1248 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1249 cp[4] = htole32( 1250 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) /* XXX */ 1251 ); 1252 break; 1253 case UE_CONTROL: 1254 if (speed == USB_SPEED_SUPER) 1255 mps = 512; 1256 else 1257 mps = mps ? mps : 8; 1258 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1259 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(8)); /* XXX */ 1260 break; 1261 #ifdef notyet 1262 case UE_ISOCHRONOUS: 1263 if (speed == USB_SPEED_FULL) { 1264 ival = ival > 18 ? 18 : ival; 1265 ival = ival < 3 ? 3 : ival; 1266 } else { 1267 ival = ival > 15 ? 15 : ival; 1268 } 1269 if (speed == USB_SPEED_SUPER) { 1270 mps = 1024; 1271 } else { 1272 mps = mps ? mps : 1024; 1273 } 1274 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1275 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(1024)); /* XXX */ 1276 break; 1277 #endif 1278 default: 1279 if (speed == USB_SPEED_SUPER) 1280 mps = 1024; 1281 else 1282 mps = mps ? mps : 512; 1283 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1284 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(1024)); /* XXX */ 1285 break; 1286 } 1287 *(uint64_t *)(&cp[2]) = htole64( 1288 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 1289 XHCI_EPCTX_2_DCS_SET(1)); 1290 1291 /* sync input contexts before they are read from memory */ 1292 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1293 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1294 sc->sc_ctxsz * 1); 1295 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1296 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1297 1298 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1299 trb.trb_2 = 0; 1300 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1301 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1302 1303 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1304 1305 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1306 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1307 sc->sc_ctxsz * 1); 1308 1309 return err; 1310 } 1311 1312 #if 0 1313 static usbd_status 1314 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1315 { 1316 #ifdef USB_DEBUG 1317 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1318 #endif 1319 1320 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1321 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1322 1323 return USBD_NORMAL_COMPLETION; 1324 } 1325 #endif 1326 1327 /* 4.6.8, 6.4.3.7 */ 1328 static usbd_status 1329 xhci_reset_endpoint(struct usbd_pipe *pipe) 1330 { 1331 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1332 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1333 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1334 struct xhci_trb trb; 1335 usbd_status err; 1336 1337 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1338 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1339 1340 KASSERT(!mutex_owned(&sc->sc_lock)); 1341 1342 trb.trb_0 = 0; 1343 trb.trb_2 = 0; 1344 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1345 XHCI_TRB_3_EP_SET(dci) | 1346 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1347 1348 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1349 1350 return err; 1351 } 1352 1353 /* 1354 * 4.6.9, 6.4.3.8 1355 * Stop execution of TDs on xfer ring. 1356 * Should be called with sc_lock held. 1357 */ 1358 static usbd_status 1359 xhci_stop_endpoint(struct usbd_pipe *pipe) 1360 { 1361 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1362 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1363 struct xhci_trb trb; 1364 usbd_status err; 1365 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1366 1367 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1368 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1369 1370 KASSERT(mutex_owned(&sc->sc_lock)); 1371 1372 trb.trb_0 = 0; 1373 trb.trb_2 = 0; 1374 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1375 XHCI_TRB_3_EP_SET(dci) | 1376 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1377 1378 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1379 1380 return err; 1381 } 1382 1383 /* 1384 * Set TR Dequeue Pointer. 1385 * xCHI 1.1 4.6.10 6.4.3.9 1386 * Purge all of the transfer requests on ring. 1387 * EPSTATE of endpoint must be ERROR or STOPPED, or CONTEXT_STATE error. 1388 */ 1389 static usbd_status 1390 xhci_set_dequeue(struct usbd_pipe *pipe) 1391 { 1392 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1393 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1394 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1395 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1396 struct xhci_trb trb; 1397 usbd_status err; 1398 1399 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1400 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1401 1402 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1403 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1404 BUS_DMASYNC_PREWRITE); 1405 1406 xr->xr_ep = 0; 1407 xr->xr_cs = 1; 1408 1409 /* set DCS */ 1410 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1411 trb.trb_2 = 0; 1412 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1413 XHCI_TRB_3_EP_SET(dci) | 1414 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1415 1416 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1417 1418 return err; 1419 } 1420 1421 /* 1422 * Open new pipe: called from usbd_setup_pipe_flags. 1423 * Fills methods of pipe. 1424 * If pipe is not for ep0, calls configure_endpoint. 1425 */ 1426 static usbd_status 1427 xhci_open(struct usbd_pipe *pipe) 1428 { 1429 struct usbd_device * const dev = pipe->up_dev; 1430 struct xhci_softc * const sc = dev->ud_bus->ub_hcpriv; 1431 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1432 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1433 1434 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1435 DPRINTFN(1, "addr %d depth %d port %d speed %d", 1436 dev->ud_addr, dev->ud_depth, dev->ud_powersrc->up_portno, 1437 dev->ud_speed); 1438 1439 if (sc->sc_dying) 1440 return USBD_IOERROR; 1441 1442 /* Root Hub */ 1443 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1444 switch (ed->bEndpointAddress) { 1445 case USB_CONTROL_ENDPOINT: 1446 pipe->up_methods = &roothub_ctrl_methods; 1447 break; 1448 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1449 pipe->up_methods = &xhci_root_intr_methods; 1450 break; 1451 default: 1452 pipe->up_methods = NULL; 1453 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1454 ed->bEndpointAddress, 0, 0, 0); 1455 return USBD_INVAL; 1456 } 1457 return USBD_NORMAL_COMPLETION; 1458 } 1459 1460 switch (xfertype) { 1461 case UE_CONTROL: 1462 pipe->up_methods = &xhci_device_ctrl_methods; 1463 break; 1464 case UE_ISOCHRONOUS: 1465 pipe->up_methods = &xhci_device_isoc_methods; 1466 return USBD_INVAL; 1467 break; 1468 case UE_BULK: 1469 pipe->up_methods = &xhci_device_bulk_methods; 1470 break; 1471 case UE_INTERRUPT: 1472 pipe->up_methods = &xhci_device_intr_methods; 1473 break; 1474 default: 1475 return USBD_IOERROR; 1476 break; 1477 } 1478 1479 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1480 return xhci_configure_endpoint(pipe); 1481 1482 return USBD_NORMAL_COMPLETION; 1483 } 1484 1485 /* 1486 * Closes pipe, called from usbd_kill_pipe via close methods. 1487 * If the endpoint to be closed is ep0, disable_slot. 1488 * Should be called with sc_lock held. 1489 */ 1490 static usbd_status 1491 xhci_close_pipe(struct usbd_pipe *pipe) 1492 { 1493 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1494 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1495 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1496 const u_int dci = xhci_ep_get_dci(ed); 1497 struct xhci_trb trb; 1498 usbd_status err; 1499 uint32_t *cp; 1500 1501 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1502 1503 if (sc->sc_dying) 1504 return USBD_IOERROR; 1505 1506 if (xs == NULL || xs->xs_idx == 0) 1507 /* xs is uninitialized before xhci_init_slot */ 1508 return USBD_IOERROR; 1509 1510 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1511 1512 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1513 KASSERT(mutex_owned(&sc->sc_lock)); 1514 1515 if (pipe->up_dev->ud_depth == 0) 1516 return USBD_NORMAL_COMPLETION; 1517 1518 if (dci == XHCI_DCI_EP_CONTROL) { 1519 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1520 return xhci_disable_slot(sc, xs->xs_idx); 1521 } 1522 1523 /* 1524 * This may fail in the case that xhci_close_pipe is called after 1525 * xhci_abort_xfer e.g. usbd_kill_pipe. 1526 */ 1527 (void)xhci_stop_endpoint(pipe); 1528 1529 /* 1530 * set appropriate bit to be dropped. 1531 * don't set DC bit to 1, otherwise all endpoints 1532 * would be deconfigured. 1533 */ 1534 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1535 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1536 cp[1] = htole32(0); 1537 1538 /* XXX should be most significant one, not dci? */ 1539 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1540 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1541 1542 /* sync input contexts before they are read from memory */ 1543 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1544 1545 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1546 trb.trb_2 = 0; 1547 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1548 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1549 1550 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1551 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1552 1553 return err; 1554 } 1555 1556 /* 1557 * Abort transfer. 1558 * Called with sc_lock held. 1559 * May be called from softintr context. 1560 */ 1561 static void 1562 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1563 { 1564 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1565 1566 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1567 DPRINTFN(4, "xfer %p pipe %p status %d", 1568 xfer, xfer->ux_pipe, status, 0); 1569 1570 KASSERT(mutex_owned(&sc->sc_lock)); 1571 1572 if (sc->sc_dying) { 1573 /* If we're dying, just do the software part. */ 1574 DPRINTFN(4, "dying", 0, 0, 0, 0); 1575 xfer->ux_status = status; /* make software ignore it */ 1576 callout_stop(&xfer->ux_callout); 1577 usb_transfer_complete(xfer); 1578 return; 1579 } 1580 1581 /* XXX need more stuff */ 1582 xfer->ux_status = status; 1583 callout_stop(&xfer->ux_callout); 1584 usb_transfer_complete(xfer); 1585 1586 KASSERT(mutex_owned(&sc->sc_lock)); 1587 } 1588 1589 #if 1 /* XXX experimental */ 1590 /* 1591 * Recover STALLed endpoint. 1592 * xHCI 1.1 sect 4.10.2.1 1593 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1594 * all transfers on transfer ring. 1595 * These are done in thread context asynchronously. 1596 */ 1597 static void 1598 xhci_clear_endpoint_stall_async_task(void *cookie) 1599 { 1600 struct usbd_xfer * const xfer = cookie; 1601 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1602 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1603 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1604 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1605 1606 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1607 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1608 1609 xhci_reset_endpoint(xfer->ux_pipe); 1610 xhci_set_dequeue(xfer->ux_pipe); 1611 1612 mutex_enter(&sc->sc_lock); 1613 tr->is_halted = false; 1614 usb_transfer_complete(xfer); 1615 mutex_exit(&sc->sc_lock); 1616 DPRINTFN(4, "ends", 0, 0, 0, 0); 1617 } 1618 1619 static usbd_status 1620 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1621 { 1622 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1623 1624 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1625 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1626 1627 if (sc->sc_dying) { 1628 return USBD_IOERROR; 1629 } 1630 1631 /* XXX never use up_async_task for incompatible type of function */ 1632 usb_init_task(&xfer->ux_pipe->up_async_task, 1633 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1634 usb_add_task(xfer->ux_pipe->up_dev, &xfer->ux_pipe->up_async_task, 1635 USB_TASKQ_HC); 1636 DPRINTFN(4, "ends", 0, 0, 0, 0); 1637 1638 return USBD_NORMAL_COMPLETION; 1639 } 1640 1641 #endif /* XXX experimental */ 1642 1643 /* 1644 * Notify roothub port status/change to uhub_intr. 1645 */ 1646 static void 1647 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1648 { 1649 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1650 uint8_t *p; 1651 1652 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1653 DPRINTFN(4, "port %u status change", port, 0, 0, 0); 1654 1655 if (xfer == NULL) 1656 return; 1657 1658 p = xfer->ux_buf; 1659 memset(p, 0, xfer->ux_length); 1660 p[port/NBBY] |= 1 << (port%NBBY); 1661 xfer->ux_actlen = xfer->ux_length; 1662 xfer->ux_status = USBD_NORMAL_COMPLETION; 1663 usb_transfer_complete(xfer); 1664 } 1665 1666 /* 1667 * Process events: 1668 * + Transfer comeplete 1669 * + Command complete 1670 * + Roothub Port status/change 1671 */ 1672 static void 1673 xhci_handle_event(struct xhci_softc * const sc, 1674 const struct xhci_trb * const trb) 1675 { 1676 uint64_t trb_0; 1677 uint32_t trb_2, trb_3; 1678 uint8_t trberr; 1679 1680 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1681 1682 trb_0 = le64toh(trb->trb_0); 1683 trb_2 = le32toh(trb->trb_2); 1684 trb_3 = le32toh(trb->trb_3); 1685 trberr = XHCI_TRB_2_ERROR_GET(trb_2); 1686 1687 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1688 trb, trb_0, trb_2, trb_3); 1689 1690 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 1691 case XHCI_TRB_EVENT_TRANSFER: { 1692 u_int slot, dci; 1693 struct xhci_slot *xs; 1694 struct xhci_ring *xr; 1695 struct xhci_xfer *xx; 1696 struct usbd_xfer *xfer; 1697 usbd_status err; 1698 1699 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1700 dci = XHCI_TRB_3_EP_GET(trb_3); 1701 1702 xs = &sc->sc_slots[slot]; 1703 xr = &xs->xs_ep[dci].xe_tr; 1704 /* sanity check */ 1705 KASSERT(xs->xs_idx != 0); 1706 1707 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1708 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 1709 1710 /* trb_0 range sanity check */ 1711 if (trb_0 < trbp || 1712 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 1713 (trb_0 - trbp) / sizeof(struct xhci_trb) >= 1714 xr->xr_ntrb) { 1715 DPRINTFN(1, 1716 "invalid trb_0 0x%"PRIx64" trbp 0x%"PRIx64, 1717 trb_0, trbp, 0, 0); 1718 break; 1719 } 1720 int idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 1721 xx = xr->xr_cookies[idx]; 1722 } else { 1723 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1724 } 1725 xfer = &xx->xx_xfer; 1726 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1727 1728 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1729 DPRINTFN(14, "transfer event data: " 1730 "0x%016"PRIx64" 0x%08"PRIx32" %02x", 1731 trb_0, XHCI_TRB_2_REM_GET(trb_2), 1732 XHCI_TRB_2_ERROR_GET(trb_2), 0); 1733 if ((trb_0 & 0x3) == 0x3) { 1734 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1735 } 1736 } 1737 1738 if (trberr == XHCI_TRB_ERROR_SUCCESS || 1739 trberr == XHCI_TRB_ERROR_SHORT_PKT) { 1740 xfer->ux_actlen = 1741 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1742 err = USBD_NORMAL_COMPLETION; 1743 } else if (trberr == XHCI_TRB_ERROR_STALL || 1744 trberr == XHCI_TRB_ERROR_BABBLE) { 1745 err = USBD_STALLED; 1746 xr->is_halted = true; 1747 DPRINTFN(1, "evh: xfer done: ERR %u slot %u dci %u", 1748 trberr, slot, dci, 0); 1749 #if 1 /* XXX experimental */ 1750 /* 1751 * Stalled endpoints can be recoverd by issuing 1752 * command TRB TYPE_RESET_EP on xHCI instead of 1753 * issuing request CLEAR_PORT_FEATURE UF_ENDPOINT_HALT 1754 * on the endpoint. However, this function may be 1755 * called from softint context (e.g. from umass), 1756 * in that case driver gets KASSERT in cv_timedwait 1757 * in xhci_do_command. 1758 * To avoid this, this runs reset_endpoint and 1759 * usb_transfer_complete in usb task thread 1760 * asynchronously (and then umass issues clear 1761 * UF_ENDPOINT_HALT). 1762 */ 1763 xfer->ux_status = err; 1764 xhci_clear_endpoint_stall_async(xfer); 1765 break; 1766 #endif 1767 } else { 1768 DPRINTFN(1, "evh: xfer done: ERR %u slot %u dci %u", 1769 trberr, slot, dci, 0); 1770 err = USBD_IOERROR; 1771 } 1772 xfer->ux_status = err; 1773 1774 //mutex_enter(&sc->sc_lock); /* XXX ??? */ 1775 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1776 if ((trb_0 & 0x3) == 0x0) { 1777 usb_transfer_complete(xfer); 1778 } 1779 } else { 1780 usb_transfer_complete(xfer); 1781 } 1782 //mutex_exit(&sc->sc_lock); /* XXX ??? */ 1783 1784 } 1785 break; 1786 case XHCI_TRB_EVENT_CMD_COMPLETE: 1787 if (trb_0 == sc->sc_command_addr) { 1788 sc->sc_result_trb.trb_0 = trb_0; 1789 sc->sc_result_trb.trb_2 = trb_2; 1790 sc->sc_result_trb.trb_3 = trb_3; 1791 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1792 XHCI_TRB_ERROR_SUCCESS) { 1793 DPRINTFN(1, "command completion " 1794 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1795 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1796 } 1797 cv_signal(&sc->sc_command_cv); 1798 } else { 1799 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 1800 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1801 trb_2, trb_3); 1802 } 1803 break; 1804 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1805 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1806 break; 1807 default: 1808 break; 1809 } 1810 } 1811 1812 static void 1813 xhci_softintr(void *v) 1814 { 1815 struct usbd_bus * const bus = v; 1816 struct xhci_softc * const sc = bus->ub_hcpriv; 1817 struct xhci_ring * const er = &sc->sc_er; 1818 struct xhci_trb *trb; 1819 int i, j, k; 1820 1821 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1822 1823 i = er->xr_ep; 1824 j = er->xr_cs; 1825 1826 DPRINTFN(16, "xr_ep %d xr_cs %d", i, j, 0, 0); 1827 1828 while (1) { 1829 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 1830 BUS_DMASYNC_POSTREAD); 1831 trb = &er->xr_trb[i]; 1832 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1833 1834 if (j != k) 1835 break; 1836 1837 xhci_handle_event(sc, trb); 1838 1839 i++; 1840 if (i == XHCI_EVENT_RING_TRBS) { 1841 i = 0; 1842 j ^= 1; 1843 } 1844 } 1845 1846 er->xr_ep = i; 1847 er->xr_cs = j; 1848 1849 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 1850 XHCI_ERDP_LO_BUSY); 1851 1852 DPRINTFN(16, "ends", 0, 0, 0, 0); 1853 1854 return; 1855 } 1856 1857 static void 1858 xhci_poll(struct usbd_bus *bus) 1859 { 1860 struct xhci_softc * const sc = bus->ub_hcpriv; 1861 1862 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1863 1864 mutex_spin_enter(&sc->sc_intr_lock); 1865 xhci_intr1(sc); 1866 mutex_spin_exit(&sc->sc_intr_lock); 1867 1868 return; 1869 } 1870 1871 static struct usbd_xfer * 1872 xhci_allocx(struct usbd_bus *bus) 1873 { 1874 struct xhci_softc * const sc = bus->ub_hcpriv; 1875 struct usbd_xfer *xfer; 1876 1877 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1878 1879 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1880 if (xfer != NULL) { 1881 memset(xfer, 0, sizeof(struct xhci_xfer)); 1882 #ifdef DIAGNOSTIC 1883 xfer->ux_state = XFER_BUSY; 1884 #endif 1885 } 1886 1887 return xfer; 1888 } 1889 1890 static void 1891 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1892 { 1893 struct xhci_softc * const sc = bus->ub_hcpriv; 1894 1895 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1896 1897 #ifdef DIAGNOSTIC 1898 if (xfer->ux_state != XFER_BUSY) { 1899 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 1900 xfer, xfer->ux_state, 0, 0); 1901 } 1902 xfer->ux_state = XFER_FREE; 1903 #endif 1904 pool_cache_put(sc->sc_xferpool, xfer); 1905 } 1906 1907 static void 1908 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1909 { 1910 struct xhci_softc * const sc = bus->ub_hcpriv; 1911 1912 *lock = &sc->sc_lock; 1913 } 1914 1915 extern uint32_t usb_cookie_no; 1916 1917 /* 1918 * Called if uhub_explore find new device (via usbd_new_device). 1919 * Allocate and construct dev structure of default endpoint (ep0). 1920 * Determine initial MaxPacketSize (mps) by speed. 1921 * Determine route string and roothub port for slot of dev. 1922 * Allocate pipe of ep0. 1923 * Enable and initialize slot and Set Address. 1924 * Read device descriptor. 1925 * Register this device. 1926 */ 1927 static usbd_status 1928 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 1929 int speed, int port, struct usbd_port *up) 1930 { 1931 struct xhci_softc * const sc = bus->ub_hcpriv; 1932 struct usbd_device *dev; 1933 usbd_status err; 1934 usb_device_descriptor_t *dd; 1935 struct usbd_device *hub; 1936 struct usbd_device *adev; 1937 int rhport = 0; 1938 struct xhci_slot *xs; 1939 uint32_t *cp; 1940 uint32_t route = 0; 1941 uint8_t slot = 0; 1942 uint8_t addr; 1943 1944 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1945 DPRINTFN(4, "port=%d depth=%d speed=%d upport %d", 1946 port, depth, speed, up->up_portno); 1947 1948 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 1949 if (dev == NULL) 1950 return USBD_NOMEM; 1951 1952 dev->ud_bus = bus; 1953 1954 /* Set up default endpoint handle. */ 1955 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 1956 1957 /* Set up default endpoint descriptor. */ 1958 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 1959 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 1960 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 1961 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 1962 /* 4.3, 4.8.2.1 */ 1963 switch (speed) { 1964 case USB_SPEED_SUPER: 1965 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 1966 break; 1967 case USB_SPEED_FULL: 1968 /* XXX using 64 as initial mps of ep0 in FS */ 1969 case USB_SPEED_HIGH: 1970 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 1971 break; 1972 case USB_SPEED_LOW: 1973 default: 1974 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 1975 break; 1976 } 1977 dev->ud_ep0desc.bInterval = 0; 1978 1979 /* doesn't matter, just don't let it uninitialized */ 1980 dev->ud_ep0.ue_toggle = 0; 1981 1982 DPRINTFN(4, "up %p portno %d", up, up->up_portno, 0, 0); 1983 1984 dev->ud_quirks = &usbd_no_quirk; 1985 dev->ud_addr = 0; 1986 dev->ud_ddesc.bMaxPacketSize = 0; 1987 dev->ud_depth = depth; 1988 dev->ud_powersrc = up; 1989 dev->ud_myhub = up->up_parent; 1990 1991 up->up_dev = dev; 1992 1993 /* Locate root hub port */ 1994 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 1995 uint32_t dep; 1996 1997 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 1998 hub, hub->ud_depth, hub->ud_powersrc, 1999 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2000 2001 if (hub->ud_powersrc == NULL) 2002 break; 2003 dep = hub->ud_depth; 2004 if (dep == 0) 2005 break; 2006 rhport = hub->ud_powersrc->up_portno; 2007 if (dep > USB_HUB_MAX_DEPTH) 2008 continue; 2009 2010 route |= 2011 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2012 << ((dep - 1) * 4); 2013 } 2014 route = route >> 4; 2015 DPRINTFN(4, "rhport %d Route %05x hub %p", rhport, route, hub, 0); 2016 2017 /* Locate port on upstream high speed hub */ 2018 for (adev = dev, hub = up->up_parent; 2019 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2020 adev = hub, hub = hub->ud_myhub) 2021 ; 2022 if (hub) { 2023 int p; 2024 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2025 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2026 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2027 goto found; 2028 } 2029 } 2030 panic("xhci_new_device: cannot find HS port"); 2031 found: 2032 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2033 } else { 2034 dev->ud_myhsport = NULL; 2035 } 2036 2037 dev->ud_speed = speed; 2038 dev->ud_langid = USBD_NOLANG; 2039 dev->ud_cookie.cookie = ++usb_cookie_no; 2040 2041 /* Establish the default pipe. */ 2042 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2043 &dev->ud_pipe0); 2044 if (err) { 2045 goto bad; 2046 } 2047 2048 dd = &dev->ud_ddesc; 2049 2050 if ((depth == 0) && (port == 0)) { 2051 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2052 bus->ub_devices[dev->ud_addr] = dev; 2053 err = usbd_get_initial_ddesc(dev, dd); 2054 if (err) 2055 goto bad; 2056 err = usbd_reload_device_desc(dev); 2057 if (err) 2058 goto bad; 2059 } else { 2060 err = xhci_enable_slot(sc, &slot); 2061 if (err) 2062 goto bad; 2063 xs = &sc->sc_slots[slot]; 2064 dev->ud_hcpriv = xs; 2065 err = xhci_init_slot(dev, slot, route, rhport); 2066 if (err) { 2067 dev->ud_hcpriv = NULL; 2068 goto bad; 2069 } 2070 2071 /* Allow device time to set new address */ 2072 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2073 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2074 //hexdump("slot context", cp, sc->sc_ctxsz); 2075 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2076 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2077 /* XXX ensure we know when the hardware does something 2078 we can't yet cope with */ 2079 KASSERT(addr >= 1 && addr <= 127); 2080 dev->ud_addr = addr; 2081 /* XXX dev->ud_addr not necessarily unique on bus */ 2082 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2083 bus->ub_devices[dev->ud_addr] = dev; 2084 2085 err = usbd_get_initial_ddesc(dev, dd); 2086 if (err) 2087 goto bad; 2088 /* 4.8.2.1 */ 2089 if (speed == USB_SPEED_SUPER) { 2090 if (dd->bMaxPacketSize != 9) { 2091 printf("%s: invalid mps 2^%u for SS ep0," 2092 " using 512\n", 2093 device_xname(sc->sc_dev), 2094 dd->bMaxPacketSize); 2095 dd->bMaxPacketSize = 9; 2096 } 2097 USETW(dev->ud_ep0desc.wMaxPacketSize, 2098 (1 << dd->bMaxPacketSize)); 2099 } else 2100 USETW(dev->ud_ep0desc.wMaxPacketSize, 2101 dd->bMaxPacketSize); 2102 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2103 xhci_update_ep0_mps(sc, xs, 2104 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2105 err = usbd_reload_device_desc(dev); 2106 if (err) 2107 goto bad; 2108 2109 #if 0 2110 /* Re-establish the default pipe with the new MPS. */ 2111 /* In xhci this is done by xhci_update_ep0_mps. */ 2112 usbd_kill_pipe(dev->ud_pipe0); 2113 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2114 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2115 #endif 2116 } 2117 2118 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2119 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2120 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2121 dd->bDeviceClass, dd->bDeviceSubClass, 2122 dd->bDeviceProtocol, 0); 2123 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2124 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2125 dev->ud_speed); 2126 2127 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2128 2129 if ((depth == 0) && (port == 0)) { 2130 usbd_attach_roothub(parent, dev); 2131 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2132 return USBD_NORMAL_COMPLETION; 2133 } 2134 2135 2136 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2137 bad: 2138 if (err != USBD_NORMAL_COMPLETION) { 2139 usbd_remove_device(dev, up); 2140 } 2141 2142 return err; 2143 } 2144 2145 static usbd_status 2146 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2147 size_t ntrb, size_t align) 2148 { 2149 usbd_status err; 2150 size_t size = ntrb * XHCI_TRB_SIZE; 2151 2152 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2153 2154 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2155 if (err) 2156 return err; 2157 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2158 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2159 xr->xr_trb = xhci_ring_trbv(xr, 0); 2160 xr->xr_ntrb = ntrb; 2161 xr->xr_ep = 0; 2162 xr->xr_cs = 1; 2163 memset(xr->xr_trb, 0, size); 2164 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 2165 xr->is_halted = false; 2166 2167 return USBD_NORMAL_COMPLETION; 2168 } 2169 2170 static void 2171 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2172 { 2173 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2174 mutex_destroy(&xr->xr_lock); 2175 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2176 } 2177 2178 static void 2179 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2180 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2181 { 2182 size_t i; 2183 u_int ri; 2184 u_int cs; 2185 uint64_t parameter; 2186 uint32_t status; 2187 uint32_t control; 2188 2189 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2190 2191 for (i = 0; i < ntrbs; i++) { 2192 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2193 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2194 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2195 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2196 XHCI_TRB_TYPE_LINK); 2197 } 2198 2199 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2200 2201 ri = xr->xr_ep; 2202 cs = xr->xr_cs; 2203 2204 /* 2205 * Although the xhci hardware can do scatter/gather dma from 2206 * arbitrary sized buffers, there is a non-obvious restriction 2207 * that a LINK trb is only allowed at the end of a burst of 2208 * transfers - which might be 16kB. 2209 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2210 * The simple solution is not to allow a LINK trb in the middle 2211 * of anything - as here. 2212 * XXX: (dsl) There are xhci controllers out there (eg some made by 2213 * ASMedia) that seem to lock up if they process a LINK trb but 2214 * cannot process the linked-to trb yet. 2215 * The code should write the 'cycle' bit on the link trb AFTER 2216 * adding the other trb. 2217 */ 2218 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2219 parameter = xhci_ring_trbp(xr, 0); 2220 status = 0; 2221 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2222 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2223 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 2224 htole32(status), htole32(control)); 2225 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2226 BUS_DMASYNC_PREWRITE); 2227 xr->xr_cookies[ri] = NULL; 2228 xr->xr_ep = 0; 2229 xr->xr_cs ^= 1; 2230 ri = xr->xr_ep; 2231 cs = xr->xr_cs; 2232 } 2233 2234 ri++; 2235 2236 /* Write any subsequent TRB first */ 2237 for (i = 1; i < ntrbs; i++) { 2238 parameter = trbs[i].trb_0; 2239 status = trbs[i].trb_2; 2240 control = trbs[i].trb_3; 2241 2242 if (cs) { 2243 control |= XHCI_TRB_3_CYCLE_BIT; 2244 } else { 2245 control &= ~XHCI_TRB_3_CYCLE_BIT; 2246 } 2247 2248 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 2249 htole32(status), htole32(control)); 2250 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2251 BUS_DMASYNC_PREWRITE); 2252 xr->xr_cookies[ri] = cookie; 2253 ri++; 2254 } 2255 2256 /* Write the first TRB last */ 2257 i = 0; 2258 parameter = trbs[i].trb_0; 2259 status = trbs[i].trb_2; 2260 control = trbs[i].trb_3; 2261 2262 if (xr->xr_cs) { 2263 control |= XHCI_TRB_3_CYCLE_BIT; 2264 } else { 2265 control &= ~XHCI_TRB_3_CYCLE_BIT; 2266 } 2267 2268 xhci_trb_put(&xr->xr_trb[xr->xr_ep], htole64(parameter), 2269 htole32(status), htole32(control)); 2270 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2271 BUS_DMASYNC_PREWRITE); 2272 xr->xr_cookies[xr->xr_ep] = cookie; 2273 2274 xr->xr_ep = ri; 2275 xr->xr_cs = cs; 2276 2277 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2278 } 2279 2280 /* 2281 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2282 * Command completion is notified by cv_signal from xhci_handle_event 2283 * (called from interrupt from xHCI), or timed-out. 2284 * Command validation is performed in xhci_handle_event by checking if 2285 * trb_0 in CMD_COMPLETE TRB and sc->sc_command_addr are identical. 2286 */ 2287 static usbd_status 2288 xhci_do_command1(struct xhci_softc * const sc, struct xhci_trb * const trb, 2289 int timeout, int locked) 2290 { 2291 struct xhci_ring * const cr = &sc->sc_cr; 2292 usbd_status err; 2293 2294 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2295 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2296 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2297 2298 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2299 2300 if (!locked) 2301 mutex_enter(&sc->sc_lock); 2302 2303 /* XXX KASSERT may fire when cv_timedwait unlocks sc_lock */ 2304 KASSERT(sc->sc_command_addr == 0); 2305 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2306 2307 mutex_enter(&cr->xr_lock); 2308 xhci_ring_put(sc, cr, NULL, trb, 1); 2309 mutex_exit(&cr->xr_lock); 2310 2311 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2312 2313 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2314 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2315 err = USBD_TIMEOUT; 2316 goto timedout; 2317 } 2318 2319 trb->trb_0 = sc->sc_result_trb.trb_0; 2320 trb->trb_2 = sc->sc_result_trb.trb_2; 2321 trb->trb_3 = sc->sc_result_trb.trb_3; 2322 2323 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2324 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2325 2326 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2327 case XHCI_TRB_ERROR_SUCCESS: 2328 err = USBD_NORMAL_COMPLETION; 2329 break; 2330 default: 2331 case 192 ... 223: 2332 err = USBD_IOERROR; 2333 break; 2334 case 224 ... 255: 2335 err = USBD_NORMAL_COMPLETION; 2336 break; 2337 } 2338 2339 timedout: 2340 sc->sc_command_addr = 0; 2341 if (!locked) 2342 mutex_exit(&sc->sc_lock); 2343 return err; 2344 } 2345 2346 static usbd_status 2347 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2348 int timeout) 2349 { 2350 return xhci_do_command1(sc, trb, timeout, 0); 2351 } 2352 2353 /* 2354 * This allows xhci_do_command with already sc_lock held. 2355 * This is needed as USB stack calls close methods with sc_lock_held. 2356 * (see usbdivar.h) 2357 */ 2358 static usbd_status 2359 xhci_do_command_locked(struct xhci_softc * const sc, 2360 struct xhci_trb * const trb, int timeout) 2361 { 2362 return xhci_do_command1(sc, trb, timeout, 1); 2363 } 2364 2365 static usbd_status 2366 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2367 { 2368 struct xhci_trb trb; 2369 usbd_status err; 2370 2371 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2372 2373 trb.trb_0 = 0; 2374 trb.trb_2 = 0; 2375 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2376 2377 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2378 if (err != USBD_NORMAL_COMPLETION) { 2379 return err; 2380 } 2381 2382 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2383 2384 return err; 2385 } 2386 2387 /* 2388 * Deallocate DMA buffer and ring buffer, and disable_slot. 2389 * Should be called with sc_lock held. 2390 */ 2391 static usbd_status 2392 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2393 { 2394 struct xhci_trb trb; 2395 struct xhci_slot *xs; 2396 2397 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2398 2399 if (sc->sc_dying) 2400 return USBD_IOERROR; 2401 2402 xs = &sc->sc_slots[slot]; 2403 if (xs->xs_idx != 0) { 2404 for (int i = XHCI_DCI_SLOT + 1; i < 32; i++) { 2405 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2406 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2407 } 2408 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2409 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2410 } 2411 2412 trb.trb_0 = 0; 2413 trb.trb_2 = 0; 2414 trb.trb_3 = htole32( 2415 XHCI_TRB_3_SLOT_SET(slot) | 2416 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2417 2418 return xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2419 } 2420 2421 /* 2422 * Change slot state. 2423 * bsr=0: ENABLED -> ADDRESSED 2424 * bsr=1: ENABLED -> DEFAULT 2425 * see xHCI 1.1 4.5.3, 3.3.4 2426 */ 2427 static usbd_status 2428 xhci_address_device(struct xhci_softc * const sc, 2429 uint64_t icp, uint8_t slot_id, bool bsr) 2430 { 2431 struct xhci_trb trb; 2432 usbd_status err; 2433 2434 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2435 2436 trb.trb_0 = icp; 2437 trb.trb_2 = 0; 2438 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2439 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2440 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2441 2442 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2443 return err; 2444 } 2445 2446 static usbd_status 2447 xhci_update_ep0_mps(struct xhci_softc * const sc, 2448 struct xhci_slot * const xs, u_int mps) 2449 { 2450 struct xhci_trb trb; 2451 usbd_status err; 2452 uint32_t * cp; 2453 2454 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2455 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2456 2457 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2458 cp[0] = htole32(0); 2459 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2460 2461 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2462 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2463 2464 /* sync input contexts before they are read from memory */ 2465 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2466 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2467 sc->sc_ctxsz * 4); 2468 2469 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2470 trb.trb_2 = 0; 2471 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2472 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2473 2474 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2475 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2476 return err; 2477 } 2478 2479 static void 2480 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2481 { 2482 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2483 2484 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2485 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2486 &dcbaa[si], dcba, si, 0); 2487 2488 dcbaa[si] = htole64(dcba); 2489 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2490 BUS_DMASYNC_PREWRITE); 2491 } 2492 2493 /* 2494 * Allocate DMA buffer and ring buffer for specified slot 2495 * and set Device Context Base Address 2496 * and issue Set Address device command. 2497 */ 2498 static usbd_status 2499 xhci_init_slot(struct usbd_device *dev, uint32_t slot, int route, int rhport) 2500 { 2501 struct xhci_softc * const sc = dev->ud_bus->ub_hcpriv; 2502 struct xhci_slot *xs; 2503 usbd_status err; 2504 u_int dci; 2505 uint32_t *cp; 2506 uint32_t mps = UGETW(dev->ud_ep0desc.wMaxPacketSize); 2507 2508 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2509 DPRINTFN(4, "slot %u speed %d rhport %d route %05x", 2510 slot, dev->ud_speed, route, rhport); 2511 2512 xs = &sc->sc_slots[slot]; 2513 2514 /* allocate contexts */ 2515 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2516 &xs->xs_dc_dma); 2517 if (err) 2518 return err; 2519 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2520 2521 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2522 &xs->xs_ic_dma); 2523 if (err) 2524 goto bad1; 2525 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2526 2527 for (dci = 0; dci < 32; dci++) { 2528 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2529 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2530 if (dci == XHCI_DCI_SLOT) 2531 continue; 2532 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2533 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2534 if (err) { 2535 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2536 goto bad2; 2537 } 2538 } 2539 2540 /* set up initial input control context */ 2541 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2542 cp[0] = htole32(0); 2543 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 2544 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2545 2546 /* set up input slot context */ 2547 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2548 xhci_setup_sctx(dev, cp); 2549 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(1)); 2550 cp[0] |= htole32(XHCI_SCTX_0_ROUTE_SET(route)); 2551 cp[1] |= htole32(XHCI_SCTX_1_RH_PORT_SET(rhport)); 2552 2553 /* set up input EP0 context */ 2554 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2555 cp[0] = htole32(0); 2556 cp[1] = htole32( 2557 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 2558 XHCI_EPCTX_1_EPTYPE_SET(4) | 2559 XHCI_EPCTX_1_CERR_SET(3) 2560 ); 2561 /* can't use xhci_ep_get_dci() yet? */ 2562 *(uint64_t *)(&cp[2]) = htole64( 2563 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 2564 XHCI_EPCTX_2_DCS_SET(1)); 2565 cp[4] = htole32( 2566 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 2567 ); 2568 2569 /* sync input contexts before they are read from memory */ 2570 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2571 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2572 sc->sc_ctxsz * 3); 2573 2574 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2575 2576 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 2577 false); 2578 2579 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2580 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2581 sc->sc_ctxsz * 2); 2582 2583 bad2: 2584 if (err == USBD_NORMAL_COMPLETION) { 2585 xs->xs_idx = slot; 2586 } else { 2587 for (int i = 1; i < dci; i++) { 2588 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2589 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2590 } 2591 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2592 bad1: 2593 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2594 xs->xs_idx = 0; 2595 } 2596 2597 return err; 2598 } 2599 2600 /* ----- */ 2601 2602 static void 2603 xhci_noop(struct usbd_pipe *pipe) 2604 { 2605 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2606 } 2607 2608 /* 2609 * Process root hub request. 2610 */ 2611 static int 2612 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2613 void *buf, int buflen) 2614 { 2615 struct xhci_softc * const sc = bus->ub_hcpriv; 2616 usb_port_status_t ps; 2617 int l, totlen = 0; 2618 uint16_t len, value, index; 2619 int port, i; 2620 uint32_t v; 2621 2622 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2623 2624 if (sc->sc_dying) 2625 return -1; 2626 2627 len = UGETW(req->wLength); 2628 value = UGETW(req->wValue); 2629 index = UGETW(req->wIndex); 2630 2631 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 2632 req->bmRequestType | (req->bRequest << 8), value, index, len); 2633 2634 #define C(x,y) ((x) | ((y) << 8)) 2635 switch (C(req->bRequest, req->bmRequestType)) { 2636 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2637 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 2638 if (len == 0) 2639 break; 2640 switch (value) { 2641 #define sd ((usb_string_descriptor_t *)buf) 2642 case C(2, UDESC_STRING): 2643 /* Product */ 2644 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 2645 break; 2646 #undef sd 2647 default: 2648 /* default from usbroothub */ 2649 return buflen; 2650 } 2651 break; 2652 2653 /* Hub requests */ 2654 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2655 break; 2656 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2657 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2658 index, value, 0, 0); 2659 if (index < 1 || index > sc->sc_maxports) { 2660 return -1; 2661 } 2662 port = XHCI_PORTSC(index); 2663 v = xhci_op_read_4(sc, port); 2664 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2665 v &= ~XHCI_PS_CLEAR; 2666 switch (value) { 2667 case UHF_PORT_ENABLE: 2668 xhci_op_write_4(sc, port, v &~ XHCI_PS_PED); 2669 break; 2670 case UHF_PORT_SUSPEND: 2671 return -1; 2672 case UHF_PORT_POWER: 2673 break; 2674 case UHF_PORT_TEST: 2675 case UHF_PORT_INDICATOR: 2676 return -1; 2677 case UHF_C_PORT_CONNECTION: 2678 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2679 break; 2680 case UHF_C_PORT_ENABLE: 2681 case UHF_C_PORT_SUSPEND: 2682 case UHF_C_PORT_OVER_CURRENT: 2683 return -1; 2684 case UHF_C_BH_PORT_RESET: 2685 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 2686 break; 2687 case UHF_C_PORT_RESET: 2688 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2689 break; 2690 case UHF_C_PORT_LINK_STATE: 2691 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 2692 break; 2693 case UHF_C_PORT_CONFIG_ERROR: 2694 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 2695 break; 2696 default: 2697 return -1; 2698 } 2699 break; 2700 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2701 if (len == 0) 2702 break; 2703 if ((value & 0xff) != 0) { 2704 return -1; 2705 } 2706 usb_hub_descriptor_t hubd; 2707 2708 totlen = min(buflen, sizeof(hubd)); 2709 memcpy(&hubd, buf, totlen); 2710 hubd.bNbrPorts = sc->sc_maxports; 2711 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2712 hubd.bPwrOn2PwrGood = 200; 2713 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 2714 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2715 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2716 totlen = min(totlen, hubd.bDescLength); 2717 memcpy(buf, &hubd, totlen); 2718 break; 2719 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2720 if (len != 4) { 2721 return -1; 2722 } 2723 memset(buf, 0, len); /* ? XXX */ 2724 totlen = len; 2725 break; 2726 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2727 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2728 if (index < 1 || index > sc->sc_maxports) { 2729 return -1; 2730 } 2731 if (len != 4) { 2732 return -1; 2733 } 2734 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 2735 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 2736 switch (XHCI_PS_SPEED_GET(v)) { 2737 case 1: 2738 i = UPS_FULL_SPEED; 2739 break; 2740 case 2: 2741 i = UPS_LOW_SPEED; 2742 break; 2743 case 3: 2744 i = UPS_HIGH_SPEED; 2745 break; 2746 case 4: 2747 i = UPS_SUPER_SPEED; 2748 break; 2749 default: 2750 i = 0; 2751 break; 2752 } 2753 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2754 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2755 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2756 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 2757 if (v & XHCI_PS_PR) i |= UPS_RESET; 2758 if (v & XHCI_PS_PP) { 2759 if (i & UPS_SUPER_SPEED) 2760 i |= UPS_PORT_POWER_SS; 2761 else 2762 i |= UPS_PORT_POWER; 2763 } 2764 USETW(ps.wPortStatus, i); 2765 i = 0; 2766 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2767 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2768 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2769 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2770 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 2771 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 2772 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 2773 USETW(ps.wPortChange, i); 2774 totlen = min(len, sizeof(ps)); 2775 memcpy(buf, &ps, totlen); 2776 break; 2777 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2778 return -1; 2779 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 2780 break; 2781 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2782 break; 2783 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 2784 int optval = (index >> 8) & 0xff; 2785 index &= 0xff; 2786 if (index < 1 || index > sc->sc_maxports) { 2787 return -1; 2788 } 2789 port = XHCI_PORTSC(index); 2790 v = xhci_op_read_4(sc, port); 2791 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2792 v &= ~XHCI_PS_CLEAR; 2793 switch (value) { 2794 case UHF_PORT_ENABLE: 2795 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 2796 break; 2797 case UHF_PORT_SUSPEND: 2798 /* XXX suspend */ 2799 break; 2800 case UHF_PORT_RESET: 2801 v &= ~ (XHCI_PS_PED | XHCI_PS_PR); 2802 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 2803 /* Wait for reset to complete. */ 2804 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2805 if (sc->sc_dying) { 2806 return -1; 2807 } 2808 v = xhci_op_read_4(sc, port); 2809 if (v & XHCI_PS_PR) { 2810 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 2811 usb_delay_ms(&sc->sc_bus, 10); 2812 /* XXX */ 2813 } 2814 break; 2815 case UHF_PORT_POWER: 2816 /* XXX power control */ 2817 break; 2818 /* XXX more */ 2819 case UHF_C_PORT_RESET: 2820 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2821 break; 2822 case UHF_PORT_U1_TIMEOUT: 2823 if (XHCI_PS_SPEED_GET(v) != 4) { 2824 return -1; 2825 } 2826 port = XHCI_PORTPMSC(index); 2827 v = xhci_op_read_4(sc, port); 2828 v &= ~XHCI_PM3_U1TO_SET(0xff); 2829 v |= XHCI_PM3_U1TO_SET(optval); 2830 xhci_op_write_4(sc, port, v); 2831 break; 2832 case UHF_PORT_U2_TIMEOUT: 2833 if (XHCI_PS_SPEED_GET(v) != 4) { 2834 return -1; 2835 } 2836 port = XHCI_PORTPMSC(index); 2837 v = xhci_op_read_4(sc, port); 2838 v &= ~XHCI_PM3_U2TO_SET(0xff); 2839 v |= XHCI_PM3_U2TO_SET(optval); 2840 xhci_op_write_4(sc, port, v); 2841 break; 2842 default: 2843 return -1; 2844 } 2845 } 2846 break; 2847 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2848 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2849 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2850 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2851 break; 2852 default: 2853 /* default from usbroothub */ 2854 return buflen; 2855 } 2856 2857 return totlen; 2858 } 2859 2860 /* root hub interrupt */ 2861 2862 static usbd_status 2863 xhci_root_intr_transfer(struct usbd_xfer *xfer) 2864 { 2865 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2866 usbd_status err; 2867 2868 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2869 2870 /* Insert last in queue. */ 2871 mutex_enter(&sc->sc_lock); 2872 err = usb_insert_transfer(xfer); 2873 mutex_exit(&sc->sc_lock); 2874 if (err) 2875 return err; 2876 2877 /* Pipe isn't running, start first */ 2878 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2879 } 2880 2881 /* Wait for roothub port status/change */ 2882 static usbd_status 2883 xhci_root_intr_start(struct usbd_xfer *xfer) 2884 { 2885 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2886 2887 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2888 2889 if (sc->sc_dying) 2890 return USBD_IOERROR; 2891 2892 mutex_enter(&sc->sc_lock); 2893 sc->sc_intrxfer = xfer; 2894 mutex_exit(&sc->sc_lock); 2895 2896 return USBD_IN_PROGRESS; 2897 } 2898 2899 static void 2900 xhci_root_intr_abort(struct usbd_xfer *xfer) 2901 { 2902 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2903 2904 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2905 2906 KASSERT(mutex_owned(&sc->sc_lock)); 2907 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2908 2909 sc->sc_intrxfer = NULL; 2910 2911 xfer->ux_status = USBD_CANCELLED; 2912 usb_transfer_complete(xfer); 2913 } 2914 2915 static void 2916 xhci_root_intr_close(struct usbd_pipe *pipe) 2917 { 2918 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 2919 2920 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2921 2922 KASSERT(mutex_owned(&sc->sc_lock)); 2923 2924 sc->sc_intrxfer = NULL; 2925 } 2926 2927 static void 2928 xhci_root_intr_done(struct usbd_xfer *xfer) 2929 { 2930 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2931 2932 xfer->ux_hcpriv = NULL; 2933 } 2934 2935 /* -------------- */ 2936 /* device control */ 2937 2938 static usbd_status 2939 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2940 { 2941 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2942 usbd_status err; 2943 2944 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2945 2946 /* Insert last in queue. */ 2947 mutex_enter(&sc->sc_lock); 2948 err = usb_insert_transfer(xfer); 2949 mutex_exit(&sc->sc_lock); 2950 if (err) 2951 return err; 2952 2953 /* Pipe isn't running, start first */ 2954 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2955 } 2956 2957 static usbd_status 2958 xhci_device_ctrl_start(struct usbd_xfer *xfer) 2959 { 2960 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2961 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 2962 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 2963 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2964 struct xhci_xfer * const xx = (void *)xfer; 2965 usb_device_request_t * const req = &xfer->ux_request; 2966 const bool isread = UT_GET_DIR(req->bmRequestType) == UT_READ; 2967 const uint32_t len = UGETW(req->wLength); 2968 usb_dma_t * const dma = &xfer->ux_dmabuf; 2969 uint64_t parameter; 2970 uint32_t status; 2971 uint32_t control; 2972 u_int i; 2973 2974 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2975 DPRINTFN(12, "req: %04x %04x %04x %04x", 2976 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 2977 UGETW(req->wIndex), UGETW(req->wLength)); 2978 2979 /* XXX */ 2980 if (tr->is_halted) { 2981 DPRINTFN(1, "ctrl xfer %p halted: slot %u dci %u", 2982 xfer, xs->xs_idx, dci, 0); 2983 xhci_reset_endpoint(xfer->ux_pipe); 2984 tr->is_halted = false; 2985 xhci_set_dequeue(xfer->ux_pipe); 2986 } 2987 2988 /* we rely on the bottom bits for extra info */ 2989 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 2990 2991 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 2992 2993 i = 0; 2994 2995 /* setup phase */ 2996 memcpy(¶meter, req, sizeof(*req)); 2997 parameter = le64toh(parameter); 2998 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 2999 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3000 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3001 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3002 XHCI_TRB_3_IDT_BIT; 3003 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3004 3005 if (len == 0) 3006 goto no_data; 3007 3008 /* data phase */ 3009 parameter = DMAADDR(dma, 0); 3010 KASSERT(len <= 0x10000); 3011 status = XHCI_TRB_2_IRQ_SET(0) | 3012 XHCI_TRB_2_TDSZ_SET(1) | 3013 XHCI_TRB_2_BYTES_SET(len); 3014 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3015 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3016 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3017 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3018 3019 parameter = (uintptr_t)xfer | 0x3; 3020 status = XHCI_TRB_2_IRQ_SET(0); 3021 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3022 XHCI_TRB_3_IOC_BIT; 3023 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3024 3025 no_data: 3026 parameter = 0; 3027 status = XHCI_TRB_2_IRQ_SET(0); 3028 /* the status stage has inverted direction */ 3029 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3030 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3031 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3032 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3033 3034 parameter = (uintptr_t)xfer | 0x0; 3035 status = XHCI_TRB_2_IRQ_SET(0); 3036 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3037 XHCI_TRB_3_IOC_BIT; 3038 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3039 3040 mutex_enter(&tr->xr_lock); 3041 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3042 mutex_exit(&tr->xr_lock); 3043 3044 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3045 3046 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3047 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3048 xhci_timeout, xfer); 3049 } 3050 3051 if (sc->sc_bus.ub_usepolling) { 3052 DPRINTFN(1, "polling", 0, 0, 0, 0); 3053 //xhci_waitintr(sc, xfer); 3054 } 3055 3056 return USBD_IN_PROGRESS; 3057 } 3058 3059 static void 3060 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3061 { 3062 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3063 3064 callout_stop(&xfer->ux_callout); /* XXX wrong place */ 3065 3066 } 3067 3068 static void 3069 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3070 { 3071 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3072 3073 xhci_abort_xfer(xfer, USBD_CANCELLED); 3074 } 3075 3076 static void 3077 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3078 { 3079 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3080 3081 (void)xhci_close_pipe(pipe); 3082 } 3083 3084 /* ------------------ */ 3085 /* device isochronous */ 3086 3087 /* ----------- */ 3088 /* device bulk */ 3089 3090 static usbd_status 3091 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3092 { 3093 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3094 usbd_status err; 3095 3096 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3097 3098 /* Insert last in queue. */ 3099 mutex_enter(&sc->sc_lock); 3100 err = usb_insert_transfer(xfer); 3101 mutex_exit(&sc->sc_lock); 3102 if (err) 3103 return err; 3104 3105 /* 3106 * Pipe isn't running (otherwise err would be USBD_INPROG), 3107 * so start it first. 3108 */ 3109 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3110 } 3111 3112 static usbd_status 3113 xhci_device_bulk_start(struct usbd_xfer *xfer) 3114 { 3115 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3116 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3117 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3118 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3119 struct xhci_xfer * const xx = (void *)xfer; 3120 const uint32_t len = xfer->ux_length; 3121 usb_dma_t * const dma = &xfer->ux_dmabuf; 3122 uint64_t parameter; 3123 uint32_t status; 3124 uint32_t control; 3125 u_int i = 0; 3126 3127 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3128 3129 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3130 3131 if (sc->sc_dying) 3132 return USBD_IOERROR; 3133 3134 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3135 3136 parameter = DMAADDR(dma, 0); 3137 /* 3138 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3139 * If the user supplied buffer crosses such a boundary then 2 3140 * (or more) TRB should be used. 3141 * If multiple TRB are used the td_size field must be set correctly. 3142 * For v1.0 devices (like ivy bridge) this is the number of usb data 3143 * blocks needed to complete the transfer. 3144 * Setting it to 1 in the last TRB causes an extra zero-length 3145 * data block be sent. 3146 * The earlier documentation differs, I don't know how it behaves. 3147 */ 3148 KASSERT(len <= 0x10000); 3149 status = XHCI_TRB_2_IRQ_SET(0) | 3150 XHCI_TRB_2_TDSZ_SET(1) | 3151 XHCI_TRB_2_BYTES_SET(len); 3152 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3153 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3154 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3155 3156 mutex_enter(&tr->xr_lock); 3157 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3158 mutex_exit(&tr->xr_lock); 3159 3160 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3161 3162 if (sc->sc_bus.ub_usepolling) { 3163 DPRINTFN(1, "polling", 0, 0, 0, 0); 3164 //xhci_waitintr(sc, xfer); 3165 } 3166 3167 return USBD_IN_PROGRESS; 3168 } 3169 3170 static void 3171 xhci_device_bulk_done(struct usbd_xfer *xfer) 3172 { 3173 #ifdef USB_DEBUG 3174 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3175 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3176 #endif 3177 const u_int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3178 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3179 3180 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3181 3182 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3183 3184 callout_stop(&xfer->ux_callout); /* XXX wrong place */ 3185 3186 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3187 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3188 } 3189 3190 static void 3191 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3192 { 3193 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3194 3195 xhci_abort_xfer(xfer, USBD_CANCELLED); 3196 } 3197 3198 static void 3199 xhci_device_bulk_close(struct usbd_pipe *pipe) 3200 { 3201 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3202 3203 (void)xhci_close_pipe(pipe); 3204 } 3205 3206 /* ---------------- */ 3207 /* device interrupt */ 3208 3209 static usbd_status 3210 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3211 { 3212 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3213 usbd_status err; 3214 3215 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3216 3217 /* Insert last in queue. */ 3218 mutex_enter(&sc->sc_lock); 3219 err = usb_insert_transfer(xfer); 3220 mutex_exit(&sc->sc_lock); 3221 if (err) 3222 return err; 3223 3224 /* 3225 * Pipe isn't running (otherwise err would be USBD_INPROG), 3226 * so start it first. 3227 */ 3228 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3229 } 3230 3231 static usbd_status 3232 xhci_device_intr_start(struct usbd_xfer *xfer) 3233 { 3234 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3235 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3236 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3237 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3238 struct xhci_xfer * const xx = (void *)xfer; 3239 const uint32_t len = xfer->ux_length; 3240 usb_dma_t * const dma = &xfer->ux_dmabuf; 3241 uint64_t parameter; 3242 uint32_t status; 3243 uint32_t control; 3244 u_int i = 0; 3245 3246 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3247 3248 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3249 3250 if (sc->sc_dying) 3251 return USBD_IOERROR; 3252 3253 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3254 3255 parameter = DMAADDR(dma, 0); 3256 KASSERT(len <= 0x10000); 3257 status = XHCI_TRB_2_IRQ_SET(0) | 3258 XHCI_TRB_2_TDSZ_SET(1) | 3259 XHCI_TRB_2_BYTES_SET(len); 3260 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3261 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3262 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3263 3264 mutex_enter(&tr->xr_lock); 3265 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3266 mutex_exit(&tr->xr_lock); 3267 3268 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3269 3270 if (sc->sc_bus.ub_usepolling) { 3271 DPRINTFN(1, "polling", 0, 0, 0, 0); 3272 //xhci_waitintr(sc, xfer); 3273 } 3274 3275 return USBD_IN_PROGRESS; 3276 } 3277 3278 static void 3279 xhci_device_intr_done(struct usbd_xfer *xfer) 3280 { 3281 struct xhci_softc * const sc __diagused = 3282 xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3283 #ifdef USB_DEBUG 3284 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3285 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3286 #endif 3287 const u_int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3288 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3289 3290 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3291 3292 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3293 3294 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3295 3296 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3297 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3298 3299 #if 0 3300 device_printf(sc->sc_dev, ""); 3301 for (size_t i = 0; i < xfer->ux_length; i++) { 3302 printf(" %02x", ((uint8_t const *)xfer->ux_buffer)[i]); 3303 } 3304 printf("\n"); 3305 #endif 3306 3307 if (xfer->ux_pipe->up_repeat) { 3308 xfer->ux_status = xhci_device_intr_start(xfer); 3309 } else { 3310 callout_stop(&xfer->ux_callout); /* XXX */ 3311 } 3312 3313 } 3314 3315 static void 3316 xhci_device_intr_abort(struct usbd_xfer *xfer) 3317 { 3318 struct xhci_softc * const sc __diagused = 3319 xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3320 3321 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3322 3323 KASSERT(mutex_owned(&sc->sc_lock)); 3324 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3325 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3326 xhci_abort_xfer(xfer, USBD_CANCELLED); 3327 } 3328 3329 static void 3330 xhci_device_intr_close(struct usbd_pipe *pipe) 3331 { 3332 //struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 3333 3334 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3335 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3336 3337 (void)xhci_close_pipe(pipe); 3338 } 3339 3340 /* ------------ */ 3341 3342 static void 3343 xhci_timeout(void *addr) 3344 { 3345 struct xhci_xfer * const xx = addr; 3346 struct usbd_xfer * const xfer = &xx->xx_xfer; 3347 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3348 3349 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3350 3351 if (sc->sc_dying) { 3352 return; 3353 } 3354 3355 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 3356 USB_TASKQ_MPSAFE); 3357 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 3358 USB_TASKQ_HC); 3359 } 3360 3361 static void 3362 xhci_timeout_task(void *addr) 3363 { 3364 struct usbd_xfer * const xfer = addr; 3365 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3366 3367 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3368 3369 mutex_enter(&sc->sc_lock); 3370 #if 0 3371 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3372 #else 3373 xfer->ux_status = USBD_TIMEOUT; 3374 usb_transfer_complete(xfer); 3375 #endif 3376 mutex_exit(&sc->sc_lock); 3377 } 3378
Indexes created Wed Oct 01 18:09:54 GMT 2025