xhci.c revision 1.28.2.23
1 /* $NetBSD: xhci.c,v 1.28.2.23 2015/05/27 07:03:18 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 3.1 specification 31 * http://www.usb.org/developers/docs/usb_31_040315.zip 32 * USB rev 2.0 specification 33 * http://www.usb.org/developers/docs/usb20_docs/usb_20_031815.zip 34 * xHCI rev 1.1 specification 35 * http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.28.2.23 2015/05/27 07:03:18 skrll Exp $"); 40 41 #include "opt_usb.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static int xhci_intr1(struct xhci_softc * const); 129 static void xhci_softintr(void *); 130 static void xhci_poll(struct usbd_bus *); 131 static struct usbd_xfer *xhci_allocx(struct usbd_bus *); 132 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 133 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 134 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 135 struct usbd_port *); 136 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 137 void *, int); 138 139 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 140 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 141 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 143 144 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 145 146 static usbd_status xhci_do_command(struct xhci_softc * const, 147 struct xhci_trb * const, int); 148 static usbd_status xhci_do_command1(struct xhci_softc * const, 149 struct xhci_trb * const, int, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t, int, int); 153 static usbd_status xhci_enable_slot(struct xhci_softc * const, 154 uint8_t * const); 155 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 156 static usbd_status xhci_address_device(struct xhci_softc * const, 157 uint64_t, uint8_t, bool); 158 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 159 struct xhci_slot * const, u_int); 160 static usbd_status xhci_ring_init(struct xhci_softc * const, 161 struct xhci_ring * const, size_t, size_t); 162 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 163 164 static void xhci_noop(struct usbd_pipe *); 165 166 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 167 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 168 static void xhci_root_intr_abort(struct usbd_xfer *); 169 static void xhci_root_intr_close(struct usbd_pipe *); 170 static void xhci_root_intr_done(struct usbd_xfer *); 171 172 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 173 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 174 static void xhci_device_ctrl_abort(struct usbd_xfer *); 175 static void xhci_device_ctrl_close(struct usbd_pipe *); 176 static void xhci_device_ctrl_done(struct usbd_xfer *); 177 178 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 179 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 180 static void xhci_device_intr_abort(struct usbd_xfer *); 181 static void xhci_device_intr_close(struct usbd_pipe *); 182 static void xhci_device_intr_done(struct usbd_xfer *); 183 184 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 185 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 186 static void xhci_device_bulk_abort(struct usbd_xfer *); 187 static void xhci_device_bulk_close(struct usbd_pipe *); 188 static void xhci_device_bulk_done(struct usbd_xfer *); 189 190 static void xhci_timeout(void *); 191 static void xhci_timeout_task(void *); 192 193 static const struct usbd_bus_methods xhci_bus_methods = { 194 .ubm_open = xhci_open, 195 .ubm_softint = xhci_softintr, 196 .ubm_dopoll = xhci_poll, 197 .ubm_allocx = xhci_allocx, 198 .ubm_freex = xhci_freex, 199 .ubm_getlock = xhci_get_lock, 200 .ubm_newdev = xhci_new_device, 201 .ubm_rhctrl = xhci_roothub_ctrl, 202 }; 203 204 static const struct usbd_pipe_methods xhci_root_intr_methods = { 205 .upm_transfer = xhci_root_intr_transfer, 206 .upm_start = xhci_root_intr_start, 207 .upm_abort = xhci_root_intr_abort, 208 .upm_close = xhci_root_intr_close, 209 .upm_cleartoggle = xhci_noop, 210 .upm_done = xhci_root_intr_done, 211 }; 212 213 214 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 215 .upm_transfer = xhci_device_ctrl_transfer, 216 .upm_start = xhci_device_ctrl_start, 217 .upm_abort = xhci_device_ctrl_abort, 218 .upm_close = xhci_device_ctrl_close, 219 .upm_cleartoggle = xhci_noop, 220 .upm_done = xhci_device_ctrl_done, 221 }; 222 223 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 224 .upm_cleartoggle = xhci_noop, 225 }; 226 227 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 228 .upm_transfer = xhci_device_bulk_transfer, 229 .upm_start = xhci_device_bulk_start, 230 .upm_abort = xhci_device_bulk_abort, 231 .upm_close = xhci_device_bulk_close, 232 .upm_cleartoggle = xhci_noop, 233 .upm_done = xhci_device_bulk_done, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_intr_methods = { 237 .upm_transfer = xhci_device_intr_transfer, 238 .upm_start = xhci_device_intr_start, 239 .upm_abort = xhci_device_intr_abort, 240 .upm_close = xhci_device_intr_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_intr_done, 243 }; 244 245 static inline uint32_t 246 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 247 { 248 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 249 } 250 251 static inline uint32_t 252 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 253 { 254 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 255 } 256 257 static inline void 258 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 259 uint32_t value) 260 { 261 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 262 } 263 264 #if 0 /* unused */ 265 static inline void 266 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 267 uint32_t value) 268 { 269 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 270 } 271 #endif /* unused */ 272 273 static inline uint32_t 274 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 275 { 276 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 277 } 278 279 static inline uint32_t 280 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 281 { 282 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 283 } 284 285 static inline void 286 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 287 uint32_t value) 288 { 289 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 290 } 291 292 #if 0 /* unused */ 293 static inline uint64_t 294 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 295 { 296 uint64_t value; 297 298 if (sc->sc_ac64) { 299 #ifdef XHCI_USE_BUS_SPACE_8 300 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 301 #else 302 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 303 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 304 offset + 4) << 32; 305 #endif 306 } else { 307 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 308 } 309 310 return value; 311 } 312 #endif /* unused */ 313 314 static inline void 315 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 316 uint64_t value) 317 { 318 if (sc->sc_ac64) { 319 #ifdef XHCI_USE_BUS_SPACE_8 320 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 321 #else 322 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 323 (value >> 0) & 0xffffffff); 324 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 325 (value >> 32) & 0xffffffff); 326 #endif 327 } else { 328 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 329 } 330 } 331 332 static inline uint32_t 333 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 334 { 335 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 336 } 337 338 static inline void 339 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 340 uint32_t value) 341 { 342 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 343 } 344 345 #if 0 /* unused */ 346 static inline uint64_t 347 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 348 { 349 uint64_t value; 350 351 if (sc->sc_ac64) { 352 #ifdef XHCI_USE_BUS_SPACE_8 353 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 354 #else 355 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 356 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 357 offset + 4) << 32; 358 #endif 359 } else { 360 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 361 } 362 363 return value; 364 } 365 #endif /* unused */ 366 367 static inline void 368 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 369 uint64_t value) 370 { 371 if (sc->sc_ac64) { 372 #ifdef XHCI_USE_BUS_SPACE_8 373 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 374 #else 375 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 376 (value >> 0) & 0xffffffff); 377 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 378 (value >> 32) & 0xffffffff); 379 #endif 380 } else { 381 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 382 } 383 } 384 385 #if 0 /* unused */ 386 static inline uint32_t 387 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 388 { 389 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 390 } 391 #endif /* unused */ 392 393 static inline void 394 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 395 uint32_t value) 396 { 397 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 398 } 399 400 /* --- */ 401 402 static inline uint8_t 403 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 404 { 405 u_int eptype = 0; 406 407 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 408 case UE_CONTROL: 409 eptype = 0x0; 410 break; 411 case UE_ISOCHRONOUS: 412 eptype = 0x1; 413 break; 414 case UE_BULK: 415 eptype = 0x2; 416 break; 417 case UE_INTERRUPT: 418 eptype = 0x3; 419 break; 420 } 421 422 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 423 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 424 return eptype | 0x4; 425 else 426 return eptype; 427 } 428 429 static u_int 430 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 431 { 432 /* xHCI 1.0 section 4.5.1 */ 433 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 434 u_int in = 0; 435 436 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 437 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 438 in = 1; 439 440 return epaddr * 2 + in; 441 } 442 443 static inline u_int 444 xhci_dci_to_ici(const u_int i) 445 { 446 return i + 1; 447 } 448 449 static inline void * 450 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 451 const u_int dci) 452 { 453 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 454 } 455 456 #if 0 /* unused */ 457 static inline bus_addr_t 458 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 459 const u_int dci) 460 { 461 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 462 } 463 #endif /* unused */ 464 465 static inline void * 466 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 467 const u_int ici) 468 { 469 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 470 } 471 472 static inline bus_addr_t 473 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline struct xhci_trb * 480 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 481 { 482 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 483 } 484 485 static inline bus_addr_t 486 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 487 { 488 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 489 } 490 491 static inline void 492 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 493 uint32_t control) 494 { 495 trb->trb_0 = parameter; 496 trb->trb_2 = status; 497 trb->trb_3 = control; 498 } 499 500 /* --- */ 501 502 void 503 xhci_childdet(device_t self, device_t child) 504 { 505 struct xhci_softc * const sc = device_private(self); 506 507 KASSERT(sc->sc_child == child); 508 if (child == sc->sc_child) 509 sc->sc_child = NULL; 510 } 511 512 int 513 xhci_detach(struct xhci_softc *sc, int flags) 514 { 515 int rv = 0; 516 517 if (sc->sc_child != NULL) 518 rv = config_detach(sc->sc_child, flags); 519 520 if (rv != 0) 521 return rv; 522 523 /* XXX unconfigure/free slots */ 524 525 /* verify: */ 526 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 527 xhci_op_write_4(sc, XHCI_USBCMD, 0); 528 /* do we need to wait for stop? */ 529 530 xhci_op_write_8(sc, XHCI_CRCR, 0); 531 xhci_ring_free(sc, &sc->sc_cr); 532 cv_destroy(&sc->sc_command_cv); 533 534 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 535 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 536 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 537 xhci_ring_free(sc, &sc->sc_er); 538 539 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 540 541 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 542 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 543 544 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 545 546 mutex_destroy(&sc->sc_lock); 547 mutex_destroy(&sc->sc_intr_lock); 548 cv_destroy(&sc->sc_softwake_cv); 549 550 pool_cache_destroy(sc->sc_xferpool); 551 552 return rv; 553 } 554 555 int 556 xhci_activate(device_t self, enum devact act) 557 { 558 struct xhci_softc * const sc = device_private(self); 559 560 switch (act) { 561 case DVACT_DEACTIVATE: 562 sc->sc_dying = true; 563 return 0; 564 default: 565 return EOPNOTSUPP; 566 } 567 } 568 569 bool 570 xhci_suspend(device_t dv, const pmf_qual_t *qual) 571 { 572 return false; 573 } 574 575 bool 576 xhci_resume(device_t dv, const pmf_qual_t *qual) 577 { 578 return false; 579 } 580 581 bool 582 xhci_shutdown(device_t self, int flags) 583 { 584 return false; 585 } 586 587 588 static void 589 hexdump(const char *msg, const void *base, size_t len) 590 { 591 #if 0 592 size_t cnt; 593 const uint32_t *p; 594 extern paddr_t vtophys(vaddr_t); 595 596 p = base; 597 cnt = 0; 598 599 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 600 (void *)vtophys((vaddr_t)base)); 601 602 while (cnt < len) { 603 if (cnt % 16 == 0) 604 printf("%p: ", p); 605 else if (cnt % 8 == 0) 606 printf(" |"); 607 printf(" %08x", *p++); 608 cnt += 4; 609 if (cnt % 16 == 0) 610 printf("\n"); 611 } 612 #endif 613 } 614 615 616 int 617 xhci_init(struct xhci_softc *sc) 618 { 619 bus_size_t bsz; 620 uint32_t cap, hcs1, hcs2, hcc, dboff, rtsoff; 621 uint32_t ecp, ecr; 622 uint32_t usbcmd, usbsts, pagesize, config; 623 int i; 624 uint16_t hciversion; 625 uint8_t caplength; 626 627 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 628 629 /* XXX Low/Full/High speeds for now */ 630 sc->sc_bus.ub_revision = USBREV_2_0; 631 sc->sc_bus.ub_usedma = true; 632 633 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 634 caplength = XHCI_CAP_CAPLENGTH(cap); 635 hciversion = XHCI_CAP_HCIVERSION(cap); 636 637 if ((hciversion < 0x0096) || (hciversion > 0x0100)) { 638 aprint_normal_dev(sc->sc_dev, 639 "xHCI version %x.%x not known to be supported\n", 640 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 641 } else { 642 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 643 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 644 } 645 646 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 647 &sc->sc_cbh) != 0) { 648 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 649 return ENOMEM; 650 } 651 652 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 653 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 654 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 655 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 656 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 657 (void)xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 658 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 659 660 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 661 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 662 aprint_debug_dev(sc->sc_dev, "ac64 %d ctxsz %d\n", sc->sc_ac64, 663 sc->sc_ctxsz); 664 665 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 666 ecp = XHCI_HCC_XECP(hcc) * 4; 667 while (ecp != 0) { 668 ecr = xhci_read_4(sc, ecp); 669 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 670 switch (XHCI_XECP_ID(ecr)) { 671 case XHCI_ID_PROTOCOLS: { 672 uint32_t w0, w4, w8; 673 uint16_t w2; 674 w0 = xhci_read_4(sc, ecp + 0); 675 w2 = (w0 >> 16) & 0xffff; 676 w4 = xhci_read_4(sc, ecp + 4); 677 w8 = xhci_read_4(sc, ecp + 8); 678 aprint_debug_dev(sc->sc_dev, "SP: %08x %08x %08x\n", 679 w0, w4, w8); 680 if (w4 == 0x20425355 && w2 == 0x0300) { 681 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 682 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 683 } 684 if (w4 == 0x20425355 && w2 == 0x0200) { 685 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 686 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 687 } 688 break; 689 } 690 case XHCI_ID_USB_LEGACY: { 691 uint8_t bios_sem; 692 693 /* Take host controller from BIOS */ 694 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 695 if (bios_sem) { 696 /* sets xHCI to be owned by OS */ 697 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 698 aprint_debug( 699 "waiting for BIOS to give up control\n"); 700 for (i = 0; i < 5000; i++) { 701 bios_sem = xhci_read_1(sc, ecp + 702 XHCI_XECP_BIOS_SEM); 703 if (bios_sem == 0) 704 break; 705 DELAY(1000); 706 } 707 if (bios_sem) 708 printf("timed out waiting for BIOS\n"); 709 } 710 break; 711 } 712 default: 713 break; 714 } 715 ecr = xhci_read_4(sc, ecp); 716 if (XHCI_XECP_NEXT(ecr) == 0) { 717 ecp = 0; 718 } else { 719 ecp += XHCI_XECP_NEXT(ecr) * 4; 720 } 721 } 722 723 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 724 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 725 &sc->sc_obh) != 0) { 726 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 727 return ENOMEM; 728 } 729 730 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 731 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 732 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 733 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 734 return ENOMEM; 735 } 736 737 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 738 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 739 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 740 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 741 return ENOMEM; 742 } 743 744 for (i = 0; i < 100; i++) { 745 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 746 if ((usbsts & XHCI_STS_CNR) == 0) 747 break; 748 usb_delay_ms(&sc->sc_bus, 1); 749 } 750 if (i >= 100) 751 return EIO; 752 753 usbcmd = 0; 754 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 755 usb_delay_ms(&sc->sc_bus, 1); 756 757 usbcmd = XHCI_CMD_HCRST; 758 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 759 for (i = 0; i < 100; i++) { 760 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 761 if ((usbcmd & XHCI_CMD_HCRST) == 0) 762 break; 763 usb_delay_ms(&sc->sc_bus, 1); 764 } 765 if (i >= 100) 766 return EIO; 767 768 for (i = 0; i < 100; i++) { 769 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 770 if ((usbsts & XHCI_STS_CNR) == 0) 771 break; 772 usb_delay_ms(&sc->sc_bus, 1); 773 } 774 if (i >= 100) 775 return EIO; 776 777 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 778 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 779 pagesize = ffs(pagesize); 780 if (pagesize == 0) 781 return EIO; 782 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 783 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 784 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 785 (uint32_t)sc->sc_maxslots); 786 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 787 788 usbd_status err; 789 790 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 791 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 792 if (sc->sc_maxspbuf != 0) { 793 err = usb_allocmem(&sc->sc_bus, 794 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 795 &sc->sc_spbufarray_dma); 796 if (err) 797 return err; 798 799 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * sc->sc_maxspbuf, KM_SLEEP); 800 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 801 for (i = 0; i < sc->sc_maxspbuf; i++) { 802 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 803 /* allocate contexts */ 804 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 805 sc->sc_pgsz, dma); 806 if (err) 807 return err; 808 spbufarray[i] = htole64(DMAADDR(dma, 0)); 809 usb_syncmem(dma, 0, sc->sc_pgsz, 810 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 811 } 812 813 usb_syncmem(&sc->sc_spbufarray_dma, 0, 814 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 815 } 816 817 config = xhci_op_read_4(sc, XHCI_CONFIG); 818 config &= ~0xFF; 819 config |= sc->sc_maxslots & 0xFF; 820 xhci_op_write_4(sc, XHCI_CONFIG, config); 821 822 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 823 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 824 if (err) { 825 aprint_error_dev(sc->sc_dev, "command ring init fail\n"); 826 return err; 827 } 828 829 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 830 XHCI_EVENT_RING_SEGMENTS_ALIGN); 831 if (err) { 832 aprint_error_dev(sc->sc_dev, "event ring init fail\n"); 833 return err; 834 } 835 836 usb_dma_t *dma; 837 size_t size; 838 size_t align; 839 840 dma = &sc->sc_eventst_dma; 841 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 842 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 843 KASSERT(size <= (512 * 1024)); 844 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 845 err = usb_allocmem(&sc->sc_bus, size, align, dma); 846 847 memset(KERNADDR(dma, 0), 0, size); 848 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 849 aprint_debug_dev(sc->sc_dev, "eventst: %s %016jx %p %zx\n", 850 usbd_errstr(err), 851 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 852 KERNADDR(&sc->sc_eventst_dma, 0), 853 sc->sc_eventst_dma.udma_block->size); 854 855 dma = &sc->sc_dcbaa_dma; 856 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 857 KASSERT(size <= 2048); 858 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 859 err = usb_allocmem(&sc->sc_bus, size, align, dma); 860 861 memset(KERNADDR(dma, 0), 0, size); 862 if (sc->sc_maxspbuf != 0) { 863 /* 864 * DCBA entry 0 hold the scratchbuf array pointer. 865 */ 866 *(uint64_t *)KERNADDR(dma, 0) = 867 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 868 } 869 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 870 aprint_debug_dev(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n", 871 usbd_errstr(err), 872 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 873 KERNADDR(&sc->sc_dcbaa_dma, 0), 874 sc->sc_dcbaa_dma.udma_block->size); 875 876 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 877 KM_SLEEP); 878 879 cv_init(&sc->sc_command_cv, "xhcicmd"); 880 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 881 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 882 cv_init(&sc->sc_softwake_cv, "xhciab"); 883 884 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 885 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 886 887 /* Set up the bus struct. */ 888 sc->sc_bus.ub_methods = &xhci_bus_methods; 889 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 890 891 struct xhci_erste *erst; 892 erst = KERNADDR(&sc->sc_eventst_dma, 0); 893 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 894 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 895 erst[0].erste_3 = htole32(0); 896 usb_syncmem(&sc->sc_eventst_dma, 0, 897 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 898 899 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 900 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 901 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 902 XHCI_ERDP_LO_BUSY); 903 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 904 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 905 sc->sc_cr.xr_cs); 906 907 #if 0 908 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 909 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 910 #endif 911 912 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 913 #ifdef XHCI_QUIRK_INTEL 914 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 915 /* Intel xhci needs interrupt rate moderated. */ 916 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 917 else 918 #endif /* XHCI_QUIRK_INTEL */ 919 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 920 921 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 922 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 923 xhci_op_read_4(sc, XHCI_USBCMD)); 924 925 return USBD_NORMAL_COMPLETION; 926 } 927 928 int 929 xhci_intr(void *v) 930 { 931 struct xhci_softc * const sc = v; 932 int ret = 0; 933 934 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 935 936 if (sc == NULL) 937 return 0; 938 939 mutex_spin_enter(&sc->sc_intr_lock); 940 941 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 942 goto done; 943 944 /* If we get an interrupt while polling, then just ignore it. */ 945 if (sc->sc_bus.ub_usepolling) { 946 #ifdef DIAGNOSTIC 947 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 948 #endif 949 goto done; 950 } 951 952 ret = xhci_intr1(sc); 953 done: 954 mutex_spin_exit(&sc->sc_intr_lock); 955 return ret; 956 } 957 958 int 959 xhci_intr1(struct xhci_softc * const sc) 960 { 961 uint32_t usbsts; 962 uint32_t iman; 963 964 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 965 966 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 967 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 968 #if 0 969 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 970 return 0; 971 } 972 #endif 973 xhci_op_write_4(sc, XHCI_USBSTS, 974 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 975 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 976 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 977 978 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 979 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 980 #ifdef XHCI_QUIRK_FORCE_INTR 981 982 if (!(sc->sc_quirks & XHCI_QUIRK_FORCE_INTR)) { 983 if ((iman & XHCI_IMAN_INTR_PEND) == 0) { 984 return 0; 985 } 986 } 987 988 #else 989 if ((iman & XHCI_IMAN_INTR_PEND) == 0) { 990 return 0; 991 } 992 #endif /* XHCI_QUIRK_FORCE_INTR */ 993 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 994 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 995 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 996 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 997 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 998 999 usb_schedsoftintr(&sc->sc_bus); 1000 1001 return 1; 1002 } 1003 1004 /* 1005 * 3 port speed types used in USB stack 1006 * 1007 * usbdi speed 1008 * definition: USB_SPEED_* in usb.h 1009 * They are used in struct usbd_device in USB stack. 1010 * ioctl interface uses these values too. 1011 * port_status speed 1012 * definition: UPS_*_SPEED in usb.h 1013 * They are used in usb_port_status_t. 1014 * Some 3.0 values overlap with 2.0 values. 1015 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1016 * means UPS_LOW_SPEED in HS.) 1017 * port status sent from hub also uses these values. 1018 * (but I've never seen UPS_SUPER_SPEED in port_status from hub.) 1019 * xspeed: 1020 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1021 * They are used in only slot context and PORTSC reg of xhci. 1022 * The difference between usbdi speed and them are that 1023 * FS and LS values are swapped. 1024 */ 1025 1026 static int 1027 xhci_speed2xspeed(int speed) 1028 { 1029 switch (speed) { 1030 case USB_SPEED_LOW: return 2; 1031 case USB_SPEED_FULL: return 1; 1032 case USB_SPEED_HIGH: return 3; 1033 case USB_SPEED_SUPER: return 4; 1034 default: 1035 break; 1036 } 1037 return 0; 1038 } 1039 1040 /* construct slot context */ 1041 static void 1042 xhci_setup_sctx(struct usbd_device *dev, uint32_t *cp) 1043 { 1044 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 1045 int speed = dev->ud_speed; 1046 int tthubslot, ttportnum; 1047 bool ishub; 1048 bool usemtt; 1049 1050 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1051 1052 /* 6.2.2 */ 1053 /* 1054 * tthubslot: 1055 * This is the slot ID of parent HS hub 1056 * if LS/FS device is connected && connected through HS hub. 1057 * This is 0 if device is not LS/FS device || 1058 * parent hub is not HS hub || 1059 * attached to root hub. 1060 * ttportnum: 1061 * This is the downstream facing port of parent HS hub 1062 * if LS/FS device is connected. 1063 * This is 0 if device is not LS/FS device || 1064 * parent hub is not HS hub || 1065 * attached to root hub. 1066 */ 1067 if (dev->ud_myhsport != NULL && 1068 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1069 (dev->ud_myhub != NULL && 1070 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1071 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 1072 ttportnum = dev->ud_myhsport->up_portno; 1073 /* XXX addr == slot ? */ 1074 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 1075 } else { 1076 ttportnum = 0; 1077 tthubslot = 0; 1078 } 1079 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 1080 dev->ud_myhsport, ttportnum, tthubslot, 0); 1081 1082 /* ishub is valid after reading UDESC_DEVICE */ 1083 ishub = (dd->bDeviceClass == UDCLASS_HUB); 1084 1085 /* dev->ud_hub is valid after reading UDESC_HUB */ 1086 if (ishub && dev->ud_hub) { 1087 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 1088 1089 cp[1] |= htole32(XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts)); 1090 cp[2] |= htole32(XHCI_SCTX_2_TT_THINK_TIME_SET( 1091 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK))); 1092 DPRINTFN(4, "nports=%d ttt=%d", 1093 hd->bNbrPorts, XHCI_SCTX_2_TT_THINK_TIME_GET(cp[2]), 0, 0); 1094 } 1095 1096 #define IS_TTHUB(dd) \ 1097 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 1098 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 1099 1100 /* 1101 * MTT flag is set if 1102 * 1. this is HS hub && MTT is enabled 1103 * or 1104 * 2. this is not hub && this is LS or FS device && 1105 * MTT of parent HS hub (and its parent, too) is enabled 1106 */ 1107 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 1108 usemtt = true; 1109 else if (!ishub && 1110 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 1111 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1112 (dev->ud_myhub != NULL && 1113 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1114 dev->ud_myhsport != NULL && 1115 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 1116 usemtt = true; 1117 else 1118 usemtt = false; 1119 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 1120 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 1121 1122 cp[0] |= htole32( 1123 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)) | 1124 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 1125 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0) 1126 ); 1127 cp[1] |= htole32(0); 1128 cp[2] |= htole32( 1129 XHCI_SCTX_2_IRQ_TARGET_SET(0) | 1130 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 1131 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum) 1132 ); 1133 cp[3] |= htole32(0); 1134 } 1135 1136 /* 1137 * called 1138 * from xhci_open 1139 * from usbd_setup_pipe_flags 1140 * from usbd_open_pipe_ival 1141 */ 1142 static usbd_status 1143 xhci_configure_endpoint(struct usbd_pipe *pipe) 1144 { 1145 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1146 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1147 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1148 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1149 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1150 struct xhci_trb trb; 1151 usbd_status err; 1152 uint32_t *cp; 1153 uint32_t mps = UGETW(ed->wMaxPacketSize); 1154 uint32_t maxb = 0; 1155 int speed = pipe->up_dev->ud_speed; 1156 uint32_t ival = ed->bInterval; 1157 1158 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1159 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1160 xs->xs_idx, dci, ed->bEndpointAddress, ed->bmAttributes); 1161 1162 /* XXX ensure input context is available? */ 1163 1164 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1165 1166 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1167 cp[0] = htole32(0); 1168 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 1169 1170 /* set up input slot context */ 1171 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1172 xhci_setup_sctx(pipe->up_dev, cp); 1173 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1174 1175 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 1176 cp[0] = htole32( 1177 XHCI_EPCTX_0_EPSTATE_SET(0) | 1178 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 1179 XHCI_EPCTX_0_LSA_SET(0) 1180 ); 1181 cp[1] = htole32( 1182 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 1183 XHCI_EPCTX_1_MAXB_SET(0) 1184 ); 1185 if (xfertype != UE_ISOCHRONOUS) 1186 cp[1] |= htole32(XHCI_EPCTX_1_CERR_SET(3)); 1187 1188 if (speed == USB_SPEED_SUPER) { 1189 usbd_desc_iter_t iter; 1190 const usb_cdc_descriptor_t *cdcd; 1191 const usb_endpoint_ss_comp_descriptor_t * esscd = NULL; 1192 uint8_t ep; 1193 1194 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc( 1195 pipe->up_dev, UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 1196 usb_desc_iter_init(pipe->up_dev, &iter); 1197 iter.cur = (const void *)cdcd; 1198 1199 /* find endpoint_ss_comp desc for ep of this pipe */ 1200 for(ep = 0;;) { 1201 cdcd = (const usb_cdc_descriptor_t *) 1202 usb_desc_iter_next(&iter); 1203 if (cdcd == NULL) 1204 break; 1205 if (ep == 0 && 1206 cdcd->bDescriptorType == UDESC_ENDPOINT) { 1207 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 1208 bEndpointAddress; 1209 if (UE_GET_ADDR(ep) == 1210 UE_GET_ADDR(ed->bEndpointAddress)) { 1211 cdcd = (const usb_cdc_descriptor_t *) 1212 usb_desc_iter_next(&iter); 1213 break; 1214 } 1215 ep = 0; 1216 } 1217 } 1218 if (cdcd != NULL && 1219 cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 1220 esscd = (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 1221 maxb = esscd->bMaxBurst; 1222 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1223 DPRINTFN(4, "setting SS MaxBurst %u", maxb, 0, 0, 0); 1224 } 1225 } 1226 if (speed == USB_SPEED_HIGH && 1227 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 1228 maxb = UE_GET_TRANS(UGETW(ed->wMaxPacketSize)); 1229 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1230 DPRINTFN(4, "setting HS MaxBurst %u", maxb, 0, 0, 0); 1231 } 1232 1233 switch (xfertype) { 1234 case UE_INTERRUPT: 1235 /* 6.2.3.6 */ 1236 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 1237 ival = ival > 10 ? 10 : ival; 1238 ival = ival < 3 ? 3 : ival; 1239 } else { 1240 ival = ival > 15 ? 15 : ival; 1241 } 1242 if (speed == USB_SPEED_SUPER) { 1243 if (maxb > 0) 1244 mps = 1024; 1245 } else { 1246 mps = mps ? mps : 8; 1247 } 1248 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1249 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1250 cp[4] = htole32( 1251 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) /* XXX */ 1252 ); 1253 break; 1254 case UE_CONTROL: 1255 if (speed == USB_SPEED_SUPER) 1256 mps = 512; 1257 else 1258 mps = mps ? mps : 8; 1259 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1260 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(8)); /* XXX */ 1261 break; 1262 #ifdef notyet 1263 case UE_ISOCHRONOUS: 1264 if (speed == USB_SPEED_FULL) { 1265 ival = ival > 18 ? 18 : ival; 1266 ival = ival < 3 ? 3 : ival; 1267 } else { 1268 ival = ival > 15 ? 15 : ival; 1269 } 1270 if (speed == USB_SPEED_SUPER) { 1271 mps = 1024; 1272 } else { 1273 mps = mps ? mps : 1024; 1274 } 1275 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1276 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(1024)); /* XXX */ 1277 break; 1278 #endif 1279 default: 1280 if (speed == USB_SPEED_SUPER) 1281 mps = 1024; 1282 else 1283 mps = mps ? mps : 512; 1284 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1285 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(1024)); /* XXX */ 1286 break; 1287 } 1288 *(uint64_t *)(&cp[2]) = htole64( 1289 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 1290 XHCI_EPCTX_2_DCS_SET(1)); 1291 1292 /* sync input contexts before they are read from memory */ 1293 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1294 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1295 sc->sc_ctxsz * 1); 1296 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1297 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1298 1299 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1300 trb.trb_2 = 0; 1301 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1302 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1303 1304 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1305 1306 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1307 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1308 sc->sc_ctxsz * 1); 1309 1310 return err; 1311 } 1312 1313 #if 0 1314 static usbd_status 1315 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1316 { 1317 #ifdef USB_DEBUG 1318 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1319 #endif 1320 1321 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1322 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1323 1324 return USBD_NORMAL_COMPLETION; 1325 } 1326 #endif 1327 1328 /* 4.6.8, 6.4.3.7 */ 1329 static usbd_status 1330 xhci_reset_endpoint(struct usbd_pipe *pipe) 1331 { 1332 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1333 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1334 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1335 struct xhci_trb trb; 1336 usbd_status err; 1337 1338 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1339 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1340 1341 KASSERT(!mutex_owned(&sc->sc_lock)); 1342 1343 trb.trb_0 = 0; 1344 trb.trb_2 = 0; 1345 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1346 XHCI_TRB_3_EP_SET(dci) | 1347 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1348 1349 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1350 1351 return err; 1352 } 1353 1354 /* 1355 * 4.6.9, 6.4.3.8 1356 * Stop execution of TDs on xfer ring. 1357 * Should be called with sc_lock held. 1358 */ 1359 static usbd_status 1360 xhci_stop_endpoint(struct usbd_pipe *pipe) 1361 { 1362 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1363 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1364 struct xhci_trb trb; 1365 usbd_status err; 1366 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1367 1368 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1369 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1370 1371 KASSERT(mutex_owned(&sc->sc_lock)); 1372 1373 trb.trb_0 = 0; 1374 trb.trb_2 = 0; 1375 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1376 XHCI_TRB_3_EP_SET(dci) | 1377 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1378 1379 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1380 1381 return err; 1382 } 1383 1384 /* 1385 * Set TR Dequeue Pointer. 1386 * xCHI 1.1 4.6.10 6.4.3.9 1387 * Purge all of the transfer requests on ring. 1388 * EPSTATE of endpoint must be ERROR or STOPPED, or CONTEXT_STATE error. 1389 */ 1390 static usbd_status 1391 xhci_set_dequeue(struct usbd_pipe *pipe) 1392 { 1393 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1394 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1395 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1396 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1397 struct xhci_trb trb; 1398 usbd_status err; 1399 1400 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1401 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1402 1403 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1404 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1405 BUS_DMASYNC_PREWRITE); 1406 1407 xr->xr_ep = 0; 1408 xr->xr_cs = 1; 1409 1410 /* set DCS */ 1411 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1412 trb.trb_2 = 0; 1413 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1414 XHCI_TRB_3_EP_SET(dci) | 1415 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1416 1417 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1418 1419 return err; 1420 } 1421 1422 /* 1423 * Open new pipe: called from usbd_setup_pipe_flags. 1424 * Fills methods of pipe. 1425 * If pipe is not for ep0, calls configure_endpoint. 1426 */ 1427 static usbd_status 1428 xhci_open(struct usbd_pipe *pipe) 1429 { 1430 struct usbd_device * const dev = pipe->up_dev; 1431 struct xhci_softc * const sc = dev->ud_bus->ub_hcpriv; 1432 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1433 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1434 1435 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1436 DPRINTFN(1, "addr %d depth %d port %d speed %d", 1437 dev->ud_addr, dev->ud_depth, dev->ud_powersrc->up_portno, 1438 dev->ud_speed); 1439 1440 if (sc->sc_dying) 1441 return USBD_IOERROR; 1442 1443 /* Root Hub */ 1444 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1445 switch (ed->bEndpointAddress) { 1446 case USB_CONTROL_ENDPOINT: 1447 pipe->up_methods = &roothub_ctrl_methods; 1448 break; 1449 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1450 pipe->up_methods = &xhci_root_intr_methods; 1451 break; 1452 default: 1453 pipe->up_methods = NULL; 1454 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1455 ed->bEndpointAddress, 0, 0, 0); 1456 return USBD_INVAL; 1457 } 1458 return USBD_NORMAL_COMPLETION; 1459 } 1460 1461 switch (xfertype) { 1462 case UE_CONTROL: 1463 pipe->up_methods = &xhci_device_ctrl_methods; 1464 break; 1465 case UE_ISOCHRONOUS: 1466 pipe->up_methods = &xhci_device_isoc_methods; 1467 return USBD_INVAL; 1468 break; 1469 case UE_BULK: 1470 pipe->up_methods = &xhci_device_bulk_methods; 1471 break; 1472 case UE_INTERRUPT: 1473 pipe->up_methods = &xhci_device_intr_methods; 1474 break; 1475 default: 1476 return USBD_IOERROR; 1477 break; 1478 } 1479 1480 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1481 return xhci_configure_endpoint(pipe); 1482 1483 return USBD_NORMAL_COMPLETION; 1484 } 1485 1486 /* 1487 * Closes pipe, called from usbd_kill_pipe via close methods. 1488 * If the endpoint to be closed is ep0, disable_slot. 1489 * Should be called with sc_lock held. 1490 */ 1491 static usbd_status 1492 xhci_close_pipe(struct usbd_pipe *pipe) 1493 { 1494 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1495 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1496 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1497 const u_int dci = xhci_ep_get_dci(ed); 1498 struct xhci_trb trb; 1499 usbd_status err; 1500 uint32_t *cp; 1501 1502 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1503 1504 if (sc->sc_dying) 1505 return USBD_IOERROR; 1506 1507 if (xs == NULL || xs->xs_idx == 0) 1508 /* xs is uninitialized before xhci_init_slot */ 1509 return USBD_IOERROR; 1510 1511 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1512 1513 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1514 KASSERT(mutex_owned(&sc->sc_lock)); 1515 1516 if (pipe->up_dev->ud_depth == 0) 1517 return USBD_NORMAL_COMPLETION; 1518 1519 if (dci == XHCI_DCI_EP_CONTROL) { 1520 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1521 return xhci_disable_slot(sc, xs->xs_idx); 1522 } 1523 1524 /* 1525 * This may fail in the case that xhci_close_pipe is called after 1526 * xhci_abort_xfer e.g. usbd_kill_pipe. 1527 */ 1528 (void)xhci_stop_endpoint(pipe); 1529 1530 /* 1531 * set appropriate bit to be dropped. 1532 * don't set DC bit to 1, otherwise all endpoints 1533 * would be deconfigured. 1534 */ 1535 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1536 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1537 cp[1] = htole32(0); 1538 1539 /* XXX should be most significant one, not dci? */ 1540 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1541 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1542 1543 /* sync input contexts before they are read from memory */ 1544 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1545 1546 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1547 trb.trb_2 = 0; 1548 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1549 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1550 1551 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1552 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1553 1554 return err; 1555 } 1556 1557 /* 1558 * Abort transfer. 1559 * Called with sc_lock held. 1560 * May be called from softintr context. 1561 */ 1562 static void 1563 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1564 { 1565 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1566 1567 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1568 DPRINTFN(4, "xfer %p pipe %p status %d", 1569 xfer, xfer->ux_pipe, status, 0); 1570 1571 KASSERT(mutex_owned(&sc->sc_lock)); 1572 1573 if (sc->sc_dying) { 1574 /* If we're dying, just do the software part. */ 1575 DPRINTFN(4, "dying", 0, 0, 0, 0); 1576 xfer->ux_status = status; /* make software ignore it */ 1577 callout_stop(&xfer->ux_callout); 1578 usb_transfer_complete(xfer); 1579 return; 1580 } 1581 1582 /* XXX need more stuff */ 1583 xfer->ux_status = status; 1584 callout_stop(&xfer->ux_callout); 1585 usb_transfer_complete(xfer); 1586 1587 KASSERT(mutex_owned(&sc->sc_lock)); 1588 } 1589 1590 #if 1 /* XXX experimental */ 1591 /* 1592 * Recover STALLed endpoint. 1593 * xHCI 1.1 sect 4.10.2.1 1594 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1595 * all transfers on transfer ring. 1596 * These are done in thread context asynchronously. 1597 */ 1598 static void 1599 xhci_clear_endpoint_stall_async_task(void *cookie) 1600 { 1601 struct usbd_xfer * const xfer = cookie; 1602 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1603 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1604 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1605 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1606 1607 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1608 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1609 1610 xhci_reset_endpoint(xfer->ux_pipe); 1611 xhci_set_dequeue(xfer->ux_pipe); 1612 1613 mutex_enter(&sc->sc_lock); 1614 tr->is_halted = false; 1615 usb_transfer_complete(xfer); 1616 mutex_exit(&sc->sc_lock); 1617 DPRINTFN(4, "ends", 0, 0, 0, 0); 1618 } 1619 1620 static usbd_status 1621 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1622 { 1623 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1624 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1625 1626 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1627 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1628 1629 if (sc->sc_dying) { 1630 return USBD_IOERROR; 1631 } 1632 1633 usb_init_task(&xp->xp_async_task, 1634 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1635 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1636 DPRINTFN(4, "ends", 0, 0, 0, 0); 1637 1638 return USBD_NORMAL_COMPLETION; 1639 } 1640 1641 #endif /* XXX experimental */ 1642 1643 /* 1644 * Notify roothub port status/change to uhub_intr. 1645 */ 1646 static void 1647 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1648 { 1649 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1650 uint8_t *p; 1651 1652 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1653 DPRINTFN(4, "port %u status change", port, 0, 0, 0); 1654 1655 if (xfer == NULL) 1656 return; 1657 1658 p = xfer->ux_buf; 1659 memset(p, 0, xfer->ux_length); 1660 p[port/NBBY] |= 1 << (port%NBBY); 1661 xfer->ux_actlen = xfer->ux_length; 1662 xfer->ux_status = USBD_NORMAL_COMPLETION; 1663 usb_transfer_complete(xfer); 1664 } 1665 1666 /* 1667 * Process events: 1668 * + Transfer comeplete 1669 * + Command complete 1670 * + Roothub Port status/change 1671 */ 1672 static void 1673 xhci_handle_event(struct xhci_softc * const sc, 1674 const struct xhci_trb * const trb) 1675 { 1676 uint64_t trb_0; 1677 uint32_t trb_2, trb_3; 1678 uint8_t trberr; 1679 1680 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1681 1682 trb_0 = le64toh(trb->trb_0); 1683 trb_2 = le32toh(trb->trb_2); 1684 trb_3 = le32toh(trb->trb_3); 1685 trberr = XHCI_TRB_2_ERROR_GET(trb_2); 1686 1687 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1688 trb, trb_0, trb_2, trb_3); 1689 1690 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 1691 case XHCI_TRB_EVENT_TRANSFER: { 1692 u_int slot, dci; 1693 struct xhci_slot *xs; 1694 struct xhci_ring *xr; 1695 struct xhci_xfer *xx; 1696 struct usbd_xfer *xfer; 1697 usbd_status err; 1698 1699 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1700 dci = XHCI_TRB_3_EP_GET(trb_3); 1701 1702 xs = &sc->sc_slots[slot]; 1703 xr = &xs->xs_ep[dci].xe_tr; 1704 /* sanity check */ 1705 KASSERT(xs->xs_idx != 0); 1706 1707 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1708 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 1709 1710 /* trb_0 range sanity check */ 1711 if (trb_0 < trbp || 1712 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 1713 (trb_0 - trbp) / sizeof(struct xhci_trb) >= 1714 xr->xr_ntrb) { 1715 DPRINTFN(1, 1716 "invalid trb_0 0x%"PRIx64" trbp 0x%"PRIx64, 1717 trb_0, trbp, 0, 0); 1718 break; 1719 } 1720 int idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 1721 xx = xr->xr_cookies[idx]; 1722 } else { 1723 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1724 } 1725 xfer = &xx->xx_xfer; 1726 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1727 1728 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1729 DPRINTFN(14, "transfer event data: " 1730 "0x%016"PRIx64" 0x%08"PRIx32" %02x", 1731 trb_0, XHCI_TRB_2_REM_GET(trb_2), 1732 XHCI_TRB_2_ERROR_GET(trb_2), 0); 1733 if ((trb_0 & 0x3) == 0x3) { 1734 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1735 } 1736 } 1737 1738 if (trberr == XHCI_TRB_ERROR_SUCCESS || 1739 trberr == XHCI_TRB_ERROR_SHORT_PKT) { 1740 xfer->ux_actlen = 1741 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1742 err = USBD_NORMAL_COMPLETION; 1743 } else if (trberr == XHCI_TRB_ERROR_STALL || 1744 trberr == XHCI_TRB_ERROR_BABBLE) { 1745 err = USBD_STALLED; 1746 xr->is_halted = true; 1747 DPRINTFN(1, "evh: xfer done: ERR %u slot %u dci %u", 1748 trberr, slot, dci, 0); 1749 #if 1 /* XXX experimental */ 1750 /* 1751 * Stalled endpoints can be recoverd by issuing 1752 * command TRB TYPE_RESET_EP on xHCI instead of 1753 * issuing request CLEAR_PORT_FEATURE UF_ENDPOINT_HALT 1754 * on the endpoint. However, this function may be 1755 * called from softint context (e.g. from umass), 1756 * in that case driver gets KASSERT in cv_timedwait 1757 * in xhci_do_command. 1758 * To avoid this, this runs reset_endpoint and 1759 * usb_transfer_complete in usb task thread 1760 * asynchronously (and then umass issues clear 1761 * UF_ENDPOINT_HALT). 1762 */ 1763 xfer->ux_status = err; 1764 xhci_clear_endpoint_stall_async(xfer); 1765 break; 1766 #endif 1767 } else { 1768 DPRINTFN(1, "evh: xfer done: ERR %u slot %u dci %u", 1769 trberr, slot, dci, 0); 1770 err = USBD_IOERROR; 1771 } 1772 xfer->ux_status = err; 1773 1774 //mutex_enter(&sc->sc_lock); /* XXX ??? */ 1775 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1776 if ((trb_0 & 0x3) == 0x0) { 1777 usb_transfer_complete(xfer); 1778 } 1779 } else { 1780 usb_transfer_complete(xfer); 1781 } 1782 //mutex_exit(&sc->sc_lock); /* XXX ??? */ 1783 1784 } 1785 break; 1786 case XHCI_TRB_EVENT_CMD_COMPLETE: 1787 if (trb_0 == sc->sc_command_addr) { 1788 sc->sc_result_trb.trb_0 = trb_0; 1789 sc->sc_result_trb.trb_2 = trb_2; 1790 sc->sc_result_trb.trb_3 = trb_3; 1791 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1792 XHCI_TRB_ERROR_SUCCESS) { 1793 DPRINTFN(1, "command completion " 1794 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1795 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1796 } 1797 cv_signal(&sc->sc_command_cv); 1798 } else { 1799 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 1800 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1801 trb_2, trb_3); 1802 } 1803 break; 1804 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1805 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1806 break; 1807 default: 1808 break; 1809 } 1810 } 1811 1812 static void 1813 xhci_softintr(void *v) 1814 { 1815 struct usbd_bus * const bus = v; 1816 struct xhci_softc * const sc = bus->ub_hcpriv; 1817 struct xhci_ring * const er = &sc->sc_er; 1818 struct xhci_trb *trb; 1819 int i, j, k; 1820 1821 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1822 1823 i = er->xr_ep; 1824 j = er->xr_cs; 1825 1826 DPRINTFN(16, "xr_ep %d xr_cs %d", i, j, 0, 0); 1827 1828 while (1) { 1829 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 1830 BUS_DMASYNC_POSTREAD); 1831 trb = &er->xr_trb[i]; 1832 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1833 1834 if (j != k) 1835 break; 1836 1837 xhci_handle_event(sc, trb); 1838 1839 i++; 1840 if (i == XHCI_EVENT_RING_TRBS) { 1841 i = 0; 1842 j ^= 1; 1843 } 1844 } 1845 1846 er->xr_ep = i; 1847 er->xr_cs = j; 1848 1849 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 1850 XHCI_ERDP_LO_BUSY); 1851 1852 DPRINTFN(16, "ends", 0, 0, 0, 0); 1853 1854 return; 1855 } 1856 1857 static void 1858 xhci_poll(struct usbd_bus *bus) 1859 { 1860 struct xhci_softc * const sc = bus->ub_hcpriv; 1861 1862 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1863 1864 mutex_spin_enter(&sc->sc_intr_lock); 1865 xhci_intr1(sc); 1866 mutex_spin_exit(&sc->sc_intr_lock); 1867 1868 return; 1869 } 1870 1871 static struct usbd_xfer * 1872 xhci_allocx(struct usbd_bus *bus) 1873 { 1874 struct xhci_softc * const sc = bus->ub_hcpriv; 1875 struct usbd_xfer *xfer; 1876 1877 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1878 1879 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1880 if (xfer != NULL) { 1881 memset(xfer, 0, sizeof(struct xhci_xfer)); 1882 #ifdef DIAGNOSTIC 1883 xfer->ux_state = XFER_BUSY; 1884 #endif 1885 } 1886 1887 return xfer; 1888 } 1889 1890 static void 1891 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1892 { 1893 struct xhci_softc * const sc = bus->ub_hcpriv; 1894 1895 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1896 1897 #ifdef DIAGNOSTIC 1898 if (xfer->ux_state != XFER_BUSY) { 1899 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 1900 xfer, xfer->ux_state, 0, 0); 1901 } 1902 xfer->ux_state = XFER_FREE; 1903 #endif 1904 pool_cache_put(sc->sc_xferpool, xfer); 1905 } 1906 1907 static void 1908 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1909 { 1910 struct xhci_softc * const sc = bus->ub_hcpriv; 1911 1912 *lock = &sc->sc_lock; 1913 } 1914 1915 extern uint32_t usb_cookie_no; 1916 1917 /* 1918 * Called if uhub_explore find new device (via usbd_new_device). 1919 * Allocate and construct dev structure of default endpoint (ep0). 1920 * Determine initial MaxPacketSize (mps) by speed. 1921 * Determine route string and roothub port for slot of dev. 1922 * Allocate pipe of ep0. 1923 * Enable and initialize slot and Set Address. 1924 * Read device descriptor. 1925 * Register this device. 1926 */ 1927 static usbd_status 1928 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 1929 int speed, int port, struct usbd_port *up) 1930 { 1931 struct xhci_softc * const sc = bus->ub_hcpriv; 1932 struct usbd_device *dev; 1933 usbd_status err; 1934 usb_device_descriptor_t *dd; 1935 struct usbd_device *hub; 1936 struct usbd_device *adev; 1937 int rhport = 0; 1938 struct xhci_slot *xs; 1939 uint32_t *cp; 1940 uint32_t route = 0; 1941 uint8_t slot = 0; 1942 uint8_t addr; 1943 1944 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1945 DPRINTFN(4, "port=%d depth=%d speed=%d upport %d", 1946 port, depth, speed, up->up_portno); 1947 1948 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 1949 if (dev == NULL) 1950 return USBD_NOMEM; 1951 1952 dev->ud_bus = bus; 1953 1954 /* Set up default endpoint handle. */ 1955 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 1956 1957 /* Set up default endpoint descriptor. */ 1958 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 1959 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 1960 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 1961 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 1962 /* 4.3, 4.8.2.1 */ 1963 switch (speed) { 1964 case USB_SPEED_SUPER: 1965 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 1966 break; 1967 case USB_SPEED_FULL: 1968 /* XXX using 64 as initial mps of ep0 in FS */ 1969 case USB_SPEED_HIGH: 1970 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 1971 break; 1972 case USB_SPEED_LOW: 1973 default: 1974 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 1975 break; 1976 } 1977 dev->ud_ep0desc.bInterval = 0; 1978 1979 /* doesn't matter, just don't let it uninitialized */ 1980 dev->ud_ep0.ue_toggle = 0; 1981 1982 DPRINTFN(4, "up %p portno %d", up, up->up_portno, 0, 0); 1983 1984 dev->ud_quirks = &usbd_no_quirk; 1985 dev->ud_addr = 0; 1986 dev->ud_ddesc.bMaxPacketSize = 0; 1987 dev->ud_depth = depth; 1988 dev->ud_powersrc = up; 1989 dev->ud_myhub = up->up_parent; 1990 1991 up->up_dev = dev; 1992 1993 /* Locate root hub port */ 1994 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 1995 uint32_t dep; 1996 1997 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 1998 hub, hub->ud_depth, hub->ud_powersrc, 1999 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2000 2001 if (hub->ud_powersrc == NULL) 2002 break; 2003 dep = hub->ud_depth; 2004 if (dep == 0) 2005 break; 2006 rhport = hub->ud_powersrc->up_portno; 2007 if (dep > USB_HUB_MAX_DEPTH) 2008 continue; 2009 2010 route |= 2011 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2012 << ((dep - 1) * 4); 2013 } 2014 route = route >> 4; 2015 DPRINTFN(4, "rhport %d Route %05x hub %p", rhport, route, hub, 0); 2016 2017 /* Locate port on upstream high speed hub */ 2018 for (adev = dev, hub = up->up_parent; 2019 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2020 adev = hub, hub = hub->ud_myhub) 2021 ; 2022 if (hub) { 2023 int p; 2024 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2025 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2026 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2027 goto found; 2028 } 2029 } 2030 panic("xhci_new_device: cannot find HS port"); 2031 found: 2032 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2033 } else { 2034 dev->ud_myhsport = NULL; 2035 } 2036 2037 dev->ud_speed = speed; 2038 dev->ud_langid = USBD_NOLANG; 2039 dev->ud_cookie.cookie = ++usb_cookie_no; 2040 2041 /* Establish the default pipe. */ 2042 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2043 &dev->ud_pipe0); 2044 if (err) { 2045 goto bad; 2046 } 2047 2048 dd = &dev->ud_ddesc; 2049 2050 if ((depth == 0) && (port == 0)) { 2051 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2052 bus->ub_devices[dev->ud_addr] = dev; 2053 err = usbd_get_initial_ddesc(dev, dd); 2054 if (err) 2055 goto bad; 2056 err = usbd_reload_device_desc(dev); 2057 if (err) 2058 goto bad; 2059 } else { 2060 err = xhci_enable_slot(sc, &slot); 2061 if (err) 2062 goto bad; 2063 xs = &sc->sc_slots[slot]; 2064 dev->ud_hcpriv = xs; 2065 err = xhci_init_slot(dev, slot, route, rhport); 2066 if (err) { 2067 dev->ud_hcpriv = NULL; 2068 /* 2069 * We have to disable_slot here because 2070 * xs->xs_idx == 0 when xhci_init_slot fails, 2071 * in that case usbd_remove_dev won't work. 2072 */ 2073 mutex_enter(&sc->sc_lock); 2074 xhci_disable_slot(sc, slot); 2075 mutex_exit(&sc->sc_lock); 2076 goto bad; 2077 } 2078 2079 /* Allow device time to set new address */ 2080 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2081 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2082 //hexdump("slot context", cp, sc->sc_ctxsz); 2083 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2084 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2085 /* XXX ensure we know when the hardware does something 2086 we can't yet cope with */ 2087 KASSERT(addr >= 1 && addr <= 127); 2088 dev->ud_addr = addr; 2089 /* XXX dev->ud_addr not necessarily unique on bus */ 2090 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2091 bus->ub_devices[dev->ud_addr] = dev; 2092 2093 err = usbd_get_initial_ddesc(dev, dd); 2094 if (err) 2095 goto bad; 2096 /* 4.8.2.1 */ 2097 if (speed == USB_SPEED_SUPER) { 2098 if (dd->bMaxPacketSize != 9) { 2099 printf("%s: invalid mps 2^%u for SS ep0," 2100 " using 512\n", 2101 device_xname(sc->sc_dev), 2102 dd->bMaxPacketSize); 2103 dd->bMaxPacketSize = 9; 2104 } 2105 USETW(dev->ud_ep0desc.wMaxPacketSize, 2106 (1 << dd->bMaxPacketSize)); 2107 } else 2108 USETW(dev->ud_ep0desc.wMaxPacketSize, 2109 dd->bMaxPacketSize); 2110 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2111 xhci_update_ep0_mps(sc, xs, 2112 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2113 err = usbd_reload_device_desc(dev); 2114 if (err) 2115 goto bad; 2116 2117 #if 0 2118 /* Re-establish the default pipe with the new MPS. */ 2119 /* In xhci this is done by xhci_update_ep0_mps. */ 2120 usbd_kill_pipe(dev->ud_pipe0); 2121 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2122 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2123 #endif 2124 } 2125 2126 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2127 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2128 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2129 dd->bDeviceClass, dd->bDeviceSubClass, 2130 dd->bDeviceProtocol, 0); 2131 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2132 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2133 dev->ud_speed); 2134 2135 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2136 2137 if ((depth == 0) && (port == 0)) { 2138 usbd_attach_roothub(parent, dev); 2139 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2140 return USBD_NORMAL_COMPLETION; 2141 } 2142 2143 2144 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2145 bad: 2146 if (err != USBD_NORMAL_COMPLETION) { 2147 usbd_remove_device(dev, up); 2148 } 2149 2150 return err; 2151 } 2152 2153 static usbd_status 2154 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2155 size_t ntrb, size_t align) 2156 { 2157 usbd_status err; 2158 size_t size = ntrb * XHCI_TRB_SIZE; 2159 2160 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2161 2162 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2163 if (err) 2164 return err; 2165 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2166 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2167 xr->xr_trb = xhci_ring_trbv(xr, 0); 2168 xr->xr_ntrb = ntrb; 2169 xr->xr_ep = 0; 2170 xr->xr_cs = 1; 2171 memset(xr->xr_trb, 0, size); 2172 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 2173 xr->is_halted = false; 2174 2175 return USBD_NORMAL_COMPLETION; 2176 } 2177 2178 static void 2179 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2180 { 2181 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2182 mutex_destroy(&xr->xr_lock); 2183 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2184 } 2185 2186 static void 2187 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2188 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2189 { 2190 size_t i; 2191 u_int ri; 2192 u_int cs; 2193 uint64_t parameter; 2194 uint32_t status; 2195 uint32_t control; 2196 2197 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2198 2199 for (i = 0; i < ntrbs; i++) { 2200 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2201 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2202 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2203 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2204 XHCI_TRB_TYPE_LINK); 2205 } 2206 2207 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2208 2209 ri = xr->xr_ep; 2210 cs = xr->xr_cs; 2211 2212 /* 2213 * Although the xhci hardware can do scatter/gather dma from 2214 * arbitrary sized buffers, there is a non-obvious restriction 2215 * that a LINK trb is only allowed at the end of a burst of 2216 * transfers - which might be 16kB. 2217 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2218 * The simple solution is not to allow a LINK trb in the middle 2219 * of anything - as here. 2220 * XXX: (dsl) There are xhci controllers out there (eg some made by 2221 * ASMedia) that seem to lock up if they process a LINK trb but 2222 * cannot process the linked-to trb yet. 2223 * The code should write the 'cycle' bit on the link trb AFTER 2224 * adding the other trb. 2225 */ 2226 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2227 parameter = xhci_ring_trbp(xr, 0); 2228 status = 0; 2229 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2230 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2231 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 2232 htole32(status), htole32(control)); 2233 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2234 BUS_DMASYNC_PREWRITE); 2235 xr->xr_cookies[ri] = NULL; 2236 xr->xr_ep = 0; 2237 xr->xr_cs ^= 1; 2238 ri = xr->xr_ep; 2239 cs = xr->xr_cs; 2240 } 2241 2242 ri++; 2243 2244 /* Write any subsequent TRB first */ 2245 for (i = 1; i < ntrbs; i++) { 2246 parameter = trbs[i].trb_0; 2247 status = trbs[i].trb_2; 2248 control = trbs[i].trb_3; 2249 2250 if (cs) { 2251 control |= XHCI_TRB_3_CYCLE_BIT; 2252 } else { 2253 control &= ~XHCI_TRB_3_CYCLE_BIT; 2254 } 2255 2256 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 2257 htole32(status), htole32(control)); 2258 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2259 BUS_DMASYNC_PREWRITE); 2260 xr->xr_cookies[ri] = cookie; 2261 ri++; 2262 } 2263 2264 /* Write the first TRB last */ 2265 i = 0; 2266 parameter = trbs[i].trb_0; 2267 status = trbs[i].trb_2; 2268 control = trbs[i].trb_3; 2269 2270 if (xr->xr_cs) { 2271 control |= XHCI_TRB_3_CYCLE_BIT; 2272 } else { 2273 control &= ~XHCI_TRB_3_CYCLE_BIT; 2274 } 2275 2276 xhci_trb_put(&xr->xr_trb[xr->xr_ep], htole64(parameter), 2277 htole32(status), htole32(control)); 2278 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2279 BUS_DMASYNC_PREWRITE); 2280 xr->xr_cookies[xr->xr_ep] = cookie; 2281 2282 xr->xr_ep = ri; 2283 xr->xr_cs = cs; 2284 2285 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2286 } 2287 2288 /* 2289 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2290 * Command completion is notified by cv_signal from xhci_handle_event 2291 * (called from interrupt from xHCI), or timed-out. 2292 * Command validation is performed in xhci_handle_event by checking if 2293 * trb_0 in CMD_COMPLETE TRB and sc->sc_command_addr are identical. 2294 */ 2295 static usbd_status 2296 xhci_do_command1(struct xhci_softc * const sc, struct xhci_trb * const trb, 2297 int timeout, int locked) 2298 { 2299 struct xhci_ring * const cr = &sc->sc_cr; 2300 usbd_status err; 2301 2302 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2303 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2304 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2305 2306 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2307 2308 if (!locked) 2309 mutex_enter(&sc->sc_lock); 2310 2311 /* XXX KASSERT may fire when cv_timedwait unlocks sc_lock */ 2312 KASSERT(sc->sc_command_addr == 0); 2313 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2314 2315 mutex_enter(&cr->xr_lock); 2316 xhci_ring_put(sc, cr, NULL, trb, 1); 2317 mutex_exit(&cr->xr_lock); 2318 2319 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2320 2321 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2322 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2323 err = USBD_TIMEOUT; 2324 goto timedout; 2325 } 2326 2327 trb->trb_0 = sc->sc_result_trb.trb_0; 2328 trb->trb_2 = sc->sc_result_trb.trb_2; 2329 trb->trb_3 = sc->sc_result_trb.trb_3; 2330 2331 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2332 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2333 2334 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2335 case XHCI_TRB_ERROR_SUCCESS: 2336 err = USBD_NORMAL_COMPLETION; 2337 break; 2338 default: 2339 case 192 ... 223: 2340 err = USBD_IOERROR; 2341 break; 2342 case 224 ... 255: 2343 err = USBD_NORMAL_COMPLETION; 2344 break; 2345 } 2346 2347 timedout: 2348 sc->sc_command_addr = 0; 2349 if (!locked) 2350 mutex_exit(&sc->sc_lock); 2351 return err; 2352 } 2353 2354 static usbd_status 2355 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2356 int timeout) 2357 { 2358 return xhci_do_command1(sc, trb, timeout, 0); 2359 } 2360 2361 /* 2362 * This allows xhci_do_command with already sc_lock held. 2363 * This is needed as USB stack calls close methods with sc_lock_held. 2364 * (see usbdivar.h) 2365 */ 2366 static usbd_status 2367 xhci_do_command_locked(struct xhci_softc * const sc, 2368 struct xhci_trb * const trb, int timeout) 2369 { 2370 return xhci_do_command1(sc, trb, timeout, 1); 2371 } 2372 2373 static usbd_status 2374 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2375 { 2376 struct xhci_trb trb; 2377 usbd_status err; 2378 2379 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2380 2381 trb.trb_0 = 0; 2382 trb.trb_2 = 0; 2383 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2384 2385 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2386 if (err != USBD_NORMAL_COMPLETION) { 2387 return err; 2388 } 2389 2390 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2391 2392 return err; 2393 } 2394 2395 /* 2396 * Deallocate DMA buffer and ring buffer, and disable_slot. 2397 * Should be called with sc_lock held. 2398 */ 2399 static usbd_status 2400 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2401 { 2402 struct xhci_trb trb; 2403 struct xhci_slot *xs; 2404 2405 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2406 2407 if (sc->sc_dying) 2408 return USBD_IOERROR; 2409 2410 xs = &sc->sc_slots[slot]; 2411 if (xs->xs_idx != 0) { 2412 for (int i = XHCI_DCI_SLOT + 1; i < 32; i++) { 2413 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2414 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2415 } 2416 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2417 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2418 } 2419 2420 trb.trb_0 = 0; 2421 trb.trb_2 = 0; 2422 trb.trb_3 = htole32( 2423 XHCI_TRB_3_SLOT_SET(slot) | 2424 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2425 2426 return xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2427 } 2428 2429 /* 2430 * Change slot state. 2431 * bsr=0: ENABLED -> ADDRESSED 2432 * bsr=1: ENABLED -> DEFAULT 2433 * see xHCI 1.1 4.5.3, 3.3.4 2434 */ 2435 static usbd_status 2436 xhci_address_device(struct xhci_softc * const sc, 2437 uint64_t icp, uint8_t slot_id, bool bsr) 2438 { 2439 struct xhci_trb trb; 2440 usbd_status err; 2441 2442 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2443 2444 trb.trb_0 = icp; 2445 trb.trb_2 = 0; 2446 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2447 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2448 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2449 2450 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2451 return err; 2452 } 2453 2454 static usbd_status 2455 xhci_update_ep0_mps(struct xhci_softc * const sc, 2456 struct xhci_slot * const xs, u_int mps) 2457 { 2458 struct xhci_trb trb; 2459 usbd_status err; 2460 uint32_t * cp; 2461 2462 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2463 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2464 2465 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2466 cp[0] = htole32(0); 2467 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2468 2469 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2470 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2471 2472 /* sync input contexts before they are read from memory */ 2473 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2474 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2475 sc->sc_ctxsz * 4); 2476 2477 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2478 trb.trb_2 = 0; 2479 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2480 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2481 2482 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2483 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2484 return err; 2485 } 2486 2487 static void 2488 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2489 { 2490 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2491 2492 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2493 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2494 &dcbaa[si], dcba, si, 0); 2495 2496 dcbaa[si] = htole64(dcba); 2497 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2498 BUS_DMASYNC_PREWRITE); 2499 } 2500 2501 /* 2502 * Allocate DMA buffer and ring buffer for specified slot 2503 * and set Device Context Base Address 2504 * and issue Set Address device command. 2505 */ 2506 static usbd_status 2507 xhci_init_slot(struct usbd_device *dev, uint32_t slot, int route, int rhport) 2508 { 2509 struct xhci_softc * const sc = dev->ud_bus->ub_hcpriv; 2510 struct xhci_slot *xs; 2511 usbd_status err; 2512 u_int dci; 2513 uint32_t *cp; 2514 uint32_t mps = UGETW(dev->ud_ep0desc.wMaxPacketSize); 2515 2516 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2517 DPRINTFN(4, "slot %u speed %d rhport %d route %05x", 2518 slot, dev->ud_speed, route, rhport); 2519 2520 xs = &sc->sc_slots[slot]; 2521 2522 /* allocate contexts */ 2523 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2524 &xs->xs_dc_dma); 2525 if (err) 2526 return err; 2527 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2528 2529 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2530 &xs->xs_ic_dma); 2531 if (err) 2532 goto bad1; 2533 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2534 2535 for (dci = 0; dci < 32; dci++) { 2536 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2537 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2538 if (dci == XHCI_DCI_SLOT) 2539 continue; 2540 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2541 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2542 if (err) { 2543 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2544 goto bad2; 2545 } 2546 } 2547 2548 /* set up initial input control context */ 2549 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2550 cp[0] = htole32(0); 2551 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 2552 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2553 2554 /* set up input slot context */ 2555 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2556 xhci_setup_sctx(dev, cp); 2557 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(1)); 2558 cp[0] |= htole32(XHCI_SCTX_0_ROUTE_SET(route)); 2559 cp[1] |= htole32(XHCI_SCTX_1_RH_PORT_SET(rhport)); 2560 2561 /* set up input EP0 context */ 2562 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2563 cp[0] = htole32(0); 2564 cp[1] = htole32( 2565 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 2566 XHCI_EPCTX_1_EPTYPE_SET(4) | 2567 XHCI_EPCTX_1_CERR_SET(3) 2568 ); 2569 /* can't use xhci_ep_get_dci() yet? */ 2570 *(uint64_t *)(&cp[2]) = htole64( 2571 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 2572 XHCI_EPCTX_2_DCS_SET(1)); 2573 cp[4] = htole32( 2574 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 2575 ); 2576 2577 /* sync input contexts before they are read from memory */ 2578 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2579 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2580 sc->sc_ctxsz * 3); 2581 2582 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2583 2584 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 2585 false); 2586 2587 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2588 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2589 sc->sc_ctxsz * 2); 2590 2591 bad2: 2592 if (err == USBD_NORMAL_COMPLETION) { 2593 xs->xs_idx = slot; 2594 } else { 2595 for (int i = 1; i < dci; i++) { 2596 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2597 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2598 } 2599 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2600 bad1: 2601 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2602 xs->xs_idx = 0; 2603 } 2604 2605 return err; 2606 } 2607 2608 /* ----- */ 2609 2610 static void 2611 xhci_noop(struct usbd_pipe *pipe) 2612 { 2613 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2614 } 2615 2616 /* 2617 * Process root hub request. 2618 */ 2619 static int 2620 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2621 void *buf, int buflen) 2622 { 2623 struct xhci_softc * const sc = bus->ub_hcpriv; 2624 usb_port_status_t ps; 2625 int l, totlen = 0; 2626 uint16_t len, value, index; 2627 int port, i; 2628 uint32_t v; 2629 2630 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2631 2632 if (sc->sc_dying) 2633 return -1; 2634 2635 len = UGETW(req->wLength); 2636 value = UGETW(req->wValue); 2637 index = UGETW(req->wIndex); 2638 2639 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 2640 req->bmRequestType | (req->bRequest << 8), value, index, len); 2641 2642 #define C(x,y) ((x) | ((y) << 8)) 2643 switch (C(req->bRequest, req->bmRequestType)) { 2644 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2645 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 2646 if (len == 0) 2647 break; 2648 switch (value) { 2649 #define sd ((usb_string_descriptor_t *)buf) 2650 case C(2, UDESC_STRING): 2651 /* Product */ 2652 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 2653 break; 2654 #undef sd 2655 default: 2656 /* default from usbroothub */ 2657 return buflen; 2658 } 2659 break; 2660 2661 /* Hub requests */ 2662 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2663 break; 2664 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2665 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2666 index, value, 0, 0); 2667 if (index < 1 || index > sc->sc_maxports) { 2668 return -1; 2669 } 2670 port = XHCI_PORTSC(index); 2671 v = xhci_op_read_4(sc, port); 2672 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2673 v &= ~XHCI_PS_CLEAR; 2674 switch (value) { 2675 case UHF_PORT_ENABLE: 2676 xhci_op_write_4(sc, port, v &~ XHCI_PS_PED); 2677 break; 2678 case UHF_PORT_SUSPEND: 2679 return -1; 2680 case UHF_PORT_POWER: 2681 break; 2682 case UHF_PORT_TEST: 2683 case UHF_PORT_INDICATOR: 2684 return -1; 2685 case UHF_C_PORT_CONNECTION: 2686 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2687 break; 2688 case UHF_C_PORT_ENABLE: 2689 case UHF_C_PORT_SUSPEND: 2690 case UHF_C_PORT_OVER_CURRENT: 2691 return -1; 2692 case UHF_C_BH_PORT_RESET: 2693 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 2694 break; 2695 case UHF_C_PORT_RESET: 2696 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2697 break; 2698 case UHF_C_PORT_LINK_STATE: 2699 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 2700 break; 2701 case UHF_C_PORT_CONFIG_ERROR: 2702 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 2703 break; 2704 default: 2705 return -1; 2706 } 2707 break; 2708 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2709 if (len == 0) 2710 break; 2711 if ((value & 0xff) != 0) { 2712 return -1; 2713 } 2714 usb_hub_descriptor_t hubd; 2715 2716 totlen = min(buflen, sizeof(hubd)); 2717 memcpy(&hubd, buf, totlen); 2718 hubd.bNbrPorts = sc->sc_maxports; 2719 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2720 hubd.bPwrOn2PwrGood = 200; 2721 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 2722 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2723 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2724 totlen = min(totlen, hubd.bDescLength); 2725 memcpy(buf, &hubd, totlen); 2726 break; 2727 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2728 if (len != 4) { 2729 return -1; 2730 } 2731 memset(buf, 0, len); /* ? XXX */ 2732 totlen = len; 2733 break; 2734 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2735 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2736 if (index < 1 || index > sc->sc_maxports) { 2737 return -1; 2738 } 2739 if (len != 4) { 2740 return -1; 2741 } 2742 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 2743 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 2744 switch (XHCI_PS_SPEED_GET(v)) { 2745 case 1: 2746 i = UPS_FULL_SPEED; 2747 break; 2748 case 2: 2749 i = UPS_LOW_SPEED; 2750 break; 2751 case 3: 2752 i = UPS_HIGH_SPEED; 2753 break; 2754 case 4: 2755 i = UPS_SUPER_SPEED; 2756 break; 2757 default: 2758 i = 0; 2759 break; 2760 } 2761 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2762 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2763 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2764 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 2765 if (v & XHCI_PS_PR) i |= UPS_RESET; 2766 if (v & XHCI_PS_PP) { 2767 if (i & UPS_SUPER_SPEED) 2768 i |= UPS_PORT_POWER_SS; 2769 else 2770 i |= UPS_PORT_POWER; 2771 } 2772 USETW(ps.wPortStatus, i); 2773 i = 0; 2774 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2775 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2776 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2777 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2778 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 2779 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 2780 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 2781 USETW(ps.wPortChange, i); 2782 totlen = min(len, sizeof(ps)); 2783 memcpy(buf, &ps, totlen); 2784 break; 2785 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2786 return -1; 2787 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 2788 break; 2789 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2790 break; 2791 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 2792 int optval = (index >> 8) & 0xff; 2793 index &= 0xff; 2794 if (index < 1 || index > sc->sc_maxports) { 2795 return -1; 2796 } 2797 port = XHCI_PORTSC(index); 2798 v = xhci_op_read_4(sc, port); 2799 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2800 v &= ~XHCI_PS_CLEAR; 2801 switch (value) { 2802 case UHF_PORT_ENABLE: 2803 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 2804 break; 2805 case UHF_PORT_SUSPEND: 2806 /* XXX suspend */ 2807 break; 2808 case UHF_PORT_RESET: 2809 v &= ~ (XHCI_PS_PED | XHCI_PS_PR); 2810 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 2811 /* Wait for reset to complete. */ 2812 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2813 if (sc->sc_dying) { 2814 return -1; 2815 } 2816 v = xhci_op_read_4(sc, port); 2817 if (v & XHCI_PS_PR) { 2818 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 2819 usb_delay_ms(&sc->sc_bus, 10); 2820 /* XXX */ 2821 } 2822 break; 2823 case UHF_PORT_POWER: 2824 /* XXX power control */ 2825 break; 2826 /* XXX more */ 2827 case UHF_C_PORT_RESET: 2828 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2829 break; 2830 case UHF_PORT_U1_TIMEOUT: 2831 if (XHCI_PS_SPEED_GET(v) != 4) { 2832 return -1; 2833 } 2834 port = XHCI_PORTPMSC(index); 2835 v = xhci_op_read_4(sc, port); 2836 v &= ~XHCI_PM3_U1TO_SET(0xff); 2837 v |= XHCI_PM3_U1TO_SET(optval); 2838 xhci_op_write_4(sc, port, v); 2839 break; 2840 case UHF_PORT_U2_TIMEOUT: 2841 if (XHCI_PS_SPEED_GET(v) != 4) { 2842 return -1; 2843 } 2844 port = XHCI_PORTPMSC(index); 2845 v = xhci_op_read_4(sc, port); 2846 v &= ~XHCI_PM3_U2TO_SET(0xff); 2847 v |= XHCI_PM3_U2TO_SET(optval); 2848 xhci_op_write_4(sc, port, v); 2849 break; 2850 default: 2851 return -1; 2852 } 2853 } 2854 break; 2855 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2856 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2857 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2858 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2859 break; 2860 default: 2861 /* default from usbroothub */ 2862 return buflen; 2863 } 2864 2865 return totlen; 2866 } 2867 2868 /* root hub interrupt */ 2869 2870 static usbd_status 2871 xhci_root_intr_transfer(struct usbd_xfer *xfer) 2872 { 2873 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2874 usbd_status err; 2875 2876 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2877 2878 /* Insert last in queue. */ 2879 mutex_enter(&sc->sc_lock); 2880 err = usb_insert_transfer(xfer); 2881 mutex_exit(&sc->sc_lock); 2882 if (err) 2883 return err; 2884 2885 /* Pipe isn't running, start first */ 2886 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2887 } 2888 2889 /* Wait for roothub port status/change */ 2890 static usbd_status 2891 xhci_root_intr_start(struct usbd_xfer *xfer) 2892 { 2893 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2894 2895 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2896 2897 if (sc->sc_dying) 2898 return USBD_IOERROR; 2899 2900 mutex_enter(&sc->sc_lock); 2901 sc->sc_intrxfer = xfer; 2902 mutex_exit(&sc->sc_lock); 2903 2904 return USBD_IN_PROGRESS; 2905 } 2906 2907 static void 2908 xhci_root_intr_abort(struct usbd_xfer *xfer) 2909 { 2910 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2911 2912 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2913 2914 KASSERT(mutex_owned(&sc->sc_lock)); 2915 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2916 2917 sc->sc_intrxfer = NULL; 2918 2919 xfer->ux_status = USBD_CANCELLED; 2920 usb_transfer_complete(xfer); 2921 } 2922 2923 static void 2924 xhci_root_intr_close(struct usbd_pipe *pipe) 2925 { 2926 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 2927 2928 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2929 2930 KASSERT(mutex_owned(&sc->sc_lock)); 2931 2932 sc->sc_intrxfer = NULL; 2933 } 2934 2935 static void 2936 xhci_root_intr_done(struct usbd_xfer *xfer) 2937 { 2938 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2939 2940 xfer->ux_hcpriv = NULL; 2941 } 2942 2943 /* -------------- */ 2944 /* device control */ 2945 2946 static usbd_status 2947 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2948 { 2949 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2950 usbd_status err; 2951 2952 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2953 2954 /* Insert last in queue. */ 2955 mutex_enter(&sc->sc_lock); 2956 err = usb_insert_transfer(xfer); 2957 mutex_exit(&sc->sc_lock); 2958 if (err) 2959 return err; 2960 2961 /* Pipe isn't running, start first */ 2962 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2963 } 2964 2965 static usbd_status 2966 xhci_device_ctrl_start(struct usbd_xfer *xfer) 2967 { 2968 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2969 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 2970 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 2971 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2972 struct xhci_xfer * const xx = (void *)xfer; 2973 usb_device_request_t * const req = &xfer->ux_request; 2974 const bool isread = UT_GET_DIR(req->bmRequestType) == UT_READ; 2975 const uint32_t len = UGETW(req->wLength); 2976 usb_dma_t * const dma = &xfer->ux_dmabuf; 2977 uint64_t parameter; 2978 uint32_t status; 2979 uint32_t control; 2980 u_int i; 2981 2982 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2983 DPRINTFN(12, "req: %04x %04x %04x %04x", 2984 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 2985 UGETW(req->wIndex), UGETW(req->wLength)); 2986 2987 /* XXX */ 2988 if (tr->is_halted) { 2989 DPRINTFN(1, "ctrl xfer %p halted: slot %u dci %u", 2990 xfer, xs->xs_idx, dci, 0); 2991 xhci_reset_endpoint(xfer->ux_pipe); 2992 tr->is_halted = false; 2993 xhci_set_dequeue(xfer->ux_pipe); 2994 } 2995 2996 /* we rely on the bottom bits for extra info */ 2997 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 2998 2999 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3000 3001 i = 0; 3002 3003 /* setup phase */ 3004 memcpy(¶meter, req, sizeof(*req)); 3005 parameter = le64toh(parameter); 3006 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3007 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3008 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3009 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3010 XHCI_TRB_3_IDT_BIT; 3011 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3012 3013 if (len == 0) 3014 goto no_data; 3015 3016 /* data phase */ 3017 parameter = DMAADDR(dma, 0); 3018 KASSERT(len <= 0x10000); 3019 status = XHCI_TRB_2_IRQ_SET(0) | 3020 XHCI_TRB_2_TDSZ_SET(1) | 3021 XHCI_TRB_2_BYTES_SET(len); 3022 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3023 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3024 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3025 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3026 3027 parameter = (uintptr_t)xfer | 0x3; 3028 status = XHCI_TRB_2_IRQ_SET(0); 3029 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3030 XHCI_TRB_3_IOC_BIT; 3031 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3032 3033 no_data: 3034 parameter = 0; 3035 status = XHCI_TRB_2_IRQ_SET(0); 3036 /* the status stage has inverted direction */ 3037 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3038 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3039 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3040 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3041 3042 parameter = (uintptr_t)xfer | 0x0; 3043 status = XHCI_TRB_2_IRQ_SET(0); 3044 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3045 XHCI_TRB_3_IOC_BIT; 3046 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3047 3048 mutex_enter(&tr->xr_lock); 3049 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3050 mutex_exit(&tr->xr_lock); 3051 3052 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3053 3054 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3055 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3056 xhci_timeout, xfer); 3057 } 3058 3059 if (sc->sc_bus.ub_usepolling) { 3060 DPRINTFN(1, "polling", 0, 0, 0, 0); 3061 //xhci_waitintr(sc, xfer); 3062 } 3063 3064 return USBD_IN_PROGRESS; 3065 } 3066 3067 static void 3068 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3069 { 3070 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3071 3072 callout_stop(&xfer->ux_callout); /* XXX wrong place */ 3073 3074 } 3075 3076 static void 3077 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3078 { 3079 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3080 3081 xhci_abort_xfer(xfer, USBD_CANCELLED); 3082 } 3083 3084 static void 3085 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3086 { 3087 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3088 3089 (void)xhci_close_pipe(pipe); 3090 } 3091 3092 /* ------------------ */ 3093 /* device isochronous */ 3094 3095 /* ----------- */ 3096 /* device bulk */ 3097 3098 static usbd_status 3099 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3100 { 3101 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3102 usbd_status err; 3103 3104 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3105 3106 /* Insert last in queue. */ 3107 mutex_enter(&sc->sc_lock); 3108 err = usb_insert_transfer(xfer); 3109 mutex_exit(&sc->sc_lock); 3110 if (err) 3111 return err; 3112 3113 /* 3114 * Pipe isn't running (otherwise err would be USBD_INPROG), 3115 * so start it first. 3116 */ 3117 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3118 } 3119 3120 static usbd_status 3121 xhci_device_bulk_start(struct usbd_xfer *xfer) 3122 { 3123 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3124 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3125 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3126 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3127 struct xhci_xfer * const xx = (void *)xfer; 3128 const uint32_t len = xfer->ux_length; 3129 usb_dma_t * const dma = &xfer->ux_dmabuf; 3130 uint64_t parameter; 3131 uint32_t status; 3132 uint32_t control; 3133 u_int i = 0; 3134 3135 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3136 3137 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3138 3139 if (sc->sc_dying) 3140 return USBD_IOERROR; 3141 3142 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3143 3144 parameter = DMAADDR(dma, 0); 3145 /* 3146 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3147 * If the user supplied buffer crosses such a boundary then 2 3148 * (or more) TRB should be used. 3149 * If multiple TRB are used the td_size field must be set correctly. 3150 * For v1.0 devices (like ivy bridge) this is the number of usb data 3151 * blocks needed to complete the transfer. 3152 * Setting it to 1 in the last TRB causes an extra zero-length 3153 * data block be sent. 3154 * The earlier documentation differs, I don't know how it behaves. 3155 */ 3156 KASSERT(len <= 0x10000); 3157 status = XHCI_TRB_2_IRQ_SET(0) | 3158 XHCI_TRB_2_TDSZ_SET(1) | 3159 XHCI_TRB_2_BYTES_SET(len); 3160 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3161 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3162 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3163 3164 mutex_enter(&tr->xr_lock); 3165 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3166 mutex_exit(&tr->xr_lock); 3167 3168 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3169 3170 if (sc->sc_bus.ub_usepolling) { 3171 DPRINTFN(1, "polling", 0, 0, 0, 0); 3172 //xhci_waitintr(sc, xfer); 3173 } 3174 3175 return USBD_IN_PROGRESS; 3176 } 3177 3178 static void 3179 xhci_device_bulk_done(struct usbd_xfer *xfer) 3180 { 3181 #ifdef USB_DEBUG 3182 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3183 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3184 #endif 3185 const u_int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3186 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3187 3188 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3189 3190 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3191 3192 callout_stop(&xfer->ux_callout); /* XXX wrong place */ 3193 3194 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3195 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3196 } 3197 3198 static void 3199 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3200 { 3201 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3202 3203 xhci_abort_xfer(xfer, USBD_CANCELLED); 3204 } 3205 3206 static void 3207 xhci_device_bulk_close(struct usbd_pipe *pipe) 3208 { 3209 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3210 3211 (void)xhci_close_pipe(pipe); 3212 } 3213 3214 /* ---------------- */ 3215 /* device interrupt */ 3216 3217 static usbd_status 3218 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3219 { 3220 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3221 usbd_status err; 3222 3223 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3224 3225 /* Insert last in queue. */ 3226 mutex_enter(&sc->sc_lock); 3227 err = usb_insert_transfer(xfer); 3228 mutex_exit(&sc->sc_lock); 3229 if (err) 3230 return err; 3231 3232 /* 3233 * Pipe isn't running (otherwise err would be USBD_INPROG), 3234 * so start it first. 3235 */ 3236 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3237 } 3238 3239 static usbd_status 3240 xhci_device_intr_start(struct usbd_xfer *xfer) 3241 { 3242 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3243 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3244 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3245 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3246 struct xhci_xfer * const xx = (void *)xfer; 3247 const uint32_t len = xfer->ux_length; 3248 usb_dma_t * const dma = &xfer->ux_dmabuf; 3249 uint64_t parameter; 3250 uint32_t status; 3251 uint32_t control; 3252 u_int i = 0; 3253 3254 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3255 3256 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3257 3258 if (sc->sc_dying) 3259 return USBD_IOERROR; 3260 3261 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3262 3263 parameter = DMAADDR(dma, 0); 3264 KASSERT(len <= 0x10000); 3265 status = XHCI_TRB_2_IRQ_SET(0) | 3266 XHCI_TRB_2_TDSZ_SET(1) | 3267 XHCI_TRB_2_BYTES_SET(len); 3268 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3269 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3270 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3271 3272 mutex_enter(&tr->xr_lock); 3273 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3274 mutex_exit(&tr->xr_lock); 3275 3276 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3277 3278 if (sc->sc_bus.ub_usepolling) { 3279 DPRINTFN(1, "polling", 0, 0, 0, 0); 3280 //xhci_waitintr(sc, xfer); 3281 } 3282 3283 return USBD_IN_PROGRESS; 3284 } 3285 3286 static void 3287 xhci_device_intr_done(struct usbd_xfer *xfer) 3288 { 3289 struct xhci_softc * const sc __diagused = 3290 xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3291 #ifdef USB_DEBUG 3292 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3293 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3294 #endif 3295 const u_int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3296 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3297 3298 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3299 3300 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3301 3302 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3303 3304 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3305 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3306 3307 #if 0 3308 device_printf(sc->sc_dev, ""); 3309 for (size_t i = 0; i < xfer->ux_length; i++) { 3310 printf(" %02x", ((uint8_t const *)xfer->ux_buffer)[i]); 3311 } 3312 printf("\n"); 3313 #endif 3314 3315 if (xfer->ux_pipe->up_repeat) { 3316 xfer->ux_status = xhci_device_intr_start(xfer); 3317 } else { 3318 callout_stop(&xfer->ux_callout); /* XXX */ 3319 } 3320 3321 } 3322 3323 static void 3324 xhci_device_intr_abort(struct usbd_xfer *xfer) 3325 { 3326 struct xhci_softc * const sc __diagused = 3327 xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3328 3329 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3330 3331 KASSERT(mutex_owned(&sc->sc_lock)); 3332 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3333 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3334 xhci_abort_xfer(xfer, USBD_CANCELLED); 3335 } 3336 3337 static void 3338 xhci_device_intr_close(struct usbd_pipe *pipe) 3339 { 3340 //struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 3341 3342 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3343 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3344 3345 (void)xhci_close_pipe(pipe); 3346 } 3347 3348 /* ------------ */ 3349 3350 static void 3351 xhci_timeout(void *addr) 3352 { 3353 struct xhci_xfer * const xx = addr; 3354 struct usbd_xfer * const xfer = &xx->xx_xfer; 3355 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3356 3357 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3358 3359 if (sc->sc_dying) { 3360 return; 3361 } 3362 3363 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 3364 USB_TASKQ_MPSAFE); 3365 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 3366 USB_TASKQ_HC); 3367 } 3368 3369 static void 3370 xhci_timeout_task(void *addr) 3371 { 3372 struct usbd_xfer * const xfer = addr; 3373 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3374 3375 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3376 3377 mutex_enter(&sc->sc_lock); 3378 #if 0 3379 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3380 #else 3381 xfer->ux_status = USBD_TIMEOUT; 3382 usb_transfer_complete(xfer); 3383 #endif 3384 mutex_exit(&sc->sc_lock); 3385 } 3386
Indexes created Wed Oct 01 18:09:54 GMT 2025