xhci.c revision 1.28.2.25
1 /* $NetBSD: xhci.c,v 1.28.2.25 2015/05/27 07:08:16 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 3.1 specification 31 * http://www.usb.org/developers/docs/usb_31_040315.zip 32 * USB rev 2.0 specification 33 * http://www.usb.org/developers/docs/usb20_docs/usb_20_031815.zip 34 * xHCI rev 1.1 specification 35 * http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.28.2.25 2015/05/27 07:08:16 skrll Exp $"); 40 41 #include "opt_usb.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static int xhci_intr1(struct xhci_softc * const); 129 static void xhci_softintr(void *); 130 static void xhci_poll(struct usbd_bus *); 131 static struct usbd_xfer *xhci_allocx(struct usbd_bus *); 132 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 133 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 134 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 135 struct usbd_port *); 136 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 137 void *, int); 138 139 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 140 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 141 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 143 144 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 145 146 static usbd_status xhci_do_command(struct xhci_softc * const, 147 struct xhci_trb * const, int); 148 static usbd_status xhci_do_command1(struct xhci_softc * const, 149 struct xhci_trb * const, int, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t, int, int); 153 static usbd_status xhci_enable_slot(struct xhci_softc * const, 154 uint8_t * const); 155 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 156 static usbd_status xhci_address_device(struct xhci_softc * const, 157 uint64_t, uint8_t, bool); 158 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 159 struct xhci_slot * const, u_int); 160 static usbd_status xhci_ring_init(struct xhci_softc * const, 161 struct xhci_ring * const, size_t, size_t); 162 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 163 164 static void xhci_noop(struct usbd_pipe *); 165 166 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 167 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 168 static void xhci_root_intr_abort(struct usbd_xfer *); 169 static void xhci_root_intr_close(struct usbd_pipe *); 170 static void xhci_root_intr_done(struct usbd_xfer *); 171 172 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 173 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 174 static void xhci_device_ctrl_abort(struct usbd_xfer *); 175 static void xhci_device_ctrl_close(struct usbd_pipe *); 176 static void xhci_device_ctrl_done(struct usbd_xfer *); 177 178 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 179 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 180 static void xhci_device_intr_abort(struct usbd_xfer *); 181 static void xhci_device_intr_close(struct usbd_pipe *); 182 static void xhci_device_intr_done(struct usbd_xfer *); 183 184 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 185 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 186 static void xhci_device_bulk_abort(struct usbd_xfer *); 187 static void xhci_device_bulk_close(struct usbd_pipe *); 188 static void xhci_device_bulk_done(struct usbd_xfer *); 189 190 static void xhci_timeout(void *); 191 static void xhci_timeout_task(void *); 192 193 static const struct usbd_bus_methods xhci_bus_methods = { 194 .ubm_open = xhci_open, 195 .ubm_softint = xhci_softintr, 196 .ubm_dopoll = xhci_poll, 197 .ubm_allocx = xhci_allocx, 198 .ubm_freex = xhci_freex, 199 .ubm_getlock = xhci_get_lock, 200 .ubm_newdev = xhci_new_device, 201 .ubm_rhctrl = xhci_roothub_ctrl, 202 }; 203 204 static const struct usbd_pipe_methods xhci_root_intr_methods = { 205 .upm_transfer = xhci_root_intr_transfer, 206 .upm_start = xhci_root_intr_start, 207 .upm_abort = xhci_root_intr_abort, 208 .upm_close = xhci_root_intr_close, 209 .upm_cleartoggle = xhci_noop, 210 .upm_done = xhci_root_intr_done, 211 }; 212 213 214 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 215 .upm_transfer = xhci_device_ctrl_transfer, 216 .upm_start = xhci_device_ctrl_start, 217 .upm_abort = xhci_device_ctrl_abort, 218 .upm_close = xhci_device_ctrl_close, 219 .upm_cleartoggle = xhci_noop, 220 .upm_done = xhci_device_ctrl_done, 221 }; 222 223 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 224 .upm_cleartoggle = xhci_noop, 225 }; 226 227 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 228 .upm_transfer = xhci_device_bulk_transfer, 229 .upm_start = xhci_device_bulk_start, 230 .upm_abort = xhci_device_bulk_abort, 231 .upm_close = xhci_device_bulk_close, 232 .upm_cleartoggle = xhci_noop, 233 .upm_done = xhci_device_bulk_done, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_intr_methods = { 237 .upm_transfer = xhci_device_intr_transfer, 238 .upm_start = xhci_device_intr_start, 239 .upm_abort = xhci_device_intr_abort, 240 .upm_close = xhci_device_intr_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_intr_done, 243 }; 244 245 static inline uint32_t 246 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 247 { 248 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 249 } 250 251 static inline uint32_t 252 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 253 { 254 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 255 } 256 257 static inline void 258 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 259 uint32_t value) 260 { 261 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 262 } 263 264 #if 0 /* unused */ 265 static inline void 266 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 267 uint32_t value) 268 { 269 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 270 } 271 #endif /* unused */ 272 273 static inline uint32_t 274 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 275 { 276 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 277 } 278 279 static inline uint32_t 280 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 281 { 282 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 283 } 284 285 static inline void 286 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 287 uint32_t value) 288 { 289 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 290 } 291 292 #if 0 /* unused */ 293 static inline uint64_t 294 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 295 { 296 uint64_t value; 297 298 if (sc->sc_ac64) { 299 #ifdef XHCI_USE_BUS_SPACE_8 300 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 301 #else 302 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 303 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 304 offset + 4) << 32; 305 #endif 306 } else { 307 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 308 } 309 310 return value; 311 } 312 #endif /* unused */ 313 314 static inline void 315 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 316 uint64_t value) 317 { 318 if (sc->sc_ac64) { 319 #ifdef XHCI_USE_BUS_SPACE_8 320 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 321 #else 322 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 323 (value >> 0) & 0xffffffff); 324 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 325 (value >> 32) & 0xffffffff); 326 #endif 327 } else { 328 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 329 } 330 } 331 332 static inline uint32_t 333 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 334 { 335 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 336 } 337 338 static inline void 339 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 340 uint32_t value) 341 { 342 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 343 } 344 345 #if 0 /* unused */ 346 static inline uint64_t 347 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 348 { 349 uint64_t value; 350 351 if (sc->sc_ac64) { 352 #ifdef XHCI_USE_BUS_SPACE_8 353 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 354 #else 355 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 356 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 357 offset + 4) << 32; 358 #endif 359 } else { 360 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 361 } 362 363 return value; 364 } 365 #endif /* unused */ 366 367 static inline void 368 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 369 uint64_t value) 370 { 371 if (sc->sc_ac64) { 372 #ifdef XHCI_USE_BUS_SPACE_8 373 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 374 #else 375 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 376 (value >> 0) & 0xffffffff); 377 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 378 (value >> 32) & 0xffffffff); 379 #endif 380 } else { 381 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 382 } 383 } 384 385 #if 0 /* unused */ 386 static inline uint32_t 387 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 388 { 389 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 390 } 391 #endif /* unused */ 392 393 static inline void 394 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 395 uint32_t value) 396 { 397 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 398 } 399 400 /* --- */ 401 402 static inline uint8_t 403 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 404 { 405 u_int eptype = 0; 406 407 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 408 case UE_CONTROL: 409 eptype = 0x0; 410 break; 411 case UE_ISOCHRONOUS: 412 eptype = 0x1; 413 break; 414 case UE_BULK: 415 eptype = 0x2; 416 break; 417 case UE_INTERRUPT: 418 eptype = 0x3; 419 break; 420 } 421 422 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 423 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 424 return eptype | 0x4; 425 else 426 return eptype; 427 } 428 429 static u_int 430 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 431 { 432 /* xHCI 1.0 section 4.5.1 */ 433 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 434 u_int in = 0; 435 436 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 437 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 438 in = 1; 439 440 return epaddr * 2 + in; 441 } 442 443 static inline u_int 444 xhci_dci_to_ici(const u_int i) 445 { 446 return i + 1; 447 } 448 449 static inline void * 450 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 451 const u_int dci) 452 { 453 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 454 } 455 456 #if 0 /* unused */ 457 static inline bus_addr_t 458 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 459 const u_int dci) 460 { 461 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 462 } 463 #endif /* unused */ 464 465 static inline void * 466 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 467 const u_int ici) 468 { 469 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 470 } 471 472 static inline bus_addr_t 473 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline struct xhci_trb * 480 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 481 { 482 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 483 } 484 485 static inline bus_addr_t 486 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 487 { 488 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 489 } 490 491 static inline void 492 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 493 uint32_t control) 494 { 495 trb->trb_0 = parameter; 496 trb->trb_2 = status; 497 trb->trb_3 = control; 498 } 499 500 /* --- */ 501 502 void 503 xhci_childdet(device_t self, device_t child) 504 { 505 struct xhci_softc * const sc = device_private(self); 506 507 KASSERT(sc->sc_child == child); 508 if (child == sc->sc_child) 509 sc->sc_child = NULL; 510 } 511 512 int 513 xhci_detach(struct xhci_softc *sc, int flags) 514 { 515 int rv = 0; 516 517 if (sc->sc_child != NULL) 518 rv = config_detach(sc->sc_child, flags); 519 520 if (rv != 0) 521 return rv; 522 523 /* XXX unconfigure/free slots */ 524 525 /* verify: */ 526 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 527 xhci_op_write_4(sc, XHCI_USBCMD, 0); 528 /* do we need to wait for stop? */ 529 530 xhci_op_write_8(sc, XHCI_CRCR, 0); 531 xhci_ring_free(sc, &sc->sc_cr); 532 cv_destroy(&sc->sc_command_cv); 533 534 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 535 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 536 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 537 xhci_ring_free(sc, &sc->sc_er); 538 539 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 540 541 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 542 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 543 544 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 545 546 mutex_destroy(&sc->sc_lock); 547 mutex_destroy(&sc->sc_intr_lock); 548 cv_destroy(&sc->sc_softwake_cv); 549 550 pool_cache_destroy(sc->sc_xferpool); 551 552 return rv; 553 } 554 555 int 556 xhci_activate(device_t self, enum devact act) 557 { 558 struct xhci_softc * const sc = device_private(self); 559 560 switch (act) { 561 case DVACT_DEACTIVATE: 562 sc->sc_dying = true; 563 return 0; 564 default: 565 return EOPNOTSUPP; 566 } 567 } 568 569 bool 570 xhci_suspend(device_t dv, const pmf_qual_t *qual) 571 { 572 return false; 573 } 574 575 bool 576 xhci_resume(device_t dv, const pmf_qual_t *qual) 577 { 578 return false; 579 } 580 581 bool 582 xhci_shutdown(device_t self, int flags) 583 { 584 return false; 585 } 586 587 588 static void 589 hexdump(const char *msg, const void *base, size_t len) 590 { 591 #if 0 592 size_t cnt; 593 const uint32_t *p; 594 extern paddr_t vtophys(vaddr_t); 595 596 p = base; 597 cnt = 0; 598 599 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 600 (void *)vtophys((vaddr_t)base)); 601 602 while (cnt < len) { 603 if (cnt % 16 == 0) 604 printf("%p: ", p); 605 else if (cnt % 8 == 0) 606 printf(" |"); 607 printf(" %08x", *p++); 608 cnt += 4; 609 if (cnt % 16 == 0) 610 printf("\n"); 611 } 612 #endif 613 } 614 615 616 int 617 xhci_init(struct xhci_softc *sc) 618 { 619 bus_size_t bsz; 620 uint32_t cap, hcs1, hcs2, hcc, dboff, rtsoff; 621 uint32_t ecp, ecr; 622 uint32_t usbcmd, usbsts, pagesize, config; 623 int i; 624 uint16_t hciversion; 625 uint8_t caplength; 626 627 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 628 629 /* XXX Low/Full/High speeds for now */ 630 sc->sc_bus.ub_revision = USBREV_2_0; 631 sc->sc_bus.ub_usedma = true; 632 633 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 634 caplength = XHCI_CAP_CAPLENGTH(cap); 635 hciversion = XHCI_CAP_HCIVERSION(cap); 636 637 if ((hciversion < 0x0096) || (hciversion > 0x0100)) { 638 aprint_normal_dev(sc->sc_dev, 639 "xHCI version %x.%x not known to be supported\n", 640 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 641 } else { 642 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 643 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 644 } 645 646 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 647 &sc->sc_cbh) != 0) { 648 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 649 return ENOMEM; 650 } 651 652 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 653 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 654 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 655 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 656 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 657 (void)xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 658 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 659 660 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 661 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 662 aprint_debug_dev(sc->sc_dev, "ac64 %d ctxsz %d\n", sc->sc_ac64, 663 sc->sc_ctxsz); 664 665 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 666 ecp = XHCI_HCC_XECP(hcc) * 4; 667 while (ecp != 0) { 668 ecr = xhci_read_4(sc, ecp); 669 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 670 switch (XHCI_XECP_ID(ecr)) { 671 case XHCI_ID_PROTOCOLS: { 672 uint32_t w0, w4, w8; 673 uint16_t w2; 674 w0 = xhci_read_4(sc, ecp + 0); 675 w2 = (w0 >> 16) & 0xffff; 676 w4 = xhci_read_4(sc, ecp + 4); 677 w8 = xhci_read_4(sc, ecp + 8); 678 aprint_debug_dev(sc->sc_dev, "SP: %08x %08x %08x\n", 679 w0, w4, w8); 680 if (w4 == 0x20425355 && w2 == 0x0300) { 681 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 682 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 683 } 684 if (w4 == 0x20425355 && w2 == 0x0200) { 685 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 686 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 687 } 688 break; 689 } 690 case XHCI_ID_USB_LEGACY: { 691 uint8_t bios_sem; 692 693 /* Take host controller from BIOS */ 694 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 695 if (bios_sem) { 696 /* sets xHCI to be owned by OS */ 697 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 698 aprint_debug( 699 "waiting for BIOS to give up control\n"); 700 for (i = 0; i < 5000; i++) { 701 bios_sem = xhci_read_1(sc, ecp + 702 XHCI_XECP_BIOS_SEM); 703 if (bios_sem == 0) 704 break; 705 DELAY(1000); 706 } 707 if (bios_sem) 708 printf("timed out waiting for BIOS\n"); 709 } 710 break; 711 } 712 default: 713 break; 714 } 715 ecr = xhci_read_4(sc, ecp); 716 if (XHCI_XECP_NEXT(ecr) == 0) { 717 ecp = 0; 718 } else { 719 ecp += XHCI_XECP_NEXT(ecr) * 4; 720 } 721 } 722 723 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 724 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 725 &sc->sc_obh) != 0) { 726 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 727 return ENOMEM; 728 } 729 730 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 731 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 732 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 733 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 734 return ENOMEM; 735 } 736 737 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 738 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 739 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 740 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 741 return ENOMEM; 742 } 743 744 for (i = 0; i < 100; i++) { 745 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 746 if ((usbsts & XHCI_STS_CNR) == 0) 747 break; 748 usb_delay_ms(&sc->sc_bus, 1); 749 } 750 if (i >= 100) 751 return EIO; 752 753 usbcmd = 0; 754 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 755 usb_delay_ms(&sc->sc_bus, 1); 756 757 usbcmd = XHCI_CMD_HCRST; 758 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 759 for (i = 0; i < 100; i++) { 760 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 761 if ((usbcmd & XHCI_CMD_HCRST) == 0) 762 break; 763 usb_delay_ms(&sc->sc_bus, 1); 764 } 765 if (i >= 100) 766 return EIO; 767 768 for (i = 0; i < 100; i++) { 769 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 770 if ((usbsts & XHCI_STS_CNR) == 0) 771 break; 772 usb_delay_ms(&sc->sc_bus, 1); 773 } 774 if (i >= 100) 775 return EIO; 776 777 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 778 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 779 pagesize = ffs(pagesize); 780 if (pagesize == 0) 781 return EIO; 782 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 783 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 784 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 785 (uint32_t)sc->sc_maxslots); 786 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 787 788 usbd_status err; 789 790 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 791 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 792 if (sc->sc_maxspbuf != 0) { 793 err = usb_allocmem(&sc->sc_bus, 794 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 795 &sc->sc_spbufarray_dma); 796 if (err) 797 return err; 798 799 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * sc->sc_maxspbuf, KM_SLEEP); 800 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 801 for (i = 0; i < sc->sc_maxspbuf; i++) { 802 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 803 /* allocate contexts */ 804 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 805 sc->sc_pgsz, dma); 806 if (err) 807 return err; 808 spbufarray[i] = htole64(DMAADDR(dma, 0)); 809 usb_syncmem(dma, 0, sc->sc_pgsz, 810 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 811 } 812 813 usb_syncmem(&sc->sc_spbufarray_dma, 0, 814 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 815 } 816 817 config = xhci_op_read_4(sc, XHCI_CONFIG); 818 config &= ~0xFF; 819 config |= sc->sc_maxslots & 0xFF; 820 xhci_op_write_4(sc, XHCI_CONFIG, config); 821 822 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 823 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 824 if (err) { 825 aprint_error_dev(sc->sc_dev, "command ring init fail\n"); 826 return err; 827 } 828 829 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 830 XHCI_EVENT_RING_SEGMENTS_ALIGN); 831 if (err) { 832 aprint_error_dev(sc->sc_dev, "event ring init fail\n"); 833 return err; 834 } 835 836 usb_dma_t *dma; 837 size_t size; 838 size_t align; 839 840 dma = &sc->sc_eventst_dma; 841 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 842 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 843 KASSERT(size <= (512 * 1024)); 844 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 845 err = usb_allocmem(&sc->sc_bus, size, align, dma); 846 847 memset(KERNADDR(dma, 0), 0, size); 848 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 849 aprint_debug_dev(sc->sc_dev, "eventst: %s %016jx %p %zx\n", 850 usbd_errstr(err), 851 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 852 KERNADDR(&sc->sc_eventst_dma, 0), 853 sc->sc_eventst_dma.udma_block->size); 854 855 dma = &sc->sc_dcbaa_dma; 856 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 857 KASSERT(size <= 2048); 858 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 859 err = usb_allocmem(&sc->sc_bus, size, align, dma); 860 861 memset(KERNADDR(dma, 0), 0, size); 862 if (sc->sc_maxspbuf != 0) { 863 /* 864 * DCBA entry 0 hold the scratchbuf array pointer. 865 */ 866 *(uint64_t *)KERNADDR(dma, 0) = 867 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 868 } 869 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 870 aprint_debug_dev(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n", 871 usbd_errstr(err), 872 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 873 KERNADDR(&sc->sc_dcbaa_dma, 0), 874 sc->sc_dcbaa_dma.udma_block->size); 875 876 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 877 KM_SLEEP); 878 879 cv_init(&sc->sc_command_cv, "xhcicmd"); 880 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 881 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 882 cv_init(&sc->sc_softwake_cv, "xhciab"); 883 884 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 885 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 886 887 /* Set up the bus struct. */ 888 sc->sc_bus.ub_methods = &xhci_bus_methods; 889 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 890 891 struct xhci_erste *erst; 892 erst = KERNADDR(&sc->sc_eventst_dma, 0); 893 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 894 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 895 erst[0].erste_3 = htole32(0); 896 usb_syncmem(&sc->sc_eventst_dma, 0, 897 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 898 899 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 900 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 901 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 902 XHCI_ERDP_LO_BUSY); 903 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 904 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 905 sc->sc_cr.xr_cs); 906 907 #if 0 908 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 909 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 910 #endif 911 912 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 913 #ifdef XHCI_QUIRK_INTEL 914 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 915 /* Intel xhci needs interrupt rate moderated. */ 916 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 917 else 918 #endif /* XHCI_QUIRK_INTEL */ 919 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 920 921 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 922 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 923 xhci_op_read_4(sc, XHCI_USBCMD)); 924 925 return USBD_NORMAL_COMPLETION; 926 } 927 928 int 929 xhci_intr(void *v) 930 { 931 struct xhci_softc * const sc = v; 932 int ret = 0; 933 934 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 935 936 if (sc == NULL) 937 return 0; 938 939 mutex_spin_enter(&sc->sc_intr_lock); 940 941 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 942 goto done; 943 944 /* If we get an interrupt while polling, then just ignore it. */ 945 if (sc->sc_bus.ub_usepolling) { 946 #ifdef DIAGNOSTIC 947 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 948 #endif 949 goto done; 950 } 951 952 ret = xhci_intr1(sc); 953 done: 954 mutex_spin_exit(&sc->sc_intr_lock); 955 return ret; 956 } 957 958 int 959 xhci_intr1(struct xhci_softc * const sc) 960 { 961 uint32_t usbsts; 962 uint32_t iman; 963 964 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 965 966 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 967 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 968 #if 0 969 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 970 return 0; 971 } 972 #endif 973 xhci_op_write_4(sc, XHCI_USBSTS, 974 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 975 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 976 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 977 978 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 979 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 980 #ifdef XHCI_QUIRK_FORCE_INTR 981 982 if (!(sc->sc_quirks & XHCI_QUIRK_FORCE_INTR)) { 983 if ((iman & XHCI_IMAN_INTR_PEND) == 0) { 984 return 0; 985 } 986 } 987 988 #else 989 if ((iman & XHCI_IMAN_INTR_PEND) == 0) { 990 return 0; 991 } 992 #endif /* XHCI_QUIRK_FORCE_INTR */ 993 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 994 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 995 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 996 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 997 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 998 999 usb_schedsoftintr(&sc->sc_bus); 1000 1001 return 1; 1002 } 1003 1004 /* 1005 * 3 port speed types used in USB stack 1006 * 1007 * usbdi speed 1008 * definition: USB_SPEED_* in usb.h 1009 * They are used in struct usbd_device in USB stack. 1010 * ioctl interface uses these values too. 1011 * port_status speed 1012 * definition: UPS_*_SPEED in usb.h 1013 * They are used in usb_port_status_t. 1014 * Some 3.0 values overlap with 2.0 values. 1015 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1016 * means UPS_LOW_SPEED in HS.) 1017 * port status sent from hub also uses these values. 1018 * (but I've never seen UPS_SUPER_SPEED in port_status from hub.) 1019 * xspeed: 1020 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1021 * They are used in only slot context and PORTSC reg of xhci. 1022 * The difference between usbdi speed and them are that 1023 * FS and LS values are swapped. 1024 */ 1025 1026 static int 1027 xhci_speed2xspeed(int speed) 1028 { 1029 switch (speed) { 1030 case USB_SPEED_LOW: return 2; 1031 case USB_SPEED_FULL: return 1; 1032 case USB_SPEED_HIGH: return 3; 1033 case USB_SPEED_SUPER: return 4; 1034 default: 1035 break; 1036 } 1037 return 0; 1038 } 1039 1040 /* construct slot context */ 1041 static void 1042 xhci_setup_sctx(struct usbd_device *dev, uint32_t *cp) 1043 { 1044 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 1045 int speed = dev->ud_speed; 1046 int tthubslot, ttportnum; 1047 bool ishub; 1048 bool usemtt; 1049 1050 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1051 1052 /* 6.2.2 */ 1053 /* 1054 * tthubslot: 1055 * This is the slot ID of parent HS hub 1056 * if LS/FS device is connected && connected through HS hub. 1057 * This is 0 if device is not LS/FS device || 1058 * parent hub is not HS hub || 1059 * attached to root hub. 1060 * ttportnum: 1061 * This is the downstream facing port of parent HS hub 1062 * if LS/FS device is connected. 1063 * This is 0 if device is not LS/FS device || 1064 * parent hub is not HS hub || 1065 * attached to root hub. 1066 */ 1067 if (dev->ud_myhsport != NULL && 1068 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1069 (dev->ud_myhub != NULL && 1070 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1071 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 1072 ttportnum = dev->ud_myhsport->up_portno; 1073 /* XXX addr == slot ? */ 1074 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 1075 } else { 1076 ttportnum = 0; 1077 tthubslot = 0; 1078 } 1079 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 1080 dev->ud_myhsport, ttportnum, tthubslot, 0); 1081 1082 /* ishub is valid after reading UDESC_DEVICE */ 1083 ishub = (dd->bDeviceClass == UDCLASS_HUB); 1084 1085 /* dev->ud_hub is valid after reading UDESC_HUB */ 1086 if (ishub && dev->ud_hub) { 1087 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 1088 1089 cp[1] |= htole32(XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts)); 1090 cp[2] |= htole32(XHCI_SCTX_2_TT_THINK_TIME_SET( 1091 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK))); 1092 DPRINTFN(4, "nports=%d ttt=%d", 1093 hd->bNbrPorts, XHCI_SCTX_2_TT_THINK_TIME_GET(cp[2]), 0, 0); 1094 } 1095 1096 #define IS_TTHUB(dd) \ 1097 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 1098 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 1099 1100 /* 1101 * MTT flag is set if 1102 * 1. this is HS hub && MTT is enabled 1103 * or 1104 * 2. this is not hub && this is LS or FS device && 1105 * MTT of parent HS hub (and its parent, too) is enabled 1106 */ 1107 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 1108 usemtt = true; 1109 else if (!ishub && 1110 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 1111 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1112 (dev->ud_myhub != NULL && 1113 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1114 dev->ud_myhsport != NULL && 1115 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 1116 usemtt = true; 1117 else 1118 usemtt = false; 1119 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 1120 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 1121 1122 cp[0] |= htole32( 1123 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)) | 1124 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 1125 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0) 1126 ); 1127 cp[1] |= htole32(0); 1128 cp[2] |= htole32( 1129 XHCI_SCTX_2_IRQ_TARGET_SET(0) | 1130 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 1131 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum) 1132 ); 1133 cp[3] |= htole32(0); 1134 } 1135 1136 /* 1137 * called 1138 * from xhci_open 1139 * from usbd_setup_pipe_flags 1140 * from usbd_open_pipe_ival 1141 */ 1142 static usbd_status 1143 xhci_configure_endpoint(struct usbd_pipe *pipe) 1144 { 1145 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1146 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1147 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1148 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1149 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1150 struct xhci_trb trb; 1151 usbd_status err; 1152 uint32_t *cp; 1153 uint32_t mps = UGETW(ed->wMaxPacketSize); 1154 uint32_t maxb = 0; 1155 int speed = pipe->up_dev->ud_speed; 1156 uint32_t ival = ed->bInterval; 1157 1158 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1159 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1160 xs->xs_idx, dci, ed->bEndpointAddress, ed->bmAttributes); 1161 1162 /* XXX ensure input context is available? */ 1163 1164 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1165 1166 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1167 cp[0] = htole32(0); 1168 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 1169 1170 /* set up input slot context */ 1171 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1172 xhci_setup_sctx(pipe->up_dev, cp); 1173 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1174 1175 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 1176 cp[0] = htole32( 1177 XHCI_EPCTX_0_EPSTATE_SET(0) | 1178 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 1179 XHCI_EPCTX_0_LSA_SET(0) 1180 ); 1181 cp[1] = htole32( 1182 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 1183 XHCI_EPCTX_1_MAXB_SET(0) 1184 ); 1185 if (xfertype != UE_ISOCHRONOUS) 1186 cp[1] |= htole32(XHCI_EPCTX_1_CERR_SET(3)); 1187 1188 if (speed == USB_SPEED_SUPER) { 1189 usbd_desc_iter_t iter; 1190 const usb_cdc_descriptor_t *cdcd; 1191 const usb_endpoint_ss_comp_descriptor_t * esscd = NULL; 1192 uint8_t ep; 1193 1194 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc( 1195 pipe->up_dev, UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 1196 usb_desc_iter_init(pipe->up_dev, &iter); 1197 iter.cur = (const void *)cdcd; 1198 1199 /* find endpoint_ss_comp desc for ep of this pipe */ 1200 for(ep = 0;;) { 1201 cdcd = (const usb_cdc_descriptor_t *) 1202 usb_desc_iter_next(&iter); 1203 if (cdcd == NULL) 1204 break; 1205 if (ep == 0 && 1206 cdcd->bDescriptorType == UDESC_ENDPOINT) { 1207 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 1208 bEndpointAddress; 1209 if (UE_GET_ADDR(ep) == 1210 UE_GET_ADDR(ed->bEndpointAddress)) { 1211 cdcd = (const usb_cdc_descriptor_t *) 1212 usb_desc_iter_next(&iter); 1213 break; 1214 } 1215 ep = 0; 1216 } 1217 } 1218 if (cdcd != NULL && 1219 cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 1220 esscd = (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 1221 maxb = esscd->bMaxBurst; 1222 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1223 DPRINTFN(4, "setting SS MaxBurst %u", maxb, 0, 0, 0); 1224 } 1225 } 1226 if (speed == USB_SPEED_HIGH && 1227 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 1228 maxb = UE_GET_TRANS(UGETW(ed->wMaxPacketSize)); 1229 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1230 DPRINTFN(4, "setting HS MaxBurst %u", maxb, 0, 0, 0); 1231 } 1232 1233 switch (xfertype) { 1234 case UE_INTERRUPT: 1235 /* 6.2.3.6 */ 1236 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 1237 ival = ival > 10 ? 10 : ival; 1238 ival = ival < 3 ? 3 : ival; 1239 } else { 1240 ival = ival > 15 ? 15 : ival; 1241 } 1242 if (speed == USB_SPEED_SUPER) { 1243 if (maxb > 0) 1244 mps = 1024; 1245 } else { 1246 mps = mps ? mps : 8; 1247 } 1248 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1249 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1250 cp[4] = htole32( 1251 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) /* XXX */ 1252 ); 1253 break; 1254 case UE_CONTROL: 1255 if (speed == USB_SPEED_SUPER) 1256 mps = 512; 1257 else 1258 mps = mps ? mps : 8; 1259 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1260 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(8)); /* XXX */ 1261 break; 1262 #ifdef notyet 1263 case UE_ISOCHRONOUS: 1264 if (speed == USB_SPEED_FULL) { 1265 ival = ival > 18 ? 18 : ival; 1266 ival = ival < 3 ? 3 : ival; 1267 } else { 1268 ival = ival > 15 ? 15 : ival; 1269 } 1270 if (speed == USB_SPEED_SUPER) { 1271 mps = 1024; 1272 } else { 1273 mps = mps ? mps : 1024; 1274 } 1275 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1276 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(1024)); /* XXX */ 1277 break; 1278 #endif 1279 default: 1280 if (speed == USB_SPEED_SUPER) 1281 mps = 1024; 1282 else 1283 mps = mps ? mps : 512; 1284 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1285 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(1024)); /* XXX */ 1286 break; 1287 } 1288 *(uint64_t *)(&cp[2]) = htole64( 1289 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 1290 XHCI_EPCTX_2_DCS_SET(1)); 1291 1292 /* sync input contexts before they are read from memory */ 1293 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1294 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1295 sc->sc_ctxsz * 1); 1296 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1297 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1298 1299 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1300 trb.trb_2 = 0; 1301 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1302 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1303 1304 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1305 1306 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1307 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1308 sc->sc_ctxsz * 1); 1309 1310 return err; 1311 } 1312 1313 #if 0 1314 static usbd_status 1315 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1316 { 1317 #ifdef USB_DEBUG 1318 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1319 #endif 1320 1321 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1322 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1323 1324 return USBD_NORMAL_COMPLETION; 1325 } 1326 #endif 1327 1328 /* 4.6.8, 6.4.3.7 */ 1329 static usbd_status 1330 xhci_reset_endpoint(struct usbd_pipe *pipe) 1331 { 1332 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1333 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1334 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1335 struct xhci_trb trb; 1336 usbd_status err; 1337 1338 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1339 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1340 1341 KASSERT(!mutex_owned(&sc->sc_lock)); 1342 1343 trb.trb_0 = 0; 1344 trb.trb_2 = 0; 1345 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1346 XHCI_TRB_3_EP_SET(dci) | 1347 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1348 1349 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1350 1351 return err; 1352 } 1353 1354 /* 1355 * 4.6.9, 6.4.3.8 1356 * Stop execution of TDs on xfer ring. 1357 * Should be called with sc_lock held. 1358 */ 1359 static usbd_status 1360 xhci_stop_endpoint(struct usbd_pipe *pipe) 1361 { 1362 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1363 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1364 struct xhci_trb trb; 1365 usbd_status err; 1366 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1367 1368 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1369 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1370 1371 KASSERT(mutex_owned(&sc->sc_lock)); 1372 1373 trb.trb_0 = 0; 1374 trb.trb_2 = 0; 1375 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1376 XHCI_TRB_3_EP_SET(dci) | 1377 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1378 1379 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1380 1381 return err; 1382 } 1383 1384 /* 1385 * Set TR Dequeue Pointer. 1386 * xCHI 1.1 4.6.10 6.4.3.9 1387 * Purge all of the transfer requests on ring. 1388 * EPSTATE of endpoint must be ERROR or STOPPED, or CONTEXT_STATE error. 1389 */ 1390 static usbd_status 1391 xhci_set_dequeue(struct usbd_pipe *pipe) 1392 { 1393 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1394 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1395 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1396 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1397 struct xhci_trb trb; 1398 usbd_status err; 1399 1400 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1401 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1402 1403 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1404 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1405 BUS_DMASYNC_PREWRITE); 1406 1407 xr->xr_ep = 0; 1408 xr->xr_cs = 1; 1409 1410 /* set DCS */ 1411 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1412 trb.trb_2 = 0; 1413 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1414 XHCI_TRB_3_EP_SET(dci) | 1415 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1416 1417 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1418 1419 return err; 1420 } 1421 1422 /* 1423 * Open new pipe: called from usbd_setup_pipe_flags. 1424 * Fills methods of pipe. 1425 * If pipe is not for ep0, calls configure_endpoint. 1426 */ 1427 static usbd_status 1428 xhci_open(struct usbd_pipe *pipe) 1429 { 1430 struct usbd_device * const dev = pipe->up_dev; 1431 struct xhci_softc * const sc = dev->ud_bus->ub_hcpriv; 1432 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1433 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1434 1435 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1436 DPRINTFN(1, "addr %d depth %d port %d speed %d", 1437 dev->ud_addr, dev->ud_depth, dev->ud_powersrc->up_portno, 1438 dev->ud_speed); 1439 1440 if (sc->sc_dying) 1441 return USBD_IOERROR; 1442 1443 /* Root Hub */ 1444 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1445 switch (ed->bEndpointAddress) { 1446 case USB_CONTROL_ENDPOINT: 1447 pipe->up_methods = &roothub_ctrl_methods; 1448 break; 1449 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1450 pipe->up_methods = &xhci_root_intr_methods; 1451 break; 1452 default: 1453 pipe->up_methods = NULL; 1454 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1455 ed->bEndpointAddress, 0, 0, 0); 1456 return USBD_INVAL; 1457 } 1458 return USBD_NORMAL_COMPLETION; 1459 } 1460 1461 switch (xfertype) { 1462 case UE_CONTROL: 1463 pipe->up_methods = &xhci_device_ctrl_methods; 1464 break; 1465 case UE_ISOCHRONOUS: 1466 pipe->up_methods = &xhci_device_isoc_methods; 1467 return USBD_INVAL; 1468 break; 1469 case UE_BULK: 1470 pipe->up_methods = &xhci_device_bulk_methods; 1471 break; 1472 case UE_INTERRUPT: 1473 pipe->up_methods = &xhci_device_intr_methods; 1474 break; 1475 default: 1476 return USBD_IOERROR; 1477 break; 1478 } 1479 1480 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1481 return xhci_configure_endpoint(pipe); 1482 1483 return USBD_NORMAL_COMPLETION; 1484 } 1485 1486 /* 1487 * Closes pipe, called from usbd_kill_pipe via close methods. 1488 * If the endpoint to be closed is ep0, disable_slot. 1489 * Should be called with sc_lock held. 1490 */ 1491 static usbd_status 1492 xhci_close_pipe(struct usbd_pipe *pipe) 1493 { 1494 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1495 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1496 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1497 const u_int dci = xhci_ep_get_dci(ed); 1498 struct xhci_trb trb; 1499 usbd_status err; 1500 uint32_t *cp; 1501 1502 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1503 1504 if (sc->sc_dying) 1505 return USBD_IOERROR; 1506 1507 if (xs == NULL || xs->xs_idx == 0) 1508 /* xs is uninitialized before xhci_init_slot */ 1509 return USBD_IOERROR; 1510 1511 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1512 1513 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1514 KASSERT(mutex_owned(&sc->sc_lock)); 1515 1516 if (pipe->up_dev->ud_depth == 0) 1517 return USBD_NORMAL_COMPLETION; 1518 1519 if (dci == XHCI_DCI_EP_CONTROL) { 1520 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1521 return xhci_disable_slot(sc, xs->xs_idx); 1522 } 1523 1524 /* 1525 * This may fail in the case that xhci_close_pipe is called after 1526 * xhci_abort_xfer e.g. usbd_kill_pipe. 1527 */ 1528 (void)xhci_stop_endpoint(pipe); 1529 1530 /* 1531 * set appropriate bit to be dropped. 1532 * don't set DC bit to 1, otherwise all endpoints 1533 * would be deconfigured. 1534 */ 1535 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1536 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1537 cp[1] = htole32(0); 1538 1539 /* XXX should be most significant one, not dci? */ 1540 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1541 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1542 1543 /* sync input contexts before they are read from memory */ 1544 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1545 1546 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1547 trb.trb_2 = 0; 1548 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1549 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1550 1551 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1552 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1553 1554 return err; 1555 } 1556 1557 /* 1558 * Abort transfer. 1559 * Called with sc_lock held. 1560 * May be called from softintr context. 1561 */ 1562 static void 1563 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1564 { 1565 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1566 1567 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1568 DPRINTFN(4, "xfer %p pipe %p status %d", 1569 xfer, xfer->ux_pipe, status, 0); 1570 1571 KASSERT(mutex_owned(&sc->sc_lock)); 1572 1573 if (sc->sc_dying) { 1574 /* If we're dying, just do the software part. */ 1575 DPRINTFN(4, "dying", 0, 0, 0, 0); 1576 xfer->ux_status = status; /* make software ignore it */ 1577 callout_stop(&xfer->ux_callout); 1578 usb_transfer_complete(xfer); 1579 return; 1580 } 1581 1582 /* XXX need more stuff */ 1583 xfer->ux_status = status; 1584 callout_stop(&xfer->ux_callout); 1585 usb_transfer_complete(xfer); 1586 1587 KASSERT(mutex_owned(&sc->sc_lock)); 1588 } 1589 1590 #if 1 /* XXX experimental */ 1591 /* 1592 * Recover STALLed endpoint. 1593 * xHCI 1.1 sect 4.10.2.1 1594 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1595 * all transfers on transfer ring. 1596 * These are done in thread context asynchronously. 1597 */ 1598 static void 1599 xhci_clear_endpoint_stall_async_task(void *cookie) 1600 { 1601 struct usbd_xfer * const xfer = cookie; 1602 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1603 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1604 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1605 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1606 1607 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1608 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1609 1610 xhci_reset_endpoint(xfer->ux_pipe); 1611 xhci_set_dequeue(xfer->ux_pipe); 1612 1613 mutex_enter(&sc->sc_lock); 1614 tr->is_halted = false; 1615 usb_transfer_complete(xfer); 1616 mutex_exit(&sc->sc_lock); 1617 DPRINTFN(4, "ends", 0, 0, 0, 0); 1618 } 1619 1620 static usbd_status 1621 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1622 { 1623 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1624 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1625 1626 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1627 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1628 1629 if (sc->sc_dying) { 1630 return USBD_IOERROR; 1631 } 1632 1633 usb_init_task(&xp->xp_async_task, 1634 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1635 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1636 DPRINTFN(4, "ends", 0, 0, 0, 0); 1637 1638 return USBD_NORMAL_COMPLETION; 1639 } 1640 1641 #endif /* XXX experimental */ 1642 1643 /* 1644 * Notify roothub port status/change to uhub_intr. 1645 */ 1646 static void 1647 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1648 { 1649 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1650 uint8_t *p; 1651 1652 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1653 DPRINTFN(4, "port %u status change", port, 0, 0, 0); 1654 1655 if (xfer == NULL) 1656 return; 1657 1658 p = xfer->ux_buf; 1659 memset(p, 0, xfer->ux_length); 1660 p[port/NBBY] |= 1 << (port%NBBY); 1661 xfer->ux_actlen = xfer->ux_length; 1662 xfer->ux_status = USBD_NORMAL_COMPLETION; 1663 usb_transfer_complete(xfer); 1664 } 1665 1666 /* 1667 * Process events: 1668 * + Transfer comeplete 1669 * + Command complete 1670 * + Roothub Port status/change 1671 */ 1672 static void 1673 xhci_handle_event(struct xhci_softc * const sc, 1674 const struct xhci_trb * const trb) 1675 { 1676 uint64_t trb_0; 1677 uint32_t trb_2, trb_3; 1678 uint8_t trberr; 1679 1680 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1681 1682 trb_0 = le64toh(trb->trb_0); 1683 trb_2 = le32toh(trb->trb_2); 1684 trb_3 = le32toh(trb->trb_3); 1685 trberr = XHCI_TRB_2_ERROR_GET(trb_2); 1686 1687 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1688 trb, trb_0, trb_2, trb_3); 1689 1690 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 1691 case XHCI_TRB_EVENT_TRANSFER: { 1692 u_int slot, dci; 1693 struct xhci_slot *xs; 1694 struct xhci_ring *xr; 1695 struct xhci_xfer *xx; 1696 struct usbd_xfer *xfer; 1697 usbd_status err; 1698 1699 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1700 dci = XHCI_TRB_3_EP_GET(trb_3); 1701 1702 xs = &sc->sc_slots[slot]; 1703 xr = &xs->xs_ep[dci].xe_tr; 1704 /* sanity check */ 1705 if (xs->xs_idx == 0 || xs->xs_idx >= sc->sc_maxslots) { 1706 DPRINTFN(1, "invalid slot %u", xs->xs_idx, 0, 0, 0); 1707 break; 1708 } 1709 1710 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1711 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 1712 1713 /* trb_0 range sanity check */ 1714 if (trb_0 < trbp || 1715 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 1716 (trb_0 - trbp) / sizeof(struct xhci_trb) >= 1717 xr->xr_ntrb) { 1718 DPRINTFN(1, 1719 "invalid trb_0 0x%"PRIx64" trbp 0x%"PRIx64, 1720 trb_0, trbp, 0, 0); 1721 break; 1722 } 1723 int idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 1724 xx = xr->xr_cookies[idx]; 1725 } else { 1726 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1727 } 1728 /* XXX this may not happen */ 1729 if (xx == NULL) { 1730 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1731 break; 1732 } 1733 xfer = &xx->xx_xfer; 1734 /* XXX this may happen when detaching */ 1735 if (xfer == NULL) { 1736 DPRINTFN(1, "xfer done: xfer is NULL", 0, 0, 0, 0); 1737 break; 1738 } 1739 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1740 /* XXX I dunno why this happens */ 1741 if (!xfer->ux_pipe->up_repeat && 1742 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1743 DPRINTFN(1, "xfer done: xfer not started", 0, 0, 0, 0); 1744 break; 1745 } 1746 1747 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1748 DPRINTFN(14, "transfer event data: " 1749 "0x%016"PRIx64" 0x%08"PRIx32" %02x", 1750 trb_0, XHCI_TRB_2_REM_GET(trb_2), 1751 XHCI_TRB_2_ERROR_GET(trb_2), 0); 1752 if ((trb_0 & 0x3) == 0x3) { 1753 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1754 } 1755 } 1756 1757 switch (trberr) { 1758 case XHCI_TRB_ERROR_SHORT_PKT: 1759 case XHCI_TRB_ERROR_SUCCESS: 1760 xfer->ux_actlen = 1761 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1762 err = USBD_NORMAL_COMPLETION; 1763 break; 1764 case XHCI_TRB_ERROR_STALL: 1765 case XHCI_TRB_ERROR_BABBLE: 1766 DPRINTFN(1, "evh: xfer done: ERR %u slot %u dci %u", 1767 trberr, slot, dci, 0); 1768 xr->is_halted = true; 1769 err = USBD_STALLED; 1770 #if 1 /* XXX experimental */ 1771 /* 1772 * Stalled endpoints can be recoverd by issuing 1773 * command TRB TYPE_RESET_EP on xHCI instead of 1774 * issuing request CLEAR_PORT_FEATURE UF_ENDPOINT_HALT 1775 * on the endpoint. However, this function may be 1776 * called from softint context (e.g. from umass), 1777 * in that case driver gets KASSERT in cv_timedwait 1778 * in xhci_do_command. 1779 * To avoid this, this runs reset_endpoint and 1780 * usb_transfer_complete in usb task thread 1781 * asynchronously (and then umass issues clear 1782 * UF_ENDPOINT_HALT). 1783 */ 1784 xfer->ux_status = err; 1785 xhci_clear_endpoint_stall_async(xfer); 1786 return; 1787 #else 1788 break; 1789 #endif 1790 case XHCI_TRB_ERROR_CMD_ABORTED: 1791 case XHCI_TRB_ERROR_STOPPED: 1792 err = USBD_CANCELLED; 1793 break; 1794 case XHCI_TRB_ERROR_NO_SLOTS: 1795 err = USBD_NO_ADDR; 1796 break; 1797 default: 1798 DPRINTFN(1, "evh: xfer done: ERR %u slot %u dci %u", 1799 trberr, slot, dci, 0); 1800 err = USBD_IOERROR; 1801 break; 1802 } 1803 xfer->ux_status = err; 1804 1805 //mutex_enter(&sc->sc_lock); /* XXX ??? */ 1806 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1807 if ((trb_0 & 0x3) == 0x0) { 1808 usb_transfer_complete(xfer); 1809 } 1810 } else { 1811 usb_transfer_complete(xfer); 1812 } 1813 //mutex_exit(&sc->sc_lock); /* XXX ??? */ 1814 1815 } 1816 break; 1817 case XHCI_TRB_EVENT_CMD_COMPLETE: 1818 if (trb_0 == sc->sc_command_addr) { 1819 sc->sc_result_trb.trb_0 = trb_0; 1820 sc->sc_result_trb.trb_2 = trb_2; 1821 sc->sc_result_trb.trb_3 = trb_3; 1822 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1823 XHCI_TRB_ERROR_SUCCESS) { 1824 DPRINTFN(1, "command completion " 1825 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1826 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1827 } 1828 cv_signal(&sc->sc_command_cv); 1829 } else { 1830 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 1831 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1832 trb_2, trb_3); 1833 } 1834 break; 1835 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1836 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1837 break; 1838 default: 1839 break; 1840 } 1841 } 1842 1843 static void 1844 xhci_softintr(void *v) 1845 { 1846 struct usbd_bus * const bus = v; 1847 struct xhci_softc * const sc = bus->ub_hcpriv; 1848 struct xhci_ring * const er = &sc->sc_er; 1849 struct xhci_trb *trb; 1850 int i, j, k; 1851 1852 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1853 1854 i = er->xr_ep; 1855 j = er->xr_cs; 1856 1857 DPRINTFN(16, "xr_ep %d xr_cs %d", i, j, 0, 0); 1858 1859 while (1) { 1860 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 1861 BUS_DMASYNC_POSTREAD); 1862 trb = &er->xr_trb[i]; 1863 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1864 1865 if (j != k) 1866 break; 1867 1868 xhci_handle_event(sc, trb); 1869 1870 i++; 1871 if (i == XHCI_EVENT_RING_TRBS) { 1872 i = 0; 1873 j ^= 1; 1874 } 1875 } 1876 1877 er->xr_ep = i; 1878 er->xr_cs = j; 1879 1880 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 1881 XHCI_ERDP_LO_BUSY); 1882 1883 DPRINTFN(16, "ends", 0, 0, 0, 0); 1884 1885 return; 1886 } 1887 1888 static void 1889 xhci_poll(struct usbd_bus *bus) 1890 { 1891 struct xhci_softc * const sc = bus->ub_hcpriv; 1892 1893 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1894 1895 mutex_spin_enter(&sc->sc_intr_lock); 1896 xhci_intr1(sc); 1897 mutex_spin_exit(&sc->sc_intr_lock); 1898 1899 return; 1900 } 1901 1902 static struct usbd_xfer * 1903 xhci_allocx(struct usbd_bus *bus) 1904 { 1905 struct xhci_softc * const sc = bus->ub_hcpriv; 1906 struct usbd_xfer *xfer; 1907 1908 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1909 1910 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1911 if (xfer != NULL) { 1912 memset(xfer, 0, sizeof(struct xhci_xfer)); 1913 #ifdef DIAGNOSTIC 1914 xfer->ux_state = XFER_BUSY; 1915 #endif 1916 } 1917 1918 return xfer; 1919 } 1920 1921 static void 1922 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1923 { 1924 struct xhci_softc * const sc = bus->ub_hcpriv; 1925 1926 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1927 1928 #ifdef DIAGNOSTIC 1929 if (xfer->ux_state != XFER_BUSY) { 1930 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 1931 xfer, xfer->ux_state, 0, 0); 1932 } 1933 xfer->ux_state = XFER_FREE; 1934 #endif 1935 pool_cache_put(sc->sc_xferpool, xfer); 1936 } 1937 1938 static void 1939 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1940 { 1941 struct xhci_softc * const sc = bus->ub_hcpriv; 1942 1943 *lock = &sc->sc_lock; 1944 } 1945 1946 extern uint32_t usb_cookie_no; 1947 1948 /* 1949 * Called if uhub_explore find new device (via usbd_new_device). 1950 * Allocate and construct dev structure of default endpoint (ep0). 1951 * Determine initial MaxPacketSize (mps) by speed. 1952 * Determine route string and roothub port for slot of dev. 1953 * Allocate pipe of ep0. 1954 * Enable and initialize slot and Set Address. 1955 * Read device descriptor. 1956 * Register this device. 1957 */ 1958 static usbd_status 1959 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 1960 int speed, int port, struct usbd_port *up) 1961 { 1962 struct xhci_softc * const sc = bus->ub_hcpriv; 1963 struct usbd_device *dev; 1964 usbd_status err; 1965 usb_device_descriptor_t *dd; 1966 struct usbd_device *hub; 1967 struct usbd_device *adev; 1968 int rhport = 0; 1969 struct xhci_slot *xs; 1970 uint32_t *cp; 1971 uint32_t route = 0; 1972 uint8_t slot = 0; 1973 uint8_t addr; 1974 1975 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1976 DPRINTFN(4, "port=%d depth=%d speed=%d upport %d", 1977 port, depth, speed, up->up_portno); 1978 1979 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 1980 if (dev == NULL) 1981 return USBD_NOMEM; 1982 1983 dev->ud_bus = bus; 1984 1985 /* Set up default endpoint handle. */ 1986 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 1987 1988 /* Set up default endpoint descriptor. */ 1989 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 1990 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 1991 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 1992 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 1993 /* 4.3, 4.8.2.1 */ 1994 switch (speed) { 1995 case USB_SPEED_SUPER: 1996 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 1997 break; 1998 case USB_SPEED_FULL: 1999 /* XXX using 64 as initial mps of ep0 in FS */ 2000 case USB_SPEED_HIGH: 2001 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2002 break; 2003 case USB_SPEED_LOW: 2004 default: 2005 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2006 break; 2007 } 2008 dev->ud_ep0desc.bInterval = 0; 2009 2010 /* doesn't matter, just don't let it uninitialized */ 2011 dev->ud_ep0.ue_toggle = 0; 2012 2013 DPRINTFN(4, "up %p portno %d", up, up->up_portno, 0, 0); 2014 2015 dev->ud_quirks = &usbd_no_quirk; 2016 dev->ud_addr = 0; 2017 dev->ud_ddesc.bMaxPacketSize = 0; 2018 dev->ud_depth = depth; 2019 dev->ud_powersrc = up; 2020 dev->ud_myhub = up->up_parent; 2021 2022 up->up_dev = dev; 2023 2024 /* Locate root hub port */ 2025 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2026 uint32_t dep; 2027 2028 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2029 hub, hub->ud_depth, hub->ud_powersrc, 2030 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2031 2032 if (hub->ud_powersrc == NULL) 2033 break; 2034 dep = hub->ud_depth; 2035 if (dep == 0) 2036 break; 2037 rhport = hub->ud_powersrc->up_portno; 2038 if (dep > USB_HUB_MAX_DEPTH) 2039 continue; 2040 2041 route |= 2042 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2043 << ((dep - 1) * 4); 2044 } 2045 route = route >> 4; 2046 DPRINTFN(4, "rhport %d Route %05x hub %p", rhport, route, hub, 0); 2047 2048 /* Locate port on upstream high speed hub */ 2049 for (adev = dev, hub = up->up_parent; 2050 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2051 adev = hub, hub = hub->ud_myhub) 2052 ; 2053 if (hub) { 2054 int p; 2055 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2056 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2057 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2058 goto found; 2059 } 2060 } 2061 panic("xhci_new_device: cannot find HS port"); 2062 found: 2063 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2064 } else { 2065 dev->ud_myhsport = NULL; 2066 } 2067 2068 dev->ud_speed = speed; 2069 dev->ud_langid = USBD_NOLANG; 2070 dev->ud_cookie.cookie = ++usb_cookie_no; 2071 2072 /* Establish the default pipe. */ 2073 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2074 &dev->ud_pipe0); 2075 if (err) { 2076 goto bad; 2077 } 2078 2079 dd = &dev->ud_ddesc; 2080 2081 if ((depth == 0) && (port == 0)) { 2082 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2083 bus->ub_devices[dev->ud_addr] = dev; 2084 err = usbd_get_initial_ddesc(dev, dd); 2085 if (err) 2086 goto bad; 2087 err = usbd_reload_device_desc(dev); 2088 if (err) 2089 goto bad; 2090 } else { 2091 err = xhci_enable_slot(sc, &slot); 2092 if (err) 2093 goto bad; 2094 xs = &sc->sc_slots[slot]; 2095 dev->ud_hcpriv = xs; 2096 err = xhci_init_slot(dev, slot, route, rhport); 2097 if (err) { 2098 dev->ud_hcpriv = NULL; 2099 /* 2100 * We have to disable_slot here because 2101 * xs->xs_idx == 0 when xhci_init_slot fails, 2102 * in that case usbd_remove_dev won't work. 2103 */ 2104 mutex_enter(&sc->sc_lock); 2105 xhci_disable_slot(sc, slot); 2106 mutex_exit(&sc->sc_lock); 2107 goto bad; 2108 } 2109 2110 /* Allow device time to set new address */ 2111 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2112 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2113 //hexdump("slot context", cp, sc->sc_ctxsz); 2114 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2115 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2116 /* XXX ensure we know when the hardware does something 2117 we can't yet cope with */ 2118 KASSERT(addr >= 1 && addr <= 127); 2119 dev->ud_addr = addr; 2120 /* XXX dev->ud_addr not necessarily unique on bus */ 2121 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2122 bus->ub_devices[dev->ud_addr] = dev; 2123 2124 err = usbd_get_initial_ddesc(dev, dd); 2125 if (err) 2126 goto bad; 2127 /* 4.8.2.1 */ 2128 if (speed == USB_SPEED_SUPER) { 2129 if (dd->bMaxPacketSize != 9) { 2130 printf("%s: invalid mps 2^%u for SS ep0," 2131 " using 512\n", 2132 device_xname(sc->sc_dev), 2133 dd->bMaxPacketSize); 2134 dd->bMaxPacketSize = 9; 2135 } 2136 USETW(dev->ud_ep0desc.wMaxPacketSize, 2137 (1 << dd->bMaxPacketSize)); 2138 } else 2139 USETW(dev->ud_ep0desc.wMaxPacketSize, 2140 dd->bMaxPacketSize); 2141 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2142 xhci_update_ep0_mps(sc, xs, 2143 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2144 err = usbd_reload_device_desc(dev); 2145 if (err) 2146 goto bad; 2147 2148 #if 0 2149 /* Re-establish the default pipe with the new MPS. */ 2150 /* In xhci this is done by xhci_update_ep0_mps. */ 2151 usbd_kill_pipe(dev->ud_pipe0); 2152 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2153 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2154 #endif 2155 } 2156 2157 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2158 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2159 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2160 dd->bDeviceClass, dd->bDeviceSubClass, 2161 dd->bDeviceProtocol, 0); 2162 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2163 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2164 dev->ud_speed); 2165 2166 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2167 2168 if ((depth == 0) && (port == 0)) { 2169 usbd_attach_roothub(parent, dev); 2170 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2171 return USBD_NORMAL_COMPLETION; 2172 } 2173 2174 2175 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2176 bad: 2177 if (err != USBD_NORMAL_COMPLETION) { 2178 usbd_remove_device(dev, up); 2179 } 2180 2181 return err; 2182 } 2183 2184 static usbd_status 2185 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2186 size_t ntrb, size_t align) 2187 { 2188 usbd_status err; 2189 size_t size = ntrb * XHCI_TRB_SIZE; 2190 2191 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2192 2193 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2194 if (err) 2195 return err; 2196 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2197 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2198 xr->xr_trb = xhci_ring_trbv(xr, 0); 2199 xr->xr_ntrb = ntrb; 2200 xr->xr_ep = 0; 2201 xr->xr_cs = 1; 2202 memset(xr->xr_trb, 0, size); 2203 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 2204 xr->is_halted = false; 2205 2206 return USBD_NORMAL_COMPLETION; 2207 } 2208 2209 static void 2210 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2211 { 2212 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2213 mutex_destroy(&xr->xr_lock); 2214 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2215 } 2216 2217 static void 2218 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2219 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2220 { 2221 size_t i; 2222 u_int ri; 2223 u_int cs; 2224 uint64_t parameter; 2225 uint32_t status; 2226 uint32_t control; 2227 2228 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2229 2230 for (i = 0; i < ntrbs; i++) { 2231 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2232 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2233 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2234 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2235 XHCI_TRB_TYPE_LINK); 2236 } 2237 2238 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2239 2240 ri = xr->xr_ep; 2241 cs = xr->xr_cs; 2242 2243 /* 2244 * Although the xhci hardware can do scatter/gather dma from 2245 * arbitrary sized buffers, there is a non-obvious restriction 2246 * that a LINK trb is only allowed at the end of a burst of 2247 * transfers - which might be 16kB. 2248 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2249 * The simple solution is not to allow a LINK trb in the middle 2250 * of anything - as here. 2251 * XXX: (dsl) There are xhci controllers out there (eg some made by 2252 * ASMedia) that seem to lock up if they process a LINK trb but 2253 * cannot process the linked-to trb yet. 2254 * The code should write the 'cycle' bit on the link trb AFTER 2255 * adding the other trb. 2256 */ 2257 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2258 parameter = xhci_ring_trbp(xr, 0); 2259 status = 0; 2260 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2261 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2262 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 2263 htole32(status), htole32(control)); 2264 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2265 BUS_DMASYNC_PREWRITE); 2266 xr->xr_cookies[ri] = NULL; 2267 xr->xr_ep = 0; 2268 xr->xr_cs ^= 1; 2269 ri = xr->xr_ep; 2270 cs = xr->xr_cs; 2271 } 2272 2273 ri++; 2274 2275 /* Write any subsequent TRB first */ 2276 for (i = 1; i < ntrbs; i++) { 2277 parameter = trbs[i].trb_0; 2278 status = trbs[i].trb_2; 2279 control = trbs[i].trb_3; 2280 2281 if (cs) { 2282 control |= XHCI_TRB_3_CYCLE_BIT; 2283 } else { 2284 control &= ~XHCI_TRB_3_CYCLE_BIT; 2285 } 2286 2287 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 2288 htole32(status), htole32(control)); 2289 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2290 BUS_DMASYNC_PREWRITE); 2291 xr->xr_cookies[ri] = cookie; 2292 ri++; 2293 } 2294 2295 /* Write the first TRB last */ 2296 i = 0; 2297 parameter = trbs[i].trb_0; 2298 status = trbs[i].trb_2; 2299 control = trbs[i].trb_3; 2300 2301 if (xr->xr_cs) { 2302 control |= XHCI_TRB_3_CYCLE_BIT; 2303 } else { 2304 control &= ~XHCI_TRB_3_CYCLE_BIT; 2305 } 2306 2307 xhci_trb_put(&xr->xr_trb[xr->xr_ep], htole64(parameter), 2308 htole32(status), htole32(control)); 2309 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2310 BUS_DMASYNC_PREWRITE); 2311 xr->xr_cookies[xr->xr_ep] = cookie; 2312 2313 xr->xr_ep = ri; 2314 xr->xr_cs = cs; 2315 2316 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2317 } 2318 2319 /* 2320 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2321 * Command completion is notified by cv_signal from xhci_handle_event 2322 * (called from interrupt from xHCI), or timed-out. 2323 * Command validation is performed in xhci_handle_event by checking if 2324 * trb_0 in CMD_COMPLETE TRB and sc->sc_command_addr are identical. 2325 */ 2326 static usbd_status 2327 xhci_do_command1(struct xhci_softc * const sc, struct xhci_trb * const trb, 2328 int timeout, int locked) 2329 { 2330 struct xhci_ring * const cr = &sc->sc_cr; 2331 usbd_status err; 2332 2333 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2334 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2335 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2336 2337 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2338 2339 if (!locked) 2340 mutex_enter(&sc->sc_lock); 2341 2342 /* XXX KASSERT may fire when cv_timedwait unlocks sc_lock */ 2343 KASSERT(sc->sc_command_addr == 0); 2344 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2345 2346 mutex_enter(&cr->xr_lock); 2347 xhci_ring_put(sc, cr, NULL, trb, 1); 2348 mutex_exit(&cr->xr_lock); 2349 2350 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2351 2352 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2353 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2354 err = USBD_TIMEOUT; 2355 goto timedout; 2356 } 2357 2358 trb->trb_0 = sc->sc_result_trb.trb_0; 2359 trb->trb_2 = sc->sc_result_trb.trb_2; 2360 trb->trb_3 = sc->sc_result_trb.trb_3; 2361 2362 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2363 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2364 2365 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2366 case XHCI_TRB_ERROR_SUCCESS: 2367 err = USBD_NORMAL_COMPLETION; 2368 break; 2369 default: 2370 case 192 ... 223: 2371 err = USBD_IOERROR; 2372 break; 2373 case 224 ... 255: 2374 err = USBD_NORMAL_COMPLETION; 2375 break; 2376 } 2377 2378 timedout: 2379 sc->sc_command_addr = 0; 2380 if (!locked) 2381 mutex_exit(&sc->sc_lock); 2382 return err; 2383 } 2384 2385 static usbd_status 2386 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2387 int timeout) 2388 { 2389 return xhci_do_command1(sc, trb, timeout, 0); 2390 } 2391 2392 /* 2393 * This allows xhci_do_command with already sc_lock held. 2394 * This is needed as USB stack calls close methods with sc_lock_held. 2395 * (see usbdivar.h) 2396 */ 2397 static usbd_status 2398 xhci_do_command_locked(struct xhci_softc * const sc, 2399 struct xhci_trb * const trb, int timeout) 2400 { 2401 return xhci_do_command1(sc, trb, timeout, 1); 2402 } 2403 2404 static usbd_status 2405 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2406 { 2407 struct xhci_trb trb; 2408 usbd_status err; 2409 2410 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2411 2412 trb.trb_0 = 0; 2413 trb.trb_2 = 0; 2414 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2415 2416 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2417 if (err != USBD_NORMAL_COMPLETION) { 2418 return err; 2419 } 2420 2421 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2422 2423 return err; 2424 } 2425 2426 /* 2427 * Deallocate DMA buffer and ring buffer, and disable_slot. 2428 * Should be called with sc_lock held. 2429 */ 2430 static usbd_status 2431 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2432 { 2433 struct xhci_trb trb; 2434 struct xhci_slot *xs; 2435 2436 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2437 2438 if (sc->sc_dying) 2439 return USBD_IOERROR; 2440 2441 xs = &sc->sc_slots[slot]; 2442 if (xs->xs_idx != 0) { 2443 for (int i = XHCI_DCI_SLOT + 1; i < 32; i++) { 2444 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2445 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2446 } 2447 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2448 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2449 } 2450 2451 trb.trb_0 = 0; 2452 trb.trb_2 = 0; 2453 trb.trb_3 = htole32( 2454 XHCI_TRB_3_SLOT_SET(slot) | 2455 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2456 2457 return xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2458 } 2459 2460 /* 2461 * Change slot state. 2462 * bsr=0: ENABLED -> ADDRESSED 2463 * bsr=1: ENABLED -> DEFAULT 2464 * see xHCI 1.1 4.5.3, 3.3.4 2465 */ 2466 static usbd_status 2467 xhci_address_device(struct xhci_softc * const sc, 2468 uint64_t icp, uint8_t slot_id, bool bsr) 2469 { 2470 struct xhci_trb trb; 2471 usbd_status err; 2472 2473 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2474 2475 trb.trb_0 = icp; 2476 trb.trb_2 = 0; 2477 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2478 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2479 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2480 2481 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2482 return err; 2483 } 2484 2485 static usbd_status 2486 xhci_update_ep0_mps(struct xhci_softc * const sc, 2487 struct xhci_slot * const xs, u_int mps) 2488 { 2489 struct xhci_trb trb; 2490 usbd_status err; 2491 uint32_t * cp; 2492 2493 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2494 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2495 2496 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2497 cp[0] = htole32(0); 2498 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2499 2500 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2501 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2502 2503 /* sync input contexts before they are read from memory */ 2504 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2505 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2506 sc->sc_ctxsz * 4); 2507 2508 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2509 trb.trb_2 = 0; 2510 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2511 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2512 2513 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2514 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2515 return err; 2516 } 2517 2518 static void 2519 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2520 { 2521 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2522 2523 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2524 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2525 &dcbaa[si], dcba, si, 0); 2526 2527 dcbaa[si] = htole64(dcba); 2528 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2529 BUS_DMASYNC_PREWRITE); 2530 } 2531 2532 /* 2533 * Allocate DMA buffer and ring buffer for specified slot 2534 * and set Device Context Base Address 2535 * and issue Set Address device command. 2536 */ 2537 static usbd_status 2538 xhci_init_slot(struct usbd_device *dev, uint32_t slot, int route, int rhport) 2539 { 2540 struct xhci_softc * const sc = dev->ud_bus->ub_hcpriv; 2541 struct xhci_slot *xs; 2542 usbd_status err; 2543 u_int dci; 2544 uint32_t *cp; 2545 uint32_t mps = UGETW(dev->ud_ep0desc.wMaxPacketSize); 2546 2547 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2548 DPRINTFN(4, "slot %u speed %d rhport %d route %05x", 2549 slot, dev->ud_speed, route, rhport); 2550 2551 xs = &sc->sc_slots[slot]; 2552 2553 /* allocate contexts */ 2554 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2555 &xs->xs_dc_dma); 2556 if (err) 2557 return err; 2558 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2559 2560 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2561 &xs->xs_ic_dma); 2562 if (err) 2563 goto bad1; 2564 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2565 2566 for (dci = 0; dci < 32; dci++) { 2567 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2568 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2569 if (dci == XHCI_DCI_SLOT) 2570 continue; 2571 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2572 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2573 if (err) { 2574 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2575 goto bad2; 2576 } 2577 } 2578 2579 /* set up initial input control context */ 2580 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2581 cp[0] = htole32(0); 2582 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 2583 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2584 2585 /* set up input slot context */ 2586 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2587 xhci_setup_sctx(dev, cp); 2588 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(1)); 2589 cp[0] |= htole32(XHCI_SCTX_0_ROUTE_SET(route)); 2590 cp[1] |= htole32(XHCI_SCTX_1_RH_PORT_SET(rhport)); 2591 2592 /* set up input EP0 context */ 2593 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2594 cp[0] = htole32(0); 2595 cp[1] = htole32( 2596 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 2597 XHCI_EPCTX_1_EPTYPE_SET(4) | 2598 XHCI_EPCTX_1_CERR_SET(3) 2599 ); 2600 /* can't use xhci_ep_get_dci() yet? */ 2601 *(uint64_t *)(&cp[2]) = htole64( 2602 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 2603 XHCI_EPCTX_2_DCS_SET(1)); 2604 cp[4] = htole32( 2605 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 2606 ); 2607 2608 /* sync input contexts before they are read from memory */ 2609 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2610 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2611 sc->sc_ctxsz * 3); 2612 2613 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2614 2615 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 2616 false); 2617 2618 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2619 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2620 sc->sc_ctxsz * 2); 2621 2622 bad2: 2623 if (err == USBD_NORMAL_COMPLETION) { 2624 xs->xs_idx = slot; 2625 } else { 2626 for (int i = 1; i < dci; i++) { 2627 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2628 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2629 } 2630 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2631 bad1: 2632 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2633 xs->xs_idx = 0; 2634 } 2635 2636 return err; 2637 } 2638 2639 /* ----- */ 2640 2641 static void 2642 xhci_noop(struct usbd_pipe *pipe) 2643 { 2644 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2645 } 2646 2647 /* 2648 * Process root hub request. 2649 */ 2650 static int 2651 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2652 void *buf, int buflen) 2653 { 2654 struct xhci_softc * const sc = bus->ub_hcpriv; 2655 usb_port_status_t ps; 2656 int l, totlen = 0; 2657 uint16_t len, value, index; 2658 int port, i; 2659 uint32_t v; 2660 2661 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2662 2663 if (sc->sc_dying) 2664 return -1; 2665 2666 len = UGETW(req->wLength); 2667 value = UGETW(req->wValue); 2668 index = UGETW(req->wIndex); 2669 2670 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 2671 req->bmRequestType | (req->bRequest << 8), value, index, len); 2672 2673 #define C(x,y) ((x) | ((y) << 8)) 2674 switch (C(req->bRequest, req->bmRequestType)) { 2675 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2676 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 2677 if (len == 0) 2678 break; 2679 switch (value) { 2680 #define sd ((usb_string_descriptor_t *)buf) 2681 case C(2, UDESC_STRING): 2682 /* Product */ 2683 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 2684 break; 2685 #undef sd 2686 default: 2687 /* default from usbroothub */ 2688 return buflen; 2689 } 2690 break; 2691 2692 /* Hub requests */ 2693 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2694 break; 2695 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2696 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2697 index, value, 0, 0); 2698 if (index < 1 || index > sc->sc_maxports) { 2699 return -1; 2700 } 2701 port = XHCI_PORTSC(index); 2702 v = xhci_op_read_4(sc, port); 2703 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2704 v &= ~XHCI_PS_CLEAR; 2705 switch (value) { 2706 case UHF_PORT_ENABLE: 2707 xhci_op_write_4(sc, port, v &~ XHCI_PS_PED); 2708 break; 2709 case UHF_PORT_SUSPEND: 2710 return -1; 2711 case UHF_PORT_POWER: 2712 break; 2713 case UHF_PORT_TEST: 2714 case UHF_PORT_INDICATOR: 2715 return -1; 2716 case UHF_C_PORT_CONNECTION: 2717 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2718 break; 2719 case UHF_C_PORT_ENABLE: 2720 case UHF_C_PORT_SUSPEND: 2721 case UHF_C_PORT_OVER_CURRENT: 2722 return -1; 2723 case UHF_C_BH_PORT_RESET: 2724 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 2725 break; 2726 case UHF_C_PORT_RESET: 2727 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2728 break; 2729 case UHF_C_PORT_LINK_STATE: 2730 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 2731 break; 2732 case UHF_C_PORT_CONFIG_ERROR: 2733 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 2734 break; 2735 default: 2736 return -1; 2737 } 2738 break; 2739 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2740 if (len == 0) 2741 break; 2742 if ((value & 0xff) != 0) { 2743 return -1; 2744 } 2745 usb_hub_descriptor_t hubd; 2746 2747 totlen = min(buflen, sizeof(hubd)); 2748 memcpy(&hubd, buf, totlen); 2749 hubd.bNbrPorts = sc->sc_maxports; 2750 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2751 hubd.bPwrOn2PwrGood = 200; 2752 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 2753 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2754 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2755 totlen = min(totlen, hubd.bDescLength); 2756 memcpy(buf, &hubd, totlen); 2757 break; 2758 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2759 if (len != 4) { 2760 return -1; 2761 } 2762 memset(buf, 0, len); /* ? XXX */ 2763 totlen = len; 2764 break; 2765 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2766 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2767 if (index < 1 || index > sc->sc_maxports) { 2768 return -1; 2769 } 2770 if (len != 4) { 2771 return -1; 2772 } 2773 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 2774 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 2775 switch (XHCI_PS_SPEED_GET(v)) { 2776 case 1: 2777 i = UPS_FULL_SPEED; 2778 break; 2779 case 2: 2780 i = UPS_LOW_SPEED; 2781 break; 2782 case 3: 2783 i = UPS_HIGH_SPEED; 2784 break; 2785 case 4: 2786 i = UPS_SUPER_SPEED; 2787 break; 2788 default: 2789 i = 0; 2790 break; 2791 } 2792 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2793 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2794 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2795 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 2796 if (v & XHCI_PS_PR) i |= UPS_RESET; 2797 if (v & XHCI_PS_PP) { 2798 if (i & UPS_SUPER_SPEED) 2799 i |= UPS_PORT_POWER_SS; 2800 else 2801 i |= UPS_PORT_POWER; 2802 } 2803 USETW(ps.wPortStatus, i); 2804 i = 0; 2805 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2806 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2807 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2808 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2809 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 2810 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 2811 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 2812 USETW(ps.wPortChange, i); 2813 totlen = min(len, sizeof(ps)); 2814 memcpy(buf, &ps, totlen); 2815 break; 2816 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2817 return -1; 2818 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 2819 break; 2820 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2821 break; 2822 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 2823 int optval = (index >> 8) & 0xff; 2824 index &= 0xff; 2825 if (index < 1 || index > sc->sc_maxports) { 2826 return -1; 2827 } 2828 port = XHCI_PORTSC(index); 2829 v = xhci_op_read_4(sc, port); 2830 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2831 v &= ~XHCI_PS_CLEAR; 2832 switch (value) { 2833 case UHF_PORT_ENABLE: 2834 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 2835 break; 2836 case UHF_PORT_SUSPEND: 2837 /* XXX suspend */ 2838 break; 2839 case UHF_PORT_RESET: 2840 v &= ~ (XHCI_PS_PED | XHCI_PS_PR); 2841 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 2842 /* Wait for reset to complete. */ 2843 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2844 if (sc->sc_dying) { 2845 return -1; 2846 } 2847 v = xhci_op_read_4(sc, port); 2848 if (v & XHCI_PS_PR) { 2849 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 2850 usb_delay_ms(&sc->sc_bus, 10); 2851 /* XXX */ 2852 } 2853 break; 2854 case UHF_PORT_POWER: 2855 /* XXX power control */ 2856 break; 2857 /* XXX more */ 2858 case UHF_C_PORT_RESET: 2859 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2860 break; 2861 case UHF_PORT_U1_TIMEOUT: 2862 if (XHCI_PS_SPEED_GET(v) != 4) { 2863 return -1; 2864 } 2865 port = XHCI_PORTPMSC(index); 2866 v = xhci_op_read_4(sc, port); 2867 v &= ~XHCI_PM3_U1TO_SET(0xff); 2868 v |= XHCI_PM3_U1TO_SET(optval); 2869 xhci_op_write_4(sc, port, v); 2870 break; 2871 case UHF_PORT_U2_TIMEOUT: 2872 if (XHCI_PS_SPEED_GET(v) != 4) { 2873 return -1; 2874 } 2875 port = XHCI_PORTPMSC(index); 2876 v = xhci_op_read_4(sc, port); 2877 v &= ~XHCI_PM3_U2TO_SET(0xff); 2878 v |= XHCI_PM3_U2TO_SET(optval); 2879 xhci_op_write_4(sc, port, v); 2880 break; 2881 default: 2882 return -1; 2883 } 2884 } 2885 break; 2886 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2887 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2888 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2889 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2890 break; 2891 default: 2892 /* default from usbroothub */ 2893 return buflen; 2894 } 2895 2896 return totlen; 2897 } 2898 2899 /* root hub interrupt */ 2900 2901 static usbd_status 2902 xhci_root_intr_transfer(struct usbd_xfer *xfer) 2903 { 2904 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2905 usbd_status err; 2906 2907 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2908 2909 /* Insert last in queue. */ 2910 mutex_enter(&sc->sc_lock); 2911 err = usb_insert_transfer(xfer); 2912 mutex_exit(&sc->sc_lock); 2913 if (err) 2914 return err; 2915 2916 /* Pipe isn't running, start first */ 2917 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2918 } 2919 2920 /* Wait for roothub port status/change */ 2921 static usbd_status 2922 xhci_root_intr_start(struct usbd_xfer *xfer) 2923 { 2924 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2925 2926 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2927 2928 if (sc->sc_dying) 2929 return USBD_IOERROR; 2930 2931 mutex_enter(&sc->sc_lock); 2932 sc->sc_intrxfer = xfer; 2933 mutex_exit(&sc->sc_lock); 2934 2935 return USBD_IN_PROGRESS; 2936 } 2937 2938 static void 2939 xhci_root_intr_abort(struct usbd_xfer *xfer) 2940 { 2941 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2942 2943 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2944 2945 KASSERT(mutex_owned(&sc->sc_lock)); 2946 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2947 2948 sc->sc_intrxfer = NULL; 2949 2950 xfer->ux_status = USBD_CANCELLED; 2951 usb_transfer_complete(xfer); 2952 } 2953 2954 static void 2955 xhci_root_intr_close(struct usbd_pipe *pipe) 2956 { 2957 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 2958 2959 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2960 2961 KASSERT(mutex_owned(&sc->sc_lock)); 2962 2963 sc->sc_intrxfer = NULL; 2964 } 2965 2966 static void 2967 xhci_root_intr_done(struct usbd_xfer *xfer) 2968 { 2969 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2970 2971 xfer->ux_hcpriv = NULL; 2972 } 2973 2974 /* -------------- */ 2975 /* device control */ 2976 2977 static usbd_status 2978 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2979 { 2980 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2981 usbd_status err; 2982 2983 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2984 2985 /* Insert last in queue. */ 2986 mutex_enter(&sc->sc_lock); 2987 err = usb_insert_transfer(xfer); 2988 mutex_exit(&sc->sc_lock); 2989 if (err) 2990 return err; 2991 2992 /* Pipe isn't running, start first */ 2993 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2994 } 2995 2996 static usbd_status 2997 xhci_device_ctrl_start(struct usbd_xfer *xfer) 2998 { 2999 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3000 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3001 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3002 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3003 struct xhci_xfer * const xx = (void *)xfer; 3004 usb_device_request_t * const req = &xfer->ux_request; 3005 const bool isread = UT_GET_DIR(req->bmRequestType) == UT_READ; 3006 const uint32_t len = UGETW(req->wLength); 3007 usb_dma_t * const dma = &xfer->ux_dmabuf; 3008 uint64_t parameter; 3009 uint32_t status; 3010 uint32_t control; 3011 u_int i; 3012 3013 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3014 DPRINTFN(12, "req: %04x %04x %04x %04x", 3015 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3016 UGETW(req->wIndex), UGETW(req->wLength)); 3017 3018 /* XXX */ 3019 if (tr->is_halted) { 3020 DPRINTFN(1, "ctrl xfer %p halted: slot %u dci %u", 3021 xfer, xs->xs_idx, dci, 0); 3022 xhci_reset_endpoint(xfer->ux_pipe); 3023 tr->is_halted = false; 3024 xhci_set_dequeue(xfer->ux_pipe); 3025 } 3026 3027 /* we rely on the bottom bits for extra info */ 3028 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 3029 3030 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3031 3032 i = 0; 3033 3034 /* setup phase */ 3035 memcpy(¶meter, req, sizeof(*req)); 3036 parameter = le64toh(parameter); 3037 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3038 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3039 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3040 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3041 XHCI_TRB_3_IDT_BIT; 3042 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3043 3044 if (len == 0) 3045 goto no_data; 3046 3047 /* data phase */ 3048 parameter = DMAADDR(dma, 0); 3049 KASSERT(len <= 0x10000); 3050 status = XHCI_TRB_2_IRQ_SET(0) | 3051 XHCI_TRB_2_TDSZ_SET(1) | 3052 XHCI_TRB_2_BYTES_SET(len); 3053 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3054 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3055 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3056 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3057 3058 parameter = (uintptr_t)xfer | 0x3; 3059 status = XHCI_TRB_2_IRQ_SET(0); 3060 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3061 XHCI_TRB_3_IOC_BIT; 3062 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3063 3064 no_data: 3065 parameter = 0; 3066 status = XHCI_TRB_2_IRQ_SET(0); 3067 /* the status stage has inverted direction */ 3068 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3069 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3070 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3071 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3072 3073 parameter = (uintptr_t)xfer | 0x0; 3074 status = XHCI_TRB_2_IRQ_SET(0); 3075 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3076 XHCI_TRB_3_IOC_BIT; 3077 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3078 3079 mutex_enter(&tr->xr_lock); 3080 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3081 mutex_exit(&tr->xr_lock); 3082 3083 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3084 3085 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3086 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3087 xhci_timeout, xfer); 3088 } 3089 3090 if (sc->sc_bus.ub_usepolling) { 3091 DPRINTFN(1, "polling", 0, 0, 0, 0); 3092 //xhci_waitintr(sc, xfer); 3093 } 3094 3095 return USBD_IN_PROGRESS; 3096 } 3097 3098 static void 3099 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3100 { 3101 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3102 3103 callout_stop(&xfer->ux_callout); /* XXX wrong place */ 3104 3105 } 3106 3107 static void 3108 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3109 { 3110 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3111 3112 xhci_abort_xfer(xfer, USBD_CANCELLED); 3113 } 3114 3115 static void 3116 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3117 { 3118 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3119 3120 (void)xhci_close_pipe(pipe); 3121 } 3122 3123 /* ------------------ */ 3124 /* device isochronous */ 3125 3126 /* ----------- */ 3127 /* device bulk */ 3128 3129 static usbd_status 3130 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3131 { 3132 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3133 usbd_status err; 3134 3135 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3136 3137 /* Insert last in queue. */ 3138 mutex_enter(&sc->sc_lock); 3139 err = usb_insert_transfer(xfer); 3140 mutex_exit(&sc->sc_lock); 3141 if (err) 3142 return err; 3143 3144 /* 3145 * Pipe isn't running (otherwise err would be USBD_INPROG), 3146 * so start it first. 3147 */ 3148 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3149 } 3150 3151 static usbd_status 3152 xhci_device_bulk_start(struct usbd_xfer *xfer) 3153 { 3154 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3155 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3156 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3157 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3158 struct xhci_xfer * const xx = (void *)xfer; 3159 const uint32_t len = xfer->ux_length; 3160 usb_dma_t * const dma = &xfer->ux_dmabuf; 3161 uint64_t parameter; 3162 uint32_t status; 3163 uint32_t control; 3164 u_int i = 0; 3165 3166 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3167 3168 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3169 3170 if (sc->sc_dying) 3171 return USBD_IOERROR; 3172 3173 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3174 3175 parameter = DMAADDR(dma, 0); 3176 /* 3177 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3178 * If the user supplied buffer crosses such a boundary then 2 3179 * (or more) TRB should be used. 3180 * If multiple TRB are used the td_size field must be set correctly. 3181 * For v1.0 devices (like ivy bridge) this is the number of usb data 3182 * blocks needed to complete the transfer. 3183 * Setting it to 1 in the last TRB causes an extra zero-length 3184 * data block be sent. 3185 * The earlier documentation differs, I don't know how it behaves. 3186 */ 3187 KASSERT(len <= 0x10000); 3188 status = XHCI_TRB_2_IRQ_SET(0) | 3189 XHCI_TRB_2_TDSZ_SET(1) | 3190 XHCI_TRB_2_BYTES_SET(len); 3191 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3192 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3193 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3194 3195 mutex_enter(&tr->xr_lock); 3196 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3197 mutex_exit(&tr->xr_lock); 3198 3199 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3200 3201 if (sc->sc_bus.ub_usepolling) { 3202 DPRINTFN(1, "polling", 0, 0, 0, 0); 3203 //xhci_waitintr(sc, xfer); 3204 } 3205 3206 return USBD_IN_PROGRESS; 3207 } 3208 3209 static void 3210 xhci_device_bulk_done(struct usbd_xfer *xfer) 3211 { 3212 #ifdef USB_DEBUG 3213 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3214 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3215 #endif 3216 const u_int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3217 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3218 3219 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3220 3221 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3222 3223 callout_stop(&xfer->ux_callout); /* XXX wrong place */ 3224 3225 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3226 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3227 } 3228 3229 static void 3230 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3231 { 3232 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3233 3234 xhci_abort_xfer(xfer, USBD_CANCELLED); 3235 } 3236 3237 static void 3238 xhci_device_bulk_close(struct usbd_pipe *pipe) 3239 { 3240 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3241 3242 (void)xhci_close_pipe(pipe); 3243 } 3244 3245 /* ---------------- */ 3246 /* device interrupt */ 3247 3248 static usbd_status 3249 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3250 { 3251 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3252 usbd_status err; 3253 3254 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3255 3256 /* Insert last in queue. */ 3257 mutex_enter(&sc->sc_lock); 3258 err = usb_insert_transfer(xfer); 3259 mutex_exit(&sc->sc_lock); 3260 if (err) 3261 return err; 3262 3263 /* 3264 * Pipe isn't running (otherwise err would be USBD_INPROG), 3265 * so start it first. 3266 */ 3267 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3268 } 3269 3270 static usbd_status 3271 xhci_device_intr_start(struct usbd_xfer *xfer) 3272 { 3273 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3274 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3275 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3276 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3277 struct xhci_xfer * const xx = (void *)xfer; 3278 const uint32_t len = xfer->ux_length; 3279 usb_dma_t * const dma = &xfer->ux_dmabuf; 3280 uint64_t parameter; 3281 uint32_t status; 3282 uint32_t control; 3283 u_int i = 0; 3284 3285 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3286 3287 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3288 3289 if (sc->sc_dying) 3290 return USBD_IOERROR; 3291 3292 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3293 3294 parameter = DMAADDR(dma, 0); 3295 KASSERT(len <= 0x10000); 3296 status = XHCI_TRB_2_IRQ_SET(0) | 3297 XHCI_TRB_2_TDSZ_SET(1) | 3298 XHCI_TRB_2_BYTES_SET(len); 3299 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3300 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3301 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3302 3303 mutex_enter(&tr->xr_lock); 3304 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3305 mutex_exit(&tr->xr_lock); 3306 3307 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3308 3309 if (sc->sc_bus.ub_usepolling) { 3310 DPRINTFN(1, "polling", 0, 0, 0, 0); 3311 //xhci_waitintr(sc, xfer); 3312 } 3313 3314 return USBD_IN_PROGRESS; 3315 } 3316 3317 static void 3318 xhci_device_intr_done(struct usbd_xfer *xfer) 3319 { 3320 struct xhci_softc * const sc __diagused = 3321 xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3322 #ifdef USB_DEBUG 3323 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3324 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3325 #endif 3326 const u_int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3327 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3328 3329 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3330 3331 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3332 3333 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3334 3335 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3336 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3337 3338 #if 0 3339 device_printf(sc->sc_dev, ""); 3340 for (size_t i = 0; i < xfer->ux_length; i++) { 3341 printf(" %02x", ((uint8_t const *)xfer->ux_buffer)[i]); 3342 } 3343 printf("\n"); 3344 #endif 3345 3346 if (xfer->ux_pipe->up_repeat) { 3347 xfer->ux_status = xhci_device_intr_start(xfer); 3348 } else { 3349 callout_stop(&xfer->ux_callout); /* XXX */ 3350 } 3351 3352 } 3353 3354 static void 3355 xhci_device_intr_abort(struct usbd_xfer *xfer) 3356 { 3357 struct xhci_softc * const sc __diagused = 3358 xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3359 3360 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3361 3362 KASSERT(mutex_owned(&sc->sc_lock)); 3363 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3364 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3365 xhci_abort_xfer(xfer, USBD_CANCELLED); 3366 } 3367 3368 static void 3369 xhci_device_intr_close(struct usbd_pipe *pipe) 3370 { 3371 //struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 3372 3373 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3374 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3375 3376 (void)xhci_close_pipe(pipe); 3377 } 3378 3379 /* ------------ */ 3380 3381 static void 3382 xhci_timeout(void *addr) 3383 { 3384 struct xhci_xfer * const xx = addr; 3385 struct usbd_xfer * const xfer = &xx->xx_xfer; 3386 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3387 3388 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3389 3390 if (sc->sc_dying) { 3391 return; 3392 } 3393 3394 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 3395 USB_TASKQ_MPSAFE); 3396 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 3397 USB_TASKQ_HC); 3398 } 3399 3400 static void 3401 xhci_timeout_task(void *addr) 3402 { 3403 struct usbd_xfer * const xfer = addr; 3404 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3405 3406 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3407 3408 mutex_enter(&sc->sc_lock); 3409 #if 0 3410 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3411 #else 3412 xfer->ux_status = USBD_TIMEOUT; 3413 usb_transfer_complete(xfer); 3414 #endif 3415 mutex_exit(&sc->sc_lock); 3416 } 3417
Indexes created Wed Oct 01 18:09:54 GMT 2025