xhci.c revision 1.28.2.29
1 /* $NetBSD: xhci.c,v 1.28.2.29 2015/06/23 12:22:35 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 3.1 specification 31 * http://www.usb.org/developers/docs/usb_31_040315.zip 32 * USB rev 2.0 specification 33 * http://www.usb.org/developers/docs/usb20_docs/usb_20_031815.zip 34 * xHCI rev 1.1 specification 35 * http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.28.2.29 2015/06/23 12:22:35 skrll Exp $"); 40 41 #include "opt_usb.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static int xhci_intr1(struct xhci_softc * const); 129 static void xhci_softintr(void *); 130 static void xhci_poll(struct usbd_bus *); 131 static struct usbd_xfer *xhci_allocx(struct usbd_bus *); 132 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 133 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 134 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 135 struct usbd_port *); 136 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 137 void *, int); 138 139 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 140 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 141 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 143 144 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 145 146 static usbd_status xhci_do_command(struct xhci_softc * const, 147 struct xhci_trb * const, int); 148 static usbd_status xhci_do_command1(struct xhci_softc * const, 149 struct xhci_trb * const, int, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t, int, int); 153 static usbd_status xhci_enable_slot(struct xhci_softc * const, 154 uint8_t * const); 155 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 156 static usbd_status xhci_address_device(struct xhci_softc * const, 157 uint64_t, uint8_t, bool); 158 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 159 struct xhci_slot * const, u_int); 160 static usbd_status xhci_ring_init(struct xhci_softc * const, 161 struct xhci_ring * const, size_t, size_t); 162 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 163 164 static void xhci_noop(struct usbd_pipe *); 165 166 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 167 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 168 static void xhci_root_intr_abort(struct usbd_xfer *); 169 static void xhci_root_intr_close(struct usbd_pipe *); 170 static void xhci_root_intr_done(struct usbd_xfer *); 171 172 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 173 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 174 static void xhci_device_ctrl_abort(struct usbd_xfer *); 175 static void xhci_device_ctrl_close(struct usbd_pipe *); 176 static void xhci_device_ctrl_done(struct usbd_xfer *); 177 178 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 179 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 180 static void xhci_device_intr_abort(struct usbd_xfer *); 181 static void xhci_device_intr_close(struct usbd_pipe *); 182 static void xhci_device_intr_done(struct usbd_xfer *); 183 184 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 185 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 186 static void xhci_device_bulk_abort(struct usbd_xfer *); 187 static void xhci_device_bulk_close(struct usbd_pipe *); 188 static void xhci_device_bulk_done(struct usbd_xfer *); 189 190 static void xhci_timeout(void *); 191 static void xhci_timeout_task(void *); 192 193 static const struct usbd_bus_methods xhci_bus_methods = { 194 .ubm_open = xhci_open, 195 .ubm_softint = xhci_softintr, 196 .ubm_dopoll = xhci_poll, 197 .ubm_allocx = xhci_allocx, 198 .ubm_freex = xhci_freex, 199 .ubm_getlock = xhci_get_lock, 200 .ubm_newdev = xhci_new_device, 201 .ubm_rhctrl = xhci_roothub_ctrl, 202 }; 203 204 static const struct usbd_pipe_methods xhci_root_intr_methods = { 205 .upm_transfer = xhci_root_intr_transfer, 206 .upm_start = xhci_root_intr_start, 207 .upm_abort = xhci_root_intr_abort, 208 .upm_close = xhci_root_intr_close, 209 .upm_cleartoggle = xhci_noop, 210 .upm_done = xhci_root_intr_done, 211 }; 212 213 214 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 215 .upm_transfer = xhci_device_ctrl_transfer, 216 .upm_start = xhci_device_ctrl_start, 217 .upm_abort = xhci_device_ctrl_abort, 218 .upm_close = xhci_device_ctrl_close, 219 .upm_cleartoggle = xhci_noop, 220 .upm_done = xhci_device_ctrl_done, 221 }; 222 223 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 224 .upm_cleartoggle = xhci_noop, 225 }; 226 227 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 228 .upm_transfer = xhci_device_bulk_transfer, 229 .upm_start = xhci_device_bulk_start, 230 .upm_abort = xhci_device_bulk_abort, 231 .upm_close = xhci_device_bulk_close, 232 .upm_cleartoggle = xhci_noop, 233 .upm_done = xhci_device_bulk_done, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_intr_methods = { 237 .upm_transfer = xhci_device_intr_transfer, 238 .upm_start = xhci_device_intr_start, 239 .upm_abort = xhci_device_intr_abort, 240 .upm_close = xhci_device_intr_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_intr_done, 243 }; 244 245 static inline uint32_t 246 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 247 { 248 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 249 } 250 251 static inline uint32_t 252 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 253 { 254 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 255 } 256 257 static inline void 258 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 259 uint32_t value) 260 { 261 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 262 } 263 264 #if 0 /* unused */ 265 static inline void 266 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 267 uint32_t value) 268 { 269 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 270 } 271 #endif /* unused */ 272 273 static inline uint32_t 274 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 275 { 276 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 277 } 278 279 static inline uint32_t 280 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 281 { 282 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 283 } 284 285 static inline void 286 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 287 uint32_t value) 288 { 289 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 290 } 291 292 #if 0 /* unused */ 293 static inline uint64_t 294 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 295 { 296 uint64_t value; 297 298 if (sc->sc_ac64) { 299 #ifdef XHCI_USE_BUS_SPACE_8 300 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 301 #else 302 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 303 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 304 offset + 4) << 32; 305 #endif 306 } else { 307 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 308 } 309 310 return value; 311 } 312 #endif /* unused */ 313 314 static inline void 315 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 316 uint64_t value) 317 { 318 if (sc->sc_ac64) { 319 #ifdef XHCI_USE_BUS_SPACE_8 320 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 321 #else 322 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 323 (value >> 0) & 0xffffffff); 324 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 325 (value >> 32) & 0xffffffff); 326 #endif 327 } else { 328 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 329 } 330 } 331 332 static inline uint32_t 333 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 334 { 335 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 336 } 337 338 static inline void 339 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 340 uint32_t value) 341 { 342 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 343 } 344 345 #if 0 /* unused */ 346 static inline uint64_t 347 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 348 { 349 uint64_t value; 350 351 if (sc->sc_ac64) { 352 #ifdef XHCI_USE_BUS_SPACE_8 353 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 354 #else 355 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 356 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 357 offset + 4) << 32; 358 #endif 359 } else { 360 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 361 } 362 363 return value; 364 } 365 #endif /* unused */ 366 367 static inline void 368 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 369 uint64_t value) 370 { 371 if (sc->sc_ac64) { 372 #ifdef XHCI_USE_BUS_SPACE_8 373 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 374 #else 375 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 376 (value >> 0) & 0xffffffff); 377 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 378 (value >> 32) & 0xffffffff); 379 #endif 380 } else { 381 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 382 } 383 } 384 385 #if 0 /* unused */ 386 static inline uint32_t 387 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 388 { 389 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 390 } 391 #endif /* unused */ 392 393 static inline void 394 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 395 uint32_t value) 396 { 397 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 398 } 399 400 /* --- */ 401 402 static inline uint8_t 403 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 404 { 405 u_int eptype = 0; 406 407 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 408 case UE_CONTROL: 409 eptype = 0x0; 410 break; 411 case UE_ISOCHRONOUS: 412 eptype = 0x1; 413 break; 414 case UE_BULK: 415 eptype = 0x2; 416 break; 417 case UE_INTERRUPT: 418 eptype = 0x3; 419 break; 420 } 421 422 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 423 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 424 return eptype | 0x4; 425 else 426 return eptype; 427 } 428 429 static u_int 430 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 431 { 432 /* xHCI 1.0 section 4.5.1 */ 433 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 434 u_int in = 0; 435 436 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 437 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 438 in = 1; 439 440 return epaddr * 2 + in; 441 } 442 443 static inline u_int 444 xhci_dci_to_ici(const u_int i) 445 { 446 return i + 1; 447 } 448 449 static inline void * 450 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 451 const u_int dci) 452 { 453 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 454 } 455 456 #if 0 /* unused */ 457 static inline bus_addr_t 458 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 459 const u_int dci) 460 { 461 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 462 } 463 #endif /* unused */ 464 465 static inline void * 466 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 467 const u_int ici) 468 { 469 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 470 } 471 472 static inline bus_addr_t 473 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline struct xhci_trb * 480 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 481 { 482 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 483 } 484 485 static inline bus_addr_t 486 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 487 { 488 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 489 } 490 491 static inline void 492 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 493 uint32_t control) 494 { 495 trb->trb_0 = parameter; 496 trb->trb_2 = status; 497 trb->trb_3 = control; 498 } 499 500 /* --- */ 501 502 void 503 xhci_childdet(device_t self, device_t child) 504 { 505 struct xhci_softc * const sc = device_private(self); 506 507 KASSERT(sc->sc_child == child); 508 if (child == sc->sc_child) 509 sc->sc_child = NULL; 510 } 511 512 int 513 xhci_detach(struct xhci_softc *sc, int flags) 514 { 515 int rv = 0; 516 517 if (sc->sc_child != NULL) 518 rv = config_detach(sc->sc_child, flags); 519 520 if (rv != 0) 521 return rv; 522 523 /* XXX unconfigure/free slots */ 524 525 /* verify: */ 526 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 527 xhci_op_write_4(sc, XHCI_USBCMD, 0); 528 /* do we need to wait for stop? */ 529 530 xhci_op_write_8(sc, XHCI_CRCR, 0); 531 xhci_ring_free(sc, &sc->sc_cr); 532 cv_destroy(&sc->sc_command_cv); 533 534 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 535 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 536 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 537 xhci_ring_free(sc, &sc->sc_er); 538 539 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 540 541 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 542 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 543 544 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 545 546 mutex_destroy(&sc->sc_lock); 547 mutex_destroy(&sc->sc_intr_lock); 548 cv_destroy(&sc->sc_softwake_cv); 549 550 pool_cache_destroy(sc->sc_xferpool); 551 552 return rv; 553 } 554 555 int 556 xhci_activate(device_t self, enum devact act) 557 { 558 struct xhci_softc * const sc = device_private(self); 559 560 switch (act) { 561 case DVACT_DEACTIVATE: 562 sc->sc_dying = true; 563 return 0; 564 default: 565 return EOPNOTSUPP; 566 } 567 } 568 569 bool 570 xhci_suspend(device_t dv, const pmf_qual_t *qual) 571 { 572 return false; 573 } 574 575 bool 576 xhci_resume(device_t dv, const pmf_qual_t *qual) 577 { 578 return false; 579 } 580 581 bool 582 xhci_shutdown(device_t self, int flags) 583 { 584 return false; 585 } 586 587 588 static void 589 hexdump(const char *msg, const void *base, size_t len) 590 { 591 #if 0 592 size_t cnt; 593 const uint32_t *p; 594 extern paddr_t vtophys(vaddr_t); 595 596 p = base; 597 cnt = 0; 598 599 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 600 (void *)vtophys((vaddr_t)base)); 601 602 while (cnt < len) { 603 if (cnt % 16 == 0) 604 printf("%p: ", p); 605 else if (cnt % 8 == 0) 606 printf(" |"); 607 printf(" %08x", *p++); 608 cnt += 4; 609 if (cnt % 16 == 0) 610 printf("\n"); 611 } 612 #endif 613 } 614 615 616 int 617 xhci_init(struct xhci_softc *sc) 618 { 619 bus_size_t bsz; 620 uint32_t cap, hcs1, hcs2, hcc, dboff, rtsoff; 621 uint32_t ecp, ecr; 622 uint32_t usbcmd, usbsts, pagesize, config; 623 int i; 624 uint16_t hciversion; 625 uint8_t caplength; 626 627 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 628 629 /* XXX Low/Full/High speeds for now */ 630 sc->sc_bus.ub_revision = USBREV_2_0; 631 sc->sc_bus.ub_usedma = true; 632 633 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 634 caplength = XHCI_CAP_CAPLENGTH(cap); 635 hciversion = XHCI_CAP_HCIVERSION(cap); 636 637 if ((hciversion < 0x0096) || (hciversion > 0x0100)) { 638 aprint_normal_dev(sc->sc_dev, 639 "xHCI version %x.%x not known to be supported\n", 640 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 641 } else { 642 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 643 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 644 } 645 646 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 647 &sc->sc_cbh) != 0) { 648 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 649 return ENOMEM; 650 } 651 652 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 653 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 654 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 655 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 656 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 657 (void)xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 658 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 659 660 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 661 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 662 aprint_debug_dev(sc->sc_dev, "ac64 %d ctxsz %d\n", sc->sc_ac64, 663 sc->sc_ctxsz); 664 665 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 666 ecp = XHCI_HCC_XECP(hcc) * 4; 667 while (ecp != 0) { 668 ecr = xhci_read_4(sc, ecp); 669 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 670 switch (XHCI_XECP_ID(ecr)) { 671 case XHCI_ID_PROTOCOLS: { 672 uint32_t w0, w4, w8; 673 uint16_t w2; 674 w0 = xhci_read_4(sc, ecp + 0); 675 w2 = (w0 >> 16) & 0xffff; 676 w4 = xhci_read_4(sc, ecp + 4); 677 w8 = xhci_read_4(sc, ecp + 8); 678 aprint_debug_dev(sc->sc_dev, "SP: %08x %08x %08x\n", 679 w0, w4, w8); 680 if (w4 == 0x20425355 && w2 == 0x0300) { 681 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 682 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 683 } 684 if (w4 == 0x20425355 && w2 == 0x0200) { 685 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 686 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 687 } 688 break; 689 } 690 case XHCI_ID_USB_LEGACY: { 691 uint8_t bios_sem; 692 693 /* Take host controller from BIOS */ 694 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 695 if (bios_sem) { 696 /* sets xHCI to be owned by OS */ 697 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 698 aprint_debug( 699 "waiting for BIOS to give up control\n"); 700 for (i = 0; i < 5000; i++) { 701 bios_sem = xhci_read_1(sc, ecp + 702 XHCI_XECP_BIOS_SEM); 703 if (bios_sem == 0) 704 break; 705 DELAY(1000); 706 } 707 if (bios_sem) 708 printf("timed out waiting for BIOS\n"); 709 } 710 break; 711 } 712 default: 713 break; 714 } 715 ecr = xhci_read_4(sc, ecp); 716 if (XHCI_XECP_NEXT(ecr) == 0) { 717 ecp = 0; 718 } else { 719 ecp += XHCI_XECP_NEXT(ecr) * 4; 720 } 721 } 722 723 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 724 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 725 &sc->sc_obh) != 0) { 726 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 727 return ENOMEM; 728 } 729 730 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 731 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 732 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 733 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 734 return ENOMEM; 735 } 736 737 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 738 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 739 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 740 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 741 return ENOMEM; 742 } 743 744 for (i = 0; i < 100; i++) { 745 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 746 if ((usbsts & XHCI_STS_CNR) == 0) 747 break; 748 usb_delay_ms(&sc->sc_bus, 1); 749 } 750 if (i >= 100) 751 return EIO; 752 753 usbcmd = 0; 754 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 755 usb_delay_ms(&sc->sc_bus, 1); 756 757 usbcmd = XHCI_CMD_HCRST; 758 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 759 for (i = 0; i < 100; i++) { 760 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 761 if ((usbcmd & XHCI_CMD_HCRST) == 0) 762 break; 763 usb_delay_ms(&sc->sc_bus, 1); 764 } 765 if (i >= 100) 766 return EIO; 767 768 for (i = 0; i < 100; i++) { 769 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 770 if ((usbsts & XHCI_STS_CNR) == 0) 771 break; 772 usb_delay_ms(&sc->sc_bus, 1); 773 } 774 if (i >= 100) 775 return EIO; 776 777 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 778 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 779 pagesize = ffs(pagesize); 780 if (pagesize == 0) 781 return EIO; 782 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 783 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 784 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 785 (uint32_t)sc->sc_maxslots); 786 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 787 788 usbd_status err; 789 790 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 791 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 792 if (sc->sc_maxspbuf != 0) { 793 err = usb_allocmem(&sc->sc_bus, 794 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 795 &sc->sc_spbufarray_dma); 796 if (err) 797 return err; 798 799 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * sc->sc_maxspbuf, KM_SLEEP); 800 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 801 for (i = 0; i < sc->sc_maxspbuf; i++) { 802 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 803 /* allocate contexts */ 804 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 805 sc->sc_pgsz, dma); 806 if (err) 807 return err; 808 spbufarray[i] = htole64(DMAADDR(dma, 0)); 809 usb_syncmem(dma, 0, sc->sc_pgsz, 810 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 811 } 812 813 usb_syncmem(&sc->sc_spbufarray_dma, 0, 814 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 815 } 816 817 config = xhci_op_read_4(sc, XHCI_CONFIG); 818 config &= ~0xFF; 819 config |= sc->sc_maxslots & 0xFF; 820 xhci_op_write_4(sc, XHCI_CONFIG, config); 821 822 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 823 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 824 if (err) { 825 aprint_error_dev(sc->sc_dev, "command ring init fail\n"); 826 return err; 827 } 828 829 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 830 XHCI_EVENT_RING_SEGMENTS_ALIGN); 831 if (err) { 832 aprint_error_dev(sc->sc_dev, "event ring init fail\n"); 833 return err; 834 } 835 836 usb_dma_t *dma; 837 size_t size; 838 size_t align; 839 840 dma = &sc->sc_eventst_dma; 841 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 842 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 843 KASSERT(size <= (512 * 1024)); 844 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 845 err = usb_allocmem(&sc->sc_bus, size, align, dma); 846 847 memset(KERNADDR(dma, 0), 0, size); 848 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 849 aprint_debug_dev(sc->sc_dev, "eventst: %s %016jx %p %zx\n", 850 usbd_errstr(err), 851 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 852 KERNADDR(&sc->sc_eventst_dma, 0), 853 sc->sc_eventst_dma.udma_block->size); 854 855 dma = &sc->sc_dcbaa_dma; 856 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 857 KASSERT(size <= 2048); 858 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 859 err = usb_allocmem(&sc->sc_bus, size, align, dma); 860 861 memset(KERNADDR(dma, 0), 0, size); 862 if (sc->sc_maxspbuf != 0) { 863 /* 864 * DCBA entry 0 hold the scratchbuf array pointer. 865 */ 866 *(uint64_t *)KERNADDR(dma, 0) = 867 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 868 } 869 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 870 aprint_debug_dev(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n", 871 usbd_errstr(err), 872 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 873 KERNADDR(&sc->sc_dcbaa_dma, 0), 874 sc->sc_dcbaa_dma.udma_block->size); 875 876 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 877 KM_SLEEP); 878 879 cv_init(&sc->sc_command_cv, "xhcicmd"); 880 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 881 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 882 cv_init(&sc->sc_softwake_cv, "xhciab"); 883 884 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 885 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 886 887 /* Set up the bus struct. */ 888 sc->sc_bus.ub_methods = &xhci_bus_methods; 889 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 890 891 struct xhci_erste *erst; 892 erst = KERNADDR(&sc->sc_eventst_dma, 0); 893 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 894 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 895 erst[0].erste_3 = htole32(0); 896 usb_syncmem(&sc->sc_eventst_dma, 0, 897 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 898 899 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 900 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 901 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 902 XHCI_ERDP_LO_BUSY); 903 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 904 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 905 sc->sc_cr.xr_cs); 906 907 #if 0 908 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 909 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 910 #endif 911 912 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 913 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 914 /* Intel xhci needs interrupt rate moderated. */ 915 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 916 else 917 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 918 aprint_debug_dev(sc->sc_dev, "setting IMOD %u\n", 919 xhci_rt_read_4(sc, XHCI_IMOD(0))); 920 921 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 922 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 923 xhci_op_read_4(sc, XHCI_USBCMD)); 924 925 return USBD_NORMAL_COMPLETION; 926 } 927 928 int 929 xhci_intr(void *v) 930 { 931 struct xhci_softc * const sc = v; 932 int ret = 0; 933 934 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 935 936 if (sc == NULL) 937 return 0; 938 939 mutex_spin_enter(&sc->sc_intr_lock); 940 941 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 942 goto done; 943 944 /* If we get an interrupt while polling, then just ignore it. */ 945 if (sc->sc_bus.ub_usepolling) { 946 #ifdef DIAGNOSTIC 947 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 948 #endif 949 goto done; 950 } 951 952 ret = xhci_intr1(sc); 953 done: 954 mutex_spin_exit(&sc->sc_intr_lock); 955 return ret; 956 } 957 958 int 959 xhci_intr1(struct xhci_softc * const sc) 960 { 961 uint32_t usbsts; 962 uint32_t iman; 963 964 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 965 966 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 967 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 968 #if 0 969 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 970 return 0; 971 } 972 #endif 973 xhci_op_write_4(sc, XHCI_USBSTS, 974 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 975 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 976 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 977 978 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 979 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 980 981 if (!(sc->sc_quirks & XHCI_QUIRK_FORCE_INTR)) { 982 if ((iman & XHCI_IMAN_INTR_PEND) == 0) { 983 return 0; 984 } 985 } 986 987 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 988 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 989 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 990 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 991 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 992 993 usb_schedsoftintr(&sc->sc_bus); 994 995 return 1; 996 } 997 998 /* 999 * 3 port speed types used in USB stack 1000 * 1001 * usbdi speed 1002 * definition: USB_SPEED_* in usb.h 1003 * They are used in struct usbd_device in USB stack. 1004 * ioctl interface uses these values too. 1005 * port_status speed 1006 * definition: UPS_*_SPEED in usb.h 1007 * They are used in usb_port_status_t and valid only for USB 2.0. 1008 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1009 * of usb_port_status_ext_t indicates port speed. 1010 * Note that some 3.0 values overlap with 2.0 values. 1011 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1012 * means UPS_LOW_SPEED in HS.) 1013 * port status returned from hub also uses these values. 1014 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1015 * or more. 1016 * xspeed: 1017 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1018 * They are used in only slot context and PORTSC reg of xhci. 1019 * The difference between usbdi speed and xspeed is 1020 * that FS and LS values are swapped. 1021 */ 1022 1023 /* convert usbdi speed to xspeed */ 1024 static int 1025 xhci_speed2xspeed(int speed) 1026 { 1027 switch (speed) { 1028 case USB_SPEED_LOW: return 2; 1029 case USB_SPEED_FULL: return 1; 1030 default: return speed; 1031 } 1032 } 1033 1034 /* convert xspeed to usbdi speed */ 1035 static int 1036 xhci_xspeed2speed(int xspeed) 1037 { 1038 switch (xspeed) { 1039 case 1: return USB_SPEED_FULL; 1040 case 2: return USB_SPEED_LOW; 1041 default: return xspeed; 1042 } 1043 } 1044 1045 /* convert xspeed to port status speed */ 1046 static int 1047 xhci_xspeed2psspeed(int xspeed) 1048 { 1049 switch (xspeed) { 1050 case 0: return 0; 1051 case 1: return UPS_FULL_SPEED; 1052 case 2: return UPS_LOW_SPEED; 1053 case 3: return UPS_HIGH_SPEED; 1054 default: return UPS_OTHER_SPEED; 1055 } 1056 } 1057 1058 /* construct slot context */ 1059 static void 1060 xhci_setup_sctx(struct usbd_device *dev, uint32_t *cp) 1061 { 1062 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 1063 int speed = dev->ud_speed; 1064 int tthubslot, ttportnum; 1065 bool ishub; 1066 bool usemtt; 1067 1068 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1069 1070 /* 6.2.2 */ 1071 /* 1072 * tthubslot: 1073 * This is the slot ID of parent HS hub 1074 * if LS/FS device is connected && connected through HS hub. 1075 * This is 0 if device is not LS/FS device || 1076 * parent hub is not HS hub || 1077 * attached to root hub. 1078 * ttportnum: 1079 * This is the downstream facing port of parent HS hub 1080 * if LS/FS device is connected. 1081 * This is 0 if device is not LS/FS device || 1082 * parent hub is not HS hub || 1083 * attached to root hub. 1084 */ 1085 if (dev->ud_myhsport != NULL && 1086 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1087 (dev->ud_myhub != NULL && 1088 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1089 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 1090 ttportnum = dev->ud_myhsport->up_portno; 1091 /* XXX addr == slot ? */ 1092 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 1093 } else { 1094 ttportnum = 0; 1095 tthubslot = 0; 1096 } 1097 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 1098 dev->ud_myhsport, ttportnum, tthubslot, 0); 1099 1100 /* ishub is valid after reading UDESC_DEVICE */ 1101 ishub = (dd->bDeviceClass == UDCLASS_HUB); 1102 1103 /* dev->ud_hub is valid after reading UDESC_HUB */ 1104 if (ishub && dev->ud_hub) { 1105 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 1106 1107 cp[1] |= htole32(XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts)); 1108 cp[2] |= htole32(XHCI_SCTX_2_TT_THINK_TIME_SET( 1109 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK))); 1110 DPRINTFN(4, "nports=%d ttt=%d", 1111 hd->bNbrPorts, XHCI_SCTX_2_TT_THINK_TIME_GET(cp[2]), 0, 0); 1112 } 1113 1114 #define IS_TTHUB(dd) \ 1115 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 1116 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 1117 1118 /* 1119 * MTT flag is set if 1120 * 1. this is HS hub && MTT is enabled 1121 * or 1122 * 2. this is not hub && this is LS or FS device && 1123 * MTT of parent HS hub (and its parent, too) is enabled 1124 */ 1125 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 1126 usemtt = true; 1127 else if (!ishub && 1128 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 1129 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1130 (dev->ud_myhub != NULL && 1131 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1132 dev->ud_myhsport != NULL && 1133 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 1134 usemtt = true; 1135 else 1136 usemtt = false; 1137 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 1138 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 1139 1140 cp[0] |= htole32( 1141 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)) | 1142 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 1143 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0) 1144 ); 1145 cp[1] |= htole32(0); 1146 cp[2] |= htole32( 1147 XHCI_SCTX_2_IRQ_TARGET_SET(0) | 1148 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 1149 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum) 1150 ); 1151 cp[3] |= htole32(0); 1152 } 1153 1154 /* 1155 * called 1156 * from xhci_open 1157 * from usbd_setup_pipe_flags 1158 * from usbd_open_pipe_ival 1159 */ 1160 static usbd_status 1161 xhci_configure_endpoint(struct usbd_pipe *pipe) 1162 { 1163 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1164 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1165 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1166 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1167 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1168 struct xhci_trb trb; 1169 usbd_status err; 1170 uint32_t *cp; 1171 uint32_t mps = UGETW(ed->wMaxPacketSize); 1172 uint32_t maxb = 0; 1173 int speed = pipe->up_dev->ud_speed; 1174 uint32_t ival = ed->bInterval; 1175 1176 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1177 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1178 xs->xs_idx, dci, ed->bEndpointAddress, ed->bmAttributes); 1179 1180 /* XXX ensure input context is available? */ 1181 1182 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1183 1184 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1185 cp[0] = htole32(0); 1186 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 1187 1188 /* set up input slot context */ 1189 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1190 xhci_setup_sctx(pipe->up_dev, cp); 1191 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1192 1193 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 1194 cp[0] = htole32( 1195 XHCI_EPCTX_0_EPSTATE_SET(0) | 1196 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 1197 XHCI_EPCTX_0_LSA_SET(0) 1198 ); 1199 cp[1] = htole32( 1200 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 1201 XHCI_EPCTX_1_MAXB_SET(0) 1202 ); 1203 if (xfertype != UE_ISOCHRONOUS) 1204 cp[1] |= htole32(XHCI_EPCTX_1_CERR_SET(3)); 1205 1206 if (USB_IS_SS(speed)) { 1207 usbd_desc_iter_t iter; 1208 const usb_cdc_descriptor_t *cdcd; 1209 const usb_endpoint_ss_comp_descriptor_t * esscd = NULL; 1210 uint8_t ep; 1211 1212 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc( 1213 pipe->up_dev, UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 1214 usb_desc_iter_init(pipe->up_dev, &iter); 1215 iter.cur = (const void *)cdcd; 1216 1217 /* find endpoint_ss_comp desc for ep of this pipe */ 1218 for(ep = 0;;) { 1219 cdcd = (const usb_cdc_descriptor_t *) 1220 usb_desc_iter_next(&iter); 1221 if (cdcd == NULL) 1222 break; 1223 if (ep == 0 && 1224 cdcd->bDescriptorType == UDESC_ENDPOINT) { 1225 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 1226 bEndpointAddress; 1227 if (UE_GET_ADDR(ep) == 1228 UE_GET_ADDR(ed->bEndpointAddress)) { 1229 cdcd = (const usb_cdc_descriptor_t *) 1230 usb_desc_iter_next(&iter); 1231 break; 1232 } 1233 ep = 0; 1234 } 1235 } 1236 if (cdcd != NULL && 1237 cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 1238 esscd = (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 1239 maxb = esscd->bMaxBurst; 1240 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1241 DPRINTFN(4, "setting SS MaxBurst %u", maxb, 0, 0, 0); 1242 } 1243 } 1244 if (speed == USB_SPEED_HIGH && 1245 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 1246 maxb = UE_GET_TRANS(UGETW(ed->wMaxPacketSize)); 1247 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1248 DPRINTFN(4, "setting HS MaxBurst %u", maxb, 0, 0, 0); 1249 } 1250 1251 switch (xfertype) { 1252 case UE_INTERRUPT: 1253 /* 6.2.3.6 */ 1254 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 1255 ival = ival > 10 ? 10 : ival; 1256 ival = ival < 3 ? 3 : ival; 1257 } else { 1258 ival = ival > 15 ? 15 : ival; 1259 } 1260 if (USB_IS_SS(speed)) { 1261 if (maxb > 0) 1262 mps = 1024; 1263 } else { 1264 mps = mps ? mps : 8; 1265 } 1266 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1267 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1268 cp[4] = htole32( 1269 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) /* XXX */ 1270 ); 1271 break; 1272 case UE_CONTROL: 1273 if (USB_IS_SS(speed)) 1274 mps = 512; 1275 else 1276 mps = mps ? mps : 8; 1277 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1278 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(8)); /* XXX */ 1279 break; 1280 #ifdef notyet 1281 case UE_ISOCHRONOUS: 1282 if (speed == USB_SPEED_FULL) { 1283 ival = ival > 18 ? 18 : ival; 1284 ival = ival < 3 ? 3 : ival; 1285 } else { 1286 ival = ival > 15 ? 15 : ival; 1287 } 1288 if (USB_IS_SS(speed)) { 1289 mps = 1024; 1290 } else { 1291 mps = mps ? mps : 1024; 1292 } 1293 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1294 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(1024)); /* XXX */ 1295 break; 1296 #endif 1297 default: 1298 if (USB_IS_SS(speed)) 1299 mps = 1024; 1300 else 1301 mps = mps ? mps : 512; 1302 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1303 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(1024)); /* XXX */ 1304 break; 1305 } 1306 *(uint64_t *)(&cp[2]) = htole64( 1307 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 1308 XHCI_EPCTX_2_DCS_SET(1)); 1309 1310 /* sync input contexts before they are read from memory */ 1311 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1312 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1313 sc->sc_ctxsz * 1); 1314 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1315 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1316 1317 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1318 trb.trb_2 = 0; 1319 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1320 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1321 1322 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1323 1324 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1325 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1326 sc->sc_ctxsz * 1); 1327 1328 return err; 1329 } 1330 1331 #if 0 1332 static usbd_status 1333 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1334 { 1335 #ifdef USB_DEBUG 1336 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1337 #endif 1338 1339 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1340 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1341 1342 return USBD_NORMAL_COMPLETION; 1343 } 1344 #endif 1345 1346 /* 4.6.8, 6.4.3.7 */ 1347 static usbd_status 1348 xhci_reset_endpoint(struct usbd_pipe *pipe) 1349 { 1350 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1351 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1352 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1353 struct xhci_trb trb; 1354 usbd_status err; 1355 1356 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1357 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1358 1359 KASSERT(!mutex_owned(&sc->sc_lock)); 1360 1361 trb.trb_0 = 0; 1362 trb.trb_2 = 0; 1363 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1364 XHCI_TRB_3_EP_SET(dci) | 1365 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1366 1367 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1368 1369 return err; 1370 } 1371 1372 /* 1373 * 4.6.9, 6.4.3.8 1374 * Stop execution of TDs on xfer ring. 1375 * Should be called with sc_lock held. 1376 */ 1377 static usbd_status 1378 xhci_stop_endpoint(struct usbd_pipe *pipe) 1379 { 1380 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1381 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1382 struct xhci_trb trb; 1383 usbd_status err; 1384 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1385 1386 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1387 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1388 1389 KASSERT(mutex_owned(&sc->sc_lock)); 1390 1391 trb.trb_0 = 0; 1392 trb.trb_2 = 0; 1393 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1394 XHCI_TRB_3_EP_SET(dci) | 1395 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1396 1397 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1398 1399 return err; 1400 } 1401 1402 /* 1403 * Set TR Dequeue Pointer. 1404 * xCHI 1.1 4.6.10 6.4.3.9 1405 * Purge all of the transfer requests on ring. 1406 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1407 * error will be generated. 1408 */ 1409 static usbd_status 1410 xhci_set_dequeue(struct usbd_pipe *pipe) 1411 { 1412 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1413 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1414 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1415 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1416 struct xhci_trb trb; 1417 usbd_status err; 1418 1419 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1420 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1421 1422 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1423 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1424 BUS_DMASYNC_PREWRITE); 1425 1426 xr->xr_ep = 0; 1427 xr->xr_cs = 1; 1428 1429 /* set DCS */ 1430 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1431 trb.trb_2 = 0; 1432 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1433 XHCI_TRB_3_EP_SET(dci) | 1434 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1435 1436 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1437 1438 return err; 1439 } 1440 1441 /* 1442 * Open new pipe: called from usbd_setup_pipe_flags. 1443 * Fills methods of pipe. 1444 * If pipe is not for ep0, calls configure_endpoint. 1445 */ 1446 static usbd_status 1447 xhci_open(struct usbd_pipe *pipe) 1448 { 1449 struct usbd_device * const dev = pipe->up_dev; 1450 struct xhci_softc * const sc = dev->ud_bus->ub_hcpriv; 1451 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1452 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1453 1454 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1455 DPRINTFN(1, "addr %d depth %d port %d speed %d", 1456 dev->ud_addr, dev->ud_depth, dev->ud_powersrc->up_portno, 1457 dev->ud_speed); 1458 1459 if (sc->sc_dying) 1460 return USBD_IOERROR; 1461 1462 /* Root Hub */ 1463 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1464 switch (ed->bEndpointAddress) { 1465 case USB_CONTROL_ENDPOINT: 1466 pipe->up_methods = &roothub_ctrl_methods; 1467 break; 1468 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1469 pipe->up_methods = &xhci_root_intr_methods; 1470 break; 1471 default: 1472 pipe->up_methods = NULL; 1473 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1474 ed->bEndpointAddress, 0, 0, 0); 1475 return USBD_INVAL; 1476 } 1477 return USBD_NORMAL_COMPLETION; 1478 } 1479 1480 switch (xfertype) { 1481 case UE_CONTROL: 1482 pipe->up_methods = &xhci_device_ctrl_methods; 1483 break; 1484 case UE_ISOCHRONOUS: 1485 pipe->up_methods = &xhci_device_isoc_methods; 1486 return USBD_INVAL; 1487 break; 1488 case UE_BULK: 1489 pipe->up_methods = &xhci_device_bulk_methods; 1490 break; 1491 case UE_INTERRUPT: 1492 pipe->up_methods = &xhci_device_intr_methods; 1493 break; 1494 default: 1495 return USBD_IOERROR; 1496 break; 1497 } 1498 1499 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1500 return xhci_configure_endpoint(pipe); 1501 1502 return USBD_NORMAL_COMPLETION; 1503 } 1504 1505 /* 1506 * Closes pipe, called from usbd_kill_pipe via close methods. 1507 * If the endpoint to be closed is ep0, disable_slot. 1508 * Should be called with sc_lock held. 1509 */ 1510 static usbd_status 1511 xhci_close_pipe(struct usbd_pipe *pipe) 1512 { 1513 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1514 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1515 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1516 const u_int dci = xhci_ep_get_dci(ed); 1517 struct xhci_trb trb; 1518 usbd_status err; 1519 uint32_t *cp; 1520 1521 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1522 1523 if (sc->sc_dying) 1524 return USBD_IOERROR; 1525 1526 if (xs == NULL || xs->xs_idx == 0) 1527 /* xs is uninitialized before xhci_init_slot */ 1528 return USBD_IOERROR; 1529 1530 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1531 1532 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1533 KASSERT(mutex_owned(&sc->sc_lock)); 1534 1535 if (pipe->up_dev->ud_depth == 0) 1536 return USBD_NORMAL_COMPLETION; 1537 1538 if (dci == XHCI_DCI_EP_CONTROL) { 1539 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1540 return xhci_disable_slot(sc, xs->xs_idx); 1541 } 1542 1543 /* 1544 * This may fail in the case that xhci_close_pipe is called after 1545 * xhci_abort_xfer e.g. usbd_kill_pipe. 1546 */ 1547 (void)xhci_stop_endpoint(pipe); 1548 1549 /* 1550 * set appropriate bit to be dropped. 1551 * don't set DC bit to 1, otherwise all endpoints 1552 * would be deconfigured. 1553 */ 1554 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1555 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1556 cp[1] = htole32(0); 1557 1558 /* XXX should be most significant one, not dci? */ 1559 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1560 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1561 1562 /* sync input contexts before they are read from memory */ 1563 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1564 1565 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1566 trb.trb_2 = 0; 1567 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1568 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1569 1570 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1571 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1572 1573 return err; 1574 } 1575 1576 /* 1577 * Abort transfer. 1578 * Called with sc_lock held. 1579 * May be called from softintr context. 1580 */ 1581 static void 1582 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1583 { 1584 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1585 1586 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1587 DPRINTFN(4, "xfer %p pipe %p status %d", 1588 xfer, xfer->ux_pipe, status, 0); 1589 1590 KASSERT(mutex_owned(&sc->sc_lock)); 1591 1592 if (sc->sc_dying) { 1593 /* If we're dying, just do the software part. */ 1594 DPRINTFN(4, "dying", 0, 0, 0, 0); 1595 xfer->ux_status = status; /* make software ignore it */ 1596 callout_stop(&xfer->ux_callout); 1597 usb_transfer_complete(xfer); 1598 return; 1599 } 1600 1601 /* XXX need more stuff */ 1602 xfer->ux_status = status; 1603 callout_stop(&xfer->ux_callout); 1604 usb_transfer_complete(xfer); 1605 1606 KASSERT(mutex_owned(&sc->sc_lock)); 1607 } 1608 1609 #if 1 /* XXX experimental */ 1610 /* 1611 * Recover STALLed endpoint. 1612 * xHCI 1.1 sect 4.10.2.1 1613 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1614 * all transfers on transfer ring. 1615 * These are done in thread context asynchronously. 1616 */ 1617 static void 1618 xhci_clear_endpoint_stall_async_task(void *cookie) 1619 { 1620 struct usbd_xfer * const xfer = cookie; 1621 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1622 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1623 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1624 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1625 1626 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1627 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1628 1629 xhci_reset_endpoint(xfer->ux_pipe); 1630 xhci_set_dequeue(xfer->ux_pipe); 1631 1632 mutex_enter(&sc->sc_lock); 1633 tr->is_halted = false; 1634 usb_transfer_complete(xfer); 1635 mutex_exit(&sc->sc_lock); 1636 DPRINTFN(4, "ends", 0, 0, 0, 0); 1637 } 1638 1639 static usbd_status 1640 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1641 { 1642 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1643 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1644 1645 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1646 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1647 1648 if (sc->sc_dying) { 1649 return USBD_IOERROR; 1650 } 1651 1652 usb_init_task(&xp->xp_async_task, 1653 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1654 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1655 DPRINTFN(4, "ends", 0, 0, 0, 0); 1656 1657 return USBD_NORMAL_COMPLETION; 1658 } 1659 1660 #endif /* XXX experimental */ 1661 1662 /* 1663 * Notify roothub port status/change to uhub_intr. 1664 */ 1665 static void 1666 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1667 { 1668 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1669 uint8_t *p; 1670 1671 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1672 DPRINTFN(4, "port %u status change", port, 0, 0, 0); 1673 1674 if (xfer == NULL) 1675 return; 1676 1677 p = xfer->ux_buf; 1678 memset(p, 0, xfer->ux_length); 1679 p[port/NBBY] |= 1 << (port%NBBY); 1680 xfer->ux_actlen = xfer->ux_length; 1681 xfer->ux_status = USBD_NORMAL_COMPLETION; 1682 usb_transfer_complete(xfer); 1683 } 1684 1685 /* 1686 * Process events: 1687 * + Transfer comeplete 1688 * + Command complete 1689 * + Roothub Port status/change 1690 */ 1691 static void 1692 xhci_handle_event(struct xhci_softc * const sc, 1693 const struct xhci_trb * const trb) 1694 { 1695 uint64_t trb_0; 1696 uint32_t trb_2, trb_3; 1697 uint8_t trberr; 1698 1699 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1700 1701 trb_0 = le64toh(trb->trb_0); 1702 trb_2 = le32toh(trb->trb_2); 1703 trb_3 = le32toh(trb->trb_3); 1704 trberr = XHCI_TRB_2_ERROR_GET(trb_2); 1705 1706 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1707 trb, trb_0, trb_2, trb_3); 1708 1709 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 1710 case XHCI_TRB_EVENT_TRANSFER: { 1711 u_int slot, dci; 1712 struct xhci_slot *xs; 1713 struct xhci_ring *xr; 1714 struct xhci_xfer *xx; 1715 struct usbd_xfer *xfer; 1716 usbd_status err; 1717 1718 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1719 dci = XHCI_TRB_3_EP_GET(trb_3); 1720 1721 xs = &sc->sc_slots[slot]; 1722 xr = &xs->xs_ep[dci].xe_tr; 1723 /* sanity check */ 1724 if (xs->xs_idx == 0 || xs->xs_idx >= sc->sc_maxslots) { 1725 DPRINTFN(1, "invalid slot %u", xs->xs_idx, 0, 0, 0); 1726 break; 1727 } 1728 1729 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1730 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 1731 1732 /* trb_0 range sanity check */ 1733 if (trb_0 < trbp || 1734 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 1735 (trb_0 - trbp) / sizeof(struct xhci_trb) >= 1736 xr->xr_ntrb) { 1737 DPRINTFN(1, 1738 "invalid trb_0 0x%"PRIx64" trbp 0x%"PRIx64, 1739 trb_0, trbp, 0, 0); 1740 break; 1741 } 1742 int idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 1743 xx = xr->xr_cookies[idx]; 1744 } else { 1745 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1746 } 1747 /* 1748 * stop_endpoint may cause ERR_STOPPED_LENGTH_INVALID, 1749 * in which case this condition may happen. 1750 */ 1751 if (xx == NULL) { 1752 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1753 break; 1754 } 1755 xfer = &xx->xx_xfer; 1756 /* XXX this may happen when detaching */ 1757 if (xfer == NULL) { 1758 DPRINTFN(1, "xfer done: xfer is NULL", 0, 0, 0, 0); 1759 break; 1760 } 1761 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1762 /* XXX I dunno why this happens */ 1763 if (!xfer->ux_pipe->up_repeat && 1764 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1765 DPRINTFN(1, "xfer done: xfer not started", 0, 0, 0, 0); 1766 break; 1767 } 1768 1769 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1770 DPRINTFN(14, "transfer event data: " 1771 "0x%016"PRIx64" 0x%08"PRIx32" %02x", 1772 trb_0, XHCI_TRB_2_REM_GET(trb_2), 1773 XHCI_TRB_2_ERROR_GET(trb_2), 0); 1774 if ((trb_0 & 0x3) == 0x3) { 1775 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1776 } 1777 } 1778 1779 switch (trberr) { 1780 case XHCI_TRB_ERROR_SHORT_PKT: 1781 case XHCI_TRB_ERROR_SUCCESS: 1782 xfer->ux_actlen = 1783 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1784 err = USBD_NORMAL_COMPLETION; 1785 break; 1786 case XHCI_TRB_ERROR_STALL: 1787 case XHCI_TRB_ERROR_BABBLE: 1788 DPRINTFN(1, "evh: xfer done: ERR %u slot %u dci %u", 1789 trberr, slot, dci, 0); 1790 xr->is_halted = true; 1791 err = USBD_STALLED; 1792 #if 1 /* XXX experimental */ 1793 /* 1794 * Stalled endpoints can be recoverd by issuing 1795 * command TRB TYPE_RESET_EP on xHCI instead of 1796 * issuing request CLEAR_PORT_FEATURE UF_ENDPOINT_HALT 1797 * on the endpoint. However, this function may be 1798 * called from softint context (e.g. from umass), 1799 * in that case driver gets KASSERT in cv_timedwait 1800 * in xhci_do_command. 1801 * To avoid this, this runs reset_endpoint and 1802 * usb_transfer_complete in usb task thread 1803 * asynchronously (and then umass issues clear 1804 * UF_ENDPOINT_HALT). 1805 */ 1806 xfer->ux_status = err; 1807 xhci_clear_endpoint_stall_async(xfer); 1808 return; 1809 #else 1810 break; 1811 #endif 1812 case XHCI_TRB_ERROR_CMD_ABORTED: 1813 case XHCI_TRB_ERROR_STOPPED: 1814 err = USBD_CANCELLED; 1815 break; 1816 case XHCI_TRB_ERROR_NO_SLOTS: 1817 err = USBD_NO_ADDR; 1818 break; 1819 default: 1820 DPRINTFN(1, "evh: xfer done: ERR %u slot %u dci %u", 1821 trberr, slot, dci, 0); 1822 err = USBD_IOERROR; 1823 break; 1824 } 1825 xfer->ux_status = err; 1826 1827 //mutex_enter(&sc->sc_lock); /* XXX ??? */ 1828 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1829 if ((trb_0 & 0x3) == 0x0) { 1830 usb_transfer_complete(xfer); 1831 } 1832 } else { 1833 usb_transfer_complete(xfer); 1834 } 1835 //mutex_exit(&sc->sc_lock); /* XXX ??? */ 1836 1837 } 1838 break; 1839 case XHCI_TRB_EVENT_CMD_COMPLETE: 1840 if (trb_0 == sc->sc_command_addr) { 1841 sc->sc_result_trb.trb_0 = trb_0; 1842 sc->sc_result_trb.trb_2 = trb_2; 1843 sc->sc_result_trb.trb_3 = trb_3; 1844 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1845 XHCI_TRB_ERROR_SUCCESS) { 1846 DPRINTFN(1, "command completion " 1847 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1848 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1849 } 1850 cv_signal(&sc->sc_command_cv); 1851 } else { 1852 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 1853 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1854 trb_2, trb_3); 1855 } 1856 break; 1857 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1858 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1859 break; 1860 default: 1861 break; 1862 } 1863 } 1864 1865 static void 1866 xhci_softintr(void *v) 1867 { 1868 struct usbd_bus * const bus = v; 1869 struct xhci_softc * const sc = bus->ub_hcpriv; 1870 struct xhci_ring * const er = &sc->sc_er; 1871 struct xhci_trb *trb; 1872 int i, j, k; 1873 1874 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1875 1876 i = er->xr_ep; 1877 j = er->xr_cs; 1878 1879 DPRINTFN(16, "xr_ep %d xr_cs %d", i, j, 0, 0); 1880 1881 while (1) { 1882 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 1883 BUS_DMASYNC_POSTREAD); 1884 trb = &er->xr_trb[i]; 1885 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1886 1887 if (j != k) 1888 break; 1889 1890 xhci_handle_event(sc, trb); 1891 1892 i++; 1893 if (i == XHCI_EVENT_RING_TRBS) { 1894 i = 0; 1895 j ^= 1; 1896 } 1897 } 1898 1899 er->xr_ep = i; 1900 er->xr_cs = j; 1901 1902 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 1903 XHCI_ERDP_LO_BUSY); 1904 1905 DPRINTFN(16, "ends", 0, 0, 0, 0); 1906 1907 return; 1908 } 1909 1910 static void 1911 xhci_poll(struct usbd_bus *bus) 1912 { 1913 struct xhci_softc * const sc = bus->ub_hcpriv; 1914 1915 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1916 1917 mutex_spin_enter(&sc->sc_intr_lock); 1918 xhci_intr1(sc); 1919 mutex_spin_exit(&sc->sc_intr_lock); 1920 1921 return; 1922 } 1923 1924 static struct usbd_xfer * 1925 xhci_allocx(struct usbd_bus *bus) 1926 { 1927 struct xhci_softc * const sc = bus->ub_hcpriv; 1928 struct usbd_xfer *xfer; 1929 1930 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1931 1932 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1933 if (xfer != NULL) { 1934 memset(xfer, 0, sizeof(struct xhci_xfer)); 1935 #ifdef DIAGNOSTIC 1936 xfer->ux_state = XFER_BUSY; 1937 #endif 1938 } 1939 1940 return xfer; 1941 } 1942 1943 static void 1944 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1945 { 1946 struct xhci_softc * const sc = bus->ub_hcpriv; 1947 1948 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1949 1950 #ifdef DIAGNOSTIC 1951 if (xfer->ux_state != XFER_BUSY) { 1952 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 1953 xfer, xfer->ux_state, 0, 0); 1954 } 1955 xfer->ux_state = XFER_FREE; 1956 #endif 1957 pool_cache_put(sc->sc_xferpool, xfer); 1958 } 1959 1960 static void 1961 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1962 { 1963 struct xhci_softc * const sc = bus->ub_hcpriv; 1964 1965 *lock = &sc->sc_lock; 1966 } 1967 1968 extern uint32_t usb_cookie_no; 1969 1970 /* 1971 * Called if uhub_explore find new device (via usbd_new_device). 1972 * Allocate and construct dev structure of default endpoint (ep0). 1973 * Determine initial MaxPacketSize (mps) by speed. 1974 * Determine route string and roothub port for slot of dev. 1975 * Allocate pipe of ep0. 1976 * Enable and initialize slot and Set Address. 1977 * Read device descriptor. 1978 * Register this device. 1979 */ 1980 static usbd_status 1981 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 1982 int speed, int port, struct usbd_port *up) 1983 { 1984 struct xhci_softc * const sc = bus->ub_hcpriv; 1985 struct usbd_device *dev; 1986 usbd_status err; 1987 usb_device_descriptor_t *dd; 1988 struct usbd_device *hub; 1989 struct usbd_device *adev; 1990 int rhport = 0; 1991 struct xhci_slot *xs; 1992 uint32_t *cp; 1993 uint32_t route = 0; 1994 uint8_t slot = 0; 1995 uint8_t addr; 1996 1997 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1998 DPRINTFN(4, "port=%d depth=%d speed=%d upport %d", 1999 port, depth, speed, up->up_portno); 2000 2001 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2002 if (dev == NULL) 2003 return USBD_NOMEM; 2004 2005 dev->ud_bus = bus; 2006 2007 /* Set up default endpoint handle. */ 2008 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2009 2010 /* Set up default endpoint descriptor. */ 2011 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2012 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2013 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2014 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2015 /* 4.3, 4.8.2.1 */ 2016 if (USB_IS_SS(speed)) { 2017 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2018 } else 2019 switch (speed) { 2020 case USB_SPEED_FULL: 2021 /* XXX using 64 as initial mps of ep0 in FS */ 2022 case USB_SPEED_HIGH: 2023 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2024 break; 2025 case USB_SPEED_LOW: 2026 default: 2027 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2028 break; 2029 } 2030 dev->ud_ep0desc.bInterval = 0; 2031 2032 /* doesn't matter, just don't let it uninitialized */ 2033 dev->ud_ep0.ue_toggle = 0; 2034 2035 DPRINTFN(4, "up %p portno %d", up, up->up_portno, 0, 0); 2036 2037 dev->ud_quirks = &usbd_no_quirk; 2038 dev->ud_addr = 0; 2039 dev->ud_ddesc.bMaxPacketSize = 0; 2040 dev->ud_depth = depth; 2041 dev->ud_powersrc = up; 2042 dev->ud_myhub = up->up_parent; 2043 2044 up->up_dev = dev; 2045 2046 /* Locate root hub port */ 2047 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2048 uint32_t dep; 2049 2050 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2051 hub, hub->ud_depth, hub->ud_powersrc, 2052 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2053 2054 if (hub->ud_powersrc == NULL) 2055 break; 2056 dep = hub->ud_depth; 2057 if (dep == 0) 2058 break; 2059 rhport = hub->ud_powersrc->up_portno; 2060 if (dep > USB_HUB_MAX_DEPTH) 2061 continue; 2062 2063 route |= 2064 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2065 << ((dep - 1) * 4); 2066 } 2067 route = route >> 4; 2068 DPRINTFN(4, "rhport %d Route %05x hub %p", rhport, route, hub, 0); 2069 2070 /* Locate port on upstream high speed hub */ 2071 for (adev = dev, hub = up->up_parent; 2072 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2073 adev = hub, hub = hub->ud_myhub) 2074 ; 2075 if (hub) { 2076 int p; 2077 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2078 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2079 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2080 goto found; 2081 } 2082 } 2083 panic("xhci_new_device: cannot find HS port"); 2084 found: 2085 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2086 } else { 2087 dev->ud_myhsport = NULL; 2088 } 2089 2090 dev->ud_speed = speed; 2091 dev->ud_langid = USBD_NOLANG; 2092 dev->ud_cookie.cookie = ++usb_cookie_no; 2093 2094 /* Establish the default pipe. */ 2095 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2096 &dev->ud_pipe0); 2097 if (err) { 2098 goto bad; 2099 } 2100 2101 dd = &dev->ud_ddesc; 2102 2103 if ((depth == 0) && (port == 0)) { 2104 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2105 bus->ub_devices[dev->ud_addr] = dev; 2106 err = usbd_get_initial_ddesc(dev, dd); 2107 if (err) 2108 goto bad; 2109 err = usbd_reload_device_desc(dev); 2110 if (err) 2111 goto bad; 2112 } else { 2113 err = xhci_enable_slot(sc, &slot); 2114 if (err) 2115 goto bad; 2116 xs = &sc->sc_slots[slot]; 2117 dev->ud_hcpriv = xs; 2118 err = xhci_init_slot(dev, slot, route, rhport); 2119 if (err) { 2120 dev->ud_hcpriv = NULL; 2121 /* 2122 * We have to disable_slot here because 2123 * xs->xs_idx == 0 when xhci_init_slot fails, 2124 * in that case usbd_remove_dev won't work. 2125 */ 2126 mutex_enter(&sc->sc_lock); 2127 xhci_disable_slot(sc, slot); 2128 mutex_exit(&sc->sc_lock); 2129 goto bad; 2130 } 2131 2132 /* Allow device time to set new address */ 2133 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2134 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2135 //hexdump("slot context", cp, sc->sc_ctxsz); 2136 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2137 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2138 /* XXX ensure we know when the hardware does something 2139 we can't yet cope with */ 2140 KASSERT(addr >= 1 && addr <= 127); 2141 dev->ud_addr = addr; 2142 /* XXX dev->ud_addr not necessarily unique on bus */ 2143 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2144 bus->ub_devices[dev->ud_addr] = dev; 2145 2146 /* read 64 bytes of device descriptor */ 2147 err = usbd_get_initial_ddesc(dev, dd); 2148 if (err) 2149 goto bad; 2150 /* 4.8.2.1 */ 2151 if (USB_IS_SS(speed)) { 2152 if (dd->bMaxPacketSize != 9) { 2153 printf("%s: invalid mps 2^%u for SS ep0," 2154 " using 512\n", 2155 device_xname(sc->sc_dev), 2156 dd->bMaxPacketSize); 2157 dd->bMaxPacketSize = 9; 2158 } 2159 USETW(dev->ud_ep0desc.wMaxPacketSize, 2160 (1 << dd->bMaxPacketSize)); 2161 } else 2162 USETW(dev->ud_ep0desc.wMaxPacketSize, 2163 dd->bMaxPacketSize); 2164 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2165 xhci_update_ep0_mps(sc, xs, 2166 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2167 err = usbd_reload_device_desc(dev); 2168 if (err) 2169 goto bad; 2170 2171 #if 0 2172 /* Re-establish the default pipe with the new MPS. */ 2173 /* In xhci this is done by xhci_update_ep0_mps. */ 2174 usbd_kill_pipe(dev->ud_pipe0); 2175 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2176 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2177 #endif 2178 } 2179 2180 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2181 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2182 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2183 dd->bDeviceClass, dd->bDeviceSubClass, 2184 dd->bDeviceProtocol, 0); 2185 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2186 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2187 dev->ud_speed); 2188 2189 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2190 2191 if ((depth == 0) && (port == 0)) { 2192 usbd_attach_roothub(parent, dev); 2193 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2194 return USBD_NORMAL_COMPLETION; 2195 } 2196 2197 2198 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2199 bad: 2200 if (err != USBD_NORMAL_COMPLETION) { 2201 usbd_remove_device(dev, up); 2202 } 2203 2204 return err; 2205 } 2206 2207 static usbd_status 2208 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2209 size_t ntrb, size_t align) 2210 { 2211 usbd_status err; 2212 size_t size = ntrb * XHCI_TRB_SIZE; 2213 2214 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2215 2216 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2217 if (err) 2218 return err; 2219 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2220 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2221 xr->xr_trb = xhci_ring_trbv(xr, 0); 2222 xr->xr_ntrb = ntrb; 2223 xr->xr_ep = 0; 2224 xr->xr_cs = 1; 2225 memset(xr->xr_trb, 0, size); 2226 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 2227 xr->is_halted = false; 2228 2229 return USBD_NORMAL_COMPLETION; 2230 } 2231 2232 static void 2233 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2234 { 2235 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2236 mutex_destroy(&xr->xr_lock); 2237 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2238 } 2239 2240 static void 2241 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2242 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2243 { 2244 size_t i; 2245 u_int ri; 2246 u_int cs; 2247 uint64_t parameter; 2248 uint32_t status; 2249 uint32_t control; 2250 2251 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2252 2253 for (i = 0; i < ntrbs; i++) { 2254 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2255 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2256 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2257 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2258 XHCI_TRB_TYPE_LINK); 2259 } 2260 2261 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2262 2263 ri = xr->xr_ep; 2264 cs = xr->xr_cs; 2265 2266 /* 2267 * Although the xhci hardware can do scatter/gather dma from 2268 * arbitrary sized buffers, there is a non-obvious restriction 2269 * that a LINK trb is only allowed at the end of a burst of 2270 * transfers - which might be 16kB. 2271 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2272 * The simple solution is not to allow a LINK trb in the middle 2273 * of anything - as here. 2274 * XXX: (dsl) There are xhci controllers out there (eg some made by 2275 * ASMedia) that seem to lock up if they process a LINK trb but 2276 * cannot process the linked-to trb yet. 2277 * The code should write the 'cycle' bit on the link trb AFTER 2278 * adding the other trb. 2279 */ 2280 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2281 parameter = xhci_ring_trbp(xr, 0); 2282 status = 0; 2283 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2284 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2285 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 2286 htole32(status), htole32(control)); 2287 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2288 BUS_DMASYNC_PREWRITE); 2289 xr->xr_cookies[ri] = NULL; 2290 xr->xr_ep = 0; 2291 xr->xr_cs ^= 1; 2292 ri = xr->xr_ep; 2293 cs = xr->xr_cs; 2294 } 2295 2296 ri++; 2297 2298 /* Write any subsequent TRB first */ 2299 for (i = 1; i < ntrbs; i++) { 2300 parameter = trbs[i].trb_0; 2301 status = trbs[i].trb_2; 2302 control = trbs[i].trb_3; 2303 2304 if (cs) { 2305 control |= XHCI_TRB_3_CYCLE_BIT; 2306 } else { 2307 control &= ~XHCI_TRB_3_CYCLE_BIT; 2308 } 2309 2310 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 2311 htole32(status), htole32(control)); 2312 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2313 BUS_DMASYNC_PREWRITE); 2314 xr->xr_cookies[ri] = cookie; 2315 ri++; 2316 } 2317 2318 /* Write the first TRB last */ 2319 i = 0; 2320 parameter = trbs[i].trb_0; 2321 status = trbs[i].trb_2; 2322 control = trbs[i].trb_3; 2323 2324 if (xr->xr_cs) { 2325 control |= XHCI_TRB_3_CYCLE_BIT; 2326 } else { 2327 control &= ~XHCI_TRB_3_CYCLE_BIT; 2328 } 2329 2330 xhci_trb_put(&xr->xr_trb[xr->xr_ep], htole64(parameter), 2331 htole32(status), htole32(control)); 2332 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2333 BUS_DMASYNC_PREWRITE); 2334 xr->xr_cookies[xr->xr_ep] = cookie; 2335 2336 xr->xr_ep = ri; 2337 xr->xr_cs = cs; 2338 2339 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2340 } 2341 2342 /* 2343 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2344 * Command completion is notified by cv_signal from xhci_handle_event 2345 * (called from interrupt from xHCI), or timed-out. 2346 * Command validation is performed in xhci_handle_event by checking if 2347 * trb_0 in CMD_COMPLETE TRB and sc->sc_command_addr are identical. 2348 * locked = 0: called without lock held 2349 * locked = 1: allows called with lock held 2350 * 'locked' is needed as some methods are called with sc_lock_held. 2351 * (see usbdivar.h) 2352 */ 2353 static usbd_status 2354 xhci_do_command1(struct xhci_softc * const sc, struct xhci_trb * const trb, 2355 int timeout, int locked) 2356 { 2357 struct xhci_ring * const cr = &sc->sc_cr; 2358 usbd_status err; 2359 2360 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2361 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2362 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2363 2364 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2365 2366 if (!locked) 2367 mutex_enter(&sc->sc_lock); 2368 2369 /* XXX KASSERT may fail when cv_timedwait unlocks sc_lock */ 2370 KASSERT(sc->sc_command_addr == 0); 2371 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2372 2373 mutex_enter(&cr->xr_lock); 2374 xhci_ring_put(sc, cr, NULL, trb, 1); 2375 mutex_exit(&cr->xr_lock); 2376 2377 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2378 2379 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2380 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2381 err = USBD_TIMEOUT; 2382 goto timedout; 2383 } 2384 2385 trb->trb_0 = sc->sc_result_trb.trb_0; 2386 trb->trb_2 = sc->sc_result_trb.trb_2; 2387 trb->trb_3 = sc->sc_result_trb.trb_3; 2388 2389 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2390 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2391 2392 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2393 case XHCI_TRB_ERROR_SUCCESS: 2394 err = USBD_NORMAL_COMPLETION; 2395 break; 2396 default: 2397 case 192 ... 223: 2398 err = USBD_IOERROR; 2399 break; 2400 case 224 ... 255: 2401 err = USBD_NORMAL_COMPLETION; 2402 break; 2403 } 2404 2405 timedout: 2406 sc->sc_command_addr = 0; 2407 if (!locked) 2408 mutex_exit(&sc->sc_lock); 2409 return err; 2410 } 2411 2412 static usbd_status 2413 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2414 int timeout) 2415 { 2416 return xhci_do_command1(sc, trb, timeout, 0); 2417 } 2418 2419 /* 2420 * This allows xhci_do_command with already sc_lock held. 2421 * This is needed as USB stack calls close methods with sc_lock_held. 2422 * (see usbdivar.h) 2423 */ 2424 static usbd_status 2425 xhci_do_command_locked(struct xhci_softc * const sc, 2426 struct xhci_trb * const trb, int timeout) 2427 { 2428 return xhci_do_command1(sc, trb, timeout, 1); 2429 } 2430 2431 static usbd_status 2432 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2433 { 2434 struct xhci_trb trb; 2435 usbd_status err; 2436 2437 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2438 2439 trb.trb_0 = 0; 2440 trb.trb_2 = 0; 2441 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2442 2443 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2444 if (err != USBD_NORMAL_COMPLETION) { 2445 return err; 2446 } 2447 2448 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2449 2450 return err; 2451 } 2452 2453 /* 2454 * Deallocate DMA buffer and ring buffer, and disable_slot. 2455 * Should be called with sc_lock held. 2456 */ 2457 static usbd_status 2458 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2459 { 2460 struct xhci_trb trb; 2461 struct xhci_slot *xs; 2462 2463 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2464 2465 if (sc->sc_dying) 2466 return USBD_IOERROR; 2467 2468 xs = &sc->sc_slots[slot]; 2469 if (xs->xs_idx != 0) { 2470 for (int i = XHCI_DCI_SLOT + 1; i < 32; i++) { 2471 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2472 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2473 } 2474 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2475 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2476 } 2477 2478 trb.trb_0 = 0; 2479 trb.trb_2 = 0; 2480 trb.trb_3 = htole32( 2481 XHCI_TRB_3_SLOT_SET(slot) | 2482 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2483 2484 return xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2485 } 2486 2487 /* 2488 * Change slot state. 2489 * bsr=0: ENABLED -> ADDRESSED 2490 * bsr=1: ENABLED -> DEFAULT 2491 * see xHCI 1.1 4.5.3, 3.3.4 2492 */ 2493 static usbd_status 2494 xhci_address_device(struct xhci_softc * const sc, 2495 uint64_t icp, uint8_t slot_id, bool bsr) 2496 { 2497 struct xhci_trb trb; 2498 usbd_status err; 2499 2500 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2501 2502 trb.trb_0 = icp; 2503 trb.trb_2 = 0; 2504 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2505 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2506 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2507 2508 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2509 return err; 2510 } 2511 2512 static usbd_status 2513 xhci_update_ep0_mps(struct xhci_softc * const sc, 2514 struct xhci_slot * const xs, u_int mps) 2515 { 2516 struct xhci_trb trb; 2517 usbd_status err; 2518 uint32_t * cp; 2519 2520 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2521 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2522 2523 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2524 cp[0] = htole32(0); 2525 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2526 2527 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2528 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2529 2530 /* sync input contexts before they are read from memory */ 2531 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2532 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2533 sc->sc_ctxsz * 4); 2534 2535 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2536 trb.trb_2 = 0; 2537 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2538 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2539 2540 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2541 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2542 return err; 2543 } 2544 2545 static void 2546 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2547 { 2548 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2549 2550 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2551 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2552 &dcbaa[si], dcba, si, 0); 2553 2554 dcbaa[si] = htole64(dcba); 2555 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2556 BUS_DMASYNC_PREWRITE); 2557 } 2558 2559 /* 2560 * Allocate DMA buffer and ring buffer for specified slot 2561 * and set Device Context Base Address 2562 * and issue Set Address device command. 2563 */ 2564 static usbd_status 2565 xhci_init_slot(struct usbd_device *dev, uint32_t slot, int route, int rhport) 2566 { 2567 struct xhci_softc * const sc = dev->ud_bus->ub_hcpriv; 2568 struct xhci_slot *xs; 2569 usbd_status err; 2570 u_int dci; 2571 uint32_t *cp; 2572 uint32_t mps = UGETW(dev->ud_ep0desc.wMaxPacketSize); 2573 2574 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2575 DPRINTFN(4, "slot %u speed %d rhport %d route %05x", 2576 slot, dev->ud_speed, route, rhport); 2577 2578 xs = &sc->sc_slots[slot]; 2579 2580 /* allocate contexts */ 2581 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2582 &xs->xs_dc_dma); 2583 if (err) 2584 return err; 2585 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2586 2587 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2588 &xs->xs_ic_dma); 2589 if (err) 2590 goto bad1; 2591 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2592 2593 for (dci = 0; dci < 32; dci++) { 2594 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2595 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2596 if (dci == XHCI_DCI_SLOT) 2597 continue; 2598 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2599 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2600 if (err) { 2601 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2602 goto bad2; 2603 } 2604 } 2605 2606 /* set up initial input control context */ 2607 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2608 cp[0] = htole32(0); 2609 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 2610 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2611 2612 /* set up input slot context */ 2613 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2614 xhci_setup_sctx(dev, cp); 2615 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(1)); 2616 cp[0] |= htole32(XHCI_SCTX_0_ROUTE_SET(route)); 2617 cp[1] |= htole32(XHCI_SCTX_1_RH_PORT_SET(rhport)); 2618 2619 /* set up input EP0 context */ 2620 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2621 cp[0] = htole32(0); 2622 cp[1] = htole32( 2623 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 2624 XHCI_EPCTX_1_EPTYPE_SET(4) | 2625 XHCI_EPCTX_1_CERR_SET(3) 2626 ); 2627 /* can't use xhci_ep_get_dci() yet? */ 2628 *(uint64_t *)(&cp[2]) = htole64( 2629 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 2630 XHCI_EPCTX_2_DCS_SET(1)); 2631 cp[4] = htole32( 2632 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 2633 ); 2634 2635 /* sync input contexts before they are read from memory */ 2636 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2637 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2638 sc->sc_ctxsz * 3); 2639 2640 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2641 2642 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 2643 false); 2644 2645 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2646 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2647 sc->sc_ctxsz * 2); 2648 2649 bad2: 2650 if (err == USBD_NORMAL_COMPLETION) { 2651 xs->xs_idx = slot; 2652 } else { 2653 for (int i = 1; i < dci; i++) { 2654 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2655 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2656 } 2657 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2658 bad1: 2659 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2660 xs->xs_idx = 0; 2661 } 2662 2663 return err; 2664 } 2665 2666 /* ----- */ 2667 2668 static void 2669 xhci_noop(struct usbd_pipe *pipe) 2670 { 2671 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2672 } 2673 2674 /* 2675 * Process root hub request. 2676 */ 2677 static int 2678 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2679 void *buf, int buflen) 2680 { 2681 struct xhci_softc * const sc = bus->ub_hcpriv; 2682 usb_port_status_t ps; 2683 int l, totlen = 0; 2684 uint16_t len, value, index; 2685 int port, i; 2686 uint32_t v; 2687 2688 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2689 2690 if (sc->sc_dying) 2691 return -1; 2692 2693 len = UGETW(req->wLength); 2694 value = UGETW(req->wValue); 2695 index = UGETW(req->wIndex); 2696 2697 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 2698 req->bmRequestType | (req->bRequest << 8), value, index, len); 2699 2700 #define C(x,y) ((x) | ((y) << 8)) 2701 switch (C(req->bRequest, req->bmRequestType)) { 2702 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2703 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 2704 if (len == 0) 2705 break; 2706 switch (value) { 2707 #define sd ((usb_string_descriptor_t *)buf) 2708 case C(2, UDESC_STRING): 2709 /* Product */ 2710 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 2711 break; 2712 #undef sd 2713 default: 2714 /* default from usbroothub */ 2715 return buflen; 2716 } 2717 break; 2718 2719 /* Hub requests */ 2720 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2721 break; 2722 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2723 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2724 index, value, 0, 0); 2725 if (index < 1 || index > sc->sc_maxports) { 2726 return -1; 2727 } 2728 port = XHCI_PORTSC(index); 2729 v = xhci_op_read_4(sc, port); 2730 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2731 v &= ~XHCI_PS_CLEAR; 2732 switch (value) { 2733 case UHF_PORT_ENABLE: 2734 xhci_op_write_4(sc, port, v &~ XHCI_PS_PED); 2735 break; 2736 case UHF_PORT_SUSPEND: 2737 return -1; 2738 case UHF_PORT_POWER: 2739 break; 2740 case UHF_PORT_TEST: 2741 case UHF_PORT_INDICATOR: 2742 return -1; 2743 case UHF_C_PORT_CONNECTION: 2744 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2745 break; 2746 case UHF_C_PORT_ENABLE: 2747 case UHF_C_PORT_SUSPEND: 2748 case UHF_C_PORT_OVER_CURRENT: 2749 return -1; 2750 case UHF_C_BH_PORT_RESET: 2751 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 2752 break; 2753 case UHF_C_PORT_RESET: 2754 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2755 break; 2756 case UHF_C_PORT_LINK_STATE: 2757 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 2758 break; 2759 case UHF_C_PORT_CONFIG_ERROR: 2760 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 2761 break; 2762 default: 2763 return -1; 2764 } 2765 break; 2766 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2767 if (len == 0) 2768 break; 2769 if ((value & 0xff) != 0) { 2770 return -1; 2771 } 2772 usb_hub_descriptor_t hubd; 2773 2774 totlen = min(buflen, sizeof(hubd)); 2775 memcpy(&hubd, buf, totlen); 2776 hubd.bNbrPorts = sc->sc_maxports; 2777 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2778 hubd.bPwrOn2PwrGood = 200; 2779 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 2780 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2781 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2782 totlen = min(totlen, hubd.bDescLength); 2783 memcpy(buf, &hubd, totlen); 2784 break; 2785 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2786 if (len != 4) { 2787 return -1; 2788 } 2789 memset(buf, 0, len); /* ? XXX */ 2790 totlen = len; 2791 break; 2792 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2793 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2794 if (index < 1 || index > sc->sc_maxports) { 2795 return -1; 2796 } 2797 if (len != 4) { 2798 return -1; 2799 } 2800 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 2801 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 2802 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 2803 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2804 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2805 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2806 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 2807 if (v & XHCI_PS_PR) i |= UPS_RESET; 2808 if (v & XHCI_PS_PP) { 2809 if (i & UPS_OTHER_SPEED) 2810 i |= UPS_PORT_POWER_SS; 2811 else 2812 i |= UPS_PORT_POWER; 2813 } 2814 if (i & UPS_OTHER_SPEED) 2815 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 2816 USETW(ps.wPortStatus, i); 2817 i = 0; 2818 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2819 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2820 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2821 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2822 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 2823 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 2824 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 2825 USETW(ps.wPortChange, i); 2826 totlen = min(len, sizeof(ps)); 2827 memcpy(buf, &ps, totlen); 2828 break; 2829 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2830 return -1; 2831 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 2832 break; 2833 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2834 break; 2835 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 2836 int optval = (index >> 8) & 0xff; 2837 index &= 0xff; 2838 if (index < 1 || index > sc->sc_maxports) { 2839 return -1; 2840 } 2841 port = XHCI_PORTSC(index); 2842 v = xhci_op_read_4(sc, port); 2843 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2844 v &= ~XHCI_PS_CLEAR; 2845 switch (value) { 2846 case UHF_PORT_ENABLE: 2847 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 2848 break; 2849 case UHF_PORT_SUSPEND: 2850 /* XXX suspend */ 2851 break; 2852 case UHF_PORT_RESET: 2853 v &= ~ (XHCI_PS_PED | XHCI_PS_PR); 2854 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 2855 /* Wait for reset to complete. */ 2856 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2857 if (sc->sc_dying) { 2858 return -1; 2859 } 2860 v = xhci_op_read_4(sc, port); 2861 if (v & XHCI_PS_PR) { 2862 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 2863 usb_delay_ms(&sc->sc_bus, 10); 2864 /* XXX */ 2865 } 2866 break; 2867 case UHF_PORT_POWER: 2868 /* XXX power control */ 2869 break; 2870 /* XXX more */ 2871 case UHF_C_PORT_RESET: 2872 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2873 break; 2874 case UHF_PORT_U1_TIMEOUT: 2875 if (USB_IS_SS(xhci_xspeed2speed(XHCI_PS_SPEED_GET(v)))){ 2876 return -1; 2877 } 2878 port = XHCI_PORTPMSC(index); 2879 v = xhci_op_read_4(sc, port); 2880 v &= ~XHCI_PM3_U1TO_SET(0xff); 2881 v |= XHCI_PM3_U1TO_SET(optval); 2882 xhci_op_write_4(sc, port, v); 2883 break; 2884 case UHF_PORT_U2_TIMEOUT: 2885 if (USB_IS_SS(xhci_xspeed2speed(XHCI_PS_SPEED_GET(v)))){ 2886 return -1; 2887 } 2888 port = XHCI_PORTPMSC(index); 2889 v = xhci_op_read_4(sc, port); 2890 v &= ~XHCI_PM3_U2TO_SET(0xff); 2891 v |= XHCI_PM3_U2TO_SET(optval); 2892 xhci_op_write_4(sc, port, v); 2893 break; 2894 default: 2895 return -1; 2896 } 2897 } 2898 break; 2899 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2900 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2901 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2902 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2903 break; 2904 default: 2905 /* default from usbroothub */ 2906 return buflen; 2907 } 2908 2909 return totlen; 2910 } 2911 2912 /* root hub interrupt */ 2913 2914 static usbd_status 2915 xhci_root_intr_transfer(struct usbd_xfer *xfer) 2916 { 2917 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2918 usbd_status err; 2919 2920 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2921 2922 /* Insert last in queue. */ 2923 mutex_enter(&sc->sc_lock); 2924 err = usb_insert_transfer(xfer); 2925 mutex_exit(&sc->sc_lock); 2926 if (err) 2927 return err; 2928 2929 /* Pipe isn't running, start first */ 2930 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2931 } 2932 2933 /* Wait for roothub port status/change */ 2934 static usbd_status 2935 xhci_root_intr_start(struct usbd_xfer *xfer) 2936 { 2937 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2938 2939 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2940 2941 if (sc->sc_dying) 2942 return USBD_IOERROR; 2943 2944 mutex_enter(&sc->sc_lock); 2945 sc->sc_intrxfer = xfer; 2946 mutex_exit(&sc->sc_lock); 2947 2948 return USBD_IN_PROGRESS; 2949 } 2950 2951 static void 2952 xhci_root_intr_abort(struct usbd_xfer *xfer) 2953 { 2954 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2955 2956 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2957 2958 KASSERT(mutex_owned(&sc->sc_lock)); 2959 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2960 2961 sc->sc_intrxfer = NULL; 2962 2963 xfer->ux_status = USBD_CANCELLED; 2964 usb_transfer_complete(xfer); 2965 } 2966 2967 static void 2968 xhci_root_intr_close(struct usbd_pipe *pipe) 2969 { 2970 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 2971 2972 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2973 2974 KASSERT(mutex_owned(&sc->sc_lock)); 2975 2976 sc->sc_intrxfer = NULL; 2977 } 2978 2979 static void 2980 xhci_root_intr_done(struct usbd_xfer *xfer) 2981 { 2982 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2983 2984 xfer->ux_hcpriv = NULL; 2985 } 2986 2987 /* -------------- */ 2988 /* device control */ 2989 2990 static usbd_status 2991 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2992 { 2993 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2994 usbd_status err; 2995 2996 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2997 2998 /* Insert last in queue. */ 2999 mutex_enter(&sc->sc_lock); 3000 err = usb_insert_transfer(xfer); 3001 mutex_exit(&sc->sc_lock); 3002 if (err) 3003 return err; 3004 3005 /* Pipe isn't running, start first */ 3006 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3007 } 3008 3009 static usbd_status 3010 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3011 { 3012 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3013 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3014 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3015 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3016 struct xhci_xfer * const xx = (void *)xfer; 3017 usb_device_request_t * const req = &xfer->ux_request; 3018 const bool isread = UT_GET_DIR(req->bmRequestType) == UT_READ; 3019 const uint32_t len = UGETW(req->wLength); 3020 usb_dma_t * const dma = &xfer->ux_dmabuf; 3021 uint64_t parameter; 3022 uint32_t status; 3023 uint32_t control; 3024 u_int i; 3025 3026 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3027 DPRINTFN(12, "req: %04x %04x %04x %04x", 3028 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3029 UGETW(req->wIndex), UGETW(req->wLength)); 3030 3031 /* XXX */ 3032 if (tr->is_halted) { 3033 DPRINTFN(1, "ctrl xfer %p halted: slot %u dci %u", 3034 xfer, xs->xs_idx, dci, 0); 3035 xhci_reset_endpoint(xfer->ux_pipe); 3036 tr->is_halted = false; 3037 xhci_set_dequeue(xfer->ux_pipe); 3038 } 3039 3040 /* we rely on the bottom bits for extra info */ 3041 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 3042 3043 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3044 3045 i = 0; 3046 3047 /* setup phase */ 3048 memcpy(¶meter, req, sizeof(*req)); 3049 parameter = le64toh(parameter); 3050 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3051 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3052 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3053 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3054 XHCI_TRB_3_IDT_BIT; 3055 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3056 3057 if (len == 0) 3058 goto no_data; 3059 3060 /* data phase */ 3061 parameter = DMAADDR(dma, 0); 3062 KASSERT(len <= 0x10000); 3063 status = XHCI_TRB_2_IRQ_SET(0) | 3064 XHCI_TRB_2_TDSZ_SET(1) | 3065 XHCI_TRB_2_BYTES_SET(len); 3066 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3067 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3068 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3069 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3070 3071 parameter = (uintptr_t)xfer | 0x3; 3072 status = XHCI_TRB_2_IRQ_SET(0); 3073 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3074 XHCI_TRB_3_IOC_BIT; 3075 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3076 3077 no_data: 3078 parameter = 0; 3079 status = XHCI_TRB_2_IRQ_SET(0); 3080 /* the status stage has inverted direction */ 3081 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3082 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3083 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3084 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3085 3086 parameter = (uintptr_t)xfer | 0x0; 3087 status = XHCI_TRB_2_IRQ_SET(0); 3088 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3089 XHCI_TRB_3_IOC_BIT; 3090 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3091 3092 mutex_enter(&tr->xr_lock); 3093 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3094 mutex_exit(&tr->xr_lock); 3095 3096 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3097 3098 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3099 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3100 xhci_timeout, xfer); 3101 } 3102 3103 if (sc->sc_bus.ub_usepolling) { 3104 DPRINTFN(1, "polling", 0, 0, 0, 0); 3105 //xhci_waitintr(sc, xfer); 3106 } 3107 3108 return USBD_IN_PROGRESS; 3109 } 3110 3111 static void 3112 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3113 { 3114 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3115 3116 callout_stop(&xfer->ux_callout); /* XXX wrong place */ 3117 3118 } 3119 3120 static void 3121 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3122 { 3123 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3124 3125 xhci_abort_xfer(xfer, USBD_CANCELLED); 3126 } 3127 3128 static void 3129 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3130 { 3131 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3132 3133 (void)xhci_close_pipe(pipe); 3134 } 3135 3136 /* ------------------ */ 3137 /* device isochronous */ 3138 3139 /* ----------- */ 3140 /* device bulk */ 3141 3142 static usbd_status 3143 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3144 { 3145 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3146 usbd_status err; 3147 3148 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3149 3150 /* Insert last in queue. */ 3151 mutex_enter(&sc->sc_lock); 3152 err = usb_insert_transfer(xfer); 3153 mutex_exit(&sc->sc_lock); 3154 if (err) 3155 return err; 3156 3157 /* 3158 * Pipe isn't running (otherwise err would be USBD_INPROG), 3159 * so start it first. 3160 */ 3161 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3162 } 3163 3164 static usbd_status 3165 xhci_device_bulk_start(struct usbd_xfer *xfer) 3166 { 3167 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3168 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3169 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3170 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3171 struct xhci_xfer * const xx = (void *)xfer; 3172 const uint32_t len = xfer->ux_length; 3173 usb_dma_t * const dma = &xfer->ux_dmabuf; 3174 uint64_t parameter; 3175 uint32_t status; 3176 uint32_t control; 3177 u_int i = 0; 3178 3179 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3180 3181 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3182 3183 if (sc->sc_dying) 3184 return USBD_IOERROR; 3185 3186 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3187 3188 parameter = DMAADDR(dma, 0); 3189 /* 3190 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3191 * If the user supplied buffer crosses such a boundary then 2 3192 * (or more) TRB should be used. 3193 * If multiple TRB are used the td_size field must be set correctly. 3194 * For v1.0 devices (like ivy bridge) this is the number of usb data 3195 * blocks needed to complete the transfer. 3196 * Setting it to 1 in the last TRB causes an extra zero-length 3197 * data block be sent. 3198 * The earlier documentation differs, I don't know how it behaves. 3199 */ 3200 KASSERT(len <= 0x10000); 3201 status = XHCI_TRB_2_IRQ_SET(0) | 3202 XHCI_TRB_2_TDSZ_SET(1) | 3203 XHCI_TRB_2_BYTES_SET(len); 3204 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3205 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3206 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3207 3208 mutex_enter(&tr->xr_lock); 3209 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3210 mutex_exit(&tr->xr_lock); 3211 3212 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3213 3214 if (sc->sc_bus.ub_usepolling) { 3215 DPRINTFN(1, "polling", 0, 0, 0, 0); 3216 //xhci_waitintr(sc, xfer); 3217 } 3218 3219 return USBD_IN_PROGRESS; 3220 } 3221 3222 static void 3223 xhci_device_bulk_done(struct usbd_xfer *xfer) 3224 { 3225 #ifdef USB_DEBUG 3226 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3227 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3228 #endif 3229 const u_int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3230 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3231 3232 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3233 3234 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3235 3236 callout_stop(&xfer->ux_callout); /* XXX wrong place */ 3237 3238 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3239 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3240 } 3241 3242 static void 3243 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3244 { 3245 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3246 3247 xhci_abort_xfer(xfer, USBD_CANCELLED); 3248 } 3249 3250 static void 3251 xhci_device_bulk_close(struct usbd_pipe *pipe) 3252 { 3253 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3254 3255 (void)xhci_close_pipe(pipe); 3256 } 3257 3258 /* ---------------- */ 3259 /* device interrupt */ 3260 3261 static usbd_status 3262 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3263 { 3264 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3265 usbd_status err; 3266 3267 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3268 3269 /* Insert last in queue. */ 3270 mutex_enter(&sc->sc_lock); 3271 err = usb_insert_transfer(xfer); 3272 mutex_exit(&sc->sc_lock); 3273 if (err) 3274 return err; 3275 3276 /* 3277 * Pipe isn't running (otherwise err would be USBD_INPROG), 3278 * so start it first. 3279 */ 3280 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3281 } 3282 3283 static usbd_status 3284 xhci_device_intr_start(struct usbd_xfer *xfer) 3285 { 3286 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3287 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3288 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3289 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3290 struct xhci_xfer * const xx = (void *)xfer; 3291 const uint32_t len = xfer->ux_length; 3292 usb_dma_t * const dma = &xfer->ux_dmabuf; 3293 uint64_t parameter; 3294 uint32_t status; 3295 uint32_t control; 3296 u_int i = 0; 3297 3298 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3299 3300 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3301 3302 if (sc->sc_dying) 3303 return USBD_IOERROR; 3304 3305 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3306 3307 parameter = DMAADDR(dma, 0); 3308 KASSERT(len <= 0x10000); 3309 status = XHCI_TRB_2_IRQ_SET(0) | 3310 XHCI_TRB_2_TDSZ_SET(1) | 3311 XHCI_TRB_2_BYTES_SET(len); 3312 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3313 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3314 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3315 3316 mutex_enter(&tr->xr_lock); 3317 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3318 mutex_exit(&tr->xr_lock); 3319 3320 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3321 3322 if (sc->sc_bus.ub_usepolling) { 3323 DPRINTFN(1, "polling", 0, 0, 0, 0); 3324 //xhci_waitintr(sc, xfer); 3325 } 3326 3327 return USBD_IN_PROGRESS; 3328 } 3329 3330 static void 3331 xhci_device_intr_done(struct usbd_xfer *xfer) 3332 { 3333 struct xhci_softc * const sc __diagused = 3334 xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3335 #ifdef USB_DEBUG 3336 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3337 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3338 #endif 3339 const u_int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3340 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3341 3342 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3343 3344 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3345 3346 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3347 3348 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3349 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3350 3351 #if 0 3352 device_printf(sc->sc_dev, ""); 3353 for (size_t i = 0; i < xfer->ux_length; i++) { 3354 printf(" %02x", ((uint8_t const *)xfer->ux_buffer)[i]); 3355 } 3356 printf("\n"); 3357 #endif 3358 3359 if (xfer->ux_pipe->up_repeat) { 3360 xfer->ux_status = xhci_device_intr_start(xfer); 3361 } else { 3362 callout_stop(&xfer->ux_callout); /* XXX */ 3363 } 3364 3365 } 3366 3367 static void 3368 xhci_device_intr_abort(struct usbd_xfer *xfer) 3369 { 3370 struct xhci_softc * const sc __diagused = 3371 xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3372 3373 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3374 3375 KASSERT(mutex_owned(&sc->sc_lock)); 3376 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3377 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3378 xhci_abort_xfer(xfer, USBD_CANCELLED); 3379 } 3380 3381 static void 3382 xhci_device_intr_close(struct usbd_pipe *pipe) 3383 { 3384 //struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 3385 3386 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3387 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3388 3389 (void)xhci_close_pipe(pipe); 3390 } 3391 3392 /* ------------ */ 3393 3394 static void 3395 xhci_timeout(void *addr) 3396 { 3397 struct xhci_xfer * const xx = addr; 3398 struct usbd_xfer * const xfer = &xx->xx_xfer; 3399 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3400 3401 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3402 3403 if (sc->sc_dying) { 3404 return; 3405 } 3406 3407 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 3408 USB_TASKQ_MPSAFE); 3409 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 3410 USB_TASKQ_HC); 3411 } 3412 3413 static void 3414 xhci_timeout_task(void *addr) 3415 { 3416 struct usbd_xfer * const xfer = addr; 3417 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3418 3419 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3420 3421 mutex_enter(&sc->sc_lock); 3422 #if 0 3423 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3424 #else 3425 xfer->ux_status = USBD_TIMEOUT; 3426 usb_transfer_complete(xfer); 3427 #endif 3428 mutex_exit(&sc->sc_lock); 3429 } 3430
Indexes created Wed Oct 01 18:09:54 GMT 2025