xhci.c revision 1.28.2.3
1 /* $NetBSD: xhci.c,v 1.28.2.3 2014/12/01 12:38:39 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.28.2.3 2014/12/01 12:38:39 skrll Exp $"); 31 32 #include "opt_usb.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/kmem.h> 38 #include <sys/malloc.h> 39 #include <sys/device.h> 40 #include <sys/select.h> 41 #include <sys/proc.h> 42 #include <sys/queue.h> 43 #include <sys/mutex.h> 44 #include <sys/condvar.h> 45 #include <sys/bus.h> 46 #include <sys/cpu.h> 47 #include <sys/sysctl.h> 48 49 #include <machine/endian.h> 50 51 #include <dev/usb/usb.h> 52 #include <dev/usb/usbdi.h> 53 #include <dev/usb/usbdivar.h> 54 #include <dev/usb/usbhist.h> 55 #include <dev/usb/usb_mem.h> 56 #include <dev/usb/usb_quirks.h> 57 58 #include <dev/usb/xhcireg.h> 59 #include <dev/usb/xhcivar.h> 60 #include <dev/usb/usbroothub_subr.h> 61 62 63 #ifdef USB_DEBUG 64 #ifndef XHCI_DEBUG 65 #define xhcidebug 0 66 #else 67 static int xhcidebug = 0; 68 69 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 70 { 71 int err; 72 const struct sysctlnode *rnode; 73 const struct sysctlnode *cnode; 74 75 err = sysctl_createv(clog, 0, NULL, &rnode, 76 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 77 SYSCTL_DESCR("xhci global controls"), 78 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 79 80 if (err) 81 goto fail; 82 83 /* control debugging printfs */ 84 err = sysctl_createv(clog, 0, &rnode, &cnode, 85 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 86 "debug", SYSCTL_DESCR("Enable debugging output"), 87 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 88 if (err) 89 goto fail; 90 91 return; 92 fail: 93 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 94 } 95 96 #endif /* XHCI_DEBUG */ 97 #endif /* USB_DEBUG */ 98 99 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 100 #define XHCIHIST_FUNC() USBHIST_FUNC() 101 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 102 103 #define XHCI_DCI_SLOT 0 104 #define XHCI_DCI_EP_CONTROL 1 105 106 #define XHCI_ICI_INPUT_CONTROL 0 107 108 struct xhci_pipe { 109 struct usbd_pipe xp_pipe; 110 }; 111 112 #define XHCI_INTR_ENDPT 1 113 #define XHCI_COMMAND_RING_TRBS 256 114 #define XHCI_EVENT_RING_TRBS 256 115 #define XHCI_EVENT_RING_SEGMENTS 1 116 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 117 118 static usbd_status xhci_open(usbd_pipe_handle); 119 static int xhci_intr1(struct xhci_softc * const); 120 static void xhci_softintr(void *); 121 static void xhci_poll(struct usbd_bus *); 122 static usbd_status xhci_allocm(struct usbd_bus *, usb_dma_t *, uint32_t); 123 static void xhci_freem(struct usbd_bus *, usb_dma_t *); 124 static usbd_xfer_handle xhci_allocx(struct usbd_bus *); 125 static void xhci_freex(struct usbd_bus *, usbd_xfer_handle); 126 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 127 static usbd_status xhci_new_device(device_t, usbd_bus_handle, int, int, int, 128 struct usbd_port *); 129 130 static usbd_status xhci_configure_endpoint(usbd_pipe_handle); 131 static usbd_status xhci_unconfigure_endpoint(usbd_pipe_handle); 132 static usbd_status xhci_reset_endpoint(usbd_pipe_handle); 133 //static usbd_status xhci_stop_endpoint(usbd_pipe_handle); 134 135 static usbd_status xhci_set_dequeue(usbd_pipe_handle); 136 137 static usbd_status xhci_do_command(struct xhci_softc * const, 138 struct xhci_trb * const, int); 139 static usbd_status xhci_init_slot(struct xhci_softc * const, uint32_t, 140 int, int, int, int); 141 static usbd_status xhci_enable_slot(struct xhci_softc * const, 142 uint8_t * const); 143 static usbd_status xhci_address_device(struct xhci_softc * const, 144 uint64_t, uint8_t, bool); 145 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 146 struct xhci_slot * const, u_int); 147 static usbd_status xhci_ring_init(struct xhci_softc * const, 148 struct xhci_ring * const, size_t, size_t); 149 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 150 151 static void xhci_noop(usbd_pipe_handle); 152 153 static usbd_status xhci_root_ctrl_transfer(usbd_xfer_handle); 154 static usbd_status xhci_root_ctrl_start(usbd_xfer_handle); 155 static void xhci_root_ctrl_abort(usbd_xfer_handle); 156 static void xhci_root_ctrl_close(usbd_pipe_handle); 157 static void xhci_root_ctrl_done(usbd_xfer_handle); 158 159 static usbd_status xhci_root_intr_transfer(usbd_xfer_handle); 160 static usbd_status xhci_root_intr_start(usbd_xfer_handle); 161 static void xhci_root_intr_abort(usbd_xfer_handle); 162 static void xhci_root_intr_close(usbd_pipe_handle); 163 static void xhci_root_intr_done(usbd_xfer_handle); 164 165 static usbd_status xhci_device_ctrl_transfer(usbd_xfer_handle); 166 static usbd_status xhci_device_ctrl_start(usbd_xfer_handle); 167 static void xhci_device_ctrl_abort(usbd_xfer_handle); 168 static void xhci_device_ctrl_close(usbd_pipe_handle); 169 static void xhci_device_ctrl_done(usbd_xfer_handle); 170 171 static usbd_status xhci_device_intr_transfer(usbd_xfer_handle); 172 static usbd_status xhci_device_intr_start(usbd_xfer_handle); 173 static void xhci_device_intr_abort(usbd_xfer_handle); 174 static void xhci_device_intr_close(usbd_pipe_handle); 175 static void xhci_device_intr_done(usbd_xfer_handle); 176 177 static usbd_status xhci_device_bulk_transfer(usbd_xfer_handle); 178 static usbd_status xhci_device_bulk_start(usbd_xfer_handle); 179 static void xhci_device_bulk_abort(usbd_xfer_handle); 180 static void xhci_device_bulk_close(usbd_pipe_handle); 181 static void xhci_device_bulk_done(usbd_xfer_handle); 182 183 static void xhci_timeout(void *); 184 static void xhci_timeout_task(void *); 185 186 static const struct usbd_bus_methods xhci_bus_methods = { 187 .ubm_open = xhci_open, 188 .ubm_softint = xhci_softintr, 189 .ubm_dopoll = xhci_poll, 190 .ubm_allocm = xhci_allocm, 191 .ubm_freem = xhci_freem, 192 .ubm_allocx = xhci_allocx, 193 .ubm_freex = xhci_freex, 194 .ubm_getlock = xhci_get_lock, 195 .ubm_newdev = xhci_new_device, 196 }; 197 198 static const struct usbd_pipe_methods xhci_root_ctrl_methods = { 199 .upm_transfer = xhci_root_ctrl_transfer, 200 .upm_start = xhci_root_ctrl_start, 201 .upm_abort = xhci_root_ctrl_abort, 202 .upm_close = xhci_root_ctrl_close, 203 .upm_cleartoggle = xhci_noop, 204 .upm_done = xhci_root_ctrl_done, 205 }; 206 207 static const struct usbd_pipe_methods xhci_root_intr_methods = { 208 .upm_transfer = xhci_root_intr_transfer, 209 .upm_start = xhci_root_intr_start, 210 .upm_abort = xhci_root_intr_abort, 211 .upm_close = xhci_root_intr_close, 212 .upm_cleartoggle = xhci_noop, 213 .upm_done = xhci_root_intr_done, 214 }; 215 216 217 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 218 .upm_transfer = xhci_device_ctrl_transfer, 219 .upm_start = xhci_device_ctrl_start, 220 .upm_abort = xhci_device_ctrl_abort, 221 .upm_close = xhci_device_ctrl_close, 222 .upm_cleartoggle = xhci_noop, 223 .upm_done = xhci_device_ctrl_done, 224 }; 225 226 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 227 .upm_cleartoggle = xhci_noop, 228 }; 229 230 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 231 .upm_transfer = xhci_device_bulk_transfer, 232 .upm_start = xhci_device_bulk_start, 233 .upm_abort = xhci_device_bulk_abort, 234 .upm_close = xhci_device_bulk_close, 235 .upm_cleartoggle = xhci_noop, 236 .upm_done = xhci_device_bulk_done, 237 }; 238 239 static const struct usbd_pipe_methods xhci_device_intr_methods = { 240 .upm_transfer = xhci_device_intr_transfer, 241 .upm_start = xhci_device_intr_start, 242 .upm_abort = xhci_device_intr_abort, 243 .upm_close = xhci_device_intr_close, 244 .upm_cleartoggle = xhci_noop, 245 .upm_done = xhci_device_intr_done, 246 }; 247 248 static inline uint32_t 249 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 250 { 251 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 252 } 253 254 #if 0 /* unused */ 255 static inline void 256 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 257 uint32_t value) 258 { 259 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 260 } 261 #endif /* unused */ 262 263 static inline uint32_t 264 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 265 { 266 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 267 } 268 269 static inline uint32_t 270 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 271 { 272 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 273 } 274 275 static inline void 276 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 277 uint32_t value) 278 { 279 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 280 } 281 282 #if 0 /* unused */ 283 static inline uint64_t 284 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 285 { 286 uint64_t value; 287 288 if (sc->sc_ac64) { 289 #ifdef XHCI_USE_BUS_SPACE_8 290 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 291 #else 292 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 293 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 294 offset + 4) << 32; 295 #endif 296 } else { 297 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 298 } 299 300 return value; 301 } 302 #endif /* unused */ 303 304 static inline void 305 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 306 uint64_t value) 307 { 308 if (sc->sc_ac64) { 309 #ifdef XHCI_USE_BUS_SPACE_8 310 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 311 #else 312 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 313 (value >> 0) & 0xffffffff); 314 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 315 (value >> 32) & 0xffffffff); 316 #endif 317 } else { 318 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 319 } 320 } 321 322 static inline uint32_t 323 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 324 { 325 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 326 } 327 328 static inline void 329 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 330 uint32_t value) 331 { 332 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 333 } 334 335 #if 0 /* unused */ 336 static inline uint64_t 337 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 338 { 339 uint64_t value; 340 341 if (sc->sc_ac64) { 342 #ifdef XHCI_USE_BUS_SPACE_8 343 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 344 #else 345 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 346 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 347 offset + 4) << 32; 348 #endif 349 } else { 350 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 351 } 352 353 return value; 354 } 355 #endif /* unused */ 356 357 static inline void 358 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 359 uint64_t value) 360 { 361 if (sc->sc_ac64) { 362 #ifdef XHCI_USE_BUS_SPACE_8 363 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 364 #else 365 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 366 (value >> 0) & 0xffffffff); 367 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 368 (value >> 32) & 0xffffffff); 369 #endif 370 } else { 371 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 372 } 373 } 374 375 #if 0 /* unused */ 376 static inline uint32_t 377 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 378 { 379 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 380 } 381 #endif /* unused */ 382 383 static inline void 384 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 385 uint32_t value) 386 { 387 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 388 } 389 390 /* --- */ 391 392 static inline uint8_t 393 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 394 { 395 u_int eptype; 396 397 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 398 case UE_CONTROL: 399 eptype = 0x0; 400 break; 401 case UE_ISOCHRONOUS: 402 eptype = 0x1; 403 break; 404 case UE_BULK: 405 eptype = 0x2; 406 break; 407 case UE_INTERRUPT: 408 eptype = 0x3; 409 break; 410 } 411 412 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 413 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 414 return eptype | 0x4; 415 else 416 return eptype; 417 } 418 419 static u_int 420 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 421 { 422 /* xHCI 1.0 section 4.5.1 */ 423 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 424 u_int in = 0; 425 426 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 427 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 428 in = 1; 429 430 return epaddr * 2 + in; 431 } 432 433 static inline u_int 434 xhci_dci_to_ici(const u_int i) 435 { 436 return i + 1; 437 } 438 439 static inline void * 440 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 441 const u_int dci) 442 { 443 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 444 } 445 446 #if 0 /* unused */ 447 static inline bus_addr_t 448 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 449 const u_int dci) 450 { 451 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 452 } 453 #endif /* unused */ 454 455 static inline void * 456 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 457 const u_int ici) 458 { 459 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 460 } 461 462 static inline bus_addr_t 463 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 464 const u_int ici) 465 { 466 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 467 } 468 469 static inline struct xhci_trb * 470 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 471 { 472 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 473 } 474 475 static inline bus_addr_t 476 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 477 { 478 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 479 } 480 481 static inline void 482 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 483 uint32_t control) 484 { 485 trb->trb_0 = parameter; 486 trb->trb_2 = status; 487 trb->trb_3 = control; 488 } 489 490 /* --- */ 491 492 void 493 xhci_childdet(device_t self, device_t child) 494 { 495 struct xhci_softc * const sc = device_private(self); 496 497 KASSERT(sc->sc_child == child); 498 if (child == sc->sc_child) 499 sc->sc_child = NULL; 500 } 501 502 int 503 xhci_detach(struct xhci_softc *sc, int flags) 504 { 505 int rv = 0; 506 507 if (sc->sc_child != NULL) 508 rv = config_detach(sc->sc_child, flags); 509 510 if (rv != 0) 511 return (rv); 512 513 /* XXX unconfigure/free slots */ 514 515 /* verify: */ 516 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 517 xhci_op_write_4(sc, XHCI_USBCMD, 0); 518 /* do we need to wait for stop? */ 519 520 xhci_op_write_8(sc, XHCI_CRCR, 0); 521 xhci_ring_free(sc, &sc->sc_cr); 522 cv_destroy(&sc->sc_command_cv); 523 524 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 525 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 526 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 527 xhci_ring_free(sc, &sc->sc_er); 528 529 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 530 531 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 532 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 533 534 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 535 536 mutex_destroy(&sc->sc_lock); 537 mutex_destroy(&sc->sc_intr_lock); 538 539 pool_cache_destroy(sc->sc_xferpool); 540 541 return rv; 542 } 543 544 int 545 xhci_activate(device_t self, enum devact act) 546 { 547 struct xhci_softc * const sc = device_private(self); 548 549 switch (act) { 550 case DVACT_DEACTIVATE: 551 sc->sc_dying = true; 552 return 0; 553 default: 554 return EOPNOTSUPP; 555 } 556 } 557 558 bool 559 xhci_suspend(device_t dv, const pmf_qual_t *qual) 560 { 561 return false; 562 } 563 564 bool 565 xhci_resume(device_t dv, const pmf_qual_t *qual) 566 { 567 return false; 568 } 569 570 bool 571 xhci_shutdown(device_t self, int flags) 572 { 573 return false; 574 } 575 576 577 static void 578 hexdump(const char *msg, const void *base, size_t len) 579 { 580 #if 0 581 size_t cnt; 582 const uint32_t *p; 583 extern paddr_t vtophys(vaddr_t); 584 585 p = base; 586 cnt = 0; 587 588 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 589 (void *)vtophys((vaddr_t)base)); 590 591 while (cnt < len) { 592 if (cnt % 16 == 0) 593 printf("%p: ", p); 594 else if (cnt % 8 == 0) 595 printf(" |"); 596 printf(" %08x", *p++); 597 cnt += 4; 598 if (cnt % 16 == 0) 599 printf("\n"); 600 } 601 #endif 602 } 603 604 605 int 606 xhci_init(struct xhci_softc *sc) 607 { 608 bus_size_t bsz; 609 uint32_t cap, hcs1, hcs2, hcc, dboff, rtsoff; 610 uint32_t ecp, ecr; 611 uint32_t usbcmd, usbsts, pagesize, config; 612 int i; 613 uint16_t hciversion; 614 uint8_t caplength; 615 616 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 617 618 /* XXX Low/Full/High speeds for now */ 619 sc->sc_bus.usbrev = USBREV_2_0; 620 621 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 622 caplength = XHCI_CAP_CAPLENGTH(cap); 623 hciversion = XHCI_CAP_HCIVERSION(cap); 624 625 if ((hciversion < 0x0096) || (hciversion > 0x0100)) { 626 aprint_normal_dev(sc->sc_dev, 627 "xHCI version %x.%x not known to be supported\n", 628 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 629 } else { 630 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 631 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 632 } 633 634 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 635 &sc->sc_cbh) != 0) { 636 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 637 return ENOMEM; 638 } 639 640 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 641 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 642 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 643 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 644 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 645 (void)xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 646 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 647 648 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 649 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 650 aprint_debug_dev(sc->sc_dev, "ac64 %d ctxsz %d\n", sc->sc_ac64, 651 sc->sc_ctxsz); 652 653 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 654 ecp = XHCI_HCC_XECP(hcc) * 4; 655 while (ecp != 0) { 656 ecr = xhci_read_4(sc, ecp); 657 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 658 switch (XHCI_XECP_ID(ecr)) { 659 case XHCI_ID_PROTOCOLS: { 660 uint32_t w0, w4, w8; 661 uint16_t w2; 662 w0 = xhci_read_4(sc, ecp + 0); 663 w2 = (w0 >> 16) & 0xffff; 664 w4 = xhci_read_4(sc, ecp + 4); 665 w8 = xhci_read_4(sc, ecp + 8); 666 aprint_debug_dev(sc->sc_dev, "SP: %08x %08x %08x\n", 667 w0, w4, w8); 668 if (w4 == 0x20425355 && w2 == 0x0300) { 669 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 670 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 671 } 672 if (w4 == 0x20425355 && w2 == 0x0200) { 673 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 674 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 675 } 676 break; 677 } 678 default: 679 break; 680 } 681 ecr = xhci_read_4(sc, ecp); 682 if (XHCI_XECP_NEXT(ecr) == 0) { 683 ecp = 0; 684 } else { 685 ecp += XHCI_XECP_NEXT(ecr) * 4; 686 } 687 } 688 689 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 690 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 691 &sc->sc_obh) != 0) { 692 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 693 return ENOMEM; 694 } 695 696 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 697 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 698 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 699 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 700 return ENOMEM; 701 } 702 703 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 704 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 705 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 706 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 707 return ENOMEM; 708 } 709 710 for (i = 0; i < 100; i++) { 711 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 712 if ((usbsts & XHCI_STS_CNR) == 0) 713 break; 714 usb_delay_ms(&sc->sc_bus, 1); 715 } 716 if (i >= 100) 717 return EIO; 718 719 usbcmd = 0; 720 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 721 usb_delay_ms(&sc->sc_bus, 1); 722 723 usbcmd = XHCI_CMD_HCRST; 724 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 725 for (i = 0; i < 100; i++) { 726 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 727 if ((usbcmd & XHCI_CMD_HCRST) == 0) 728 break; 729 usb_delay_ms(&sc->sc_bus, 1); 730 } 731 if (i >= 100) 732 return EIO; 733 734 for (i = 0; i < 100; i++) { 735 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 736 if ((usbsts & XHCI_STS_CNR) == 0) 737 break; 738 usb_delay_ms(&sc->sc_bus, 1); 739 } 740 if (i >= 100) 741 return EIO; 742 743 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 744 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 745 pagesize = ffs(pagesize); 746 if (pagesize == 0) 747 return EIO; 748 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 749 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 750 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 751 (uint32_t)sc->sc_maxslots); 752 753 usbd_status err; 754 755 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 756 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 757 if (sc->sc_maxspbuf != 0) { 758 err = usb_allocmem(&sc->sc_bus, 759 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 760 &sc->sc_spbufarray_dma); 761 if (err) 762 return err; 763 764 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * sc->sc_maxspbuf, KM_SLEEP); 765 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 766 for (i = 0; i < sc->sc_maxspbuf; i++) { 767 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 768 /* allocate contexts */ 769 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 770 sc->sc_pgsz, dma); 771 if (err) 772 return err; 773 spbufarray[i] = htole64(DMAADDR(dma, 0)); 774 usb_syncmem(dma, 0, sc->sc_pgsz, 775 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 776 } 777 778 usb_syncmem(&sc->sc_spbufarray_dma, 0, 779 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 780 } 781 782 config = xhci_op_read_4(sc, XHCI_CONFIG); 783 config &= ~0xFF; 784 config |= sc->sc_maxslots & 0xFF; 785 xhci_op_write_4(sc, XHCI_CONFIG, config); 786 787 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 788 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 789 if (err) { 790 aprint_error_dev(sc->sc_dev, "command ring init fail\n"); 791 return err; 792 } 793 794 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 795 XHCI_EVENT_RING_SEGMENTS_ALIGN); 796 if (err) { 797 aprint_error_dev(sc->sc_dev, "event ring init fail\n"); 798 return err; 799 } 800 801 usb_dma_t *dma; 802 size_t size; 803 size_t align; 804 805 dma = &sc->sc_eventst_dma; 806 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 807 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 808 KASSERT(size <= (512 * 1024)); 809 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 810 err = usb_allocmem(&sc->sc_bus, size, align, dma); 811 812 memset(KERNADDR(dma, 0), 0, size); 813 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 814 aprint_debug_dev(sc->sc_dev, "eventst: %s %016jx %p %zx\n", 815 usbd_errstr(err), 816 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 817 KERNADDR(&sc->sc_eventst_dma, 0), 818 sc->sc_eventst_dma.block->size); 819 820 dma = &sc->sc_dcbaa_dma; 821 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 822 KASSERT(size <= 2048); 823 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 824 err = usb_allocmem(&sc->sc_bus, size, align, dma); 825 826 memset(KERNADDR(dma, 0), 0, size); 827 if (sc->sc_maxspbuf != 0) { 828 /* 829 * DCBA entry 0 hold the scratchbuf array pointer. 830 */ 831 *(uint64_t *)KERNADDR(dma, 0) = 832 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 833 } 834 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 835 aprint_debug_dev(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n", 836 usbd_errstr(err), 837 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 838 KERNADDR(&sc->sc_dcbaa_dma, 0), 839 sc->sc_dcbaa_dma.block->size); 840 841 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 842 KM_SLEEP); 843 844 cv_init(&sc->sc_command_cv, "xhcicmd"); 845 846 struct xhci_erste *erst; 847 erst = KERNADDR(&sc->sc_eventst_dma, 0); 848 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 849 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 850 erst[0].erste_3 = htole32(0); 851 usb_syncmem(&sc->sc_eventst_dma, 0, 852 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 853 854 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 855 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 856 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 857 XHCI_ERDP_LO_BUSY); 858 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 859 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 860 sc->sc_cr.xr_cs); 861 862 #if 0 863 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 864 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 865 #endif 866 867 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 868 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 869 870 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 871 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 872 xhci_op_read_4(sc, XHCI_USBCMD)); 873 874 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 875 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 876 cv_init(&sc->sc_softwake_cv, "xhciab"); 877 878 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 879 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 880 881 /* Set up the bus struct. */ 882 sc->sc_bus.methods = &xhci_bus_methods; 883 sc->sc_bus.pipe_size = sizeof(struct xhci_pipe); 884 885 return USBD_NORMAL_COMPLETION; 886 } 887 888 int 889 xhci_intr(void *v) 890 { 891 struct xhci_softc * const sc = v; 892 int ret = 0; 893 894 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 895 896 if (sc == NULL) 897 return 0; 898 899 mutex_spin_enter(&sc->sc_intr_lock); 900 901 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 902 goto done; 903 904 /* If we get an interrupt while polling, then just ignore it. */ 905 if (sc->sc_bus.use_polling) { 906 #ifdef DIAGNOSTIC 907 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 908 #endif 909 goto done; 910 } 911 912 ret = xhci_intr1(sc); 913 done: 914 mutex_spin_exit(&sc->sc_intr_lock); 915 return ret; 916 } 917 918 int 919 xhci_intr1(struct xhci_softc * const sc) 920 { 921 uint32_t usbsts; 922 uint32_t iman; 923 924 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 925 926 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 927 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 928 #if 0 929 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 930 return 0; 931 } 932 #endif 933 xhci_op_write_4(sc, XHCI_USBSTS, 934 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 935 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 936 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 937 938 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 939 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 940 if ((iman & XHCI_IMAN_INTR_PEND) == 0) { 941 return 0; 942 } 943 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 944 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 945 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 946 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 947 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 948 949 usb_schedsoftintr(&sc->sc_bus); 950 951 return 1; 952 } 953 954 static usbd_status 955 xhci_configure_endpoint(usbd_pipe_handle pipe) 956 { 957 struct xhci_softc * const sc = pipe->device->bus->hci_private; 958 struct xhci_slot * const xs = pipe->device->hci_private; 959 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 960 usb_endpoint_descriptor_t * const ed = pipe->endpoint->edesc; 961 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 962 struct xhci_trb trb; 963 usbd_status err; 964 uint32_t *cp; 965 966 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 967 DPRINTFN(4, "dci %u epaddr 0x%02x attr 0x%02x", 968 dci, ed->bEndpointAddress, ed->bmAttributes, 0); 969 970 /* XXX ensure input context is available? */ 971 972 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 973 974 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 975 cp[0] = htole32(0); 976 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 977 978 /* set up input slot context */ 979 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 980 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 981 cp[1] = htole32(0); 982 cp[2] = htole32(0); 983 cp[3] = htole32(0); 984 985 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 986 if (xfertype == UE_INTERRUPT) { 987 cp[0] = htole32( 988 XHCI_EPCTX_0_IVAL_SET(3) /* XXX */ 989 ); 990 cp[1] = htole32( 991 XHCI_EPCTX_1_CERR_SET(3) | 992 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(pipe->endpoint->edesc)) | 993 XHCI_EPCTX_1_MAXB_SET(0) | 994 XHCI_EPCTX_1_MAXP_SIZE_SET(8) /* XXX */ 995 ); 996 cp[4] = htole32( 997 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 998 ); 999 } else { 1000 cp[0] = htole32(0); 1001 cp[1] = htole32( 1002 XHCI_EPCTX_1_CERR_SET(3) | 1003 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(pipe->endpoint->edesc)) | 1004 XHCI_EPCTX_1_MAXB_SET(0) | 1005 XHCI_EPCTX_1_MAXP_SIZE_SET(512) /* XXX */ 1006 ); 1007 } 1008 *(uint64_t *)(&cp[2]) = htole64( 1009 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 1010 XHCI_EPCTX_2_DCS_SET(1)); 1011 1012 /* sync input contexts before they are read from memory */ 1013 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1014 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1015 sc->sc_ctxsz * 1); 1016 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1017 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1018 1019 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1020 trb.trb_2 = 0; 1021 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1022 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1023 1024 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1025 1026 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1027 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1028 sc->sc_ctxsz * 1); 1029 1030 return err; 1031 } 1032 1033 static usbd_status 1034 xhci_unconfigure_endpoint(usbd_pipe_handle pipe) 1035 { 1036 #ifdef USB_DEBUG 1037 struct xhci_slot * const xs = pipe->device->hci_private; 1038 #endif 1039 1040 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1041 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1042 1043 return USBD_NORMAL_COMPLETION; 1044 } 1045 1046 static usbd_status 1047 xhci_reset_endpoint(usbd_pipe_handle pipe) 1048 { 1049 struct xhci_softc * const sc = pipe->device->bus->hci_private; 1050 struct xhci_slot * const xs = pipe->device->hci_private; 1051 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 1052 struct xhci_trb trb; 1053 usbd_status err; 1054 1055 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1056 DPRINTFN(4, "dci %u", dci, 0, 0, 0); 1057 1058 trb.trb_0 = 0; 1059 trb.trb_2 = 0; 1060 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1061 XHCI_TRB_3_EP_SET(dci) | 1062 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1063 1064 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1065 1066 return err; 1067 } 1068 1069 #if 0 1070 static usbd_status 1071 xhci_stop_endpoint(usbd_pipe_handle pipe) 1072 { 1073 struct xhci_softc * const sc = pipe->device->bus->hci_private; 1074 struct xhci_slot * const xs = pipe->device->hci_private; 1075 struct xhci_trb trb; 1076 usbd_status err; 1077 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 1078 1079 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1080 DPRINTFN(4, "dci %u", dci, 0, 0, 0); 1081 1082 trb.trb_0 = 0; 1083 trb.trb_2 = 0; 1084 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1085 XHCI_TRB_3_EP_SET(dci) | 1086 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1087 1088 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1089 1090 return err; 1091 } 1092 #endif 1093 1094 static usbd_status 1095 xhci_set_dequeue(usbd_pipe_handle pipe) 1096 { 1097 struct xhci_softc * const sc = pipe->device->bus->hci_private; 1098 struct xhci_slot * const xs = pipe->device->hci_private; 1099 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 1100 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1101 struct xhci_trb trb; 1102 usbd_status err; 1103 1104 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1105 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1106 1107 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1108 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1109 BUS_DMASYNC_PREWRITE); 1110 1111 xr->xr_ep = 0; 1112 xr->xr_cs = 1; 1113 1114 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1115 trb.trb_2 = 0; 1116 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1117 XHCI_TRB_3_EP_SET(dci) | 1118 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1119 1120 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1121 1122 return err; 1123 } 1124 1125 static usbd_status 1126 xhci_open(usbd_pipe_handle pipe) 1127 { 1128 usbd_device_handle const dev = pipe->device; 1129 struct xhci_softc * const sc = dev->bus->hci_private; 1130 usb_endpoint_descriptor_t * const ed = pipe->endpoint->edesc; 1131 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1132 1133 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1134 DPRINTFN(1, "addr %d depth %d port %d speed %d", 1135 dev->address, dev->depth, dev->powersrc->portno, dev->speed); 1136 1137 if (sc->sc_dying) 1138 return USBD_IOERROR; 1139 1140 /* Root Hub */ 1141 if (dev->depth == 0 && dev->powersrc->portno == 0 && 1142 dev->speed != USB_SPEED_SUPER) { 1143 switch (ed->bEndpointAddress) { 1144 case USB_CONTROL_ENDPOINT: 1145 pipe->methods = &xhci_root_ctrl_methods; 1146 break; 1147 case UE_DIR_IN | XHCI_INTR_ENDPT: 1148 pipe->methods = &xhci_root_intr_methods; 1149 break; 1150 default: 1151 pipe->methods = NULL; 1152 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1153 ed->bEndpointAddress, 0, 0, 0); 1154 return USBD_INVAL; 1155 } 1156 return USBD_NORMAL_COMPLETION; 1157 } 1158 1159 switch (xfertype) { 1160 case UE_CONTROL: 1161 pipe->methods = &xhci_device_ctrl_methods; 1162 break; 1163 case UE_ISOCHRONOUS: 1164 pipe->methods = &xhci_device_isoc_methods; 1165 return USBD_INVAL; 1166 break; 1167 case UE_BULK: 1168 pipe->methods = &xhci_device_bulk_methods; 1169 break; 1170 case UE_INTERRUPT: 1171 pipe->methods = &xhci_device_intr_methods; 1172 break; 1173 default: 1174 return USBD_IOERROR; 1175 break; 1176 } 1177 1178 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1179 xhci_configure_endpoint(pipe); 1180 1181 return USBD_NORMAL_COMPLETION; 1182 } 1183 1184 static void 1185 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1186 { 1187 usbd_xfer_handle const xfer = sc->sc_intrxfer; 1188 uint8_t *p; 1189 1190 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1191 DPRINTFN(4, "port %u status change", port, 0, 0, 0); 1192 1193 if (xfer == NULL) 1194 return; 1195 1196 if (!(port >= sc->sc_hs_port_start && 1197 port < sc->sc_hs_port_start + sc->sc_hs_port_count)) 1198 return; 1199 1200 port -= sc->sc_hs_port_start; 1201 port += 1; 1202 DPRINTFN(4, "hs port %u status change", port, 0, 0, 0); 1203 1204 p = KERNADDR(&xfer->dmabuf, 0); 1205 memset(p, 0, xfer->length); 1206 p[port/NBBY] |= 1 << (port%NBBY); 1207 xfer->actlen = xfer->length; 1208 xfer->status = USBD_NORMAL_COMPLETION; 1209 usb_transfer_complete(xfer); 1210 } 1211 1212 static void 1213 xhci_handle_event(struct xhci_softc * const sc, 1214 const struct xhci_trb * const trb) 1215 { 1216 uint64_t trb_0; 1217 uint32_t trb_2, trb_3; 1218 1219 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1220 1221 trb_0 = le64toh(trb->trb_0); 1222 trb_2 = le32toh(trb->trb_2); 1223 trb_3 = le32toh(trb->trb_3); 1224 1225 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1226 trb, trb_0, trb_2, trb_3); 1227 1228 switch (XHCI_TRB_3_TYPE_GET(trb_3)){ 1229 case XHCI_TRB_EVENT_TRANSFER: { 1230 u_int slot, dci; 1231 struct xhci_slot *xs; 1232 struct xhci_ring *xr; 1233 struct xhci_xfer *xx; 1234 usbd_xfer_handle xfer; 1235 usbd_status err; 1236 1237 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1238 dci = XHCI_TRB_3_EP_GET(trb_3); 1239 1240 xs = &sc->sc_slots[slot]; 1241 xr = &xs->xs_ep[dci].xe_tr; 1242 1243 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1244 xx = xr->xr_cookies[(trb_0 - xhci_ring_trbp(xr, 0))/ 1245 sizeof(struct xhci_trb)]; 1246 } else { 1247 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1248 } 1249 xfer = &xx->xx_xfer; 1250 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1251 1252 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1253 DPRINTFN(14, "transfer event data: " 1254 "0x%016"PRIx64" 0x%08"PRIx32" %02x", 1255 trb_0, XHCI_TRB_2_REM_GET(trb_2), 1256 XHCI_TRB_2_ERROR_GET(trb_2), 0); 1257 if ((trb_0 & 0x3) == 0x3) { 1258 xfer->actlen = XHCI_TRB_2_REM_GET(trb_2); 1259 } 1260 } 1261 1262 if (XHCI_TRB_2_ERROR_GET(trb_2) == 1263 XHCI_TRB_ERROR_SUCCESS) { 1264 xfer->actlen = xfer->length - XHCI_TRB_2_REM_GET(trb_2); 1265 err = USBD_NORMAL_COMPLETION; 1266 } else if (XHCI_TRB_2_ERROR_GET(trb_2) == 1267 XHCI_TRB_ERROR_SHORT_PKT) { 1268 xfer->actlen = xfer->length - XHCI_TRB_2_REM_GET(trb_2); 1269 err = USBD_NORMAL_COMPLETION; 1270 } else if (XHCI_TRB_2_ERROR_GET(trb_2) == 1271 XHCI_TRB_ERROR_STALL) { 1272 err = USBD_STALLED; 1273 xr->is_halted = true; 1274 DPRINTFN(1, "ev: xfer done: err %u slot %u dci %u", 1275 XHCI_TRB_2_ERROR_GET(trb_2), slot, dci, 0); 1276 } else { 1277 err = USBD_IOERROR; 1278 } 1279 xfer->status = err; 1280 1281 //mutex_enter(&sc->sc_lock); /* XXX ??? */ 1282 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1283 if ((trb_0 & 0x3) == 0x0) { 1284 usb_transfer_complete(xfer); 1285 } 1286 } else { 1287 usb_transfer_complete(xfer); 1288 } 1289 //mutex_exit(&sc->sc_lock); /* XXX ??? */ 1290 1291 } 1292 break; 1293 case XHCI_TRB_EVENT_CMD_COMPLETE: 1294 if (trb_0 == sc->sc_command_addr) { 1295 sc->sc_result_trb.trb_0 = trb_0; 1296 sc->sc_result_trb.trb_2 = trb_2; 1297 sc->sc_result_trb.trb_3 = trb_3; 1298 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1299 XHCI_TRB_ERROR_SUCCESS) { 1300 DPRINTFN(1, "command completion " 1301 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1302 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1303 } 1304 cv_signal(&sc->sc_command_cv); 1305 } else { 1306 DPRINTFN(1, "event: %p 0x%016"PRIx64" " 1307 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1308 trb_2, trb_3); 1309 } 1310 break; 1311 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1312 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1313 break; 1314 default: 1315 break; 1316 } 1317 } 1318 1319 static void 1320 xhci_softintr(void *v) 1321 { 1322 struct usbd_bus * const bus = v; 1323 struct xhci_softc * const sc = bus->hci_private; 1324 struct xhci_ring * const er = &sc->sc_er; 1325 struct xhci_trb *trb; 1326 int i, j, k; 1327 1328 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1329 1330 i = er->xr_ep; 1331 j = er->xr_cs; 1332 1333 DPRINTFN(16, "xr_ep %d xr_cs %d", i, j, 0, 0); 1334 1335 while (1) { 1336 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 1337 BUS_DMASYNC_POSTREAD); 1338 trb = &er->xr_trb[i]; 1339 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1340 1341 if (j != k) 1342 break; 1343 1344 xhci_handle_event(sc, trb); 1345 1346 i++; 1347 if (i == XHCI_EVENT_RING_TRBS) { 1348 i = 0; 1349 j ^= 1; 1350 } 1351 } 1352 1353 er->xr_ep = i; 1354 er->xr_cs = j; 1355 1356 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 1357 XHCI_ERDP_LO_BUSY); 1358 1359 DPRINTFN(16, "ends", 0, 0, 0, 0); 1360 1361 return; 1362 } 1363 1364 static void 1365 xhci_poll(struct usbd_bus *bus) 1366 { 1367 struct xhci_softc * const sc = bus->hci_private; 1368 1369 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1370 1371 mutex_spin_enter(&sc->sc_intr_lock); 1372 xhci_intr1(sc); 1373 mutex_spin_exit(&sc->sc_intr_lock); 1374 1375 return; 1376 } 1377 1378 static usbd_status 1379 xhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, uint32_t size) 1380 { 1381 struct xhci_softc * const sc = bus->hci_private; 1382 usbd_status err; 1383 1384 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1385 1386 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1387 #if 0 1388 if (err == USBD_NOMEM) 1389 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1390 #endif 1391 #ifdef XHCI_DEBUG 1392 if (err) 1393 DPRINTFN(1, "usb_allocmem(%u)=%d", err, size, 0, 0); 1394 #endif 1395 1396 return err; 1397 } 1398 1399 static void 1400 xhci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1401 { 1402 struct xhci_softc * const sc = bus->hci_private; 1403 1404 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1405 1406 #if 0 1407 if (dma->block->flags & USB_DMA_RESERVE) { 1408 usb_reserve_freem(&sc->sc_dma_reserve, dma); 1409 return; 1410 } 1411 #endif 1412 usb_freemem(&sc->sc_bus, dma); 1413 } 1414 1415 static usbd_xfer_handle 1416 xhci_allocx(struct usbd_bus *bus) 1417 { 1418 struct xhci_softc * const sc = bus->hci_private; 1419 usbd_xfer_handle xfer; 1420 1421 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1422 1423 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1424 if (xfer != NULL) { 1425 memset(xfer, 0, sizeof(struct xhci_xfer)); 1426 #ifdef DIAGNOSTIC 1427 xfer->busy_free = XFER_BUSY; 1428 #endif 1429 } 1430 1431 return xfer; 1432 } 1433 1434 static void 1435 xhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1436 { 1437 struct xhci_softc * const sc = bus->hci_private; 1438 1439 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1440 1441 #ifdef DIAGNOSTIC 1442 if (xfer->busy_free != XFER_BUSY) { 1443 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 1444 xfer, xfer->busy_free, 0, 0); 1445 } 1446 xfer->busy_free = XFER_FREE; 1447 #endif 1448 pool_cache_put(sc->sc_xferpool, xfer); 1449 } 1450 1451 static void 1452 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1453 { 1454 struct xhci_softc * const sc = bus->hci_private; 1455 1456 *lock = &sc->sc_lock; 1457 } 1458 1459 extern uint32_t usb_cookie_no; 1460 1461 static usbd_status 1462 xhci_new_device(device_t parent, usbd_bus_handle bus, int depth, 1463 int speed, int port, struct usbd_port *up) 1464 { 1465 struct xhci_softc * const sc = bus->hci_private; 1466 usbd_device_handle dev; 1467 usbd_status err; 1468 usb_device_descriptor_t *dd; 1469 struct usbd_device *hub; 1470 struct usbd_device *adev; 1471 int rhport = 0; 1472 struct xhci_slot *xs; 1473 uint32_t *cp; 1474 uint8_t slot; 1475 uint8_t addr; 1476 1477 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1478 DPRINTFN(4, "port=%d depth=%d speed=%d upport %d", 1479 port, depth, speed, up->portno); 1480 1481 dev = malloc(sizeof *dev, M_USB, M_NOWAIT|M_ZERO); 1482 if (dev == NULL) 1483 return USBD_NOMEM; 1484 1485 dev->bus = bus; 1486 1487 /* Set up default endpoint handle. */ 1488 dev->def_ep.edesc = &dev->def_ep_desc; 1489 1490 /* Set up default endpoint descriptor. */ 1491 dev->def_ep_desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 1492 dev->def_ep_desc.bDescriptorType = UDESC_ENDPOINT; 1493 dev->def_ep_desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 1494 dev->def_ep_desc.bmAttributes = UE_CONTROL; 1495 /* XXX */ 1496 if (speed == USB_SPEED_LOW) 1497 USETW(dev->def_ep_desc.wMaxPacketSize, USB_MAX_IPACKET); 1498 else 1499 USETW(dev->def_ep_desc.wMaxPacketSize, 64); 1500 dev->def_ep_desc.bInterval = 0; 1501 1502 /* doesn't matter, just don't let it uninitialized */ 1503 dev->def_ep.datatoggle = 0; 1504 1505 DPRINTFN(4, "up %p portno %d", up, up->portno, 0, 0); 1506 1507 dev->quirks = &usbd_no_quirk; 1508 dev->address = 0; 1509 dev->ddesc.bMaxPacketSize = 0; 1510 dev->depth = depth; 1511 dev->powersrc = up; 1512 dev->myhub = up->parent; 1513 1514 up->device = dev; 1515 1516 /* Locate root hub port */ 1517 for (adev = dev, hub = dev; 1518 hub != NULL; 1519 adev = hub, hub = hub->myhub) { 1520 DPRINTFN(4, "hub %p", hub, 0, 0, 0); 1521 } 1522 DPRINTFN(4, "hub %p", hub, 0, 0, 0); 1523 1524 if (hub != NULL) { 1525 for (int p = 0; p < hub->hub->hubdesc.bNbrPorts; p++) { 1526 if (hub->hub->ports[p].device == adev) { 1527 rhport = p; 1528 } 1529 } 1530 } else { 1531 rhport = port; 1532 } 1533 if (speed == USB_SPEED_SUPER) { 1534 rhport += sc->sc_ss_port_start - 1; 1535 } else { 1536 rhport += sc->sc_hs_port_start - 1; 1537 } 1538 DPRINTFN(4, "rhport %d", rhport, 0, 0, 0); 1539 1540 dev->speed = speed; 1541 dev->langid = USBD_NOLANG; 1542 dev->cookie.cookie = ++usb_cookie_no; 1543 1544 /* Establish the default pipe. */ 1545 err = usbd_setup_pipe(dev, 0, &dev->def_ep, USBD_DEFAULT_INTERVAL, 1546 &dev->default_pipe); 1547 if (err) { 1548 usbd_remove_device(dev, up); 1549 return (err); 1550 } 1551 1552 dd = &dev->ddesc; 1553 1554 if ((depth == 0) && (port == 0)) { 1555 KASSERT(bus->devices[dev->address] == NULL); 1556 bus->devices[dev->address] = dev; 1557 err = usbd_get_initial_ddesc(dev, dd); 1558 if (err) 1559 return err; 1560 err = usbd_reload_device_desc(dev); 1561 if (err) 1562 return err; 1563 } else { 1564 err = xhci_enable_slot(sc, &slot); 1565 if (err) 1566 return err; 1567 err = xhci_init_slot(sc, slot, depth, speed, port, rhport); 1568 if (err) 1569 return err; 1570 xs = &sc->sc_slots[slot]; 1571 dev->hci_private = xs; 1572 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 1573 //hexdump("slot context", cp, sc->sc_ctxsz); 1574 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 1575 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 1576 /* XXX ensure we know when the hardware does something 1577 we can't yet cope with */ 1578 KASSERT(addr >= 1 && addr <= 127); 1579 dev->address = addr; 1580 /* XXX dev->address not necessarily unique on bus */ 1581 KASSERT(bus->devices[dev->address] == NULL); 1582 bus->devices[dev->address] = dev; 1583 1584 err = usbd_get_initial_ddesc(dev, dd); 1585 if (err) 1586 return err; 1587 /* 4.8.2.1 */ 1588 if (speed == USB_SPEED_SUPER) 1589 USETW(dev->def_ep_desc.wMaxPacketSize, 1590 (1 << dd->bMaxPacketSize)); 1591 else 1592 USETW(dev->def_ep_desc.wMaxPacketSize, 1593 dd->bMaxPacketSize); 1594 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 1595 xhci_update_ep0_mps(sc, xs, 1596 UGETW(dev->def_ep_desc.wMaxPacketSize)); 1597 err = usbd_reload_device_desc(dev); 1598 if (err) 1599 return err; 1600 1601 usbd_kill_pipe(dev->default_pipe); 1602 err = usbd_setup_pipe(dev, 0, &dev->def_ep, 1603 USBD_DEFAULT_INTERVAL, &dev->default_pipe); 1604 } 1605 1606 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 1607 dev->address, UGETW(dd->bcdUSB), 0, 0); 1608 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 1609 dd->bDeviceClass, dd->bDeviceSubClass, 1610 dd->bDeviceProtocol, 0); 1611 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 1612 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 1613 dev->speed); 1614 1615 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 1616 1617 if ((depth == 0) && (port == 0)) { 1618 usbd_attach_roothub(parent, dev); 1619 DPRINTFN(1, "root_hub %p", bus->root_hub, 0, 0, 0); 1620 return USBD_NORMAL_COMPLETION; 1621 } 1622 1623 1624 err = usbd_probe_and_attach(parent, dev, port, dev->address); 1625 if (err) { 1626 usbd_remove_device(dev, up); 1627 return (err); 1628 } 1629 1630 return USBD_NORMAL_COMPLETION; 1631 } 1632 1633 static usbd_status 1634 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 1635 size_t ntrb, size_t align) 1636 { 1637 usbd_status err; 1638 size_t size = ntrb * XHCI_TRB_SIZE; 1639 1640 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1641 1642 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 1643 if (err) 1644 return err; 1645 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1646 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 1647 xr->xr_trb = xhci_ring_trbv(xr, 0); 1648 xr->xr_ntrb = ntrb; 1649 xr->xr_ep = 0; 1650 xr->xr_cs = 1; 1651 memset(xr->xr_trb, 0, size); 1652 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 1653 xr->is_halted = false; 1654 1655 return USBD_NORMAL_COMPLETION; 1656 } 1657 1658 static void 1659 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 1660 { 1661 usb_freemem(&sc->sc_bus, &xr->xr_dma); 1662 mutex_destroy(&xr->xr_lock); 1663 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 1664 } 1665 1666 static void 1667 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 1668 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 1669 { 1670 size_t i; 1671 u_int ri; 1672 u_int cs; 1673 uint64_t parameter; 1674 uint32_t status; 1675 uint32_t control; 1676 1677 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1678 1679 for (i = 0; i < ntrbs; i++) { 1680 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 1681 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 1682 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 1683 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 1684 XHCI_TRB_TYPE_LINK); 1685 } 1686 1687 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 1688 1689 ri = xr->xr_ep; 1690 cs = xr->xr_cs; 1691 1692 /* 1693 * Although the xhci hardware can do scatter/gather dma from 1694 * arbitrary sized buffers, there is a non-obvious restriction 1695 * that a LINK trb is only allowed at the end of a burst of 1696 * transfers - which might be 16kB. 1697 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 1698 * The simple solution is not to allow a LINK trb in the middle 1699 * of anything - as here. 1700 * XXX: (dsl) There are xhci controllers out there (eg some made by 1701 * ASMedia) that seem to lock up if they process a LINK trb but 1702 * cannot process the linked-to trb yet. 1703 * The code should write the 'cycle' bit on the link trb AFTER 1704 * adding the other trb. 1705 */ 1706 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 1707 parameter = xhci_ring_trbp(xr, 0); 1708 status = 0; 1709 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1710 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 1711 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 1712 htole32(status), htole32(control)); 1713 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1714 BUS_DMASYNC_PREWRITE); 1715 xr->xr_cookies[ri] = NULL; 1716 xr->xr_ep = 0; 1717 xr->xr_cs ^= 1; 1718 ri = xr->xr_ep; 1719 cs = xr->xr_cs; 1720 } 1721 1722 ri++; 1723 1724 /* Write any subsequent TRB first */ 1725 for (i = 1; i < ntrbs; i++) { 1726 parameter = trbs[i].trb_0; 1727 status = trbs[i].trb_2; 1728 control = trbs[i].trb_3; 1729 1730 if (cs) { 1731 control |= XHCI_TRB_3_CYCLE_BIT; 1732 } else { 1733 control &= ~XHCI_TRB_3_CYCLE_BIT; 1734 } 1735 1736 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 1737 htole32(status), htole32(control)); 1738 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1739 BUS_DMASYNC_PREWRITE); 1740 xr->xr_cookies[ri] = cookie; 1741 ri++; 1742 } 1743 1744 /* Write the first TRB last */ 1745 i = 0; 1746 { 1747 parameter = trbs[i].trb_0; 1748 status = trbs[i].trb_2; 1749 control = trbs[i].trb_3; 1750 1751 if (xr->xr_cs) { 1752 control |= XHCI_TRB_3_CYCLE_BIT; 1753 } else { 1754 control &= ~XHCI_TRB_3_CYCLE_BIT; 1755 } 1756 1757 xhci_trb_put(&xr->xr_trb[xr->xr_ep], htole64(parameter), 1758 htole32(status), htole32(control)); 1759 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1760 BUS_DMASYNC_PREWRITE); 1761 xr->xr_cookies[xr->xr_ep] = cookie; 1762 } 1763 1764 xr->xr_ep = ri; 1765 xr->xr_cs = cs; 1766 1767 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 1768 } 1769 1770 static usbd_status 1771 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 1772 int timeout) 1773 { 1774 struct xhci_ring * const cr = &sc->sc_cr; 1775 usbd_status err; 1776 1777 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1778 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1779 trb->trb_0, trb->trb_2, trb->trb_3, 0); 1780 1781 mutex_enter(&sc->sc_lock); 1782 1783 KASSERT(sc->sc_command_addr == 0); 1784 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 1785 1786 mutex_enter(&cr->xr_lock); 1787 xhci_ring_put(sc, cr, NULL, trb, 1); 1788 mutex_exit(&cr->xr_lock); 1789 1790 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 1791 1792 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 1793 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 1794 err = USBD_TIMEOUT; 1795 goto timedout; 1796 } 1797 1798 trb->trb_0 = sc->sc_result_trb.trb_0; 1799 trb->trb_2 = sc->sc_result_trb.trb_2; 1800 trb->trb_3 = sc->sc_result_trb.trb_3; 1801 1802 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 1803 trb->trb_0, trb->trb_2, trb->trb_3, 0); 1804 1805 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 1806 case XHCI_TRB_ERROR_SUCCESS: 1807 err = USBD_NORMAL_COMPLETION; 1808 break; 1809 default: 1810 case 192 ... 223: 1811 err = USBD_IOERROR; 1812 break; 1813 case 224 ... 255: 1814 err = USBD_NORMAL_COMPLETION; 1815 break; 1816 } 1817 1818 timedout: 1819 sc->sc_command_addr = 0; 1820 mutex_exit(&sc->sc_lock); 1821 return err; 1822 } 1823 1824 static usbd_status 1825 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 1826 { 1827 struct xhci_trb trb; 1828 usbd_status err; 1829 1830 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1831 1832 trb.trb_0 = 0; 1833 trb.trb_2 = 0; 1834 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 1835 1836 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1837 if (err != USBD_NORMAL_COMPLETION) { 1838 return err; 1839 } 1840 1841 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 1842 1843 return err; 1844 } 1845 1846 static usbd_status 1847 xhci_address_device(struct xhci_softc * const sc, 1848 uint64_t icp, uint8_t slot_id, bool bsr) 1849 { 1850 struct xhci_trb trb; 1851 usbd_status err; 1852 1853 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1854 1855 trb.trb_0 = icp; 1856 trb.trb_2 = 0; 1857 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 1858 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1859 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 1860 1861 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1862 return err; 1863 } 1864 1865 static usbd_status 1866 xhci_update_ep0_mps(struct xhci_softc * const sc, 1867 struct xhci_slot * const xs, u_int mps) 1868 { 1869 struct xhci_trb trb; 1870 usbd_status err; 1871 uint32_t * cp; 1872 1873 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1874 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 1875 1876 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1877 cp[0] = htole32(0); 1878 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 1879 1880 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 1881 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1882 1883 /* sync input contexts before they are read from memory */ 1884 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1885 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 1886 sc->sc_ctxsz * 4); 1887 1888 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1889 trb.trb_2 = 0; 1890 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1891 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 1892 1893 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1894 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 1895 return err; 1896 } 1897 1898 static void 1899 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 1900 { 1901 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 1902 1903 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1904 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 1905 &dcbaa[si], dcba, si, 0); 1906 1907 dcbaa[si] = htole64(dcba); 1908 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 1909 BUS_DMASYNC_PREWRITE); 1910 } 1911 1912 static usbd_status 1913 xhci_init_slot(struct xhci_softc * const sc, uint32_t slot, int depth, 1914 int speed, int port, int rhport) 1915 { 1916 struct xhci_slot *xs; 1917 usbd_status err; 1918 u_int dci; 1919 uint32_t *cp; 1920 uint32_t mps; 1921 uint32_t xspeed; 1922 1923 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1924 DPRINTFN(4, "slot %u depth %d speed %d", 1925 slot, depth, speed, 0); 1926 DPRINTFN(4, " port %d rhport %d", 1927 port, rhport, 0, 0); 1928 1929 switch (speed) { 1930 case USB_SPEED_LOW: 1931 xspeed = 2; 1932 mps = USB_MAX_IPACKET; 1933 break; 1934 case USB_SPEED_FULL: 1935 xspeed = 1; 1936 mps = 64; 1937 break; 1938 case USB_SPEED_HIGH: 1939 xspeed = 3; 1940 mps = USB_2_MAX_CTRL_PACKET; 1941 break; 1942 case USB_SPEED_SUPER: 1943 xspeed = 4; 1944 mps = USB_3_MAX_CTRL_PACKET; 1945 break; 1946 default: 1947 DPRINTFN(0, "impossible speed: %x", speed, 0, 0, 0); 1948 return USBD_INVAL; 1949 } 1950 1951 xs = &sc->sc_slots[slot]; 1952 xs->xs_idx = slot; 1953 1954 /* allocate contexts */ 1955 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 1956 &xs->xs_dc_dma); 1957 if (err) 1958 return err; 1959 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 1960 1961 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 1962 &xs->xs_ic_dma); 1963 if (err) 1964 return err; 1965 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 1966 1967 for (dci = 0; dci < 32; dci++) { 1968 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 1969 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 1970 if (dci == XHCI_DCI_SLOT) 1971 continue; 1972 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 1973 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 1974 if (err) { 1975 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 1976 return err; 1977 } 1978 } 1979 1980 /* set up initial input control context */ 1981 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1982 cp[0] = htole32(0); 1983 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 1984 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 1985 1986 /* set up input slot context */ 1987 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1988 cp[0] = htole32( 1989 XHCI_SCTX_0_CTX_NUM_SET(1) | 1990 XHCI_SCTX_0_SPEED_SET(xspeed) 1991 ); 1992 cp[1] = htole32( 1993 XHCI_SCTX_1_RH_PORT_SET(rhport) 1994 ); 1995 cp[2] = htole32( 1996 XHCI_SCTX_2_IRQ_TARGET_SET(0) 1997 ); 1998 cp[3] = htole32(0); 1999 2000 /* set up input EP0 context */ 2001 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2002 cp[0] = htole32(0); 2003 cp[1] = htole32( 2004 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 2005 XHCI_EPCTX_1_EPTYPE_SET(4) | 2006 XHCI_EPCTX_1_CERR_SET(3) 2007 ); 2008 /* can't use xhci_ep_get_dci() yet? */ 2009 *(uint64_t *)(&cp[2]) = htole64( 2010 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 2011 XHCI_EPCTX_2_DCS_SET(1)); 2012 cp[4] = htole32( 2013 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 2014 ); 2015 2016 /* sync input contexts before they are read from memory */ 2017 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2018 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2019 sc->sc_ctxsz * 3); 2020 2021 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2022 2023 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 2024 false); 2025 2026 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2027 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2028 sc->sc_ctxsz * 2); 2029 2030 return err; 2031 } 2032 2033 /* ----- */ 2034 2035 static void 2036 xhci_noop(usbd_pipe_handle pipe) 2037 { 2038 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2039 } 2040 2041 /* root hub descriptors */ 2042 2043 static const usb_device_descriptor_t xhci_devd = { 2044 USB_DEVICE_DESCRIPTOR_SIZE, 2045 UDESC_DEVICE, /* type */ 2046 {0x00, 0x02}, /* USB version */ 2047 UDCLASS_HUB, /* class */ 2048 UDSUBCLASS_HUB, /* subclass */ 2049 UDPROTO_HSHUBSTT, /* protocol */ 2050 64, /* max packet */ 2051 {0},{0},{0x00,0x01}, /* device id */ 2052 1,2,0, /* string indexes */ 2053 1 /* # of configurations */ 2054 }; 2055 2056 static const usb_device_qualifier_t xhci_odevd = { 2057 USB_DEVICE_DESCRIPTOR_SIZE, 2058 UDESC_DEVICE_QUALIFIER, /* type */ 2059 {0x00, 0x02}, /* USB version */ 2060 UDCLASS_HUB, /* class */ 2061 UDSUBCLASS_HUB, /* subclass */ 2062 UDPROTO_FSHUB, /* protocol */ 2063 64, /* max packet */ 2064 1, /* # of configurations */ 2065 0 2066 }; 2067 2068 static const usb_config_descriptor_t xhci_confd = { 2069 USB_CONFIG_DESCRIPTOR_SIZE, 2070 UDESC_CONFIG, 2071 {USB_CONFIG_DESCRIPTOR_SIZE + 2072 USB_INTERFACE_DESCRIPTOR_SIZE + 2073 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2074 1, 2075 1, 2076 0, 2077 UC_ATTR_MBO | UC_SELF_POWERED, 2078 0 /* max power */ 2079 }; 2080 2081 static const usb_interface_descriptor_t xhci_ifcd = { 2082 USB_INTERFACE_DESCRIPTOR_SIZE, 2083 UDESC_INTERFACE, 2084 0, 2085 0, 2086 1, 2087 UICLASS_HUB, 2088 UISUBCLASS_HUB, 2089 UIPROTO_HSHUBSTT, 2090 0 2091 }; 2092 2093 static const usb_endpoint_descriptor_t xhci_endpd = { 2094 USB_ENDPOINT_DESCRIPTOR_SIZE, 2095 UDESC_ENDPOINT, 2096 UE_DIR_IN | XHCI_INTR_ENDPT, 2097 UE_INTERRUPT, 2098 {8, 0}, /* max packet */ 2099 12 2100 }; 2101 2102 static const usb_hub_descriptor_t xhci_hubd = { 2103 USB_HUB_DESCRIPTOR_SIZE, 2104 UDESC_HUB, 2105 0, 2106 {0,0}, 2107 0, 2108 0, 2109 {""}, 2110 {""}, 2111 }; 2112 2113 /* root hub control */ 2114 2115 static usbd_status 2116 xhci_root_ctrl_transfer(usbd_xfer_handle xfer) 2117 { 2118 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2119 usbd_status err; 2120 2121 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2122 2123 /* Insert last in queue. */ 2124 mutex_enter(&sc->sc_lock); 2125 err = usb_insert_transfer(xfer); 2126 mutex_exit(&sc->sc_lock); 2127 if (err) 2128 return err; 2129 2130 /* Pipe isn't running, start first */ 2131 return (xhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2132 } 2133 2134 static usbd_status 2135 xhci_root_ctrl_start(usbd_xfer_handle xfer) 2136 { 2137 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2138 usb_port_status_t ps; 2139 usb_device_request_t *req; 2140 void *buf = NULL; 2141 usb_hub_descriptor_t hubd; 2142 usbd_status err; 2143 int len, value, index; 2144 int l, totlen = 0; 2145 int port, i; 2146 uint32_t v; 2147 2148 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2149 2150 if (sc->sc_dying) 2151 return USBD_IOERROR; 2152 2153 req = &xfer->request; 2154 2155 value = UGETW(req->wValue); 2156 index = UGETW(req->wIndex); 2157 len = UGETW(req->wLength); 2158 2159 if (len != 0) 2160 buf = KERNADDR(&xfer->dmabuf, 0); 2161 2162 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 2163 req->bmRequestType | (req->bRequest << 8), value, index, len); 2164 2165 #define C(x,y) ((x) | ((y) << 8)) 2166 switch(C(req->bRequest, req->bmRequestType)) { 2167 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2168 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2169 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2170 /* 2171 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2172 * for the integrated root hub. 2173 */ 2174 break; 2175 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2176 if (len > 0) { 2177 *(uint8_t *)buf = sc->sc_conf; 2178 totlen = 1; 2179 } 2180 break; 2181 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2182 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 2183 if (len == 0) 2184 break; 2185 switch(value >> 8) { 2186 case UDESC_DEVICE: 2187 if ((value & 0xff) != 0) { 2188 err = USBD_IOERROR; 2189 goto ret; 2190 } 2191 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2192 memcpy(buf, &xhci_devd, min(l, sizeof(xhci_devd))); 2193 break; 2194 case UDESC_DEVICE_QUALIFIER: 2195 if ((value & 0xff) != 0) { 2196 } 2197 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2198 memcpy(buf, &xhci_odevd, min(l, sizeof(xhci_odevd))); 2199 break; 2200 case UDESC_OTHER_SPEED_CONFIGURATION: 2201 case UDESC_CONFIG: 2202 if ((value & 0xff) != 0) { 2203 err = USBD_IOERROR; 2204 goto ret; 2205 } 2206 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2207 memcpy(buf, &xhci_confd, min(l, sizeof(xhci_confd))); 2208 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2209 value >> 8; 2210 buf = (char *)buf + l; 2211 len -= l; 2212 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2213 totlen += l; 2214 memcpy(buf, &xhci_ifcd, min(l, sizeof(xhci_ifcd))); 2215 buf = (char *)buf + l; 2216 len -= l; 2217 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2218 totlen += l; 2219 memcpy(buf, &xhci_endpd, min(l, sizeof(xhci_endpd))); 2220 break; 2221 case UDESC_STRING: 2222 #define sd ((usb_string_descriptor_t *)buf) 2223 switch (value & 0xff) { 2224 case 0: /* Language table */ 2225 totlen = usb_makelangtbl(sd, len); 2226 break; 2227 case 1: /* Vendor */ 2228 totlen = usb_makestrdesc(sd, len, "NetBSD"); 2229 break; 2230 case 2: /* Product */ 2231 totlen = usb_makestrdesc(sd, len, 2232 "xHCI Root Hub"); 2233 break; 2234 } 2235 #undef sd 2236 break; 2237 default: 2238 err = USBD_IOERROR; 2239 goto ret; 2240 } 2241 break; 2242 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2243 if (len > 0) { 2244 *(uint8_t *)buf = 0; 2245 totlen = 1; 2246 } 2247 break; 2248 case C(UR_GET_STATUS, UT_READ_DEVICE): 2249 if (len > 1) { 2250 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2251 totlen = 2; 2252 } 2253 break; 2254 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2255 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2256 if (len > 1) { 2257 USETW(((usb_status_t *)buf)->wStatus, 0); 2258 totlen = 2; 2259 } 2260 break; 2261 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2262 if (value >= USB_MAX_DEVICES) { 2263 err = USBD_IOERROR; 2264 goto ret; 2265 } 2266 //sc->sc_addr = value; 2267 break; 2268 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2269 if (value != 0 && value != 1) { 2270 err = USBD_IOERROR; 2271 goto ret; 2272 } 2273 sc->sc_conf = value; 2274 break; 2275 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2276 break; 2277 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2278 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2279 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2280 err = USBD_IOERROR; 2281 goto ret; 2282 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2283 break; 2284 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2285 break; 2286 /* Hub requests */ 2287 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2288 break; 2289 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2290 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2291 index, value, 0, 0); 2292 if (index < 1 || index > sc->sc_hs_port_count) { 2293 err = USBD_IOERROR; 2294 goto ret; 2295 } 2296 port = XHCI_PORTSC(sc->sc_hs_port_start - 1 + index); 2297 v = xhci_op_read_4(sc, port); 2298 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2299 v &= ~XHCI_PS_CLEAR; 2300 switch (value) { 2301 case UHF_PORT_ENABLE: 2302 xhci_op_write_4(sc, port, v &~ XHCI_PS_PED); 2303 break; 2304 case UHF_PORT_SUSPEND: 2305 err = USBD_IOERROR; 2306 goto ret; 2307 case UHF_PORT_POWER: 2308 break; 2309 case UHF_PORT_TEST: 2310 case UHF_PORT_INDICATOR: 2311 err = USBD_IOERROR; 2312 goto ret; 2313 case UHF_C_PORT_CONNECTION: 2314 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2315 break; 2316 case UHF_C_PORT_ENABLE: 2317 case UHF_C_PORT_SUSPEND: 2318 case UHF_C_PORT_OVER_CURRENT: 2319 err = USBD_IOERROR; 2320 goto ret; 2321 case UHF_C_PORT_RESET: 2322 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2323 break; 2324 default: 2325 err = USBD_IOERROR; 2326 goto ret; 2327 } 2328 2329 break; 2330 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2331 if (len == 0) 2332 break; 2333 if ((value & 0xff) != 0) { 2334 err = USBD_IOERROR; 2335 goto ret; 2336 } 2337 hubd = xhci_hubd; 2338 hubd.bNbrPorts = sc->sc_hs_port_count; 2339 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2340 hubd.bPwrOn2PwrGood = 200; 2341 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 2342 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2343 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2344 l = min(len, hubd.bDescLength); 2345 totlen = l; 2346 memcpy(buf, &hubd, l); 2347 break; 2348 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2349 if (len != 4) { 2350 err = USBD_IOERROR; 2351 goto ret; 2352 } 2353 memset(buf, 0, len); /* ? XXX */ 2354 totlen = len; 2355 break; 2356 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2357 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2358 if (index < 1 || index > sc->sc_maxports) { 2359 err = USBD_IOERROR; 2360 goto ret; 2361 } 2362 if (len != 4) { 2363 err = USBD_IOERROR; 2364 goto ret; 2365 } 2366 v = xhci_op_read_4(sc, XHCI_PORTSC(sc->sc_hs_port_start - 1 + 2367 index)); 2368 DPRINTFN(4, "READ_CLASS_OTHER GET_STATUS PORTSC %d (%d) %08x", 2369 index, sc->sc_hs_port_start - 1 + index, v, 0); 2370 switch (XHCI_PS_SPEED_GET(v)) { 2371 case 1: 2372 i = UPS_FULL_SPEED; 2373 break; 2374 case 2: 2375 i = UPS_LOW_SPEED; 2376 break; 2377 case 3: 2378 i = UPS_HIGH_SPEED; 2379 break; 2380 default: 2381 i = 0; 2382 break; 2383 } 2384 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2385 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2386 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2387 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 2388 if (v & XHCI_PS_PR) i |= UPS_RESET; 2389 if (v & XHCI_PS_PP) i |= UPS_PORT_POWER; 2390 USETW(ps.wPortStatus, i); 2391 i = 0; 2392 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2393 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2394 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2395 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2396 USETW(ps.wPortChange, i); 2397 l = min(len, sizeof ps); 2398 memcpy(buf, &ps, l); 2399 totlen = l; 2400 break; 2401 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2402 err = USBD_IOERROR; 2403 goto ret; 2404 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2405 break; 2406 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2407 if (index < 1 || index > sc->sc_hs_port_count) { 2408 err = USBD_IOERROR; 2409 goto ret; 2410 } 2411 port = XHCI_PORTSC(sc->sc_hs_port_start - 1 + index); 2412 v = xhci_op_read_4(sc, port); 2413 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2414 v &= ~XHCI_PS_CLEAR; 2415 switch (value) { 2416 case UHF_PORT_ENABLE: 2417 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 2418 break; 2419 case UHF_PORT_SUSPEND: 2420 /* XXX suspend */ 2421 break; 2422 case UHF_PORT_RESET: 2423 v &= ~ (XHCI_PS_PED | XHCI_PS_PR); 2424 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 2425 /* Wait for reset to complete. */ 2426 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2427 if (sc->sc_dying) { 2428 err = USBD_IOERROR; 2429 goto ret; 2430 } 2431 v = xhci_op_read_4(sc, port); 2432 if (v & XHCI_PS_PR) { 2433 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 2434 usb_delay_ms(&sc->sc_bus, 10); 2435 /* XXX */ 2436 } 2437 break; 2438 case UHF_PORT_POWER: 2439 /* XXX power control */ 2440 break; 2441 /* XXX more */ 2442 case UHF_C_PORT_RESET: 2443 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2444 break; 2445 default: 2446 err = USBD_IOERROR; 2447 goto ret; 2448 } 2449 break; 2450 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2451 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2452 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2453 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2454 break; 2455 default: 2456 err = USBD_IOERROR; 2457 goto ret; 2458 } 2459 xfer->actlen = totlen; 2460 err = USBD_NORMAL_COMPLETION; 2461 ret: 2462 xfer->status = err; 2463 mutex_enter(&sc->sc_lock); 2464 usb_transfer_complete(xfer); 2465 mutex_exit(&sc->sc_lock); 2466 return USBD_IN_PROGRESS; 2467 } 2468 2469 2470 static void 2471 xhci_root_ctrl_abort(usbd_xfer_handle xfer) 2472 { 2473 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2474 /* Nothing to do, all transfers are synchronous. */ 2475 } 2476 2477 2478 static void 2479 xhci_root_ctrl_close(usbd_pipe_handle pipe) 2480 { 2481 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2482 /* Nothing to do. */ 2483 } 2484 2485 static void 2486 xhci_root_ctrl_done(usbd_xfer_handle xfer) 2487 { 2488 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2489 2490 xfer->hcpriv = NULL; 2491 } 2492 2493 /* root hub interrupt */ 2494 2495 static usbd_status 2496 xhci_root_intr_transfer(usbd_xfer_handle xfer) 2497 { 2498 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2499 usbd_status err; 2500 2501 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2502 2503 /* Insert last in queue. */ 2504 mutex_enter(&sc->sc_lock); 2505 err = usb_insert_transfer(xfer); 2506 mutex_exit(&sc->sc_lock); 2507 if (err) 2508 return err; 2509 2510 /* Pipe isn't running, start first */ 2511 return (xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2512 } 2513 2514 static usbd_status 2515 xhci_root_intr_start(usbd_xfer_handle xfer) 2516 { 2517 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2518 2519 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2520 2521 if (sc->sc_dying) 2522 return USBD_IOERROR; 2523 2524 mutex_enter(&sc->sc_lock); 2525 sc->sc_intrxfer = xfer; 2526 mutex_exit(&sc->sc_lock); 2527 2528 return USBD_IN_PROGRESS; 2529 } 2530 2531 static void 2532 xhci_root_intr_abort(usbd_xfer_handle xfer) 2533 { 2534 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2535 2536 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2537 2538 KASSERT(mutex_owned(&sc->sc_lock)); 2539 KASSERT(xfer->pipe->intrxfer == xfer); 2540 2541 DPRINTFN(1, "remove", 0, 0, 0, 0); 2542 2543 sc->sc_intrxfer = NULL; 2544 2545 xfer->status = USBD_CANCELLED; 2546 usb_transfer_complete(xfer); 2547 } 2548 2549 static void 2550 xhci_root_intr_close(usbd_pipe_handle pipe) 2551 { 2552 struct xhci_softc * const sc = pipe->device->bus->hci_private; 2553 2554 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2555 2556 KASSERT(mutex_owned(&sc->sc_lock)); 2557 2558 sc->sc_intrxfer = NULL; 2559 } 2560 2561 static void 2562 xhci_root_intr_done(usbd_xfer_handle xfer) 2563 { 2564 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2565 2566 xfer->hcpriv = NULL; 2567 } 2568 2569 /* -------------- */ 2570 /* device control */ 2571 2572 static usbd_status 2573 xhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2574 { 2575 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2576 usbd_status err; 2577 2578 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2579 2580 /* Insert last in queue. */ 2581 mutex_enter(&sc->sc_lock); 2582 err = usb_insert_transfer(xfer); 2583 mutex_exit(&sc->sc_lock); 2584 if (err) 2585 return (err); 2586 2587 /* Pipe isn't running, start first */ 2588 return (xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2589 } 2590 2591 static usbd_status 2592 xhci_device_ctrl_start(usbd_xfer_handle xfer) 2593 { 2594 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2595 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2596 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2597 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2598 struct xhci_xfer * const xx = (void *)xfer; 2599 usb_device_request_t * const req = &xfer->request; 2600 const bool isread = UT_GET_DIR(req->bmRequestType) == UT_READ; 2601 const uint32_t len = UGETW(req->wLength); 2602 usb_dma_t * const dma = &xfer->dmabuf; 2603 uint64_t parameter; 2604 uint32_t status; 2605 uint32_t control; 2606 u_int i; 2607 2608 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2609 DPRINTFN(12, "req: %04x %04x %04x %04x", 2610 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 2611 UGETW(req->wIndex), UGETW(req->wLength)); 2612 2613 /* XXX */ 2614 if (tr->is_halted) { 2615 xhci_reset_endpoint(xfer->pipe); 2616 tr->is_halted = false; 2617 xhci_set_dequeue(xfer->pipe); 2618 } 2619 2620 /* we rely on the bottom bits for extra info */ 2621 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 2622 2623 KASSERT((xfer->rqflags & URQ_REQUEST) != 0); 2624 2625 i = 0; 2626 2627 /* setup phase */ 2628 memcpy(¶meter, req, sizeof(*req)); 2629 parameter = le64toh(parameter); 2630 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 2631 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 2632 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 2633 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 2634 XHCI_TRB_3_IDT_BIT; 2635 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2636 2637 if (len == 0) 2638 goto no_data; 2639 2640 /* data phase */ 2641 parameter = DMAADDR(dma, 0); 2642 KASSERT(len <= 0x10000); 2643 status = XHCI_TRB_2_IRQ_SET(0) | 2644 XHCI_TRB_2_TDSZ_SET(1) | 2645 XHCI_TRB_2_BYTES_SET(len); 2646 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 2647 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 2648 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 2649 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2650 2651 parameter = (uintptr_t)xfer | 0x3; 2652 status = XHCI_TRB_2_IRQ_SET(0); 2653 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 2654 XHCI_TRB_3_IOC_BIT; 2655 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2656 2657 no_data: 2658 parameter = 0; 2659 status = XHCI_TRB_2_IRQ_SET(0); 2660 /* the status stage has inverted direction */ 2661 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 2662 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 2663 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 2664 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2665 2666 parameter = (uintptr_t)xfer | 0x0; 2667 status = XHCI_TRB_2_IRQ_SET(0); 2668 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 2669 XHCI_TRB_3_IOC_BIT; 2670 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2671 2672 mutex_enter(&tr->xr_lock); 2673 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2674 mutex_exit(&tr->xr_lock); 2675 2676 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2677 2678 if (xfer->timeout && !sc->sc_bus.use_polling) { 2679 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2680 xhci_timeout, xfer); 2681 } 2682 2683 if (sc->sc_bus.use_polling) { 2684 DPRINTFN(1, "polling", 0, 0, 0, 0); 2685 //xhci_waitintr(sc, xfer); 2686 } 2687 2688 return USBD_IN_PROGRESS; 2689 } 2690 2691 static void 2692 xhci_device_ctrl_done(usbd_xfer_handle xfer) 2693 { 2694 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2695 2696 callout_stop(&xfer->timeout_handle); /* XXX wrong place */ 2697 2698 } 2699 2700 static void 2701 xhci_device_ctrl_abort(usbd_xfer_handle xfer) 2702 { 2703 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2704 } 2705 2706 static void 2707 xhci_device_ctrl_close(usbd_pipe_handle pipe) 2708 { 2709 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2710 } 2711 2712 /* ----------------- */ 2713 /* device isochronus */ 2714 2715 /* ----------- */ 2716 /* device bulk */ 2717 2718 static usbd_status 2719 xhci_device_bulk_transfer(usbd_xfer_handle xfer) 2720 { 2721 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2722 usbd_status err; 2723 2724 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2725 2726 /* Insert last in queue. */ 2727 mutex_enter(&sc->sc_lock); 2728 err = usb_insert_transfer(xfer); 2729 mutex_exit(&sc->sc_lock); 2730 if (err) 2731 return err; 2732 2733 /* 2734 * Pipe isn't running (otherwise err would be USBD_INPROG), 2735 * so start it first. 2736 */ 2737 return (xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2738 } 2739 2740 static usbd_status 2741 xhci_device_bulk_start(usbd_xfer_handle xfer) 2742 { 2743 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2744 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2745 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2746 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2747 struct xhci_xfer * const xx = (void *)xfer; 2748 const uint32_t len = xfer->length; 2749 usb_dma_t * const dma = &xfer->dmabuf; 2750 uint64_t parameter; 2751 uint32_t status; 2752 uint32_t control; 2753 u_int i = 0; 2754 2755 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2756 2757 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 2758 2759 if (sc->sc_dying) 2760 return USBD_IOERROR; 2761 2762 KASSERT((xfer->rqflags & URQ_REQUEST) == 0); 2763 2764 parameter = DMAADDR(dma, 0); 2765 /* 2766 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 2767 * If the user supplied buffer crosses such a boundary then 2 2768 * (or more) TRB should be used. 2769 * If multiple TRB are used the td_size field must be set correctly. 2770 * For v1.0 devices (like ivy bridge) this is the number of usb data 2771 * blocks needed to complete the transfer. 2772 * Setting it to 1 in the last TRB causes an extra zero-length 2773 * data block be sent. 2774 * The earlier documentation differs, I don't know how it behaves. 2775 */ 2776 KASSERT(len <= 0x10000); 2777 status = XHCI_TRB_2_IRQ_SET(0) | 2778 XHCI_TRB_2_TDSZ_SET(1) | 2779 XHCI_TRB_2_BYTES_SET(len); 2780 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 2781 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 2782 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2783 2784 mutex_enter(&tr->xr_lock); 2785 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2786 mutex_exit(&tr->xr_lock); 2787 2788 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2789 2790 if (sc->sc_bus.use_polling) { 2791 DPRINTFN(1, "polling", 0, 0, 0, 0); 2792 //xhci_waitintr(sc, xfer); 2793 } 2794 2795 return USBD_IN_PROGRESS; 2796 } 2797 2798 static void 2799 xhci_device_bulk_done(usbd_xfer_handle xfer) 2800 { 2801 #ifdef USB_DEBUG 2802 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2803 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2804 #endif 2805 const u_int endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 2806 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2807 2808 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2809 2810 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 2811 2812 callout_stop(&xfer->timeout_handle); /* XXX wrong place */ 2813 2814 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 2815 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2816 2817 2818 } 2819 2820 static void 2821 xhci_device_bulk_abort(usbd_xfer_handle xfer) 2822 { 2823 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2824 } 2825 2826 static void 2827 xhci_device_bulk_close(usbd_pipe_handle pipe) 2828 { 2829 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2830 } 2831 2832 /* --------------- */ 2833 /* device intrrupt */ 2834 2835 static usbd_status 2836 xhci_device_intr_transfer(usbd_xfer_handle xfer) 2837 { 2838 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2839 usbd_status err; 2840 2841 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2842 2843 /* Insert last in queue. */ 2844 mutex_enter(&sc->sc_lock); 2845 err = usb_insert_transfer(xfer); 2846 mutex_exit(&sc->sc_lock); 2847 if (err) 2848 return err; 2849 2850 /* 2851 * Pipe isn't running (otherwise err would be USBD_INPROG), 2852 * so start it first. 2853 */ 2854 return (xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2855 } 2856 2857 static usbd_status 2858 xhci_device_intr_start(usbd_xfer_handle xfer) 2859 { 2860 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2861 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2862 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2863 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2864 struct xhci_xfer * const xx = (void *)xfer; 2865 const uint32_t len = xfer->length; 2866 usb_dma_t * const dma = &xfer->dmabuf; 2867 uint64_t parameter; 2868 uint32_t status; 2869 uint32_t control; 2870 u_int i = 0; 2871 2872 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2873 2874 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 2875 2876 if (sc->sc_dying) 2877 return USBD_IOERROR; 2878 2879 KASSERT((xfer->rqflags & URQ_REQUEST) == 0); 2880 2881 parameter = DMAADDR(dma, 0); 2882 KASSERT(len <= 0x10000); 2883 status = XHCI_TRB_2_IRQ_SET(0) | 2884 XHCI_TRB_2_TDSZ_SET(1) | 2885 XHCI_TRB_2_BYTES_SET(len); 2886 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 2887 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 2888 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2889 2890 mutex_enter(&tr->xr_lock); 2891 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2892 mutex_exit(&tr->xr_lock); 2893 2894 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2895 2896 if (sc->sc_bus.use_polling) { 2897 DPRINTFN(1, "polling", 0, 0, 0, 0); 2898 //xhci_waitintr(sc, xfer); 2899 } 2900 2901 return USBD_IN_PROGRESS; 2902 } 2903 2904 static void 2905 xhci_device_intr_done(usbd_xfer_handle xfer) 2906 { 2907 struct xhci_softc * const sc __diagused = 2908 xfer->pipe->device->bus->hci_private; 2909 #ifdef USB_DEBUG 2910 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2911 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2912 #endif 2913 const u_int endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 2914 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2915 2916 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2917 2918 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 2919 2920 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 2921 2922 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 2923 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2924 2925 #if 0 2926 device_printf(sc->sc_dev, ""); 2927 for (size_t i = 0; i < xfer->length; i++) { 2928 printf(" %02x", ((uint8_t const *)xfer->buffer)[i]); 2929 } 2930 printf("\n"); 2931 #endif 2932 2933 if (xfer->pipe->repeat) { 2934 xfer->status = xhci_device_intr_start(xfer); 2935 } else { 2936 callout_stop(&xfer->timeout_handle); /* XXX */ 2937 } 2938 2939 } 2940 2941 static void 2942 xhci_device_intr_abort(usbd_xfer_handle xfer) 2943 { 2944 struct xhci_softc * const sc __diagused = 2945 xfer->pipe->device->bus->hci_private; 2946 2947 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2948 2949 KASSERT(mutex_owned(&sc->sc_lock)); 2950 DPRINTFN(15, "%p", xfer, 0, 0, 0); 2951 KASSERT(xfer->pipe->intrxfer == xfer); 2952 xfer->status = USBD_CANCELLED; 2953 usb_transfer_complete(xfer); 2954 } 2955 2956 static void 2957 xhci_device_intr_close(usbd_pipe_handle pipe) 2958 { 2959 //struct xhci_softc * const sc = pipe->device->bus->hci_private; 2960 2961 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2962 DPRINTFN(15, "%p", pipe, 0, 0, 0); 2963 2964 xhci_unconfigure_endpoint(pipe); 2965 } 2966 2967 /* ------------ */ 2968 2969 static void 2970 xhci_timeout(void *addr) 2971 { 2972 struct xhci_xfer * const xx = addr; 2973 usbd_xfer_handle const xfer = &xx->xx_xfer; 2974 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2975 2976 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2977 2978 if (sc->sc_dying) { 2979 return; 2980 } 2981 2982 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 2983 USB_TASKQ_MPSAFE); 2984 usb_add_task(xx->xx_xfer.pipe->device, &xx->xx_abort_task, 2985 USB_TASKQ_HC); 2986 } 2987 2988 static void 2989 xhci_timeout_task(void *addr) 2990 { 2991 usbd_xfer_handle const xfer = addr; 2992 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2993 2994 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2995 2996 mutex_enter(&sc->sc_lock); 2997 #if 0 2998 xhci_abort_xfer(xfer, USBD_TIMEOUT); 2999 #else 3000 xfer->status = USBD_TIMEOUT; 3001 usb_transfer_complete(xfer); 3002 #endif 3003 mutex_exit(&sc->sc_lock); 3004 } 3005
Indexes created Wed Oct 01 18:09:54 GMT 2025