xhci.c revision 1.28.2.30
1 /* $NetBSD: xhci.c,v 1.28.2.30 2015/06/25 06:30:13 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 3.1 specification 31 * http://www.usb.org/developers/docs/usb_31_040315.zip 32 * USB rev 2.0 specification 33 * http://www.usb.org/developers/docs/usb20_docs/usb_20_031815.zip 34 * xHCI rev 1.1 specification 35 * http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.28.2.30 2015/06/25 06:30:13 skrll Exp $"); 40 41 #include "opt_usb.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static int xhci_intr1(struct xhci_softc * const); 129 static void xhci_softintr(void *); 130 static void xhci_poll(struct usbd_bus *); 131 static struct usbd_xfer *xhci_allocx(struct usbd_bus *); 132 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 133 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 134 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 135 struct usbd_port *); 136 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 137 void *, int); 138 139 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 140 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 141 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 143 144 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 145 146 static usbd_status xhci_do_command(struct xhci_softc * const, 147 struct xhci_trb * const, int); 148 static usbd_status xhci_do_command1(struct xhci_softc * const, 149 struct xhci_trb * const, int, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t, int, int); 153 static usbd_status xhci_enable_slot(struct xhci_softc * const, 154 uint8_t * const); 155 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 156 static usbd_status xhci_address_device(struct xhci_softc * const, 157 uint64_t, uint8_t, bool); 158 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 159 struct xhci_slot * const, u_int); 160 static usbd_status xhci_ring_init(struct xhci_softc * const, 161 struct xhci_ring * const, size_t, size_t); 162 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 163 164 static void xhci_noop(struct usbd_pipe *); 165 166 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 167 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 168 static void xhci_root_intr_abort(struct usbd_xfer *); 169 static void xhci_root_intr_close(struct usbd_pipe *); 170 static void xhci_root_intr_done(struct usbd_xfer *); 171 172 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 173 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 174 static void xhci_device_ctrl_abort(struct usbd_xfer *); 175 static void xhci_device_ctrl_close(struct usbd_pipe *); 176 static void xhci_device_ctrl_done(struct usbd_xfer *); 177 178 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 179 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 180 static void xhci_device_intr_abort(struct usbd_xfer *); 181 static void xhci_device_intr_close(struct usbd_pipe *); 182 static void xhci_device_intr_done(struct usbd_xfer *); 183 184 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 185 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 186 static void xhci_device_bulk_abort(struct usbd_xfer *); 187 static void xhci_device_bulk_close(struct usbd_pipe *); 188 static void xhci_device_bulk_done(struct usbd_xfer *); 189 190 static void xhci_timeout(void *); 191 static void xhci_timeout_task(void *); 192 193 static const struct usbd_bus_methods xhci_bus_methods = { 194 .ubm_open = xhci_open, 195 .ubm_softint = xhci_softintr, 196 .ubm_dopoll = xhci_poll, 197 .ubm_allocx = xhci_allocx, 198 .ubm_freex = xhci_freex, 199 .ubm_getlock = xhci_get_lock, 200 .ubm_newdev = xhci_new_device, 201 .ubm_rhctrl = xhci_roothub_ctrl, 202 }; 203 204 static const struct usbd_pipe_methods xhci_root_intr_methods = { 205 .upm_transfer = xhci_root_intr_transfer, 206 .upm_start = xhci_root_intr_start, 207 .upm_abort = xhci_root_intr_abort, 208 .upm_close = xhci_root_intr_close, 209 .upm_cleartoggle = xhci_noop, 210 .upm_done = xhci_root_intr_done, 211 }; 212 213 214 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 215 .upm_transfer = xhci_device_ctrl_transfer, 216 .upm_start = xhci_device_ctrl_start, 217 .upm_abort = xhci_device_ctrl_abort, 218 .upm_close = xhci_device_ctrl_close, 219 .upm_cleartoggle = xhci_noop, 220 .upm_done = xhci_device_ctrl_done, 221 }; 222 223 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 224 .upm_cleartoggle = xhci_noop, 225 }; 226 227 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 228 .upm_transfer = xhci_device_bulk_transfer, 229 .upm_start = xhci_device_bulk_start, 230 .upm_abort = xhci_device_bulk_abort, 231 .upm_close = xhci_device_bulk_close, 232 .upm_cleartoggle = xhci_noop, 233 .upm_done = xhci_device_bulk_done, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_intr_methods = { 237 .upm_transfer = xhci_device_intr_transfer, 238 .upm_start = xhci_device_intr_start, 239 .upm_abort = xhci_device_intr_abort, 240 .upm_close = xhci_device_intr_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_intr_done, 243 }; 244 245 static inline uint32_t 246 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 247 { 248 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 249 } 250 251 static inline uint32_t 252 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 253 { 254 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 255 } 256 257 static inline void 258 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 259 uint32_t value) 260 { 261 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 262 } 263 264 #if 0 /* unused */ 265 static inline void 266 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 267 uint32_t value) 268 { 269 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 270 } 271 #endif /* unused */ 272 273 static inline uint32_t 274 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 275 { 276 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 277 } 278 279 static inline uint32_t 280 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 281 { 282 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 283 } 284 285 static inline void 286 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 287 uint32_t value) 288 { 289 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 290 } 291 292 #if 0 /* unused */ 293 static inline uint64_t 294 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 295 { 296 uint64_t value; 297 298 if (sc->sc_ac64) { 299 #ifdef XHCI_USE_BUS_SPACE_8 300 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 301 #else 302 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 303 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 304 offset + 4) << 32; 305 #endif 306 } else { 307 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 308 } 309 310 return value; 311 } 312 #endif /* unused */ 313 314 static inline void 315 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 316 uint64_t value) 317 { 318 if (sc->sc_ac64) { 319 #ifdef XHCI_USE_BUS_SPACE_8 320 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 321 #else 322 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 323 (value >> 0) & 0xffffffff); 324 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 325 (value >> 32) & 0xffffffff); 326 #endif 327 } else { 328 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 329 } 330 } 331 332 static inline uint32_t 333 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 334 { 335 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 336 } 337 338 static inline void 339 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 340 uint32_t value) 341 { 342 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 343 } 344 345 #if 0 /* unused */ 346 static inline uint64_t 347 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 348 { 349 uint64_t value; 350 351 if (sc->sc_ac64) { 352 #ifdef XHCI_USE_BUS_SPACE_8 353 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 354 #else 355 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 356 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 357 offset + 4) << 32; 358 #endif 359 } else { 360 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 361 } 362 363 return value; 364 } 365 #endif /* unused */ 366 367 static inline void 368 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 369 uint64_t value) 370 { 371 if (sc->sc_ac64) { 372 #ifdef XHCI_USE_BUS_SPACE_8 373 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 374 #else 375 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 376 (value >> 0) & 0xffffffff); 377 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 378 (value >> 32) & 0xffffffff); 379 #endif 380 } else { 381 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 382 } 383 } 384 385 #if 0 /* unused */ 386 static inline uint32_t 387 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 388 { 389 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 390 } 391 #endif /* unused */ 392 393 static inline void 394 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 395 uint32_t value) 396 { 397 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 398 } 399 400 /* --- */ 401 402 static inline uint8_t 403 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 404 { 405 u_int eptype = 0; 406 407 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 408 case UE_CONTROL: 409 eptype = 0x0; 410 break; 411 case UE_ISOCHRONOUS: 412 eptype = 0x1; 413 break; 414 case UE_BULK: 415 eptype = 0x2; 416 break; 417 case UE_INTERRUPT: 418 eptype = 0x3; 419 break; 420 } 421 422 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 423 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 424 return eptype | 0x4; 425 else 426 return eptype; 427 } 428 429 static u_int 430 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 431 { 432 /* xHCI 1.0 section 4.5.1 */ 433 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 434 u_int in = 0; 435 436 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 437 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 438 in = 1; 439 440 return epaddr * 2 + in; 441 } 442 443 static inline u_int 444 xhci_dci_to_ici(const u_int i) 445 { 446 return i + 1; 447 } 448 449 static inline void * 450 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 451 const u_int dci) 452 { 453 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 454 } 455 456 #if 0 /* unused */ 457 static inline bus_addr_t 458 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 459 const u_int dci) 460 { 461 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 462 } 463 #endif /* unused */ 464 465 static inline void * 466 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 467 const u_int ici) 468 { 469 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 470 } 471 472 static inline bus_addr_t 473 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline struct xhci_trb * 480 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 481 { 482 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 483 } 484 485 static inline bus_addr_t 486 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 487 { 488 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 489 } 490 491 static inline void 492 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 493 uint32_t control) 494 { 495 trb->trb_0 = parameter; 496 trb->trb_2 = status; 497 trb->trb_3 = control; 498 } 499 500 /* --- */ 501 502 void 503 xhci_childdet(device_t self, device_t child) 504 { 505 struct xhci_softc * const sc = device_private(self); 506 507 KASSERT(sc->sc_child == child); 508 if (child == sc->sc_child) 509 sc->sc_child = NULL; 510 } 511 512 int 513 xhci_detach(struct xhci_softc *sc, int flags) 514 { 515 int rv = 0; 516 517 if (sc->sc_child != NULL) 518 rv = config_detach(sc->sc_child, flags); 519 520 if (rv != 0) 521 return rv; 522 523 /* XXX unconfigure/free slots */ 524 525 /* verify: */ 526 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 527 xhci_op_write_4(sc, XHCI_USBCMD, 0); 528 /* do we need to wait for stop? */ 529 530 xhci_op_write_8(sc, XHCI_CRCR, 0); 531 xhci_ring_free(sc, &sc->sc_cr); 532 cv_destroy(&sc->sc_command_cv); 533 534 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 535 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 536 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 537 xhci_ring_free(sc, &sc->sc_er); 538 539 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 540 541 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 542 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 543 544 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 545 546 mutex_destroy(&sc->sc_lock); 547 mutex_destroy(&sc->sc_intr_lock); 548 cv_destroy(&sc->sc_softwake_cv); 549 550 pool_cache_destroy(sc->sc_xferpool); 551 552 return rv; 553 } 554 555 int 556 xhci_activate(device_t self, enum devact act) 557 { 558 struct xhci_softc * const sc = device_private(self); 559 560 switch (act) { 561 case DVACT_DEACTIVATE: 562 sc->sc_dying = true; 563 return 0; 564 default: 565 return EOPNOTSUPP; 566 } 567 } 568 569 bool 570 xhci_suspend(device_t dv, const pmf_qual_t *qual) 571 { 572 return false; 573 } 574 575 bool 576 xhci_resume(device_t dv, const pmf_qual_t *qual) 577 { 578 return false; 579 } 580 581 bool 582 xhci_shutdown(device_t self, int flags) 583 { 584 return false; 585 } 586 587 588 static void 589 hexdump(const char *msg, const void *base, size_t len) 590 { 591 #if 0 592 size_t cnt; 593 const uint32_t *p; 594 extern paddr_t vtophys(vaddr_t); 595 596 p = base; 597 cnt = 0; 598 599 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 600 (void *)vtophys((vaddr_t)base)); 601 602 while (cnt < len) { 603 if (cnt % 16 == 0) 604 printf("%p: ", p); 605 else if (cnt % 8 == 0) 606 printf(" |"); 607 printf(" %08x", *p++); 608 cnt += 4; 609 if (cnt % 16 == 0) 610 printf("\n"); 611 } 612 #endif 613 } 614 615 616 int 617 xhci_init(struct xhci_softc *sc) 618 { 619 bus_size_t bsz; 620 uint32_t cap, hcs1, hcs2, hcc, dboff, rtsoff; 621 uint32_t ecp, ecr; 622 uint32_t usbcmd, usbsts, pagesize, config; 623 int i; 624 uint16_t hciversion; 625 uint8_t caplength; 626 627 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 628 629 /* XXX Low/Full/High speeds for now */ 630 sc->sc_bus.ub_revision = USBREV_2_0; 631 sc->sc_bus.ub_usedma = true; 632 633 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 634 caplength = XHCI_CAP_CAPLENGTH(cap); 635 hciversion = XHCI_CAP_HCIVERSION(cap); 636 637 if ((hciversion < 0x0096) || (hciversion > 0x0100)) { 638 aprint_normal_dev(sc->sc_dev, 639 "xHCI version %x.%x not known to be supported\n", 640 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 641 } else { 642 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 643 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 644 } 645 646 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 647 &sc->sc_cbh) != 0) { 648 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 649 return ENOMEM; 650 } 651 652 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 653 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 654 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 655 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 656 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 657 (void)xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 658 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 659 660 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 661 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 662 aprint_debug_dev(sc->sc_dev, "ac64 %d ctxsz %d\n", sc->sc_ac64, 663 sc->sc_ctxsz); 664 665 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 666 ecp = XHCI_HCC_XECP(hcc) * 4; 667 while (ecp != 0) { 668 ecr = xhci_read_4(sc, ecp); 669 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 670 switch (XHCI_XECP_ID(ecr)) { 671 case XHCI_ID_PROTOCOLS: { 672 uint32_t w0, w4, w8; 673 uint16_t w2; 674 w0 = xhci_read_4(sc, ecp + 0); 675 w2 = (w0 >> 16) & 0xffff; 676 w4 = xhci_read_4(sc, ecp + 4); 677 w8 = xhci_read_4(sc, ecp + 8); 678 aprint_debug_dev(sc->sc_dev, "SP: %08x %08x %08x\n", 679 w0, w4, w8); 680 if (w4 == 0x20425355 && w2 == 0x0300) { 681 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 682 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 683 } 684 if (w4 == 0x20425355 && w2 == 0x0200) { 685 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 686 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 687 } 688 break; 689 } 690 case XHCI_ID_USB_LEGACY: { 691 uint8_t bios_sem; 692 693 /* Take host controller from BIOS */ 694 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 695 if (bios_sem) { 696 /* sets xHCI to be owned by OS */ 697 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 698 aprint_debug( 699 "waiting for BIOS to give up control\n"); 700 for (i = 0; i < 5000; i++) { 701 bios_sem = xhci_read_1(sc, ecp + 702 XHCI_XECP_BIOS_SEM); 703 if (bios_sem == 0) 704 break; 705 DELAY(1000); 706 } 707 if (bios_sem) 708 printf("timed out waiting for BIOS\n"); 709 } 710 break; 711 } 712 default: 713 break; 714 } 715 ecr = xhci_read_4(sc, ecp); 716 if (XHCI_XECP_NEXT(ecr) == 0) { 717 ecp = 0; 718 } else { 719 ecp += XHCI_XECP_NEXT(ecr) * 4; 720 } 721 } 722 723 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 724 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 725 &sc->sc_obh) != 0) { 726 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 727 return ENOMEM; 728 } 729 730 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 731 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 732 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 733 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 734 return ENOMEM; 735 } 736 737 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 738 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 739 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 740 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 741 return ENOMEM; 742 } 743 744 for (i = 0; i < 100; i++) { 745 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 746 if ((usbsts & XHCI_STS_CNR) == 0) 747 break; 748 usb_delay_ms(&sc->sc_bus, 1); 749 } 750 if (i >= 100) 751 return EIO; 752 753 usbcmd = 0; 754 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 755 usb_delay_ms(&sc->sc_bus, 1); 756 757 usbcmd = XHCI_CMD_HCRST; 758 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 759 for (i = 0; i < 100; i++) { 760 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 761 if ((usbcmd & XHCI_CMD_HCRST) == 0) 762 break; 763 usb_delay_ms(&sc->sc_bus, 1); 764 } 765 if (i >= 100) 766 return EIO; 767 768 for (i = 0; i < 100; i++) { 769 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 770 if ((usbsts & XHCI_STS_CNR) == 0) 771 break; 772 usb_delay_ms(&sc->sc_bus, 1); 773 } 774 if (i >= 100) 775 return EIO; 776 777 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 778 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 779 pagesize = ffs(pagesize); 780 if (pagesize == 0) 781 return EIO; 782 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 783 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 784 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 785 (uint32_t)sc->sc_maxslots); 786 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 787 788 usbd_status err; 789 790 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 791 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 792 if (sc->sc_maxspbuf != 0) { 793 err = usb_allocmem(&sc->sc_bus, 794 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 795 &sc->sc_spbufarray_dma); 796 if (err) 797 return err; 798 799 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * sc->sc_maxspbuf, KM_SLEEP); 800 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 801 for (i = 0; i < sc->sc_maxspbuf; i++) { 802 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 803 /* allocate contexts */ 804 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 805 sc->sc_pgsz, dma); 806 if (err) 807 return err; 808 spbufarray[i] = htole64(DMAADDR(dma, 0)); 809 usb_syncmem(dma, 0, sc->sc_pgsz, 810 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 811 } 812 813 usb_syncmem(&sc->sc_spbufarray_dma, 0, 814 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 815 } 816 817 config = xhci_op_read_4(sc, XHCI_CONFIG); 818 config &= ~0xFF; 819 config |= sc->sc_maxslots & 0xFF; 820 xhci_op_write_4(sc, XHCI_CONFIG, config); 821 822 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 823 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 824 if (err) { 825 aprint_error_dev(sc->sc_dev, "command ring init fail\n"); 826 return err; 827 } 828 829 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 830 XHCI_EVENT_RING_SEGMENTS_ALIGN); 831 if (err) { 832 aprint_error_dev(sc->sc_dev, "event ring init fail\n"); 833 return err; 834 } 835 836 usb_dma_t *dma; 837 size_t size; 838 size_t align; 839 840 dma = &sc->sc_eventst_dma; 841 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 842 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 843 KASSERT(size <= (512 * 1024)); 844 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 845 err = usb_allocmem(&sc->sc_bus, size, align, dma); 846 847 memset(KERNADDR(dma, 0), 0, size); 848 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 849 aprint_debug_dev(sc->sc_dev, "eventst: %s %016jx %p %zx\n", 850 usbd_errstr(err), 851 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 852 KERNADDR(&sc->sc_eventst_dma, 0), 853 sc->sc_eventst_dma.udma_block->size); 854 855 dma = &sc->sc_dcbaa_dma; 856 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 857 KASSERT(size <= 2048); 858 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 859 err = usb_allocmem(&sc->sc_bus, size, align, dma); 860 861 memset(KERNADDR(dma, 0), 0, size); 862 if (sc->sc_maxspbuf != 0) { 863 /* 864 * DCBA entry 0 hold the scratchbuf array pointer. 865 */ 866 *(uint64_t *)KERNADDR(dma, 0) = 867 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 868 } 869 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 870 aprint_debug_dev(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n", 871 usbd_errstr(err), 872 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 873 KERNADDR(&sc->sc_dcbaa_dma, 0), 874 sc->sc_dcbaa_dma.udma_block->size); 875 876 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 877 KM_SLEEP); 878 879 cv_init(&sc->sc_command_cv, "xhcicmd"); 880 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 881 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 882 cv_init(&sc->sc_softwake_cv, "xhciab"); 883 884 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 885 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 886 887 /* Set up the bus struct. */ 888 sc->sc_bus.ub_methods = &xhci_bus_methods; 889 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 890 891 struct xhci_erste *erst; 892 erst = KERNADDR(&sc->sc_eventst_dma, 0); 893 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 894 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 895 erst[0].erste_3 = htole32(0); 896 usb_syncmem(&sc->sc_eventst_dma, 0, 897 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 898 899 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 900 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 901 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 902 XHCI_ERDP_LO_BUSY); 903 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 904 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 905 sc->sc_cr.xr_cs); 906 907 #if 0 908 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 909 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 910 #endif 911 912 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 913 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 914 /* Intel xhci needs interrupt rate moderated. */ 915 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 916 else 917 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 918 aprint_debug_dev(sc->sc_dev, "setting IMOD %u\n", 919 xhci_rt_read_4(sc, XHCI_IMOD(0))); 920 921 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 922 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 923 xhci_op_read_4(sc, XHCI_USBCMD)); 924 925 return USBD_NORMAL_COMPLETION; 926 } 927 928 int 929 xhci_intr(void *v) 930 { 931 struct xhci_softc * const sc = v; 932 int ret = 0; 933 934 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 935 936 if (sc == NULL) 937 return 0; 938 939 mutex_spin_enter(&sc->sc_intr_lock); 940 941 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 942 goto done; 943 944 /* If we get an interrupt while polling, then just ignore it. */ 945 if (sc->sc_bus.ub_usepolling) { 946 #ifdef DIAGNOSTIC 947 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 948 #endif 949 goto done; 950 } 951 952 ret = xhci_intr1(sc); 953 done: 954 mutex_spin_exit(&sc->sc_intr_lock); 955 return ret; 956 } 957 958 int 959 xhci_intr1(struct xhci_softc * const sc) 960 { 961 uint32_t usbsts; 962 uint32_t iman; 963 964 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 965 966 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 967 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 968 #if 0 969 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 970 return 0; 971 } 972 #endif 973 xhci_op_write_4(sc, XHCI_USBSTS, 974 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 975 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 976 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 977 978 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 979 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 980 981 if (!(sc->sc_quirks & XHCI_QUIRK_FORCE_INTR)) { 982 if ((iman & XHCI_IMAN_INTR_PEND) == 0) { 983 return 0; 984 } 985 } 986 987 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 988 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 989 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 990 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 991 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 992 993 usb_schedsoftintr(&sc->sc_bus); 994 995 return 1; 996 } 997 998 /* 999 * 3 port speed types used in USB stack 1000 * 1001 * usbdi speed 1002 * definition: USB_SPEED_* in usb.h 1003 * They are used in struct usbd_device in USB stack. 1004 * ioctl interface uses these values too. 1005 * port_status speed 1006 * definition: UPS_*_SPEED in usb.h 1007 * They are used in usb_port_status_t and valid only for USB 2.0. 1008 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1009 * of usb_port_status_ext_t indicates port speed. 1010 * Note that some 3.0 values overlap with 2.0 values. 1011 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1012 * means UPS_LOW_SPEED in HS.) 1013 * port status returned from hub also uses these values. 1014 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1015 * or more. 1016 * xspeed: 1017 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1018 * They are used in only slot context and PORTSC reg of xhci. 1019 * The difference between usbdi speed and xspeed is 1020 * that FS and LS values are swapped. 1021 */ 1022 1023 /* convert usbdi speed to xspeed */ 1024 static int 1025 xhci_speed2xspeed(int speed) 1026 { 1027 switch (speed) { 1028 case USB_SPEED_LOW: return 2; 1029 case USB_SPEED_FULL: return 1; 1030 default: return speed; 1031 } 1032 } 1033 1034 /* convert xspeed to usbdi speed */ 1035 static int 1036 xhci_xspeed2speed(int xspeed) 1037 { 1038 switch (xspeed) { 1039 case 1: return USB_SPEED_FULL; 1040 case 2: return USB_SPEED_LOW; 1041 default: return xspeed; 1042 } 1043 } 1044 1045 /* convert xspeed to port status speed */ 1046 static int 1047 xhci_xspeed2psspeed(int xspeed) 1048 { 1049 switch (xspeed) { 1050 case 0: return 0; 1051 case 1: return UPS_FULL_SPEED; 1052 case 2: return UPS_LOW_SPEED; 1053 case 3: return UPS_HIGH_SPEED; 1054 default: return UPS_OTHER_SPEED; 1055 } 1056 } 1057 1058 /* construct slot context */ 1059 static void 1060 xhci_setup_sctx(struct usbd_device *dev, uint32_t *cp) 1061 { 1062 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 1063 int speed = dev->ud_speed; 1064 int tthubslot, ttportnum; 1065 bool ishub; 1066 bool usemtt; 1067 1068 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1069 1070 /* 6.2.2 */ 1071 /* 1072 * tthubslot: 1073 * This is the slot ID of parent HS hub 1074 * if LS/FS device is connected && connected through HS hub. 1075 * This is 0 if device is not LS/FS device || 1076 * parent hub is not HS hub || 1077 * attached to root hub. 1078 * ttportnum: 1079 * This is the downstream facing port of parent HS hub 1080 * if LS/FS device is connected. 1081 * This is 0 if device is not LS/FS device || 1082 * parent hub is not HS hub || 1083 * attached to root hub. 1084 */ 1085 if (dev->ud_myhsport != NULL && 1086 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1087 (dev->ud_myhub != NULL && 1088 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1089 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 1090 ttportnum = dev->ud_myhsport->up_portno; 1091 /* XXX addr == slot ? */ 1092 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 1093 } else { 1094 ttportnum = 0; 1095 tthubslot = 0; 1096 } 1097 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 1098 dev->ud_myhsport, ttportnum, tthubslot, 0); 1099 1100 /* ishub is valid after reading UDESC_DEVICE */ 1101 ishub = (dd->bDeviceClass == UDCLASS_HUB); 1102 1103 /* dev->ud_hub is valid after reading UDESC_HUB */ 1104 if (ishub && dev->ud_hub) { 1105 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 1106 1107 cp[1] |= htole32(XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts)); 1108 cp[2] |= htole32(XHCI_SCTX_2_TT_THINK_TIME_SET( 1109 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK))); 1110 DPRINTFN(4, "nports=%d ttt=%d", 1111 hd->bNbrPorts, XHCI_SCTX_2_TT_THINK_TIME_GET(cp[2]), 0, 0); 1112 } 1113 1114 #define IS_TTHUB(dd) \ 1115 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 1116 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 1117 1118 /* 1119 * MTT flag is set if 1120 * 1. this is HS hub && MTT is enabled 1121 * or 1122 * 2. this is not hub && this is LS or FS device && 1123 * MTT of parent HS hub (and its parent, too) is enabled 1124 */ 1125 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 1126 usemtt = true; 1127 else if (!ishub && 1128 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 1129 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1130 (dev->ud_myhub != NULL && 1131 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1132 dev->ud_myhsport != NULL && 1133 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 1134 usemtt = true; 1135 else 1136 usemtt = false; 1137 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 1138 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 1139 1140 cp[0] |= htole32( 1141 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)) | 1142 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 1143 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0) 1144 ); 1145 cp[1] |= htole32(0); 1146 cp[2] |= htole32( 1147 XHCI_SCTX_2_IRQ_TARGET_SET(0) | 1148 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 1149 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum) 1150 ); 1151 cp[3] |= htole32(0); 1152 } 1153 1154 /* 1155 * called 1156 * from xhci_open 1157 * from usbd_setup_pipe_flags 1158 * from usbd_open_pipe_ival 1159 */ 1160 static usbd_status 1161 xhci_configure_endpoint(struct usbd_pipe *pipe) 1162 { 1163 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1164 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1165 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1166 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1167 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1168 struct xhci_trb trb; 1169 usbd_status err; 1170 uint32_t *cp; 1171 uint32_t mps = UGETW(ed->wMaxPacketSize); 1172 uint32_t maxb = 0; 1173 int speed = pipe->up_dev->ud_speed; 1174 uint32_t ival = ed->bInterval; 1175 1176 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1177 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1178 xs->xs_idx, dci, ed->bEndpointAddress, ed->bmAttributes); 1179 1180 /* XXX ensure input context is available? */ 1181 1182 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1183 1184 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1185 cp[0] = htole32(0); 1186 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 1187 1188 /* set up input slot context */ 1189 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1190 xhci_setup_sctx(pipe->up_dev, cp); 1191 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1192 1193 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 1194 cp[0] = htole32( 1195 XHCI_EPCTX_0_EPSTATE_SET(0) | 1196 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 1197 XHCI_EPCTX_0_LSA_SET(0) 1198 ); 1199 cp[1] = htole32( 1200 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 1201 XHCI_EPCTX_1_MAXB_SET(0) 1202 ); 1203 if (xfertype != UE_ISOCHRONOUS) 1204 cp[1] |= htole32(XHCI_EPCTX_1_CERR_SET(3)); 1205 1206 if (USB_IS_SS(speed)) { 1207 usbd_desc_iter_t iter; 1208 const usb_cdc_descriptor_t *cdcd; 1209 const usb_endpoint_ss_comp_descriptor_t * esscd = NULL; 1210 uint8_t ep; 1211 1212 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc( 1213 pipe->up_dev, UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 1214 usb_desc_iter_init(pipe->up_dev, &iter); 1215 iter.cur = (const void *)cdcd; 1216 1217 /* find endpoint_ss_comp desc for ep of this pipe */ 1218 for(ep = 0;;) { 1219 cdcd = (const usb_cdc_descriptor_t *) 1220 usb_desc_iter_next(&iter); 1221 if (cdcd == NULL) 1222 break; 1223 if (ep == 0 && 1224 cdcd->bDescriptorType == UDESC_ENDPOINT) { 1225 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 1226 bEndpointAddress; 1227 if (UE_GET_ADDR(ep) == 1228 UE_GET_ADDR(ed->bEndpointAddress)) { 1229 cdcd = (const usb_cdc_descriptor_t *) 1230 usb_desc_iter_next(&iter); 1231 break; 1232 } 1233 ep = 0; 1234 } 1235 } 1236 if (cdcd != NULL && 1237 cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 1238 esscd = (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 1239 maxb = esscd->bMaxBurst; 1240 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1241 DPRINTFN(4, "setting SS MaxBurst %u", maxb, 0, 0, 0); 1242 } 1243 } 1244 if (speed == USB_SPEED_HIGH && 1245 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 1246 maxb = UE_GET_TRANS(UGETW(ed->wMaxPacketSize)); 1247 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1248 DPRINTFN(4, "setting HS MaxBurst %u", maxb, 0, 0, 0); 1249 } 1250 1251 switch (xfertype) { 1252 case UE_INTERRUPT: 1253 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1254 ival = pipe->up_interval; 1255 1256 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 1257 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 1258 int i; 1259 1260 /* 1261 * round ival down to "the nearest base 2 multiple of 1262 * bInterval * 8". 1263 * bInterval is at most 255 as its type is uByte. 1264 * 255(ms) = 2040(x 125us) < 2^11, so start with 11. 1265 */ 1266 for (i = 11; i > 0; i--) { 1267 if ((ival * 8) >= (1 << i)) 1268 break; 1269 } 1270 ival = i; 1271 } else { 1272 /* Interval = bInterval-1 for SS/HS */ 1273 ival--; 1274 } 1275 DPRINTFN(4, "ival %u", ival, 0, 0, 0); 1276 1277 if (USB_IS_SS(speed)) { 1278 if (maxb > 0) 1279 mps = 1024; 1280 } else { 1281 mps = mps ? mps : 8; 1282 } 1283 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1284 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1285 cp[4] = htole32( 1286 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) /* XXX */ 1287 ); 1288 break; 1289 case UE_CONTROL: 1290 if (USB_IS_SS(speed)) 1291 mps = 512; 1292 else 1293 mps = mps ? mps : 8; 1294 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1295 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(8)); /* XXX */ 1296 break; 1297 #ifdef notyet 1298 case UE_ISOCHRONOUS: 1299 if (speed == USB_SPEED_FULL) 1300 ival += 3; /* 1ms -> 125us */ 1301 ival--; 1302 DPRINTFN(4, "ival %u", ival, 0, 0, 0); 1303 1304 if (USB_IS_SS(speed)) { 1305 mps = 1024; 1306 } else { 1307 mps = mps ? mps : 1024; 1308 } 1309 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1310 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(1024)); /* XXX */ 1311 break; 1312 #endif 1313 default: 1314 if (USB_IS_SS(speed)) 1315 mps = 1024; 1316 else 1317 mps = mps ? mps : 512; 1318 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1319 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(1024)); /* XXX */ 1320 break; 1321 } 1322 *(uint64_t *)(&cp[2]) = htole64( 1323 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 1324 XHCI_EPCTX_2_DCS_SET(1)); 1325 1326 /* sync input contexts before they are read from memory */ 1327 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1328 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1329 sc->sc_ctxsz * 1); 1330 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1331 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1332 1333 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1334 trb.trb_2 = 0; 1335 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1336 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1337 1338 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1339 1340 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1341 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1342 sc->sc_ctxsz * 1); 1343 1344 return err; 1345 } 1346 1347 #if 0 1348 static usbd_status 1349 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1350 { 1351 #ifdef USB_DEBUG 1352 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1353 #endif 1354 1355 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1356 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1357 1358 return USBD_NORMAL_COMPLETION; 1359 } 1360 #endif 1361 1362 /* 4.6.8, 6.4.3.7 */ 1363 static usbd_status 1364 xhci_reset_endpoint(struct usbd_pipe *pipe) 1365 { 1366 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1367 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1368 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1369 struct xhci_trb trb; 1370 usbd_status err; 1371 1372 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1373 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1374 1375 KASSERT(!mutex_owned(&sc->sc_lock)); 1376 1377 trb.trb_0 = 0; 1378 trb.trb_2 = 0; 1379 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1380 XHCI_TRB_3_EP_SET(dci) | 1381 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1382 1383 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1384 1385 return err; 1386 } 1387 1388 /* 1389 * 4.6.9, 6.4.3.8 1390 * Stop execution of TDs on xfer ring. 1391 * Should be called with sc_lock held. 1392 */ 1393 static usbd_status 1394 xhci_stop_endpoint(struct usbd_pipe *pipe) 1395 { 1396 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1397 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1398 struct xhci_trb trb; 1399 usbd_status err; 1400 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1401 1402 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1403 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1404 1405 KASSERT(mutex_owned(&sc->sc_lock)); 1406 1407 trb.trb_0 = 0; 1408 trb.trb_2 = 0; 1409 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1410 XHCI_TRB_3_EP_SET(dci) | 1411 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1412 1413 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1414 1415 return err; 1416 } 1417 1418 /* 1419 * Set TR Dequeue Pointer. 1420 * xCHI 1.1 4.6.10 6.4.3.9 1421 * Purge all of the transfer requests on ring. 1422 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1423 * error will be generated. 1424 */ 1425 static usbd_status 1426 xhci_set_dequeue(struct usbd_pipe *pipe) 1427 { 1428 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1429 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1430 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1431 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1432 struct xhci_trb trb; 1433 usbd_status err; 1434 1435 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1436 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1437 1438 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1439 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1440 BUS_DMASYNC_PREWRITE); 1441 1442 xr->xr_ep = 0; 1443 xr->xr_cs = 1; 1444 1445 /* set DCS */ 1446 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1447 trb.trb_2 = 0; 1448 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1449 XHCI_TRB_3_EP_SET(dci) | 1450 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1451 1452 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1453 1454 return err; 1455 } 1456 1457 /* 1458 * Open new pipe: called from usbd_setup_pipe_flags. 1459 * Fills methods of pipe. 1460 * If pipe is not for ep0, calls configure_endpoint. 1461 */ 1462 static usbd_status 1463 xhci_open(struct usbd_pipe *pipe) 1464 { 1465 struct usbd_device * const dev = pipe->up_dev; 1466 struct xhci_softc * const sc = dev->ud_bus->ub_hcpriv; 1467 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1468 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1469 1470 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1471 DPRINTFN(1, "addr %d depth %d port %d speed %d", 1472 dev->ud_addr, dev->ud_depth, dev->ud_powersrc->up_portno, 1473 dev->ud_speed); 1474 1475 if (sc->sc_dying) 1476 return USBD_IOERROR; 1477 1478 /* Root Hub */ 1479 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1480 switch (ed->bEndpointAddress) { 1481 case USB_CONTROL_ENDPOINT: 1482 pipe->up_methods = &roothub_ctrl_methods; 1483 break; 1484 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1485 pipe->up_methods = &xhci_root_intr_methods; 1486 break; 1487 default: 1488 pipe->up_methods = NULL; 1489 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1490 ed->bEndpointAddress, 0, 0, 0); 1491 return USBD_INVAL; 1492 } 1493 return USBD_NORMAL_COMPLETION; 1494 } 1495 1496 switch (xfertype) { 1497 case UE_CONTROL: 1498 pipe->up_methods = &xhci_device_ctrl_methods; 1499 break; 1500 case UE_ISOCHRONOUS: 1501 pipe->up_methods = &xhci_device_isoc_methods; 1502 return USBD_INVAL; 1503 break; 1504 case UE_BULK: 1505 pipe->up_methods = &xhci_device_bulk_methods; 1506 break; 1507 case UE_INTERRUPT: 1508 pipe->up_methods = &xhci_device_intr_methods; 1509 break; 1510 default: 1511 return USBD_IOERROR; 1512 break; 1513 } 1514 1515 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1516 return xhci_configure_endpoint(pipe); 1517 1518 return USBD_NORMAL_COMPLETION; 1519 } 1520 1521 /* 1522 * Closes pipe, called from usbd_kill_pipe via close methods. 1523 * If the endpoint to be closed is ep0, disable_slot. 1524 * Should be called with sc_lock held. 1525 */ 1526 static usbd_status 1527 xhci_close_pipe(struct usbd_pipe *pipe) 1528 { 1529 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1530 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1531 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1532 const u_int dci = xhci_ep_get_dci(ed); 1533 struct xhci_trb trb; 1534 usbd_status err; 1535 uint32_t *cp; 1536 1537 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1538 1539 if (sc->sc_dying) 1540 return USBD_IOERROR; 1541 1542 if (xs == NULL || xs->xs_idx == 0) 1543 /* xs is uninitialized before xhci_init_slot */ 1544 return USBD_IOERROR; 1545 1546 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1547 1548 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1549 KASSERT(mutex_owned(&sc->sc_lock)); 1550 1551 if (pipe->up_dev->ud_depth == 0) 1552 return USBD_NORMAL_COMPLETION; 1553 1554 if (dci == XHCI_DCI_EP_CONTROL) { 1555 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1556 return xhci_disable_slot(sc, xs->xs_idx); 1557 } 1558 1559 /* 1560 * This may fail in the case that xhci_close_pipe is called after 1561 * xhci_abort_xfer e.g. usbd_kill_pipe. 1562 */ 1563 (void)xhci_stop_endpoint(pipe); 1564 1565 /* 1566 * set appropriate bit to be dropped. 1567 * don't set DC bit to 1, otherwise all endpoints 1568 * would be deconfigured. 1569 */ 1570 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1571 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1572 cp[1] = htole32(0); 1573 1574 /* XXX should be most significant one, not dci? */ 1575 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1576 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1577 1578 /* sync input contexts before they are read from memory */ 1579 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1580 1581 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1582 trb.trb_2 = 0; 1583 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1584 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1585 1586 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1587 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1588 1589 return err; 1590 } 1591 1592 /* 1593 * Abort transfer. 1594 * Called with sc_lock held. 1595 * May be called from softintr context. 1596 */ 1597 static void 1598 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1599 { 1600 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1601 1602 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1603 DPRINTFN(4, "xfer %p pipe %p status %d", 1604 xfer, xfer->ux_pipe, status, 0); 1605 1606 KASSERT(mutex_owned(&sc->sc_lock)); 1607 1608 if (sc->sc_dying) { 1609 /* If we're dying, just do the software part. */ 1610 DPRINTFN(4, "dying", 0, 0, 0, 0); 1611 xfer->ux_status = status; /* make software ignore it */ 1612 callout_stop(&xfer->ux_callout); 1613 usb_transfer_complete(xfer); 1614 return; 1615 } 1616 1617 /* XXX need more stuff */ 1618 xfer->ux_status = status; 1619 callout_stop(&xfer->ux_callout); 1620 usb_transfer_complete(xfer); 1621 1622 KASSERT(mutex_owned(&sc->sc_lock)); 1623 } 1624 1625 #if 1 /* XXX experimental */ 1626 /* 1627 * Recover STALLed endpoint. 1628 * xHCI 1.1 sect 4.10.2.1 1629 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1630 * all transfers on transfer ring. 1631 * These are done in thread context asynchronously. 1632 */ 1633 static void 1634 xhci_clear_endpoint_stall_async_task(void *cookie) 1635 { 1636 struct usbd_xfer * const xfer = cookie; 1637 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1638 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1639 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1640 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1641 1642 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1643 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1644 1645 xhci_reset_endpoint(xfer->ux_pipe); 1646 xhci_set_dequeue(xfer->ux_pipe); 1647 1648 mutex_enter(&sc->sc_lock); 1649 tr->is_halted = false; 1650 usb_transfer_complete(xfer); 1651 mutex_exit(&sc->sc_lock); 1652 DPRINTFN(4, "ends", 0, 0, 0, 0); 1653 } 1654 1655 static usbd_status 1656 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1657 { 1658 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1659 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1660 1661 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1662 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1663 1664 if (sc->sc_dying) { 1665 return USBD_IOERROR; 1666 } 1667 1668 usb_init_task(&xp->xp_async_task, 1669 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1670 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1671 DPRINTFN(4, "ends", 0, 0, 0, 0); 1672 1673 return USBD_NORMAL_COMPLETION; 1674 } 1675 1676 #endif /* XXX experimental */ 1677 1678 /* 1679 * Notify roothub port status/change to uhub_intr. 1680 */ 1681 static void 1682 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1683 { 1684 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1685 uint8_t *p; 1686 1687 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1688 DPRINTFN(4, "port %u status change", port, 0, 0, 0); 1689 1690 if (xfer == NULL) 1691 return; 1692 1693 p = xfer->ux_buf; 1694 memset(p, 0, xfer->ux_length); 1695 p[port/NBBY] |= 1 << (port%NBBY); 1696 xfer->ux_actlen = xfer->ux_length; 1697 xfer->ux_status = USBD_NORMAL_COMPLETION; 1698 usb_transfer_complete(xfer); 1699 } 1700 1701 /* 1702 * Process events: 1703 * + Transfer comeplete 1704 * + Command complete 1705 * + Roothub Port status/change 1706 */ 1707 static void 1708 xhci_handle_event(struct xhci_softc * const sc, 1709 const struct xhci_trb * const trb) 1710 { 1711 uint64_t trb_0; 1712 uint32_t trb_2, trb_3; 1713 uint8_t trberr; 1714 1715 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1716 1717 trb_0 = le64toh(trb->trb_0); 1718 trb_2 = le32toh(trb->trb_2); 1719 trb_3 = le32toh(trb->trb_3); 1720 trberr = XHCI_TRB_2_ERROR_GET(trb_2); 1721 1722 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1723 trb, trb_0, trb_2, trb_3); 1724 1725 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 1726 case XHCI_TRB_EVENT_TRANSFER: { 1727 u_int slot, dci; 1728 struct xhci_slot *xs; 1729 struct xhci_ring *xr; 1730 struct xhci_xfer *xx; 1731 struct usbd_xfer *xfer; 1732 usbd_status err; 1733 1734 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1735 dci = XHCI_TRB_3_EP_GET(trb_3); 1736 1737 xs = &sc->sc_slots[slot]; 1738 xr = &xs->xs_ep[dci].xe_tr; 1739 /* sanity check */ 1740 if (xs->xs_idx == 0 || xs->xs_idx >= sc->sc_maxslots) { 1741 DPRINTFN(1, "invalid slot %u", xs->xs_idx, 0, 0, 0); 1742 break; 1743 } 1744 1745 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1746 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 1747 1748 /* trb_0 range sanity check */ 1749 if (trb_0 < trbp || 1750 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 1751 (trb_0 - trbp) / sizeof(struct xhci_trb) >= 1752 xr->xr_ntrb) { 1753 DPRINTFN(1, 1754 "invalid trb_0 0x%"PRIx64" trbp 0x%"PRIx64, 1755 trb_0, trbp, 0, 0); 1756 break; 1757 } 1758 int idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 1759 xx = xr->xr_cookies[idx]; 1760 } else { 1761 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1762 } 1763 /* 1764 * stop_endpoint may cause ERR_STOPPED_LENGTH_INVALID, 1765 * in which case this condition may happen. 1766 */ 1767 if (xx == NULL) { 1768 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1769 break; 1770 } 1771 xfer = &xx->xx_xfer; 1772 /* XXX this may happen when detaching */ 1773 if (xfer == NULL) { 1774 DPRINTFN(1, "xfer done: xfer is NULL", 0, 0, 0, 0); 1775 break; 1776 } 1777 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1778 /* XXX I dunno why this happens */ 1779 if (!xfer->ux_pipe->up_repeat && 1780 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1781 DPRINTFN(1, "xfer done: xfer not started", 0, 0, 0, 0); 1782 break; 1783 } 1784 1785 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1786 DPRINTFN(14, "transfer event data: " 1787 "0x%016"PRIx64" 0x%08"PRIx32" %02x", 1788 trb_0, XHCI_TRB_2_REM_GET(trb_2), 1789 XHCI_TRB_2_ERROR_GET(trb_2), 0); 1790 if ((trb_0 & 0x3) == 0x3) { 1791 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1792 } 1793 } 1794 1795 switch (trberr) { 1796 case XHCI_TRB_ERROR_SHORT_PKT: 1797 case XHCI_TRB_ERROR_SUCCESS: 1798 xfer->ux_actlen = 1799 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1800 err = USBD_NORMAL_COMPLETION; 1801 break; 1802 case XHCI_TRB_ERROR_STALL: 1803 case XHCI_TRB_ERROR_BABBLE: 1804 DPRINTFN(1, "evh: xfer done: ERR %u slot %u dci %u", 1805 trberr, slot, dci, 0); 1806 xr->is_halted = true; 1807 err = USBD_STALLED; 1808 #if 1 /* XXX experimental */ 1809 /* 1810 * Stalled endpoints can be recoverd by issuing 1811 * command TRB TYPE_RESET_EP on xHCI instead of 1812 * issuing request CLEAR_PORT_FEATURE UF_ENDPOINT_HALT 1813 * on the endpoint. However, this function may be 1814 * called from softint context (e.g. from umass), 1815 * in that case driver gets KASSERT in cv_timedwait 1816 * in xhci_do_command. 1817 * To avoid this, this runs reset_endpoint and 1818 * usb_transfer_complete in usb task thread 1819 * asynchronously (and then umass issues clear 1820 * UF_ENDPOINT_HALT). 1821 */ 1822 xfer->ux_status = err; 1823 xhci_clear_endpoint_stall_async(xfer); 1824 return; 1825 #else 1826 break; 1827 #endif 1828 case XHCI_TRB_ERROR_CMD_ABORTED: 1829 case XHCI_TRB_ERROR_STOPPED: 1830 err = USBD_CANCELLED; 1831 break; 1832 case XHCI_TRB_ERROR_NO_SLOTS: 1833 err = USBD_NO_ADDR; 1834 break; 1835 default: 1836 DPRINTFN(1, "evh: xfer done: ERR %u slot %u dci %u", 1837 trberr, slot, dci, 0); 1838 err = USBD_IOERROR; 1839 break; 1840 } 1841 xfer->ux_status = err; 1842 1843 //mutex_enter(&sc->sc_lock); /* XXX ??? */ 1844 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1845 if ((trb_0 & 0x3) == 0x0) { 1846 usb_transfer_complete(xfer); 1847 } 1848 } else { 1849 usb_transfer_complete(xfer); 1850 } 1851 //mutex_exit(&sc->sc_lock); /* XXX ??? */ 1852 1853 } 1854 break; 1855 case XHCI_TRB_EVENT_CMD_COMPLETE: 1856 if (trb_0 == sc->sc_command_addr) { 1857 sc->sc_result_trb.trb_0 = trb_0; 1858 sc->sc_result_trb.trb_2 = trb_2; 1859 sc->sc_result_trb.trb_3 = trb_3; 1860 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1861 XHCI_TRB_ERROR_SUCCESS) { 1862 DPRINTFN(1, "command completion " 1863 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1864 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1865 } 1866 cv_signal(&sc->sc_command_cv); 1867 } else { 1868 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 1869 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1870 trb_2, trb_3); 1871 } 1872 break; 1873 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1874 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1875 break; 1876 default: 1877 break; 1878 } 1879 } 1880 1881 static void 1882 xhci_softintr(void *v) 1883 { 1884 struct usbd_bus * const bus = v; 1885 struct xhci_softc * const sc = bus->ub_hcpriv; 1886 struct xhci_ring * const er = &sc->sc_er; 1887 struct xhci_trb *trb; 1888 int i, j, k; 1889 1890 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1891 1892 i = er->xr_ep; 1893 j = er->xr_cs; 1894 1895 DPRINTFN(16, "xr_ep %d xr_cs %d", i, j, 0, 0); 1896 1897 while (1) { 1898 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 1899 BUS_DMASYNC_POSTREAD); 1900 trb = &er->xr_trb[i]; 1901 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1902 1903 if (j != k) 1904 break; 1905 1906 xhci_handle_event(sc, trb); 1907 1908 i++; 1909 if (i == XHCI_EVENT_RING_TRBS) { 1910 i = 0; 1911 j ^= 1; 1912 } 1913 } 1914 1915 er->xr_ep = i; 1916 er->xr_cs = j; 1917 1918 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 1919 XHCI_ERDP_LO_BUSY); 1920 1921 DPRINTFN(16, "ends", 0, 0, 0, 0); 1922 1923 return; 1924 } 1925 1926 static void 1927 xhci_poll(struct usbd_bus *bus) 1928 { 1929 struct xhci_softc * const sc = bus->ub_hcpriv; 1930 1931 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1932 1933 mutex_spin_enter(&sc->sc_intr_lock); 1934 xhci_intr1(sc); 1935 mutex_spin_exit(&sc->sc_intr_lock); 1936 1937 return; 1938 } 1939 1940 static struct usbd_xfer * 1941 xhci_allocx(struct usbd_bus *bus) 1942 { 1943 struct xhci_softc * const sc = bus->ub_hcpriv; 1944 struct usbd_xfer *xfer; 1945 1946 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1947 1948 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1949 if (xfer != NULL) { 1950 memset(xfer, 0, sizeof(struct xhci_xfer)); 1951 #ifdef DIAGNOSTIC 1952 xfer->ux_state = XFER_BUSY; 1953 #endif 1954 } 1955 1956 return xfer; 1957 } 1958 1959 static void 1960 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1961 { 1962 struct xhci_softc * const sc = bus->ub_hcpriv; 1963 1964 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1965 1966 #ifdef DIAGNOSTIC 1967 if (xfer->ux_state != XFER_BUSY) { 1968 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 1969 xfer, xfer->ux_state, 0, 0); 1970 } 1971 xfer->ux_state = XFER_FREE; 1972 #endif 1973 pool_cache_put(sc->sc_xferpool, xfer); 1974 } 1975 1976 static void 1977 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1978 { 1979 struct xhci_softc * const sc = bus->ub_hcpriv; 1980 1981 *lock = &sc->sc_lock; 1982 } 1983 1984 extern uint32_t usb_cookie_no; 1985 1986 /* 1987 * Called if uhub_explore find new device (via usbd_new_device). 1988 * Allocate and construct dev structure of default endpoint (ep0). 1989 * Determine initial MaxPacketSize (mps) by speed. 1990 * Determine route string and roothub port for slot of dev. 1991 * Allocate pipe of ep0. 1992 * Enable and initialize slot and Set Address. 1993 * Read device descriptor. 1994 * Register this device. 1995 */ 1996 static usbd_status 1997 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 1998 int speed, int port, struct usbd_port *up) 1999 { 2000 struct xhci_softc * const sc = bus->ub_hcpriv; 2001 struct usbd_device *dev; 2002 usbd_status err; 2003 usb_device_descriptor_t *dd; 2004 struct usbd_device *hub; 2005 struct usbd_device *adev; 2006 int rhport = 0; 2007 struct xhci_slot *xs; 2008 uint32_t *cp; 2009 uint32_t route = 0; 2010 uint8_t slot = 0; 2011 uint8_t addr; 2012 2013 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2014 DPRINTFN(4, "port=%d depth=%d speed=%d upport %d", 2015 port, depth, speed, up->up_portno); 2016 2017 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2018 if (dev == NULL) 2019 return USBD_NOMEM; 2020 2021 dev->ud_bus = bus; 2022 2023 /* Set up default endpoint handle. */ 2024 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2025 2026 /* Set up default endpoint descriptor. */ 2027 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2028 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2029 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2030 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2031 /* 4.3, 4.8.2.1 */ 2032 if (USB_IS_SS(speed)) { 2033 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2034 } else 2035 switch (speed) { 2036 case USB_SPEED_FULL: 2037 /* XXX using 64 as initial mps of ep0 in FS */ 2038 case USB_SPEED_HIGH: 2039 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2040 break; 2041 case USB_SPEED_LOW: 2042 default: 2043 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2044 break; 2045 } 2046 dev->ud_ep0desc.bInterval = 0; 2047 2048 /* doesn't matter, just don't let it uninitialized */ 2049 dev->ud_ep0.ue_toggle = 0; 2050 2051 DPRINTFN(4, "up %p portno %d", up, up->up_portno, 0, 0); 2052 2053 dev->ud_quirks = &usbd_no_quirk; 2054 dev->ud_addr = 0; 2055 dev->ud_ddesc.bMaxPacketSize = 0; 2056 dev->ud_depth = depth; 2057 dev->ud_powersrc = up; 2058 dev->ud_myhub = up->up_parent; 2059 2060 up->up_dev = dev; 2061 2062 /* Locate root hub port */ 2063 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2064 uint32_t dep; 2065 2066 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2067 hub, hub->ud_depth, hub->ud_powersrc, 2068 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2069 2070 if (hub->ud_powersrc == NULL) 2071 break; 2072 dep = hub->ud_depth; 2073 if (dep == 0) 2074 break; 2075 rhport = hub->ud_powersrc->up_portno; 2076 if (dep > USB_HUB_MAX_DEPTH) 2077 continue; 2078 2079 route |= 2080 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2081 << ((dep - 1) * 4); 2082 } 2083 route = route >> 4; 2084 DPRINTFN(4, "rhport %d Route %05x hub %p", rhport, route, hub, 0); 2085 2086 /* Locate port on upstream high speed hub */ 2087 for (adev = dev, hub = up->up_parent; 2088 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2089 adev = hub, hub = hub->ud_myhub) 2090 ; 2091 if (hub) { 2092 int p; 2093 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2094 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2095 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2096 goto found; 2097 } 2098 } 2099 panic("xhci_new_device: cannot find HS port"); 2100 found: 2101 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2102 } else { 2103 dev->ud_myhsport = NULL; 2104 } 2105 2106 dev->ud_speed = speed; 2107 dev->ud_langid = USBD_NOLANG; 2108 dev->ud_cookie.cookie = ++usb_cookie_no; 2109 2110 /* Establish the default pipe. */ 2111 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2112 &dev->ud_pipe0); 2113 if (err) { 2114 goto bad; 2115 } 2116 2117 dd = &dev->ud_ddesc; 2118 2119 if ((depth == 0) && (port == 0)) { 2120 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2121 bus->ub_devices[dev->ud_addr] = dev; 2122 err = usbd_get_initial_ddesc(dev, dd); 2123 if (err) 2124 goto bad; 2125 err = usbd_reload_device_desc(dev); 2126 if (err) 2127 goto bad; 2128 } else { 2129 err = xhci_enable_slot(sc, &slot); 2130 if (err) 2131 goto bad; 2132 xs = &sc->sc_slots[slot]; 2133 dev->ud_hcpriv = xs; 2134 err = xhci_init_slot(dev, slot, route, rhport); 2135 if (err) { 2136 dev->ud_hcpriv = NULL; 2137 /* 2138 * We have to disable_slot here because 2139 * xs->xs_idx == 0 when xhci_init_slot fails, 2140 * in that case usbd_remove_dev won't work. 2141 */ 2142 mutex_enter(&sc->sc_lock); 2143 xhci_disable_slot(sc, slot); 2144 mutex_exit(&sc->sc_lock); 2145 goto bad; 2146 } 2147 2148 /* Allow device time to set new address */ 2149 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2150 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2151 //hexdump("slot context", cp, sc->sc_ctxsz); 2152 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2153 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2154 /* XXX ensure we know when the hardware does something 2155 we can't yet cope with */ 2156 KASSERT(addr >= 1 && addr <= 127); 2157 dev->ud_addr = addr; 2158 /* XXX dev->ud_addr not necessarily unique on bus */ 2159 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2160 bus->ub_devices[dev->ud_addr] = dev; 2161 2162 /* read 64 bytes of device descriptor */ 2163 err = usbd_get_initial_ddesc(dev, dd); 2164 if (err) 2165 goto bad; 2166 /* 4.8.2.1 */ 2167 if (USB_IS_SS(speed)) { 2168 if (dd->bMaxPacketSize != 9) { 2169 printf("%s: invalid mps 2^%u for SS ep0," 2170 " using 512\n", 2171 device_xname(sc->sc_dev), 2172 dd->bMaxPacketSize); 2173 dd->bMaxPacketSize = 9; 2174 } 2175 USETW(dev->ud_ep0desc.wMaxPacketSize, 2176 (1 << dd->bMaxPacketSize)); 2177 } else 2178 USETW(dev->ud_ep0desc.wMaxPacketSize, 2179 dd->bMaxPacketSize); 2180 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2181 xhci_update_ep0_mps(sc, xs, 2182 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2183 err = usbd_reload_device_desc(dev); 2184 if (err) 2185 goto bad; 2186 2187 #if 0 2188 /* Re-establish the default pipe with the new MPS. */ 2189 /* In xhci this is done by xhci_update_ep0_mps. */ 2190 usbd_kill_pipe(dev->ud_pipe0); 2191 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2192 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2193 #endif 2194 } 2195 2196 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2197 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2198 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2199 dd->bDeviceClass, dd->bDeviceSubClass, 2200 dd->bDeviceProtocol, 0); 2201 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2202 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2203 dev->ud_speed); 2204 2205 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2206 2207 if ((depth == 0) && (port == 0)) { 2208 usbd_attach_roothub(parent, dev); 2209 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2210 return USBD_NORMAL_COMPLETION; 2211 } 2212 2213 2214 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2215 bad: 2216 if (err != USBD_NORMAL_COMPLETION) { 2217 usbd_remove_device(dev, up); 2218 } 2219 2220 return err; 2221 } 2222 2223 static usbd_status 2224 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2225 size_t ntrb, size_t align) 2226 { 2227 usbd_status err; 2228 size_t size = ntrb * XHCI_TRB_SIZE; 2229 2230 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2231 2232 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2233 if (err) 2234 return err; 2235 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2236 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2237 xr->xr_trb = xhci_ring_trbv(xr, 0); 2238 xr->xr_ntrb = ntrb; 2239 xr->xr_ep = 0; 2240 xr->xr_cs = 1; 2241 memset(xr->xr_trb, 0, size); 2242 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 2243 xr->is_halted = false; 2244 2245 return USBD_NORMAL_COMPLETION; 2246 } 2247 2248 static void 2249 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2250 { 2251 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2252 mutex_destroy(&xr->xr_lock); 2253 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2254 } 2255 2256 static void 2257 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2258 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2259 { 2260 size_t i; 2261 u_int ri; 2262 u_int cs; 2263 uint64_t parameter; 2264 uint32_t status; 2265 uint32_t control; 2266 2267 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2268 2269 for (i = 0; i < ntrbs; i++) { 2270 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2271 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2272 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2273 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2274 XHCI_TRB_TYPE_LINK); 2275 } 2276 2277 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2278 2279 ri = xr->xr_ep; 2280 cs = xr->xr_cs; 2281 2282 /* 2283 * Although the xhci hardware can do scatter/gather dma from 2284 * arbitrary sized buffers, there is a non-obvious restriction 2285 * that a LINK trb is only allowed at the end of a burst of 2286 * transfers - which might be 16kB. 2287 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2288 * The simple solution is not to allow a LINK trb in the middle 2289 * of anything - as here. 2290 * XXX: (dsl) There are xhci controllers out there (eg some made by 2291 * ASMedia) that seem to lock up if they process a LINK trb but 2292 * cannot process the linked-to trb yet. 2293 * The code should write the 'cycle' bit on the link trb AFTER 2294 * adding the other trb. 2295 */ 2296 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2297 parameter = xhci_ring_trbp(xr, 0); 2298 status = 0; 2299 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2300 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2301 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 2302 htole32(status), htole32(control)); 2303 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2304 BUS_DMASYNC_PREWRITE); 2305 xr->xr_cookies[ri] = NULL; 2306 xr->xr_ep = 0; 2307 xr->xr_cs ^= 1; 2308 ri = xr->xr_ep; 2309 cs = xr->xr_cs; 2310 } 2311 2312 ri++; 2313 2314 /* Write any subsequent TRB first */ 2315 for (i = 1; i < ntrbs; i++) { 2316 parameter = trbs[i].trb_0; 2317 status = trbs[i].trb_2; 2318 control = trbs[i].trb_3; 2319 2320 if (cs) { 2321 control |= XHCI_TRB_3_CYCLE_BIT; 2322 } else { 2323 control &= ~XHCI_TRB_3_CYCLE_BIT; 2324 } 2325 2326 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 2327 htole32(status), htole32(control)); 2328 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2329 BUS_DMASYNC_PREWRITE); 2330 xr->xr_cookies[ri] = cookie; 2331 ri++; 2332 } 2333 2334 /* Write the first TRB last */ 2335 i = 0; 2336 parameter = trbs[i].trb_0; 2337 status = trbs[i].trb_2; 2338 control = trbs[i].trb_3; 2339 2340 if (xr->xr_cs) { 2341 control |= XHCI_TRB_3_CYCLE_BIT; 2342 } else { 2343 control &= ~XHCI_TRB_3_CYCLE_BIT; 2344 } 2345 2346 xhci_trb_put(&xr->xr_trb[xr->xr_ep], htole64(parameter), 2347 htole32(status), htole32(control)); 2348 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2349 BUS_DMASYNC_PREWRITE); 2350 xr->xr_cookies[xr->xr_ep] = cookie; 2351 2352 xr->xr_ep = ri; 2353 xr->xr_cs = cs; 2354 2355 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2356 } 2357 2358 /* 2359 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2360 * Command completion is notified by cv_signal from xhci_handle_event 2361 * (called from interrupt from xHCI), or timed-out. 2362 * Command validation is performed in xhci_handle_event by checking if 2363 * trb_0 in CMD_COMPLETE TRB and sc->sc_command_addr are identical. 2364 * locked = 0: called without lock held 2365 * locked = 1: allows called with lock held 2366 * 'locked' is needed as some methods are called with sc_lock_held. 2367 * (see usbdivar.h) 2368 */ 2369 static usbd_status 2370 xhci_do_command1(struct xhci_softc * const sc, struct xhci_trb * const trb, 2371 int timeout, int locked) 2372 { 2373 struct xhci_ring * const cr = &sc->sc_cr; 2374 usbd_status err; 2375 2376 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2377 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2378 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2379 2380 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2381 2382 if (!locked) 2383 mutex_enter(&sc->sc_lock); 2384 2385 /* XXX KASSERT may fail when cv_timedwait unlocks sc_lock */ 2386 KASSERT(sc->sc_command_addr == 0); 2387 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2388 2389 mutex_enter(&cr->xr_lock); 2390 xhci_ring_put(sc, cr, NULL, trb, 1); 2391 mutex_exit(&cr->xr_lock); 2392 2393 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2394 2395 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2396 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2397 err = USBD_TIMEOUT; 2398 goto timedout; 2399 } 2400 2401 trb->trb_0 = sc->sc_result_trb.trb_0; 2402 trb->trb_2 = sc->sc_result_trb.trb_2; 2403 trb->trb_3 = sc->sc_result_trb.trb_3; 2404 2405 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2406 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2407 2408 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2409 case XHCI_TRB_ERROR_SUCCESS: 2410 err = USBD_NORMAL_COMPLETION; 2411 break; 2412 default: 2413 case 192 ... 223: 2414 err = USBD_IOERROR; 2415 break; 2416 case 224 ... 255: 2417 err = USBD_NORMAL_COMPLETION; 2418 break; 2419 } 2420 2421 timedout: 2422 sc->sc_command_addr = 0; 2423 if (!locked) 2424 mutex_exit(&sc->sc_lock); 2425 return err; 2426 } 2427 2428 static usbd_status 2429 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2430 int timeout) 2431 { 2432 return xhci_do_command1(sc, trb, timeout, 0); 2433 } 2434 2435 /* 2436 * This allows xhci_do_command with already sc_lock held. 2437 * This is needed as USB stack calls close methods with sc_lock_held. 2438 * (see usbdivar.h) 2439 */ 2440 static usbd_status 2441 xhci_do_command_locked(struct xhci_softc * const sc, 2442 struct xhci_trb * const trb, int timeout) 2443 { 2444 return xhci_do_command1(sc, trb, timeout, 1); 2445 } 2446 2447 static usbd_status 2448 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2449 { 2450 struct xhci_trb trb; 2451 usbd_status err; 2452 2453 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2454 2455 trb.trb_0 = 0; 2456 trb.trb_2 = 0; 2457 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2458 2459 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2460 if (err != USBD_NORMAL_COMPLETION) { 2461 return err; 2462 } 2463 2464 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2465 2466 return err; 2467 } 2468 2469 /* 2470 * Deallocate DMA buffer and ring buffer, and disable_slot. 2471 * Should be called with sc_lock held. 2472 */ 2473 static usbd_status 2474 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2475 { 2476 struct xhci_trb trb; 2477 struct xhci_slot *xs; 2478 2479 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2480 2481 if (sc->sc_dying) 2482 return USBD_IOERROR; 2483 2484 xs = &sc->sc_slots[slot]; 2485 if (xs->xs_idx != 0) { 2486 for (int i = XHCI_DCI_SLOT + 1; i < 32; i++) { 2487 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2488 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2489 } 2490 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2491 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2492 } 2493 2494 trb.trb_0 = 0; 2495 trb.trb_2 = 0; 2496 trb.trb_3 = htole32( 2497 XHCI_TRB_3_SLOT_SET(slot) | 2498 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2499 2500 return xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2501 } 2502 2503 /* 2504 * Change slot state. 2505 * bsr=0: ENABLED -> ADDRESSED 2506 * bsr=1: ENABLED -> DEFAULT 2507 * see xHCI 1.1 4.5.3, 3.3.4 2508 */ 2509 static usbd_status 2510 xhci_address_device(struct xhci_softc * const sc, 2511 uint64_t icp, uint8_t slot_id, bool bsr) 2512 { 2513 struct xhci_trb trb; 2514 usbd_status err; 2515 2516 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2517 2518 trb.trb_0 = icp; 2519 trb.trb_2 = 0; 2520 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2521 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2522 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2523 2524 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2525 return err; 2526 } 2527 2528 static usbd_status 2529 xhci_update_ep0_mps(struct xhci_softc * const sc, 2530 struct xhci_slot * const xs, u_int mps) 2531 { 2532 struct xhci_trb trb; 2533 usbd_status err; 2534 uint32_t * cp; 2535 2536 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2537 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2538 2539 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2540 cp[0] = htole32(0); 2541 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2542 2543 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2544 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2545 2546 /* sync input contexts before they are read from memory */ 2547 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2548 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2549 sc->sc_ctxsz * 4); 2550 2551 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2552 trb.trb_2 = 0; 2553 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2554 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2555 2556 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2557 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2558 return err; 2559 } 2560 2561 static void 2562 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2563 { 2564 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2565 2566 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2567 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2568 &dcbaa[si], dcba, si, 0); 2569 2570 dcbaa[si] = htole64(dcba); 2571 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2572 BUS_DMASYNC_PREWRITE); 2573 } 2574 2575 /* 2576 * Allocate DMA buffer and ring buffer for specified slot 2577 * and set Device Context Base Address 2578 * and issue Set Address device command. 2579 */ 2580 static usbd_status 2581 xhci_init_slot(struct usbd_device *dev, uint32_t slot, int route, int rhport) 2582 { 2583 struct xhci_softc * const sc = dev->ud_bus->ub_hcpriv; 2584 struct xhci_slot *xs; 2585 usbd_status err; 2586 u_int dci; 2587 uint32_t *cp; 2588 uint32_t mps = UGETW(dev->ud_ep0desc.wMaxPacketSize); 2589 2590 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2591 DPRINTFN(4, "slot %u speed %d rhport %d route %05x", 2592 slot, dev->ud_speed, route, rhport); 2593 2594 xs = &sc->sc_slots[slot]; 2595 2596 /* allocate contexts */ 2597 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2598 &xs->xs_dc_dma); 2599 if (err) 2600 return err; 2601 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2602 2603 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2604 &xs->xs_ic_dma); 2605 if (err) 2606 goto bad1; 2607 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2608 2609 for (dci = 0; dci < 32; dci++) { 2610 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2611 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2612 if (dci == XHCI_DCI_SLOT) 2613 continue; 2614 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2615 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2616 if (err) { 2617 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2618 goto bad2; 2619 } 2620 } 2621 2622 /* set up initial input control context */ 2623 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2624 cp[0] = htole32(0); 2625 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 2626 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2627 2628 /* set up input slot context */ 2629 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2630 xhci_setup_sctx(dev, cp); 2631 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(1)); 2632 cp[0] |= htole32(XHCI_SCTX_0_ROUTE_SET(route)); 2633 cp[1] |= htole32(XHCI_SCTX_1_RH_PORT_SET(rhport)); 2634 2635 /* set up input EP0 context */ 2636 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2637 cp[0] = htole32(0); 2638 cp[1] = htole32( 2639 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 2640 XHCI_EPCTX_1_EPTYPE_SET(4) | 2641 XHCI_EPCTX_1_CERR_SET(3) 2642 ); 2643 /* can't use xhci_ep_get_dci() yet? */ 2644 *(uint64_t *)(&cp[2]) = htole64( 2645 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 2646 XHCI_EPCTX_2_DCS_SET(1)); 2647 cp[4] = htole32( 2648 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 2649 ); 2650 2651 /* sync input contexts before they are read from memory */ 2652 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2653 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2654 sc->sc_ctxsz * 3); 2655 2656 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2657 2658 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 2659 false); 2660 2661 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2662 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2663 sc->sc_ctxsz * 2); 2664 2665 bad2: 2666 if (err == USBD_NORMAL_COMPLETION) { 2667 xs->xs_idx = slot; 2668 } else { 2669 for (int i = 1; i < dci; i++) { 2670 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2671 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2672 } 2673 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2674 bad1: 2675 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2676 xs->xs_idx = 0; 2677 } 2678 2679 return err; 2680 } 2681 2682 /* ----- */ 2683 2684 static void 2685 xhci_noop(struct usbd_pipe *pipe) 2686 { 2687 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2688 } 2689 2690 /* 2691 * Process root hub request. 2692 */ 2693 static int 2694 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2695 void *buf, int buflen) 2696 { 2697 struct xhci_softc * const sc = bus->ub_hcpriv; 2698 usb_port_status_t ps; 2699 int l, totlen = 0; 2700 uint16_t len, value, index; 2701 int port, i; 2702 uint32_t v; 2703 2704 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2705 2706 if (sc->sc_dying) 2707 return -1; 2708 2709 len = UGETW(req->wLength); 2710 value = UGETW(req->wValue); 2711 index = UGETW(req->wIndex); 2712 2713 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 2714 req->bmRequestType | (req->bRequest << 8), value, index, len); 2715 2716 #define C(x,y) ((x) | ((y) << 8)) 2717 switch (C(req->bRequest, req->bmRequestType)) { 2718 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2719 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 2720 if (len == 0) 2721 break; 2722 switch (value) { 2723 #define sd ((usb_string_descriptor_t *)buf) 2724 case C(2, UDESC_STRING): 2725 /* Product */ 2726 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 2727 break; 2728 #undef sd 2729 default: 2730 /* default from usbroothub */ 2731 return buflen; 2732 } 2733 break; 2734 2735 /* Hub requests */ 2736 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2737 break; 2738 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2739 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2740 index, value, 0, 0); 2741 if (index < 1 || index > sc->sc_maxports) { 2742 return -1; 2743 } 2744 port = XHCI_PORTSC(index); 2745 v = xhci_op_read_4(sc, port); 2746 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2747 v &= ~XHCI_PS_CLEAR; 2748 switch (value) { 2749 case UHF_PORT_ENABLE: 2750 xhci_op_write_4(sc, port, v &~ XHCI_PS_PED); 2751 break; 2752 case UHF_PORT_SUSPEND: 2753 return -1; 2754 case UHF_PORT_POWER: 2755 break; 2756 case UHF_PORT_TEST: 2757 case UHF_PORT_INDICATOR: 2758 return -1; 2759 case UHF_C_PORT_CONNECTION: 2760 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2761 break; 2762 case UHF_C_PORT_ENABLE: 2763 case UHF_C_PORT_SUSPEND: 2764 case UHF_C_PORT_OVER_CURRENT: 2765 return -1; 2766 case UHF_C_BH_PORT_RESET: 2767 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 2768 break; 2769 case UHF_C_PORT_RESET: 2770 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2771 break; 2772 case UHF_C_PORT_LINK_STATE: 2773 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 2774 break; 2775 case UHF_C_PORT_CONFIG_ERROR: 2776 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 2777 break; 2778 default: 2779 return -1; 2780 } 2781 break; 2782 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2783 if (len == 0) 2784 break; 2785 if ((value & 0xff) != 0) { 2786 return -1; 2787 } 2788 usb_hub_descriptor_t hubd; 2789 2790 totlen = min(buflen, sizeof(hubd)); 2791 memcpy(&hubd, buf, totlen); 2792 hubd.bNbrPorts = sc->sc_maxports; 2793 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2794 hubd.bPwrOn2PwrGood = 200; 2795 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 2796 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2797 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2798 totlen = min(totlen, hubd.bDescLength); 2799 memcpy(buf, &hubd, totlen); 2800 break; 2801 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2802 if (len != 4) { 2803 return -1; 2804 } 2805 memset(buf, 0, len); /* ? XXX */ 2806 totlen = len; 2807 break; 2808 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2809 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2810 if (index < 1 || index > sc->sc_maxports) { 2811 return -1; 2812 } 2813 if (len != 4) { 2814 return -1; 2815 } 2816 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 2817 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 2818 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 2819 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2820 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2821 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2822 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 2823 if (v & XHCI_PS_PR) i |= UPS_RESET; 2824 if (v & XHCI_PS_PP) { 2825 if (i & UPS_OTHER_SPEED) 2826 i |= UPS_PORT_POWER_SS; 2827 else 2828 i |= UPS_PORT_POWER; 2829 } 2830 if (i & UPS_OTHER_SPEED) 2831 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 2832 USETW(ps.wPortStatus, i); 2833 i = 0; 2834 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2835 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2836 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2837 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2838 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 2839 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 2840 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 2841 USETW(ps.wPortChange, i); 2842 totlen = min(len, sizeof(ps)); 2843 memcpy(buf, &ps, totlen); 2844 break; 2845 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2846 return -1; 2847 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 2848 break; 2849 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2850 break; 2851 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 2852 int optval = (index >> 8) & 0xff; 2853 index &= 0xff; 2854 if (index < 1 || index > sc->sc_maxports) { 2855 return -1; 2856 } 2857 port = XHCI_PORTSC(index); 2858 v = xhci_op_read_4(sc, port); 2859 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2860 v &= ~XHCI_PS_CLEAR; 2861 switch (value) { 2862 case UHF_PORT_ENABLE: 2863 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 2864 break; 2865 case UHF_PORT_SUSPEND: 2866 /* XXX suspend */ 2867 break; 2868 case UHF_PORT_RESET: 2869 v &= ~ (XHCI_PS_PED | XHCI_PS_PR); 2870 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 2871 /* Wait for reset to complete. */ 2872 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2873 if (sc->sc_dying) { 2874 return -1; 2875 } 2876 v = xhci_op_read_4(sc, port); 2877 if (v & XHCI_PS_PR) { 2878 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 2879 usb_delay_ms(&sc->sc_bus, 10); 2880 /* XXX */ 2881 } 2882 break; 2883 case UHF_PORT_POWER: 2884 /* XXX power control */ 2885 break; 2886 /* XXX more */ 2887 case UHF_C_PORT_RESET: 2888 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2889 break; 2890 case UHF_PORT_U1_TIMEOUT: 2891 if (USB_IS_SS(xhci_xspeed2speed(XHCI_PS_SPEED_GET(v)))){ 2892 return -1; 2893 } 2894 port = XHCI_PORTPMSC(index); 2895 v = xhci_op_read_4(sc, port); 2896 v &= ~XHCI_PM3_U1TO_SET(0xff); 2897 v |= XHCI_PM3_U1TO_SET(optval); 2898 xhci_op_write_4(sc, port, v); 2899 break; 2900 case UHF_PORT_U2_TIMEOUT: 2901 if (USB_IS_SS(xhci_xspeed2speed(XHCI_PS_SPEED_GET(v)))){ 2902 return -1; 2903 } 2904 port = XHCI_PORTPMSC(index); 2905 v = xhci_op_read_4(sc, port); 2906 v &= ~XHCI_PM3_U2TO_SET(0xff); 2907 v |= XHCI_PM3_U2TO_SET(optval); 2908 xhci_op_write_4(sc, port, v); 2909 break; 2910 default: 2911 return -1; 2912 } 2913 } 2914 break; 2915 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2916 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2917 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2918 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2919 break; 2920 default: 2921 /* default from usbroothub */ 2922 return buflen; 2923 } 2924 2925 return totlen; 2926 } 2927 2928 /* root hub interrupt */ 2929 2930 static usbd_status 2931 xhci_root_intr_transfer(struct usbd_xfer *xfer) 2932 { 2933 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2934 usbd_status err; 2935 2936 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2937 2938 /* Insert last in queue. */ 2939 mutex_enter(&sc->sc_lock); 2940 err = usb_insert_transfer(xfer); 2941 mutex_exit(&sc->sc_lock); 2942 if (err) 2943 return err; 2944 2945 /* Pipe isn't running, start first */ 2946 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2947 } 2948 2949 /* Wait for roothub port status/change */ 2950 static usbd_status 2951 xhci_root_intr_start(struct usbd_xfer *xfer) 2952 { 2953 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2954 2955 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2956 2957 if (sc->sc_dying) 2958 return USBD_IOERROR; 2959 2960 mutex_enter(&sc->sc_lock); 2961 sc->sc_intrxfer = xfer; 2962 mutex_exit(&sc->sc_lock); 2963 2964 return USBD_IN_PROGRESS; 2965 } 2966 2967 static void 2968 xhci_root_intr_abort(struct usbd_xfer *xfer) 2969 { 2970 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2971 2972 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2973 2974 KASSERT(mutex_owned(&sc->sc_lock)); 2975 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2976 2977 sc->sc_intrxfer = NULL; 2978 2979 xfer->ux_status = USBD_CANCELLED; 2980 usb_transfer_complete(xfer); 2981 } 2982 2983 static void 2984 xhci_root_intr_close(struct usbd_pipe *pipe) 2985 { 2986 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 2987 2988 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2989 2990 KASSERT(mutex_owned(&sc->sc_lock)); 2991 2992 sc->sc_intrxfer = NULL; 2993 } 2994 2995 static void 2996 xhci_root_intr_done(struct usbd_xfer *xfer) 2997 { 2998 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2999 3000 xfer->ux_hcpriv = NULL; 3001 } 3002 3003 /* -------------- */ 3004 /* device control */ 3005 3006 static usbd_status 3007 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3008 { 3009 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3010 usbd_status err; 3011 3012 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3013 3014 /* Insert last in queue. */ 3015 mutex_enter(&sc->sc_lock); 3016 err = usb_insert_transfer(xfer); 3017 mutex_exit(&sc->sc_lock); 3018 if (err) 3019 return err; 3020 3021 /* Pipe isn't running, start first */ 3022 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3023 } 3024 3025 static usbd_status 3026 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3027 { 3028 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3029 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3030 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3031 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3032 struct xhci_xfer * const xx = (void *)xfer; 3033 usb_device_request_t * const req = &xfer->ux_request; 3034 const bool isread = UT_GET_DIR(req->bmRequestType) == UT_READ; 3035 const uint32_t len = UGETW(req->wLength); 3036 usb_dma_t * const dma = &xfer->ux_dmabuf; 3037 uint64_t parameter; 3038 uint32_t status; 3039 uint32_t control; 3040 u_int i; 3041 3042 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3043 DPRINTFN(12, "req: %04x %04x %04x %04x", 3044 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3045 UGETW(req->wIndex), UGETW(req->wLength)); 3046 3047 /* XXX */ 3048 if (tr->is_halted) { 3049 DPRINTFN(1, "ctrl xfer %p halted: slot %u dci %u", 3050 xfer, xs->xs_idx, dci, 0); 3051 xhci_reset_endpoint(xfer->ux_pipe); 3052 tr->is_halted = false; 3053 xhci_set_dequeue(xfer->ux_pipe); 3054 } 3055 3056 /* we rely on the bottom bits for extra info */ 3057 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 3058 3059 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3060 3061 i = 0; 3062 3063 /* setup phase */ 3064 memcpy(¶meter, req, sizeof(*req)); 3065 parameter = le64toh(parameter); 3066 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3067 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3068 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3069 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3070 XHCI_TRB_3_IDT_BIT; 3071 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3072 3073 if (len == 0) 3074 goto no_data; 3075 3076 /* data phase */ 3077 parameter = DMAADDR(dma, 0); 3078 KASSERT(len <= 0x10000); 3079 status = XHCI_TRB_2_IRQ_SET(0) | 3080 XHCI_TRB_2_TDSZ_SET(1) | 3081 XHCI_TRB_2_BYTES_SET(len); 3082 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3083 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3084 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3085 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3086 3087 parameter = (uintptr_t)xfer | 0x3; 3088 status = XHCI_TRB_2_IRQ_SET(0); 3089 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3090 XHCI_TRB_3_IOC_BIT; 3091 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3092 3093 no_data: 3094 parameter = 0; 3095 status = XHCI_TRB_2_IRQ_SET(0); 3096 /* the status stage has inverted direction */ 3097 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3098 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3099 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3100 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3101 3102 parameter = (uintptr_t)xfer | 0x0; 3103 status = XHCI_TRB_2_IRQ_SET(0); 3104 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3105 XHCI_TRB_3_IOC_BIT; 3106 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3107 3108 mutex_enter(&tr->xr_lock); 3109 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3110 mutex_exit(&tr->xr_lock); 3111 3112 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3113 3114 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3115 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3116 xhci_timeout, xfer); 3117 } 3118 3119 if (sc->sc_bus.ub_usepolling) { 3120 DPRINTFN(1, "polling", 0, 0, 0, 0); 3121 //xhci_waitintr(sc, xfer); 3122 } 3123 3124 return USBD_IN_PROGRESS; 3125 } 3126 3127 static void 3128 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3129 { 3130 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3131 3132 callout_stop(&xfer->ux_callout); /* XXX wrong place */ 3133 3134 } 3135 3136 static void 3137 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3138 { 3139 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3140 3141 xhci_abort_xfer(xfer, USBD_CANCELLED); 3142 } 3143 3144 static void 3145 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3146 { 3147 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3148 3149 (void)xhci_close_pipe(pipe); 3150 } 3151 3152 /* ------------------ */ 3153 /* device isochronous */ 3154 3155 /* ----------- */ 3156 /* device bulk */ 3157 3158 static usbd_status 3159 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3160 { 3161 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3162 usbd_status err; 3163 3164 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3165 3166 /* Insert last in queue. */ 3167 mutex_enter(&sc->sc_lock); 3168 err = usb_insert_transfer(xfer); 3169 mutex_exit(&sc->sc_lock); 3170 if (err) 3171 return err; 3172 3173 /* 3174 * Pipe isn't running (otherwise err would be USBD_INPROG), 3175 * so start it first. 3176 */ 3177 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3178 } 3179 3180 static usbd_status 3181 xhci_device_bulk_start(struct usbd_xfer *xfer) 3182 { 3183 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3184 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3185 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3186 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3187 struct xhci_xfer * const xx = (void *)xfer; 3188 const uint32_t len = xfer->ux_length; 3189 usb_dma_t * const dma = &xfer->ux_dmabuf; 3190 uint64_t parameter; 3191 uint32_t status; 3192 uint32_t control; 3193 u_int i = 0; 3194 3195 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3196 3197 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3198 3199 if (sc->sc_dying) 3200 return USBD_IOERROR; 3201 3202 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3203 3204 parameter = DMAADDR(dma, 0); 3205 /* 3206 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3207 * If the user supplied buffer crosses such a boundary then 2 3208 * (or more) TRB should be used. 3209 * If multiple TRB are used the td_size field must be set correctly. 3210 * For v1.0 devices (like ivy bridge) this is the number of usb data 3211 * blocks needed to complete the transfer. 3212 * Setting it to 1 in the last TRB causes an extra zero-length 3213 * data block be sent. 3214 * The earlier documentation differs, I don't know how it behaves. 3215 */ 3216 KASSERT(len <= 0x10000); 3217 status = XHCI_TRB_2_IRQ_SET(0) | 3218 XHCI_TRB_2_TDSZ_SET(1) | 3219 XHCI_TRB_2_BYTES_SET(len); 3220 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3221 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3222 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3223 3224 mutex_enter(&tr->xr_lock); 3225 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3226 mutex_exit(&tr->xr_lock); 3227 3228 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3229 3230 if (sc->sc_bus.ub_usepolling) { 3231 DPRINTFN(1, "polling", 0, 0, 0, 0); 3232 //xhci_waitintr(sc, xfer); 3233 } 3234 3235 return USBD_IN_PROGRESS; 3236 } 3237 3238 static void 3239 xhci_device_bulk_done(struct usbd_xfer *xfer) 3240 { 3241 #ifdef USB_DEBUG 3242 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3243 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3244 #endif 3245 const u_int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3246 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3247 3248 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3249 3250 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3251 3252 callout_stop(&xfer->ux_callout); /* XXX wrong place */ 3253 3254 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3255 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3256 } 3257 3258 static void 3259 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3260 { 3261 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3262 3263 xhci_abort_xfer(xfer, USBD_CANCELLED); 3264 } 3265 3266 static void 3267 xhci_device_bulk_close(struct usbd_pipe *pipe) 3268 { 3269 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3270 3271 (void)xhci_close_pipe(pipe); 3272 } 3273 3274 /* ---------------- */ 3275 /* device interrupt */ 3276 3277 static usbd_status 3278 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3279 { 3280 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3281 usbd_status err; 3282 3283 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3284 3285 /* Insert last in queue. */ 3286 mutex_enter(&sc->sc_lock); 3287 err = usb_insert_transfer(xfer); 3288 mutex_exit(&sc->sc_lock); 3289 if (err) 3290 return err; 3291 3292 /* 3293 * Pipe isn't running (otherwise err would be USBD_INPROG), 3294 * so start it first. 3295 */ 3296 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3297 } 3298 3299 static usbd_status 3300 xhci_device_intr_start(struct usbd_xfer *xfer) 3301 { 3302 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3303 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3304 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3305 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3306 struct xhci_xfer * const xx = (void *)xfer; 3307 const uint32_t len = xfer->ux_length; 3308 usb_dma_t * const dma = &xfer->ux_dmabuf; 3309 uint64_t parameter; 3310 uint32_t status; 3311 uint32_t control; 3312 u_int i = 0; 3313 3314 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3315 3316 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3317 3318 if (sc->sc_dying) 3319 return USBD_IOERROR; 3320 3321 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3322 3323 parameter = DMAADDR(dma, 0); 3324 KASSERT(len <= 0x10000); 3325 status = XHCI_TRB_2_IRQ_SET(0) | 3326 XHCI_TRB_2_TDSZ_SET(1) | 3327 XHCI_TRB_2_BYTES_SET(len); 3328 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3329 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3330 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3331 3332 mutex_enter(&tr->xr_lock); 3333 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3334 mutex_exit(&tr->xr_lock); 3335 3336 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3337 3338 if (sc->sc_bus.ub_usepolling) { 3339 DPRINTFN(1, "polling", 0, 0, 0, 0); 3340 //xhci_waitintr(sc, xfer); 3341 } 3342 3343 return USBD_IN_PROGRESS; 3344 } 3345 3346 static void 3347 xhci_device_intr_done(struct usbd_xfer *xfer) 3348 { 3349 struct xhci_softc * const sc __diagused = 3350 xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3351 #ifdef USB_DEBUG 3352 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3353 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3354 #endif 3355 const u_int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3356 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3357 3358 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3359 3360 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3361 3362 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3363 3364 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3365 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3366 3367 #if 0 3368 device_printf(sc->sc_dev, ""); 3369 for (size_t i = 0; i < xfer->ux_length; i++) { 3370 printf(" %02x", ((uint8_t const *)xfer->ux_buffer)[i]); 3371 } 3372 printf("\n"); 3373 #endif 3374 3375 if (xfer->ux_pipe->up_repeat) { 3376 xfer->ux_status = xhci_device_intr_start(xfer); 3377 } else { 3378 callout_stop(&xfer->ux_callout); /* XXX */ 3379 } 3380 3381 } 3382 3383 static void 3384 xhci_device_intr_abort(struct usbd_xfer *xfer) 3385 { 3386 struct xhci_softc * const sc __diagused = 3387 xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3388 3389 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3390 3391 KASSERT(mutex_owned(&sc->sc_lock)); 3392 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3393 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3394 xhci_abort_xfer(xfer, USBD_CANCELLED); 3395 } 3396 3397 static void 3398 xhci_device_intr_close(struct usbd_pipe *pipe) 3399 { 3400 //struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 3401 3402 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3403 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3404 3405 (void)xhci_close_pipe(pipe); 3406 } 3407 3408 /* ------------ */ 3409 3410 static void 3411 xhci_timeout(void *addr) 3412 { 3413 struct xhci_xfer * const xx = addr; 3414 struct usbd_xfer * const xfer = &xx->xx_xfer; 3415 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3416 3417 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3418 3419 if (sc->sc_dying) { 3420 return; 3421 } 3422 3423 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 3424 USB_TASKQ_MPSAFE); 3425 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 3426 USB_TASKQ_HC); 3427 } 3428 3429 static void 3430 xhci_timeout_task(void *addr) 3431 { 3432 struct usbd_xfer * const xfer = addr; 3433 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3434 3435 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3436 3437 mutex_enter(&sc->sc_lock); 3438 #if 0 3439 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3440 #else 3441 xfer->ux_status = USBD_TIMEOUT; 3442 usb_transfer_complete(xfer); 3443 #endif 3444 mutex_exit(&sc->sc_lock); 3445 } 3446
Indexes created Wed Oct 01 15:09:59 GMT 2025