xhci.c revision 1.28.2.31
1 /* $NetBSD: xhci.c,v 1.28.2.31 2015/06/26 15:39:55 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 3.1 specification 31 * http://www.usb.org/developers/docs/usb_31_040315.zip 32 * USB rev 2.0 specification 33 * http://www.usb.org/developers/docs/usb20_docs/usb_20_031815.zip 34 * xHCI rev 1.1 specification 35 * http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.28.2.31 2015/06/26 15:39:55 skrll Exp $"); 40 41 #include "opt_usb.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static int xhci_intr1(struct xhci_softc * const); 129 static void xhci_softintr(void *); 130 static void xhci_poll(struct usbd_bus *); 131 static struct usbd_xfer *xhci_allocx(struct usbd_bus *); 132 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 133 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 134 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 135 struct usbd_port *); 136 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 137 void *, int); 138 139 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 140 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 141 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 143 144 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 145 146 static usbd_status xhci_do_command(struct xhci_softc * const, 147 struct xhci_trb * const, int); 148 static usbd_status xhci_do_command1(struct xhci_softc * const, 149 struct xhci_trb * const, int, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t, int, int); 153 static usbd_status xhci_enable_slot(struct xhci_softc * const, 154 uint8_t * const); 155 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 156 static usbd_status xhci_address_device(struct xhci_softc * const, 157 uint64_t, uint8_t, bool); 158 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 159 struct xhci_slot * const, u_int); 160 static usbd_status xhci_ring_init(struct xhci_softc * const, 161 struct xhci_ring * const, size_t, size_t); 162 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 163 164 static void xhci_noop(struct usbd_pipe *); 165 166 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 167 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 168 static void xhci_root_intr_abort(struct usbd_xfer *); 169 static void xhci_root_intr_close(struct usbd_pipe *); 170 static void xhci_root_intr_done(struct usbd_xfer *); 171 172 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 173 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 174 static void xhci_device_ctrl_abort(struct usbd_xfer *); 175 static void xhci_device_ctrl_close(struct usbd_pipe *); 176 static void xhci_device_ctrl_done(struct usbd_xfer *); 177 178 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 179 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 180 static void xhci_device_intr_abort(struct usbd_xfer *); 181 static void xhci_device_intr_close(struct usbd_pipe *); 182 static void xhci_device_intr_done(struct usbd_xfer *); 183 184 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 185 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 186 static void xhci_device_bulk_abort(struct usbd_xfer *); 187 static void xhci_device_bulk_close(struct usbd_pipe *); 188 static void xhci_device_bulk_done(struct usbd_xfer *); 189 190 static void xhci_timeout(void *); 191 static void xhci_timeout_task(void *); 192 193 static const struct usbd_bus_methods xhci_bus_methods = { 194 .ubm_open = xhci_open, 195 .ubm_softint = xhci_softintr, 196 .ubm_dopoll = xhci_poll, 197 .ubm_allocx = xhci_allocx, 198 .ubm_freex = xhci_freex, 199 .ubm_getlock = xhci_get_lock, 200 .ubm_newdev = xhci_new_device, 201 .ubm_rhctrl = xhci_roothub_ctrl, 202 }; 203 204 static const struct usbd_pipe_methods xhci_root_intr_methods = { 205 .upm_transfer = xhci_root_intr_transfer, 206 .upm_start = xhci_root_intr_start, 207 .upm_abort = xhci_root_intr_abort, 208 .upm_close = xhci_root_intr_close, 209 .upm_cleartoggle = xhci_noop, 210 .upm_done = xhci_root_intr_done, 211 }; 212 213 214 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 215 .upm_transfer = xhci_device_ctrl_transfer, 216 .upm_start = xhci_device_ctrl_start, 217 .upm_abort = xhci_device_ctrl_abort, 218 .upm_close = xhci_device_ctrl_close, 219 .upm_cleartoggle = xhci_noop, 220 .upm_done = xhci_device_ctrl_done, 221 }; 222 223 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 224 .upm_cleartoggle = xhci_noop, 225 }; 226 227 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 228 .upm_transfer = xhci_device_bulk_transfer, 229 .upm_start = xhci_device_bulk_start, 230 .upm_abort = xhci_device_bulk_abort, 231 .upm_close = xhci_device_bulk_close, 232 .upm_cleartoggle = xhci_noop, 233 .upm_done = xhci_device_bulk_done, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_intr_methods = { 237 .upm_transfer = xhci_device_intr_transfer, 238 .upm_start = xhci_device_intr_start, 239 .upm_abort = xhci_device_intr_abort, 240 .upm_close = xhci_device_intr_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_intr_done, 243 }; 244 245 static inline uint32_t 246 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 247 { 248 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 249 } 250 251 static inline uint32_t 252 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 253 { 254 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 255 } 256 257 static inline void 258 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 259 uint32_t value) 260 { 261 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 262 } 263 264 #if 0 /* unused */ 265 static inline void 266 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 267 uint32_t value) 268 { 269 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 270 } 271 #endif /* unused */ 272 273 static inline uint32_t 274 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 275 { 276 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 277 } 278 279 static inline uint32_t 280 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 281 { 282 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 283 } 284 285 static inline void 286 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 287 uint32_t value) 288 { 289 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 290 } 291 292 #if 0 /* unused */ 293 static inline uint64_t 294 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 295 { 296 uint64_t value; 297 298 if (sc->sc_ac64) { 299 #ifdef XHCI_USE_BUS_SPACE_8 300 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 301 #else 302 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 303 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 304 offset + 4) << 32; 305 #endif 306 } else { 307 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 308 } 309 310 return value; 311 } 312 #endif /* unused */ 313 314 static inline void 315 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 316 uint64_t value) 317 { 318 if (sc->sc_ac64) { 319 #ifdef XHCI_USE_BUS_SPACE_8 320 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 321 #else 322 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 323 (value >> 0) & 0xffffffff); 324 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 325 (value >> 32) & 0xffffffff); 326 #endif 327 } else { 328 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 329 } 330 } 331 332 static inline uint32_t 333 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 334 { 335 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 336 } 337 338 static inline void 339 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 340 uint32_t value) 341 { 342 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 343 } 344 345 #if 0 /* unused */ 346 static inline uint64_t 347 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 348 { 349 uint64_t value; 350 351 if (sc->sc_ac64) { 352 #ifdef XHCI_USE_BUS_SPACE_8 353 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 354 #else 355 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 356 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 357 offset + 4) << 32; 358 #endif 359 } else { 360 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 361 } 362 363 return value; 364 } 365 #endif /* unused */ 366 367 static inline void 368 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 369 uint64_t value) 370 { 371 if (sc->sc_ac64) { 372 #ifdef XHCI_USE_BUS_SPACE_8 373 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 374 #else 375 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 376 (value >> 0) & 0xffffffff); 377 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 378 (value >> 32) & 0xffffffff); 379 #endif 380 } else { 381 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 382 } 383 } 384 385 #if 0 /* unused */ 386 static inline uint32_t 387 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 388 { 389 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 390 } 391 #endif /* unused */ 392 393 static inline void 394 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 395 uint32_t value) 396 { 397 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 398 } 399 400 /* --- */ 401 402 static inline uint8_t 403 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 404 { 405 u_int eptype = 0; 406 407 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 408 case UE_CONTROL: 409 eptype = 0x0; 410 break; 411 case UE_ISOCHRONOUS: 412 eptype = 0x1; 413 break; 414 case UE_BULK: 415 eptype = 0x2; 416 break; 417 case UE_INTERRUPT: 418 eptype = 0x3; 419 break; 420 } 421 422 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 423 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 424 return eptype | 0x4; 425 else 426 return eptype; 427 } 428 429 static u_int 430 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 431 { 432 /* xHCI 1.0 section 4.5.1 */ 433 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 434 u_int in = 0; 435 436 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 437 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 438 in = 1; 439 440 return epaddr * 2 + in; 441 } 442 443 static inline u_int 444 xhci_dci_to_ici(const u_int i) 445 { 446 return i + 1; 447 } 448 449 static inline void * 450 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 451 const u_int dci) 452 { 453 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 454 } 455 456 #if 0 /* unused */ 457 static inline bus_addr_t 458 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 459 const u_int dci) 460 { 461 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 462 } 463 #endif /* unused */ 464 465 static inline void * 466 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 467 const u_int ici) 468 { 469 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 470 } 471 472 static inline bus_addr_t 473 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline struct xhci_trb * 480 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 481 { 482 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 483 } 484 485 static inline bus_addr_t 486 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 487 { 488 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 489 } 490 491 static inline void 492 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 493 uint32_t control) 494 { 495 trb->trb_0 = parameter; 496 trb->trb_2 = status; 497 trb->trb_3 = control; 498 } 499 500 /* --- */ 501 502 void 503 xhci_childdet(device_t self, device_t child) 504 { 505 struct xhci_softc * const sc = device_private(self); 506 507 KASSERT(sc->sc_child == child); 508 if (child == sc->sc_child) 509 sc->sc_child = NULL; 510 } 511 512 int 513 xhci_detach(struct xhci_softc *sc, int flags) 514 { 515 int rv = 0; 516 517 if (sc->sc_child != NULL) 518 rv = config_detach(sc->sc_child, flags); 519 520 if (rv != 0) 521 return rv; 522 523 /* XXX unconfigure/free slots */ 524 525 /* verify: */ 526 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 527 xhci_op_write_4(sc, XHCI_USBCMD, 0); 528 /* do we need to wait for stop? */ 529 530 xhci_op_write_8(sc, XHCI_CRCR, 0); 531 xhci_ring_free(sc, &sc->sc_cr); 532 cv_destroy(&sc->sc_command_cv); 533 534 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 535 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 536 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 537 xhci_ring_free(sc, &sc->sc_er); 538 539 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 540 541 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 542 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 543 544 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 545 546 mutex_destroy(&sc->sc_lock); 547 mutex_destroy(&sc->sc_intr_lock); 548 cv_destroy(&sc->sc_softwake_cv); 549 550 pool_cache_destroy(sc->sc_xferpool); 551 552 return rv; 553 } 554 555 int 556 xhci_activate(device_t self, enum devact act) 557 { 558 struct xhci_softc * const sc = device_private(self); 559 560 switch (act) { 561 case DVACT_DEACTIVATE: 562 sc->sc_dying = true; 563 return 0; 564 default: 565 return EOPNOTSUPP; 566 } 567 } 568 569 bool 570 xhci_suspend(device_t dv, const pmf_qual_t *qual) 571 { 572 return false; 573 } 574 575 bool 576 xhci_resume(device_t dv, const pmf_qual_t *qual) 577 { 578 return false; 579 } 580 581 bool 582 xhci_shutdown(device_t self, int flags) 583 { 584 return false; 585 } 586 587 588 static void 589 hexdump(const char *msg, const void *base, size_t len) 590 { 591 #if 0 592 size_t cnt; 593 const uint32_t *p; 594 extern paddr_t vtophys(vaddr_t); 595 596 p = base; 597 cnt = 0; 598 599 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 600 (void *)vtophys((vaddr_t)base)); 601 602 while (cnt < len) { 603 if (cnt % 16 == 0) 604 printf("%p: ", p); 605 else if (cnt % 8 == 0) 606 printf(" |"); 607 printf(" %08x", *p++); 608 cnt += 4; 609 if (cnt % 16 == 0) 610 printf("\n"); 611 } 612 #endif 613 } 614 615 616 int 617 xhci_init(struct xhci_softc *sc) 618 { 619 bus_size_t bsz; 620 uint32_t cap, hcs1, hcs2, hcc, dboff, rtsoff; 621 uint32_t ecp, ecr; 622 uint32_t usbcmd, usbsts, pagesize, config; 623 int i; 624 uint16_t hciversion; 625 uint8_t caplength; 626 627 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 628 629 /* XXX Low/Full/High speeds for now */ 630 sc->sc_bus.ub_revision = USBREV_2_0; 631 sc->sc_bus.ub_usedma = true; 632 633 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 634 caplength = XHCI_CAP_CAPLENGTH(cap); 635 hciversion = XHCI_CAP_HCIVERSION(cap); 636 637 if ((hciversion < 0x0096) || (hciversion > 0x0100)) { 638 aprint_normal_dev(sc->sc_dev, 639 "xHCI version %x.%x not known to be supported\n", 640 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 641 } else { 642 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 643 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 644 } 645 646 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 647 &sc->sc_cbh) != 0) { 648 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 649 return ENOMEM; 650 } 651 652 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 653 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 654 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 655 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 656 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 657 (void)xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 658 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 659 660 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 661 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 662 aprint_debug_dev(sc->sc_dev, "ac64 %d ctxsz %d\n", sc->sc_ac64, 663 sc->sc_ctxsz); 664 665 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 666 ecp = XHCI_HCC_XECP(hcc) * 4; 667 while (ecp != 0) { 668 ecr = xhci_read_4(sc, ecp); 669 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 670 switch (XHCI_XECP_ID(ecr)) { 671 case XHCI_ID_PROTOCOLS: { 672 uint32_t w0, w4, w8; 673 uint16_t w2; 674 w0 = xhci_read_4(sc, ecp + 0); 675 w2 = (w0 >> 16) & 0xffff; 676 w4 = xhci_read_4(sc, ecp + 4); 677 w8 = xhci_read_4(sc, ecp + 8); 678 aprint_debug_dev(sc->sc_dev, "SP: %08x %08x %08x\n", 679 w0, w4, w8); 680 if (w4 == 0x20425355 && w2 == 0x0300) { 681 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 682 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 683 } 684 if (w4 == 0x20425355 && w2 == 0x0200) { 685 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 686 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 687 } 688 break; 689 } 690 case XHCI_ID_USB_LEGACY: { 691 uint8_t bios_sem; 692 693 /* Take host controller from BIOS */ 694 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 695 if (bios_sem) { 696 /* sets xHCI to be owned by OS */ 697 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 698 aprint_debug( 699 "waiting for BIOS to give up control\n"); 700 for (i = 0; i < 5000; i++) { 701 bios_sem = xhci_read_1(sc, ecp + 702 XHCI_XECP_BIOS_SEM); 703 if (bios_sem == 0) 704 break; 705 DELAY(1000); 706 } 707 if (bios_sem) 708 printf("timed out waiting for BIOS\n"); 709 } 710 break; 711 } 712 default: 713 break; 714 } 715 ecr = xhci_read_4(sc, ecp); 716 if (XHCI_XECP_NEXT(ecr) == 0) { 717 ecp = 0; 718 } else { 719 ecp += XHCI_XECP_NEXT(ecr) * 4; 720 } 721 } 722 723 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 724 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 725 &sc->sc_obh) != 0) { 726 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 727 return ENOMEM; 728 } 729 730 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 731 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 732 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 733 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 734 return ENOMEM; 735 } 736 737 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 738 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 739 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 740 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 741 return ENOMEM; 742 } 743 744 for (i = 0; i < 100; i++) { 745 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 746 if ((usbsts & XHCI_STS_CNR) == 0) 747 break; 748 usb_delay_ms(&sc->sc_bus, 1); 749 } 750 if (i >= 100) 751 return EIO; 752 753 usbcmd = 0; 754 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 755 usb_delay_ms(&sc->sc_bus, 1); 756 757 usbcmd = XHCI_CMD_HCRST; 758 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 759 for (i = 0; i < 100; i++) { 760 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 761 if ((usbcmd & XHCI_CMD_HCRST) == 0) 762 break; 763 usb_delay_ms(&sc->sc_bus, 1); 764 } 765 if (i >= 100) 766 return EIO; 767 768 for (i = 0; i < 100; i++) { 769 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 770 if ((usbsts & XHCI_STS_CNR) == 0) 771 break; 772 usb_delay_ms(&sc->sc_bus, 1); 773 } 774 if (i >= 100) 775 return EIO; 776 777 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 778 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 779 pagesize = ffs(pagesize); 780 if (pagesize == 0) 781 return EIO; 782 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 783 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 784 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 785 (uint32_t)sc->sc_maxslots); 786 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 787 788 usbd_status err; 789 790 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 791 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 792 if (sc->sc_maxspbuf != 0) { 793 err = usb_allocmem(&sc->sc_bus, 794 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 795 &sc->sc_spbufarray_dma); 796 if (err) 797 return err; 798 799 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * sc->sc_maxspbuf, KM_SLEEP); 800 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 801 for (i = 0; i < sc->sc_maxspbuf; i++) { 802 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 803 /* allocate contexts */ 804 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 805 sc->sc_pgsz, dma); 806 if (err) 807 return err; 808 spbufarray[i] = htole64(DMAADDR(dma, 0)); 809 usb_syncmem(dma, 0, sc->sc_pgsz, 810 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 811 } 812 813 usb_syncmem(&sc->sc_spbufarray_dma, 0, 814 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 815 } 816 817 config = xhci_op_read_4(sc, XHCI_CONFIG); 818 config &= ~0xFF; 819 config |= sc->sc_maxslots & 0xFF; 820 xhci_op_write_4(sc, XHCI_CONFIG, config); 821 822 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 823 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 824 if (err) { 825 aprint_error_dev(sc->sc_dev, "command ring init fail\n"); 826 return err; 827 } 828 829 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 830 XHCI_EVENT_RING_SEGMENTS_ALIGN); 831 if (err) { 832 aprint_error_dev(sc->sc_dev, "event ring init fail\n"); 833 return err; 834 } 835 836 usb_dma_t *dma; 837 size_t size; 838 size_t align; 839 840 dma = &sc->sc_eventst_dma; 841 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 842 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 843 KASSERT(size <= (512 * 1024)); 844 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 845 err = usb_allocmem(&sc->sc_bus, size, align, dma); 846 847 memset(KERNADDR(dma, 0), 0, size); 848 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 849 aprint_debug_dev(sc->sc_dev, "eventst: %s %016jx %p %zx\n", 850 usbd_errstr(err), 851 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 852 KERNADDR(&sc->sc_eventst_dma, 0), 853 sc->sc_eventst_dma.udma_block->size); 854 855 dma = &sc->sc_dcbaa_dma; 856 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 857 KASSERT(size <= 2048); 858 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 859 err = usb_allocmem(&sc->sc_bus, size, align, dma); 860 861 memset(KERNADDR(dma, 0), 0, size); 862 if (sc->sc_maxspbuf != 0) { 863 /* 864 * DCBA entry 0 hold the scratchbuf array pointer. 865 */ 866 *(uint64_t *)KERNADDR(dma, 0) = 867 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 868 } 869 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 870 aprint_debug_dev(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n", 871 usbd_errstr(err), 872 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 873 KERNADDR(&sc->sc_dcbaa_dma, 0), 874 sc->sc_dcbaa_dma.udma_block->size); 875 876 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 877 KM_SLEEP); 878 879 cv_init(&sc->sc_command_cv, "xhcicmd"); 880 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 881 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 882 cv_init(&sc->sc_softwake_cv, "xhciab"); 883 884 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 885 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 886 887 /* Set up the bus struct. */ 888 sc->sc_bus.ub_methods = &xhci_bus_methods; 889 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 890 891 struct xhci_erste *erst; 892 erst = KERNADDR(&sc->sc_eventst_dma, 0); 893 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 894 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 895 erst[0].erste_3 = htole32(0); 896 usb_syncmem(&sc->sc_eventst_dma, 0, 897 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 898 899 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 900 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 901 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 902 XHCI_ERDP_LO_BUSY); 903 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 904 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 905 sc->sc_cr.xr_cs); 906 907 #if 0 908 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 909 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 910 #endif 911 912 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 913 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 914 /* Intel xhci needs interrupt rate moderated. */ 915 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 916 else 917 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 918 aprint_debug_dev(sc->sc_dev, "setting IMOD %u\n", 919 xhci_rt_read_4(sc, XHCI_IMOD(0))); 920 921 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 922 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 923 xhci_op_read_4(sc, XHCI_USBCMD)); 924 925 return USBD_NORMAL_COMPLETION; 926 } 927 928 int 929 xhci_intr(void *v) 930 { 931 struct xhci_softc * const sc = v; 932 int ret = 0; 933 934 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 935 936 if (sc == NULL) 937 return 0; 938 939 mutex_spin_enter(&sc->sc_intr_lock); 940 941 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 942 goto done; 943 944 /* If we get an interrupt while polling, then just ignore it. */ 945 if (sc->sc_bus.ub_usepolling) { 946 #ifdef DIAGNOSTIC 947 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 948 #endif 949 goto done; 950 } 951 952 ret = xhci_intr1(sc); 953 done: 954 mutex_spin_exit(&sc->sc_intr_lock); 955 return ret; 956 } 957 958 int 959 xhci_intr1(struct xhci_softc * const sc) 960 { 961 uint32_t usbsts; 962 uint32_t iman; 963 964 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 965 966 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 967 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 968 #if 0 969 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 970 return 0; 971 } 972 #endif 973 xhci_op_write_4(sc, XHCI_USBSTS, 974 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 975 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 976 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 977 978 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 979 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 980 981 if (!(sc->sc_quirks & XHCI_QUIRK_FORCE_INTR)) { 982 if ((iman & XHCI_IMAN_INTR_PEND) == 0) { 983 return 0; 984 } 985 } 986 987 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 988 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 989 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 990 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 991 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 992 993 usb_schedsoftintr(&sc->sc_bus); 994 995 return 1; 996 } 997 998 /* 999 * 3 port speed types used in USB stack 1000 * 1001 * usbdi speed 1002 * definition: USB_SPEED_* in usb.h 1003 * They are used in struct usbd_device in USB stack. 1004 * ioctl interface uses these values too. 1005 * port_status speed 1006 * definition: UPS_*_SPEED in usb.h 1007 * They are used in usb_port_status_t and valid only for USB 2.0. 1008 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1009 * of usb_port_status_ext_t indicates port speed. 1010 * Note that some 3.0 values overlap with 2.0 values. 1011 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1012 * means UPS_LOW_SPEED in HS.) 1013 * port status returned from hub also uses these values. 1014 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1015 * or more. 1016 * xspeed: 1017 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1018 * They are used in only slot context and PORTSC reg of xhci. 1019 * The difference between usbdi speed and xspeed is 1020 * that FS and LS values are swapped. 1021 */ 1022 1023 /* convert usbdi speed to xspeed */ 1024 static int 1025 xhci_speed2xspeed(int speed) 1026 { 1027 switch (speed) { 1028 case USB_SPEED_LOW: return 2; 1029 case USB_SPEED_FULL: return 1; 1030 default: return speed; 1031 } 1032 } 1033 1034 /* convert xspeed to usbdi speed */ 1035 static int 1036 xhci_xspeed2speed(int xspeed) 1037 { 1038 switch (xspeed) { 1039 case 1: return USB_SPEED_FULL; 1040 case 2: return USB_SPEED_LOW; 1041 default: return xspeed; 1042 } 1043 } 1044 1045 /* convert xspeed to port status speed */ 1046 static int 1047 xhci_xspeed2psspeed(int xspeed) 1048 { 1049 switch (xspeed) { 1050 case 0: return 0; 1051 case 1: return UPS_FULL_SPEED; 1052 case 2: return UPS_LOW_SPEED; 1053 case 3: return UPS_HIGH_SPEED; 1054 default: return UPS_OTHER_SPEED; 1055 } 1056 } 1057 1058 /* construct slot context */ 1059 static void 1060 xhci_setup_sctx(struct usbd_device *dev, uint32_t *cp) 1061 { 1062 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 1063 int speed = dev->ud_speed; 1064 int tthubslot, ttportnum; 1065 bool ishub; 1066 bool usemtt; 1067 1068 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1069 1070 /* 6.2.2 */ 1071 /* 1072 * tthubslot: 1073 * This is the slot ID of parent HS hub 1074 * if LS/FS device is connected && connected through HS hub. 1075 * This is 0 if device is not LS/FS device || 1076 * parent hub is not HS hub || 1077 * attached to root hub. 1078 * ttportnum: 1079 * This is the downstream facing port of parent HS hub 1080 * if LS/FS device is connected. 1081 * This is 0 if device is not LS/FS device || 1082 * parent hub is not HS hub || 1083 * attached to root hub. 1084 */ 1085 if (dev->ud_myhsport != NULL && 1086 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1087 (dev->ud_myhub != NULL && 1088 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1089 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 1090 ttportnum = dev->ud_myhsport->up_portno; 1091 /* XXX addr == slot ? */ 1092 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 1093 } else { 1094 ttportnum = 0; 1095 tthubslot = 0; 1096 } 1097 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 1098 dev->ud_myhsport, ttportnum, tthubslot, 0); 1099 1100 /* ishub is valid after reading UDESC_DEVICE */ 1101 ishub = (dd->bDeviceClass == UDCLASS_HUB); 1102 1103 /* dev->ud_hub is valid after reading UDESC_HUB */ 1104 if (ishub && dev->ud_hub) { 1105 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 1106 1107 cp[1] |= htole32(XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts)); 1108 cp[2] |= htole32(XHCI_SCTX_2_TT_THINK_TIME_SET( 1109 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK))); 1110 DPRINTFN(4, "nports=%d ttt=%d", 1111 hd->bNbrPorts, XHCI_SCTX_2_TT_THINK_TIME_GET(cp[2]), 0, 0); 1112 } 1113 1114 #define IS_TTHUB(dd) \ 1115 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 1116 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 1117 1118 /* 1119 * MTT flag is set if 1120 * 1. this is HS hub && MTT is enabled 1121 * or 1122 * 2. this is not hub && this is LS or FS device && 1123 * MTT of parent HS hub (and its parent, too) is enabled 1124 */ 1125 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 1126 usemtt = true; 1127 else if (!ishub && 1128 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 1129 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1130 (dev->ud_myhub != NULL && 1131 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1132 dev->ud_myhsport != NULL && 1133 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 1134 usemtt = true; 1135 else 1136 usemtt = false; 1137 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 1138 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 1139 1140 cp[0] |= htole32( 1141 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)) | 1142 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 1143 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0) 1144 ); 1145 cp[1] |= htole32(0); 1146 cp[2] |= htole32( 1147 XHCI_SCTX_2_IRQ_TARGET_SET(0) | 1148 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 1149 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum) 1150 ); 1151 cp[3] |= htole32(0); 1152 } 1153 1154 /* 1155 * called 1156 * from xhci_open 1157 * from usbd_setup_pipe_flags 1158 * from usbd_open_pipe_ival 1159 */ 1160 static usbd_status 1161 xhci_configure_endpoint(struct usbd_pipe *pipe) 1162 { 1163 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1164 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1165 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1166 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1167 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1168 struct xhci_trb trb; 1169 usbd_status err; 1170 uint32_t *cp; 1171 uint32_t mps = UGETW(ed->wMaxPacketSize); 1172 uint32_t maxb = 0; 1173 int speed = pipe->up_dev->ud_speed; 1174 uint32_t ival = ed->bInterval; 1175 1176 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1177 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1178 xs->xs_idx, dci, ed->bEndpointAddress, ed->bmAttributes); 1179 1180 /* XXX ensure input context is available? */ 1181 1182 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1183 1184 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1185 cp[0] = htole32(0); 1186 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 1187 1188 /* set up input slot context */ 1189 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1190 xhci_setup_sctx(pipe->up_dev, cp); 1191 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1192 1193 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 1194 cp[0] = htole32( 1195 XHCI_EPCTX_0_EPSTATE_SET(0) | 1196 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 1197 XHCI_EPCTX_0_LSA_SET(0) 1198 ); 1199 cp[1] = htole32( 1200 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 1201 XHCI_EPCTX_1_MAXB_SET(0) 1202 ); 1203 if (xfertype != UE_ISOCHRONOUS) 1204 cp[1] |= htole32(XHCI_EPCTX_1_CERR_SET(3)); 1205 1206 if (USB_IS_SS(speed)) { 1207 usbd_desc_iter_t iter; 1208 const usb_cdc_descriptor_t *cdcd; 1209 const usb_endpoint_ss_comp_descriptor_t * esscd = NULL; 1210 uint8_t ep; 1211 1212 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc( 1213 pipe->up_dev, UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 1214 usb_desc_iter_init(pipe->up_dev, &iter); 1215 iter.cur = (const void *)cdcd; 1216 1217 /* find endpoint_ss_comp desc for ep of this pipe */ 1218 for(ep = 0;;) { 1219 cdcd = (const usb_cdc_descriptor_t *) 1220 usb_desc_iter_next(&iter); 1221 if (cdcd == NULL) 1222 break; 1223 if (ep == 0 && 1224 cdcd->bDescriptorType == UDESC_ENDPOINT) { 1225 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 1226 bEndpointAddress; 1227 if (UE_GET_ADDR(ep) == 1228 UE_GET_ADDR(ed->bEndpointAddress)) { 1229 cdcd = (const usb_cdc_descriptor_t *) 1230 usb_desc_iter_next(&iter); 1231 break; 1232 } 1233 ep = 0; 1234 } 1235 } 1236 if (cdcd != NULL && 1237 cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 1238 esscd = (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 1239 maxb = esscd->bMaxBurst; 1240 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1241 DPRINTFN(4, "setting SS MaxBurst %u", maxb, 0, 0, 0); 1242 } 1243 } 1244 if (speed == USB_SPEED_HIGH && 1245 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 1246 maxb = UE_GET_TRANS(UGETW(ed->wMaxPacketSize)); 1247 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1248 DPRINTFN(4, "setting HS MaxBurst %u", maxb, 0, 0, 0); 1249 } 1250 1251 switch (xfertype) { 1252 case UE_INTERRUPT: 1253 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1254 ival = pipe->up_interval; 1255 1256 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 1257 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 1258 int i; 1259 1260 /* 1261 * round ival down to "the nearest base 2 multiple of 1262 * bInterval * 8". 1263 * bInterval is at most 255 as its type is uByte. 1264 * 255(ms) = 2040(x 125us) < 2^11, so start with 11. 1265 */ 1266 for (i = 11; i > 0; i--) { 1267 if ((ival * 8) >= (1 << i)) 1268 break; 1269 } 1270 ival = i; 1271 } else { 1272 /* Interval = bInterval-1 for SS/HS */ 1273 ival--; 1274 } 1275 DPRINTFN(4, "ival %u", ival, 0, 0, 0); 1276 1277 if (USB_IS_SS(speed)) { 1278 if (maxb > 0) 1279 mps = 1024; 1280 } else { 1281 mps = mps ? mps : 8; 1282 } 1283 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1284 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1285 cp[4] = htole32( 1286 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) /* XXX */ 1287 ); 1288 break; 1289 case UE_CONTROL: 1290 if (USB_IS_SS(speed)) 1291 mps = 512; 1292 else 1293 mps = mps ? mps : 8; 1294 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1295 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(8)); /* XXX */ 1296 break; 1297 #ifdef notyet 1298 case UE_ISOCHRONOUS: 1299 if (speed == USB_SPEED_FULL) 1300 ival += 3; /* 1ms -> 125us */ 1301 ival--; 1302 DPRINTFN(4, "ival %u", ival, 0, 0, 0); 1303 1304 if (USB_IS_SS(speed)) { 1305 mps = 1024; 1306 } else { 1307 mps = mps ? mps : 1024; 1308 } 1309 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1310 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(1024)); /* XXX */ 1311 break; 1312 #endif 1313 default: 1314 if (USB_IS_SS(speed)) 1315 mps = 1024; 1316 else 1317 mps = mps ? mps : 512; 1318 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1319 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(1024)); /* XXX */ 1320 break; 1321 } 1322 *(uint64_t *)(&cp[2]) = htole64( 1323 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 1324 XHCI_EPCTX_2_DCS_SET(1)); 1325 1326 /* sync input contexts before they are read from memory */ 1327 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1328 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1329 sc->sc_ctxsz * 1); 1330 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1331 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1332 1333 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1334 trb.trb_2 = 0; 1335 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1336 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1337 1338 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1339 1340 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1341 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1342 sc->sc_ctxsz * 1); 1343 1344 return err; 1345 } 1346 1347 #if 0 1348 static usbd_status 1349 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1350 { 1351 #ifdef USB_DEBUG 1352 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1353 #endif 1354 1355 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1356 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1357 1358 return USBD_NORMAL_COMPLETION; 1359 } 1360 #endif 1361 1362 /* 4.6.8, 6.4.3.7 */ 1363 static usbd_status 1364 xhci_reset_endpoint(struct usbd_pipe *pipe) 1365 { 1366 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1367 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1368 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1369 struct xhci_trb trb; 1370 usbd_status err; 1371 1372 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1373 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1374 1375 KASSERT(!mutex_owned(&sc->sc_lock)); 1376 1377 trb.trb_0 = 0; 1378 trb.trb_2 = 0; 1379 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1380 XHCI_TRB_3_EP_SET(dci) | 1381 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1382 1383 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1384 1385 return err; 1386 } 1387 1388 /* 1389 * 4.6.9, 6.4.3.8 1390 * Stop execution of TDs on xfer ring. 1391 * Should be called with sc_lock held. 1392 */ 1393 static usbd_status 1394 xhci_stop_endpoint(struct usbd_pipe *pipe) 1395 { 1396 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1397 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1398 struct xhci_trb trb; 1399 usbd_status err; 1400 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1401 1402 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1403 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1404 1405 KASSERT(mutex_owned(&sc->sc_lock)); 1406 1407 trb.trb_0 = 0; 1408 trb.trb_2 = 0; 1409 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1410 XHCI_TRB_3_EP_SET(dci) | 1411 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1412 1413 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1414 1415 return err; 1416 } 1417 1418 /* 1419 * Set TR Dequeue Pointer. 1420 * xCHI 1.1 4.6.10 6.4.3.9 1421 * Purge all of the transfer requests on ring. 1422 * EPSTATE of endpoint must be ERROR or STOPPED, or CONTEXT_STATE error. 1423 */ 1424 static usbd_status 1425 xhci_set_dequeue(struct usbd_pipe *pipe) 1426 { 1427 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1428 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1429 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1430 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1431 struct xhci_trb trb; 1432 usbd_status err; 1433 1434 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1435 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1436 1437 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1438 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1439 BUS_DMASYNC_PREWRITE); 1440 1441 xr->xr_ep = 0; 1442 xr->xr_cs = 1; 1443 1444 /* set DCS */ 1445 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1446 trb.trb_2 = 0; 1447 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1448 XHCI_TRB_3_EP_SET(dci) | 1449 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1450 1451 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1452 1453 return err; 1454 } 1455 1456 /* 1457 * Open new pipe: called from usbd_setup_pipe_flags. 1458 * Fills methods of pipe. 1459 * If pipe is not for ep0, calls configure_endpoint. 1460 */ 1461 static usbd_status 1462 xhci_open(struct usbd_pipe *pipe) 1463 { 1464 struct usbd_device * const dev = pipe->up_dev; 1465 struct xhci_softc * const sc = dev->ud_bus->ub_hcpriv; 1466 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1467 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1468 1469 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1470 DPRINTFN(1, "addr %d depth %d port %d speed %d", 1471 dev->ud_addr, dev->ud_depth, dev->ud_powersrc->up_portno, 1472 dev->ud_speed); 1473 1474 if (sc->sc_dying) 1475 return USBD_IOERROR; 1476 1477 /* Root Hub */ 1478 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1479 switch (ed->bEndpointAddress) { 1480 case USB_CONTROL_ENDPOINT: 1481 pipe->up_methods = &roothub_ctrl_methods; 1482 break; 1483 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1484 pipe->up_methods = &xhci_root_intr_methods; 1485 break; 1486 default: 1487 pipe->up_methods = NULL; 1488 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1489 ed->bEndpointAddress, 0, 0, 0); 1490 return USBD_INVAL; 1491 } 1492 return USBD_NORMAL_COMPLETION; 1493 } 1494 1495 switch (xfertype) { 1496 case UE_CONTROL: 1497 pipe->up_methods = &xhci_device_ctrl_methods; 1498 break; 1499 case UE_ISOCHRONOUS: 1500 pipe->up_methods = &xhci_device_isoc_methods; 1501 return USBD_INVAL; 1502 break; 1503 case UE_BULK: 1504 pipe->up_methods = &xhci_device_bulk_methods; 1505 break; 1506 case UE_INTERRUPT: 1507 pipe->up_methods = &xhci_device_intr_methods; 1508 break; 1509 default: 1510 return USBD_IOERROR; 1511 break; 1512 } 1513 1514 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1515 return xhci_configure_endpoint(pipe); 1516 1517 return USBD_NORMAL_COMPLETION; 1518 } 1519 1520 /* 1521 * Closes pipe, called from usbd_kill_pipe via close methods. 1522 * If the endpoint to be closed is ep0, disable_slot. 1523 * Should be called with sc_lock held. 1524 */ 1525 static usbd_status 1526 xhci_close_pipe(struct usbd_pipe *pipe) 1527 { 1528 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1529 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1530 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1531 const u_int dci = xhci_ep_get_dci(ed); 1532 struct xhci_trb trb; 1533 usbd_status err; 1534 uint32_t *cp; 1535 1536 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1537 1538 if (sc->sc_dying) 1539 return USBD_IOERROR; 1540 1541 if (xs == NULL || xs->xs_idx == 0) 1542 /* xs is uninitialized before xhci_init_slot */ 1543 return USBD_IOERROR; 1544 1545 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1546 1547 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1548 KASSERT(mutex_owned(&sc->sc_lock)); 1549 1550 if (pipe->up_dev->ud_depth == 0) 1551 return USBD_NORMAL_COMPLETION; 1552 1553 if (dci == XHCI_DCI_EP_CONTROL) { 1554 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1555 return xhci_disable_slot(sc, xs->xs_idx); 1556 } 1557 1558 /* 1559 * This may fail in the case that xhci_close_pipe is called after 1560 * xhci_abort_xfer e.g. usbd_kill_pipe. 1561 */ 1562 (void)xhci_stop_endpoint(pipe); 1563 1564 /* 1565 * set appropriate bit to be dropped. 1566 * don't set DC bit to 1, otherwise all endpoints 1567 * would be deconfigured. 1568 */ 1569 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1570 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1571 cp[1] = htole32(0); 1572 1573 /* XXX should be most significant one, not dci? */ 1574 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1575 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1576 1577 /* sync input contexts before they are read from memory */ 1578 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1579 1580 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1581 trb.trb_2 = 0; 1582 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1583 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1584 1585 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1586 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1587 1588 return err; 1589 } 1590 1591 /* 1592 * Abort transfer. 1593 * Called with sc_lock held. 1594 * May be called from softintr context. 1595 */ 1596 static void 1597 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1598 { 1599 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1600 1601 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1602 DPRINTFN(4, "xfer %p pipe %p status %d", 1603 xfer, xfer->ux_pipe, status, 0); 1604 1605 KASSERT(mutex_owned(&sc->sc_lock)); 1606 1607 if (sc->sc_dying) { 1608 /* If we're dying, just do the software part. */ 1609 DPRINTFN(4, "dying", 0, 0, 0, 0); 1610 xfer->ux_status = status; /* make software ignore it */ 1611 callout_stop(&xfer->ux_callout); 1612 usb_transfer_complete(xfer); 1613 return; 1614 } 1615 1616 /* XXX need more stuff */ 1617 xfer->ux_status = status; 1618 callout_stop(&xfer->ux_callout); 1619 usb_transfer_complete(xfer); 1620 1621 KASSERT(mutex_owned(&sc->sc_lock)); 1622 } 1623 1624 #if 1 /* XXX experimental */ 1625 /* 1626 * Recover STALLed endpoint. 1627 * xHCI 1.1 sect 4.10.2.1 1628 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1629 * all transfers on transfer ring. 1630 * These are done in thread context asynchronously. 1631 */ 1632 static void 1633 xhci_clear_endpoint_stall_async_task(void *cookie) 1634 { 1635 struct usbd_xfer * const xfer = cookie; 1636 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1637 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1638 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1639 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1640 1641 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1642 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1643 1644 xhci_reset_endpoint(xfer->ux_pipe); 1645 xhci_set_dequeue(xfer->ux_pipe); 1646 1647 mutex_enter(&sc->sc_lock); 1648 tr->is_halted = false; 1649 usb_transfer_complete(xfer); 1650 mutex_exit(&sc->sc_lock); 1651 DPRINTFN(4, "ends", 0, 0, 0, 0); 1652 } 1653 1654 static usbd_status 1655 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1656 { 1657 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1658 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1659 1660 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1661 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1662 1663 if (sc->sc_dying) { 1664 return USBD_IOERROR; 1665 } 1666 1667 usb_init_task(&xp->xp_async_task, 1668 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1669 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1670 DPRINTFN(4, "ends", 0, 0, 0, 0); 1671 1672 return USBD_NORMAL_COMPLETION; 1673 } 1674 1675 #endif /* XXX experimental */ 1676 1677 /* 1678 * Notify roothub port status/change to uhub_intr. 1679 */ 1680 static void 1681 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1682 { 1683 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1684 uint8_t *p; 1685 1686 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1687 DPRINTFN(4, "port %u status change", port, 0, 0, 0); 1688 1689 if (xfer == NULL) 1690 return; 1691 1692 p = xfer->ux_buf; 1693 memset(p, 0, xfer->ux_length); 1694 p[port/NBBY] |= 1 << (port%NBBY); 1695 xfer->ux_actlen = xfer->ux_length; 1696 xfer->ux_status = USBD_NORMAL_COMPLETION; 1697 usb_transfer_complete(xfer); 1698 } 1699 1700 /* 1701 * Process events: 1702 * + Transfer comeplete 1703 * + Command complete 1704 * + Roothub Port status/change 1705 */ 1706 static void 1707 xhci_handle_event(struct xhci_softc * const sc, 1708 const struct xhci_trb * const trb) 1709 { 1710 uint64_t trb_0; 1711 uint32_t trb_2, trb_3; 1712 uint8_t trberr; 1713 1714 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1715 1716 trb_0 = le64toh(trb->trb_0); 1717 trb_2 = le32toh(trb->trb_2); 1718 trb_3 = le32toh(trb->trb_3); 1719 trberr = XHCI_TRB_2_ERROR_GET(trb_2); 1720 1721 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1722 trb, trb_0, trb_2, trb_3); 1723 1724 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 1725 case XHCI_TRB_EVENT_TRANSFER: { 1726 u_int slot, dci; 1727 struct xhci_slot *xs; 1728 struct xhci_ring *xr; 1729 struct xhci_xfer *xx; 1730 struct usbd_xfer *xfer; 1731 usbd_status err; 1732 1733 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1734 dci = XHCI_TRB_3_EP_GET(trb_3); 1735 1736 xs = &sc->sc_slots[slot]; 1737 xr = &xs->xs_ep[dci].xe_tr; 1738 /* sanity check */ 1739 if (xs->xs_idx == 0 || xs->xs_idx >= sc->sc_maxslots) { 1740 DPRINTFN(1, "invalid slot %u", xs->xs_idx, 0, 0, 0); 1741 break; 1742 } 1743 1744 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1745 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 1746 1747 /* trb_0 range sanity check */ 1748 if (trb_0 < trbp || 1749 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 1750 (trb_0 - trbp) / sizeof(struct xhci_trb) >= 1751 xr->xr_ntrb) { 1752 DPRINTFN(1, 1753 "invalid trb_0 0x%"PRIx64" trbp 0x%"PRIx64, 1754 trb_0, trbp, 0, 0); 1755 break; 1756 } 1757 int idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 1758 xx = xr->xr_cookies[idx]; 1759 } else { 1760 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1761 } 1762 /* XXX this may not happen */ 1763 if (xx == NULL) { 1764 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1765 break; 1766 } 1767 xfer = &xx->xx_xfer; 1768 /* XXX this may happen when detaching */ 1769 if (xfer == NULL) { 1770 DPRINTFN(1, "xfer done: xfer is NULL", 0, 0, 0, 0); 1771 break; 1772 } 1773 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1774 /* XXX I dunno why this happens */ 1775 if (!xfer->ux_pipe->up_repeat && 1776 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1777 DPRINTFN(1, "xfer done: xfer not started", 0, 0, 0, 0); 1778 break; 1779 } 1780 1781 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1782 DPRINTFN(14, "transfer event data: " 1783 "0x%016"PRIx64" 0x%08"PRIx32" %02x", 1784 trb_0, XHCI_TRB_2_REM_GET(trb_2), 1785 XHCI_TRB_2_ERROR_GET(trb_2), 0); 1786 if ((trb_0 & 0x3) == 0x3) { 1787 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1788 } 1789 } 1790 1791 switch (trberr) { 1792 case XHCI_TRB_ERROR_SHORT_PKT: 1793 case XHCI_TRB_ERROR_SUCCESS: 1794 xfer->ux_actlen = 1795 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1796 err = USBD_NORMAL_COMPLETION; 1797 break; 1798 case XHCI_TRB_ERROR_STALL: 1799 case XHCI_TRB_ERROR_BABBLE: 1800 DPRINTFN(1, "evh: xfer done: ERR %u slot %u dci %u", 1801 trberr, slot, dci, 0); 1802 xr->is_halted = true; 1803 err = USBD_STALLED; 1804 #if 1 /* XXX experimental */ 1805 /* 1806 * Stalled endpoints can be recoverd by issuing 1807 * command TRB TYPE_RESET_EP on xHCI instead of 1808 * issuing request CLEAR_PORT_FEATURE UF_ENDPOINT_HALT 1809 * on the endpoint. However, this function may be 1810 * called from softint context (e.g. from umass), 1811 * in that case driver gets KASSERT in cv_timedwait 1812 * in xhci_do_command. 1813 * To avoid this, this runs reset_endpoint and 1814 * usb_transfer_complete in usb task thread 1815 * asynchronously (and then umass issues clear 1816 * UF_ENDPOINT_HALT). 1817 */ 1818 xfer->ux_status = err; 1819 xhci_clear_endpoint_stall_async(xfer); 1820 return; 1821 #else 1822 break; 1823 #endif 1824 case XHCI_TRB_ERROR_CMD_ABORTED: 1825 case XHCI_TRB_ERROR_STOPPED: 1826 err = USBD_CANCELLED; 1827 break; 1828 case XHCI_TRB_ERROR_NO_SLOTS: 1829 err = USBD_NO_ADDR; 1830 break; 1831 default: 1832 DPRINTFN(1, "evh: xfer done: ERR %u slot %u dci %u", 1833 trberr, slot, dci, 0); 1834 err = USBD_IOERROR; 1835 break; 1836 } 1837 xfer->ux_status = err; 1838 1839 //mutex_enter(&sc->sc_lock); /* XXX ??? */ 1840 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1841 if ((trb_0 & 0x3) == 0x0) { 1842 usb_transfer_complete(xfer); 1843 } 1844 } else { 1845 usb_transfer_complete(xfer); 1846 } 1847 //mutex_exit(&sc->sc_lock); /* XXX ??? */ 1848 1849 } 1850 break; 1851 case XHCI_TRB_EVENT_CMD_COMPLETE: 1852 if (trb_0 == sc->sc_command_addr) { 1853 sc->sc_result_trb.trb_0 = trb_0; 1854 sc->sc_result_trb.trb_2 = trb_2; 1855 sc->sc_result_trb.trb_3 = trb_3; 1856 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1857 XHCI_TRB_ERROR_SUCCESS) { 1858 DPRINTFN(1, "command completion " 1859 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1860 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1861 } 1862 cv_signal(&sc->sc_command_cv); 1863 } else { 1864 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 1865 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1866 trb_2, trb_3); 1867 } 1868 break; 1869 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1870 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1871 break; 1872 default: 1873 break; 1874 } 1875 } 1876 1877 static void 1878 xhci_softintr(void *v) 1879 { 1880 struct usbd_bus * const bus = v; 1881 struct xhci_softc * const sc = bus->ub_hcpriv; 1882 struct xhci_ring * const er = &sc->sc_er; 1883 struct xhci_trb *trb; 1884 int i, j, k; 1885 1886 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1887 1888 i = er->xr_ep; 1889 j = er->xr_cs; 1890 1891 DPRINTFN(16, "xr_ep %d xr_cs %d", i, j, 0, 0); 1892 1893 while (1) { 1894 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 1895 BUS_DMASYNC_POSTREAD); 1896 trb = &er->xr_trb[i]; 1897 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1898 1899 if (j != k) 1900 break; 1901 1902 xhci_handle_event(sc, trb); 1903 1904 i++; 1905 if (i == XHCI_EVENT_RING_TRBS) { 1906 i = 0; 1907 j ^= 1; 1908 } 1909 } 1910 1911 er->xr_ep = i; 1912 er->xr_cs = j; 1913 1914 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 1915 XHCI_ERDP_LO_BUSY); 1916 1917 DPRINTFN(16, "ends", 0, 0, 0, 0); 1918 1919 return; 1920 } 1921 1922 static void 1923 xhci_poll(struct usbd_bus *bus) 1924 { 1925 struct xhci_softc * const sc = bus->ub_hcpriv; 1926 1927 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1928 1929 mutex_spin_enter(&sc->sc_intr_lock); 1930 xhci_intr1(sc); 1931 mutex_spin_exit(&sc->sc_intr_lock); 1932 1933 return; 1934 } 1935 1936 static struct usbd_xfer * 1937 xhci_allocx(struct usbd_bus *bus) 1938 { 1939 struct xhci_softc * const sc = bus->ub_hcpriv; 1940 struct usbd_xfer *xfer; 1941 1942 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1943 1944 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1945 if (xfer != NULL) { 1946 memset(xfer, 0, sizeof(struct xhci_xfer)); 1947 #ifdef DIAGNOSTIC 1948 xfer->ux_state = XFER_BUSY; 1949 #endif 1950 } 1951 1952 return xfer; 1953 } 1954 1955 static void 1956 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1957 { 1958 struct xhci_softc * const sc = bus->ub_hcpriv; 1959 1960 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1961 1962 #ifdef DIAGNOSTIC 1963 if (xfer->ux_state != XFER_BUSY) { 1964 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 1965 xfer, xfer->ux_state, 0, 0); 1966 } 1967 xfer->ux_state = XFER_FREE; 1968 #endif 1969 pool_cache_put(sc->sc_xferpool, xfer); 1970 } 1971 1972 static void 1973 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1974 { 1975 struct xhci_softc * const sc = bus->ub_hcpriv; 1976 1977 *lock = &sc->sc_lock; 1978 } 1979 1980 extern uint32_t usb_cookie_no; 1981 1982 /* 1983 * Called if uhub_explore find new device (via usbd_new_device). 1984 * Allocate and construct dev structure of default endpoint (ep0). 1985 * Determine initial MaxPacketSize (mps) by speed. 1986 * Determine route string and roothub port for slot of dev. 1987 * Allocate pipe of ep0. 1988 * Enable and initialize slot and Set Address. 1989 * Read device descriptor. 1990 * Register this device. 1991 */ 1992 static usbd_status 1993 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 1994 int speed, int port, struct usbd_port *up) 1995 { 1996 struct xhci_softc * const sc = bus->ub_hcpriv; 1997 struct usbd_device *dev; 1998 usbd_status err; 1999 usb_device_descriptor_t *dd; 2000 struct usbd_device *hub; 2001 struct usbd_device *adev; 2002 int rhport = 0; 2003 struct xhci_slot *xs; 2004 uint32_t *cp; 2005 uint32_t route = 0; 2006 uint8_t slot = 0; 2007 uint8_t addr; 2008 2009 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2010 DPRINTFN(4, "port=%d depth=%d speed=%d upport %d", 2011 port, depth, speed, up->up_portno); 2012 2013 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2014 if (dev == NULL) 2015 return USBD_NOMEM; 2016 2017 dev->ud_bus = bus; 2018 2019 /* Set up default endpoint handle. */ 2020 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2021 2022 /* Set up default endpoint descriptor. */ 2023 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2024 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2025 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2026 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2027 /* 4.3, 4.8.2.1 */ 2028 if (USB_IS_SS(speed)) { 2029 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2030 } else 2031 switch (speed) { 2032 case USB_SPEED_FULL: 2033 /* XXX using 64 as initial mps of ep0 in FS */ 2034 case USB_SPEED_HIGH: 2035 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2036 break; 2037 case USB_SPEED_LOW: 2038 default: 2039 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2040 break; 2041 } 2042 dev->ud_ep0desc.bInterval = 0; 2043 2044 /* doesn't matter, just don't let it uninitialized */ 2045 dev->ud_ep0.ue_toggle = 0; 2046 2047 DPRINTFN(4, "up %p portno %d", up, up->up_portno, 0, 0); 2048 2049 dev->ud_quirks = &usbd_no_quirk; 2050 dev->ud_addr = 0; 2051 dev->ud_ddesc.bMaxPacketSize = 0; 2052 dev->ud_depth = depth; 2053 dev->ud_powersrc = up; 2054 dev->ud_myhub = up->up_parent; 2055 2056 up->up_dev = dev; 2057 2058 /* Locate root hub port */ 2059 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2060 uint32_t dep; 2061 2062 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2063 hub, hub->ud_depth, hub->ud_powersrc, 2064 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2065 2066 if (hub->ud_powersrc == NULL) 2067 break; 2068 dep = hub->ud_depth; 2069 if (dep == 0) 2070 break; 2071 rhport = hub->ud_powersrc->up_portno; 2072 if (dep > USB_HUB_MAX_DEPTH) 2073 continue; 2074 2075 route |= 2076 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2077 << ((dep - 1) * 4); 2078 } 2079 route = route >> 4; 2080 DPRINTFN(4, "rhport %d Route %05x hub %p", rhport, route, hub, 0); 2081 2082 /* Locate port on upstream high speed hub */ 2083 for (adev = dev, hub = up->up_parent; 2084 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2085 adev = hub, hub = hub->ud_myhub) 2086 ; 2087 if (hub) { 2088 int p; 2089 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2090 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2091 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2092 goto found; 2093 } 2094 } 2095 panic("xhci_new_device: cannot find HS port"); 2096 found: 2097 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2098 } else { 2099 dev->ud_myhsport = NULL; 2100 } 2101 2102 dev->ud_speed = speed; 2103 dev->ud_langid = USBD_NOLANG; 2104 dev->ud_cookie.cookie = ++usb_cookie_no; 2105 2106 /* Establish the default pipe. */ 2107 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2108 &dev->ud_pipe0); 2109 if (err) { 2110 goto bad; 2111 } 2112 2113 dd = &dev->ud_ddesc; 2114 2115 if ((depth == 0) && (port == 0)) { 2116 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2117 bus->ub_devices[dev->ud_addr] = dev; 2118 err = usbd_get_initial_ddesc(dev, dd); 2119 if (err) 2120 goto bad; 2121 err = usbd_reload_device_desc(dev); 2122 if (err) 2123 goto bad; 2124 } else { 2125 err = xhci_enable_slot(sc, &slot); 2126 if (err) 2127 goto bad; 2128 xs = &sc->sc_slots[slot]; 2129 dev->ud_hcpriv = xs; 2130 err = xhci_init_slot(dev, slot, route, rhport); 2131 if (err) { 2132 dev->ud_hcpriv = NULL; 2133 /* 2134 * We have to disable_slot here because 2135 * xs->xs_idx == 0 when xhci_init_slot fails, 2136 * in that case usbd_remove_dev won't work. 2137 */ 2138 mutex_enter(&sc->sc_lock); 2139 xhci_disable_slot(sc, slot); 2140 mutex_exit(&sc->sc_lock); 2141 goto bad; 2142 } 2143 2144 /* Allow device time to set new address */ 2145 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2146 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2147 //hexdump("slot context", cp, sc->sc_ctxsz); 2148 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2149 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2150 /* XXX ensure we know when the hardware does something 2151 we can't yet cope with */ 2152 KASSERT(addr >= 1 && addr <= 127); 2153 dev->ud_addr = addr; 2154 /* XXX dev->ud_addr not necessarily unique on bus */ 2155 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2156 bus->ub_devices[dev->ud_addr] = dev; 2157 2158 err = usbd_get_initial_ddesc(dev, dd); 2159 if (err) 2160 goto bad; 2161 /* 4.8.2.1 */ 2162 if (USB_IS_SS(speed)) { 2163 if (dd->bMaxPacketSize != 9) { 2164 printf("%s: invalid mps 2^%u for SS ep0," 2165 " using 512\n", 2166 device_xname(sc->sc_dev), 2167 dd->bMaxPacketSize); 2168 dd->bMaxPacketSize = 9; 2169 } 2170 USETW(dev->ud_ep0desc.wMaxPacketSize, 2171 (1 << dd->bMaxPacketSize)); 2172 } else 2173 USETW(dev->ud_ep0desc.wMaxPacketSize, 2174 dd->bMaxPacketSize); 2175 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2176 xhci_update_ep0_mps(sc, xs, 2177 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2178 err = usbd_reload_device_desc(dev); 2179 if (err) 2180 goto bad; 2181 2182 #if 0 2183 /* Re-establish the default pipe with the new MPS. */ 2184 /* In xhci this is done by xhci_update_ep0_mps. */ 2185 usbd_kill_pipe(dev->ud_pipe0); 2186 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2187 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2188 #endif 2189 } 2190 2191 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2192 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2193 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2194 dd->bDeviceClass, dd->bDeviceSubClass, 2195 dd->bDeviceProtocol, 0); 2196 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2197 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2198 dev->ud_speed); 2199 2200 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2201 2202 if ((depth == 0) && (port == 0)) { 2203 usbd_attach_roothub(parent, dev); 2204 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2205 return USBD_NORMAL_COMPLETION; 2206 } 2207 2208 2209 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2210 bad: 2211 if (err != USBD_NORMAL_COMPLETION) { 2212 usbd_remove_device(dev, up); 2213 } 2214 2215 return err; 2216 } 2217 2218 static usbd_status 2219 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2220 size_t ntrb, size_t align) 2221 { 2222 usbd_status err; 2223 size_t size = ntrb * XHCI_TRB_SIZE; 2224 2225 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2226 2227 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2228 if (err) 2229 return err; 2230 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2231 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2232 xr->xr_trb = xhci_ring_trbv(xr, 0); 2233 xr->xr_ntrb = ntrb; 2234 xr->xr_ep = 0; 2235 xr->xr_cs = 1; 2236 memset(xr->xr_trb, 0, size); 2237 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 2238 xr->is_halted = false; 2239 2240 return USBD_NORMAL_COMPLETION; 2241 } 2242 2243 static void 2244 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2245 { 2246 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2247 mutex_destroy(&xr->xr_lock); 2248 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2249 } 2250 2251 static void 2252 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2253 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2254 { 2255 size_t i; 2256 u_int ri; 2257 u_int cs; 2258 uint64_t parameter; 2259 uint32_t status; 2260 uint32_t control; 2261 2262 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2263 2264 for (i = 0; i < ntrbs; i++) { 2265 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2266 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2267 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2268 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2269 XHCI_TRB_TYPE_LINK); 2270 } 2271 2272 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2273 2274 ri = xr->xr_ep; 2275 cs = xr->xr_cs; 2276 2277 /* 2278 * Although the xhci hardware can do scatter/gather dma from 2279 * arbitrary sized buffers, there is a non-obvious restriction 2280 * that a LINK trb is only allowed at the end of a burst of 2281 * transfers - which might be 16kB. 2282 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2283 * The simple solution is not to allow a LINK trb in the middle 2284 * of anything - as here. 2285 * XXX: (dsl) There are xhci controllers out there (eg some made by 2286 * ASMedia) that seem to lock up if they process a LINK trb but 2287 * cannot process the linked-to trb yet. 2288 * The code should write the 'cycle' bit on the link trb AFTER 2289 * adding the other trb. 2290 */ 2291 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2292 parameter = xhci_ring_trbp(xr, 0); 2293 status = 0; 2294 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2295 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2296 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 2297 htole32(status), htole32(control)); 2298 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2299 BUS_DMASYNC_PREWRITE); 2300 xr->xr_cookies[ri] = NULL; 2301 xr->xr_ep = 0; 2302 xr->xr_cs ^= 1; 2303 ri = xr->xr_ep; 2304 cs = xr->xr_cs; 2305 } 2306 2307 ri++; 2308 2309 /* Write any subsequent TRB first */ 2310 for (i = 1; i < ntrbs; i++) { 2311 parameter = trbs[i].trb_0; 2312 status = trbs[i].trb_2; 2313 control = trbs[i].trb_3; 2314 2315 if (cs) { 2316 control |= XHCI_TRB_3_CYCLE_BIT; 2317 } else { 2318 control &= ~XHCI_TRB_3_CYCLE_BIT; 2319 } 2320 2321 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 2322 htole32(status), htole32(control)); 2323 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2324 BUS_DMASYNC_PREWRITE); 2325 xr->xr_cookies[ri] = cookie; 2326 ri++; 2327 } 2328 2329 /* Write the first TRB last */ 2330 i = 0; 2331 parameter = trbs[i].trb_0; 2332 status = trbs[i].trb_2; 2333 control = trbs[i].trb_3; 2334 2335 if (xr->xr_cs) { 2336 control |= XHCI_TRB_3_CYCLE_BIT; 2337 } else { 2338 control &= ~XHCI_TRB_3_CYCLE_BIT; 2339 } 2340 2341 xhci_trb_put(&xr->xr_trb[xr->xr_ep], htole64(parameter), 2342 htole32(status), htole32(control)); 2343 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2344 BUS_DMASYNC_PREWRITE); 2345 xr->xr_cookies[xr->xr_ep] = cookie; 2346 2347 xr->xr_ep = ri; 2348 xr->xr_cs = cs; 2349 2350 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2351 } 2352 2353 /* 2354 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2355 * Command completion is notified by cv_signal from xhci_handle_event 2356 * (called from interrupt from xHCI), or timed-out. 2357 * Command validation is performed in xhci_handle_event by checking if 2358 * trb_0 in CMD_COMPLETE TRB and sc->sc_command_addr are identical. 2359 */ 2360 static usbd_status 2361 xhci_do_command1(struct xhci_softc * const sc, struct xhci_trb * const trb, 2362 int timeout, int locked) 2363 { 2364 struct xhci_ring * const cr = &sc->sc_cr; 2365 usbd_status err; 2366 2367 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2368 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2369 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2370 2371 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2372 2373 if (!locked) 2374 mutex_enter(&sc->sc_lock); 2375 2376 /* XXX KASSERT may fire when cv_timedwait unlocks sc_lock */ 2377 KASSERT(sc->sc_command_addr == 0); 2378 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2379 2380 mutex_enter(&cr->xr_lock); 2381 xhci_ring_put(sc, cr, NULL, trb, 1); 2382 mutex_exit(&cr->xr_lock); 2383 2384 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2385 2386 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2387 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2388 err = USBD_TIMEOUT; 2389 goto timedout; 2390 } 2391 2392 trb->trb_0 = sc->sc_result_trb.trb_0; 2393 trb->trb_2 = sc->sc_result_trb.trb_2; 2394 trb->trb_3 = sc->sc_result_trb.trb_3; 2395 2396 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2397 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2398 2399 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2400 case XHCI_TRB_ERROR_SUCCESS: 2401 err = USBD_NORMAL_COMPLETION; 2402 break; 2403 default: 2404 case 192 ... 223: 2405 err = USBD_IOERROR; 2406 break; 2407 case 224 ... 255: 2408 err = USBD_NORMAL_COMPLETION; 2409 break; 2410 } 2411 2412 timedout: 2413 sc->sc_command_addr = 0; 2414 if (!locked) 2415 mutex_exit(&sc->sc_lock); 2416 return err; 2417 } 2418 2419 static usbd_status 2420 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2421 int timeout) 2422 { 2423 return xhci_do_command1(sc, trb, timeout, 0); 2424 } 2425 2426 /* 2427 * This allows xhci_do_command with already sc_lock held. 2428 * This is needed as USB stack calls close methods with sc_lock_held. 2429 * (see usbdivar.h) 2430 */ 2431 static usbd_status 2432 xhci_do_command_locked(struct xhci_softc * const sc, 2433 struct xhci_trb * const trb, int timeout) 2434 { 2435 return xhci_do_command1(sc, trb, timeout, 1); 2436 } 2437 2438 static usbd_status 2439 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2440 { 2441 struct xhci_trb trb; 2442 usbd_status err; 2443 2444 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2445 2446 trb.trb_0 = 0; 2447 trb.trb_2 = 0; 2448 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2449 2450 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2451 if (err != USBD_NORMAL_COMPLETION) { 2452 return err; 2453 } 2454 2455 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2456 2457 return err; 2458 } 2459 2460 /* 2461 * Deallocate DMA buffer and ring buffer, and disable_slot. 2462 * Should be called with sc_lock held. 2463 */ 2464 static usbd_status 2465 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2466 { 2467 struct xhci_trb trb; 2468 struct xhci_slot *xs; 2469 2470 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2471 2472 if (sc->sc_dying) 2473 return USBD_IOERROR; 2474 2475 xs = &sc->sc_slots[slot]; 2476 if (xs->xs_idx != 0) { 2477 for (int i = XHCI_DCI_SLOT + 1; i < 32; i++) { 2478 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2479 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2480 } 2481 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2482 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2483 } 2484 2485 trb.trb_0 = 0; 2486 trb.trb_2 = 0; 2487 trb.trb_3 = htole32( 2488 XHCI_TRB_3_SLOT_SET(slot) | 2489 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2490 2491 return xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2492 } 2493 2494 /* 2495 * Change slot state. 2496 * bsr=0: ENABLED -> ADDRESSED 2497 * bsr=1: ENABLED -> DEFAULT 2498 * see xHCI 1.1 4.5.3, 3.3.4 2499 */ 2500 static usbd_status 2501 xhci_address_device(struct xhci_softc * const sc, 2502 uint64_t icp, uint8_t slot_id, bool bsr) 2503 { 2504 struct xhci_trb trb; 2505 usbd_status err; 2506 2507 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2508 2509 trb.trb_0 = icp; 2510 trb.trb_2 = 0; 2511 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2512 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2513 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2514 2515 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2516 return err; 2517 } 2518 2519 static usbd_status 2520 xhci_update_ep0_mps(struct xhci_softc * const sc, 2521 struct xhci_slot * const xs, u_int mps) 2522 { 2523 struct xhci_trb trb; 2524 usbd_status err; 2525 uint32_t * cp; 2526 2527 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2528 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2529 2530 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2531 cp[0] = htole32(0); 2532 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2533 2534 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2535 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2536 2537 /* sync input contexts before they are read from memory */ 2538 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2539 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2540 sc->sc_ctxsz * 4); 2541 2542 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2543 trb.trb_2 = 0; 2544 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2545 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2546 2547 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2548 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2549 return err; 2550 } 2551 2552 static void 2553 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2554 { 2555 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2556 2557 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2558 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2559 &dcbaa[si], dcba, si, 0); 2560 2561 dcbaa[si] = htole64(dcba); 2562 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2563 BUS_DMASYNC_PREWRITE); 2564 } 2565 2566 /* 2567 * Allocate DMA buffer and ring buffer for specified slot 2568 * and set Device Context Base Address 2569 * and issue Set Address device command. 2570 */ 2571 static usbd_status 2572 xhci_init_slot(struct usbd_device *dev, uint32_t slot, int route, int rhport) 2573 { 2574 struct xhci_softc * const sc = dev->ud_bus->ub_hcpriv; 2575 struct xhci_slot *xs; 2576 usbd_status err; 2577 u_int dci; 2578 uint32_t *cp; 2579 uint32_t mps = UGETW(dev->ud_ep0desc.wMaxPacketSize); 2580 2581 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2582 DPRINTFN(4, "slot %u speed %d rhport %d route %05x", 2583 slot, dev->ud_speed, route, rhport); 2584 2585 xs = &sc->sc_slots[slot]; 2586 2587 /* allocate contexts */ 2588 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2589 &xs->xs_dc_dma); 2590 if (err) 2591 return err; 2592 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2593 2594 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2595 &xs->xs_ic_dma); 2596 if (err) 2597 goto bad1; 2598 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2599 2600 for (dci = 0; dci < 32; dci++) { 2601 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2602 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2603 if (dci == XHCI_DCI_SLOT) 2604 continue; 2605 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2606 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2607 if (err) { 2608 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2609 goto bad2; 2610 } 2611 } 2612 2613 /* set up initial input control context */ 2614 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2615 cp[0] = htole32(0); 2616 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 2617 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2618 2619 /* set up input slot context */ 2620 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2621 xhci_setup_sctx(dev, cp); 2622 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(1)); 2623 cp[0] |= htole32(XHCI_SCTX_0_ROUTE_SET(route)); 2624 cp[1] |= htole32(XHCI_SCTX_1_RH_PORT_SET(rhport)); 2625 2626 /* set up input EP0 context */ 2627 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2628 cp[0] = htole32(0); 2629 cp[1] = htole32( 2630 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 2631 XHCI_EPCTX_1_EPTYPE_SET(4) | 2632 XHCI_EPCTX_1_CERR_SET(3) 2633 ); 2634 /* can't use xhci_ep_get_dci() yet? */ 2635 *(uint64_t *)(&cp[2]) = htole64( 2636 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 2637 XHCI_EPCTX_2_DCS_SET(1)); 2638 cp[4] = htole32( 2639 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 2640 ); 2641 2642 /* sync input contexts before they are read from memory */ 2643 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2644 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2645 sc->sc_ctxsz * 3); 2646 2647 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2648 2649 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 2650 false); 2651 2652 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2653 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2654 sc->sc_ctxsz * 2); 2655 2656 bad2: 2657 if (err == USBD_NORMAL_COMPLETION) { 2658 xs->xs_idx = slot; 2659 } else { 2660 for (int i = 1; i < dci; i++) { 2661 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2662 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2663 } 2664 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2665 bad1: 2666 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2667 xs->xs_idx = 0; 2668 } 2669 2670 return err; 2671 } 2672 2673 /* ----- */ 2674 2675 static void 2676 xhci_noop(struct usbd_pipe *pipe) 2677 { 2678 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2679 } 2680 2681 /* 2682 * Process root hub request. 2683 */ 2684 static int 2685 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2686 void *buf, int buflen) 2687 { 2688 struct xhci_softc * const sc = bus->ub_hcpriv; 2689 usb_port_status_t ps; 2690 int l, totlen = 0; 2691 uint16_t len, value, index; 2692 int port, i; 2693 uint32_t v; 2694 2695 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2696 2697 if (sc->sc_dying) 2698 return -1; 2699 2700 len = UGETW(req->wLength); 2701 value = UGETW(req->wValue); 2702 index = UGETW(req->wIndex); 2703 2704 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 2705 req->bmRequestType | (req->bRequest << 8), value, index, len); 2706 2707 #define C(x,y) ((x) | ((y) << 8)) 2708 switch (C(req->bRequest, req->bmRequestType)) { 2709 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2710 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 2711 if (len == 0) 2712 break; 2713 switch (value) { 2714 #define sd ((usb_string_descriptor_t *)buf) 2715 case C(2, UDESC_STRING): 2716 /* Product */ 2717 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 2718 break; 2719 #undef sd 2720 default: 2721 /* default from usbroothub */ 2722 return buflen; 2723 } 2724 break; 2725 2726 /* Hub requests */ 2727 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2728 break; 2729 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2730 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2731 index, value, 0, 0); 2732 if (index < 1 || index > sc->sc_maxports) { 2733 return -1; 2734 } 2735 port = XHCI_PORTSC(index); 2736 v = xhci_op_read_4(sc, port); 2737 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2738 v &= ~XHCI_PS_CLEAR; 2739 switch (value) { 2740 case UHF_PORT_ENABLE: 2741 xhci_op_write_4(sc, port, v &~ XHCI_PS_PED); 2742 break; 2743 case UHF_PORT_SUSPEND: 2744 return -1; 2745 case UHF_PORT_POWER: 2746 break; 2747 case UHF_PORT_TEST: 2748 case UHF_PORT_INDICATOR: 2749 return -1; 2750 case UHF_C_PORT_CONNECTION: 2751 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2752 break; 2753 case UHF_C_PORT_ENABLE: 2754 case UHF_C_PORT_SUSPEND: 2755 case UHF_C_PORT_OVER_CURRENT: 2756 return -1; 2757 case UHF_C_BH_PORT_RESET: 2758 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 2759 break; 2760 case UHF_C_PORT_RESET: 2761 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2762 break; 2763 case UHF_C_PORT_LINK_STATE: 2764 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 2765 break; 2766 case UHF_C_PORT_CONFIG_ERROR: 2767 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 2768 break; 2769 default: 2770 return -1; 2771 } 2772 break; 2773 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2774 if (len == 0) 2775 break; 2776 if ((value & 0xff) != 0) { 2777 return -1; 2778 } 2779 usb_hub_descriptor_t hubd; 2780 2781 totlen = min(buflen, sizeof(hubd)); 2782 memcpy(&hubd, buf, totlen); 2783 hubd.bNbrPorts = sc->sc_maxports; 2784 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2785 hubd.bPwrOn2PwrGood = 200; 2786 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 2787 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2788 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2789 totlen = min(totlen, hubd.bDescLength); 2790 memcpy(buf, &hubd, totlen); 2791 break; 2792 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2793 if (len != 4) { 2794 return -1; 2795 } 2796 memset(buf, 0, len); /* ? XXX */ 2797 totlen = len; 2798 break; 2799 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2800 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2801 if (index < 1 || index > sc->sc_maxports) { 2802 return -1; 2803 } 2804 if (len != 4) { 2805 return -1; 2806 } 2807 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 2808 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 2809 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 2810 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2811 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2812 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2813 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 2814 if (v & XHCI_PS_PR) i |= UPS_RESET; 2815 if (v & XHCI_PS_PP) { 2816 if (i & UPS_OTHER_SPEED) 2817 i |= UPS_PORT_POWER_SS; 2818 else 2819 i |= UPS_PORT_POWER; 2820 } 2821 if (i & UPS_OTHER_SPEED) 2822 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 2823 USETW(ps.wPortStatus, i); 2824 i = 0; 2825 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2826 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2827 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2828 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2829 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 2830 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 2831 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 2832 USETW(ps.wPortChange, i); 2833 totlen = min(len, sizeof(ps)); 2834 memcpy(buf, &ps, totlen); 2835 break; 2836 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2837 return -1; 2838 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 2839 break; 2840 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2841 break; 2842 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 2843 int optval = (index >> 8) & 0xff; 2844 index &= 0xff; 2845 if (index < 1 || index > sc->sc_maxports) { 2846 return -1; 2847 } 2848 port = XHCI_PORTSC(index); 2849 v = xhci_op_read_4(sc, port); 2850 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2851 v &= ~XHCI_PS_CLEAR; 2852 switch (value) { 2853 case UHF_PORT_ENABLE: 2854 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 2855 break; 2856 case UHF_PORT_SUSPEND: 2857 /* XXX suspend */ 2858 break; 2859 case UHF_PORT_RESET: 2860 v &= ~ (XHCI_PS_PED | XHCI_PS_PR); 2861 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 2862 /* Wait for reset to complete. */ 2863 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2864 if (sc->sc_dying) { 2865 return -1; 2866 } 2867 v = xhci_op_read_4(sc, port); 2868 if (v & XHCI_PS_PR) { 2869 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 2870 usb_delay_ms(&sc->sc_bus, 10); 2871 /* XXX */ 2872 } 2873 break; 2874 case UHF_PORT_POWER: 2875 /* XXX power control */ 2876 break; 2877 /* XXX more */ 2878 case UHF_C_PORT_RESET: 2879 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2880 break; 2881 case UHF_PORT_U1_TIMEOUT: 2882 if (USB_IS_SS(xhci_xspeed2speed(XHCI_PS_SPEED_GET(v)))){ 2883 return -1; 2884 } 2885 port = XHCI_PORTPMSC(index); 2886 v = xhci_op_read_4(sc, port); 2887 v &= ~XHCI_PM3_U1TO_SET(0xff); 2888 v |= XHCI_PM3_U1TO_SET(optval); 2889 xhci_op_write_4(sc, port, v); 2890 break; 2891 case UHF_PORT_U2_TIMEOUT: 2892 if (USB_IS_SS(xhci_xspeed2speed(XHCI_PS_SPEED_GET(v)))){ 2893 return -1; 2894 } 2895 port = XHCI_PORTPMSC(index); 2896 v = xhci_op_read_4(sc, port); 2897 v &= ~XHCI_PM3_U2TO_SET(0xff); 2898 v |= XHCI_PM3_U2TO_SET(optval); 2899 xhci_op_write_4(sc, port, v); 2900 break; 2901 default: 2902 return -1; 2903 } 2904 } 2905 break; 2906 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2907 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2908 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2909 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2910 break; 2911 default: 2912 /* default from usbroothub */ 2913 return buflen; 2914 } 2915 2916 return totlen; 2917 } 2918 2919 /* root hub interrupt */ 2920 2921 static usbd_status 2922 xhci_root_intr_transfer(struct usbd_xfer *xfer) 2923 { 2924 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2925 usbd_status err; 2926 2927 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2928 2929 /* Insert last in queue. */ 2930 mutex_enter(&sc->sc_lock); 2931 err = usb_insert_transfer(xfer); 2932 mutex_exit(&sc->sc_lock); 2933 if (err) 2934 return err; 2935 2936 /* Pipe isn't running, start first */ 2937 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2938 } 2939 2940 /* Wait for roothub port status/change */ 2941 static usbd_status 2942 xhci_root_intr_start(struct usbd_xfer *xfer) 2943 { 2944 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2945 2946 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2947 2948 if (sc->sc_dying) 2949 return USBD_IOERROR; 2950 2951 mutex_enter(&sc->sc_lock); 2952 sc->sc_intrxfer = xfer; 2953 mutex_exit(&sc->sc_lock); 2954 2955 return USBD_IN_PROGRESS; 2956 } 2957 2958 static void 2959 xhci_root_intr_abort(struct usbd_xfer *xfer) 2960 { 2961 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2962 2963 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2964 2965 KASSERT(mutex_owned(&sc->sc_lock)); 2966 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2967 2968 sc->sc_intrxfer = NULL; 2969 2970 xfer->ux_status = USBD_CANCELLED; 2971 usb_transfer_complete(xfer); 2972 } 2973 2974 static void 2975 xhci_root_intr_close(struct usbd_pipe *pipe) 2976 { 2977 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 2978 2979 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2980 2981 KASSERT(mutex_owned(&sc->sc_lock)); 2982 2983 sc->sc_intrxfer = NULL; 2984 } 2985 2986 static void 2987 xhci_root_intr_done(struct usbd_xfer *xfer) 2988 { 2989 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2990 2991 xfer->ux_hcpriv = NULL; 2992 } 2993 2994 /* -------------- */ 2995 /* device control */ 2996 2997 static usbd_status 2998 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 2999 { 3000 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3001 usbd_status err; 3002 3003 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3004 3005 /* Insert last in queue. */ 3006 mutex_enter(&sc->sc_lock); 3007 err = usb_insert_transfer(xfer); 3008 mutex_exit(&sc->sc_lock); 3009 if (err) 3010 return err; 3011 3012 /* Pipe isn't running, start first */ 3013 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3014 } 3015 3016 static usbd_status 3017 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3018 { 3019 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3020 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3021 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3022 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3023 struct xhci_xfer * const xx = (void *)xfer; 3024 usb_device_request_t * const req = &xfer->ux_request; 3025 const bool isread = UT_GET_DIR(req->bmRequestType) == UT_READ; 3026 const uint32_t len = UGETW(req->wLength); 3027 usb_dma_t * const dma = &xfer->ux_dmabuf; 3028 uint64_t parameter; 3029 uint32_t status; 3030 uint32_t control; 3031 u_int i; 3032 3033 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3034 DPRINTFN(12, "req: %04x %04x %04x %04x", 3035 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3036 UGETW(req->wIndex), UGETW(req->wLength)); 3037 3038 /* XXX */ 3039 if (tr->is_halted) { 3040 DPRINTFN(1, "ctrl xfer %p halted: slot %u dci %u", 3041 xfer, xs->xs_idx, dci, 0); 3042 xhci_reset_endpoint(xfer->ux_pipe); 3043 tr->is_halted = false; 3044 xhci_set_dequeue(xfer->ux_pipe); 3045 } 3046 3047 /* we rely on the bottom bits for extra info */ 3048 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 3049 3050 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3051 3052 i = 0; 3053 3054 /* setup phase */ 3055 memcpy(¶meter, req, sizeof(*req)); 3056 parameter = le64toh(parameter); 3057 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3058 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3059 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3060 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3061 XHCI_TRB_3_IDT_BIT; 3062 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3063 3064 if (len == 0) 3065 goto no_data; 3066 3067 /* data phase */ 3068 parameter = DMAADDR(dma, 0); 3069 KASSERT(len <= 0x10000); 3070 status = XHCI_TRB_2_IRQ_SET(0) | 3071 XHCI_TRB_2_TDSZ_SET(1) | 3072 XHCI_TRB_2_BYTES_SET(len); 3073 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3074 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3075 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3076 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3077 3078 parameter = (uintptr_t)xfer | 0x3; 3079 status = XHCI_TRB_2_IRQ_SET(0); 3080 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3081 XHCI_TRB_3_IOC_BIT; 3082 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3083 3084 no_data: 3085 parameter = 0; 3086 status = XHCI_TRB_2_IRQ_SET(0); 3087 /* the status stage has inverted direction */ 3088 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3089 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3090 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3091 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3092 3093 parameter = (uintptr_t)xfer | 0x0; 3094 status = XHCI_TRB_2_IRQ_SET(0); 3095 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3096 XHCI_TRB_3_IOC_BIT; 3097 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3098 3099 mutex_enter(&tr->xr_lock); 3100 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3101 mutex_exit(&tr->xr_lock); 3102 3103 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3104 3105 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3106 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3107 xhci_timeout, xfer); 3108 } 3109 3110 if (sc->sc_bus.ub_usepolling) { 3111 DPRINTFN(1, "polling", 0, 0, 0, 0); 3112 //xhci_waitintr(sc, xfer); 3113 } 3114 3115 return USBD_IN_PROGRESS; 3116 } 3117 3118 static void 3119 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3120 { 3121 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3122 3123 callout_stop(&xfer->ux_callout); /* XXX wrong place */ 3124 3125 } 3126 3127 static void 3128 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3129 { 3130 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3131 3132 xhci_abort_xfer(xfer, USBD_CANCELLED); 3133 } 3134 3135 static void 3136 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3137 { 3138 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3139 3140 (void)xhci_close_pipe(pipe); 3141 } 3142 3143 /* ------------------ */ 3144 /* device isochronous */ 3145 3146 /* ----------- */ 3147 /* device bulk */ 3148 3149 static usbd_status 3150 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3151 { 3152 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3153 usbd_status err; 3154 3155 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3156 3157 /* Insert last in queue. */ 3158 mutex_enter(&sc->sc_lock); 3159 err = usb_insert_transfer(xfer); 3160 mutex_exit(&sc->sc_lock); 3161 if (err) 3162 return err; 3163 3164 /* 3165 * Pipe isn't running (otherwise err would be USBD_INPROG), 3166 * so start it first. 3167 */ 3168 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3169 } 3170 3171 static usbd_status 3172 xhci_device_bulk_start(struct usbd_xfer *xfer) 3173 { 3174 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3175 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3176 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3177 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3178 struct xhci_xfer * const xx = (void *)xfer; 3179 const uint32_t len = xfer->ux_length; 3180 usb_dma_t * const dma = &xfer->ux_dmabuf; 3181 uint64_t parameter; 3182 uint32_t status; 3183 uint32_t control; 3184 u_int i = 0; 3185 3186 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3187 3188 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3189 3190 if (sc->sc_dying) 3191 return USBD_IOERROR; 3192 3193 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3194 3195 parameter = DMAADDR(dma, 0); 3196 /* 3197 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3198 * If the user supplied buffer crosses such a boundary then 2 3199 * (or more) TRB should be used. 3200 * If multiple TRB are used the td_size field must be set correctly. 3201 * For v1.0 devices (like ivy bridge) this is the number of usb data 3202 * blocks needed to complete the transfer. 3203 * Setting it to 1 in the last TRB causes an extra zero-length 3204 * data block be sent. 3205 * The earlier documentation differs, I don't know how it behaves. 3206 */ 3207 KASSERT(len <= 0x10000); 3208 status = XHCI_TRB_2_IRQ_SET(0) | 3209 XHCI_TRB_2_TDSZ_SET(1) | 3210 XHCI_TRB_2_BYTES_SET(len); 3211 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3212 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3213 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3214 3215 mutex_enter(&tr->xr_lock); 3216 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3217 mutex_exit(&tr->xr_lock); 3218 3219 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3220 3221 if (sc->sc_bus.ub_usepolling) { 3222 DPRINTFN(1, "polling", 0, 0, 0, 0); 3223 //xhci_waitintr(sc, xfer); 3224 } 3225 3226 return USBD_IN_PROGRESS; 3227 } 3228 3229 static void 3230 xhci_device_bulk_done(struct usbd_xfer *xfer) 3231 { 3232 #ifdef USB_DEBUG 3233 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3234 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3235 #endif 3236 const u_int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3237 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3238 3239 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3240 3241 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3242 3243 callout_stop(&xfer->ux_callout); /* XXX wrong place */ 3244 3245 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3246 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3247 } 3248 3249 static void 3250 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3251 { 3252 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3253 3254 xhci_abort_xfer(xfer, USBD_CANCELLED); 3255 } 3256 3257 static void 3258 xhci_device_bulk_close(struct usbd_pipe *pipe) 3259 { 3260 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3261 3262 (void)xhci_close_pipe(pipe); 3263 } 3264 3265 /* ---------------- */ 3266 /* device interrupt */ 3267 3268 static usbd_status 3269 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3270 { 3271 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3272 usbd_status err; 3273 3274 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3275 3276 /* Insert last in queue. */ 3277 mutex_enter(&sc->sc_lock); 3278 err = usb_insert_transfer(xfer); 3279 mutex_exit(&sc->sc_lock); 3280 if (err) 3281 return err; 3282 3283 /* 3284 * Pipe isn't running (otherwise err would be USBD_INPROG), 3285 * so start it first. 3286 */ 3287 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3288 } 3289 3290 static usbd_status 3291 xhci_device_intr_start(struct usbd_xfer *xfer) 3292 { 3293 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3294 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3295 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3296 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3297 struct xhci_xfer * const xx = (void *)xfer; 3298 const uint32_t len = xfer->ux_length; 3299 usb_dma_t * const dma = &xfer->ux_dmabuf; 3300 uint64_t parameter; 3301 uint32_t status; 3302 uint32_t control; 3303 u_int i = 0; 3304 3305 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3306 3307 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3308 3309 if (sc->sc_dying) 3310 return USBD_IOERROR; 3311 3312 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3313 3314 parameter = DMAADDR(dma, 0); 3315 KASSERT(len <= 0x10000); 3316 status = XHCI_TRB_2_IRQ_SET(0) | 3317 XHCI_TRB_2_TDSZ_SET(1) | 3318 XHCI_TRB_2_BYTES_SET(len); 3319 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3320 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3321 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3322 3323 mutex_enter(&tr->xr_lock); 3324 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3325 mutex_exit(&tr->xr_lock); 3326 3327 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3328 3329 if (sc->sc_bus.ub_usepolling) { 3330 DPRINTFN(1, "polling", 0, 0, 0, 0); 3331 //xhci_waitintr(sc, xfer); 3332 } 3333 3334 return USBD_IN_PROGRESS; 3335 } 3336 3337 static void 3338 xhci_device_intr_done(struct usbd_xfer *xfer) 3339 { 3340 struct xhci_softc * const sc __diagused = 3341 xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3342 #ifdef USB_DEBUG 3343 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3344 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3345 #endif 3346 const u_int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3347 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3348 3349 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3350 3351 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3352 3353 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3354 3355 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3356 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3357 3358 #if 0 3359 device_printf(sc->sc_dev, ""); 3360 for (size_t i = 0; i < xfer->ux_length; i++) { 3361 printf(" %02x", ((uint8_t const *)xfer->ux_buffer)[i]); 3362 } 3363 printf("\n"); 3364 #endif 3365 3366 if (xfer->ux_pipe->up_repeat) { 3367 xfer->ux_status = xhci_device_intr_start(xfer); 3368 } else { 3369 callout_stop(&xfer->ux_callout); /* XXX */ 3370 } 3371 3372 } 3373 3374 static void 3375 xhci_device_intr_abort(struct usbd_xfer *xfer) 3376 { 3377 struct xhci_softc * const sc __diagused = 3378 xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3379 3380 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3381 3382 KASSERT(mutex_owned(&sc->sc_lock)); 3383 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3384 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3385 xhci_abort_xfer(xfer, USBD_CANCELLED); 3386 } 3387 3388 static void 3389 xhci_device_intr_close(struct usbd_pipe *pipe) 3390 { 3391 //struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 3392 3393 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3394 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3395 3396 (void)xhci_close_pipe(pipe); 3397 } 3398 3399 /* ------------ */ 3400 3401 static void 3402 xhci_timeout(void *addr) 3403 { 3404 struct xhci_xfer * const xx = addr; 3405 struct usbd_xfer * const xfer = &xx->xx_xfer; 3406 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3407 3408 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3409 3410 if (sc->sc_dying) { 3411 return; 3412 } 3413 3414 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 3415 USB_TASKQ_MPSAFE); 3416 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 3417 USB_TASKQ_HC); 3418 } 3419 3420 static void 3421 xhci_timeout_task(void *addr) 3422 { 3423 struct usbd_xfer * const xfer = addr; 3424 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3425 3426 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3427 3428 mutex_enter(&sc->sc_lock); 3429 #if 0 3430 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3431 #else 3432 xfer->ux_status = USBD_TIMEOUT; 3433 usb_transfer_complete(xfer); 3434 #endif 3435 mutex_exit(&sc->sc_lock); 3436 } 3437
Indexes created Wed Oct 01 15:09:59 GMT 2025