xhci.c revision 1.28.2.39
1 /* $NetBSD: xhci.c,v 1.28.2.39 2015/09/29 11:38:29 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 3.1 specification 31 * http://www.usb.org/developers/docs/usb_31_040315.zip 32 * USB rev 2.0 specification 33 * http://www.usb.org/developers/docs/usb20_docs/usb_20_031815.zip 34 * xHCI rev 1.1 specification 35 * http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.28.2.39 2015/09/29 11:38:29 skrll Exp $"); 40 41 #include "opt_usb.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 146 147 static usbd_status xhci_do_command(struct xhci_softc * const, 148 struct xhci_trb * const, int); 149 static usbd_status xhci_do_command1(struct xhci_softc * const, 150 struct xhci_trb * const, int, int); 151 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 152 struct xhci_trb * const, int); 153 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t, int, int); 154 static usbd_status xhci_enable_slot(struct xhci_softc * const, 155 uint8_t * const); 156 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 157 static usbd_status xhci_address_device(struct xhci_softc * const, 158 uint64_t, uint8_t, bool); 159 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 160 struct xhci_slot * const, u_int); 161 static usbd_status xhci_ring_init(struct xhci_softc * const, 162 struct xhci_ring * const, size_t, size_t); 163 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 164 165 static void xhci_noop(struct usbd_pipe *); 166 167 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 168 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 169 static void xhci_root_intr_abort(struct usbd_xfer *); 170 static void xhci_root_intr_close(struct usbd_pipe *); 171 static void xhci_root_intr_done(struct usbd_xfer *); 172 173 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 174 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 175 static void xhci_device_ctrl_abort(struct usbd_xfer *); 176 static void xhci_device_ctrl_close(struct usbd_pipe *); 177 static void xhci_device_ctrl_done(struct usbd_xfer *); 178 179 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 180 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 181 static void xhci_device_intr_abort(struct usbd_xfer *); 182 static void xhci_device_intr_close(struct usbd_pipe *); 183 static void xhci_device_intr_done(struct usbd_xfer *); 184 185 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 186 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 187 static void xhci_device_bulk_abort(struct usbd_xfer *); 188 static void xhci_device_bulk_close(struct usbd_pipe *); 189 static void xhci_device_bulk_done(struct usbd_xfer *); 190 191 static void xhci_timeout(void *); 192 static void xhci_timeout_task(void *); 193 194 static const struct usbd_bus_methods xhci_bus_methods = { 195 .ubm_open = xhci_open, 196 .ubm_softint = xhci_softintr, 197 .ubm_dopoll = xhci_poll, 198 .ubm_allocx = xhci_allocx, 199 .ubm_freex = xhci_freex, 200 .ubm_getlock = xhci_get_lock, 201 .ubm_newdev = xhci_new_device, 202 .ubm_rhctrl = xhci_roothub_ctrl, 203 }; 204 205 static const struct usbd_pipe_methods xhci_root_intr_methods = { 206 .upm_transfer = xhci_root_intr_transfer, 207 .upm_start = xhci_root_intr_start, 208 .upm_abort = xhci_root_intr_abort, 209 .upm_close = xhci_root_intr_close, 210 .upm_cleartoggle = xhci_noop, 211 .upm_done = xhci_root_intr_done, 212 }; 213 214 215 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 216 .upm_transfer = xhci_device_ctrl_transfer, 217 .upm_start = xhci_device_ctrl_start, 218 .upm_abort = xhci_device_ctrl_abort, 219 .upm_close = xhci_device_ctrl_close, 220 .upm_cleartoggle = xhci_noop, 221 .upm_done = xhci_device_ctrl_done, 222 }; 223 224 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 225 .upm_cleartoggle = xhci_noop, 226 }; 227 228 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 229 .upm_transfer = xhci_device_bulk_transfer, 230 .upm_start = xhci_device_bulk_start, 231 .upm_abort = xhci_device_bulk_abort, 232 .upm_close = xhci_device_bulk_close, 233 .upm_cleartoggle = xhci_noop, 234 .upm_done = xhci_device_bulk_done, 235 }; 236 237 static const struct usbd_pipe_methods xhci_device_intr_methods = { 238 .upm_transfer = xhci_device_intr_transfer, 239 .upm_start = xhci_device_intr_start, 240 .upm_abort = xhci_device_intr_abort, 241 .upm_close = xhci_device_intr_close, 242 .upm_cleartoggle = xhci_noop, 243 .upm_done = xhci_device_intr_done, 244 }; 245 246 static inline uint32_t 247 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 248 { 249 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 250 } 251 252 static inline uint32_t 253 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 254 { 255 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 256 } 257 258 static inline void 259 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 260 uint32_t value) 261 { 262 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 263 } 264 265 #if 0 /* unused */ 266 static inline void 267 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 268 uint32_t value) 269 { 270 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 271 } 272 #endif /* unused */ 273 274 static inline uint32_t 275 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 276 { 277 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 278 } 279 280 static inline uint32_t 281 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 282 { 283 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 284 } 285 286 static inline void 287 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 288 uint32_t value) 289 { 290 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 291 } 292 293 #if 0 /* unused */ 294 static inline uint64_t 295 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 296 { 297 uint64_t value; 298 299 if (sc->sc_ac64) { 300 #ifdef XHCI_USE_BUS_SPACE_8 301 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 302 #else 303 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 304 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 305 offset + 4) << 32; 306 #endif 307 } else { 308 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 309 } 310 311 return value; 312 } 313 #endif /* unused */ 314 315 static inline void 316 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 317 uint64_t value) 318 { 319 if (sc->sc_ac64) { 320 #ifdef XHCI_USE_BUS_SPACE_8 321 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 322 #else 323 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 324 (value >> 0) & 0xffffffff); 325 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 326 (value >> 32) & 0xffffffff); 327 #endif 328 } else { 329 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 330 } 331 } 332 333 static inline uint32_t 334 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 335 { 336 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 337 } 338 339 static inline void 340 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 341 uint32_t value) 342 { 343 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 344 } 345 346 #if 0 /* unused */ 347 static inline uint64_t 348 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 349 { 350 uint64_t value; 351 352 if (sc->sc_ac64) { 353 #ifdef XHCI_USE_BUS_SPACE_8 354 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 355 #else 356 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 357 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 358 offset + 4) << 32; 359 #endif 360 } else { 361 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 362 } 363 364 return value; 365 } 366 #endif /* unused */ 367 368 static inline void 369 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 370 uint64_t value) 371 { 372 if (sc->sc_ac64) { 373 #ifdef XHCI_USE_BUS_SPACE_8 374 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 375 #else 376 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 377 (value >> 0) & 0xffffffff); 378 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 379 (value >> 32) & 0xffffffff); 380 #endif 381 } else { 382 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 383 } 384 } 385 386 #if 0 /* unused */ 387 static inline uint32_t 388 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 389 { 390 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 391 } 392 #endif /* unused */ 393 394 static inline void 395 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 396 uint32_t value) 397 { 398 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 399 } 400 401 /* --- */ 402 403 static inline uint8_t 404 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 405 { 406 u_int eptype = 0; 407 408 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 409 case UE_CONTROL: 410 eptype = 0x0; 411 break; 412 case UE_ISOCHRONOUS: 413 eptype = 0x1; 414 break; 415 case UE_BULK: 416 eptype = 0x2; 417 break; 418 case UE_INTERRUPT: 419 eptype = 0x3; 420 break; 421 } 422 423 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 424 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 425 return eptype | 0x4; 426 else 427 return eptype; 428 } 429 430 static u_int 431 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 432 { 433 /* xHCI 1.0 section 4.5.1 */ 434 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 435 u_int in = 0; 436 437 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 438 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 439 in = 1; 440 441 return epaddr * 2 + in; 442 } 443 444 static inline u_int 445 xhci_dci_to_ici(const u_int i) 446 { 447 return i + 1; 448 } 449 450 static inline void * 451 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 452 const u_int dci) 453 { 454 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 455 } 456 457 #if 0 /* unused */ 458 static inline bus_addr_t 459 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 460 const u_int dci) 461 { 462 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 463 } 464 #endif /* unused */ 465 466 static inline void * 467 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 468 const u_int ici) 469 { 470 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 471 } 472 473 static inline bus_addr_t 474 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 475 const u_int ici) 476 { 477 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 478 } 479 480 static inline struct xhci_trb * 481 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 482 { 483 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 484 } 485 486 static inline bus_addr_t 487 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 488 { 489 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 490 } 491 492 static inline void 493 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 494 uint32_t control) 495 { 496 trb->trb_0 = htole64(parameter); 497 trb->trb_2 = htole32(status); 498 trb->trb_3 = htole32(control); 499 } 500 501 /* --- */ 502 503 void 504 xhci_childdet(device_t self, device_t child) 505 { 506 struct xhci_softc * const sc = device_private(self); 507 508 KASSERT(sc->sc_child == child); 509 if (child == sc->sc_child) 510 sc->sc_child = NULL; 511 } 512 513 int 514 xhci_detach(struct xhci_softc *sc, int flags) 515 { 516 int rv = 0; 517 518 if (sc->sc_child != NULL) 519 rv = config_detach(sc->sc_child, flags); 520 521 if (rv != 0) 522 return rv; 523 524 /* XXX unconfigure/free slots */ 525 526 /* verify: */ 527 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 528 xhci_op_write_4(sc, XHCI_USBCMD, 0); 529 /* do we need to wait for stop? */ 530 531 xhci_op_write_8(sc, XHCI_CRCR, 0); 532 xhci_ring_free(sc, &sc->sc_cr); 533 cv_destroy(&sc->sc_command_cv); 534 535 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 536 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 537 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 538 xhci_ring_free(sc, &sc->sc_er); 539 540 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 541 542 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 543 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 544 545 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 546 547 mutex_destroy(&sc->sc_lock); 548 mutex_destroy(&sc->sc_intr_lock); 549 cv_destroy(&sc->sc_softwake_cv); 550 551 pool_cache_destroy(sc->sc_xferpool); 552 553 return rv; 554 } 555 556 int 557 xhci_activate(device_t self, enum devact act) 558 { 559 struct xhci_softc * const sc = device_private(self); 560 561 switch (act) { 562 case DVACT_DEACTIVATE: 563 sc->sc_dying = true; 564 return 0; 565 default: 566 return EOPNOTSUPP; 567 } 568 } 569 570 bool 571 xhci_suspend(device_t dv, const pmf_qual_t *qual) 572 { 573 return false; 574 } 575 576 bool 577 xhci_resume(device_t dv, const pmf_qual_t *qual) 578 { 579 return false; 580 } 581 582 bool 583 xhci_shutdown(device_t self, int flags) 584 { 585 return false; 586 } 587 588 589 static void 590 hexdump(const char *msg, const void *base, size_t len) 591 { 592 #if 0 593 size_t cnt; 594 const uint32_t *p; 595 extern paddr_t vtophys(vaddr_t); 596 597 p = base; 598 cnt = 0; 599 600 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 601 (void *)vtophys((vaddr_t)base)); 602 603 while (cnt < len) { 604 if (cnt % 16 == 0) 605 printf("%p: ", p); 606 else if (cnt % 8 == 0) 607 printf(" |"); 608 printf(" %08x", *p++); 609 cnt += 4; 610 if (cnt % 16 == 0) 611 printf("\n"); 612 } 613 #endif 614 } 615 616 #define XHCI_HCCPREV1_BITS \ 617 "\177\020" /* New bitmask */ \ 618 "f\020\020XECP\0" \ 619 "f\014\4MAXPSA\0" \ 620 "b\013CFC\0" \ 621 "b\012SEC\0" \ 622 "b\011SBD\0" \ 623 "b\010FSE\0" \ 624 "b\7NSS\0" \ 625 "b\6LTC\0" \ 626 "b\5LHRC\0" \ 627 "b\4PIND\0" \ 628 "b\3PPC\0" \ 629 "b\2CZC\0" \ 630 "b\1BNC\0" \ 631 "b\0AC64\0" \ 632 "\0" 633 #define XHCI_HCCV1_x_BITS \ 634 "\177\020" /* New bitmask */ \ 635 "f\020\020XECP\0" \ 636 "f\014\4MAXPSA\0" \ 637 "b\013CFC\0" \ 638 "b\012SEC\0" \ 639 "b\011SPC\0" \ 640 "b\010PAE\0" \ 641 "b\7NSS\0" \ 642 "b\6LTC\0" \ 643 "b\5LHRC\0" \ 644 "b\4PIND\0" \ 645 "b\3PPC\0" \ 646 "b\2CSZ\0" \ 647 "b\1BNC\0" \ 648 "b\0AC64\0" \ 649 "\0" 650 651 int 652 xhci_init(struct xhci_softc *sc) 653 { 654 bus_size_t bsz; 655 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 656 uint32_t ecp, ecr; 657 uint32_t usbcmd, usbsts, pagesize, config; 658 int i; 659 uint16_t hciversion; 660 uint8_t caplength; 661 662 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 663 664 /* XXX Low/Full/High speeds for now */ 665 sc->sc_bus.ub_revision = USBREV_2_0; 666 sc->sc_bus.ub_usedma = true; 667 668 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 669 caplength = XHCI_CAP_CAPLENGTH(cap); 670 hciversion = XHCI_CAP_HCIVERSION(cap); 671 672 if (hciversion < XHCI_HCIVERSION_0_96 || 673 hciversion > XHCI_HCIVERSION_1_0) { 674 aprint_normal_dev(sc->sc_dev, 675 "xHCI version %x.%x not known to be supported\n", 676 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 677 } else { 678 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 679 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 680 } 681 682 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 683 &sc->sc_cbh) != 0) { 684 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 685 return ENOMEM; 686 } 687 688 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 689 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 690 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 691 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 692 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 693 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 694 aprint_debug_dev(sc->sc_dev, 695 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 696 697 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 698 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 699 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 700 701 char sbuf[128]; 702 if (hciversion < XHCI_HCIVERSION_1_0) 703 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 704 else 705 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 706 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 707 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 708 709 ecp = XHCI_HCC_XECP(hcc) * 4; 710 while (ecp != 0) { 711 ecr = xhci_read_4(sc, ecp); 712 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 713 switch (XHCI_XECP_ID(ecr)) { 714 case XHCI_ID_PROTOCOLS: { 715 uint32_t w0, w4, w8; 716 uint16_t w2; 717 w0 = xhci_read_4(sc, ecp + 0); 718 w2 = (w0 >> 16) & 0xffff; 719 w4 = xhci_read_4(sc, ecp + 4); 720 w8 = xhci_read_4(sc, ecp + 8); 721 aprint_debug_dev(sc->sc_dev, "SP: %08x %08x %08x\n", 722 w0, w4, w8); 723 if (w4 == 0x20425355 && w2 == 0x0300) { 724 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 725 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 726 } 727 if (w4 == 0x20425355 && w2 == 0x0200) { 728 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 729 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 730 } 731 break; 732 } 733 case XHCI_ID_USB_LEGACY: { 734 uint8_t bios_sem; 735 736 /* Take host controller from BIOS */ 737 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 738 if (bios_sem) { 739 /* sets xHCI to be owned by OS */ 740 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 741 aprint_debug( 742 "waiting for BIOS to give up control\n"); 743 for (i = 0; i < 5000; i++) { 744 bios_sem = xhci_read_1(sc, ecp + 745 XHCI_XECP_BIOS_SEM); 746 if (bios_sem == 0) 747 break; 748 DELAY(1000); 749 } 750 if (bios_sem) 751 printf("timed out waiting for BIOS\n"); 752 } 753 break; 754 } 755 default: 756 break; 757 } 758 ecr = xhci_read_4(sc, ecp); 759 if (XHCI_XECP_NEXT(ecr) == 0) { 760 ecp = 0; 761 } else { 762 ecp += XHCI_XECP_NEXT(ecr) * 4; 763 } 764 } 765 766 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 767 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 768 &sc->sc_obh) != 0) { 769 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 770 return ENOMEM; 771 } 772 773 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 774 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 775 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 776 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 777 return ENOMEM; 778 } 779 780 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 781 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 782 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 783 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 784 return ENOMEM; 785 } 786 787 for (i = 0; i < 100; i++) { 788 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 789 if ((usbsts & XHCI_STS_CNR) == 0) 790 break; 791 usb_delay_ms(&sc->sc_bus, 1); 792 } 793 if (i >= 100) 794 return EIO; 795 796 usbcmd = 0; 797 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 798 usb_delay_ms(&sc->sc_bus, 1); 799 800 usbcmd = XHCI_CMD_HCRST; 801 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 802 for (i = 0; i < 100; i++) { 803 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 804 if ((usbcmd & XHCI_CMD_HCRST) == 0) 805 break; 806 usb_delay_ms(&sc->sc_bus, 1); 807 } 808 if (i >= 100) 809 return EIO; 810 811 for (i = 0; i < 100; i++) { 812 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 813 if ((usbsts & XHCI_STS_CNR) == 0) 814 break; 815 usb_delay_ms(&sc->sc_bus, 1); 816 } 817 if (i >= 100) 818 return EIO; 819 820 if (sc->sc_vendor_init) 821 sc->sc_vendor_init(sc); 822 823 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 824 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 825 pagesize = ffs(pagesize); 826 if (pagesize == 0) 827 return EIO; 828 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 829 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 830 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 831 (uint32_t)sc->sc_maxslots); 832 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 833 834 usbd_status err; 835 836 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 837 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 838 if (sc->sc_maxspbuf != 0) { 839 err = usb_allocmem(&sc->sc_bus, 840 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 841 &sc->sc_spbufarray_dma); 842 if (err) 843 return err; 844 845 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * sc->sc_maxspbuf, KM_SLEEP); 846 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 847 for (i = 0; i < sc->sc_maxspbuf; i++) { 848 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 849 /* allocate contexts */ 850 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 851 sc->sc_pgsz, dma); 852 if (err) 853 return err; 854 spbufarray[i] = htole64(DMAADDR(dma, 0)); 855 usb_syncmem(dma, 0, sc->sc_pgsz, 856 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 857 } 858 859 usb_syncmem(&sc->sc_spbufarray_dma, 0, 860 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 861 } 862 863 config = xhci_op_read_4(sc, XHCI_CONFIG); 864 config &= ~0xFF; 865 config |= sc->sc_maxslots & 0xFF; 866 xhci_op_write_4(sc, XHCI_CONFIG, config); 867 868 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 869 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 870 if (err) { 871 aprint_error_dev(sc->sc_dev, "command ring init fail\n"); 872 return err; 873 } 874 875 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 876 XHCI_EVENT_RING_SEGMENTS_ALIGN); 877 if (err) { 878 aprint_error_dev(sc->sc_dev, "event ring init fail\n"); 879 return err; 880 } 881 882 usb_dma_t *dma; 883 size_t size; 884 size_t align; 885 886 dma = &sc->sc_eventst_dma; 887 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 888 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 889 KASSERT(size <= (512 * 1024)); 890 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 891 err = usb_allocmem(&sc->sc_bus, size, align, dma); 892 893 memset(KERNADDR(dma, 0), 0, size); 894 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 895 aprint_debug_dev(sc->sc_dev, "eventst: %s %016jx %p %zx\n", 896 usbd_errstr(err), 897 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 898 KERNADDR(&sc->sc_eventst_dma, 0), 899 sc->sc_eventst_dma.udma_block->size); 900 901 dma = &sc->sc_dcbaa_dma; 902 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 903 KASSERT(size <= 2048); 904 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 905 err = usb_allocmem(&sc->sc_bus, size, align, dma); 906 907 memset(KERNADDR(dma, 0), 0, size); 908 if (sc->sc_maxspbuf != 0) { 909 /* 910 * DCBA entry 0 hold the scratchbuf array pointer. 911 */ 912 *(uint64_t *)KERNADDR(dma, 0) = 913 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 914 } 915 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 916 aprint_debug_dev(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n", 917 usbd_errstr(err), 918 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 919 KERNADDR(&sc->sc_dcbaa_dma, 0), 920 sc->sc_dcbaa_dma.udma_block->size); 921 922 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 923 KM_SLEEP); 924 925 cv_init(&sc->sc_command_cv, "xhcicmd"); 926 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 927 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 928 cv_init(&sc->sc_softwake_cv, "xhciab"); 929 930 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 931 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 932 933 /* Set up the bus struct. */ 934 sc->sc_bus.ub_methods = &xhci_bus_methods; 935 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 936 937 struct xhci_erste *erst; 938 erst = KERNADDR(&sc->sc_eventst_dma, 0); 939 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 940 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 941 erst[0].erste_3 = htole32(0); 942 usb_syncmem(&sc->sc_eventst_dma, 0, 943 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 944 945 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 946 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 947 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 948 XHCI_ERDP_LO_BUSY); 949 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 950 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 951 sc->sc_cr.xr_cs); 952 953 #if 0 954 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 955 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 956 #endif 957 958 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 959 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 960 /* Intel xhci needs interrupt rate moderated. */ 961 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 962 else 963 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 964 aprint_debug_dev(sc->sc_dev, "setting IMOD %u\n", 965 xhci_rt_read_4(sc, XHCI_IMOD(0))); 966 967 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 968 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 969 xhci_op_read_4(sc, XHCI_USBCMD)); 970 971 return USBD_NORMAL_COMPLETION; 972 } 973 974 int 975 xhci_intr(void *v) 976 { 977 struct xhci_softc * const sc = v; 978 int ret = 0; 979 980 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 981 982 if (sc == NULL) 983 return 0; 984 985 mutex_spin_enter(&sc->sc_intr_lock); 986 987 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 988 goto done; 989 990 /* If we get an interrupt while polling, then just ignore it. */ 991 if (sc->sc_bus.ub_usepolling) { 992 #ifdef DIAGNOSTIC 993 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 994 #endif 995 goto done; 996 } 997 998 ret = xhci_intr1(sc); 999 done: 1000 mutex_spin_exit(&sc->sc_intr_lock); 1001 return ret; 1002 } 1003 1004 int 1005 xhci_intr1(struct xhci_softc * const sc) 1006 { 1007 uint32_t usbsts; 1008 uint32_t iman; 1009 1010 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1011 1012 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1013 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1014 #if 0 1015 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1016 return 0; 1017 } 1018 #endif 1019 xhci_op_write_4(sc, XHCI_USBSTS, 1020 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1021 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1022 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1023 1024 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1025 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1026 1027 /* XXX 4.17.5 IP may be 0 if MSI/MSI-X is used */ 1028 if (!(sc->sc_quirks & XHCI_QUIRK_FORCE_INTR)) { 1029 if ((iman & XHCI_IMAN_INTR_PEND) == 0) { 1030 return 0; 1031 } 1032 } 1033 1034 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1035 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1036 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1037 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1038 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1039 1040 usb_schedsoftintr(&sc->sc_bus); 1041 1042 return 1; 1043 } 1044 1045 /* 1046 * 3 port speed types used in USB stack 1047 * 1048 * usbdi speed 1049 * definition: USB_SPEED_* in usb.h 1050 * They are used in struct usbd_device in USB stack. 1051 * ioctl interface uses these values too. 1052 * port_status speed 1053 * definition: UPS_*_SPEED in usb.h 1054 * They are used in usb_port_status_t and valid only for USB 2.0. 1055 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1056 * of usb_port_status_ext_t indicates port speed. 1057 * Note that some 3.0 values overlap with 2.0 values. 1058 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1059 * means UPS_LOW_SPEED in HS.) 1060 * port status returned from hub also uses these values. 1061 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1062 * or more. 1063 * xspeed: 1064 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1065 * They are used in only slot context and PORTSC reg of xhci. 1066 * The difference between usbdi speed and xspeed is 1067 * that FS and LS values are swapped. 1068 */ 1069 1070 /* convert usbdi speed to xspeed */ 1071 static int 1072 xhci_speed2xspeed(int speed) 1073 { 1074 switch (speed) { 1075 case USB_SPEED_LOW: return 2; 1076 case USB_SPEED_FULL: return 1; 1077 default: return speed; 1078 } 1079 } 1080 1081 /* convert xspeed to usbdi speed */ 1082 static int 1083 xhci_xspeed2speed(int xspeed) 1084 { 1085 switch (xspeed) { 1086 case 1: return USB_SPEED_FULL; 1087 case 2: return USB_SPEED_LOW; 1088 default: return xspeed; 1089 } 1090 } 1091 1092 /* convert xspeed to port status speed */ 1093 static int 1094 xhci_xspeed2psspeed(int xspeed) 1095 { 1096 switch (xspeed) { 1097 case 0: return 0; 1098 case 1: return UPS_FULL_SPEED; 1099 case 2: return UPS_LOW_SPEED; 1100 case 3: return UPS_HIGH_SPEED; 1101 default: return UPS_OTHER_SPEED; 1102 } 1103 } 1104 1105 /* construct slot context */ 1106 static void 1107 xhci_setup_sctx(struct usbd_device *dev, uint32_t *cp) 1108 { 1109 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 1110 int speed = dev->ud_speed; 1111 int tthubslot, ttportnum; 1112 bool ishub; 1113 bool usemtt; 1114 1115 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1116 1117 /* 1118 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 1119 * tthubslot: 1120 * This is the slot ID of parent HS hub 1121 * if LS/FS device is connected && connected through HS hub. 1122 * This is 0 if device is not LS/FS device || 1123 * parent hub is not HS hub || 1124 * attached to root hub. 1125 * ttportnum: 1126 * This is the downstream facing port of parent HS hub 1127 * if LS/FS device is connected. 1128 * This is 0 if device is not LS/FS device || 1129 * parent hub is not HS hub || 1130 * attached to root hub. 1131 */ 1132 if (dev->ud_myhsport != NULL && 1133 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1134 (dev->ud_myhub != NULL && 1135 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1136 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 1137 ttportnum = dev->ud_myhsport->up_portno; 1138 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 1139 } else { 1140 ttportnum = 0; 1141 tthubslot = 0; 1142 } 1143 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 1144 dev->ud_myhsport, ttportnum, tthubslot, 0); 1145 1146 /* ishub is valid after reading UDESC_DEVICE */ 1147 ishub = (dd->bDeviceClass == UDCLASS_HUB); 1148 1149 /* dev->ud_hub is valid after reading UDESC_HUB */ 1150 if (ishub && dev->ud_hub) { 1151 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 1152 1153 cp[1] |= htole32(XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts)); 1154 cp[2] |= htole32(XHCI_SCTX_2_TT_THINK_TIME_SET( 1155 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK))); 1156 DPRINTFN(4, "nports=%d ttt=%d", 1157 hd->bNbrPorts, XHCI_SCTX_2_TT_THINK_TIME_GET(cp[2]), 0, 0); 1158 } 1159 1160 #define IS_TTHUB(dd) \ 1161 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 1162 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 1163 1164 /* 1165 * MTT flag is set if 1166 * 1. this is HS hub && MTT is enabled 1167 * or 1168 * 2. this is not hub && this is LS or FS device && 1169 * MTT of parent HS hub (and its parent, too) is enabled 1170 */ 1171 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 1172 usemtt = true; 1173 else if (!ishub && 1174 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 1175 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1176 (dev->ud_myhub != NULL && 1177 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1178 dev->ud_myhsport != NULL && 1179 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 1180 usemtt = true; 1181 else 1182 usemtt = false; 1183 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 1184 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 1185 1186 cp[0] |= htole32( 1187 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)) | 1188 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 1189 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0) 1190 ); 1191 cp[1] |= htole32(0); 1192 cp[2] |= htole32( 1193 XHCI_SCTX_2_IRQ_TARGET_SET(0) | 1194 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 1195 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum) 1196 ); 1197 cp[3] |= htole32(0); 1198 } 1199 1200 static uint32_t 1201 xhci_get_maxburst(struct usbd_pipe *pipe) 1202 { 1203 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1204 usbd_desc_iter_t iter; 1205 const usb_cdc_descriptor_t *cdcd; 1206 const usb_endpoint_ss_comp_descriptor_t * esscd = NULL; 1207 uint32_t maxb = 0; 1208 uint8_t ep; 1209 1210 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc( 1211 pipe->up_dev, UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 1212 usb_desc_iter_init(pipe->up_dev, &iter); 1213 iter.cur = (const void *)cdcd; 1214 1215 /* find endpoint_ss_comp desc for ep of this pipe */ 1216 for (ep = 0;;) { 1217 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 1218 if (cdcd == NULL) 1219 break; 1220 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 1221 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 1222 bEndpointAddress; 1223 if (UE_GET_ADDR(ep) == 1224 UE_GET_ADDR(ed->bEndpointAddress)) { 1225 cdcd = (const usb_cdc_descriptor_t *) 1226 usb_desc_iter_next(&iter); 1227 break; 1228 } 1229 ep = 0; 1230 } 1231 } 1232 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 1233 esscd = (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 1234 maxb = esscd->bMaxBurst; 1235 } 1236 1237 return maxb; 1238 } 1239 1240 /* 1241 * Convert endpoint bInterval value to endpoint context interval value 1242 * for Interrupt pipe. 1243 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 1244 */ 1245 static uint32_t 1246 xhci_bival2ival(uint32_t ival, int speed) 1247 { 1248 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 1249 int i; 1250 1251 /* 1252 * round ival down to "the nearest base 2 multiple of 1253 * bInterval * 8". 1254 * bInterval is at most 255 as its type is uByte. 1255 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 1256 */ 1257 for (i = 10; i > 0; i--) { 1258 if ((ival * 8) >= (1 << i)) 1259 break; 1260 } 1261 ival = i; 1262 } else { 1263 /* Interval = bInterval-1 for SS/HS */ 1264 ival--; 1265 } 1266 1267 return ival; 1268 } 1269 1270 /* 1271 * 4.8.2, 6.2.3.2 1272 * construct common endpoint parameters 1273 */ 1274 static void 1275 xhci_setup_endp_ctx(struct usbd_pipe *pipe, uint32_t *cp) 1276 { 1277 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1278 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1279 const u_int dci = xhci_ep_get_dci(ed); 1280 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1281 uint32_t mps = UGETW(ed->wMaxPacketSize); 1282 uint32_t maxb = 0; 1283 int speed = pipe->up_dev->ud_speed; 1284 uint32_t ival = ed->bInterval; 1285 1286 cp[0] = htole32( 1287 XHCI_EPCTX_0_EPSTATE_SET(0) | 1288 XHCI_EPCTX_0_MULT_SET(0) | /* always 0 except SS iscoh */ 1289 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 1290 XHCI_EPCTX_0_LSA_SET(0) | 1291 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0) 1292 ); 1293 cp[1] = htole32( 1294 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 1295 XHCI_EPCTX_1_HID_SET(0) | 1296 XHCI_EPCTX_1_MAXB_SET(0) 1297 ); 1298 if (xfertype != UE_ISOCHRONOUS) 1299 cp[1] |= htole32(XHCI_EPCTX_1_CERR_SET(3)); 1300 1301 /* 6.2.3.4, 4.8.2.4 */ 1302 if (USB_IS_SS(speed)) { 1303 /* UBS 3.1 9.6.6 */ 1304 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1305 /* UBS 3.1 9.6.7 */ 1306 maxb = xhci_get_maxburst(pipe); 1307 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1308 } else { 1309 /* UBS 2.0 9.6.6 */ 1310 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps))); 1311 1312 /* 6.2.3.4 */ 1313 if (speed == USB_SPEED_HIGH && 1314 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 1315 maxb = UE_GET_TRANS(mps); 1316 } else { 1317 /* LS/FS or HS CTRL or HS BULK */ 1318 maxb = 0; 1319 } 1320 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1321 } 1322 1323 if (xfertype == UE_CONTROL) 1324 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(8)); /* 6.2.3 */ 1325 else if (USB_IS_SS(speed)) 1326 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps)); 1327 else 1328 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps))); 1329 1330 switch (xfertype) { 1331 case UE_CONTROL: 1332 break; 1333 case UE_BULK: 1334 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 1335 break; 1336 case UE_INTERRUPT: 1337 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1338 ival = pipe->up_interval; 1339 1340 ival = xhci_bival2ival(ival, speed); 1341 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1342 break; 1343 case UE_ISOCHRONOUS: 1344 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1345 ival = pipe->up_interval; 1346 1347 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 1348 if (speed == USB_SPEED_FULL) 1349 ival += 3; /* 1ms -> 125us */ 1350 ival--; 1351 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1352 1353 if (USB_IS_SS(speed)) { 1354 /* XXX if LEC = 1, set ESIT instead */ 1355 cp[0] |= htole32(XHCI_EPCTX_0_MULT_SET(0)); 1356 } 1357 break; 1358 default: 1359 break; 1360 } 1361 *(uint64_t *)(&cp[2]) = htole64( 1362 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 1363 XHCI_EPCTX_2_DCS_SET(1)); 1364 } 1365 1366 /* 1367 * Construct input contexts and issue TRB 1368 */ 1369 static usbd_status 1370 xhci_configure_endpoint(struct usbd_pipe *pipe) 1371 { 1372 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1373 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1374 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1375 struct xhci_trb trb; 1376 usbd_status err; 1377 uint32_t *cp; 1378 1379 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1380 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1381 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1382 pipe->up_endpoint->ue_edesc->bmAttributes); 1383 1384 /* XXX ensure input context is available? */ 1385 1386 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1387 1388 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1389 cp[0] = htole32(0); 1390 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 1391 1392 /* set up input slot context */ 1393 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1394 xhci_setup_sctx(pipe->up_dev, cp); 1395 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1396 1397 /* set up input endpoint context */ 1398 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 1399 xhci_setup_endp_ctx(pipe, cp); 1400 1401 /* sync input contexts before they are read from memory */ 1402 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1403 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1404 sc->sc_ctxsz * 1); 1405 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1406 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1407 1408 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1409 trb.trb_2 = 0; 1410 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1411 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1412 1413 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1414 1415 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1416 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1417 sc->sc_ctxsz * 1); 1418 1419 return err; 1420 } 1421 1422 #if 0 1423 static usbd_status 1424 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1425 { 1426 #ifdef USB_DEBUG 1427 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1428 #endif 1429 1430 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1431 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1432 1433 return USBD_NORMAL_COMPLETION; 1434 } 1435 #endif 1436 1437 /* 4.6.8, 6.4.3.7 */ 1438 static usbd_status 1439 xhci_reset_endpoint(struct usbd_pipe *pipe) 1440 { 1441 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1442 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1443 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1444 struct xhci_trb trb; 1445 usbd_status err; 1446 1447 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1448 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1449 1450 KASSERT(!mutex_owned(&sc->sc_lock)); 1451 1452 trb.trb_0 = 0; 1453 trb.trb_2 = 0; 1454 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1455 XHCI_TRB_3_EP_SET(dci) | 1456 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1457 1458 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1459 1460 return err; 1461 } 1462 1463 /* 1464 * 4.6.9, 6.4.3.8 1465 * Stop execution of TDs on xfer ring. 1466 * Should be called with sc_lock held. 1467 */ 1468 static usbd_status 1469 xhci_stop_endpoint(struct usbd_pipe *pipe) 1470 { 1471 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1472 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1473 struct xhci_trb trb; 1474 usbd_status err; 1475 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1476 1477 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1478 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1479 1480 KASSERT(mutex_owned(&sc->sc_lock)); 1481 1482 trb.trb_0 = 0; 1483 trb.trb_2 = 0; 1484 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1485 XHCI_TRB_3_EP_SET(dci) | 1486 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1487 1488 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1489 1490 return err; 1491 } 1492 1493 /* 1494 * Set TR Dequeue Pointer. 1495 * xCHI 1.1 4.6.10 6.4.3.9 1496 * Purge all of the transfer requests on ring. 1497 * EPSTATE of endpoint must be ERROR or STOPPED, or CONTEXT_STATE error. 1498 */ 1499 static usbd_status 1500 xhci_set_dequeue(struct usbd_pipe *pipe) 1501 { 1502 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1503 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1504 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1505 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1506 struct xhci_trb trb; 1507 usbd_status err; 1508 1509 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1510 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1511 1512 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1513 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1514 BUS_DMASYNC_PREWRITE); 1515 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1516 1517 xr->xr_ep = 0; 1518 xr->xr_cs = 1; 1519 1520 /* set DCS */ 1521 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1522 trb.trb_2 = 0; 1523 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1524 XHCI_TRB_3_EP_SET(dci) | 1525 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1526 1527 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1528 1529 return err; 1530 } 1531 1532 /* 1533 * Open new pipe: called from usbd_setup_pipe_flags. 1534 * Fills methods of pipe. 1535 * If pipe is not for ep0, calls configure_endpoint. 1536 */ 1537 static usbd_status 1538 xhci_open(struct usbd_pipe *pipe) 1539 { 1540 struct usbd_device * const dev = pipe->up_dev; 1541 struct xhci_softc * const sc = dev->ud_bus->ub_hcpriv; 1542 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1543 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1544 1545 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1546 DPRINTFN(1, "addr %d depth %d port %d speed %d", 1547 dev->ud_addr, dev->ud_depth, dev->ud_powersrc->up_portno, 1548 dev->ud_speed); 1549 1550 if (sc->sc_dying) 1551 return USBD_IOERROR; 1552 1553 /* Root Hub */ 1554 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1555 switch (ed->bEndpointAddress) { 1556 case USB_CONTROL_ENDPOINT: 1557 pipe->up_methods = &roothub_ctrl_methods; 1558 break; 1559 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1560 pipe->up_methods = &xhci_root_intr_methods; 1561 break; 1562 default: 1563 pipe->up_methods = NULL; 1564 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1565 ed->bEndpointAddress, 0, 0, 0); 1566 return USBD_INVAL; 1567 } 1568 return USBD_NORMAL_COMPLETION; 1569 } 1570 1571 switch (xfertype) { 1572 case UE_CONTROL: 1573 pipe->up_methods = &xhci_device_ctrl_methods; 1574 break; 1575 case UE_ISOCHRONOUS: 1576 pipe->up_methods = &xhci_device_isoc_methods; 1577 return USBD_INVAL; 1578 break; 1579 case UE_BULK: 1580 pipe->up_methods = &xhci_device_bulk_methods; 1581 break; 1582 case UE_INTERRUPT: 1583 pipe->up_methods = &xhci_device_intr_methods; 1584 break; 1585 default: 1586 return USBD_IOERROR; 1587 break; 1588 } 1589 1590 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1591 return xhci_configure_endpoint(pipe); 1592 1593 return USBD_NORMAL_COMPLETION; 1594 } 1595 1596 /* 1597 * Closes pipe, called from usbd_kill_pipe via close methods. 1598 * If the endpoint to be closed is ep0, disable_slot. 1599 * Should be called with sc_lock held. 1600 */ 1601 static void 1602 xhci_close_pipe(struct usbd_pipe *pipe) 1603 { 1604 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1605 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1606 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1607 const u_int dci = xhci_ep_get_dci(ed); 1608 struct xhci_trb trb; 1609 uint32_t *cp; 1610 1611 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1612 1613 if (sc->sc_dying) 1614 return; 1615 1616 if (xs == NULL || xs->xs_idx == 0) 1617 /* xs is uninitialized before xhci_init_slot */ 1618 return; 1619 1620 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1621 1622 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1623 KASSERT(mutex_owned(&sc->sc_lock)); 1624 1625 if (pipe->up_dev->ud_depth == 0) 1626 return; 1627 1628 if (dci == XHCI_DCI_EP_CONTROL) { 1629 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1630 xhci_disable_slot(sc, xs->xs_idx); 1631 return; 1632 } 1633 1634 /* 1635 * This may fail in the case that xhci_close_pipe is called after 1636 * xhci_abort_xfer e.g. usbd_kill_pipe. 1637 */ 1638 (void)xhci_stop_endpoint(pipe); 1639 1640 /* 1641 * set appropriate bit to be dropped. 1642 * don't set DC bit to 1, otherwise all endpoints 1643 * would be deconfigured. 1644 */ 1645 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1646 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1647 cp[1] = htole32(0); 1648 1649 /* XXX should be most significant one, not dci? */ 1650 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1651 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1652 1653 /* sync input contexts before they are read from memory */ 1654 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1655 1656 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1657 trb.trb_2 = 0; 1658 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1659 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1660 1661 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1662 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1663 } 1664 1665 /* 1666 * Abort transfer. 1667 * Called with sc_lock held. 1668 * May be called from softintr context. 1669 */ 1670 static void 1671 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1672 { 1673 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1674 1675 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1676 DPRINTFN(4, "xfer %p pipe %p status %d", 1677 xfer, xfer->ux_pipe, status, 0); 1678 1679 KASSERT(mutex_owned(&sc->sc_lock)); 1680 1681 if (sc->sc_dying) { 1682 /* If we're dying, just do the software part. */ 1683 DPRINTFN(4, "dying", 0, 0, 0, 0); 1684 xfer->ux_status = status; /* make software ignore it */ 1685 callout_stop(&xfer->ux_callout); 1686 usb_transfer_complete(xfer); 1687 return; 1688 } 1689 1690 /* XXX need more stuff */ 1691 xfer->ux_status = status; 1692 callout_stop(&xfer->ux_callout); 1693 usb_transfer_complete(xfer); 1694 DPRINTFN(14, "end", 0, 0, 0, 0); 1695 1696 KASSERT(mutex_owned(&sc->sc_lock)); 1697 } 1698 1699 /* 1700 * Recover STALLed endpoint. 1701 * xHCI 1.1 sect 4.10.2.1 1702 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1703 * all transfers on transfer ring. 1704 * These are done in thread context asynchronously. 1705 */ 1706 static void 1707 xhci_clear_endpoint_stall_async_task(void *cookie) 1708 { 1709 struct usbd_xfer * const xfer = cookie; 1710 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1711 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1712 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1713 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1714 1715 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1716 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1717 1718 xhci_reset_endpoint(xfer->ux_pipe); 1719 xhci_set_dequeue(xfer->ux_pipe); 1720 1721 mutex_enter(&sc->sc_lock); 1722 tr->is_halted = false; 1723 usb_transfer_complete(xfer); 1724 mutex_exit(&sc->sc_lock); 1725 DPRINTFN(4, "ends", 0, 0, 0, 0); 1726 } 1727 1728 static usbd_status 1729 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1730 { 1731 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1732 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1733 1734 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1735 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1736 1737 if (sc->sc_dying) { 1738 return USBD_IOERROR; 1739 } 1740 1741 usb_init_task(&xp->xp_async_task, 1742 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1743 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1744 DPRINTFN(4, "ends", 0, 0, 0, 0); 1745 1746 return USBD_NORMAL_COMPLETION; 1747 } 1748 1749 /* Process roothub port status/change events and notify to uhub_intr. */ 1750 static void 1751 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1752 { 1753 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1754 uint8_t *p; 1755 1756 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1757 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1758 port, 0, 0); 1759 1760 if (xfer == NULL) 1761 return; 1762 1763 if (port > sc->sc_maxports) 1764 return; 1765 1766 p = xfer->ux_buf; 1767 memset(p, 0, xfer->ux_length); 1768 p[port/NBBY] |= 1 << (port%NBBY); 1769 xfer->ux_actlen = xfer->ux_length; 1770 xfer->ux_status = USBD_NORMAL_COMPLETION; 1771 usb_transfer_complete(xfer); 1772 } 1773 1774 /* Process Transfer Events */ 1775 static void 1776 xhci_event_transfer(struct xhci_softc * const sc, 1777 const struct xhci_trb * const trb) 1778 { 1779 uint64_t trb_0; 1780 uint32_t trb_2, trb_3; 1781 uint8_t trbcode; 1782 u_int slot, dci; 1783 struct xhci_slot *xs; 1784 struct xhci_ring *xr; 1785 struct xhci_xfer *xx; 1786 struct usbd_xfer *xfer; 1787 usbd_status err; 1788 1789 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1790 1791 trb_0 = le64toh(trb->trb_0); 1792 trb_2 = le32toh(trb->trb_2); 1793 trb_3 = le32toh(trb->trb_3); 1794 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1795 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1796 dci = XHCI_TRB_3_EP_GET(trb_3); 1797 xs = &sc->sc_slots[slot]; 1798 xr = &xs->xs_ep[dci].xe_tr; 1799 1800 /* sanity check */ 1801 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx < sc->sc_maxslots, 1802 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1803 1804 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1805 /* 1806 * When ED == 0, trb_0 is physical address of the TRB 1807 * that caused this event. (6.4.2.1) 1808 */ 1809 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 1810 1811 /* trb_0 range sanity check */ 1812 if (trb_0 < trbp || 1813 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 1814 (trb_0 - trbp) / sizeof(struct xhci_trb) >= 1815 xr->xr_ntrb) { 1816 DPRINTFN(1, "invalid trb_0 0x%"PRIx64" trbp 0x%"PRIx64, 1817 trb_0, trbp, 0, 0); 1818 return; 1819 } 1820 int idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 1821 xx = xr->xr_cookies[idx]; 1822 1823 /* 1824 * If endpoint is stopped between TDs, TRB pointer points at 1825 * next TRB, however, it is not put yet or is a garbage TRB. 1826 * That's why xr_cookies may be NULL or look like broken. 1827 * Note: this ev happens only when hciversion >= 1.0 or 1828 * hciversion == 0.96 and FSE of hcc1 is set. 1829 */ 1830 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1831 DPRINTFN(1, "xx NULL: #%u: cookie %p: code %u trb_0 %" 1832 PRIx64, idx, xx, trbcode, trb_0); 1833 } 1834 } else { 1835 /* When ED != 0, trb_0 is kaddr of struct xhci_xfer. */ 1836 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1837 } 1838 /* XXX this may not happen */ 1839 if (xx == NULL) { 1840 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1841 return; 1842 } 1843 xfer = &xx->xx_xfer; 1844 /* XXX this may happen when detaching */ 1845 if (xfer == NULL) { 1846 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1847 xx, trb_0, 0, 0); 1848 return; 1849 } 1850 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1851 /* XXX I dunno why this happens */ 1852 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1853 1854 if (!xfer->ux_pipe->up_repeat && 1855 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1856 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1857 return; 1858 } 1859 1860 /* 4.11.5.2 Event Data TRB */ 1861 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1862 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1863 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1864 if ((trb_0 & 0x3) == 0x3) { 1865 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1866 } 1867 } 1868 1869 switch (trbcode) { 1870 case XHCI_TRB_ERROR_SHORT_PKT: 1871 case XHCI_TRB_ERROR_SUCCESS: 1872 xfer->ux_actlen = 1873 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1874 err = USBD_NORMAL_COMPLETION; 1875 break; 1876 case XHCI_TRB_ERROR_STALL: 1877 case XHCI_TRB_ERROR_BABBLE: 1878 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1879 xr->is_halted = true; 1880 err = USBD_STALLED; 1881 /* 1882 * Stalled endpoints can be recoverd by issuing 1883 * command TRB TYPE_RESET_EP on xHCI instead of 1884 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1885 * on the endpoint. However, this function may be 1886 * called from softint context (e.g. from umass), 1887 * in that case driver gets KASSERT in cv_timedwait 1888 * in xhci_do_command. 1889 * To avoid this, this runs reset_endpoint and 1890 * usb_transfer_complete in usb task thread 1891 * asynchronously (and then umass issues clear 1892 * UF_ENDPOINT_HALT). 1893 */ 1894 xfer->ux_status = err; 1895 xhci_clear_endpoint_stall_async(xfer); 1896 return; 1897 default: 1898 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1899 err = USBD_IOERROR; 1900 break; 1901 } 1902 xfer->ux_status = err; 1903 1904 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1905 if ((trb_0 & 0x3) == 0x0) { 1906 usb_transfer_complete(xfer); 1907 } 1908 } else { 1909 usb_transfer_complete(xfer); 1910 } 1911 } 1912 1913 /* Process Command complete events */ 1914 static void 1915 xhci_event_cmd(struct xhci_softc * const sc, 1916 const struct xhci_trb * const trb) 1917 { 1918 uint64_t trb_0; 1919 uint32_t trb_2, trb_3; 1920 1921 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1922 1923 trb_0 = le64toh(trb->trb_0); 1924 trb_2 = le32toh(trb->trb_2); 1925 trb_3 = le32toh(trb->trb_3); 1926 1927 if (trb_0 == sc->sc_command_addr) { 1928 sc->sc_result_trb.trb_0 = trb_0; 1929 sc->sc_result_trb.trb_2 = trb_2; 1930 sc->sc_result_trb.trb_3 = trb_3; 1931 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1932 XHCI_TRB_ERROR_SUCCESS) { 1933 DPRINTFN(1, "command completion " 1934 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1935 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1936 } 1937 cv_signal(&sc->sc_command_cv); 1938 } else { 1939 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 1940 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1941 trb_2, trb_3); 1942 } 1943 } 1944 1945 /* 1946 * Process events. 1947 * called from xhci_softintr 1948 */ 1949 static void 1950 xhci_handle_event(struct xhci_softc * const sc, 1951 const struct xhci_trb * const trb) 1952 { 1953 uint64_t trb_0; 1954 uint32_t trb_2, trb_3; 1955 1956 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1957 1958 KASSERT(mutex_owned(&sc->sc_lock)); 1959 1960 trb_0 = le64toh(trb->trb_0); 1961 trb_2 = le32toh(trb->trb_2); 1962 trb_3 = le32toh(trb->trb_3); 1963 1964 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1965 trb, trb_0, trb_2, trb_3); 1966 1967 /* 1968 * 4.11.3.1, 6.4.2.1 1969 * TRB Pointer is invalid for these completion codes. 1970 */ 1971 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 1972 case XHCI_TRB_ERROR_RING_UNDERRUN: 1973 case XHCI_TRB_ERROR_RING_OVERRUN: 1974 case XHCI_TRB_ERROR_VF_RING_FULL: 1975 return; 1976 default: 1977 if (trb_0 == 0) { 1978 return; 1979 } 1980 break; 1981 } 1982 1983 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 1984 case XHCI_TRB_EVENT_TRANSFER: 1985 xhci_event_transfer(sc, trb); 1986 break; 1987 case XHCI_TRB_EVENT_CMD_COMPLETE: 1988 xhci_event_cmd(sc, trb); 1989 break; 1990 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1991 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1992 break; 1993 default: 1994 break; 1995 } 1996 } 1997 1998 static void 1999 xhci_softintr(void *v) 2000 { 2001 struct usbd_bus * const bus = v; 2002 struct xhci_softc * const sc = bus->ub_hcpriv; 2003 struct xhci_ring * const er = &sc->sc_er; 2004 struct xhci_trb *trb; 2005 int i, j, k; 2006 2007 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2008 2009 i = er->xr_ep; 2010 j = er->xr_cs; 2011 2012 DPRINTFN(16, "xr_ep %d xr_cs %d", i, j, 0, 0); 2013 2014 while (1) { 2015 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2016 BUS_DMASYNC_POSTREAD); 2017 trb = &er->xr_trb[i]; 2018 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2019 2020 if (j != k) 2021 break; 2022 2023 xhci_handle_event(sc, trb); 2024 2025 i++; 2026 if (i == XHCI_EVENT_RING_TRBS) { 2027 i = 0; 2028 j ^= 1; 2029 } 2030 } 2031 2032 er->xr_ep = i; 2033 er->xr_cs = j; 2034 2035 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2036 XHCI_ERDP_LO_BUSY); 2037 2038 DPRINTFN(16, "ends", 0, 0, 0, 0); 2039 2040 return; 2041 } 2042 2043 static void 2044 xhci_poll(struct usbd_bus *bus) 2045 { 2046 struct xhci_softc * const sc = bus->ub_hcpriv; 2047 2048 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2049 2050 mutex_spin_enter(&sc->sc_intr_lock); 2051 xhci_intr1(sc); 2052 mutex_spin_exit(&sc->sc_intr_lock); 2053 2054 return; 2055 } 2056 2057 static struct usbd_xfer * 2058 xhci_allocx(struct usbd_bus *bus) 2059 { 2060 struct xhci_softc * const sc = bus->ub_hcpriv; 2061 struct usbd_xfer *xfer; 2062 2063 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2064 2065 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 2066 if (xfer != NULL) { 2067 memset(xfer, 0, sizeof(struct xhci_xfer)); 2068 #ifdef DIAGNOSTIC 2069 xfer->ux_state = XFER_BUSY; 2070 #endif 2071 } 2072 2073 return xfer; 2074 } 2075 2076 static void 2077 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2078 { 2079 struct xhci_softc * const sc = bus->ub_hcpriv; 2080 2081 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2082 2083 #ifdef DIAGNOSTIC 2084 if (xfer->ux_state != XFER_BUSY) { 2085 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 2086 xfer, xfer->ux_state, 0, 0); 2087 } 2088 xfer->ux_state = XFER_FREE; 2089 #endif 2090 pool_cache_put(sc->sc_xferpool, xfer); 2091 } 2092 2093 static void 2094 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2095 { 2096 struct xhci_softc * const sc = bus->ub_hcpriv; 2097 2098 *lock = &sc->sc_lock; 2099 } 2100 2101 extern uint32_t usb_cookie_no; 2102 2103 /* 2104 * Called if uhub_explore finds a new device (via usbd_new_device). 2105 * Allocate and construct dev structure of default endpoint (ep0). 2106 * Determine initial MaxPacketSize (mps) by speed. 2107 * Determine route string and roothub port for slot of dev. 2108 * Allocate pipe of ep0. 2109 * Enable and initialize slot and Set Address. 2110 * Read device descriptor. 2111 * Register this device. 2112 */ 2113 static usbd_status 2114 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2115 int speed, int port, struct usbd_port *up) 2116 { 2117 struct xhci_softc * const sc = bus->ub_hcpriv; 2118 struct usbd_device *dev; 2119 usbd_status err; 2120 usb_device_descriptor_t *dd; 2121 struct usbd_device *hub; 2122 struct usbd_device *adev; 2123 int rhport = 0; 2124 struct xhci_slot *xs; 2125 uint32_t *cp; 2126 uint32_t route = 0; 2127 uint8_t slot = 0; 2128 uint8_t addr; 2129 2130 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2131 DPRINTFN(4, "port=%d depth=%d speed=%d upport %d", 2132 port, depth, speed, up->up_portno); 2133 2134 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2135 if (dev == NULL) 2136 return USBD_NOMEM; 2137 2138 dev->ud_bus = bus; 2139 2140 /* Set up default endpoint handle. */ 2141 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2142 2143 /* Set up default endpoint descriptor. */ 2144 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2145 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2146 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2147 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2148 /* 4.3, 4.8.2.1 */ 2149 if (USB_IS_SS(speed)) { 2150 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2151 } else 2152 switch (speed) { 2153 case USB_SPEED_FULL: 2154 /* XXX using 64 as initial mps of ep0 in FS */ 2155 case USB_SPEED_HIGH: 2156 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2157 break; 2158 case USB_SPEED_LOW: 2159 default: 2160 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2161 break; 2162 } 2163 dev->ud_ep0desc.bInterval = 0; 2164 2165 /* doesn't matter, just don't let it uninitialized */ 2166 dev->ud_ep0.ue_toggle = 0; 2167 2168 DPRINTFN(4, "up %p portno %d", up, up->up_portno, 0, 0); 2169 2170 dev->ud_quirks = &usbd_no_quirk; 2171 dev->ud_addr = 0; 2172 dev->ud_ddesc.bMaxPacketSize = 0; 2173 dev->ud_depth = depth; 2174 dev->ud_powersrc = up; 2175 dev->ud_myhub = up->up_parent; 2176 2177 up->up_dev = dev; 2178 2179 /* Locate root hub port */ 2180 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2181 uint32_t dep; 2182 2183 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2184 hub, hub->ud_depth, hub->ud_powersrc, 2185 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2186 2187 if (hub->ud_powersrc == NULL) 2188 break; 2189 dep = hub->ud_depth; 2190 if (dep == 0) 2191 break; 2192 rhport = hub->ud_powersrc->up_portno; 2193 if (dep > USB_HUB_MAX_DEPTH) 2194 continue; 2195 2196 route |= 2197 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2198 << ((dep - 1) * 4); 2199 } 2200 route = route >> 4; 2201 DPRINTFN(4, "rhport %d Route %05x hub %p", rhport, route, hub, 0); 2202 2203 /* Locate port on upstream high speed hub */ 2204 for (adev = dev, hub = up->up_parent; 2205 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2206 adev = hub, hub = hub->ud_myhub) 2207 ; 2208 if (hub) { 2209 int p; 2210 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2211 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2212 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2213 goto found; 2214 } 2215 } 2216 panic("xhci_new_device: cannot find HS port"); 2217 found: 2218 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2219 } else { 2220 dev->ud_myhsport = NULL; 2221 } 2222 2223 dev->ud_speed = speed; 2224 dev->ud_langid = USBD_NOLANG; 2225 dev->ud_cookie.cookie = ++usb_cookie_no; 2226 2227 /* Establish the default pipe. */ 2228 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2229 &dev->ud_pipe0); 2230 if (err) { 2231 goto bad; 2232 } 2233 2234 dd = &dev->ud_ddesc; 2235 2236 if ((depth == 0) && (port == 0)) { 2237 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2238 bus->ub_devices[dev->ud_addr] = dev; 2239 err = usbd_get_initial_ddesc(dev, dd); 2240 if (err) 2241 goto bad; 2242 err = usbd_reload_device_desc(dev); 2243 if (err) 2244 goto bad; 2245 } else { 2246 err = xhci_enable_slot(sc, &slot); 2247 if (err) 2248 goto bad; 2249 xs = &sc->sc_slots[slot]; 2250 dev->ud_hcpriv = xs; 2251 err = xhci_init_slot(dev, slot, route, rhport); 2252 if (err) { 2253 dev->ud_hcpriv = NULL; 2254 /* 2255 * We have to disable_slot here because 2256 * xs->xs_idx == 0 when xhci_init_slot fails, 2257 * in that case usbd_remove_dev won't work. 2258 */ 2259 mutex_enter(&sc->sc_lock); 2260 xhci_disable_slot(sc, slot); 2261 mutex_exit(&sc->sc_lock); 2262 goto bad; 2263 } 2264 2265 /* Allow device time to set new address */ 2266 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2267 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2268 //hexdump("slot context", cp, sc->sc_ctxsz); 2269 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2270 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2271 /* XXX ensure we know when the hardware does something 2272 we can't yet cope with */ 2273 KASSERT(addr >= 1 && addr <= 127); 2274 dev->ud_addr = addr; 2275 /* XXX dev->ud_addr not necessarily unique on bus */ 2276 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2277 bus->ub_devices[dev->ud_addr] = dev; 2278 2279 err = usbd_get_initial_ddesc(dev, dd); 2280 if (err) 2281 goto bad; 2282 /* 4.8.2.1 */ 2283 if (USB_IS_SS(speed)) { 2284 if (dd->bMaxPacketSize != 9) { 2285 printf("%s: invalid mps 2^%u for SS ep0," 2286 " using 512\n", 2287 device_xname(sc->sc_dev), 2288 dd->bMaxPacketSize); 2289 dd->bMaxPacketSize = 9; 2290 } 2291 USETW(dev->ud_ep0desc.wMaxPacketSize, 2292 (1 << dd->bMaxPacketSize)); 2293 } else 2294 USETW(dev->ud_ep0desc.wMaxPacketSize, 2295 dd->bMaxPacketSize); 2296 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2297 xhci_update_ep0_mps(sc, xs, 2298 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2299 err = usbd_reload_device_desc(dev); 2300 if (err) 2301 goto bad; 2302 2303 #if 0 2304 /* Re-establish the default pipe with the new MPS. */ 2305 /* In xhci this is done by xhci_update_ep0_mps. */ 2306 usbd_kill_pipe(dev->ud_pipe0); 2307 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2308 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2309 #endif 2310 } 2311 2312 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2313 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2314 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2315 dd->bDeviceClass, dd->bDeviceSubClass, 2316 dd->bDeviceProtocol, 0); 2317 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2318 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2319 dev->ud_speed); 2320 2321 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2322 2323 if ((depth == 0) && (port == 0)) { 2324 usbd_attach_roothub(parent, dev); 2325 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2326 return USBD_NORMAL_COMPLETION; 2327 } 2328 2329 2330 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2331 bad: 2332 if (err != USBD_NORMAL_COMPLETION) { 2333 usbd_remove_device(dev, up); 2334 } 2335 2336 return err; 2337 } 2338 2339 static usbd_status 2340 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2341 size_t ntrb, size_t align) 2342 { 2343 usbd_status err; 2344 size_t size = ntrb * XHCI_TRB_SIZE; 2345 2346 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2347 2348 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2349 if (err) 2350 return err; 2351 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2352 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2353 xr->xr_trb = xhci_ring_trbv(xr, 0); 2354 xr->xr_ntrb = ntrb; 2355 xr->xr_ep = 0; 2356 xr->xr_cs = 1; 2357 memset(xr->xr_trb, 0, size); 2358 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 2359 xr->is_halted = false; 2360 2361 return USBD_NORMAL_COMPLETION; 2362 } 2363 2364 static void 2365 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2366 { 2367 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2368 mutex_destroy(&xr->xr_lock); 2369 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2370 } 2371 2372 static void 2373 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2374 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2375 { 2376 size_t i; 2377 u_int ri; 2378 u_int cs; 2379 uint64_t parameter; 2380 uint32_t status; 2381 uint32_t control; 2382 2383 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2384 2385 KASSERT(ntrbs <= XHCI_XFER_NTRB); 2386 for (i = 0; i < ntrbs; i++) { 2387 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2388 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2389 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2390 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2391 XHCI_TRB_TYPE_LINK); 2392 } 2393 2394 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2395 2396 ri = xr->xr_ep; 2397 cs = xr->xr_cs; 2398 2399 /* 2400 * Although the xhci hardware can do scatter/gather dma from 2401 * arbitrary sized buffers, there is a non-obvious restriction 2402 * that a LINK trb is only allowed at the end of a burst of 2403 * transfers - which might be 16kB. 2404 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2405 * The simple solution is not to allow a LINK trb in the middle 2406 * of anything - as here. 2407 * XXX: (dsl) There are xhci controllers out there (eg some made by 2408 * ASMedia) that seem to lock up if they process a LINK trb but 2409 * cannot process the linked-to trb yet. 2410 * The code should write the 'cycle' bit on the link trb AFTER 2411 * adding the other trb. 2412 */ 2413 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2414 parameter = xhci_ring_trbp(xr, 0); 2415 status = 0; 2416 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2417 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2418 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2419 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2420 BUS_DMASYNC_PREWRITE); 2421 xr->xr_cookies[ri] = NULL; 2422 xr->xr_ep = 0; 2423 xr->xr_cs ^= 1; 2424 ri = xr->xr_ep; 2425 cs = xr->xr_cs; 2426 } 2427 2428 ri++; 2429 2430 /* Write any subsequent TRB first */ 2431 for (i = 1; i < ntrbs; i++) { 2432 parameter = trbs[i].trb_0; 2433 status = trbs[i].trb_2; 2434 control = trbs[i].trb_3; 2435 2436 if (cs) { 2437 control |= XHCI_TRB_3_CYCLE_BIT; 2438 } else { 2439 control &= ~XHCI_TRB_3_CYCLE_BIT; 2440 } 2441 2442 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2443 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2444 BUS_DMASYNC_PREWRITE); 2445 xr->xr_cookies[ri] = cookie; 2446 ri++; 2447 } 2448 2449 /* Write the first TRB last */ 2450 i = 0; 2451 parameter = trbs[i].trb_0; 2452 status = trbs[i].trb_2; 2453 control = trbs[i].trb_3; 2454 2455 if (xr->xr_cs) { 2456 control |= XHCI_TRB_3_CYCLE_BIT; 2457 } else { 2458 control &= ~XHCI_TRB_3_CYCLE_BIT; 2459 } 2460 2461 xhci_trb_put(&xr->xr_trb[xr->xr_ep], parameter, status, control); 2462 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2463 BUS_DMASYNC_PREWRITE); 2464 xr->xr_cookies[xr->xr_ep] = cookie; 2465 2466 xr->xr_ep = ri; 2467 xr->xr_cs = cs; 2468 2469 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2470 } 2471 2472 /* 2473 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2474 * Command completion is notified by cv_signal from xhci_handle_event 2475 * (called from interrupt from xHCI), or timed-out. 2476 * Command validation is performed in xhci_handle_event by checking if 2477 * trb_0 in CMD_COMPLETE TRB and sc->sc_command_addr are identical. 2478 */ 2479 static usbd_status 2480 xhci_do_command1(struct xhci_softc * const sc, struct xhci_trb * const trb, 2481 int timeout, int locked) 2482 { 2483 struct xhci_ring * const cr = &sc->sc_cr; 2484 usbd_status err; 2485 2486 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2487 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2488 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2489 2490 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2491 2492 if (!locked) 2493 mutex_enter(&sc->sc_lock); 2494 2495 /* XXX KASSERT may fire when cv_timedwait unlocks sc_lock */ 2496 KASSERT(sc->sc_command_addr == 0); 2497 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2498 2499 mutex_enter(&cr->xr_lock); 2500 xhci_ring_put(sc, cr, NULL, trb, 1); 2501 mutex_exit(&cr->xr_lock); 2502 2503 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2504 2505 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2506 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2507 err = USBD_TIMEOUT; 2508 goto timedout; 2509 } 2510 2511 trb->trb_0 = sc->sc_result_trb.trb_0; 2512 trb->trb_2 = sc->sc_result_trb.trb_2; 2513 trb->trb_3 = sc->sc_result_trb.trb_3; 2514 2515 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2516 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2517 2518 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2519 case XHCI_TRB_ERROR_SUCCESS: 2520 err = USBD_NORMAL_COMPLETION; 2521 break; 2522 default: 2523 case 192 ... 223: 2524 err = USBD_IOERROR; 2525 break; 2526 case 224 ... 255: 2527 err = USBD_NORMAL_COMPLETION; 2528 break; 2529 } 2530 2531 timedout: 2532 sc->sc_command_addr = 0; 2533 if (!locked) 2534 mutex_exit(&sc->sc_lock); 2535 return err; 2536 } 2537 2538 static usbd_status 2539 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2540 int timeout) 2541 { 2542 return xhci_do_command1(sc, trb, timeout, 0); 2543 } 2544 2545 /* 2546 * This allows xhci_do_command with already sc_lock held. 2547 * This is needed as USB stack calls close methods with sc_lock_held. 2548 * (see usbdivar.h) 2549 */ 2550 static usbd_status 2551 xhci_do_command_locked(struct xhci_softc * const sc, 2552 struct xhci_trb * const trb, int timeout) 2553 { 2554 return xhci_do_command1(sc, trb, timeout, 1); 2555 } 2556 2557 static usbd_status 2558 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2559 { 2560 struct xhci_trb trb; 2561 usbd_status err; 2562 2563 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2564 2565 trb.trb_0 = 0; 2566 trb.trb_2 = 0; 2567 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2568 2569 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2570 if (err != USBD_NORMAL_COMPLETION) { 2571 return err; 2572 } 2573 2574 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2575 2576 return err; 2577 } 2578 2579 /* 2580 * Deallocate DMA buffer and ring buffer, and disable_slot. 2581 * Should be called with sc_lock held. 2582 */ 2583 static usbd_status 2584 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2585 { 2586 struct xhci_trb trb; 2587 struct xhci_slot *xs; 2588 2589 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2590 2591 if (sc->sc_dying) 2592 return USBD_IOERROR; 2593 2594 xs = &sc->sc_slots[slot]; 2595 if (xs->xs_idx != 0) { 2596 for (int i = XHCI_DCI_SLOT + 1; i < 32; i++) { 2597 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2598 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2599 } 2600 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2601 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2602 } 2603 2604 trb.trb_0 = 0; 2605 trb.trb_2 = 0; 2606 trb.trb_3 = htole32( 2607 XHCI_TRB_3_SLOT_SET(slot) | 2608 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2609 2610 return xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2611 } 2612 2613 /* 2614 * Change slot state. 2615 * bsr=0: ENABLED -> ADDRESSED 2616 * bsr=1: ENABLED -> DEFAULT 2617 * see xHCI 1.1 4.5.3, 3.3.4 2618 */ 2619 static usbd_status 2620 xhci_address_device(struct xhci_softc * const sc, 2621 uint64_t icp, uint8_t slot_id, bool bsr) 2622 { 2623 struct xhci_trb trb; 2624 usbd_status err; 2625 2626 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2627 2628 trb.trb_0 = icp; 2629 trb.trb_2 = 0; 2630 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2631 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2632 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2633 2634 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2635 2636 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2637 err = USBD_NO_ADDR; 2638 2639 return err; 2640 } 2641 2642 static usbd_status 2643 xhci_update_ep0_mps(struct xhci_softc * const sc, 2644 struct xhci_slot * const xs, u_int mps) 2645 { 2646 struct xhci_trb trb; 2647 usbd_status err; 2648 uint32_t * cp; 2649 2650 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2651 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2652 2653 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2654 cp[0] = htole32(0); 2655 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2656 2657 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2658 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2659 2660 /* sync input contexts before they are read from memory */ 2661 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2662 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2663 sc->sc_ctxsz * 4); 2664 2665 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2666 trb.trb_2 = 0; 2667 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2668 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2669 2670 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2671 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2672 return err; 2673 } 2674 2675 static void 2676 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2677 { 2678 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2679 2680 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2681 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2682 &dcbaa[si], dcba, si, 0); 2683 2684 dcbaa[si] = htole64(dcba); 2685 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2686 BUS_DMASYNC_PREWRITE); 2687 } 2688 2689 /* 2690 * Allocate DMA buffer and ring buffer for specified slot 2691 * and set Device Context Base Address 2692 * and issue Set Address device command. 2693 */ 2694 static usbd_status 2695 xhci_init_slot(struct usbd_device *dev, uint32_t slot, int route, int rhport) 2696 { 2697 struct xhci_softc * const sc = dev->ud_bus->ub_hcpriv; 2698 struct xhci_slot *xs; 2699 usbd_status err; 2700 u_int dci; 2701 uint32_t *cp; 2702 uint32_t mps = UGETW(dev->ud_ep0desc.wMaxPacketSize); 2703 2704 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2705 DPRINTFN(4, "slot %u speed %d rhport %d route %05x", 2706 slot, dev->ud_speed, route, rhport); 2707 2708 xs = &sc->sc_slots[slot]; 2709 2710 /* allocate contexts */ 2711 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2712 &xs->xs_dc_dma); 2713 if (err) 2714 return err; 2715 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2716 2717 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2718 &xs->xs_ic_dma); 2719 if (err) 2720 goto bad1; 2721 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2722 2723 for (dci = 0; dci < 32; dci++) { 2724 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2725 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2726 if (dci == XHCI_DCI_SLOT) 2727 continue; 2728 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2729 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2730 if (err) { 2731 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2732 goto bad2; 2733 } 2734 } 2735 2736 /* set up initial input control context */ 2737 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2738 cp[0] = htole32(0); 2739 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 2740 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2741 2742 /* set up input slot context */ 2743 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2744 xhci_setup_sctx(dev, cp); 2745 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(1)); 2746 cp[0] |= htole32(XHCI_SCTX_0_ROUTE_SET(route)); 2747 cp[1] |= htole32(XHCI_SCTX_1_RH_PORT_SET(rhport)); 2748 2749 /* set up input EP0 context */ 2750 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2751 cp[0] = htole32(0); 2752 cp[1] = htole32( 2753 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 2754 XHCI_EPCTX_1_EPTYPE_SET(4) | 2755 XHCI_EPCTX_1_CERR_SET(3) 2756 ); 2757 /* can't use xhci_ep_get_dci() yet? */ 2758 *(uint64_t *)(&cp[2]) = htole64( 2759 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 2760 XHCI_EPCTX_2_DCS_SET(1)); 2761 cp[4] = htole32( 2762 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 2763 ); 2764 2765 /* sync input contexts before they are read from memory */ 2766 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2767 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2768 sc->sc_ctxsz * 3); 2769 2770 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2771 2772 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 2773 false); 2774 2775 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2776 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2777 sc->sc_ctxsz * 2); 2778 2779 bad2: 2780 if (err == USBD_NORMAL_COMPLETION) { 2781 xs->xs_idx = slot; 2782 } else { 2783 for (int i = 1; i < dci; i++) { 2784 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2785 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2786 } 2787 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2788 bad1: 2789 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2790 xs->xs_idx = 0; 2791 } 2792 2793 return err; 2794 } 2795 2796 /* ----- */ 2797 2798 static void 2799 xhci_noop(struct usbd_pipe *pipe) 2800 { 2801 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2802 } 2803 2804 /* 2805 * Process root hub request. 2806 */ 2807 static int 2808 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2809 void *buf, int buflen) 2810 { 2811 struct xhci_softc * const sc = bus->ub_hcpriv; 2812 usb_port_status_t ps; 2813 int l, totlen = 0; 2814 uint16_t len, value, index; 2815 int port, i; 2816 uint32_t v; 2817 2818 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2819 2820 if (sc->sc_dying) 2821 return -1; 2822 2823 len = UGETW(req->wLength); 2824 value = UGETW(req->wValue); 2825 index = UGETW(req->wIndex); 2826 2827 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 2828 req->bmRequestType | (req->bRequest << 8), value, index, len); 2829 2830 #define C(x,y) ((x) | ((y) << 8)) 2831 switch (C(req->bRequest, req->bmRequestType)) { 2832 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2833 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 2834 if (len == 0) 2835 break; 2836 switch (value) { 2837 case C(0, UDESC_DEVICE): { 2838 usb_device_descriptor_t devd; 2839 totlen = min(buflen, sizeof(devd)); 2840 memcpy(&devd, buf, totlen); 2841 USETW(devd.idVendor, sc->sc_id_vendor); 2842 memcpy(buf, &devd, totlen); 2843 break; 2844 } 2845 #define sd ((usb_string_descriptor_t *)buf) 2846 case C(1, UDESC_STRING): 2847 /* Vendor */ 2848 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2849 break; 2850 case C(2, UDESC_STRING): 2851 /* Product */ 2852 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 2853 break; 2854 #undef sd 2855 default: 2856 /* default from usbroothub */ 2857 return buflen; 2858 } 2859 break; 2860 2861 /* Hub requests */ 2862 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2863 break; 2864 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2865 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2866 index, value, 0, 0); 2867 if (index < 1 || index > sc->sc_maxports) { 2868 return -1; 2869 } 2870 port = XHCI_PORTSC(index); 2871 v = xhci_op_read_4(sc, port); 2872 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2873 v &= ~XHCI_PS_CLEAR; 2874 switch (value) { 2875 case UHF_PORT_ENABLE: 2876 xhci_op_write_4(sc, port, v &~ XHCI_PS_PED); 2877 break; 2878 case UHF_PORT_SUSPEND: 2879 return -1; 2880 case UHF_PORT_POWER: 2881 break; 2882 case UHF_PORT_TEST: 2883 case UHF_PORT_INDICATOR: 2884 return -1; 2885 case UHF_C_PORT_CONNECTION: 2886 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2887 break; 2888 case UHF_C_PORT_ENABLE: 2889 case UHF_C_PORT_SUSPEND: 2890 case UHF_C_PORT_OVER_CURRENT: 2891 return -1; 2892 case UHF_C_BH_PORT_RESET: 2893 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 2894 break; 2895 case UHF_C_PORT_RESET: 2896 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2897 break; 2898 case UHF_C_PORT_LINK_STATE: 2899 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 2900 break; 2901 case UHF_C_PORT_CONFIG_ERROR: 2902 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 2903 break; 2904 default: 2905 return -1; 2906 } 2907 break; 2908 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2909 if (len == 0) 2910 break; 2911 if ((value & 0xff) != 0) { 2912 return -1; 2913 } 2914 usb_hub_descriptor_t hubd; 2915 2916 totlen = min(buflen, sizeof(hubd)); 2917 memcpy(&hubd, buf, totlen); 2918 hubd.bNbrPorts = sc->sc_maxports; 2919 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2920 hubd.bPwrOn2PwrGood = 200; 2921 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 2922 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2923 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2924 totlen = min(totlen, hubd.bDescLength); 2925 memcpy(buf, &hubd, totlen); 2926 break; 2927 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2928 if (len != 4) { 2929 return -1; 2930 } 2931 memset(buf, 0, len); /* ? XXX */ 2932 totlen = len; 2933 break; 2934 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2935 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2936 if (index < 1 || index > sc->sc_maxports) { 2937 return -1; 2938 } 2939 if (len != 4) { 2940 return -1; 2941 } 2942 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 2943 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 2944 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 2945 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2946 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2947 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2948 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 2949 if (v & XHCI_PS_PR) i |= UPS_RESET; 2950 if (v & XHCI_PS_PP) { 2951 if (i & UPS_OTHER_SPEED) 2952 i |= UPS_PORT_POWER_SS; 2953 else 2954 i |= UPS_PORT_POWER; 2955 } 2956 if (i & UPS_OTHER_SPEED) 2957 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 2958 if (sc->sc_vendor_port_status) 2959 i = sc->sc_vendor_port_status(sc, v, i); 2960 USETW(ps.wPortStatus, i); 2961 i = 0; 2962 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2963 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2964 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2965 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2966 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 2967 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 2968 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 2969 USETW(ps.wPortChange, i); 2970 totlen = min(len, sizeof(ps)); 2971 memcpy(buf, &ps, totlen); 2972 break; 2973 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2974 return -1; 2975 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 2976 break; 2977 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2978 break; 2979 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 2980 int optval = (index >> 8) & 0xff; 2981 index &= 0xff; 2982 if (index < 1 || index > sc->sc_maxports) { 2983 return -1; 2984 } 2985 port = XHCI_PORTSC(index); 2986 v = xhci_op_read_4(sc, port); 2987 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2988 v &= ~XHCI_PS_CLEAR; 2989 switch (value) { 2990 case UHF_PORT_ENABLE: 2991 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 2992 break; 2993 case UHF_PORT_SUSPEND: 2994 /* XXX suspend */ 2995 break; 2996 case UHF_PORT_RESET: 2997 v &= ~ (XHCI_PS_PED | XHCI_PS_PR); 2998 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 2999 /* Wait for reset to complete. */ 3000 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3001 if (sc->sc_dying) { 3002 return -1; 3003 } 3004 v = xhci_op_read_4(sc, port); 3005 if (v & XHCI_PS_PR) { 3006 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3007 usb_delay_ms(&sc->sc_bus, 10); 3008 /* XXX */ 3009 } 3010 break; 3011 case UHF_PORT_POWER: 3012 /* XXX power control */ 3013 break; 3014 /* XXX more */ 3015 case UHF_C_PORT_RESET: 3016 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3017 break; 3018 case UHF_PORT_U1_TIMEOUT: 3019 if (USB_IS_SS(xhci_xspeed2speed(XHCI_PS_SPEED_GET(v)))){ 3020 return -1; 3021 } 3022 port = XHCI_PORTPMSC(index); 3023 v = xhci_op_read_4(sc, port); 3024 v &= ~XHCI_PM3_U1TO_SET(0xff); 3025 v |= XHCI_PM3_U1TO_SET(optval); 3026 xhci_op_write_4(sc, port, v); 3027 break; 3028 case UHF_PORT_U2_TIMEOUT: 3029 if (USB_IS_SS(xhci_xspeed2speed(XHCI_PS_SPEED_GET(v)))){ 3030 return -1; 3031 } 3032 port = XHCI_PORTPMSC(index); 3033 v = xhci_op_read_4(sc, port); 3034 v &= ~XHCI_PM3_U2TO_SET(0xff); 3035 v |= XHCI_PM3_U2TO_SET(optval); 3036 xhci_op_write_4(sc, port, v); 3037 break; 3038 default: 3039 return -1; 3040 } 3041 } 3042 break; 3043 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3044 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3045 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3046 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3047 break; 3048 default: 3049 /* default from usbroothub */ 3050 return buflen; 3051 } 3052 3053 return totlen; 3054 } 3055 3056 /* root hub interrupt */ 3057 3058 static usbd_status 3059 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3060 { 3061 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3062 usbd_status err; 3063 3064 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3065 3066 /* Insert last in queue. */ 3067 mutex_enter(&sc->sc_lock); 3068 err = usb_insert_transfer(xfer); 3069 mutex_exit(&sc->sc_lock); 3070 if (err) 3071 return err; 3072 3073 /* Pipe isn't running, start first */ 3074 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3075 } 3076 3077 /* Wait for roothub port status/change */ 3078 static usbd_status 3079 xhci_root_intr_start(struct usbd_xfer *xfer) 3080 { 3081 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3082 3083 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3084 3085 if (sc->sc_dying) 3086 return USBD_IOERROR; 3087 3088 mutex_enter(&sc->sc_lock); 3089 sc->sc_intrxfer = xfer; 3090 mutex_exit(&sc->sc_lock); 3091 3092 return USBD_IN_PROGRESS; 3093 } 3094 3095 static void 3096 xhci_root_intr_abort(struct usbd_xfer *xfer) 3097 { 3098 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3099 3100 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3101 3102 KASSERT(mutex_owned(&sc->sc_lock)); 3103 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3104 3105 sc->sc_intrxfer = NULL; 3106 3107 xfer->ux_status = USBD_CANCELLED; 3108 usb_transfer_complete(xfer); 3109 } 3110 3111 static void 3112 xhci_root_intr_close(struct usbd_pipe *pipe) 3113 { 3114 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 3115 3116 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3117 3118 KASSERT(mutex_owned(&sc->sc_lock)); 3119 3120 sc->sc_intrxfer = NULL; 3121 } 3122 3123 static void 3124 xhci_root_intr_done(struct usbd_xfer *xfer) 3125 { 3126 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3127 3128 xfer->ux_hcpriv = NULL; 3129 } 3130 3131 /* -------------- */ 3132 /* device control */ 3133 3134 static usbd_status 3135 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3136 { 3137 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3138 usbd_status err; 3139 3140 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3141 3142 /* Insert last in queue. */ 3143 mutex_enter(&sc->sc_lock); 3144 err = usb_insert_transfer(xfer); 3145 mutex_exit(&sc->sc_lock); 3146 if (err) 3147 return err; 3148 3149 /* Pipe isn't running, start first */ 3150 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3151 } 3152 3153 static usbd_status 3154 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3155 { 3156 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3157 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3158 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3159 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3160 struct xhci_xfer * const xx = (void *)xfer; 3161 usb_device_request_t * const req = &xfer->ux_request; 3162 const int isread = usbd_xfer_isread(xfer); 3163 const uint32_t len = UGETW(req->wLength); 3164 usb_dma_t * const dma = &xfer->ux_dmabuf; 3165 uint64_t parameter; 3166 uint32_t status; 3167 uint32_t control; 3168 u_int i; 3169 3170 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3171 DPRINTFN(12, "req: %04x %04x %04x %04x", 3172 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3173 UGETW(req->wIndex), UGETW(req->wLength)); 3174 3175 #if 0 /* event handler does this */ 3176 /* XXX */ 3177 if (tr->is_halted) { 3178 DPRINTFN(1, "ctrl xfer %p halted: slot %u dci %u", 3179 xfer, xs->xs_idx, dci, 0); 3180 xhci_reset_endpoint(xfer->ux_pipe); 3181 tr->is_halted = false; 3182 xhci_set_dequeue(xfer->ux_pipe); 3183 } 3184 #endif 3185 3186 /* we rely on the bottom bits for extra info */ 3187 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 3188 3189 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3190 3191 i = 0; 3192 3193 /* setup phase */ 3194 memcpy(¶meter, req, sizeof(*req)); 3195 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3196 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3197 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3198 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3199 XHCI_TRB_3_IDT_BIT; 3200 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3201 3202 if (len == 0) 3203 goto no_data; 3204 3205 /* data phase */ 3206 parameter = DMAADDR(dma, 0); 3207 KASSERT(len <= 0x10000); 3208 status = XHCI_TRB_2_IRQ_SET(0) | 3209 XHCI_TRB_2_TDSZ_SET(1) | 3210 XHCI_TRB_2_BYTES_SET(len); 3211 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3212 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3213 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3214 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3215 3216 parameter = (uintptr_t)xfer | 0x3; 3217 status = XHCI_TRB_2_IRQ_SET(0); 3218 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3219 XHCI_TRB_3_IOC_BIT; 3220 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3221 3222 no_data: 3223 parameter = 0; 3224 status = XHCI_TRB_2_IRQ_SET(0); 3225 /* the status stage has inverted direction */ 3226 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3227 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3228 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3229 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3230 3231 parameter = (uintptr_t)xfer | 0x0; 3232 status = XHCI_TRB_2_IRQ_SET(0); 3233 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3234 XHCI_TRB_3_IOC_BIT; 3235 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3236 3237 mutex_enter(&tr->xr_lock); 3238 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3239 mutex_exit(&tr->xr_lock); 3240 3241 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3242 3243 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3244 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3245 xhci_timeout, xfer); 3246 } 3247 3248 if (sc->sc_bus.ub_usepolling) { 3249 DPRINTFN(1, "polling", 0, 0, 0, 0); 3250 //xhci_waitintr(sc, xfer); 3251 } 3252 3253 return USBD_IN_PROGRESS; 3254 } 3255 3256 static void 3257 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3258 { 3259 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3260 3261 callout_stop(&xfer->ux_callout); /* XXX wrong place */ 3262 3263 } 3264 3265 static void 3266 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3267 { 3268 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3269 3270 xhci_abort_xfer(xfer, USBD_CANCELLED); 3271 } 3272 3273 static void 3274 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3275 { 3276 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3277 3278 xhci_close_pipe(pipe); 3279 } 3280 3281 /* ------------------ */ 3282 /* device isochronous */ 3283 3284 /* ----------- */ 3285 /* device bulk */ 3286 3287 static usbd_status 3288 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3289 { 3290 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3291 usbd_status err; 3292 3293 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3294 3295 /* Insert last in queue. */ 3296 mutex_enter(&sc->sc_lock); 3297 err = usb_insert_transfer(xfer); 3298 mutex_exit(&sc->sc_lock); 3299 if (err) 3300 return err; 3301 3302 /* 3303 * Pipe isn't running (otherwise err would be USBD_INPROG), 3304 * so start it first. 3305 */ 3306 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3307 } 3308 3309 static usbd_status 3310 xhci_device_bulk_start(struct usbd_xfer *xfer) 3311 { 3312 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3313 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3314 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3315 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3316 struct xhci_xfer * const xx = (void *)xfer; 3317 const uint32_t len = xfer->ux_length; 3318 usb_dma_t * const dma = &xfer->ux_dmabuf; 3319 uint64_t parameter; 3320 uint32_t status; 3321 uint32_t control; 3322 u_int i = 0; 3323 3324 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3325 3326 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3327 3328 if (sc->sc_dying) 3329 return USBD_IOERROR; 3330 3331 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3332 3333 parameter = DMAADDR(dma, 0); 3334 /* 3335 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3336 * If the user supplied buffer crosses such a boundary then 2 3337 * (or more) TRB should be used. 3338 * If multiple TRB are used the td_size field must be set correctly. 3339 * For v1.0 devices (like ivy bridge) this is the number of usb data 3340 * blocks needed to complete the transfer. 3341 * Setting it to 1 in the last TRB causes an extra zero-length 3342 * data block be sent. 3343 * The earlier documentation differs, I don't know how it behaves. 3344 */ 3345 KASSERT(len <= 0x10000); 3346 status = XHCI_TRB_2_IRQ_SET(0) | 3347 XHCI_TRB_2_TDSZ_SET(1) | 3348 XHCI_TRB_2_BYTES_SET(len); 3349 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3350 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3351 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3352 3353 mutex_enter(&tr->xr_lock); 3354 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3355 mutex_exit(&tr->xr_lock); 3356 3357 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3358 3359 if (sc->sc_bus.ub_usepolling) { 3360 DPRINTFN(1, "polling", 0, 0, 0, 0); 3361 //xhci_waitintr(sc, xfer); 3362 } 3363 3364 return USBD_IN_PROGRESS; 3365 } 3366 3367 static void 3368 xhci_device_bulk_done(struct usbd_xfer *xfer) 3369 { 3370 #ifdef USB_DEBUG 3371 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3372 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3373 #endif 3374 const int isread = usbd_xfer_isread(xfer); 3375 3376 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3377 3378 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3379 3380 callout_stop(&xfer->ux_callout); /* XXX wrong place */ 3381 3382 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3383 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3384 } 3385 3386 static void 3387 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3388 { 3389 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3390 3391 xhci_abort_xfer(xfer, USBD_CANCELLED); 3392 } 3393 3394 static void 3395 xhci_device_bulk_close(struct usbd_pipe *pipe) 3396 { 3397 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3398 3399 xhci_close_pipe(pipe); 3400 } 3401 3402 /* ---------------- */ 3403 /* device interrupt */ 3404 3405 static usbd_status 3406 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3407 { 3408 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3409 usbd_status err; 3410 3411 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3412 3413 /* Insert last in queue. */ 3414 mutex_enter(&sc->sc_lock); 3415 err = usb_insert_transfer(xfer); 3416 mutex_exit(&sc->sc_lock); 3417 if (err) 3418 return err; 3419 3420 /* 3421 * Pipe isn't running (otherwise err would be USBD_INPROG), 3422 * so start it first. 3423 */ 3424 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3425 } 3426 3427 static usbd_status 3428 xhci_device_intr_start(struct usbd_xfer *xfer) 3429 { 3430 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3431 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3432 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3433 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3434 struct xhci_xfer * const xx = (void *)xfer; 3435 const uint32_t len = xfer->ux_length; 3436 usb_dma_t * const dma = &xfer->ux_dmabuf; 3437 uint64_t parameter; 3438 uint32_t status; 3439 uint32_t control; 3440 u_int i = 0; 3441 3442 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3443 3444 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3445 3446 if (sc->sc_dying) 3447 return USBD_IOERROR; 3448 3449 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3450 3451 parameter = DMAADDR(dma, 0); 3452 KASSERT(len <= 0x10000); 3453 status = XHCI_TRB_2_IRQ_SET(0) | 3454 XHCI_TRB_2_TDSZ_SET(1) | 3455 XHCI_TRB_2_BYTES_SET(len); 3456 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3457 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3458 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3459 3460 mutex_enter(&tr->xr_lock); 3461 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3462 mutex_exit(&tr->xr_lock); 3463 3464 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3465 3466 if (sc->sc_bus.ub_usepolling) { 3467 DPRINTFN(1, "polling", 0, 0, 0, 0); 3468 //xhci_waitintr(sc, xfer); 3469 } 3470 3471 return USBD_IN_PROGRESS; 3472 } 3473 3474 static void 3475 xhci_device_intr_done(struct usbd_xfer *xfer) 3476 { 3477 struct xhci_softc * const sc __diagused = 3478 xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3479 #ifdef USB_DEBUG 3480 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3481 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3482 #endif 3483 const int isread = usbd_xfer_isread(xfer); 3484 3485 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3486 3487 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3488 3489 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3490 3491 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3492 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3493 3494 #if 0 3495 device_printf(sc->sc_dev, ""); 3496 for (size_t i = 0; i < xfer->ux_length; i++) { 3497 printf(" %02x", ((uint8_t const *)xfer->ux_buffer)[i]); 3498 } 3499 printf("\n"); 3500 #endif 3501 3502 if (xfer->ux_pipe->up_repeat) { 3503 xfer->ux_status = xhci_device_intr_start(xfer); 3504 } else { 3505 callout_stop(&xfer->ux_callout); /* XXX */ 3506 } 3507 3508 } 3509 3510 static void 3511 xhci_device_intr_abort(struct usbd_xfer *xfer) 3512 { 3513 struct xhci_softc * const sc __diagused = 3514 xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3515 3516 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3517 3518 KASSERT(mutex_owned(&sc->sc_lock)); 3519 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3520 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3521 xhci_abort_xfer(xfer, USBD_CANCELLED); 3522 } 3523 3524 static void 3525 xhci_device_intr_close(struct usbd_pipe *pipe) 3526 { 3527 //struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 3528 3529 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3530 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3531 3532 xhci_close_pipe(pipe); 3533 } 3534 3535 /* ------------ */ 3536 3537 static void 3538 xhci_timeout(void *addr) 3539 { 3540 struct xhci_xfer * const xx = addr; 3541 struct usbd_xfer * const xfer = &xx->xx_xfer; 3542 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3543 3544 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3545 3546 if (sc->sc_dying) { 3547 return; 3548 } 3549 3550 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 3551 USB_TASKQ_MPSAFE); 3552 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 3553 USB_TASKQ_HC); 3554 } 3555 3556 static void 3557 xhci_timeout_task(void *addr) 3558 { 3559 struct usbd_xfer * const xfer = addr; 3560 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3561 3562 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3563 3564 mutex_enter(&sc->sc_lock); 3565 #if 0 3566 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3567 #else 3568 xfer->ux_status = USBD_TIMEOUT; 3569 usb_transfer_complete(xfer); 3570 #endif 3571 mutex_exit(&sc->sc_lock); 3572 } 3573
Indexes created Wed Oct 01 18:09:54 GMT 2025