xhci.c revision 1.28.2.54
1 /* $NetBSD: xhci.c,v 1.28.2.54 2016/03/19 11:30:21 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 3.1 specification 31 * http://www.usb.org/developers/docs/usb_31_040315.zip 32 * USB rev 2.0 specification 33 * http://www.usb.org/developers/docs/usb20_docs/usb_20_031815.zip 34 * xHCI rev 1.1 specification 35 * http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.28.2.54 2016/03/19 11:30:21 skrll Exp $"); 40 41 #include "opt_usb.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 146 147 static usbd_status xhci_do_command(struct xhci_softc * const, 148 struct xhci_trb * const, int); 149 static usbd_status xhci_do_command1(struct xhci_softc * const, 150 struct xhci_trb * const, int, int); 151 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 152 struct xhci_trb * const, int); 153 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t, int, int); 154 static usbd_status xhci_enable_slot(struct xhci_softc * const, 155 uint8_t * const); 156 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 157 static usbd_status xhci_address_device(struct xhci_softc * const, 158 uint64_t, uint8_t, bool); 159 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 160 struct xhci_slot * const, u_int); 161 static usbd_status xhci_ring_init(struct xhci_softc * const, 162 struct xhci_ring * const, size_t, size_t); 163 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 164 165 static void xhci_noop(struct usbd_pipe *); 166 167 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 168 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 169 static void xhci_root_intr_abort(struct usbd_xfer *); 170 static void xhci_root_intr_close(struct usbd_pipe *); 171 static void xhci_root_intr_done(struct usbd_xfer *); 172 173 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 174 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 175 static void xhci_device_ctrl_abort(struct usbd_xfer *); 176 static void xhci_device_ctrl_close(struct usbd_pipe *); 177 static void xhci_device_ctrl_done(struct usbd_xfer *); 178 179 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 180 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 181 static void xhci_device_intr_abort(struct usbd_xfer *); 182 static void xhci_device_intr_close(struct usbd_pipe *); 183 static void xhci_device_intr_done(struct usbd_xfer *); 184 185 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 186 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 187 static void xhci_device_bulk_abort(struct usbd_xfer *); 188 static void xhci_device_bulk_close(struct usbd_pipe *); 189 static void xhci_device_bulk_done(struct usbd_xfer *); 190 191 static void xhci_timeout(void *); 192 static void xhci_timeout_task(void *); 193 194 static const struct usbd_bus_methods xhci_bus_methods = { 195 .ubm_open = xhci_open, 196 .ubm_softint = xhci_softintr, 197 .ubm_dopoll = xhci_poll, 198 .ubm_allocx = xhci_allocx, 199 .ubm_freex = xhci_freex, 200 .ubm_getlock = xhci_get_lock, 201 .ubm_newdev = xhci_new_device, 202 .ubm_rhctrl = xhci_roothub_ctrl, 203 }; 204 205 static const struct usbd_pipe_methods xhci_root_intr_methods = { 206 .upm_transfer = xhci_root_intr_transfer, 207 .upm_start = xhci_root_intr_start, 208 .upm_abort = xhci_root_intr_abort, 209 .upm_close = xhci_root_intr_close, 210 .upm_cleartoggle = xhci_noop, 211 .upm_done = xhci_root_intr_done, 212 }; 213 214 215 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 216 .upm_transfer = xhci_device_ctrl_transfer, 217 .upm_start = xhci_device_ctrl_start, 218 .upm_abort = xhci_device_ctrl_abort, 219 .upm_close = xhci_device_ctrl_close, 220 .upm_cleartoggle = xhci_noop, 221 .upm_done = xhci_device_ctrl_done, 222 }; 223 224 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 225 .upm_cleartoggle = xhci_noop, 226 }; 227 228 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 229 .upm_transfer = xhci_device_bulk_transfer, 230 .upm_start = xhci_device_bulk_start, 231 .upm_abort = xhci_device_bulk_abort, 232 .upm_close = xhci_device_bulk_close, 233 .upm_cleartoggle = xhci_noop, 234 .upm_done = xhci_device_bulk_done, 235 }; 236 237 static const struct usbd_pipe_methods xhci_device_intr_methods = { 238 .upm_transfer = xhci_device_intr_transfer, 239 .upm_start = xhci_device_intr_start, 240 .upm_abort = xhci_device_intr_abort, 241 .upm_close = xhci_device_intr_close, 242 .upm_cleartoggle = xhci_noop, 243 .upm_done = xhci_device_intr_done, 244 }; 245 246 static inline uint32_t 247 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 248 { 249 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 250 } 251 252 static inline uint32_t 253 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 254 { 255 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 256 } 257 258 static inline void 259 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 260 uint32_t value) 261 { 262 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 263 } 264 265 #if 0 /* unused */ 266 static inline void 267 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 268 uint32_t value) 269 { 270 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 271 } 272 #endif /* unused */ 273 274 static inline uint32_t 275 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 276 { 277 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 278 } 279 280 static inline uint32_t 281 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 282 { 283 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 284 } 285 286 static inline void 287 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 288 uint32_t value) 289 { 290 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 291 } 292 293 #if 0 /* unused */ 294 static inline uint64_t 295 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 296 { 297 uint64_t value; 298 299 if (sc->sc_ac64) { 300 #ifdef XHCI_USE_BUS_SPACE_8 301 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 302 #else 303 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 304 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 305 offset + 4) << 32; 306 #endif 307 } else { 308 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 309 } 310 311 return value; 312 } 313 #endif /* unused */ 314 315 static inline void 316 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 317 uint64_t value) 318 { 319 if (sc->sc_ac64) { 320 #ifdef XHCI_USE_BUS_SPACE_8 321 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 322 #else 323 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 324 (value >> 0) & 0xffffffff); 325 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 326 (value >> 32) & 0xffffffff); 327 #endif 328 } else { 329 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 330 } 331 } 332 333 static inline uint32_t 334 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 335 { 336 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 337 } 338 339 static inline void 340 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 341 uint32_t value) 342 { 343 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 344 } 345 346 #if 0 /* unused */ 347 static inline uint64_t 348 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 349 { 350 uint64_t value; 351 352 if (sc->sc_ac64) { 353 #ifdef XHCI_USE_BUS_SPACE_8 354 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 355 #else 356 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 357 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 358 offset + 4) << 32; 359 #endif 360 } else { 361 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 362 } 363 364 return value; 365 } 366 #endif /* unused */ 367 368 static inline void 369 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 370 uint64_t value) 371 { 372 if (sc->sc_ac64) { 373 #ifdef XHCI_USE_BUS_SPACE_8 374 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 375 #else 376 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 377 (value >> 0) & 0xffffffff); 378 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 379 (value >> 32) & 0xffffffff); 380 #endif 381 } else { 382 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 383 } 384 } 385 386 #if 0 /* unused */ 387 static inline uint32_t 388 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 389 { 390 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 391 } 392 #endif /* unused */ 393 394 static inline void 395 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 396 uint32_t value) 397 { 398 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 399 } 400 401 /* --- */ 402 403 static inline uint8_t 404 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 405 { 406 u_int eptype = 0; 407 408 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 409 case UE_CONTROL: 410 eptype = 0x0; 411 break; 412 case UE_ISOCHRONOUS: 413 eptype = 0x1; 414 break; 415 case UE_BULK: 416 eptype = 0x2; 417 break; 418 case UE_INTERRUPT: 419 eptype = 0x3; 420 break; 421 } 422 423 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 424 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 425 return eptype | 0x4; 426 else 427 return eptype; 428 } 429 430 static u_int 431 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 432 { 433 /* xHCI 1.0 section 4.5.1 */ 434 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 435 u_int in = 0; 436 437 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 438 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 439 in = 1; 440 441 return epaddr * 2 + in; 442 } 443 444 static inline u_int 445 xhci_dci_to_ici(const u_int i) 446 { 447 return i + 1; 448 } 449 450 static inline void * 451 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 452 const u_int dci) 453 { 454 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 455 } 456 457 #if 0 /* unused */ 458 static inline bus_addr_t 459 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 460 const u_int dci) 461 { 462 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 463 } 464 #endif /* unused */ 465 466 static inline void * 467 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 468 const u_int ici) 469 { 470 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 471 } 472 473 static inline bus_addr_t 474 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 475 const u_int ici) 476 { 477 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 478 } 479 480 static inline struct xhci_trb * 481 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 482 { 483 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 484 } 485 486 static inline bus_addr_t 487 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 488 { 489 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 490 } 491 492 static inline void 493 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 494 uint32_t control) 495 { 496 trb->trb_0 = htole64(parameter); 497 trb->trb_2 = htole32(status); 498 trb->trb_3 = htole32(control); 499 } 500 501 /* --- */ 502 503 void 504 xhci_childdet(device_t self, device_t child) 505 { 506 struct xhci_softc * const sc = device_private(self); 507 508 KASSERT(sc->sc_child == child); 509 if (child == sc->sc_child) 510 sc->sc_child = NULL; 511 } 512 513 int 514 xhci_detach(struct xhci_softc *sc, int flags) 515 { 516 int rv = 0; 517 518 if (sc->sc_child != NULL) 519 rv = config_detach(sc->sc_child, flags); 520 521 if (rv != 0) 522 return rv; 523 524 /* XXX unconfigure/free slots */ 525 526 /* verify: */ 527 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 528 xhci_op_write_4(sc, XHCI_USBCMD, 0); 529 /* do we need to wait for stop? */ 530 531 xhci_op_write_8(sc, XHCI_CRCR, 0); 532 xhci_ring_free(sc, &sc->sc_cr); 533 cv_destroy(&sc->sc_command_cv); 534 535 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 536 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 537 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 538 xhci_ring_free(sc, &sc->sc_er); 539 540 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 541 542 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 543 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 544 545 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 546 547 mutex_destroy(&sc->sc_lock); 548 mutex_destroy(&sc->sc_intr_lock); 549 cv_destroy(&sc->sc_softwake_cv); 550 551 pool_cache_destroy(sc->sc_xferpool); 552 553 return rv; 554 } 555 556 int 557 xhci_activate(device_t self, enum devact act) 558 { 559 struct xhci_softc * const sc = device_private(self); 560 561 switch (act) { 562 case DVACT_DEACTIVATE: 563 sc->sc_dying = true; 564 return 0; 565 default: 566 return EOPNOTSUPP; 567 } 568 } 569 570 bool 571 xhci_suspend(device_t dv, const pmf_qual_t *qual) 572 { 573 return false; 574 } 575 576 bool 577 xhci_resume(device_t dv, const pmf_qual_t *qual) 578 { 579 return false; 580 } 581 582 bool 583 xhci_shutdown(device_t self, int flags) 584 { 585 return false; 586 } 587 588 589 static void 590 hexdump(const char *msg, const void *base, size_t len) 591 { 592 #if 0 593 size_t cnt; 594 const uint32_t *p; 595 extern paddr_t vtophys(vaddr_t); 596 597 p = base; 598 cnt = 0; 599 600 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 601 (void *)vtophys((vaddr_t)base)); 602 603 while (cnt < len) { 604 if (cnt % 16 == 0) 605 printf("%p: ", p); 606 else if (cnt % 8 == 0) 607 printf(" |"); 608 printf(" %08x", *p++); 609 cnt += 4; 610 if (cnt % 16 == 0) 611 printf("\n"); 612 } 613 #endif 614 } 615 616 #define XHCI_HCCPREV1_BITS \ 617 "\177\020" /* New bitmask */ \ 618 "f\020\020XECP\0" \ 619 "f\014\4MAXPSA\0" \ 620 "b\013CFC\0" \ 621 "b\012SEC\0" \ 622 "b\011SBD\0" \ 623 "b\010FSE\0" \ 624 "b\7NSS\0" \ 625 "b\6LTC\0" \ 626 "b\5LHRC\0" \ 627 "b\4PIND\0" \ 628 "b\3PPC\0" \ 629 "b\2CZC\0" \ 630 "b\1BNC\0" \ 631 "b\0AC64\0" \ 632 "\0" 633 #define XHCI_HCCV1_x_BITS \ 634 "\177\020" /* New bitmask */ \ 635 "f\020\020XECP\0" \ 636 "f\014\4MAXPSA\0" \ 637 "b\013CFC\0" \ 638 "b\012SEC\0" \ 639 "b\011SPC\0" \ 640 "b\010PAE\0" \ 641 "b\7NSS\0" \ 642 "b\6LTC\0" \ 643 "b\5LHRC\0" \ 644 "b\4PIND\0" \ 645 "b\3PPC\0" \ 646 "b\2CSZ\0" \ 647 "b\1BNC\0" \ 648 "b\0AC64\0" \ 649 "\0" 650 651 int 652 xhci_init(struct xhci_softc *sc) 653 { 654 bus_size_t bsz; 655 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 656 uint32_t ecp, ecr; 657 uint32_t usbcmd, usbsts, pagesize, config; 658 int i; 659 uint16_t hciversion; 660 uint8_t caplength; 661 662 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 663 664 sc->sc_bus.ub_revision = USBREV_3_0; 665 sc->sc_bus.ub_usedma = true; 666 667 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 668 caplength = XHCI_CAP_CAPLENGTH(cap); 669 hciversion = XHCI_CAP_HCIVERSION(cap); 670 671 if (hciversion < XHCI_HCIVERSION_0_96 || 672 hciversion > XHCI_HCIVERSION_1_0) { 673 aprint_normal_dev(sc->sc_dev, 674 "xHCI version %x.%x not known to be supported\n", 675 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 676 } else { 677 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 678 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 679 } 680 681 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 682 &sc->sc_cbh) != 0) { 683 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 684 return ENOMEM; 685 } 686 687 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 688 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 689 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 690 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 691 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 692 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 693 aprint_debug_dev(sc->sc_dev, 694 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 695 696 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 697 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 698 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 699 700 char sbuf[128]; 701 if (hciversion < XHCI_HCIVERSION_1_0) 702 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 703 else 704 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 705 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 706 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 707 708 ecp = XHCI_HCC_XECP(hcc) * 4; 709 while (ecp != 0) { 710 ecr = xhci_read_4(sc, ecp); 711 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 712 switch (XHCI_XECP_ID(ecr)) { 713 case XHCI_ID_PROTOCOLS: { 714 uint32_t w0, w4, w8; 715 uint16_t w2; 716 w0 = xhci_read_4(sc, ecp + 0); 717 w2 = (w0 >> 16) & 0xffff; 718 w4 = xhci_read_4(sc, ecp + 4); 719 w8 = xhci_read_4(sc, ecp + 8); 720 aprint_debug_dev(sc->sc_dev, "SP: %08x %08x %08x\n", 721 w0, w4, w8); 722 if (w4 == 0x20425355 && w2 == 0x0300) { 723 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 724 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 725 } 726 if (w4 == 0x20425355 && w2 == 0x0200) { 727 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 728 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 729 } 730 break; 731 } 732 case XHCI_ID_USB_LEGACY: { 733 uint8_t bios_sem; 734 735 /* Take host controller from BIOS */ 736 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 737 if (bios_sem) { 738 /* sets xHCI to be owned by OS */ 739 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 740 aprint_debug( 741 "waiting for BIOS to give up control\n"); 742 for (i = 0; i < 5000; i++) { 743 bios_sem = xhci_read_1(sc, ecp + 744 XHCI_XECP_BIOS_SEM); 745 if (bios_sem == 0) 746 break; 747 DELAY(1000); 748 } 749 if (bios_sem) 750 printf("timed out waiting for BIOS\n"); 751 } 752 break; 753 } 754 default: 755 break; 756 } 757 ecr = xhci_read_4(sc, ecp); 758 if (XHCI_XECP_NEXT(ecr) == 0) { 759 ecp = 0; 760 } else { 761 ecp += XHCI_XECP_NEXT(ecr) * 4; 762 } 763 } 764 765 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 766 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 767 &sc->sc_obh) != 0) { 768 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 769 return ENOMEM; 770 } 771 772 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 773 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 774 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 775 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 776 return ENOMEM; 777 } 778 779 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 780 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 781 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 782 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 783 return ENOMEM; 784 } 785 786 for (i = 0; i < 100; i++) { 787 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 788 if ((usbsts & XHCI_STS_CNR) == 0) 789 break; 790 usb_delay_ms(&sc->sc_bus, 1); 791 } 792 if (i >= 100) 793 return EIO; 794 795 usbcmd = 0; 796 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 797 usb_delay_ms(&sc->sc_bus, 1); 798 799 usbcmd = XHCI_CMD_HCRST; 800 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 801 for (i = 0; i < 100; i++) { 802 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 803 if ((usbcmd & XHCI_CMD_HCRST) == 0) 804 break; 805 usb_delay_ms(&sc->sc_bus, 1); 806 } 807 if (i >= 100) 808 return EIO; 809 810 for (i = 0; i < 100; i++) { 811 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 812 if ((usbsts & XHCI_STS_CNR) == 0) 813 break; 814 usb_delay_ms(&sc->sc_bus, 1); 815 } 816 if (i >= 100) 817 return EIO; 818 819 if (sc->sc_vendor_init) 820 sc->sc_vendor_init(sc); 821 822 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 823 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 824 pagesize = ffs(pagesize); 825 if (pagesize == 0) 826 return EIO; 827 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 828 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 829 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 830 (uint32_t)sc->sc_maxslots); 831 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 832 833 usbd_status err; 834 835 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 836 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 837 if (sc->sc_maxspbuf != 0) { 838 err = usb_allocmem(&sc->sc_bus, 839 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 840 &sc->sc_spbufarray_dma); 841 if (err) 842 return err; 843 844 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * sc->sc_maxspbuf, KM_SLEEP); 845 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 846 for (i = 0; i < sc->sc_maxspbuf; i++) { 847 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 848 /* allocate contexts */ 849 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 850 sc->sc_pgsz, dma); 851 if (err) 852 return err; 853 spbufarray[i] = htole64(DMAADDR(dma, 0)); 854 usb_syncmem(dma, 0, sc->sc_pgsz, 855 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 856 } 857 858 usb_syncmem(&sc->sc_spbufarray_dma, 0, 859 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 860 } 861 862 config = xhci_op_read_4(sc, XHCI_CONFIG); 863 config &= ~0xFF; 864 config |= sc->sc_maxslots & 0xFF; 865 xhci_op_write_4(sc, XHCI_CONFIG, config); 866 867 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 868 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 869 if (err) { 870 aprint_error_dev(sc->sc_dev, "command ring init fail\n"); 871 return err; 872 } 873 874 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 875 XHCI_EVENT_RING_SEGMENTS_ALIGN); 876 if (err) { 877 aprint_error_dev(sc->sc_dev, "event ring init fail\n"); 878 return err; 879 } 880 881 usb_dma_t *dma; 882 size_t size; 883 size_t align; 884 885 dma = &sc->sc_eventst_dma; 886 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 887 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 888 KASSERT(size <= (512 * 1024)); 889 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 890 err = usb_allocmem(&sc->sc_bus, size, align, dma); 891 892 memset(KERNADDR(dma, 0), 0, size); 893 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 894 aprint_debug_dev(sc->sc_dev, "eventst: %s %016jx %p %zx\n", 895 usbd_errstr(err), 896 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 897 KERNADDR(&sc->sc_eventst_dma, 0), 898 sc->sc_eventst_dma.udma_block->size); 899 900 dma = &sc->sc_dcbaa_dma; 901 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 902 KASSERT(size <= 2048); 903 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 904 err = usb_allocmem(&sc->sc_bus, size, align, dma); 905 906 memset(KERNADDR(dma, 0), 0, size); 907 if (sc->sc_maxspbuf != 0) { 908 /* 909 * DCBA entry 0 hold the scratchbuf array pointer. 910 */ 911 *(uint64_t *)KERNADDR(dma, 0) = 912 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 913 } 914 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 915 aprint_debug_dev(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n", 916 usbd_errstr(err), 917 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 918 KERNADDR(&sc->sc_dcbaa_dma, 0), 919 sc->sc_dcbaa_dma.udma_block->size); 920 921 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 922 KM_SLEEP); 923 924 cv_init(&sc->sc_command_cv, "xhcicmd"); 925 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 926 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 927 cv_init(&sc->sc_softwake_cv, "xhciab"); 928 929 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 930 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 931 932 /* Set up the bus struct. */ 933 sc->sc_bus.ub_methods = &xhci_bus_methods; 934 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 935 936 struct xhci_erste *erst; 937 erst = KERNADDR(&sc->sc_eventst_dma, 0); 938 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 939 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 940 erst[0].erste_3 = htole32(0); 941 usb_syncmem(&sc->sc_eventst_dma, 0, 942 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 943 944 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 945 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 946 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 947 XHCI_ERDP_LO_BUSY); 948 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 949 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 950 sc->sc_cr.xr_cs); 951 952 #if 0 953 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 954 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 955 #endif 956 957 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 958 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 959 /* Intel xhci needs interrupt rate moderated. */ 960 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 961 else 962 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 963 aprint_debug_dev(sc->sc_dev, "setting IMOD %u\n", 964 xhci_rt_read_4(sc, XHCI_IMOD(0))); 965 966 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 967 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 968 xhci_op_read_4(sc, XHCI_USBCMD)); 969 970 return USBD_NORMAL_COMPLETION; 971 } 972 973 int 974 xhci_intr(void *v) 975 { 976 struct xhci_softc * const sc = v; 977 int ret = 0; 978 979 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 980 981 if (sc == NULL) 982 return 0; 983 984 mutex_spin_enter(&sc->sc_intr_lock); 985 986 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 987 goto done; 988 989 /* If we get an interrupt while polling, then just ignore it. */ 990 if (sc->sc_bus.ub_usepolling) { 991 #ifdef DIAGNOSTIC 992 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 993 #endif 994 goto done; 995 } 996 997 ret = xhci_intr1(sc); 998 done: 999 mutex_spin_exit(&sc->sc_intr_lock); 1000 return ret; 1001 } 1002 1003 int 1004 xhci_intr1(struct xhci_softc * const sc) 1005 { 1006 uint32_t usbsts; 1007 uint32_t iman; 1008 1009 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1010 1011 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1012 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1013 #if 0 1014 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1015 return 0; 1016 } 1017 #endif 1018 xhci_op_write_4(sc, XHCI_USBSTS, 1019 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1020 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1021 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1022 1023 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1024 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1025 1026 /* XXX 4.17.5 IP may be 0 if MSI/MSI-X is used */ 1027 if (!(sc->sc_quirks & XHCI_QUIRK_FORCE_INTR)) { 1028 if ((iman & XHCI_IMAN_INTR_PEND) == 0) { 1029 return 0; 1030 } 1031 } 1032 1033 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1034 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1035 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1036 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1037 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1038 1039 usb_schedsoftintr(&sc->sc_bus); 1040 1041 return 1; 1042 } 1043 1044 /* 1045 * 3 port speed types used in USB stack 1046 * 1047 * usbdi speed 1048 * definition: USB_SPEED_* in usb.h 1049 * They are used in struct usbd_device in USB stack. 1050 * ioctl interface uses these values too. 1051 * port_status speed 1052 * definition: UPS_*_SPEED in usb.h 1053 * They are used in usb_port_status_t and valid only for USB 2.0. 1054 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1055 * of usb_port_status_ext_t indicates port speed. 1056 * Note that some 3.0 values overlap with 2.0 values. 1057 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1058 * means UPS_LOW_SPEED in HS.) 1059 * port status returned from hub also uses these values. 1060 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1061 * or more. 1062 * xspeed: 1063 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1064 * They are used in only slot context and PORTSC reg of xhci. 1065 * The difference between usbdi speed and xspeed is 1066 * that FS and LS values are swapped. 1067 */ 1068 1069 /* convert usbdi speed to xspeed */ 1070 static int 1071 xhci_speed2xspeed(int speed) 1072 { 1073 switch (speed) { 1074 case USB_SPEED_LOW: return 2; 1075 case USB_SPEED_FULL: return 1; 1076 default: return speed; 1077 } 1078 } 1079 1080 #if 0 1081 /* convert xspeed to usbdi speed */ 1082 static int 1083 xhci_xspeed2speed(int xspeed) 1084 { 1085 switch (xspeed) { 1086 case 1: return USB_SPEED_FULL; 1087 case 2: return USB_SPEED_LOW; 1088 default: return xspeed; 1089 } 1090 } 1091 #endif 1092 1093 /* convert xspeed to port status speed */ 1094 static int 1095 xhci_xspeed2psspeed(int xspeed) 1096 { 1097 switch (xspeed) { 1098 case 0: return 0; 1099 case 1: return UPS_FULL_SPEED; 1100 case 2: return UPS_LOW_SPEED; 1101 case 3: return UPS_HIGH_SPEED; 1102 default: return UPS_OTHER_SPEED; 1103 } 1104 } 1105 1106 /* construct slot context */ 1107 static void 1108 xhci_setup_sctx(struct usbd_device *dev, uint32_t *cp) 1109 { 1110 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 1111 int speed = dev->ud_speed; 1112 int tthubslot, ttportnum; 1113 bool ishub; 1114 bool usemtt; 1115 1116 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1117 1118 /* 1119 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 1120 * tthubslot: 1121 * This is the slot ID of parent HS hub 1122 * if LS/FS device is connected && connected through HS hub. 1123 * This is 0 if device is not LS/FS device || 1124 * parent hub is not HS hub || 1125 * attached to root hub. 1126 * ttportnum: 1127 * This is the downstream facing port of parent HS hub 1128 * if LS/FS device is connected. 1129 * This is 0 if device is not LS/FS device || 1130 * parent hub is not HS hub || 1131 * attached to root hub. 1132 */ 1133 if (dev->ud_myhsport != NULL && 1134 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1135 (dev->ud_myhub != NULL && 1136 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1137 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 1138 ttportnum = dev->ud_myhsport->up_portno; 1139 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 1140 } else { 1141 ttportnum = 0; 1142 tthubslot = 0; 1143 } 1144 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 1145 dev->ud_myhsport, ttportnum, tthubslot, 0); 1146 1147 /* ishub is valid after reading UDESC_DEVICE */ 1148 ishub = (dd->bDeviceClass == UDCLASS_HUB); 1149 1150 /* dev->ud_hub is valid after reading UDESC_HUB */ 1151 if (ishub && dev->ud_hub) { 1152 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 1153 1154 cp[1] |= htole32(XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts)); 1155 cp[2] |= htole32(XHCI_SCTX_2_TT_THINK_TIME_SET( 1156 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK))); 1157 DPRINTFN(4, "nports=%d ttt=%d", 1158 hd->bNbrPorts, XHCI_SCTX_2_TT_THINK_TIME_GET(cp[2]), 0, 0); 1159 } 1160 1161 #define IS_TTHUB(dd) \ 1162 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 1163 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 1164 1165 /* 1166 * MTT flag is set if 1167 * 1. this is HS hub && MTT is enabled 1168 * or 1169 * 2. this is not hub && this is LS or FS device && 1170 * MTT of parent HS hub (and its parent, too) is enabled 1171 */ 1172 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 1173 usemtt = true; 1174 else if (!ishub && 1175 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 1176 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1177 (dev->ud_myhub != NULL && 1178 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1179 dev->ud_myhsport != NULL && 1180 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 1181 usemtt = true; 1182 else 1183 usemtt = false; 1184 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 1185 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 1186 1187 cp[0] |= htole32( 1188 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)) | 1189 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 1190 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0) 1191 ); 1192 cp[1] |= htole32(0); 1193 cp[2] |= htole32( 1194 XHCI_SCTX_2_IRQ_TARGET_SET(0) | 1195 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 1196 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum) 1197 ); 1198 cp[3] |= htole32(0); 1199 } 1200 1201 static uint32_t 1202 xhci_get_maxburst(struct usbd_pipe *pipe) 1203 { 1204 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1205 usbd_desc_iter_t iter; 1206 const usb_cdc_descriptor_t *cdcd; 1207 const usb_endpoint_ss_comp_descriptor_t * esscd = NULL; 1208 uint32_t maxb = 0; 1209 uint8_t ep; 1210 1211 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc( 1212 pipe->up_dev, UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 1213 usb_desc_iter_init(pipe->up_dev, &iter); 1214 iter.cur = (const void *)cdcd; 1215 1216 /* find endpoint_ss_comp desc for ep of this pipe */ 1217 for (ep = 0;;) { 1218 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 1219 if (cdcd == NULL) 1220 break; 1221 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 1222 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 1223 bEndpointAddress; 1224 if (UE_GET_ADDR(ep) == 1225 UE_GET_ADDR(ed->bEndpointAddress)) { 1226 cdcd = (const usb_cdc_descriptor_t *) 1227 usb_desc_iter_next(&iter); 1228 break; 1229 } 1230 ep = 0; 1231 } 1232 } 1233 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 1234 esscd = (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 1235 maxb = esscd->bMaxBurst; 1236 } 1237 1238 return maxb; 1239 } 1240 1241 /* 1242 * Convert endpoint bInterval value to endpoint context interval value 1243 * for Interrupt pipe. 1244 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 1245 */ 1246 static uint32_t 1247 xhci_bival2ival(uint32_t ival, int speed) 1248 { 1249 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 1250 int i; 1251 1252 /* 1253 * round ival down to "the nearest base 2 multiple of 1254 * bInterval * 8". 1255 * bInterval is at most 255 as its type is uByte. 1256 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 1257 */ 1258 for (i = 10; i > 0; i--) { 1259 if ((ival * 8) >= (1 << i)) 1260 break; 1261 } 1262 ival = i; 1263 } else { 1264 /* Interval = bInterval-1 for SS/HS */ 1265 ival--; 1266 } 1267 1268 return ival; 1269 } 1270 1271 /* 1272 * 4.8.2, 6.2.3.2 1273 * construct common endpoint parameters 1274 */ 1275 static void 1276 xhci_setup_endp_ctx(struct usbd_pipe *pipe, uint32_t *cp) 1277 { 1278 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1279 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1280 const u_int dci = xhci_ep_get_dci(ed); 1281 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1282 uint32_t mps = UGETW(ed->wMaxPacketSize); 1283 uint32_t maxb = 0; 1284 int speed = pipe->up_dev->ud_speed; 1285 uint32_t ival = ed->bInterval; 1286 1287 cp[0] = htole32( 1288 XHCI_EPCTX_0_EPSTATE_SET(0) | 1289 XHCI_EPCTX_0_MULT_SET(0) | /* always 0 except SS iscoh */ 1290 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 1291 XHCI_EPCTX_0_LSA_SET(0) | 1292 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0) 1293 ); 1294 cp[1] = htole32( 1295 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 1296 XHCI_EPCTX_1_HID_SET(0) | 1297 XHCI_EPCTX_1_MAXB_SET(0) 1298 ); 1299 if (xfertype != UE_ISOCHRONOUS) 1300 cp[1] |= htole32(XHCI_EPCTX_1_CERR_SET(3)); 1301 1302 /* 6.2.3.4, 4.8.2.4 */ 1303 if (USB_IS_SS(speed)) { 1304 /* UBS 3.1 9.6.6 */ 1305 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1306 /* UBS 3.1 9.6.7 */ 1307 maxb = xhci_get_maxburst(pipe); 1308 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1309 } else { 1310 /* UBS 2.0 9.6.6 */ 1311 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps))); 1312 1313 /* 6.2.3.4 */ 1314 if (speed == USB_SPEED_HIGH && 1315 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 1316 maxb = UE_GET_TRANS(mps); 1317 } else { 1318 /* LS/FS or HS CTRL or HS BULK */ 1319 maxb = 0; 1320 } 1321 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1322 } 1323 1324 if (xfertype == UE_CONTROL) 1325 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(8)); /* 6.2.3 */ 1326 else if (USB_IS_SS(speed)) 1327 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps)); 1328 else 1329 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps))); 1330 1331 switch (xfertype) { 1332 case UE_CONTROL: 1333 break; 1334 case UE_BULK: 1335 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 1336 break; 1337 case UE_INTERRUPT: 1338 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1339 ival = pipe->up_interval; 1340 1341 ival = xhci_bival2ival(ival, speed); 1342 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1343 break; 1344 case UE_ISOCHRONOUS: 1345 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1346 ival = pipe->up_interval; 1347 1348 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 1349 if (speed == USB_SPEED_FULL) 1350 ival += 3; /* 1ms -> 125us */ 1351 ival--; 1352 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1353 1354 if (USB_IS_SS(speed)) { 1355 /* XXX if LEC = 1, set ESIT instead */ 1356 cp[0] |= htole32(XHCI_EPCTX_0_MULT_SET(0)); 1357 } 1358 break; 1359 default: 1360 break; 1361 } 1362 *(uint64_t *)(&cp[2]) = htole64( 1363 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 1364 XHCI_EPCTX_2_DCS_SET(1)); 1365 } 1366 1367 /* 1368 * Construct input contexts and issue TRB 1369 */ 1370 static usbd_status 1371 xhci_configure_endpoint(struct usbd_pipe *pipe) 1372 { 1373 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1374 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1375 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1376 struct xhci_trb trb; 1377 usbd_status err; 1378 uint32_t *cp; 1379 1380 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1381 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1382 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1383 pipe->up_endpoint->ue_edesc->bmAttributes); 1384 1385 /* XXX ensure input context is available? */ 1386 1387 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1388 1389 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1390 cp[0] = htole32(0); 1391 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 1392 1393 /* set up input slot context */ 1394 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1395 xhci_setup_sctx(pipe->up_dev, cp); 1396 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1397 1398 /* set up input endpoint context */ 1399 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 1400 xhci_setup_endp_ctx(pipe, cp); 1401 1402 /* sync input contexts before they are read from memory */ 1403 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1404 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1405 sc->sc_ctxsz * 1); 1406 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1407 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1408 1409 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1410 trb.trb_2 = 0; 1411 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1412 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1413 1414 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1415 1416 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1417 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1418 sc->sc_ctxsz * 1); 1419 1420 return err; 1421 } 1422 1423 #if 0 1424 static usbd_status 1425 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1426 { 1427 #ifdef USB_DEBUG 1428 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1429 #endif 1430 1431 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1432 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1433 1434 return USBD_NORMAL_COMPLETION; 1435 } 1436 #endif 1437 1438 /* 4.6.8, 6.4.3.7 */ 1439 static usbd_status 1440 xhci_reset_endpoint(struct usbd_pipe *pipe) 1441 { 1442 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1443 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1444 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1445 struct xhci_trb trb; 1446 usbd_status err; 1447 1448 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1449 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1450 1451 KASSERT(!mutex_owned(&sc->sc_lock)); 1452 1453 trb.trb_0 = 0; 1454 trb.trb_2 = 0; 1455 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1456 XHCI_TRB_3_EP_SET(dci) | 1457 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1458 1459 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1460 1461 return err; 1462 } 1463 1464 /* 1465 * 4.6.9, 6.4.3.8 1466 * Stop execution of TDs on xfer ring. 1467 * Should be called with sc_lock held. 1468 */ 1469 static usbd_status 1470 xhci_stop_endpoint(struct usbd_pipe *pipe) 1471 { 1472 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1473 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1474 struct xhci_trb trb; 1475 usbd_status err; 1476 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1477 1478 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1479 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1480 1481 KASSERT(mutex_owned(&sc->sc_lock)); 1482 1483 trb.trb_0 = 0; 1484 trb.trb_2 = 0; 1485 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1486 XHCI_TRB_3_EP_SET(dci) | 1487 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1488 1489 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1490 1491 return err; 1492 } 1493 1494 /* 1495 * Set TR Dequeue Pointer. 1496 * xCHI 1.1 4.6.10 6.4.3.9 1497 * Purge all of the transfer requests on ring. 1498 * EPSTATE of endpoint must be ERROR or STOPPED, or CONTEXT_STATE error. 1499 */ 1500 static usbd_status 1501 xhci_set_dequeue(struct usbd_pipe *pipe) 1502 { 1503 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1504 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1505 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1506 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1507 struct xhci_trb trb; 1508 usbd_status err; 1509 1510 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1511 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1512 1513 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1514 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1515 BUS_DMASYNC_PREWRITE); 1516 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1517 1518 xr->xr_ep = 0; 1519 xr->xr_cs = 1; 1520 1521 /* set DCS */ 1522 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1523 trb.trb_2 = 0; 1524 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1525 XHCI_TRB_3_EP_SET(dci) | 1526 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1527 1528 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1529 1530 return err; 1531 } 1532 1533 /* 1534 * Open new pipe: called from usbd_setup_pipe_flags. 1535 * Fills methods of pipe. 1536 * If pipe is not for ep0, calls configure_endpoint. 1537 */ 1538 static usbd_status 1539 xhci_open(struct usbd_pipe *pipe) 1540 { 1541 struct usbd_device * const dev = pipe->up_dev; 1542 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1543 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1544 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1545 1546 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1547 DPRINTFN(1, "addr %d depth %d port %d speed %d", 1548 dev->ud_addr, dev->ud_depth, dev->ud_powersrc->up_portno, 1549 dev->ud_speed); 1550 1551 if (sc->sc_dying) 1552 return USBD_IOERROR; 1553 1554 /* Root Hub */ 1555 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1556 switch (ed->bEndpointAddress) { 1557 case USB_CONTROL_ENDPOINT: 1558 pipe->up_methods = &roothub_ctrl_methods; 1559 break; 1560 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1561 pipe->up_methods = &xhci_root_intr_methods; 1562 break; 1563 default: 1564 pipe->up_methods = NULL; 1565 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1566 ed->bEndpointAddress, 0, 0, 0); 1567 return USBD_INVAL; 1568 } 1569 return USBD_NORMAL_COMPLETION; 1570 } 1571 1572 switch (xfertype) { 1573 case UE_CONTROL: 1574 pipe->up_methods = &xhci_device_ctrl_methods; 1575 break; 1576 case UE_ISOCHRONOUS: 1577 pipe->up_methods = &xhci_device_isoc_methods; 1578 return USBD_INVAL; 1579 break; 1580 case UE_BULK: 1581 pipe->up_methods = &xhci_device_bulk_methods; 1582 break; 1583 case UE_INTERRUPT: 1584 pipe->up_methods = &xhci_device_intr_methods; 1585 break; 1586 default: 1587 return USBD_IOERROR; 1588 break; 1589 } 1590 1591 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1592 return xhci_configure_endpoint(pipe); 1593 1594 return USBD_NORMAL_COMPLETION; 1595 } 1596 1597 /* 1598 * Closes pipe, called from usbd_kill_pipe via close methods. 1599 * If the endpoint to be closed is ep0, disable_slot. 1600 * Should be called with sc_lock held. 1601 */ 1602 static void 1603 xhci_close_pipe(struct usbd_pipe *pipe) 1604 { 1605 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1606 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1607 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1608 const u_int dci = xhci_ep_get_dci(ed); 1609 struct xhci_trb trb; 1610 uint32_t *cp; 1611 1612 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1613 1614 if (sc->sc_dying) 1615 return; 1616 1617 if (xs == NULL || xs->xs_idx == 0) 1618 /* xs is uninitialized before xhci_init_slot */ 1619 return; 1620 1621 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1622 1623 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1624 KASSERT(mutex_owned(&sc->sc_lock)); 1625 1626 if (pipe->up_dev->ud_depth == 0) 1627 return; 1628 1629 if (dci == XHCI_DCI_EP_CONTROL) { 1630 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1631 xhci_disable_slot(sc, xs->xs_idx); 1632 return; 1633 } 1634 1635 /* 1636 * This may fail in the case that xhci_close_pipe is called after 1637 * xhci_abort_xfer e.g. usbd_kill_pipe. 1638 */ 1639 (void)xhci_stop_endpoint(pipe); 1640 1641 /* 1642 * set appropriate bit to be dropped. 1643 * don't set DC bit to 1, otherwise all endpoints 1644 * would be deconfigured. 1645 */ 1646 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1647 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1648 cp[1] = htole32(0); 1649 1650 /* XXX should be most significant one, not dci? */ 1651 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1652 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1653 1654 /* sync input contexts before they are read from memory */ 1655 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1656 1657 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1658 trb.trb_2 = 0; 1659 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1660 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1661 1662 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1663 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1664 } 1665 1666 /* 1667 * Abort transfer. 1668 * Called with sc_lock held. 1669 * May be called from softintr context. 1670 */ 1671 static void 1672 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1673 { 1674 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1675 1676 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1677 DPRINTFN(4, "xfer %p pipe %p status %d", 1678 xfer, xfer->ux_pipe, status, 0); 1679 1680 KASSERT(mutex_owned(&sc->sc_lock)); 1681 1682 if (sc->sc_dying) { 1683 /* If we're dying, just do the software part. */ 1684 DPRINTFN(4, "dying", 0, 0, 0, 0); 1685 xfer->ux_status = status; /* make software ignore it */ 1686 callout_stop(&xfer->ux_callout); 1687 usb_transfer_complete(xfer); 1688 return; 1689 } 1690 1691 /* XXX need more stuff */ 1692 xfer->ux_status = status; 1693 callout_stop(&xfer->ux_callout); 1694 usb_transfer_complete(xfer); 1695 DPRINTFN(14, "end", 0, 0, 0, 0); 1696 1697 KASSERT(mutex_owned(&sc->sc_lock)); 1698 } 1699 1700 /* 1701 * Recover STALLed endpoint. 1702 * xHCI 1.1 sect 4.10.2.1 1703 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1704 * all transfers on transfer ring. 1705 * These are done in thread context asynchronously. 1706 */ 1707 static void 1708 xhci_clear_endpoint_stall_async_task(void *cookie) 1709 { 1710 struct usbd_xfer * const xfer = cookie; 1711 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1712 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1713 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1714 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1715 1716 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1717 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1718 1719 xhci_reset_endpoint(xfer->ux_pipe); 1720 xhci_set_dequeue(xfer->ux_pipe); 1721 1722 mutex_enter(&sc->sc_lock); 1723 tr->is_halted = false; 1724 usb_transfer_complete(xfer); 1725 mutex_exit(&sc->sc_lock); 1726 DPRINTFN(4, "ends", 0, 0, 0, 0); 1727 } 1728 1729 static usbd_status 1730 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1731 { 1732 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1733 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1734 1735 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1736 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1737 1738 if (sc->sc_dying) { 1739 return USBD_IOERROR; 1740 } 1741 1742 usb_init_task(&xp->xp_async_task, 1743 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1744 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1745 DPRINTFN(4, "ends", 0, 0, 0, 0); 1746 1747 return USBD_NORMAL_COMPLETION; 1748 } 1749 1750 /* Process roothub port status/change events and notify to uhub_intr. */ 1751 static void 1752 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1753 { 1754 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1755 uint8_t *p; 1756 1757 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1758 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1759 port, 0, 0); 1760 1761 if (xfer == NULL) 1762 return; 1763 1764 if (port > sc->sc_maxports) 1765 return; 1766 1767 p = xfer->ux_buf; 1768 memset(p, 0, xfer->ux_length); 1769 p[port/NBBY] |= 1 << (port%NBBY); 1770 xfer->ux_actlen = xfer->ux_length; 1771 xfer->ux_status = USBD_NORMAL_COMPLETION; 1772 usb_transfer_complete(xfer); 1773 } 1774 1775 /* Process Transfer Events */ 1776 static void 1777 xhci_event_transfer(struct xhci_softc * const sc, 1778 const struct xhci_trb * const trb) 1779 { 1780 uint64_t trb_0; 1781 uint32_t trb_2, trb_3; 1782 uint8_t trbcode; 1783 u_int slot, dci; 1784 struct xhci_slot *xs; 1785 struct xhci_ring *xr; 1786 struct xhci_xfer *xx; 1787 struct usbd_xfer *xfer; 1788 usbd_status err; 1789 1790 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1791 1792 trb_0 = le64toh(trb->trb_0); 1793 trb_2 = le32toh(trb->trb_2); 1794 trb_3 = le32toh(trb->trb_3); 1795 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1796 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1797 dci = XHCI_TRB_3_EP_GET(trb_3); 1798 xs = &sc->sc_slots[slot]; 1799 xr = &xs->xs_ep[dci].xe_tr; 1800 1801 /* sanity check */ 1802 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx < sc->sc_maxslots, 1803 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1804 1805 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1806 /* 1807 * When ED == 0, trb_0 is physical address of the TRB 1808 * that caused this event. (6.4.2.1) 1809 */ 1810 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 1811 1812 /* trb_0 range sanity check */ 1813 if (trb_0 < trbp || 1814 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 1815 (trb_0 - trbp) / sizeof(struct xhci_trb) >= 1816 xr->xr_ntrb) { 1817 DPRINTFN(1, "invalid trb_0 0x%"PRIx64" trbp 0x%"PRIx64, 1818 trb_0, trbp, 0, 0); 1819 return; 1820 } 1821 int idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 1822 xx = xr->xr_cookies[idx]; 1823 1824 /* 1825 * If endpoint is stopped between TDs, TRB pointer points at 1826 * next TRB, however, it is not put yet or is a garbage TRB. 1827 * That's why xr_cookies may be NULL or look like broken. 1828 * Note: this ev happens only when hciversion >= 1.0 or 1829 * hciversion == 0.96 and FSE of hcc1 is set. 1830 */ 1831 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1832 DPRINTFN(1, "xx NULL: #%u: cookie %p: code %u trb_0 %" 1833 PRIx64, idx, xx, trbcode, trb_0); 1834 } 1835 } else { 1836 /* When ED != 0, trb_0 is kaddr of struct xhci_xfer. */ 1837 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1838 } 1839 /* XXX this may not happen */ 1840 if (xx == NULL) { 1841 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1842 return; 1843 } 1844 xfer = &xx->xx_xfer; 1845 /* XXX this may happen when detaching */ 1846 if (xfer == NULL) { 1847 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1848 xx, trb_0, 0, 0); 1849 return; 1850 } 1851 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1852 /* XXX I dunno why this happens */ 1853 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1854 1855 if (!xfer->ux_pipe->up_repeat && 1856 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1857 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1858 return; 1859 } 1860 1861 /* 4.11.5.2 Event Data TRB */ 1862 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1863 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1864 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1865 if ((trb_0 & 0x3) == 0x3) { 1866 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1867 } 1868 } 1869 1870 switch (trbcode) { 1871 case XHCI_TRB_ERROR_SHORT_PKT: 1872 case XHCI_TRB_ERROR_SUCCESS: 1873 xfer->ux_actlen = 1874 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1875 err = USBD_NORMAL_COMPLETION; 1876 break; 1877 case XHCI_TRB_ERROR_STALL: 1878 case XHCI_TRB_ERROR_BABBLE: 1879 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1880 xr->is_halted = true; 1881 err = USBD_STALLED; 1882 /* 1883 * Stalled endpoints can be recoverd by issuing 1884 * command TRB TYPE_RESET_EP on xHCI instead of 1885 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1886 * on the endpoint. However, this function may be 1887 * called from softint context (e.g. from umass), 1888 * in that case driver gets KASSERT in cv_timedwait 1889 * in xhci_do_command. 1890 * To avoid this, this runs reset_endpoint and 1891 * usb_transfer_complete in usb task thread 1892 * asynchronously (and then umass issues clear 1893 * UF_ENDPOINT_HALT). 1894 */ 1895 xfer->ux_status = err; 1896 xhci_clear_endpoint_stall_async(xfer); 1897 return; 1898 default: 1899 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1900 err = USBD_IOERROR; 1901 break; 1902 } 1903 xfer->ux_status = err; 1904 1905 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1906 if ((trb_0 & 0x3) == 0x0) { 1907 callout_stop(&xfer->ux_callout); 1908 usb_transfer_complete(xfer); 1909 } 1910 } else { 1911 callout_stop(&xfer->ux_callout); 1912 usb_transfer_complete(xfer); 1913 } 1914 } 1915 1916 /* Process Command complete events */ 1917 static void 1918 xhci_event_cmd(struct xhci_softc * const sc, 1919 const struct xhci_trb * const trb) 1920 { 1921 uint64_t trb_0; 1922 uint32_t trb_2, trb_3; 1923 1924 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1925 1926 trb_0 = le64toh(trb->trb_0); 1927 trb_2 = le32toh(trb->trb_2); 1928 trb_3 = le32toh(trb->trb_3); 1929 1930 if (trb_0 == sc->sc_command_addr) { 1931 sc->sc_result_trb.trb_0 = trb_0; 1932 sc->sc_result_trb.trb_2 = trb_2; 1933 sc->sc_result_trb.trb_3 = trb_3; 1934 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1935 XHCI_TRB_ERROR_SUCCESS) { 1936 DPRINTFN(1, "command completion " 1937 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1938 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1939 } 1940 cv_signal(&sc->sc_command_cv); 1941 } else { 1942 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 1943 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1944 trb_2, trb_3); 1945 } 1946 } 1947 1948 /* 1949 * Process events. 1950 * called from xhci_softintr 1951 */ 1952 static void 1953 xhci_handle_event(struct xhci_softc * const sc, 1954 const struct xhci_trb * const trb) 1955 { 1956 uint64_t trb_0; 1957 uint32_t trb_2, trb_3; 1958 1959 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1960 1961 KASSERT(mutex_owned(&sc->sc_lock)); 1962 1963 trb_0 = le64toh(trb->trb_0); 1964 trb_2 = le32toh(trb->trb_2); 1965 trb_3 = le32toh(trb->trb_3); 1966 1967 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1968 trb, trb_0, trb_2, trb_3); 1969 1970 /* 1971 * 4.11.3.1, 6.4.2.1 1972 * TRB Pointer is invalid for these completion codes. 1973 */ 1974 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 1975 case XHCI_TRB_ERROR_RING_UNDERRUN: 1976 case XHCI_TRB_ERROR_RING_OVERRUN: 1977 case XHCI_TRB_ERROR_VF_RING_FULL: 1978 return; 1979 default: 1980 if (trb_0 == 0) { 1981 return; 1982 } 1983 break; 1984 } 1985 1986 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 1987 case XHCI_TRB_EVENT_TRANSFER: 1988 xhci_event_transfer(sc, trb); 1989 break; 1990 case XHCI_TRB_EVENT_CMD_COMPLETE: 1991 xhci_event_cmd(sc, trb); 1992 break; 1993 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1994 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1995 break; 1996 default: 1997 break; 1998 } 1999 } 2000 2001 static void 2002 xhci_softintr(void *v) 2003 { 2004 struct usbd_bus * const bus = v; 2005 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2006 struct xhci_ring * const er = &sc->sc_er; 2007 struct xhci_trb *trb; 2008 int i, j, k; 2009 2010 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2011 2012 i = er->xr_ep; 2013 j = er->xr_cs; 2014 2015 DPRINTFN(16, "xr_ep %d xr_cs %d", i, j, 0, 0); 2016 2017 while (1) { 2018 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2019 BUS_DMASYNC_POSTREAD); 2020 trb = &er->xr_trb[i]; 2021 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2022 2023 if (j != k) 2024 break; 2025 2026 xhci_handle_event(sc, trb); 2027 2028 i++; 2029 if (i == XHCI_EVENT_RING_TRBS) { 2030 i = 0; 2031 j ^= 1; 2032 } 2033 } 2034 2035 er->xr_ep = i; 2036 er->xr_cs = j; 2037 2038 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2039 XHCI_ERDP_LO_BUSY); 2040 2041 DPRINTFN(16, "ends", 0, 0, 0, 0); 2042 2043 return; 2044 } 2045 2046 static void 2047 xhci_poll(struct usbd_bus *bus) 2048 { 2049 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2050 2051 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2052 2053 mutex_spin_enter(&sc->sc_intr_lock); 2054 xhci_intr1(sc); 2055 mutex_spin_exit(&sc->sc_intr_lock); 2056 2057 return; 2058 } 2059 2060 static struct usbd_xfer * 2061 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2062 { 2063 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2064 struct usbd_xfer *xfer; 2065 2066 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2067 2068 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 2069 if (xfer != NULL) { 2070 memset(xfer, 0, sizeof(struct xhci_xfer)); 2071 #ifdef DIAGNOSTIC 2072 xfer->ux_state = XFER_BUSY; 2073 #endif 2074 } 2075 2076 return xfer; 2077 } 2078 2079 static void 2080 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2081 { 2082 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2083 2084 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2085 2086 #ifdef DIAGNOSTIC 2087 if (xfer->ux_state != XFER_BUSY) { 2088 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 2089 xfer, xfer->ux_state, 0, 0); 2090 } 2091 xfer->ux_state = XFER_FREE; 2092 #endif 2093 pool_cache_put(sc->sc_xferpool, xfer); 2094 } 2095 2096 static void 2097 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2098 { 2099 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2100 2101 *lock = &sc->sc_lock; 2102 } 2103 2104 extern uint32_t usb_cookie_no; 2105 2106 /* 2107 * Called if uhub_explore finds a new device (via usbd_new_device). 2108 * Allocate and construct dev structure of default endpoint (ep0). 2109 * Determine initial MaxPacketSize (mps) by speed. 2110 * Determine route string and roothub port for slot of dev. 2111 * Allocate pipe of ep0. 2112 * Enable and initialize slot and Set Address. 2113 * Read device descriptor. 2114 * Register this device. 2115 */ 2116 static usbd_status 2117 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2118 int speed, int port, struct usbd_port *up) 2119 { 2120 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2121 struct usbd_device *dev; 2122 usbd_status err; 2123 usb_device_descriptor_t *dd; 2124 struct usbd_device *hub; 2125 struct usbd_device *adev; 2126 int rhport = 0; 2127 struct xhci_slot *xs; 2128 uint32_t *cp; 2129 uint32_t route = 0; 2130 uint8_t slot = 0; 2131 uint8_t addr; 2132 2133 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2134 DPRINTFN(4, "port=%d depth=%d speed=%d upport %d", 2135 port, depth, speed, up->up_portno); 2136 2137 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2138 if (dev == NULL) 2139 return USBD_NOMEM; 2140 2141 dev->ud_bus = bus; 2142 2143 /* Set up default endpoint handle. */ 2144 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2145 2146 /* Set up default endpoint descriptor. */ 2147 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2148 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2149 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2150 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2151 /* 4.3, 4.8.2.1 */ 2152 if (USB_IS_SS(speed)) { 2153 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2154 } else 2155 switch (speed) { 2156 case USB_SPEED_FULL: 2157 /* XXX using 64 as initial mps of ep0 in FS */ 2158 case USB_SPEED_HIGH: 2159 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2160 break; 2161 case USB_SPEED_LOW: 2162 default: 2163 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2164 break; 2165 } 2166 dev->ud_ep0desc.bInterval = 0; 2167 2168 /* doesn't matter, just don't let it uninitialized */ 2169 dev->ud_ep0.ue_toggle = 0; 2170 2171 DPRINTFN(4, "up %p portno %d", up, up->up_portno, 0, 0); 2172 2173 dev->ud_quirks = &usbd_no_quirk; 2174 dev->ud_addr = 0; 2175 dev->ud_ddesc.bMaxPacketSize = 0; 2176 dev->ud_depth = depth; 2177 dev->ud_powersrc = up; 2178 dev->ud_myhub = up->up_parent; 2179 2180 up->up_dev = dev; 2181 2182 /* Locate root hub port */ 2183 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2184 uint32_t dep; 2185 2186 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2187 hub, hub->ud_depth, hub->ud_powersrc, 2188 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2189 2190 if (hub->ud_powersrc == NULL) 2191 break; 2192 dep = hub->ud_depth; 2193 if (dep == 0) 2194 break; 2195 rhport = hub->ud_powersrc->up_portno; 2196 if (dep > USB_HUB_MAX_DEPTH) 2197 continue; 2198 2199 route |= 2200 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2201 << ((dep - 1) * 4); 2202 } 2203 route = route >> 4; 2204 DPRINTFN(4, "rhport %d Route %05x hub %p", rhport, route, hub, 0); 2205 2206 /* Locate port on upstream high speed hub */ 2207 for (adev = dev, hub = up->up_parent; 2208 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2209 adev = hub, hub = hub->ud_myhub) 2210 ; 2211 if (hub) { 2212 int p; 2213 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2214 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2215 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2216 goto found; 2217 } 2218 } 2219 panic("xhci_new_device: cannot find HS port"); 2220 found: 2221 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2222 } else { 2223 dev->ud_myhsport = NULL; 2224 } 2225 2226 dev->ud_speed = speed; 2227 dev->ud_langid = USBD_NOLANG; 2228 dev->ud_cookie.cookie = ++usb_cookie_no; 2229 2230 /* Establish the default pipe. */ 2231 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2232 &dev->ud_pipe0); 2233 if (err) { 2234 goto bad; 2235 } 2236 2237 dd = &dev->ud_ddesc; 2238 2239 if ((depth == 0) && (port == 0)) { 2240 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2241 bus->ub_devices[dev->ud_addr] = dev; 2242 err = usbd_get_initial_ddesc(dev, dd); 2243 if (err) 2244 goto bad; 2245 err = usbd_reload_device_desc(dev); 2246 if (err) 2247 goto bad; 2248 } else { 2249 err = xhci_enable_slot(sc, &slot); 2250 if (err) 2251 goto bad; 2252 xs = &sc->sc_slots[slot]; 2253 dev->ud_hcpriv = xs; 2254 err = xhci_init_slot(dev, slot, route, rhport); 2255 if (err) { 2256 dev->ud_hcpriv = NULL; 2257 /* 2258 * We have to disable_slot here because 2259 * xs->xs_idx == 0 when xhci_init_slot fails, 2260 * in that case usbd_remove_dev won't work. 2261 */ 2262 mutex_enter(&sc->sc_lock); 2263 xhci_disable_slot(sc, slot); 2264 mutex_exit(&sc->sc_lock); 2265 goto bad; 2266 } 2267 2268 /* Allow device time to set new address */ 2269 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2270 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2271 //hexdump("slot context", cp, sc->sc_ctxsz); 2272 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2273 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2274 /* XXX ensure we know when the hardware does something 2275 we can't yet cope with */ 2276 KASSERT(addr >= 1 && addr <= 127); 2277 dev->ud_addr = addr; 2278 /* XXX dev->ud_addr not necessarily unique on bus */ 2279 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2280 bus->ub_devices[dev->ud_addr] = dev; 2281 2282 err = usbd_get_initial_ddesc(dev, dd); 2283 if (err) 2284 goto bad; 2285 /* 4.8.2.1 */ 2286 if (USB_IS_SS(speed)) { 2287 if (dd->bMaxPacketSize != 9) { 2288 printf("%s: invalid mps 2^%u for SS ep0," 2289 " using 512\n", 2290 device_xname(sc->sc_dev), 2291 dd->bMaxPacketSize); 2292 dd->bMaxPacketSize = 9; 2293 } 2294 USETW(dev->ud_ep0desc.wMaxPacketSize, 2295 (1 << dd->bMaxPacketSize)); 2296 } else 2297 USETW(dev->ud_ep0desc.wMaxPacketSize, 2298 dd->bMaxPacketSize); 2299 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2300 xhci_update_ep0_mps(sc, xs, 2301 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2302 err = usbd_reload_device_desc(dev); 2303 if (err) 2304 goto bad; 2305 2306 #if 0 2307 /* Re-establish the default pipe with the new MPS. */ 2308 /* In xhci this is done by xhci_update_ep0_mps. */ 2309 usbd_kill_pipe(dev->ud_pipe0); 2310 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2311 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2312 #endif 2313 } 2314 2315 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2316 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2317 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2318 dd->bDeviceClass, dd->bDeviceSubClass, 2319 dd->bDeviceProtocol, 0); 2320 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2321 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2322 dev->ud_speed); 2323 2324 usbd_get_device_strings(dev); 2325 2326 usbd_get_device_strings(dev); 2327 2328 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2329 2330 if ((depth == 0) && (port == 0)) { 2331 usbd_attach_roothub(parent, dev); 2332 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2333 return USBD_NORMAL_COMPLETION; 2334 } 2335 2336 2337 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2338 bad: 2339 if (err != USBD_NORMAL_COMPLETION) { 2340 usbd_remove_device(dev, up); 2341 } 2342 2343 return err; 2344 } 2345 2346 static usbd_status 2347 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2348 size_t ntrb, size_t align) 2349 { 2350 usbd_status err; 2351 size_t size = ntrb * XHCI_TRB_SIZE; 2352 2353 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2354 2355 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2356 if (err) 2357 return err; 2358 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2359 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2360 xr->xr_trb = xhci_ring_trbv(xr, 0); 2361 xr->xr_ntrb = ntrb; 2362 xr->xr_ep = 0; 2363 xr->xr_cs = 1; 2364 memset(xr->xr_trb, 0, size); 2365 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 2366 xr->is_halted = false; 2367 2368 return USBD_NORMAL_COMPLETION; 2369 } 2370 2371 static void 2372 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2373 { 2374 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2375 mutex_destroy(&xr->xr_lock); 2376 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2377 } 2378 2379 static void 2380 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2381 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2382 { 2383 size_t i; 2384 u_int ri; 2385 u_int cs; 2386 uint64_t parameter; 2387 uint32_t status; 2388 uint32_t control; 2389 2390 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2391 2392 KASSERT(ntrbs <= XHCI_XFER_NTRB); 2393 for (i = 0; i < ntrbs; i++) { 2394 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2395 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2396 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2397 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2398 XHCI_TRB_TYPE_LINK); 2399 } 2400 2401 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2402 2403 ri = xr->xr_ep; 2404 cs = xr->xr_cs; 2405 2406 /* 2407 * Although the xhci hardware can do scatter/gather dma from 2408 * arbitrary sized buffers, there is a non-obvious restriction 2409 * that a LINK trb is only allowed at the end of a burst of 2410 * transfers - which might be 16kB. 2411 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2412 * The simple solution is not to allow a LINK trb in the middle 2413 * of anything - as here. 2414 * XXX: (dsl) There are xhci controllers out there (eg some made by 2415 * ASMedia) that seem to lock up if they process a LINK trb but 2416 * cannot process the linked-to trb yet. 2417 * The code should write the 'cycle' bit on the link trb AFTER 2418 * adding the other trb. 2419 */ 2420 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2421 parameter = xhci_ring_trbp(xr, 0); 2422 status = 0; 2423 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2424 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2425 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2426 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2427 BUS_DMASYNC_PREWRITE); 2428 xr->xr_cookies[ri] = NULL; 2429 xr->xr_ep = 0; 2430 xr->xr_cs ^= 1; 2431 ri = xr->xr_ep; 2432 cs = xr->xr_cs; 2433 } 2434 2435 ri++; 2436 2437 /* Write any subsequent TRB first */ 2438 for (i = 1; i < ntrbs; i++) { 2439 parameter = trbs[i].trb_0; 2440 status = trbs[i].trb_2; 2441 control = trbs[i].trb_3; 2442 2443 if (cs) { 2444 control |= XHCI_TRB_3_CYCLE_BIT; 2445 } else { 2446 control &= ~XHCI_TRB_3_CYCLE_BIT; 2447 } 2448 2449 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2450 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2451 BUS_DMASYNC_PREWRITE); 2452 xr->xr_cookies[ri] = cookie; 2453 ri++; 2454 } 2455 2456 /* Write the first TRB last */ 2457 i = 0; 2458 parameter = trbs[i].trb_0; 2459 status = trbs[i].trb_2; 2460 control = trbs[i].trb_3; 2461 2462 if (xr->xr_cs) { 2463 control |= XHCI_TRB_3_CYCLE_BIT; 2464 } else { 2465 control &= ~XHCI_TRB_3_CYCLE_BIT; 2466 } 2467 2468 xhci_trb_put(&xr->xr_trb[xr->xr_ep], parameter, status, control); 2469 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2470 BUS_DMASYNC_PREWRITE); 2471 xr->xr_cookies[xr->xr_ep] = cookie; 2472 2473 xr->xr_ep = ri; 2474 xr->xr_cs = cs; 2475 2476 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2477 } 2478 2479 /* 2480 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2481 * Command completion is notified by cv_signal from xhci_handle_event 2482 * (called from interrupt from xHCI), or timed-out. 2483 * Command validation is performed in xhci_handle_event by checking if 2484 * trb_0 in CMD_COMPLETE TRB and sc->sc_command_addr are identical. 2485 */ 2486 static usbd_status 2487 xhci_do_command1(struct xhci_softc * const sc, struct xhci_trb * const trb, 2488 int timeout, int locked) 2489 { 2490 struct xhci_ring * const cr = &sc->sc_cr; 2491 usbd_status err; 2492 2493 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2494 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2495 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2496 2497 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2498 2499 if (!locked) 2500 mutex_enter(&sc->sc_lock); 2501 2502 /* XXX KASSERT may fire when cv_timedwait unlocks sc_lock */ 2503 KASSERT(sc->sc_command_addr == 0); 2504 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2505 2506 mutex_enter(&cr->xr_lock); 2507 xhci_ring_put(sc, cr, NULL, trb, 1); 2508 mutex_exit(&cr->xr_lock); 2509 2510 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2511 2512 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2513 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2514 err = USBD_TIMEOUT; 2515 goto timedout; 2516 } 2517 2518 trb->trb_0 = sc->sc_result_trb.trb_0; 2519 trb->trb_2 = sc->sc_result_trb.trb_2; 2520 trb->trb_3 = sc->sc_result_trb.trb_3; 2521 2522 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2523 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2524 2525 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2526 case XHCI_TRB_ERROR_SUCCESS: 2527 err = USBD_NORMAL_COMPLETION; 2528 break; 2529 default: 2530 case 192 ... 223: 2531 err = USBD_IOERROR; 2532 break; 2533 case 224 ... 255: 2534 err = USBD_NORMAL_COMPLETION; 2535 break; 2536 } 2537 2538 timedout: 2539 sc->sc_command_addr = 0; 2540 if (!locked) 2541 mutex_exit(&sc->sc_lock); 2542 return err; 2543 } 2544 2545 static usbd_status 2546 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2547 int timeout) 2548 { 2549 return xhci_do_command1(sc, trb, timeout, 0); 2550 } 2551 2552 /* 2553 * This allows xhci_do_command with already sc_lock held. 2554 * This is needed as USB stack calls close methods with sc_lock_held. 2555 * (see usbdivar.h) 2556 */ 2557 static usbd_status 2558 xhci_do_command_locked(struct xhci_softc * const sc, 2559 struct xhci_trb * const trb, int timeout) 2560 { 2561 return xhci_do_command1(sc, trb, timeout, 1); 2562 } 2563 2564 static usbd_status 2565 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2566 { 2567 struct xhci_trb trb; 2568 usbd_status err; 2569 2570 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2571 2572 trb.trb_0 = 0; 2573 trb.trb_2 = 0; 2574 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2575 2576 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2577 if (err != USBD_NORMAL_COMPLETION) { 2578 return err; 2579 } 2580 2581 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2582 2583 return err; 2584 } 2585 2586 /* 2587 * Deallocate DMA buffer and ring buffer, and disable_slot. 2588 * Should be called with sc_lock held. 2589 */ 2590 static usbd_status 2591 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2592 { 2593 struct xhci_trb trb; 2594 struct xhci_slot *xs; 2595 2596 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2597 2598 if (sc->sc_dying) 2599 return USBD_IOERROR; 2600 2601 xs = &sc->sc_slots[slot]; 2602 if (xs->xs_idx != 0) { 2603 for (int i = XHCI_DCI_SLOT + 1; i < 32; i++) { 2604 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2605 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2606 } 2607 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2608 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2609 } 2610 2611 trb.trb_0 = 0; 2612 trb.trb_2 = 0; 2613 trb.trb_3 = htole32( 2614 XHCI_TRB_3_SLOT_SET(slot) | 2615 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2616 2617 return xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2618 } 2619 2620 /* 2621 * Change slot state. 2622 * bsr=0: ENABLED -> ADDRESSED 2623 * bsr=1: ENABLED -> DEFAULT 2624 * see xHCI 1.1 4.5.3, 3.3.4 2625 */ 2626 static usbd_status 2627 xhci_address_device(struct xhci_softc * const sc, 2628 uint64_t icp, uint8_t slot_id, bool bsr) 2629 { 2630 struct xhci_trb trb; 2631 usbd_status err; 2632 2633 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2634 2635 trb.trb_0 = icp; 2636 trb.trb_2 = 0; 2637 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2638 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2639 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2640 2641 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2642 2643 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2644 err = USBD_NO_ADDR; 2645 2646 return err; 2647 } 2648 2649 static usbd_status 2650 xhci_update_ep0_mps(struct xhci_softc * const sc, 2651 struct xhci_slot * const xs, u_int mps) 2652 { 2653 struct xhci_trb trb; 2654 usbd_status err; 2655 uint32_t * cp; 2656 2657 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2658 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2659 2660 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2661 cp[0] = htole32(0); 2662 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2663 2664 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2665 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2666 2667 /* sync input contexts before they are read from memory */ 2668 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2669 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2670 sc->sc_ctxsz * 4); 2671 2672 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2673 trb.trb_2 = 0; 2674 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2675 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2676 2677 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2678 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2679 return err; 2680 } 2681 2682 static void 2683 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2684 { 2685 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2686 2687 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2688 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2689 &dcbaa[si], dcba, si, 0); 2690 2691 dcbaa[si] = htole64(dcba); 2692 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2693 BUS_DMASYNC_PREWRITE); 2694 } 2695 2696 /* 2697 * Allocate DMA buffer and ring buffer for specified slot 2698 * and set Device Context Base Address 2699 * and issue Set Address device command. 2700 */ 2701 static usbd_status 2702 xhci_init_slot(struct usbd_device *dev, uint32_t slot, int route, int rhport) 2703 { 2704 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2705 struct xhci_slot *xs; 2706 usbd_status err; 2707 u_int dci; 2708 uint32_t *cp; 2709 uint32_t mps = UGETW(dev->ud_ep0desc.wMaxPacketSize); 2710 2711 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2712 DPRINTFN(4, "slot %u speed %d rhport %d route %05x", 2713 slot, dev->ud_speed, route, rhport); 2714 2715 xs = &sc->sc_slots[slot]; 2716 2717 /* allocate contexts */ 2718 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2719 &xs->xs_dc_dma); 2720 if (err) 2721 return err; 2722 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2723 2724 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2725 &xs->xs_ic_dma); 2726 if (err) 2727 goto bad1; 2728 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2729 2730 for (dci = 0; dci < 32; dci++) { 2731 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2732 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2733 if (dci == XHCI_DCI_SLOT) 2734 continue; 2735 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2736 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2737 if (err) { 2738 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2739 goto bad2; 2740 } 2741 } 2742 2743 /* set up initial input control context */ 2744 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2745 cp[0] = htole32(0); 2746 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 2747 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2748 2749 /* set up input slot context */ 2750 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2751 xhci_setup_sctx(dev, cp); 2752 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(1)); 2753 cp[0] |= htole32(XHCI_SCTX_0_ROUTE_SET(route)); 2754 cp[1] |= htole32(XHCI_SCTX_1_RH_PORT_SET(rhport)); 2755 2756 /* set up input EP0 context */ 2757 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2758 cp[0] = htole32(0); 2759 cp[1] = htole32( 2760 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 2761 XHCI_EPCTX_1_EPTYPE_SET(4) | 2762 XHCI_EPCTX_1_CERR_SET(3) 2763 ); 2764 /* can't use xhci_ep_get_dci() yet? */ 2765 *(uint64_t *)(&cp[2]) = htole64( 2766 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 2767 XHCI_EPCTX_2_DCS_SET(1)); 2768 cp[4] = htole32( 2769 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 2770 ); 2771 2772 /* sync input contexts before they are read from memory */ 2773 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2774 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2775 sc->sc_ctxsz * 3); 2776 2777 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2778 2779 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 2780 false); 2781 2782 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2783 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2784 sc->sc_ctxsz * 2); 2785 2786 bad2: 2787 if (err == USBD_NORMAL_COMPLETION) { 2788 xs->xs_idx = slot; 2789 } else { 2790 for (int i = 1; i < dci; i++) { 2791 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2792 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2793 } 2794 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2795 bad1: 2796 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2797 xs->xs_idx = 0; 2798 } 2799 2800 return err; 2801 } 2802 2803 /* ----- */ 2804 2805 static void 2806 xhci_noop(struct usbd_pipe *pipe) 2807 { 2808 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2809 } 2810 2811 /* 2812 * Process root hub request. 2813 */ 2814 static int 2815 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2816 void *buf, int buflen) 2817 { 2818 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2819 usb_port_status_t ps; 2820 int l, totlen = 0; 2821 uint16_t len, value, index; 2822 int port, i; 2823 uint32_t v; 2824 2825 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2826 2827 if (sc->sc_dying) 2828 return -1; 2829 2830 len = UGETW(req->wLength); 2831 value = UGETW(req->wValue); 2832 index = UGETW(req->wIndex); 2833 2834 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 2835 req->bmRequestType | (req->bRequest << 8), value, index, len); 2836 2837 #define C(x,y) ((x) | ((y) << 8)) 2838 switch (C(req->bRequest, req->bmRequestType)) { 2839 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2840 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 2841 if (len == 0) 2842 break; 2843 switch (value) { 2844 case C(0, UDESC_DEVICE): { 2845 usb_device_descriptor_t devd; 2846 totlen = min(buflen, sizeof(devd)); 2847 memcpy(&devd, buf, totlen); 2848 USETW(devd.idVendor, sc->sc_id_vendor); 2849 memcpy(buf, &devd, totlen); 2850 break; 2851 } 2852 #define sd ((usb_string_descriptor_t *)buf) 2853 case C(1, UDESC_STRING): 2854 /* Vendor */ 2855 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2856 break; 2857 case C(2, UDESC_STRING): 2858 /* Product */ 2859 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 2860 break; 2861 #undef sd 2862 default: 2863 /* default from usbroothub */ 2864 return buflen; 2865 } 2866 break; 2867 2868 /* Hub requests */ 2869 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2870 break; 2871 /* Clear Port Feature request */ 2872 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2873 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2874 index, value, 0, 0); 2875 if (index < 1 || index > sc->sc_maxports) { 2876 return -1; 2877 } 2878 port = XHCI_PORTSC(index); 2879 v = xhci_op_read_4(sc, port); 2880 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2881 v &= ~XHCI_PS_CLEAR; 2882 switch (value) { 2883 case UHF_PORT_ENABLE: 2884 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 2885 break; 2886 case UHF_PORT_SUSPEND: 2887 return -1; 2888 case UHF_PORT_POWER: 2889 break; 2890 case UHF_PORT_TEST: 2891 case UHF_PORT_INDICATOR: 2892 return -1; 2893 case UHF_C_PORT_CONNECTION: 2894 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2895 break; 2896 case UHF_C_PORT_ENABLE: 2897 case UHF_C_PORT_SUSPEND: 2898 case UHF_C_PORT_OVER_CURRENT: 2899 return -1; 2900 case UHF_C_BH_PORT_RESET: 2901 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 2902 break; 2903 case UHF_C_PORT_RESET: 2904 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2905 break; 2906 case UHF_C_PORT_LINK_STATE: 2907 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 2908 break; 2909 case UHF_C_PORT_CONFIG_ERROR: 2910 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 2911 break; 2912 default: 2913 return -1; 2914 } 2915 break; 2916 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2917 if (len == 0) 2918 break; 2919 if ((value & 0xff) != 0) { 2920 return -1; 2921 } 2922 usb_hub_descriptor_t hubd; 2923 2924 totlen = min(buflen, sizeof(hubd)); 2925 memcpy(&hubd, buf, totlen); 2926 hubd.bNbrPorts = sc->sc_maxports; 2927 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2928 hubd.bPwrOn2PwrGood = 200; 2929 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 2930 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2931 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2932 totlen = min(totlen, hubd.bDescLength); 2933 memcpy(buf, &hubd, totlen); 2934 break; 2935 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2936 if (len != 4) { 2937 return -1; 2938 } 2939 memset(buf, 0, len); /* ? XXX */ 2940 totlen = len; 2941 break; 2942 /* Get Port Status request */ 2943 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2944 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2945 if (index < 1 || index > sc->sc_maxports) { 2946 return -1; 2947 } 2948 if (len != 4) { 2949 return -1; 2950 } 2951 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 2952 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 2953 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 2954 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2955 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2956 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2957 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 2958 if (v & XHCI_PS_PR) i |= UPS_RESET; 2959 if (v & XHCI_PS_PP) { 2960 if (i & UPS_OTHER_SPEED) 2961 i |= UPS_PORT_POWER_SS; 2962 else 2963 i |= UPS_PORT_POWER; 2964 } 2965 if (i & UPS_OTHER_SPEED) 2966 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 2967 if (sc->sc_vendor_port_status) 2968 i = sc->sc_vendor_port_status(sc, v, i); 2969 USETW(ps.wPortStatus, i); 2970 i = 0; 2971 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2972 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2973 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2974 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2975 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 2976 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 2977 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 2978 USETW(ps.wPortChange, i); 2979 totlen = min(len, sizeof(ps)); 2980 memcpy(buf, &ps, totlen); 2981 break; 2982 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2983 return -1; 2984 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 2985 break; 2986 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2987 break; 2988 /* Set Port Feature request */ 2989 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 2990 int optval = (index >> 8) & 0xff; 2991 index &= 0xff; 2992 if (index < 1 || index > sc->sc_maxports) { 2993 return -1; 2994 } 2995 port = XHCI_PORTSC(index); 2996 v = xhci_op_read_4(sc, port); 2997 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2998 uint32_t v0 = v; 2999 v &= ~XHCI_PS_CLEAR; 3000 switch (value) { 3001 case UHF_PORT_ENABLE: 3002 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3003 break; 3004 case UHF_PORT_SUSPEND: 3005 /* XXX suspend */ 3006 break; 3007 case UHF_PORT_RESET: 3008 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3009 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3010 /* Wait for reset to complete. */ 3011 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3012 if (sc->sc_dying) { 3013 return -1; 3014 } 3015 v = xhci_op_read_4(sc, port); 3016 if (v & XHCI_PS_PR) { 3017 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3018 usb_delay_ms(&sc->sc_bus, 10); 3019 /* XXX */ 3020 } 3021 break; 3022 case UHF_PORT_POWER: 3023 /* XXX power control */ 3024 break; 3025 /* XXX more */ 3026 case UHF_C_PORT_RESET: 3027 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3028 break; 3029 case UHF_PORT_U1_TIMEOUT: 3030 if (XHCI_PS_SPEED_GET(v0) != XHCI_PS_SPEED_SS) { 3031 return -1; 3032 } 3033 port = XHCI_PORTPMSC(index); 3034 v = xhci_op_read_4(sc, port); 3035 v &= ~XHCI_PM3_U1TO_SET(0xff); 3036 v |= XHCI_PM3_U1TO_SET(optval); 3037 xhci_op_write_4(sc, port, v); 3038 break; 3039 case UHF_PORT_U2_TIMEOUT: 3040 if (XHCI_PS_SPEED_GET(v0) != XHCI_PS_SPEED_SS) { 3041 return -1; 3042 } 3043 port = XHCI_PORTPMSC(index); 3044 v = xhci_op_read_4(sc, port); 3045 v &= ~XHCI_PM3_U2TO_SET(0xff); 3046 v |= XHCI_PM3_U2TO_SET(optval); 3047 xhci_op_write_4(sc, port, v); 3048 break; 3049 default: 3050 return -1; 3051 } 3052 } 3053 break; 3054 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3055 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3056 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3057 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3058 break; 3059 default: 3060 /* default from usbroothub */ 3061 return buflen; 3062 } 3063 3064 return totlen; 3065 } 3066 3067 /* root hub interrupt */ 3068 3069 static usbd_status 3070 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3071 { 3072 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3073 usbd_status err; 3074 3075 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3076 3077 /* Insert last in queue. */ 3078 mutex_enter(&sc->sc_lock); 3079 err = usb_insert_transfer(xfer); 3080 mutex_exit(&sc->sc_lock); 3081 if (err) 3082 return err; 3083 3084 /* Pipe isn't running, start first */ 3085 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3086 } 3087 3088 /* Wait for roothub port status/change */ 3089 static usbd_status 3090 xhci_root_intr_start(struct usbd_xfer *xfer) 3091 { 3092 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3093 3094 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3095 3096 if (sc->sc_dying) 3097 return USBD_IOERROR; 3098 3099 mutex_enter(&sc->sc_lock); 3100 sc->sc_intrxfer = xfer; 3101 mutex_exit(&sc->sc_lock); 3102 3103 return USBD_IN_PROGRESS; 3104 } 3105 3106 static void 3107 xhci_root_intr_abort(struct usbd_xfer *xfer) 3108 { 3109 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3110 3111 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3112 3113 KASSERT(mutex_owned(&sc->sc_lock)); 3114 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3115 3116 sc->sc_intrxfer = NULL; 3117 3118 xfer->ux_status = USBD_CANCELLED; 3119 usb_transfer_complete(xfer); 3120 } 3121 3122 static void 3123 xhci_root_intr_close(struct usbd_pipe *pipe) 3124 { 3125 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3126 3127 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3128 3129 KASSERT(mutex_owned(&sc->sc_lock)); 3130 3131 sc->sc_intrxfer = NULL; 3132 } 3133 3134 static void 3135 xhci_root_intr_done(struct usbd_xfer *xfer) 3136 { 3137 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3138 3139 xfer->ux_hcpriv = NULL; 3140 } 3141 3142 /* -------------- */ 3143 /* device control */ 3144 3145 static usbd_status 3146 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3147 { 3148 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3149 usbd_status err; 3150 3151 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3152 3153 /* Insert last in queue. */ 3154 mutex_enter(&sc->sc_lock); 3155 err = usb_insert_transfer(xfer); 3156 mutex_exit(&sc->sc_lock); 3157 if (err) 3158 return err; 3159 3160 /* Pipe isn't running, start first */ 3161 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3162 } 3163 3164 static usbd_status 3165 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3166 { 3167 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3168 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3169 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3170 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3171 struct xhci_xfer * const xx = (void *)xfer; 3172 usb_device_request_t * const req = &xfer->ux_request; 3173 const int isread = usbd_xfer_isread(xfer); 3174 const uint32_t len = UGETW(req->wLength); 3175 usb_dma_t * const dma = &xfer->ux_dmabuf; 3176 uint64_t parameter; 3177 uint32_t status; 3178 uint32_t control; 3179 u_int i; 3180 3181 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3182 DPRINTFN(12, "req: %04x %04x %04x %04x", 3183 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3184 UGETW(req->wIndex), UGETW(req->wLength)); 3185 3186 #if 0 /* event handler does this */ 3187 /* XXX */ 3188 if (tr->is_halted) { 3189 DPRINTFN(1, "ctrl xfer %p halted: slot %u dci %u", 3190 xfer, xs->xs_idx, dci, 0); 3191 xhci_reset_endpoint(xfer->ux_pipe); 3192 tr->is_halted = false; 3193 xhci_set_dequeue(xfer->ux_pipe); 3194 } 3195 #endif 3196 3197 /* we rely on the bottom bits for extra info */ 3198 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 3199 3200 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3201 3202 i = 0; 3203 3204 /* setup phase */ 3205 memcpy(¶meter, req, sizeof(*req)); 3206 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3207 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3208 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3209 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3210 XHCI_TRB_3_IDT_BIT; 3211 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3212 3213 if (len != 0) { 3214 /* data phase */ 3215 parameter = DMAADDR(dma, 0); 3216 KASSERT(len <= 0x10000); 3217 status = XHCI_TRB_2_IRQ_SET(0) | 3218 XHCI_TRB_2_TDSZ_SET(1) | 3219 XHCI_TRB_2_BYTES_SET(len); 3220 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3221 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3222 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3223 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3224 3225 parameter = (uintptr_t)xfer | 0x3; 3226 status = XHCI_TRB_2_IRQ_SET(0); 3227 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3228 XHCI_TRB_3_IOC_BIT; 3229 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3230 } 3231 3232 parameter = 0; 3233 status = XHCI_TRB_2_IRQ_SET(0); 3234 /* the status stage has inverted direction */ 3235 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3236 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3237 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3238 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3239 3240 parameter = (uintptr_t)xfer | 0x0; 3241 status = XHCI_TRB_2_IRQ_SET(0); 3242 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3243 XHCI_TRB_3_IOC_BIT; 3244 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3245 3246 mutex_enter(&tr->xr_lock); 3247 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3248 mutex_exit(&tr->xr_lock); 3249 3250 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3251 3252 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3253 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3254 xhci_timeout, xfer); 3255 } 3256 3257 if (sc->sc_bus.ub_usepolling) { 3258 DPRINTFN(1, "polling", 0, 0, 0, 0); 3259 //xhci_waitintr(sc, xfer); 3260 } 3261 3262 return USBD_IN_PROGRESS; 3263 } 3264 3265 static void 3266 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3267 { 3268 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3269 usb_device_request_t *req = &xfer->ux_request; 3270 int len = UGETW(req->wLength); 3271 int rd = req->bmRequestType & UT_READ; 3272 3273 if (len) 3274 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3275 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3276 } 3277 3278 static void 3279 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3280 { 3281 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3282 3283 xhci_abort_xfer(xfer, USBD_CANCELLED); 3284 } 3285 3286 static void 3287 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3288 { 3289 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3290 3291 xhci_close_pipe(pipe); 3292 } 3293 3294 /* ------------------ */ 3295 /* device isochronous */ 3296 3297 /* ----------- */ 3298 /* device bulk */ 3299 3300 static usbd_status 3301 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3302 { 3303 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3304 usbd_status err; 3305 3306 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3307 3308 /* Insert last in queue. */ 3309 mutex_enter(&sc->sc_lock); 3310 err = usb_insert_transfer(xfer); 3311 mutex_exit(&sc->sc_lock); 3312 if (err) 3313 return err; 3314 3315 /* 3316 * Pipe isn't running (otherwise err would be USBD_INPROG), 3317 * so start it first. 3318 */ 3319 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3320 } 3321 3322 static usbd_status 3323 xhci_device_bulk_start(struct usbd_xfer *xfer) 3324 { 3325 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3326 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3327 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3328 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3329 struct xhci_xfer * const xx = (void *)xfer; 3330 const uint32_t len = xfer->ux_length; 3331 usb_dma_t * const dma = &xfer->ux_dmabuf; 3332 uint64_t parameter; 3333 uint32_t status; 3334 uint32_t control; 3335 u_int i = 0; 3336 3337 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3338 3339 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3340 3341 if (sc->sc_dying) 3342 return USBD_IOERROR; 3343 3344 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3345 3346 parameter = DMAADDR(dma, 0); 3347 /* 3348 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3349 * If the user supplied buffer crosses such a boundary then 2 3350 * (or more) TRB should be used. 3351 * If multiple TRB are used the td_size field must be set correctly. 3352 * For v1.0 devices (like ivy bridge) this is the number of usb data 3353 * blocks needed to complete the transfer. 3354 * Setting it to 1 in the last TRB causes an extra zero-length 3355 * data block be sent. 3356 * The earlier documentation differs, I don't know how it behaves. 3357 */ 3358 KASSERT(len <= 0x10000); 3359 status = XHCI_TRB_2_IRQ_SET(0) | 3360 XHCI_TRB_2_TDSZ_SET(1) | 3361 XHCI_TRB_2_BYTES_SET(len); 3362 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3363 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3364 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3365 3366 mutex_enter(&tr->xr_lock); 3367 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3368 mutex_exit(&tr->xr_lock); 3369 3370 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3371 3372 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3373 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3374 xhci_timeout, xfer); 3375 } 3376 3377 if (sc->sc_bus.ub_usepolling) { 3378 DPRINTFN(1, "polling", 0, 0, 0, 0); 3379 //xhci_waitintr(sc, xfer); 3380 } 3381 3382 return USBD_IN_PROGRESS; 3383 } 3384 3385 static void 3386 xhci_device_bulk_done(struct usbd_xfer *xfer) 3387 { 3388 #ifdef USB_DEBUG 3389 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3390 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3391 #endif 3392 const int isread = usbd_xfer_isread(xfer); 3393 3394 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3395 3396 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3397 3398 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3399 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3400 } 3401 3402 static void 3403 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3404 { 3405 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3406 3407 xhci_abort_xfer(xfer, USBD_CANCELLED); 3408 } 3409 3410 static void 3411 xhci_device_bulk_close(struct usbd_pipe *pipe) 3412 { 3413 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3414 3415 xhci_close_pipe(pipe); 3416 } 3417 3418 /* ---------------- */ 3419 /* device interrupt */ 3420 3421 static usbd_status 3422 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3423 { 3424 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3425 usbd_status err; 3426 3427 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3428 3429 /* Insert last in queue. */ 3430 mutex_enter(&sc->sc_lock); 3431 err = usb_insert_transfer(xfer); 3432 mutex_exit(&sc->sc_lock); 3433 if (err) 3434 return err; 3435 3436 /* 3437 * Pipe isn't running (otherwise err would be USBD_INPROG), 3438 * so start it first. 3439 */ 3440 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3441 } 3442 3443 static usbd_status 3444 xhci_device_intr_start(struct usbd_xfer *xfer) 3445 { 3446 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3447 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3448 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3449 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3450 struct xhci_xfer * const xx = (void *)xfer; 3451 const uint32_t len = xfer->ux_length; 3452 usb_dma_t * const dma = &xfer->ux_dmabuf; 3453 uint64_t parameter; 3454 uint32_t status; 3455 uint32_t control; 3456 u_int i = 0; 3457 3458 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3459 3460 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3461 3462 if (sc->sc_dying) 3463 return USBD_IOERROR; 3464 3465 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3466 3467 parameter = DMAADDR(dma, 0); 3468 KASSERT(len <= 0x10000); 3469 status = XHCI_TRB_2_IRQ_SET(0) | 3470 XHCI_TRB_2_TDSZ_SET(1) | 3471 XHCI_TRB_2_BYTES_SET(len); 3472 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3473 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3474 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3475 3476 mutex_enter(&tr->xr_lock); 3477 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3478 mutex_exit(&tr->xr_lock); 3479 3480 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3481 3482 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3483 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3484 xhci_timeout, xfer); 3485 } 3486 3487 if (sc->sc_bus.ub_usepolling) { 3488 DPRINTFN(1, "polling", 0, 0, 0, 0); 3489 //xhci_waitintr(sc, xfer); 3490 } 3491 3492 return USBD_IN_PROGRESS; 3493 } 3494 3495 static void 3496 xhci_device_intr_done(struct usbd_xfer *xfer) 3497 { 3498 struct xhci_softc * const sc __diagused = 3499 XHCI_XFER2SC(xfer); 3500 #ifdef USB_DEBUG 3501 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3502 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3503 #endif 3504 const int isread = usbd_xfer_isread(xfer); 3505 3506 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3507 3508 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3509 3510 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3511 3512 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3513 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3514 3515 #if 0 3516 device_printf(sc->sc_dev, ""); 3517 for (size_t i = 0; i < xfer->ux_length; i++) { 3518 printf(" %02x", ((uint8_t const *)xfer->ux_buffer)[i]); 3519 } 3520 printf("\n"); 3521 #endif 3522 3523 } 3524 3525 static void 3526 xhci_device_intr_abort(struct usbd_xfer *xfer) 3527 { 3528 struct xhci_softc * const sc __diagused = 3529 XHCI_XFER2SC(xfer); 3530 3531 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3532 3533 KASSERT(mutex_owned(&sc->sc_lock)); 3534 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3535 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3536 xhci_abort_xfer(xfer, USBD_CANCELLED); 3537 } 3538 3539 static void 3540 xhci_device_intr_close(struct usbd_pipe *pipe) 3541 { 3542 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3543 3544 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3545 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3546 3547 xhci_close_pipe(pipe); 3548 } 3549 3550 /* ------------ */ 3551 3552 static void 3553 xhci_timeout(void *addr) 3554 { 3555 struct xhci_xfer * const xx = addr; 3556 struct usbd_xfer * const xfer = &xx->xx_xfer; 3557 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3558 3559 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3560 3561 if (sc->sc_dying) { 3562 return; 3563 } 3564 3565 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 3566 USB_TASKQ_MPSAFE); 3567 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 3568 USB_TASKQ_HC); 3569 } 3570 3571 static void 3572 xhci_timeout_task(void *addr) 3573 { 3574 struct usbd_xfer * const xfer = addr; 3575 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3576 3577 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3578 3579 mutex_enter(&sc->sc_lock); 3580 #if 0 3581 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3582 #else 3583 xfer->ux_status = USBD_TIMEOUT; 3584 usb_transfer_complete(xfer); 3585 #endif 3586 mutex_exit(&sc->sc_lock); 3587 } 3588
Indexes created Wed Oct 01 15:09:59 GMT 2025