xhci.c revision 1.28.2.56
1 /* $NetBSD: xhci.c,v 1.28.2.56 2016/04/10 15:32:26 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 3.1 specification 31 * http://www.usb.org/developers/docs/usb_31_040315.zip 32 * USB rev 2.0 specification 33 * http://www.usb.org/developers/docs/usb20_docs/usb_20_031815.zip 34 * xHCI rev 1.1 specification 35 * http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.28.2.56 2016/04/10 15:32:26 skrll Exp $"); 40 41 #include "opt_usb.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 146 147 static usbd_status xhci_do_command(struct xhci_softc * const, 148 struct xhci_trb * const, int); 149 static usbd_status xhci_do_command1(struct xhci_softc * const, 150 struct xhci_trb * const, int, int); 151 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 152 struct xhci_trb * const, int); 153 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t, int, int); 154 static usbd_status xhci_enable_slot(struct xhci_softc * const, 155 uint8_t * const); 156 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 157 static usbd_status xhci_address_device(struct xhci_softc * const, 158 uint64_t, uint8_t, bool); 159 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 160 struct xhci_slot * const, u_int); 161 static usbd_status xhci_ring_init(struct xhci_softc * const, 162 struct xhci_ring * const, size_t, size_t); 163 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 164 165 static void xhci_noop(struct usbd_pipe *); 166 167 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 168 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 169 static void xhci_root_intr_abort(struct usbd_xfer *); 170 static void xhci_root_intr_close(struct usbd_pipe *); 171 static void xhci_root_intr_done(struct usbd_xfer *); 172 173 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 174 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 175 static void xhci_device_ctrl_abort(struct usbd_xfer *); 176 static void xhci_device_ctrl_close(struct usbd_pipe *); 177 static void xhci_device_ctrl_done(struct usbd_xfer *); 178 179 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 180 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 181 static void xhci_device_intr_abort(struct usbd_xfer *); 182 static void xhci_device_intr_close(struct usbd_pipe *); 183 static void xhci_device_intr_done(struct usbd_xfer *); 184 185 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 186 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 187 static void xhci_device_bulk_abort(struct usbd_xfer *); 188 static void xhci_device_bulk_close(struct usbd_pipe *); 189 static void xhci_device_bulk_done(struct usbd_xfer *); 190 191 static void xhci_timeout(void *); 192 static void xhci_timeout_task(void *); 193 194 static const struct usbd_bus_methods xhci_bus_methods = { 195 .ubm_open = xhci_open, 196 .ubm_softint = xhci_softintr, 197 .ubm_dopoll = xhci_poll, 198 .ubm_allocx = xhci_allocx, 199 .ubm_freex = xhci_freex, 200 .ubm_getlock = xhci_get_lock, 201 .ubm_newdev = xhci_new_device, 202 .ubm_rhctrl = xhci_roothub_ctrl, 203 }; 204 205 static const struct usbd_pipe_methods xhci_root_intr_methods = { 206 .upm_transfer = xhci_root_intr_transfer, 207 .upm_start = xhci_root_intr_start, 208 .upm_abort = xhci_root_intr_abort, 209 .upm_close = xhci_root_intr_close, 210 .upm_cleartoggle = xhci_noop, 211 .upm_done = xhci_root_intr_done, 212 }; 213 214 215 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 216 .upm_transfer = xhci_device_ctrl_transfer, 217 .upm_start = xhci_device_ctrl_start, 218 .upm_abort = xhci_device_ctrl_abort, 219 .upm_close = xhci_device_ctrl_close, 220 .upm_cleartoggle = xhci_noop, 221 .upm_done = xhci_device_ctrl_done, 222 }; 223 224 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 225 .upm_cleartoggle = xhci_noop, 226 }; 227 228 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 229 .upm_transfer = xhci_device_bulk_transfer, 230 .upm_start = xhci_device_bulk_start, 231 .upm_abort = xhci_device_bulk_abort, 232 .upm_close = xhci_device_bulk_close, 233 .upm_cleartoggle = xhci_noop, 234 .upm_done = xhci_device_bulk_done, 235 }; 236 237 static const struct usbd_pipe_methods xhci_device_intr_methods = { 238 .upm_transfer = xhci_device_intr_transfer, 239 .upm_start = xhci_device_intr_start, 240 .upm_abort = xhci_device_intr_abort, 241 .upm_close = xhci_device_intr_close, 242 .upm_cleartoggle = xhci_noop, 243 .upm_done = xhci_device_intr_done, 244 }; 245 246 static inline uint32_t 247 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 248 { 249 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 250 } 251 252 static inline uint32_t 253 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 254 { 255 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 256 } 257 258 static inline void 259 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 260 uint32_t value) 261 { 262 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 263 } 264 265 #if 0 /* unused */ 266 static inline void 267 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 268 uint32_t value) 269 { 270 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 271 } 272 #endif /* unused */ 273 274 static inline uint32_t 275 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 276 { 277 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 278 } 279 280 static inline uint32_t 281 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 282 { 283 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 284 } 285 286 static inline void 287 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 288 uint32_t value) 289 { 290 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 291 } 292 293 #if 0 /* unused */ 294 static inline uint64_t 295 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 296 { 297 uint64_t value; 298 299 if (sc->sc_ac64) { 300 #ifdef XHCI_USE_BUS_SPACE_8 301 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 302 #else 303 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 304 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 305 offset + 4) << 32; 306 #endif 307 } else { 308 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 309 } 310 311 return value; 312 } 313 #endif /* unused */ 314 315 static inline void 316 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 317 uint64_t value) 318 { 319 if (sc->sc_ac64) { 320 #ifdef XHCI_USE_BUS_SPACE_8 321 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 322 #else 323 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 324 (value >> 0) & 0xffffffff); 325 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 326 (value >> 32) & 0xffffffff); 327 #endif 328 } else { 329 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 330 } 331 } 332 333 static inline uint32_t 334 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 335 { 336 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 337 } 338 339 static inline void 340 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 341 uint32_t value) 342 { 343 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 344 } 345 346 #if 0 /* unused */ 347 static inline uint64_t 348 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 349 { 350 uint64_t value; 351 352 if (sc->sc_ac64) { 353 #ifdef XHCI_USE_BUS_SPACE_8 354 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 355 #else 356 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 357 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 358 offset + 4) << 32; 359 #endif 360 } else { 361 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 362 } 363 364 return value; 365 } 366 #endif /* unused */ 367 368 static inline void 369 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 370 uint64_t value) 371 { 372 if (sc->sc_ac64) { 373 #ifdef XHCI_USE_BUS_SPACE_8 374 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 375 #else 376 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 377 (value >> 0) & 0xffffffff); 378 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 379 (value >> 32) & 0xffffffff); 380 #endif 381 } else { 382 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 383 } 384 } 385 386 #if 0 /* unused */ 387 static inline uint32_t 388 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 389 { 390 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 391 } 392 #endif /* unused */ 393 394 static inline void 395 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 396 uint32_t value) 397 { 398 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 399 } 400 401 /* --- */ 402 403 static inline uint8_t 404 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 405 { 406 u_int eptype = 0; 407 408 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 409 case UE_CONTROL: 410 eptype = 0x0; 411 break; 412 case UE_ISOCHRONOUS: 413 eptype = 0x1; 414 break; 415 case UE_BULK: 416 eptype = 0x2; 417 break; 418 case UE_INTERRUPT: 419 eptype = 0x3; 420 break; 421 } 422 423 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 424 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 425 return eptype | 0x4; 426 else 427 return eptype; 428 } 429 430 static u_int 431 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 432 { 433 /* xHCI 1.0 section 4.5.1 */ 434 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 435 u_int in = 0; 436 437 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 438 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 439 in = 1; 440 441 return epaddr * 2 + in; 442 } 443 444 static inline u_int 445 xhci_dci_to_ici(const u_int i) 446 { 447 return i + 1; 448 } 449 450 static inline void * 451 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 452 const u_int dci) 453 { 454 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 455 } 456 457 #if 0 /* unused */ 458 static inline bus_addr_t 459 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 460 const u_int dci) 461 { 462 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 463 } 464 #endif /* unused */ 465 466 static inline void * 467 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 468 const u_int ici) 469 { 470 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 471 } 472 473 static inline bus_addr_t 474 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 475 const u_int ici) 476 { 477 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 478 } 479 480 static inline struct xhci_trb * 481 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 482 { 483 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 484 } 485 486 static inline bus_addr_t 487 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 488 { 489 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 490 } 491 492 static inline void 493 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 494 uint32_t control) 495 { 496 trb->trb_0 = htole64(parameter); 497 trb->trb_2 = htole32(status); 498 trb->trb_3 = htole32(control); 499 } 500 501 /* --- */ 502 503 void 504 xhci_childdet(device_t self, device_t child) 505 { 506 struct xhci_softc * const sc = device_private(self); 507 508 KASSERT(sc->sc_child == child); 509 if (child == sc->sc_child) 510 sc->sc_child = NULL; 511 } 512 513 int 514 xhci_detach(struct xhci_softc *sc, int flags) 515 { 516 int rv = 0; 517 518 if (sc->sc_child != NULL) 519 rv = config_detach(sc->sc_child, flags); 520 521 if (rv != 0) 522 return rv; 523 524 /* XXX unconfigure/free slots */ 525 526 /* verify: */ 527 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 528 xhci_op_write_4(sc, XHCI_USBCMD, 0); 529 /* do we need to wait for stop? */ 530 531 xhci_op_write_8(sc, XHCI_CRCR, 0); 532 xhci_ring_free(sc, &sc->sc_cr); 533 cv_destroy(&sc->sc_command_cv); 534 535 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 536 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 537 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 538 xhci_ring_free(sc, &sc->sc_er); 539 540 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 541 542 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 543 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 544 545 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 546 547 mutex_destroy(&sc->sc_lock); 548 mutex_destroy(&sc->sc_intr_lock); 549 cv_destroy(&sc->sc_softwake_cv); 550 551 pool_cache_destroy(sc->sc_xferpool); 552 553 return rv; 554 } 555 556 int 557 xhci_activate(device_t self, enum devact act) 558 { 559 struct xhci_softc * const sc = device_private(self); 560 561 switch (act) { 562 case DVACT_DEACTIVATE: 563 sc->sc_dying = true; 564 return 0; 565 default: 566 return EOPNOTSUPP; 567 } 568 } 569 570 bool 571 xhci_suspend(device_t dv, const pmf_qual_t *qual) 572 { 573 return false; 574 } 575 576 bool 577 xhci_resume(device_t dv, const pmf_qual_t *qual) 578 { 579 return false; 580 } 581 582 bool 583 xhci_shutdown(device_t self, int flags) 584 { 585 return false; 586 } 587 588 589 static void 590 hexdump(const char *msg, const void *base, size_t len) 591 { 592 #if 0 593 size_t cnt; 594 const uint32_t *p; 595 extern paddr_t vtophys(vaddr_t); 596 597 p = base; 598 cnt = 0; 599 600 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 601 (void *)vtophys((vaddr_t)base)); 602 603 while (cnt < len) { 604 if (cnt % 16 == 0) 605 printf("%p: ", p); 606 else if (cnt % 8 == 0) 607 printf(" |"); 608 printf(" %08x", *p++); 609 cnt += 4; 610 if (cnt % 16 == 0) 611 printf("\n"); 612 } 613 #endif 614 } 615 616 #define XHCI_HCCPREV1_BITS \ 617 "\177\020" /* New bitmask */ \ 618 "f\020\020XECP\0" \ 619 "f\014\4MAXPSA\0" \ 620 "b\013CFC\0" \ 621 "b\012SEC\0" \ 622 "b\011SBD\0" \ 623 "b\010FSE\0" \ 624 "b\7NSS\0" \ 625 "b\6LTC\0" \ 626 "b\5LHRC\0" \ 627 "b\4PIND\0" \ 628 "b\3PPC\0" \ 629 "b\2CZC\0" \ 630 "b\1BNC\0" \ 631 "b\0AC64\0" \ 632 "\0" 633 #define XHCI_HCCV1_x_BITS \ 634 "\177\020" /* New bitmask */ \ 635 "f\020\020XECP\0" \ 636 "f\014\4MAXPSA\0" \ 637 "b\013CFC\0" \ 638 "b\012SEC\0" \ 639 "b\011SPC\0" \ 640 "b\010PAE\0" \ 641 "b\7NSS\0" \ 642 "b\6LTC\0" \ 643 "b\5LHRC\0" \ 644 "b\4PIND\0" \ 645 "b\3PPC\0" \ 646 "b\2CSZ\0" \ 647 "b\1BNC\0" \ 648 "b\0AC64\0" \ 649 "\0" 650 651 int 652 xhci_init(struct xhci_softc *sc) 653 { 654 bus_size_t bsz; 655 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 656 uint32_t ecp, ecr; 657 uint32_t usbcmd, usbsts, pagesize, config; 658 int i; 659 uint16_t hciversion; 660 uint8_t caplength; 661 662 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 663 664 sc->sc_bus.ub_revision = USBREV_3_0; 665 sc->sc_bus.ub_usedma = true; 666 667 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 668 caplength = XHCI_CAP_CAPLENGTH(cap); 669 hciversion = XHCI_CAP_HCIVERSION(cap); 670 671 if (hciversion < XHCI_HCIVERSION_0_96 || 672 hciversion > XHCI_HCIVERSION_1_0) { 673 aprint_normal_dev(sc->sc_dev, 674 "xHCI version %x.%x not known to be supported\n", 675 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 676 } else { 677 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 678 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 679 } 680 681 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 682 &sc->sc_cbh) != 0) { 683 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 684 return ENOMEM; 685 } 686 687 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 688 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 689 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 690 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 691 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 692 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 693 aprint_debug_dev(sc->sc_dev, 694 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 695 696 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 697 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 698 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 699 700 char sbuf[128]; 701 if (hciversion < XHCI_HCIVERSION_1_0) 702 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 703 else 704 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 705 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 706 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 707 708 ecp = XHCI_HCC_XECP(hcc) * 4; 709 while (ecp != 0) { 710 ecr = xhci_read_4(sc, ecp); 711 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 712 switch (XHCI_XECP_ID(ecr)) { 713 case XHCI_ID_PROTOCOLS: { 714 uint32_t w0, w4, w8; 715 uint16_t w2; 716 w0 = xhci_read_4(sc, ecp + 0); 717 w2 = (w0 >> 16) & 0xffff; 718 w4 = xhci_read_4(sc, ecp + 4); 719 w8 = xhci_read_4(sc, ecp + 8); 720 aprint_debug_dev(sc->sc_dev, "SP: %08x %08x %08x\n", 721 w0, w4, w8); 722 if (w4 == 0x20425355 && w2 == 0x0300) { 723 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 724 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 725 } 726 if (w4 == 0x20425355 && w2 == 0x0200) { 727 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 728 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 729 } 730 break; 731 } 732 case XHCI_ID_USB_LEGACY: { 733 uint8_t bios_sem; 734 735 /* Take host controller from BIOS */ 736 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 737 if (bios_sem) { 738 /* sets xHCI to be owned by OS */ 739 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 740 aprint_debug( 741 "waiting for BIOS to give up control\n"); 742 for (i = 0; i < 5000; i++) { 743 bios_sem = xhci_read_1(sc, ecp + 744 XHCI_XECP_BIOS_SEM); 745 if (bios_sem == 0) 746 break; 747 DELAY(1000); 748 } 749 if (bios_sem) 750 printf("timed out waiting for BIOS\n"); 751 } 752 break; 753 } 754 default: 755 break; 756 } 757 ecr = xhci_read_4(sc, ecp); 758 if (XHCI_XECP_NEXT(ecr) == 0) { 759 ecp = 0; 760 } else { 761 ecp += XHCI_XECP_NEXT(ecr) * 4; 762 } 763 } 764 765 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 766 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 767 &sc->sc_obh) != 0) { 768 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 769 return ENOMEM; 770 } 771 772 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 773 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 774 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 775 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 776 return ENOMEM; 777 } 778 779 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 780 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 781 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 782 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 783 return ENOMEM; 784 } 785 786 for (i = 0; i < 100; i++) { 787 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 788 if ((usbsts & XHCI_STS_CNR) == 0) 789 break; 790 usb_delay_ms(&sc->sc_bus, 1); 791 } 792 if (i >= 100) 793 return EIO; 794 795 usbcmd = 0; 796 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 797 usb_delay_ms(&sc->sc_bus, 1); 798 799 usbcmd = XHCI_CMD_HCRST; 800 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 801 for (i = 0; i < 100; i++) { 802 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 803 if ((usbcmd & XHCI_CMD_HCRST) == 0) 804 break; 805 usb_delay_ms(&sc->sc_bus, 1); 806 } 807 if (i >= 100) 808 return EIO; 809 810 for (i = 0; i < 100; i++) { 811 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 812 if ((usbsts & XHCI_STS_CNR) == 0) 813 break; 814 usb_delay_ms(&sc->sc_bus, 1); 815 } 816 if (i >= 100) 817 return EIO; 818 819 if (sc->sc_vendor_init) 820 sc->sc_vendor_init(sc); 821 822 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 823 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 824 pagesize = ffs(pagesize); 825 if (pagesize == 0) 826 return EIO; 827 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 828 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 829 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 830 (uint32_t)sc->sc_maxslots); 831 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 832 833 usbd_status err; 834 835 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 836 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 837 if (sc->sc_maxspbuf != 0) { 838 err = usb_allocmem(&sc->sc_bus, 839 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 840 &sc->sc_spbufarray_dma); 841 if (err) 842 return err; 843 844 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * sc->sc_maxspbuf, KM_SLEEP); 845 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 846 for (i = 0; i < sc->sc_maxspbuf; i++) { 847 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 848 /* allocate contexts */ 849 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 850 sc->sc_pgsz, dma); 851 if (err) 852 return err; 853 spbufarray[i] = htole64(DMAADDR(dma, 0)); 854 usb_syncmem(dma, 0, sc->sc_pgsz, 855 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 856 } 857 858 usb_syncmem(&sc->sc_spbufarray_dma, 0, 859 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 860 } 861 862 config = xhci_op_read_4(sc, XHCI_CONFIG); 863 config &= ~0xFF; 864 config |= sc->sc_maxslots & 0xFF; 865 xhci_op_write_4(sc, XHCI_CONFIG, config); 866 867 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 868 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 869 if (err) { 870 aprint_error_dev(sc->sc_dev, "command ring init fail\n"); 871 return err; 872 } 873 874 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 875 XHCI_EVENT_RING_SEGMENTS_ALIGN); 876 if (err) { 877 aprint_error_dev(sc->sc_dev, "event ring init fail\n"); 878 return err; 879 } 880 881 usb_dma_t *dma; 882 size_t size; 883 size_t align; 884 885 dma = &sc->sc_eventst_dma; 886 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 887 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 888 KASSERT(size <= (512 * 1024)); 889 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 890 err = usb_allocmem(&sc->sc_bus, size, align, dma); 891 892 memset(KERNADDR(dma, 0), 0, size); 893 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 894 aprint_debug_dev(sc->sc_dev, "eventst: %s %016jx %p %zx\n", 895 usbd_errstr(err), 896 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 897 KERNADDR(&sc->sc_eventst_dma, 0), 898 sc->sc_eventst_dma.udma_block->size); 899 900 dma = &sc->sc_dcbaa_dma; 901 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 902 KASSERT(size <= 2048); 903 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 904 err = usb_allocmem(&sc->sc_bus, size, align, dma); 905 906 memset(KERNADDR(dma, 0), 0, size); 907 if (sc->sc_maxspbuf != 0) { 908 /* 909 * DCBA entry 0 hold the scratchbuf array pointer. 910 */ 911 *(uint64_t *)KERNADDR(dma, 0) = 912 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 913 } 914 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 915 aprint_debug_dev(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n", 916 usbd_errstr(err), 917 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 918 KERNADDR(&sc->sc_dcbaa_dma, 0), 919 sc->sc_dcbaa_dma.udma_block->size); 920 921 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 922 KM_SLEEP); 923 924 cv_init(&sc->sc_command_cv, "xhcicmd"); 925 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 926 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 927 cv_init(&sc->sc_softwake_cv, "xhciab"); 928 929 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 930 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 931 932 /* Set up the bus struct. */ 933 sc->sc_bus.ub_methods = &xhci_bus_methods; 934 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 935 936 struct xhci_erste *erst; 937 erst = KERNADDR(&sc->sc_eventst_dma, 0); 938 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 939 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 940 erst[0].erste_3 = htole32(0); 941 usb_syncmem(&sc->sc_eventst_dma, 0, 942 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 943 944 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 945 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 946 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 947 XHCI_ERDP_LO_BUSY); 948 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 949 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 950 sc->sc_cr.xr_cs); 951 952 #if 0 953 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 954 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 955 #endif 956 957 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 958 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 959 /* Intel xhci needs interrupt rate moderated. */ 960 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 961 else 962 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 963 aprint_debug_dev(sc->sc_dev, "setting IMOD %u\n", 964 xhci_rt_read_4(sc, XHCI_IMOD(0))); 965 966 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 967 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 968 xhci_op_read_4(sc, XHCI_USBCMD)); 969 970 return USBD_NORMAL_COMPLETION; 971 } 972 973 int 974 xhci_intr(void *v) 975 { 976 struct xhci_softc * const sc = v; 977 int ret = 0; 978 979 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 980 981 if (sc == NULL) 982 return 0; 983 984 mutex_spin_enter(&sc->sc_intr_lock); 985 986 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 987 goto done; 988 989 /* If we get an interrupt while polling, then just ignore it. */ 990 if (sc->sc_bus.ub_usepolling) { 991 #ifdef DIAGNOSTIC 992 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 993 #endif 994 goto done; 995 } 996 997 ret = xhci_intr1(sc); 998 done: 999 mutex_spin_exit(&sc->sc_intr_lock); 1000 return ret; 1001 } 1002 1003 int 1004 xhci_intr1(struct xhci_softc * const sc) 1005 { 1006 uint32_t usbsts; 1007 uint32_t iman; 1008 1009 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1010 1011 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1012 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1013 #if 0 1014 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1015 return 0; 1016 } 1017 #endif 1018 xhci_op_write_4(sc, XHCI_USBSTS, 1019 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1020 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1021 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1022 1023 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1024 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1025 iman |= XHCI_IMAN_INTR_PEND; 1026 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1027 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1028 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1029 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1030 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1031 1032 usb_schedsoftintr(&sc->sc_bus); 1033 1034 return 1; 1035 } 1036 1037 /* 1038 * 3 port speed types used in USB stack 1039 * 1040 * usbdi speed 1041 * definition: USB_SPEED_* in usb.h 1042 * They are used in struct usbd_device in USB stack. 1043 * ioctl interface uses these values too. 1044 * port_status speed 1045 * definition: UPS_*_SPEED in usb.h 1046 * They are used in usb_port_status_t and valid only for USB 2.0. 1047 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1048 * of usb_port_status_ext_t indicates port speed. 1049 * Note that some 3.0 values overlap with 2.0 values. 1050 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1051 * means UPS_LOW_SPEED in HS.) 1052 * port status returned from hub also uses these values. 1053 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1054 * or more. 1055 * xspeed: 1056 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1057 * They are used in only slot context and PORTSC reg of xhci. 1058 * The difference between usbdi speed and xspeed is 1059 * that FS and LS values are swapped. 1060 */ 1061 1062 /* convert usbdi speed to xspeed */ 1063 static int 1064 xhci_speed2xspeed(int speed) 1065 { 1066 switch (speed) { 1067 case USB_SPEED_LOW: return 2; 1068 case USB_SPEED_FULL: return 1; 1069 default: return speed; 1070 } 1071 } 1072 1073 #if 0 1074 /* convert xspeed to usbdi speed */ 1075 static int 1076 xhci_xspeed2speed(int xspeed) 1077 { 1078 switch (xspeed) { 1079 case 1: return USB_SPEED_FULL; 1080 case 2: return USB_SPEED_LOW; 1081 default: return xspeed; 1082 } 1083 } 1084 #endif 1085 1086 /* convert xspeed to port status speed */ 1087 static int 1088 xhci_xspeed2psspeed(int xspeed) 1089 { 1090 switch (xspeed) { 1091 case 0: return 0; 1092 case 1: return UPS_FULL_SPEED; 1093 case 2: return UPS_LOW_SPEED; 1094 case 3: return UPS_HIGH_SPEED; 1095 default: return UPS_OTHER_SPEED; 1096 } 1097 } 1098 1099 /* construct slot context */ 1100 static void 1101 xhci_setup_sctx(struct usbd_device *dev, uint32_t *cp) 1102 { 1103 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 1104 int speed = dev->ud_speed; 1105 int tthubslot, ttportnum; 1106 bool ishub; 1107 bool usemtt; 1108 1109 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1110 1111 /* 1112 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 1113 * tthubslot: 1114 * This is the slot ID of parent HS hub 1115 * if LS/FS device is connected && connected through HS hub. 1116 * This is 0 if device is not LS/FS device || 1117 * parent hub is not HS hub || 1118 * attached to root hub. 1119 * ttportnum: 1120 * This is the downstream facing port of parent HS hub 1121 * if LS/FS device is connected. 1122 * This is 0 if device is not LS/FS device || 1123 * parent hub is not HS hub || 1124 * attached to root hub. 1125 */ 1126 if (dev->ud_myhsport != NULL && 1127 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1128 (dev->ud_myhub != NULL && 1129 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1130 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 1131 ttportnum = dev->ud_myhsport->up_portno; 1132 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 1133 } else { 1134 ttportnum = 0; 1135 tthubslot = 0; 1136 } 1137 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 1138 dev->ud_myhsport, ttportnum, tthubslot, 0); 1139 1140 /* ishub is valid after reading UDESC_DEVICE */ 1141 ishub = (dd->bDeviceClass == UDCLASS_HUB); 1142 1143 /* dev->ud_hub is valid after reading UDESC_HUB */ 1144 if (ishub && dev->ud_hub) { 1145 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 1146 1147 cp[1] |= htole32(XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts)); 1148 cp[2] |= htole32(XHCI_SCTX_2_TT_THINK_TIME_SET( 1149 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK))); 1150 DPRINTFN(4, "nports=%d ttt=%d", 1151 hd->bNbrPorts, XHCI_SCTX_2_TT_THINK_TIME_GET(cp[2]), 0, 0); 1152 } 1153 1154 #define IS_TTHUB(dd) \ 1155 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 1156 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 1157 1158 /* 1159 * MTT flag is set if 1160 * 1. this is HS hub && MTT is enabled 1161 * or 1162 * 2. this is not hub && this is LS or FS device && 1163 * MTT of parent HS hub (and its parent, too) is enabled 1164 */ 1165 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 1166 usemtt = true; 1167 else if (!ishub && 1168 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 1169 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1170 (dev->ud_myhub != NULL && 1171 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1172 dev->ud_myhsport != NULL && 1173 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 1174 usemtt = true; 1175 else 1176 usemtt = false; 1177 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 1178 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 1179 1180 cp[0] |= htole32( 1181 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)) | 1182 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 1183 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0) 1184 ); 1185 cp[1] |= htole32(0); 1186 cp[2] |= htole32( 1187 XHCI_SCTX_2_IRQ_TARGET_SET(0) | 1188 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 1189 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum) 1190 ); 1191 cp[3] |= htole32(0); 1192 } 1193 1194 static uint32_t 1195 xhci_get_maxburst(struct usbd_pipe *pipe) 1196 { 1197 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1198 usbd_desc_iter_t iter; 1199 const usb_cdc_descriptor_t *cdcd; 1200 const usb_endpoint_ss_comp_descriptor_t * esscd = NULL; 1201 uint32_t maxb = 0; 1202 uint8_t ep; 1203 1204 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc( 1205 pipe->up_dev, UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 1206 usb_desc_iter_init(pipe->up_dev, &iter); 1207 iter.cur = (const void *)cdcd; 1208 1209 /* find endpoint_ss_comp desc for ep of this pipe */ 1210 for (ep = 0;;) { 1211 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 1212 if (cdcd == NULL) 1213 break; 1214 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 1215 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 1216 bEndpointAddress; 1217 if (UE_GET_ADDR(ep) == 1218 UE_GET_ADDR(ed->bEndpointAddress)) { 1219 cdcd = (const usb_cdc_descriptor_t *) 1220 usb_desc_iter_next(&iter); 1221 break; 1222 } 1223 ep = 0; 1224 } 1225 } 1226 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 1227 esscd = (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 1228 maxb = esscd->bMaxBurst; 1229 } 1230 1231 return maxb; 1232 } 1233 1234 /* 1235 * Convert endpoint bInterval value to endpoint context interval value 1236 * for Interrupt pipe. 1237 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 1238 */ 1239 static uint32_t 1240 xhci_bival2ival(uint32_t ival, int speed) 1241 { 1242 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 1243 int i; 1244 1245 /* 1246 * round ival down to "the nearest base 2 multiple of 1247 * bInterval * 8". 1248 * bInterval is at most 255 as its type is uByte. 1249 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 1250 */ 1251 for (i = 10; i > 0; i--) { 1252 if ((ival * 8) >= (1 << i)) 1253 break; 1254 } 1255 ival = i; 1256 } else { 1257 /* Interval = bInterval-1 for SS/HS */ 1258 ival--; 1259 } 1260 1261 return ival; 1262 } 1263 1264 /* 1265 * 4.8.2, 6.2.3.2 1266 * construct common endpoint parameters 1267 */ 1268 static void 1269 xhci_setup_endp_ctx(struct usbd_pipe *pipe, uint32_t *cp) 1270 { 1271 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1272 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1273 const u_int dci = xhci_ep_get_dci(ed); 1274 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1275 uint32_t mps = UGETW(ed->wMaxPacketSize); 1276 uint32_t maxb = 0; 1277 int speed = pipe->up_dev->ud_speed; 1278 uint32_t ival = ed->bInterval; 1279 1280 cp[0] = htole32( 1281 XHCI_EPCTX_0_EPSTATE_SET(0) | 1282 XHCI_EPCTX_0_MULT_SET(0) | /* always 0 except SS iscoh */ 1283 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 1284 XHCI_EPCTX_0_LSA_SET(0) | 1285 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0) 1286 ); 1287 cp[1] = htole32( 1288 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 1289 XHCI_EPCTX_1_HID_SET(0) | 1290 XHCI_EPCTX_1_MAXB_SET(0) 1291 ); 1292 if (xfertype != UE_ISOCHRONOUS) 1293 cp[1] |= htole32(XHCI_EPCTX_1_CERR_SET(3)); 1294 1295 /* 6.2.3.4, 4.8.2.4 */ 1296 if (USB_IS_SS(speed)) { 1297 /* UBS 3.1 9.6.6 */ 1298 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1299 /* UBS 3.1 9.6.7 */ 1300 maxb = xhci_get_maxburst(pipe); 1301 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1302 } else { 1303 /* UBS 2.0 9.6.6 */ 1304 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps))); 1305 1306 /* 6.2.3.4 */ 1307 if (speed == USB_SPEED_HIGH && 1308 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 1309 maxb = UE_GET_TRANS(mps); 1310 } else { 1311 /* LS/FS or HS CTRL or HS BULK */ 1312 maxb = 0; 1313 } 1314 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1315 } 1316 1317 if (xfertype == UE_CONTROL) 1318 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(8)); /* 6.2.3 */ 1319 else if (USB_IS_SS(speed)) 1320 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps)); 1321 else 1322 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps))); 1323 1324 switch (xfertype) { 1325 case UE_CONTROL: 1326 break; 1327 case UE_BULK: 1328 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 1329 break; 1330 case UE_INTERRUPT: 1331 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1332 ival = pipe->up_interval; 1333 1334 ival = xhci_bival2ival(ival, speed); 1335 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1336 break; 1337 case UE_ISOCHRONOUS: 1338 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1339 ival = pipe->up_interval; 1340 1341 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 1342 if (speed == USB_SPEED_FULL) 1343 ival += 3; /* 1ms -> 125us */ 1344 ival--; 1345 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1346 1347 if (USB_IS_SS(speed)) { 1348 /* XXX if LEC = 1, set ESIT instead */ 1349 cp[0] |= htole32(XHCI_EPCTX_0_MULT_SET(0)); 1350 } 1351 break; 1352 default: 1353 break; 1354 } 1355 *(uint64_t *)(&cp[2]) = htole64( 1356 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 1357 XHCI_EPCTX_2_DCS_SET(1)); 1358 } 1359 1360 /* 1361 * Construct input contexts and issue TRB 1362 */ 1363 static usbd_status 1364 xhci_configure_endpoint(struct usbd_pipe *pipe) 1365 { 1366 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1367 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1368 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1369 struct xhci_trb trb; 1370 usbd_status err; 1371 uint32_t *cp; 1372 1373 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1374 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1375 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1376 pipe->up_endpoint->ue_edesc->bmAttributes); 1377 1378 /* XXX ensure input context is available? */ 1379 1380 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1381 1382 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1383 cp[0] = htole32(0); 1384 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 1385 1386 /* set up input slot context */ 1387 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1388 xhci_setup_sctx(pipe->up_dev, cp); 1389 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1390 1391 /* set up input endpoint context */ 1392 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 1393 xhci_setup_endp_ctx(pipe, cp); 1394 1395 /* sync input contexts before they are read from memory */ 1396 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1397 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1398 sc->sc_ctxsz * 1); 1399 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1400 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1401 1402 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1403 trb.trb_2 = 0; 1404 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1405 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1406 1407 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1408 1409 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1410 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1411 sc->sc_ctxsz * 1); 1412 1413 return err; 1414 } 1415 1416 #if 0 1417 static usbd_status 1418 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1419 { 1420 #ifdef USB_DEBUG 1421 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1422 #endif 1423 1424 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1425 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1426 1427 return USBD_NORMAL_COMPLETION; 1428 } 1429 #endif 1430 1431 /* 4.6.8, 6.4.3.7 */ 1432 static usbd_status 1433 xhci_reset_endpoint(struct usbd_pipe *pipe) 1434 { 1435 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1436 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1437 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1438 struct xhci_trb trb; 1439 usbd_status err; 1440 1441 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1442 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1443 1444 KASSERT(!mutex_owned(&sc->sc_lock)); 1445 1446 trb.trb_0 = 0; 1447 trb.trb_2 = 0; 1448 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1449 XHCI_TRB_3_EP_SET(dci) | 1450 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1451 1452 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1453 1454 return err; 1455 } 1456 1457 /* 1458 * 4.6.9, 6.4.3.8 1459 * Stop execution of TDs on xfer ring. 1460 * Should be called with sc_lock held. 1461 */ 1462 static usbd_status 1463 xhci_stop_endpoint(struct usbd_pipe *pipe) 1464 { 1465 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1466 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1467 struct xhci_trb trb; 1468 usbd_status err; 1469 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1470 1471 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1472 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1473 1474 KASSERT(mutex_owned(&sc->sc_lock)); 1475 1476 trb.trb_0 = 0; 1477 trb.trb_2 = 0; 1478 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1479 XHCI_TRB_3_EP_SET(dci) | 1480 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1481 1482 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1483 1484 return err; 1485 } 1486 1487 /* 1488 * Set TR Dequeue Pointer. 1489 * xCHI 1.1 4.6.10 6.4.3.9 1490 * Purge all of the transfer requests on ring. 1491 * EPSTATE of endpoint must be ERROR or STOPPED, or CONTEXT_STATE error. 1492 */ 1493 static usbd_status 1494 xhci_set_dequeue(struct usbd_pipe *pipe) 1495 { 1496 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1497 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1498 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1499 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1500 struct xhci_trb trb; 1501 usbd_status err; 1502 1503 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1504 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1505 1506 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1507 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1508 BUS_DMASYNC_PREWRITE); 1509 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1510 1511 xr->xr_ep = 0; 1512 xr->xr_cs = 1; 1513 1514 /* set DCS */ 1515 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1516 trb.trb_2 = 0; 1517 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1518 XHCI_TRB_3_EP_SET(dci) | 1519 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1520 1521 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1522 1523 return err; 1524 } 1525 1526 /* 1527 * Open new pipe: called from usbd_setup_pipe_flags. 1528 * Fills methods of pipe. 1529 * If pipe is not for ep0, calls configure_endpoint. 1530 */ 1531 static usbd_status 1532 xhci_open(struct usbd_pipe *pipe) 1533 { 1534 struct usbd_device * const dev = pipe->up_dev; 1535 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1536 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1537 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1538 1539 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1540 DPRINTFN(1, "addr %d depth %d port %d speed %d", 1541 dev->ud_addr, dev->ud_depth, dev->ud_powersrc->up_portno, 1542 dev->ud_speed); 1543 1544 if (sc->sc_dying) 1545 return USBD_IOERROR; 1546 1547 /* Root Hub */ 1548 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1549 switch (ed->bEndpointAddress) { 1550 case USB_CONTROL_ENDPOINT: 1551 pipe->up_methods = &roothub_ctrl_methods; 1552 break; 1553 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1554 pipe->up_methods = &xhci_root_intr_methods; 1555 break; 1556 default: 1557 pipe->up_methods = NULL; 1558 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1559 ed->bEndpointAddress, 0, 0, 0); 1560 return USBD_INVAL; 1561 } 1562 return USBD_NORMAL_COMPLETION; 1563 } 1564 1565 switch (xfertype) { 1566 case UE_CONTROL: 1567 pipe->up_methods = &xhci_device_ctrl_methods; 1568 break; 1569 case UE_ISOCHRONOUS: 1570 pipe->up_methods = &xhci_device_isoc_methods; 1571 return USBD_INVAL; 1572 break; 1573 case UE_BULK: 1574 pipe->up_methods = &xhci_device_bulk_methods; 1575 break; 1576 case UE_INTERRUPT: 1577 pipe->up_methods = &xhci_device_intr_methods; 1578 break; 1579 default: 1580 return USBD_IOERROR; 1581 break; 1582 } 1583 1584 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1585 return xhci_configure_endpoint(pipe); 1586 1587 return USBD_NORMAL_COMPLETION; 1588 } 1589 1590 /* 1591 * Closes pipe, called from usbd_kill_pipe via close methods. 1592 * If the endpoint to be closed is ep0, disable_slot. 1593 * Should be called with sc_lock held. 1594 */ 1595 static void 1596 xhci_close_pipe(struct usbd_pipe *pipe) 1597 { 1598 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1599 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1600 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1601 const u_int dci = xhci_ep_get_dci(ed); 1602 struct xhci_trb trb; 1603 uint32_t *cp; 1604 1605 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1606 1607 if (sc->sc_dying) 1608 return; 1609 1610 if (xs == NULL || xs->xs_idx == 0) 1611 /* xs is uninitialized before xhci_init_slot */ 1612 return; 1613 1614 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1615 1616 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1617 KASSERT(mutex_owned(&sc->sc_lock)); 1618 1619 if (pipe->up_dev->ud_depth == 0) 1620 return; 1621 1622 if (dci == XHCI_DCI_EP_CONTROL) { 1623 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1624 xhci_disable_slot(sc, xs->xs_idx); 1625 return; 1626 } 1627 1628 /* 1629 * This may fail in the case that xhci_close_pipe is called after 1630 * xhci_abort_xfer e.g. usbd_kill_pipe. 1631 */ 1632 (void)xhci_stop_endpoint(pipe); 1633 1634 /* 1635 * set appropriate bit to be dropped. 1636 * don't set DC bit to 1, otherwise all endpoints 1637 * would be deconfigured. 1638 */ 1639 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1640 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1641 cp[1] = htole32(0); 1642 1643 /* XXX should be most significant one, not dci? */ 1644 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1645 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1646 1647 /* sync input contexts before they are read from memory */ 1648 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1649 1650 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1651 trb.trb_2 = 0; 1652 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1653 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1654 1655 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1656 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1657 } 1658 1659 /* 1660 * Abort transfer. 1661 * Called with sc_lock held. 1662 * May be called from softintr context. 1663 */ 1664 static void 1665 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1666 { 1667 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1668 1669 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1670 DPRINTFN(4, "xfer %p pipe %p status %d", 1671 xfer, xfer->ux_pipe, status, 0); 1672 1673 KASSERT(mutex_owned(&sc->sc_lock)); 1674 1675 if (sc->sc_dying) { 1676 /* If we're dying, just do the software part. */ 1677 DPRINTFN(4, "dying", 0, 0, 0, 0); 1678 xfer->ux_status = status; /* make software ignore it */ 1679 callout_stop(&xfer->ux_callout); 1680 usb_transfer_complete(xfer); 1681 return; 1682 } 1683 1684 /* XXX need more stuff */ 1685 xfer->ux_status = status; 1686 callout_stop(&xfer->ux_callout); 1687 usb_transfer_complete(xfer); 1688 DPRINTFN(14, "end", 0, 0, 0, 0); 1689 1690 KASSERT(mutex_owned(&sc->sc_lock)); 1691 } 1692 1693 /* 1694 * Recover STALLed endpoint. 1695 * xHCI 1.1 sect 4.10.2.1 1696 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1697 * all transfers on transfer ring. 1698 * These are done in thread context asynchronously. 1699 */ 1700 static void 1701 xhci_clear_endpoint_stall_async_task(void *cookie) 1702 { 1703 struct usbd_xfer * const xfer = cookie; 1704 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1705 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1706 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1707 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1708 1709 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1710 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1711 1712 xhci_reset_endpoint(xfer->ux_pipe); 1713 xhci_set_dequeue(xfer->ux_pipe); 1714 1715 mutex_enter(&sc->sc_lock); 1716 tr->is_halted = false; 1717 usb_transfer_complete(xfer); 1718 mutex_exit(&sc->sc_lock); 1719 DPRINTFN(4, "ends", 0, 0, 0, 0); 1720 } 1721 1722 static usbd_status 1723 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1724 { 1725 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1726 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1727 1728 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1729 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1730 1731 if (sc->sc_dying) { 1732 return USBD_IOERROR; 1733 } 1734 1735 usb_init_task(&xp->xp_async_task, 1736 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1737 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1738 DPRINTFN(4, "ends", 0, 0, 0, 0); 1739 1740 return USBD_NORMAL_COMPLETION; 1741 } 1742 1743 /* Process roothub port status/change events and notify to uhub_intr. */ 1744 static void 1745 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1746 { 1747 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1748 uint8_t *p; 1749 1750 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1751 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1752 port, 0, 0); 1753 1754 if (xfer == NULL) 1755 return; 1756 1757 if (port > sc->sc_maxports) 1758 return; 1759 1760 p = xfer->ux_buf; 1761 memset(p, 0, xfer->ux_length); 1762 p[port/NBBY] |= 1 << (port%NBBY); 1763 xfer->ux_actlen = xfer->ux_length; 1764 xfer->ux_status = USBD_NORMAL_COMPLETION; 1765 usb_transfer_complete(xfer); 1766 } 1767 1768 /* Process Transfer Events */ 1769 static void 1770 xhci_event_transfer(struct xhci_softc * const sc, 1771 const struct xhci_trb * const trb) 1772 { 1773 uint64_t trb_0; 1774 uint32_t trb_2, trb_3; 1775 uint8_t trbcode; 1776 u_int slot, dci; 1777 struct xhci_slot *xs; 1778 struct xhci_ring *xr; 1779 struct xhci_xfer *xx; 1780 struct usbd_xfer *xfer; 1781 usbd_status err; 1782 1783 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1784 1785 trb_0 = le64toh(trb->trb_0); 1786 trb_2 = le32toh(trb->trb_2); 1787 trb_3 = le32toh(trb->trb_3); 1788 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1789 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1790 dci = XHCI_TRB_3_EP_GET(trb_3); 1791 xs = &sc->sc_slots[slot]; 1792 xr = &xs->xs_ep[dci].xe_tr; 1793 1794 /* sanity check */ 1795 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx < sc->sc_maxslots, 1796 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1797 1798 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1799 /* 1800 * When ED == 0, trb_0 is physical address of the TRB 1801 * that caused this event. (6.4.2.1) 1802 */ 1803 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 1804 1805 /* trb_0 range sanity check */ 1806 if (trb_0 < trbp || 1807 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 1808 (trb_0 - trbp) / sizeof(struct xhci_trb) >= 1809 xr->xr_ntrb) { 1810 DPRINTFN(1, "invalid trb_0 0x%"PRIx64" trbp 0x%"PRIx64, 1811 trb_0, trbp, 0, 0); 1812 return; 1813 } 1814 int idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 1815 xx = xr->xr_cookies[idx]; 1816 1817 /* 1818 * If endpoint is stopped between TDs, TRB pointer points at 1819 * next TRB, however, it is not put yet or is a garbage TRB. 1820 * That's why xr_cookies may be NULL or look like broken. 1821 * Note: this ev happens only when hciversion >= 1.0 or 1822 * hciversion == 0.96 and FSE of hcc1 is set. 1823 */ 1824 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1825 DPRINTFN(1, "xx NULL: #%u: cookie %p: code %u trb_0 %" 1826 PRIx64, idx, xx, trbcode, trb_0); 1827 } 1828 } else { 1829 /* When ED != 0, trb_0 is kaddr of struct xhci_xfer. */ 1830 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1831 } 1832 /* XXX this may not happen */ 1833 if (xx == NULL) { 1834 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1835 return; 1836 } 1837 xfer = &xx->xx_xfer; 1838 /* XXX this may happen when detaching */ 1839 if (xfer == NULL) { 1840 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1841 xx, trb_0, 0, 0); 1842 return; 1843 } 1844 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1845 /* XXX I dunno why this happens */ 1846 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1847 1848 if (!xfer->ux_pipe->up_repeat && 1849 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1850 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1851 return; 1852 } 1853 1854 /* 4.11.5.2 Event Data TRB */ 1855 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1856 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1857 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1858 if ((trb_0 & 0x3) == 0x3) { 1859 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1860 } 1861 } 1862 1863 switch (trbcode) { 1864 case XHCI_TRB_ERROR_SHORT_PKT: 1865 case XHCI_TRB_ERROR_SUCCESS: 1866 xfer->ux_actlen = 1867 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1868 err = USBD_NORMAL_COMPLETION; 1869 break; 1870 case XHCI_TRB_ERROR_STALL: 1871 case XHCI_TRB_ERROR_BABBLE: 1872 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1873 xr->is_halted = true; 1874 err = USBD_STALLED; 1875 /* 1876 * Stalled endpoints can be recoverd by issuing 1877 * command TRB TYPE_RESET_EP on xHCI instead of 1878 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1879 * on the endpoint. However, this function may be 1880 * called from softint context (e.g. from umass), 1881 * in that case driver gets KASSERT in cv_timedwait 1882 * in xhci_do_command. 1883 * To avoid this, this runs reset_endpoint and 1884 * usb_transfer_complete in usb task thread 1885 * asynchronously (and then umass issues clear 1886 * UF_ENDPOINT_HALT). 1887 */ 1888 xfer->ux_status = err; 1889 xhci_clear_endpoint_stall_async(xfer); 1890 return; 1891 default: 1892 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1893 err = USBD_IOERROR; 1894 break; 1895 } 1896 xfer->ux_status = err; 1897 1898 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1899 if ((trb_0 & 0x3) == 0x0) { 1900 callout_stop(&xfer->ux_callout); 1901 usb_transfer_complete(xfer); 1902 } 1903 } else { 1904 callout_stop(&xfer->ux_callout); 1905 usb_transfer_complete(xfer); 1906 } 1907 } 1908 1909 /* Process Command complete events */ 1910 static void 1911 xhci_event_cmd(struct xhci_softc * const sc, 1912 const struct xhci_trb * const trb) 1913 { 1914 uint64_t trb_0; 1915 uint32_t trb_2, trb_3; 1916 1917 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1918 1919 trb_0 = le64toh(trb->trb_0); 1920 trb_2 = le32toh(trb->trb_2); 1921 trb_3 = le32toh(trb->trb_3); 1922 1923 if (trb_0 == sc->sc_command_addr) { 1924 sc->sc_result_trb.trb_0 = trb_0; 1925 sc->sc_result_trb.trb_2 = trb_2; 1926 sc->sc_result_trb.trb_3 = trb_3; 1927 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1928 XHCI_TRB_ERROR_SUCCESS) { 1929 DPRINTFN(1, "command completion " 1930 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1931 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1932 } 1933 cv_signal(&sc->sc_command_cv); 1934 } else { 1935 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 1936 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1937 trb_2, trb_3); 1938 } 1939 } 1940 1941 /* 1942 * Process events. 1943 * called from xhci_softintr 1944 */ 1945 static void 1946 xhci_handle_event(struct xhci_softc * const sc, 1947 const struct xhci_trb * const trb) 1948 { 1949 uint64_t trb_0; 1950 uint32_t trb_2, trb_3; 1951 1952 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1953 1954 KASSERT(mutex_owned(&sc->sc_lock)); 1955 1956 trb_0 = le64toh(trb->trb_0); 1957 trb_2 = le32toh(trb->trb_2); 1958 trb_3 = le32toh(trb->trb_3); 1959 1960 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1961 trb, trb_0, trb_2, trb_3); 1962 1963 /* 1964 * 4.11.3.1, 6.4.2.1 1965 * TRB Pointer is invalid for these completion codes. 1966 */ 1967 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 1968 case XHCI_TRB_ERROR_RING_UNDERRUN: 1969 case XHCI_TRB_ERROR_RING_OVERRUN: 1970 case XHCI_TRB_ERROR_VF_RING_FULL: 1971 return; 1972 default: 1973 if (trb_0 == 0) { 1974 return; 1975 } 1976 break; 1977 } 1978 1979 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 1980 case XHCI_TRB_EVENT_TRANSFER: 1981 xhci_event_transfer(sc, trb); 1982 break; 1983 case XHCI_TRB_EVENT_CMD_COMPLETE: 1984 xhci_event_cmd(sc, trb); 1985 break; 1986 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1987 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1988 break; 1989 default: 1990 break; 1991 } 1992 } 1993 1994 static void 1995 xhci_softintr(void *v) 1996 { 1997 struct usbd_bus * const bus = v; 1998 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1999 struct xhci_ring * const er = &sc->sc_er; 2000 struct xhci_trb *trb; 2001 int i, j, k; 2002 2003 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2004 2005 i = er->xr_ep; 2006 j = er->xr_cs; 2007 2008 DPRINTFN(16, "xr_ep %d xr_cs %d", i, j, 0, 0); 2009 2010 while (1) { 2011 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2012 BUS_DMASYNC_POSTREAD); 2013 trb = &er->xr_trb[i]; 2014 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2015 2016 if (j != k) 2017 break; 2018 2019 xhci_handle_event(sc, trb); 2020 2021 i++; 2022 if (i == XHCI_EVENT_RING_TRBS) { 2023 i = 0; 2024 j ^= 1; 2025 } 2026 } 2027 2028 er->xr_ep = i; 2029 er->xr_cs = j; 2030 2031 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2032 XHCI_ERDP_LO_BUSY); 2033 2034 DPRINTFN(16, "ends", 0, 0, 0, 0); 2035 2036 return; 2037 } 2038 2039 static void 2040 xhci_poll(struct usbd_bus *bus) 2041 { 2042 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2043 2044 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2045 2046 mutex_spin_enter(&sc->sc_intr_lock); 2047 xhci_intr1(sc); 2048 mutex_spin_exit(&sc->sc_intr_lock); 2049 2050 return; 2051 } 2052 2053 static struct usbd_xfer * 2054 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2055 { 2056 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2057 struct usbd_xfer *xfer; 2058 2059 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2060 2061 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 2062 if (xfer != NULL) { 2063 memset(xfer, 0, sizeof(struct xhci_xfer)); 2064 #ifdef DIAGNOSTIC 2065 xfer->ux_state = XFER_BUSY; 2066 #endif 2067 } 2068 2069 return xfer; 2070 } 2071 2072 static void 2073 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2074 { 2075 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2076 2077 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2078 2079 #ifdef DIAGNOSTIC 2080 if (xfer->ux_state != XFER_BUSY) { 2081 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 2082 xfer, xfer->ux_state, 0, 0); 2083 } 2084 xfer->ux_state = XFER_FREE; 2085 #endif 2086 pool_cache_put(sc->sc_xferpool, xfer); 2087 } 2088 2089 static void 2090 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2091 { 2092 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2093 2094 *lock = &sc->sc_lock; 2095 } 2096 2097 extern uint32_t usb_cookie_no; 2098 2099 /* 2100 * Called if uhub_explore finds a new device (via usbd_new_device). 2101 * Allocate and construct dev structure of default endpoint (ep0). 2102 * Determine initial MaxPacketSize (mps) by speed. 2103 * Determine route string and roothub port for slot of dev. 2104 * Allocate pipe of ep0. 2105 * Enable and initialize slot and Set Address. 2106 * Read device descriptor. 2107 * Register this device. 2108 */ 2109 static usbd_status 2110 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2111 int speed, int port, struct usbd_port *up) 2112 { 2113 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2114 struct usbd_device *dev; 2115 usbd_status err; 2116 usb_device_descriptor_t *dd; 2117 struct usbd_device *hub; 2118 struct usbd_device *adev; 2119 int rhport = 0; 2120 struct xhci_slot *xs; 2121 uint32_t *cp; 2122 uint32_t route = 0; 2123 uint8_t slot = 0; 2124 uint8_t addr; 2125 2126 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2127 DPRINTFN(4, "port=%d depth=%d speed=%d upport %d", 2128 port, depth, speed, up->up_portno); 2129 2130 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2131 if (dev == NULL) 2132 return USBD_NOMEM; 2133 2134 dev->ud_bus = bus; 2135 2136 /* Set up default endpoint handle. */ 2137 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2138 2139 /* Set up default endpoint descriptor. */ 2140 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2141 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2142 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2143 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2144 /* 4.3, 4.8.2.1 */ 2145 if (USB_IS_SS(speed)) { 2146 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2147 } else 2148 switch (speed) { 2149 case USB_SPEED_FULL: 2150 /* XXX using 64 as initial mps of ep0 in FS */ 2151 case USB_SPEED_HIGH: 2152 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2153 break; 2154 case USB_SPEED_LOW: 2155 default: 2156 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2157 break; 2158 } 2159 dev->ud_ep0desc.bInterval = 0; 2160 2161 /* doesn't matter, just don't let it uninitialized */ 2162 dev->ud_ep0.ue_toggle = 0; 2163 2164 DPRINTFN(4, "up %p portno %d", up, up->up_portno, 0, 0); 2165 2166 dev->ud_quirks = &usbd_no_quirk; 2167 dev->ud_addr = 0; 2168 dev->ud_ddesc.bMaxPacketSize = 0; 2169 dev->ud_depth = depth; 2170 dev->ud_powersrc = up; 2171 dev->ud_myhub = up->up_parent; 2172 2173 up->up_dev = dev; 2174 2175 /* Locate root hub port */ 2176 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2177 uint32_t dep; 2178 2179 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2180 hub, hub->ud_depth, hub->ud_powersrc, 2181 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2182 2183 if (hub->ud_powersrc == NULL) 2184 break; 2185 dep = hub->ud_depth; 2186 if (dep == 0) 2187 break; 2188 rhport = hub->ud_powersrc->up_portno; 2189 if (dep > USB_HUB_MAX_DEPTH) 2190 continue; 2191 2192 route |= 2193 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2194 << ((dep - 1) * 4); 2195 } 2196 route = route >> 4; 2197 DPRINTFN(4, "rhport %d Route %05x hub %p", rhport, route, hub, 0); 2198 2199 /* Locate port on upstream high speed hub */ 2200 for (adev = dev, hub = up->up_parent; 2201 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2202 adev = hub, hub = hub->ud_myhub) 2203 ; 2204 if (hub) { 2205 int p; 2206 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2207 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2208 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2209 goto found; 2210 } 2211 } 2212 panic("xhci_new_device: cannot find HS port"); 2213 found: 2214 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2215 } else { 2216 dev->ud_myhsport = NULL; 2217 } 2218 2219 dev->ud_speed = speed; 2220 dev->ud_langid = USBD_NOLANG; 2221 dev->ud_cookie.cookie = ++usb_cookie_no; 2222 2223 /* Establish the default pipe. */ 2224 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2225 &dev->ud_pipe0); 2226 if (err) { 2227 goto bad; 2228 } 2229 2230 dd = &dev->ud_ddesc; 2231 2232 if ((depth == 0) && (port == 0)) { 2233 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2234 bus->ub_devices[dev->ud_addr] = dev; 2235 err = usbd_get_initial_ddesc(dev, dd); 2236 if (err) 2237 goto bad; 2238 err = usbd_reload_device_desc(dev); 2239 if (err) 2240 goto bad; 2241 } else { 2242 err = xhci_enable_slot(sc, &slot); 2243 if (err) 2244 goto bad; 2245 xs = &sc->sc_slots[slot]; 2246 dev->ud_hcpriv = xs; 2247 err = xhci_init_slot(dev, slot, route, rhport); 2248 if (err) { 2249 dev->ud_hcpriv = NULL; 2250 /* 2251 * We have to disable_slot here because 2252 * xs->xs_idx == 0 when xhci_init_slot fails, 2253 * in that case usbd_remove_dev won't work. 2254 */ 2255 mutex_enter(&sc->sc_lock); 2256 xhci_disable_slot(sc, slot); 2257 mutex_exit(&sc->sc_lock); 2258 goto bad; 2259 } 2260 2261 /* Allow device time to set new address */ 2262 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2263 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2264 //hexdump("slot context", cp, sc->sc_ctxsz); 2265 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2266 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2267 /* XXX ensure we know when the hardware does something 2268 we can't yet cope with */ 2269 KASSERT(addr >= 1 && addr <= 127); 2270 dev->ud_addr = addr; 2271 /* XXX dev->ud_addr not necessarily unique on bus */ 2272 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2273 bus->ub_devices[dev->ud_addr] = dev; 2274 2275 err = usbd_get_initial_ddesc(dev, dd); 2276 if (err) 2277 goto bad; 2278 /* 4.8.2.1 */ 2279 if (USB_IS_SS(speed)) { 2280 if (dd->bMaxPacketSize != 9) { 2281 printf("%s: invalid mps 2^%u for SS ep0," 2282 " using 512\n", 2283 device_xname(sc->sc_dev), 2284 dd->bMaxPacketSize); 2285 dd->bMaxPacketSize = 9; 2286 } 2287 USETW(dev->ud_ep0desc.wMaxPacketSize, 2288 (1 << dd->bMaxPacketSize)); 2289 } else 2290 USETW(dev->ud_ep0desc.wMaxPacketSize, 2291 dd->bMaxPacketSize); 2292 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2293 xhci_update_ep0_mps(sc, xs, 2294 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2295 err = usbd_reload_device_desc(dev); 2296 if (err) 2297 goto bad; 2298 2299 #if 0 2300 /* Re-establish the default pipe with the new MPS. */ 2301 /* In xhci this is done by xhci_update_ep0_mps. */ 2302 usbd_kill_pipe(dev->ud_pipe0); 2303 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2304 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2305 #endif 2306 } 2307 2308 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2309 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2310 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2311 dd->bDeviceClass, dd->bDeviceSubClass, 2312 dd->bDeviceProtocol, 0); 2313 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2314 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2315 dev->ud_speed); 2316 2317 usbd_get_device_strings(dev); 2318 2319 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2320 2321 if ((depth == 0) && (port == 0)) { 2322 usbd_attach_roothub(parent, dev); 2323 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2324 return USBD_NORMAL_COMPLETION; 2325 } 2326 2327 2328 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2329 bad: 2330 if (err != USBD_NORMAL_COMPLETION) { 2331 usbd_remove_device(dev, up); 2332 } 2333 2334 return err; 2335 } 2336 2337 static usbd_status 2338 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2339 size_t ntrb, size_t align) 2340 { 2341 usbd_status err; 2342 size_t size = ntrb * XHCI_TRB_SIZE; 2343 2344 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2345 2346 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2347 if (err) 2348 return err; 2349 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2350 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2351 xr->xr_trb = xhci_ring_trbv(xr, 0); 2352 xr->xr_ntrb = ntrb; 2353 xr->xr_ep = 0; 2354 xr->xr_cs = 1; 2355 memset(xr->xr_trb, 0, size); 2356 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 2357 xr->is_halted = false; 2358 2359 return USBD_NORMAL_COMPLETION; 2360 } 2361 2362 static void 2363 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2364 { 2365 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2366 mutex_destroy(&xr->xr_lock); 2367 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2368 } 2369 2370 static void 2371 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2372 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2373 { 2374 size_t i; 2375 u_int ri; 2376 u_int cs; 2377 uint64_t parameter; 2378 uint32_t status; 2379 uint32_t control; 2380 2381 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2382 2383 KASSERT(ntrbs <= XHCI_XFER_NTRB); 2384 for (i = 0; i < ntrbs; i++) { 2385 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2386 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2387 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2388 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2389 XHCI_TRB_TYPE_LINK); 2390 } 2391 2392 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2393 2394 ri = xr->xr_ep; 2395 cs = xr->xr_cs; 2396 2397 /* 2398 * Although the xhci hardware can do scatter/gather dma from 2399 * arbitrary sized buffers, there is a non-obvious restriction 2400 * that a LINK trb is only allowed at the end of a burst of 2401 * transfers - which might be 16kB. 2402 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2403 * The simple solution is not to allow a LINK trb in the middle 2404 * of anything - as here. 2405 * XXX: (dsl) There are xhci controllers out there (eg some made by 2406 * ASMedia) that seem to lock up if they process a LINK trb but 2407 * cannot process the linked-to trb yet. 2408 * The code should write the 'cycle' bit on the link trb AFTER 2409 * adding the other trb. 2410 */ 2411 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2412 parameter = xhci_ring_trbp(xr, 0); 2413 status = 0; 2414 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2415 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2416 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2417 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2418 BUS_DMASYNC_PREWRITE); 2419 xr->xr_cookies[ri] = NULL; 2420 xr->xr_ep = 0; 2421 xr->xr_cs ^= 1; 2422 ri = xr->xr_ep; 2423 cs = xr->xr_cs; 2424 } 2425 2426 ri++; 2427 2428 /* Write any subsequent TRB first */ 2429 for (i = 1; i < ntrbs; i++) { 2430 parameter = trbs[i].trb_0; 2431 status = trbs[i].trb_2; 2432 control = trbs[i].trb_3; 2433 2434 if (cs) { 2435 control |= XHCI_TRB_3_CYCLE_BIT; 2436 } else { 2437 control &= ~XHCI_TRB_3_CYCLE_BIT; 2438 } 2439 2440 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2441 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2442 BUS_DMASYNC_PREWRITE); 2443 xr->xr_cookies[ri] = cookie; 2444 ri++; 2445 } 2446 2447 /* Write the first TRB last */ 2448 i = 0; 2449 parameter = trbs[i].trb_0; 2450 status = trbs[i].trb_2; 2451 control = trbs[i].trb_3; 2452 2453 if (xr->xr_cs) { 2454 control |= XHCI_TRB_3_CYCLE_BIT; 2455 } else { 2456 control &= ~XHCI_TRB_3_CYCLE_BIT; 2457 } 2458 2459 xhci_trb_put(&xr->xr_trb[xr->xr_ep], parameter, status, control); 2460 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2461 BUS_DMASYNC_PREWRITE); 2462 xr->xr_cookies[xr->xr_ep] = cookie; 2463 2464 xr->xr_ep = ri; 2465 xr->xr_cs = cs; 2466 2467 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2468 } 2469 2470 /* 2471 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2472 * Command completion is notified by cv_signal from xhci_handle_event 2473 * (called from interrupt from xHCI), or timed-out. 2474 * Command validation is performed in xhci_handle_event by checking if 2475 * trb_0 in CMD_COMPLETE TRB and sc->sc_command_addr are identical. 2476 */ 2477 static usbd_status 2478 xhci_do_command1(struct xhci_softc * const sc, struct xhci_trb * const trb, 2479 int timeout, int locked) 2480 { 2481 struct xhci_ring * const cr = &sc->sc_cr; 2482 usbd_status err; 2483 2484 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2485 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2486 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2487 2488 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2489 2490 if (!locked) 2491 mutex_enter(&sc->sc_lock); 2492 2493 /* XXX KASSERT may fire when cv_timedwait unlocks sc_lock */ 2494 KASSERT(sc->sc_command_addr == 0); 2495 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2496 2497 mutex_enter(&cr->xr_lock); 2498 xhci_ring_put(sc, cr, NULL, trb, 1); 2499 mutex_exit(&cr->xr_lock); 2500 2501 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2502 2503 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2504 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2505 err = USBD_TIMEOUT; 2506 goto timedout; 2507 } 2508 2509 trb->trb_0 = sc->sc_result_trb.trb_0; 2510 trb->trb_2 = sc->sc_result_trb.trb_2; 2511 trb->trb_3 = sc->sc_result_trb.trb_3; 2512 2513 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2514 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2515 2516 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2517 case XHCI_TRB_ERROR_SUCCESS: 2518 err = USBD_NORMAL_COMPLETION; 2519 break; 2520 default: 2521 case 192 ... 223: 2522 err = USBD_IOERROR; 2523 break; 2524 case 224 ... 255: 2525 err = USBD_NORMAL_COMPLETION; 2526 break; 2527 } 2528 2529 timedout: 2530 sc->sc_command_addr = 0; 2531 if (!locked) 2532 mutex_exit(&sc->sc_lock); 2533 return err; 2534 } 2535 2536 static usbd_status 2537 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2538 int timeout) 2539 { 2540 return xhci_do_command1(sc, trb, timeout, 0); 2541 } 2542 2543 /* 2544 * This allows xhci_do_command with already sc_lock held. 2545 * This is needed as USB stack calls close methods with sc_lock_held. 2546 * (see usbdivar.h) 2547 */ 2548 static usbd_status 2549 xhci_do_command_locked(struct xhci_softc * const sc, 2550 struct xhci_trb * const trb, int timeout) 2551 { 2552 return xhci_do_command1(sc, trb, timeout, 1); 2553 } 2554 2555 static usbd_status 2556 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2557 { 2558 struct xhci_trb trb; 2559 usbd_status err; 2560 2561 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2562 2563 trb.trb_0 = 0; 2564 trb.trb_2 = 0; 2565 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2566 2567 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2568 if (err != USBD_NORMAL_COMPLETION) { 2569 return err; 2570 } 2571 2572 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2573 2574 return err; 2575 } 2576 2577 /* 2578 * Deallocate DMA buffer and ring buffer, and disable_slot. 2579 * Should be called with sc_lock held. 2580 */ 2581 static usbd_status 2582 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2583 { 2584 struct xhci_trb trb; 2585 struct xhci_slot *xs; 2586 2587 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2588 2589 if (sc->sc_dying) 2590 return USBD_IOERROR; 2591 2592 xs = &sc->sc_slots[slot]; 2593 if (xs->xs_idx != 0) { 2594 for (int i = XHCI_DCI_SLOT + 1; i < 32; i++) { 2595 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2596 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2597 } 2598 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2599 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2600 } 2601 2602 trb.trb_0 = 0; 2603 trb.trb_2 = 0; 2604 trb.trb_3 = htole32( 2605 XHCI_TRB_3_SLOT_SET(slot) | 2606 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2607 2608 return xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2609 } 2610 2611 /* 2612 * Change slot state. 2613 * bsr=0: ENABLED -> ADDRESSED 2614 * bsr=1: ENABLED -> DEFAULT 2615 * see xHCI 1.1 4.5.3, 3.3.4 2616 */ 2617 static usbd_status 2618 xhci_address_device(struct xhci_softc * const sc, 2619 uint64_t icp, uint8_t slot_id, bool bsr) 2620 { 2621 struct xhci_trb trb; 2622 usbd_status err; 2623 2624 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2625 2626 trb.trb_0 = icp; 2627 trb.trb_2 = 0; 2628 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2629 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2630 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2631 2632 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2633 2634 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2635 err = USBD_NO_ADDR; 2636 2637 return err; 2638 } 2639 2640 static usbd_status 2641 xhci_update_ep0_mps(struct xhci_softc * const sc, 2642 struct xhci_slot * const xs, u_int mps) 2643 { 2644 struct xhci_trb trb; 2645 usbd_status err; 2646 uint32_t * cp; 2647 2648 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2649 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2650 2651 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2652 cp[0] = htole32(0); 2653 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2654 2655 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2656 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2657 2658 /* sync input contexts before they are read from memory */ 2659 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2660 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2661 sc->sc_ctxsz * 4); 2662 2663 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2664 trb.trb_2 = 0; 2665 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2666 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2667 2668 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2669 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2670 return err; 2671 } 2672 2673 static void 2674 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2675 { 2676 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2677 2678 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2679 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2680 &dcbaa[si], dcba, si, 0); 2681 2682 dcbaa[si] = htole64(dcba); 2683 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2684 BUS_DMASYNC_PREWRITE); 2685 } 2686 2687 /* 2688 * Allocate DMA buffer and ring buffer for specified slot 2689 * and set Device Context Base Address 2690 * and issue Set Address device command. 2691 */ 2692 static usbd_status 2693 xhci_init_slot(struct usbd_device *dev, uint32_t slot, int route, int rhport) 2694 { 2695 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2696 struct xhci_slot *xs; 2697 usbd_status err; 2698 u_int dci; 2699 uint32_t *cp; 2700 uint32_t mps = UGETW(dev->ud_ep0desc.wMaxPacketSize); 2701 2702 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2703 DPRINTFN(4, "slot %u speed %d rhport %d route %05x", 2704 slot, dev->ud_speed, route, rhport); 2705 2706 xs = &sc->sc_slots[slot]; 2707 2708 /* allocate contexts */ 2709 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2710 &xs->xs_dc_dma); 2711 if (err) 2712 return err; 2713 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2714 2715 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2716 &xs->xs_ic_dma); 2717 if (err) 2718 goto bad1; 2719 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2720 2721 for (dci = 0; dci < 32; dci++) { 2722 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2723 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2724 if (dci == XHCI_DCI_SLOT) 2725 continue; 2726 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2727 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2728 if (err) { 2729 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2730 goto bad2; 2731 } 2732 } 2733 2734 /* set up initial input control context */ 2735 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2736 cp[0] = htole32(0); 2737 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 2738 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2739 2740 /* set up input slot context */ 2741 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2742 xhci_setup_sctx(dev, cp); 2743 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(1)); 2744 cp[0] |= htole32(XHCI_SCTX_0_ROUTE_SET(route)); 2745 cp[1] |= htole32(XHCI_SCTX_1_RH_PORT_SET(rhport)); 2746 2747 /* set up input EP0 context */ 2748 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2749 cp[0] = htole32(0); 2750 cp[1] = htole32( 2751 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 2752 XHCI_EPCTX_1_EPTYPE_SET(4) | 2753 XHCI_EPCTX_1_CERR_SET(3) 2754 ); 2755 /* can't use xhci_ep_get_dci() yet? */ 2756 *(uint64_t *)(&cp[2]) = htole64( 2757 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 2758 XHCI_EPCTX_2_DCS_SET(1)); 2759 cp[4] = htole32( 2760 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 2761 ); 2762 2763 /* sync input contexts before they are read from memory */ 2764 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2765 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2766 sc->sc_ctxsz * 3); 2767 2768 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2769 2770 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 2771 false); 2772 2773 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2774 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2775 sc->sc_ctxsz * 2); 2776 2777 bad2: 2778 if (err == USBD_NORMAL_COMPLETION) { 2779 xs->xs_idx = slot; 2780 } else { 2781 for (int i = 1; i < dci; i++) { 2782 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2783 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2784 } 2785 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2786 bad1: 2787 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2788 xs->xs_idx = 0; 2789 } 2790 2791 return err; 2792 } 2793 2794 /* ----- */ 2795 2796 static void 2797 xhci_noop(struct usbd_pipe *pipe) 2798 { 2799 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2800 } 2801 2802 /* 2803 * Process root hub request. 2804 */ 2805 static int 2806 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2807 void *buf, int buflen) 2808 { 2809 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2810 usb_port_status_t ps; 2811 int l, totlen = 0; 2812 uint16_t len, value, index; 2813 int port, i; 2814 uint32_t v; 2815 2816 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2817 2818 if (sc->sc_dying) 2819 return -1; 2820 2821 len = UGETW(req->wLength); 2822 value = UGETW(req->wValue); 2823 index = UGETW(req->wIndex); 2824 2825 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 2826 req->bmRequestType | (req->bRequest << 8), value, index, len); 2827 2828 #define C(x,y) ((x) | ((y) << 8)) 2829 switch (C(req->bRequest, req->bmRequestType)) { 2830 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2831 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 2832 if (len == 0) 2833 break; 2834 switch (value) { 2835 case C(0, UDESC_DEVICE): { 2836 usb_device_descriptor_t devd; 2837 totlen = min(buflen, sizeof(devd)); 2838 memcpy(&devd, buf, totlen); 2839 USETW(devd.idVendor, sc->sc_id_vendor); 2840 memcpy(buf, &devd, totlen); 2841 break; 2842 } 2843 #define sd ((usb_string_descriptor_t *)buf) 2844 case C(1, UDESC_STRING): 2845 /* Vendor */ 2846 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2847 break; 2848 case C(2, UDESC_STRING): 2849 /* Product */ 2850 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 2851 break; 2852 #undef sd 2853 default: 2854 /* default from usbroothub */ 2855 return buflen; 2856 } 2857 break; 2858 2859 /* Hub requests */ 2860 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2861 break; 2862 /* Clear Port Feature request */ 2863 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2864 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2865 index, value, 0, 0); 2866 if (index < 1 || index > sc->sc_maxports) { 2867 return -1; 2868 } 2869 port = XHCI_PORTSC(index); 2870 v = xhci_op_read_4(sc, port); 2871 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2872 v &= ~XHCI_PS_CLEAR; 2873 switch (value) { 2874 case UHF_PORT_ENABLE: 2875 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 2876 break; 2877 case UHF_PORT_SUSPEND: 2878 return -1; 2879 case UHF_PORT_POWER: 2880 break; 2881 case UHF_PORT_TEST: 2882 case UHF_PORT_INDICATOR: 2883 return -1; 2884 case UHF_C_PORT_CONNECTION: 2885 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2886 break; 2887 case UHF_C_PORT_ENABLE: 2888 case UHF_C_PORT_SUSPEND: 2889 case UHF_C_PORT_OVER_CURRENT: 2890 return -1; 2891 case UHF_C_BH_PORT_RESET: 2892 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 2893 break; 2894 case UHF_C_PORT_RESET: 2895 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2896 break; 2897 case UHF_C_PORT_LINK_STATE: 2898 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 2899 break; 2900 case UHF_C_PORT_CONFIG_ERROR: 2901 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 2902 break; 2903 default: 2904 return -1; 2905 } 2906 break; 2907 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2908 if (len == 0) 2909 break; 2910 if ((value & 0xff) != 0) { 2911 return -1; 2912 } 2913 usb_hub_descriptor_t hubd; 2914 2915 totlen = min(buflen, sizeof(hubd)); 2916 memcpy(&hubd, buf, totlen); 2917 hubd.bNbrPorts = sc->sc_maxports; 2918 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2919 hubd.bPwrOn2PwrGood = 200; 2920 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 2921 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2922 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2923 totlen = min(totlen, hubd.bDescLength); 2924 memcpy(buf, &hubd, totlen); 2925 break; 2926 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2927 if (len != 4) { 2928 return -1; 2929 } 2930 memset(buf, 0, len); /* ? XXX */ 2931 totlen = len; 2932 break; 2933 /* Get Port Status request */ 2934 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2935 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2936 if (index < 1 || index > sc->sc_maxports) { 2937 return -1; 2938 } 2939 if (len != 4) { 2940 return -1; 2941 } 2942 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 2943 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 2944 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 2945 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2946 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2947 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2948 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 2949 if (v & XHCI_PS_PR) i |= UPS_RESET; 2950 if (v & XHCI_PS_PP) { 2951 if (i & UPS_OTHER_SPEED) 2952 i |= UPS_PORT_POWER_SS; 2953 else 2954 i |= UPS_PORT_POWER; 2955 } 2956 if (i & UPS_OTHER_SPEED) 2957 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 2958 if (sc->sc_vendor_port_status) 2959 i = sc->sc_vendor_port_status(sc, v, i); 2960 USETW(ps.wPortStatus, i); 2961 i = 0; 2962 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2963 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2964 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2965 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2966 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 2967 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 2968 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 2969 USETW(ps.wPortChange, i); 2970 totlen = min(len, sizeof(ps)); 2971 memcpy(buf, &ps, totlen); 2972 break; 2973 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2974 return -1; 2975 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 2976 break; 2977 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2978 break; 2979 /* Set Port Feature request */ 2980 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 2981 int optval = (index >> 8) & 0xff; 2982 index &= 0xff; 2983 if (index < 1 || index > sc->sc_maxports) { 2984 return -1; 2985 } 2986 port = XHCI_PORTSC(index); 2987 v = xhci_op_read_4(sc, port); 2988 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2989 uint32_t v0 = v; 2990 v &= ~XHCI_PS_CLEAR; 2991 switch (value) { 2992 case UHF_PORT_ENABLE: 2993 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 2994 break; 2995 case UHF_PORT_SUSPEND: 2996 /* XXX suspend */ 2997 break; 2998 case UHF_PORT_RESET: 2999 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3000 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3001 /* Wait for reset to complete. */ 3002 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3003 if (sc->sc_dying) { 3004 return -1; 3005 } 3006 v = xhci_op_read_4(sc, port); 3007 if (v & XHCI_PS_PR) { 3008 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3009 usb_delay_ms(&sc->sc_bus, 10); 3010 /* XXX */ 3011 } 3012 break; 3013 case UHF_PORT_POWER: 3014 /* XXX power control */ 3015 break; 3016 /* XXX more */ 3017 case UHF_C_PORT_RESET: 3018 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3019 break; 3020 case UHF_PORT_U1_TIMEOUT: 3021 if (XHCI_PS_SPEED_GET(v0) != XHCI_PS_SPEED_SS) { 3022 return -1; 3023 } 3024 port = XHCI_PORTPMSC(index); 3025 v = xhci_op_read_4(sc, port); 3026 v &= ~XHCI_PM3_U1TO_SET(0xff); 3027 v |= XHCI_PM3_U1TO_SET(optval); 3028 xhci_op_write_4(sc, port, v); 3029 break; 3030 case UHF_PORT_U2_TIMEOUT: 3031 if (XHCI_PS_SPEED_GET(v0) != XHCI_PS_SPEED_SS) { 3032 return -1; 3033 } 3034 port = XHCI_PORTPMSC(index); 3035 v = xhci_op_read_4(sc, port); 3036 v &= ~XHCI_PM3_U2TO_SET(0xff); 3037 v |= XHCI_PM3_U2TO_SET(optval); 3038 xhci_op_write_4(sc, port, v); 3039 break; 3040 default: 3041 return -1; 3042 } 3043 } 3044 break; 3045 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3046 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3047 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3048 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3049 break; 3050 default: 3051 /* default from usbroothub */ 3052 return buflen; 3053 } 3054 3055 return totlen; 3056 } 3057 3058 /* root hub interrupt */ 3059 3060 static usbd_status 3061 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3062 { 3063 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3064 usbd_status err; 3065 3066 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3067 3068 /* Insert last in queue. */ 3069 mutex_enter(&sc->sc_lock); 3070 err = usb_insert_transfer(xfer); 3071 mutex_exit(&sc->sc_lock); 3072 if (err) 3073 return err; 3074 3075 /* Pipe isn't running, start first */ 3076 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3077 } 3078 3079 /* Wait for roothub port status/change */ 3080 static usbd_status 3081 xhci_root_intr_start(struct usbd_xfer *xfer) 3082 { 3083 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3084 3085 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3086 3087 if (sc->sc_dying) 3088 return USBD_IOERROR; 3089 3090 mutex_enter(&sc->sc_lock); 3091 sc->sc_intrxfer = xfer; 3092 mutex_exit(&sc->sc_lock); 3093 3094 return USBD_IN_PROGRESS; 3095 } 3096 3097 static void 3098 xhci_root_intr_abort(struct usbd_xfer *xfer) 3099 { 3100 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3101 3102 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3103 3104 KASSERT(mutex_owned(&sc->sc_lock)); 3105 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3106 3107 sc->sc_intrxfer = NULL; 3108 3109 xfer->ux_status = USBD_CANCELLED; 3110 usb_transfer_complete(xfer); 3111 } 3112 3113 static void 3114 xhci_root_intr_close(struct usbd_pipe *pipe) 3115 { 3116 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3117 3118 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3119 3120 KASSERT(mutex_owned(&sc->sc_lock)); 3121 3122 sc->sc_intrxfer = NULL; 3123 } 3124 3125 static void 3126 xhci_root_intr_done(struct usbd_xfer *xfer) 3127 { 3128 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3129 3130 xfer->ux_hcpriv = NULL; 3131 } 3132 3133 /* -------------- */ 3134 /* device control */ 3135 3136 static usbd_status 3137 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3138 { 3139 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3140 usbd_status err; 3141 3142 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3143 3144 /* Insert last in queue. */ 3145 mutex_enter(&sc->sc_lock); 3146 err = usb_insert_transfer(xfer); 3147 mutex_exit(&sc->sc_lock); 3148 if (err) 3149 return err; 3150 3151 /* Pipe isn't running, start first */ 3152 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3153 } 3154 3155 static usbd_status 3156 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3157 { 3158 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3159 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3160 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3161 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3162 struct xhci_xfer * const xx = (void *)xfer; 3163 usb_device_request_t * const req = &xfer->ux_request; 3164 const int isread = usbd_xfer_isread(xfer); 3165 const uint32_t len = UGETW(req->wLength); 3166 usb_dma_t * const dma = &xfer->ux_dmabuf; 3167 uint64_t parameter; 3168 uint32_t status; 3169 uint32_t control; 3170 u_int i; 3171 3172 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3173 DPRINTFN(12, "req: %04x %04x %04x %04x", 3174 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3175 UGETW(req->wIndex), UGETW(req->wLength)); 3176 3177 #if 0 /* event handler does this */ 3178 /* XXX */ 3179 if (tr->is_halted) { 3180 DPRINTFN(1, "ctrl xfer %p halted: slot %u dci %u", 3181 xfer, xs->xs_idx, dci, 0); 3182 xhci_reset_endpoint(xfer->ux_pipe); 3183 tr->is_halted = false; 3184 xhci_set_dequeue(xfer->ux_pipe); 3185 } 3186 #endif 3187 3188 /* we rely on the bottom bits for extra info */ 3189 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 3190 3191 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3192 3193 i = 0; 3194 3195 /* setup phase */ 3196 memcpy(¶meter, req, sizeof(*req)); 3197 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3198 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3199 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3200 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3201 XHCI_TRB_3_IDT_BIT; 3202 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3203 3204 if (len != 0) { 3205 /* data phase */ 3206 parameter = DMAADDR(dma, 0); 3207 KASSERT(len <= 0x10000); 3208 status = XHCI_TRB_2_IRQ_SET(0) | 3209 XHCI_TRB_2_TDSZ_SET(1) | 3210 XHCI_TRB_2_BYTES_SET(len); 3211 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3212 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3213 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3214 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3215 3216 parameter = (uintptr_t)xfer | 0x3; 3217 status = XHCI_TRB_2_IRQ_SET(0); 3218 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3219 XHCI_TRB_3_IOC_BIT; 3220 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3221 } 3222 3223 parameter = 0; 3224 status = XHCI_TRB_2_IRQ_SET(0); 3225 /* the status stage has inverted direction */ 3226 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3227 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3228 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3229 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3230 3231 parameter = (uintptr_t)xfer | 0x0; 3232 status = XHCI_TRB_2_IRQ_SET(0); 3233 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3234 XHCI_TRB_3_IOC_BIT; 3235 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3236 3237 mutex_enter(&tr->xr_lock); 3238 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3239 mutex_exit(&tr->xr_lock); 3240 3241 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3242 3243 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3244 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3245 xhci_timeout, xfer); 3246 } 3247 3248 if (sc->sc_bus.ub_usepolling) { 3249 DPRINTFN(1, "polling", 0, 0, 0, 0); 3250 //xhci_waitintr(sc, xfer); 3251 } 3252 3253 return USBD_IN_PROGRESS; 3254 } 3255 3256 static void 3257 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3258 { 3259 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3260 usb_device_request_t *req = &xfer->ux_request; 3261 int len = UGETW(req->wLength); 3262 int rd = req->bmRequestType & UT_READ; 3263 3264 if (len) 3265 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3266 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3267 } 3268 3269 static void 3270 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3271 { 3272 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3273 3274 xhci_abort_xfer(xfer, USBD_CANCELLED); 3275 } 3276 3277 static void 3278 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3279 { 3280 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3281 3282 xhci_close_pipe(pipe); 3283 } 3284 3285 /* ------------------ */ 3286 /* device isochronous */ 3287 3288 /* ----------- */ 3289 /* device bulk */ 3290 3291 static usbd_status 3292 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3293 { 3294 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3295 usbd_status err; 3296 3297 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3298 3299 /* Insert last in queue. */ 3300 mutex_enter(&sc->sc_lock); 3301 err = usb_insert_transfer(xfer); 3302 mutex_exit(&sc->sc_lock); 3303 if (err) 3304 return err; 3305 3306 /* 3307 * Pipe isn't running (otherwise err would be USBD_INPROG), 3308 * so start it first. 3309 */ 3310 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3311 } 3312 3313 static usbd_status 3314 xhci_device_bulk_start(struct usbd_xfer *xfer) 3315 { 3316 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3317 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3318 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3319 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3320 struct xhci_xfer * const xx = (void *)xfer; 3321 const uint32_t len = xfer->ux_length; 3322 usb_dma_t * const dma = &xfer->ux_dmabuf; 3323 uint64_t parameter; 3324 uint32_t status; 3325 uint32_t control; 3326 u_int i = 0; 3327 3328 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3329 3330 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3331 3332 if (sc->sc_dying) 3333 return USBD_IOERROR; 3334 3335 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3336 3337 parameter = DMAADDR(dma, 0); 3338 /* 3339 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3340 * If the user supplied buffer crosses such a boundary then 2 3341 * (or more) TRB should be used. 3342 * If multiple TRB are used the td_size field must be set correctly. 3343 * For v1.0 devices (like ivy bridge) this is the number of usb data 3344 * blocks needed to complete the transfer. 3345 * Setting it to 1 in the last TRB causes an extra zero-length 3346 * data block be sent. 3347 * The earlier documentation differs, I don't know how it behaves. 3348 */ 3349 KASSERT(len <= 0x10000); 3350 status = XHCI_TRB_2_IRQ_SET(0) | 3351 XHCI_TRB_2_TDSZ_SET(1) | 3352 XHCI_TRB_2_BYTES_SET(len); 3353 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3354 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3355 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3356 3357 mutex_enter(&tr->xr_lock); 3358 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3359 mutex_exit(&tr->xr_lock); 3360 3361 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3362 3363 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3364 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3365 xhci_timeout, xfer); 3366 } 3367 3368 if (sc->sc_bus.ub_usepolling) { 3369 DPRINTFN(1, "polling", 0, 0, 0, 0); 3370 //xhci_waitintr(sc, xfer); 3371 } 3372 3373 return USBD_IN_PROGRESS; 3374 } 3375 3376 static void 3377 xhci_device_bulk_done(struct usbd_xfer *xfer) 3378 { 3379 #ifdef USB_DEBUG 3380 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3381 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3382 #endif 3383 const int isread = usbd_xfer_isread(xfer); 3384 3385 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3386 3387 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3388 3389 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3390 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3391 } 3392 3393 static void 3394 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3395 { 3396 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3397 3398 xhci_abort_xfer(xfer, USBD_CANCELLED); 3399 } 3400 3401 static void 3402 xhci_device_bulk_close(struct usbd_pipe *pipe) 3403 { 3404 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3405 3406 xhci_close_pipe(pipe); 3407 } 3408 3409 /* ---------------- */ 3410 /* device interrupt */ 3411 3412 static usbd_status 3413 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3414 { 3415 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3416 usbd_status err; 3417 3418 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3419 3420 /* Insert last in queue. */ 3421 mutex_enter(&sc->sc_lock); 3422 err = usb_insert_transfer(xfer); 3423 mutex_exit(&sc->sc_lock); 3424 if (err) 3425 return err; 3426 3427 /* 3428 * Pipe isn't running (otherwise err would be USBD_INPROG), 3429 * so start it first. 3430 */ 3431 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3432 } 3433 3434 static usbd_status 3435 xhci_device_intr_start(struct usbd_xfer *xfer) 3436 { 3437 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3438 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3439 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3440 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3441 struct xhci_xfer * const xx = (void *)xfer; 3442 const uint32_t len = xfer->ux_length; 3443 usb_dma_t * const dma = &xfer->ux_dmabuf; 3444 uint64_t parameter; 3445 uint32_t status; 3446 uint32_t control; 3447 u_int i = 0; 3448 3449 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3450 3451 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3452 3453 if (sc->sc_dying) 3454 return USBD_IOERROR; 3455 3456 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3457 3458 parameter = DMAADDR(dma, 0); 3459 KASSERT(len <= 0x10000); 3460 status = XHCI_TRB_2_IRQ_SET(0) | 3461 XHCI_TRB_2_TDSZ_SET(1) | 3462 XHCI_TRB_2_BYTES_SET(len); 3463 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3464 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3465 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3466 3467 mutex_enter(&tr->xr_lock); 3468 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3469 mutex_exit(&tr->xr_lock); 3470 3471 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3472 3473 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3474 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3475 xhci_timeout, xfer); 3476 } 3477 3478 if (sc->sc_bus.ub_usepolling) { 3479 DPRINTFN(1, "polling", 0, 0, 0, 0); 3480 //xhci_waitintr(sc, xfer); 3481 } 3482 3483 return USBD_IN_PROGRESS; 3484 } 3485 3486 static void 3487 xhci_device_intr_done(struct usbd_xfer *xfer) 3488 { 3489 struct xhci_softc * const sc __diagused = 3490 XHCI_XFER2SC(xfer); 3491 #ifdef USB_DEBUG 3492 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3493 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3494 #endif 3495 const int isread = usbd_xfer_isread(xfer); 3496 3497 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3498 3499 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3500 3501 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3502 3503 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3504 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3505 3506 #if 0 3507 device_printf(sc->sc_dev, ""); 3508 for (size_t i = 0; i < xfer->ux_length; i++) { 3509 printf(" %02x", ((uint8_t const *)xfer->ux_buffer)[i]); 3510 } 3511 printf("\n"); 3512 #endif 3513 3514 } 3515 3516 static void 3517 xhci_device_intr_abort(struct usbd_xfer *xfer) 3518 { 3519 struct xhci_softc * const sc __diagused = 3520 XHCI_XFER2SC(xfer); 3521 3522 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3523 3524 KASSERT(mutex_owned(&sc->sc_lock)); 3525 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3526 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3527 xhci_abort_xfer(xfer, USBD_CANCELLED); 3528 } 3529 3530 static void 3531 xhci_device_intr_close(struct usbd_pipe *pipe) 3532 { 3533 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3534 3535 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3536 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3537 3538 xhci_close_pipe(pipe); 3539 } 3540 3541 /* ------------ */ 3542 3543 static void 3544 xhci_timeout(void *addr) 3545 { 3546 struct xhci_xfer * const xx = addr; 3547 struct usbd_xfer * const xfer = &xx->xx_xfer; 3548 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3549 3550 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3551 3552 if (sc->sc_dying) { 3553 return; 3554 } 3555 3556 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 3557 USB_TASKQ_MPSAFE); 3558 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 3559 USB_TASKQ_HC); 3560 } 3561 3562 static void 3563 xhci_timeout_task(void *addr) 3564 { 3565 struct usbd_xfer * const xfer = addr; 3566 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3567 3568 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3569 3570 mutex_enter(&sc->sc_lock); 3571 #if 0 3572 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3573 #else 3574 xfer->ux_status = USBD_TIMEOUT; 3575 usb_transfer_complete(xfer); 3576 #endif 3577 mutex_exit(&sc->sc_lock); 3578 } 3579
Indexes created Wed Oct 01 18:09:54 GMT 2025