xhci.c revision 1.28.2.59
1 /* $NetBSD: xhci.c,v 1.28.2.59 2016/04/10 15:48:34 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 3.1 specification 31 * http://www.usb.org/developers/docs/usb_31_040315.zip 32 * USB rev 2.0 specification 33 * http://www.usb.org/developers/docs/usb20_docs/usb_20_031815.zip 34 * xHCI rev 1.1 specification 35 * http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.28.2.59 2016/04/10 15:48:34 skrll Exp $"); 40 41 #include "opt_usb.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 146 147 static usbd_status xhci_do_command(struct xhci_softc * const, 148 struct xhci_trb * const, int); 149 static usbd_status xhci_do_command1(struct xhci_softc * const, 150 struct xhci_trb * const, int, int); 151 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 152 struct xhci_trb * const, int); 153 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t, int, int); 154 static usbd_status xhci_enable_slot(struct xhci_softc * const, 155 uint8_t * const); 156 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 157 static usbd_status xhci_address_device(struct xhci_softc * const, 158 uint64_t, uint8_t, bool); 159 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 160 struct xhci_slot * const, u_int); 161 static usbd_status xhci_ring_init(struct xhci_softc * const, 162 struct xhci_ring * const, size_t, size_t); 163 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 164 165 static void xhci_noop(struct usbd_pipe *); 166 167 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 168 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 169 static void xhci_root_intr_abort(struct usbd_xfer *); 170 static void xhci_root_intr_close(struct usbd_pipe *); 171 static void xhci_root_intr_done(struct usbd_xfer *); 172 173 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 174 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 175 static void xhci_device_ctrl_abort(struct usbd_xfer *); 176 static void xhci_device_ctrl_close(struct usbd_pipe *); 177 static void xhci_device_ctrl_done(struct usbd_xfer *); 178 179 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 180 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 181 static void xhci_device_intr_abort(struct usbd_xfer *); 182 static void xhci_device_intr_close(struct usbd_pipe *); 183 static void xhci_device_intr_done(struct usbd_xfer *); 184 185 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 186 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 187 static void xhci_device_bulk_abort(struct usbd_xfer *); 188 static void xhci_device_bulk_close(struct usbd_pipe *); 189 static void xhci_device_bulk_done(struct usbd_xfer *); 190 191 static void xhci_timeout(void *); 192 static void xhci_timeout_task(void *); 193 194 static const struct usbd_bus_methods xhci_bus_methods = { 195 .ubm_open = xhci_open, 196 .ubm_softint = xhci_softintr, 197 .ubm_dopoll = xhci_poll, 198 .ubm_allocx = xhci_allocx, 199 .ubm_freex = xhci_freex, 200 .ubm_getlock = xhci_get_lock, 201 .ubm_newdev = xhci_new_device, 202 .ubm_rhctrl = xhci_roothub_ctrl, 203 }; 204 205 static const struct usbd_pipe_methods xhci_root_intr_methods = { 206 .upm_transfer = xhci_root_intr_transfer, 207 .upm_start = xhci_root_intr_start, 208 .upm_abort = xhci_root_intr_abort, 209 .upm_close = xhci_root_intr_close, 210 .upm_cleartoggle = xhci_noop, 211 .upm_done = xhci_root_intr_done, 212 }; 213 214 215 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 216 .upm_transfer = xhci_device_ctrl_transfer, 217 .upm_start = xhci_device_ctrl_start, 218 .upm_abort = xhci_device_ctrl_abort, 219 .upm_close = xhci_device_ctrl_close, 220 .upm_cleartoggle = xhci_noop, 221 .upm_done = xhci_device_ctrl_done, 222 }; 223 224 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 225 .upm_cleartoggle = xhci_noop, 226 }; 227 228 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 229 .upm_transfer = xhci_device_bulk_transfer, 230 .upm_start = xhci_device_bulk_start, 231 .upm_abort = xhci_device_bulk_abort, 232 .upm_close = xhci_device_bulk_close, 233 .upm_cleartoggle = xhci_noop, 234 .upm_done = xhci_device_bulk_done, 235 }; 236 237 static const struct usbd_pipe_methods xhci_device_intr_methods = { 238 .upm_transfer = xhci_device_intr_transfer, 239 .upm_start = xhci_device_intr_start, 240 .upm_abort = xhci_device_intr_abort, 241 .upm_close = xhci_device_intr_close, 242 .upm_cleartoggle = xhci_noop, 243 .upm_done = xhci_device_intr_done, 244 }; 245 246 static inline uint32_t 247 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 248 { 249 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 250 } 251 252 static inline uint32_t 253 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 254 { 255 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 256 } 257 258 static inline void 259 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 260 uint32_t value) 261 { 262 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 263 } 264 265 #if 0 /* unused */ 266 static inline void 267 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 268 uint32_t value) 269 { 270 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 271 } 272 #endif /* unused */ 273 274 static inline uint32_t 275 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 276 { 277 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 278 } 279 280 static inline uint32_t 281 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 282 { 283 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 284 } 285 286 static inline void 287 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 288 uint32_t value) 289 { 290 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 291 } 292 293 #if 0 /* unused */ 294 static inline uint64_t 295 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 296 { 297 uint64_t value; 298 299 if (sc->sc_ac64) { 300 #ifdef XHCI_USE_BUS_SPACE_8 301 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 302 #else 303 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 304 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 305 offset + 4) << 32; 306 #endif 307 } else { 308 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 309 } 310 311 return value; 312 } 313 #endif /* unused */ 314 315 static inline void 316 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 317 uint64_t value) 318 { 319 if (sc->sc_ac64) { 320 #ifdef XHCI_USE_BUS_SPACE_8 321 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 322 #else 323 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 324 (value >> 0) & 0xffffffff); 325 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 326 (value >> 32) & 0xffffffff); 327 #endif 328 } else { 329 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 330 } 331 } 332 333 static inline uint32_t 334 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 335 { 336 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 337 } 338 339 static inline void 340 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 341 uint32_t value) 342 { 343 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 344 } 345 346 #if 0 /* unused */ 347 static inline uint64_t 348 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 349 { 350 uint64_t value; 351 352 if (sc->sc_ac64) { 353 #ifdef XHCI_USE_BUS_SPACE_8 354 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 355 #else 356 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 357 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 358 offset + 4) << 32; 359 #endif 360 } else { 361 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 362 } 363 364 return value; 365 } 366 #endif /* unused */ 367 368 static inline void 369 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 370 uint64_t value) 371 { 372 if (sc->sc_ac64) { 373 #ifdef XHCI_USE_BUS_SPACE_8 374 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 375 #else 376 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 377 (value >> 0) & 0xffffffff); 378 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 379 (value >> 32) & 0xffffffff); 380 #endif 381 } else { 382 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 383 } 384 } 385 386 #if 0 /* unused */ 387 static inline uint32_t 388 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 389 { 390 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 391 } 392 #endif /* unused */ 393 394 static inline void 395 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 396 uint32_t value) 397 { 398 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 399 } 400 401 /* --- */ 402 403 static inline uint8_t 404 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 405 { 406 u_int eptype = 0; 407 408 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 409 case UE_CONTROL: 410 eptype = 0x0; 411 break; 412 case UE_ISOCHRONOUS: 413 eptype = 0x1; 414 break; 415 case UE_BULK: 416 eptype = 0x2; 417 break; 418 case UE_INTERRUPT: 419 eptype = 0x3; 420 break; 421 } 422 423 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 424 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 425 return eptype | 0x4; 426 else 427 return eptype; 428 } 429 430 static u_int 431 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 432 { 433 /* xHCI 1.0 section 4.5.1 */ 434 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 435 u_int in = 0; 436 437 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 438 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 439 in = 1; 440 441 return epaddr * 2 + in; 442 } 443 444 static inline u_int 445 xhci_dci_to_ici(const u_int i) 446 { 447 return i + 1; 448 } 449 450 static inline void * 451 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 452 const u_int dci) 453 { 454 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 455 } 456 457 #if 0 /* unused */ 458 static inline bus_addr_t 459 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 460 const u_int dci) 461 { 462 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 463 } 464 #endif /* unused */ 465 466 static inline void * 467 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 468 const u_int ici) 469 { 470 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 471 } 472 473 static inline bus_addr_t 474 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 475 const u_int ici) 476 { 477 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 478 } 479 480 static inline struct xhci_trb * 481 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 482 { 483 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 484 } 485 486 static inline bus_addr_t 487 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 488 { 489 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 490 } 491 492 static inline void 493 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 494 uint32_t control) 495 { 496 trb->trb_0 = htole64(parameter); 497 trb->trb_2 = htole32(status); 498 trb->trb_3 = htole32(control); 499 } 500 501 /* --- */ 502 503 void 504 xhci_childdet(device_t self, device_t child) 505 { 506 struct xhci_softc * const sc = device_private(self); 507 508 KASSERT(sc->sc_child == child); 509 if (child == sc->sc_child) 510 sc->sc_child = NULL; 511 } 512 513 int 514 xhci_detach(struct xhci_softc *sc, int flags) 515 { 516 int rv = 0; 517 518 if (sc->sc_child != NULL) 519 rv = config_detach(sc->sc_child, flags); 520 521 if (rv != 0) 522 return rv; 523 524 /* XXX unconfigure/free slots */ 525 526 /* verify: */ 527 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 528 xhci_op_write_4(sc, XHCI_USBCMD, 0); 529 /* do we need to wait for stop? */ 530 531 xhci_op_write_8(sc, XHCI_CRCR, 0); 532 xhci_ring_free(sc, &sc->sc_cr); 533 cv_destroy(&sc->sc_command_cv); 534 535 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 536 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 537 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 538 xhci_ring_free(sc, &sc->sc_er); 539 540 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 541 542 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 543 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 544 545 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 546 547 mutex_destroy(&sc->sc_lock); 548 mutex_destroy(&sc->sc_intr_lock); 549 cv_destroy(&sc->sc_softwake_cv); 550 551 pool_cache_destroy(sc->sc_xferpool); 552 553 return rv; 554 } 555 556 int 557 xhci_activate(device_t self, enum devact act) 558 { 559 struct xhci_softc * const sc = device_private(self); 560 561 switch (act) { 562 case DVACT_DEACTIVATE: 563 sc->sc_dying = true; 564 return 0; 565 default: 566 return EOPNOTSUPP; 567 } 568 } 569 570 bool 571 xhci_suspend(device_t dv, const pmf_qual_t *qual) 572 { 573 return false; 574 } 575 576 bool 577 xhci_resume(device_t dv, const pmf_qual_t *qual) 578 { 579 return false; 580 } 581 582 bool 583 xhci_shutdown(device_t self, int flags) 584 { 585 return false; 586 } 587 588 589 static void 590 hexdump(const char *msg, const void *base, size_t len) 591 { 592 #if 0 593 size_t cnt; 594 const uint32_t *p; 595 extern paddr_t vtophys(vaddr_t); 596 597 p = base; 598 cnt = 0; 599 600 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 601 (void *)vtophys((vaddr_t)base)); 602 603 while (cnt < len) { 604 if (cnt % 16 == 0) 605 printf("%p: ", p); 606 else if (cnt % 8 == 0) 607 printf(" |"); 608 printf(" %08x", *p++); 609 cnt += 4; 610 if (cnt % 16 == 0) 611 printf("\n"); 612 } 613 #endif 614 } 615 616 #define XHCI_HCCPREV1_BITS \ 617 "\177\020" /* New bitmask */ \ 618 "f\020\020XECP\0" \ 619 "f\014\4MAXPSA\0" \ 620 "b\013CFC\0" \ 621 "b\012SEC\0" \ 622 "b\011SBD\0" \ 623 "b\010FSE\0" \ 624 "b\7NSS\0" \ 625 "b\6LTC\0" \ 626 "b\5LHRC\0" \ 627 "b\4PIND\0" \ 628 "b\3PPC\0" \ 629 "b\2CZC\0" \ 630 "b\1BNC\0" \ 631 "b\0AC64\0" \ 632 "\0" 633 #define XHCI_HCCV1_x_BITS \ 634 "\177\020" /* New bitmask */ \ 635 "f\020\020XECP\0" \ 636 "f\014\4MAXPSA\0" \ 637 "b\013CFC\0" \ 638 "b\012SEC\0" \ 639 "b\011SPC\0" \ 640 "b\010PAE\0" \ 641 "b\7NSS\0" \ 642 "b\6LTC\0" \ 643 "b\5LHRC\0" \ 644 "b\4PIND\0" \ 645 "b\3PPC\0" \ 646 "b\2CSZ\0" \ 647 "b\1BNC\0" \ 648 "b\0AC64\0" \ 649 "\0" 650 651 int 652 xhci_init(struct xhci_softc *sc) 653 { 654 bus_size_t bsz; 655 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 656 uint32_t ecp, ecr; 657 uint32_t usbcmd, usbsts, pagesize, config; 658 int i; 659 uint16_t hciversion; 660 uint8_t caplength; 661 662 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 663 664 sc->sc_bus.ub_revision = USBREV_3_0; 665 sc->sc_bus.ub_usedma = true; 666 667 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 668 caplength = XHCI_CAP_CAPLENGTH(cap); 669 hciversion = XHCI_CAP_HCIVERSION(cap); 670 671 if (hciversion < XHCI_HCIVERSION_0_96 || 672 hciversion > XHCI_HCIVERSION_1_0) { 673 aprint_normal_dev(sc->sc_dev, 674 "xHCI version %x.%x not known to be supported\n", 675 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 676 } else { 677 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 678 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 679 } 680 681 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 682 &sc->sc_cbh) != 0) { 683 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 684 return ENOMEM; 685 } 686 687 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 688 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 689 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 690 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 691 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 692 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 693 aprint_debug_dev(sc->sc_dev, 694 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 695 696 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 697 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 698 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 699 700 char sbuf[128]; 701 if (hciversion < XHCI_HCIVERSION_1_0) 702 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 703 else 704 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 705 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 706 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 707 708 ecp = XHCI_HCC_XECP(hcc) * 4; 709 while (ecp != 0) { 710 ecr = xhci_read_4(sc, ecp); 711 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 712 switch (XHCI_XECP_ID(ecr)) { 713 case XHCI_ID_PROTOCOLS: { 714 uint32_t w0, w4, w8; 715 uint16_t w2; 716 w0 = xhci_read_4(sc, ecp + 0); 717 w2 = (w0 >> 16) & 0xffff; 718 w4 = xhci_read_4(sc, ecp + 4); 719 w8 = xhci_read_4(sc, ecp + 8); 720 aprint_debug_dev(sc->sc_dev, "SP: %08x %08x %08x\n", 721 w0, w4, w8); 722 if (w4 == 0x20425355 && w2 == 0x0300) { 723 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 724 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 725 } 726 if (w4 == 0x20425355 && w2 == 0x0200) { 727 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 728 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 729 } 730 break; 731 } 732 case XHCI_ID_USB_LEGACY: { 733 uint8_t bios_sem; 734 735 /* Take host controller from BIOS */ 736 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 737 if (bios_sem) { 738 /* sets xHCI to be owned by OS */ 739 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 740 aprint_debug( 741 "waiting for BIOS to give up control\n"); 742 for (i = 0; i < 5000; i++) { 743 bios_sem = xhci_read_1(sc, ecp + 744 XHCI_XECP_BIOS_SEM); 745 if (bios_sem == 0) 746 break; 747 DELAY(1000); 748 } 749 if (bios_sem) 750 printf("timed out waiting for BIOS\n"); 751 } 752 break; 753 } 754 default: 755 break; 756 } 757 ecr = xhci_read_4(sc, ecp); 758 if (XHCI_XECP_NEXT(ecr) == 0) { 759 ecp = 0; 760 } else { 761 ecp += XHCI_XECP_NEXT(ecr) * 4; 762 } 763 } 764 765 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 766 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 767 &sc->sc_obh) != 0) { 768 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 769 return ENOMEM; 770 } 771 772 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 773 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 774 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 775 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 776 return ENOMEM; 777 } 778 779 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 780 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 781 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 782 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 783 return ENOMEM; 784 } 785 786 for (i = 0; i < 100; i++) { 787 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 788 if ((usbsts & XHCI_STS_CNR) == 0) 789 break; 790 usb_delay_ms(&sc->sc_bus, 1); 791 } 792 if (i >= 100) 793 return EIO; 794 795 usbcmd = 0; 796 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 797 usb_delay_ms(&sc->sc_bus, 1); 798 799 usbcmd = XHCI_CMD_HCRST; 800 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 801 for (i = 0; i < 100; i++) { 802 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 803 if ((usbcmd & XHCI_CMD_HCRST) == 0) 804 break; 805 usb_delay_ms(&sc->sc_bus, 1); 806 } 807 if (i >= 100) 808 return EIO; 809 810 for (i = 0; i < 100; i++) { 811 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 812 if ((usbsts & XHCI_STS_CNR) == 0) 813 break; 814 usb_delay_ms(&sc->sc_bus, 1); 815 } 816 if (i >= 100) 817 return EIO; 818 819 if (sc->sc_vendor_init) 820 sc->sc_vendor_init(sc); 821 822 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 823 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 824 pagesize = ffs(pagesize); 825 if (pagesize == 0) 826 return EIO; 827 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 828 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 829 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 830 (uint32_t)sc->sc_maxslots); 831 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 832 833 usbd_status err; 834 835 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 836 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 837 if (sc->sc_maxspbuf != 0) { 838 err = usb_allocmem(&sc->sc_bus, 839 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 840 &sc->sc_spbufarray_dma); 841 if (err) 842 return err; 843 844 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * sc->sc_maxspbuf, KM_SLEEP); 845 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 846 for (i = 0; i < sc->sc_maxspbuf; i++) { 847 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 848 /* allocate contexts */ 849 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 850 sc->sc_pgsz, dma); 851 if (err) 852 return err; 853 spbufarray[i] = htole64(DMAADDR(dma, 0)); 854 usb_syncmem(dma, 0, sc->sc_pgsz, 855 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 856 } 857 858 usb_syncmem(&sc->sc_spbufarray_dma, 0, 859 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 860 } 861 862 config = xhci_op_read_4(sc, XHCI_CONFIG); 863 config &= ~0xFF; 864 config |= sc->sc_maxslots & 0xFF; 865 xhci_op_write_4(sc, XHCI_CONFIG, config); 866 867 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 868 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 869 if (err) { 870 aprint_error_dev(sc->sc_dev, "command ring init fail\n"); 871 return err; 872 } 873 874 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 875 XHCI_EVENT_RING_SEGMENTS_ALIGN); 876 if (err) { 877 aprint_error_dev(sc->sc_dev, "event ring init fail\n"); 878 return err; 879 } 880 881 usb_dma_t *dma; 882 size_t size; 883 size_t align; 884 885 dma = &sc->sc_eventst_dma; 886 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 887 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 888 KASSERT(size <= (512 * 1024)); 889 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 890 err = usb_allocmem(&sc->sc_bus, size, align, dma); 891 892 memset(KERNADDR(dma, 0), 0, size); 893 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 894 aprint_debug_dev(sc->sc_dev, "eventst: %s %016jx %p %zx\n", 895 usbd_errstr(err), 896 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 897 KERNADDR(&sc->sc_eventst_dma, 0), 898 sc->sc_eventst_dma.udma_block->size); 899 900 dma = &sc->sc_dcbaa_dma; 901 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 902 KASSERT(size <= 2048); 903 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 904 err = usb_allocmem(&sc->sc_bus, size, align, dma); 905 906 memset(KERNADDR(dma, 0), 0, size); 907 if (sc->sc_maxspbuf != 0) { 908 /* 909 * DCBA entry 0 hold the scratchbuf array pointer. 910 */ 911 *(uint64_t *)KERNADDR(dma, 0) = 912 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 913 } 914 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 915 aprint_debug_dev(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n", 916 usbd_errstr(err), 917 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 918 KERNADDR(&sc->sc_dcbaa_dma, 0), 919 sc->sc_dcbaa_dma.udma_block->size); 920 921 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 922 KM_SLEEP); 923 924 cv_init(&sc->sc_command_cv, "xhcicmd"); 925 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 926 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 927 cv_init(&sc->sc_softwake_cv, "xhciab"); 928 929 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 930 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 931 932 /* Set up the bus struct. */ 933 sc->sc_bus.ub_methods = &xhci_bus_methods; 934 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 935 936 struct xhci_erste *erst; 937 erst = KERNADDR(&sc->sc_eventst_dma, 0); 938 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 939 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 940 erst[0].erste_3 = htole32(0); 941 usb_syncmem(&sc->sc_eventst_dma, 0, 942 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 943 944 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 945 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 946 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 947 XHCI_ERDP_LO_BUSY); 948 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 949 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 950 sc->sc_cr.xr_cs); 951 952 #if 0 953 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 954 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 955 #endif 956 957 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 958 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 959 /* Intel xhci needs interrupt rate moderated. */ 960 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 961 else 962 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 963 aprint_debug_dev(sc->sc_dev, "setting IMOD %u\n", 964 xhci_rt_read_4(sc, XHCI_IMOD(0))); 965 966 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 967 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 968 xhci_op_read_4(sc, XHCI_USBCMD)); 969 970 return USBD_NORMAL_COMPLETION; 971 } 972 973 int 974 xhci_intr(void *v) 975 { 976 struct xhci_softc * const sc = v; 977 int ret = 0; 978 979 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 980 981 if (sc == NULL) 982 return 0; 983 984 mutex_spin_enter(&sc->sc_intr_lock); 985 986 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 987 goto done; 988 989 /* If we get an interrupt while polling, then just ignore it. */ 990 if (sc->sc_bus.ub_usepolling) { 991 #ifdef DIAGNOSTIC 992 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 993 #endif 994 goto done; 995 } 996 997 ret = xhci_intr1(sc); 998 done: 999 mutex_spin_exit(&sc->sc_intr_lock); 1000 return ret; 1001 } 1002 1003 int 1004 xhci_intr1(struct xhci_softc * const sc) 1005 { 1006 uint32_t usbsts; 1007 uint32_t iman; 1008 1009 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1010 1011 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1012 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1013 #if 0 1014 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1015 return 0; 1016 } 1017 #endif 1018 xhci_op_write_4(sc, XHCI_USBSTS, 1019 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1020 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1021 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1022 1023 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1024 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1025 iman |= XHCI_IMAN_INTR_PEND; 1026 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1027 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1028 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1029 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1030 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1031 1032 usb_schedsoftintr(&sc->sc_bus); 1033 1034 return 1; 1035 } 1036 1037 /* 1038 * 3 port speed types used in USB stack 1039 * 1040 * usbdi speed 1041 * definition: USB_SPEED_* in usb.h 1042 * They are used in struct usbd_device in USB stack. 1043 * ioctl interface uses these values too. 1044 * port_status speed 1045 * definition: UPS_*_SPEED in usb.h 1046 * They are used in usb_port_status_t and valid only for USB 2.0. 1047 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1048 * of usb_port_status_ext_t indicates port speed. 1049 * Note that some 3.0 values overlap with 2.0 values. 1050 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1051 * means UPS_LOW_SPEED in HS.) 1052 * port status returned from hub also uses these values. 1053 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1054 * or more. 1055 * xspeed: 1056 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1057 * They are used in only slot context and PORTSC reg of xhci. 1058 * The difference between usbdi speed and xspeed is 1059 * that FS and LS values are swapped. 1060 */ 1061 1062 /* convert usbdi speed to xspeed */ 1063 static int 1064 xhci_speed2xspeed(int speed) 1065 { 1066 switch (speed) { 1067 case USB_SPEED_LOW: return 2; 1068 case USB_SPEED_FULL: return 1; 1069 default: return speed; 1070 } 1071 } 1072 1073 #if 0 1074 /* convert xspeed to usbdi speed */ 1075 static int 1076 xhci_xspeed2speed(int xspeed) 1077 { 1078 switch (xspeed) { 1079 case 1: return USB_SPEED_FULL; 1080 case 2: return USB_SPEED_LOW; 1081 default: return xspeed; 1082 } 1083 } 1084 #endif 1085 1086 /* convert xspeed to port status speed */ 1087 static int 1088 xhci_xspeed2psspeed(int xspeed) 1089 { 1090 switch (xspeed) { 1091 case 0: return 0; 1092 case 1: return UPS_FULL_SPEED; 1093 case 2: return UPS_LOW_SPEED; 1094 case 3: return UPS_HIGH_SPEED; 1095 default: return UPS_OTHER_SPEED; 1096 } 1097 } 1098 1099 /* construct slot context */ 1100 static void 1101 xhci_setup_sctx(struct usbd_device *dev, uint32_t *cp) 1102 { 1103 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 1104 int speed = dev->ud_speed; 1105 int tthubslot, ttportnum; 1106 bool ishub; 1107 bool usemtt; 1108 1109 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1110 1111 /* 1112 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 1113 * tthubslot: 1114 * This is the slot ID of parent HS hub 1115 * if LS/FS device is connected && connected through HS hub. 1116 * This is 0 if device is not LS/FS device || 1117 * parent hub is not HS hub || 1118 * attached to root hub. 1119 * ttportnum: 1120 * This is the downstream facing port of parent HS hub 1121 * if LS/FS device is connected. 1122 * This is 0 if device is not LS/FS device || 1123 * parent hub is not HS hub || 1124 * attached to root hub. 1125 */ 1126 if (dev->ud_myhsport != NULL && 1127 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1128 (dev->ud_myhub != NULL && 1129 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1130 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 1131 ttportnum = dev->ud_myhsport->up_portno; 1132 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 1133 } else { 1134 ttportnum = 0; 1135 tthubslot = 0; 1136 } 1137 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 1138 dev->ud_myhsport, ttportnum, tthubslot, 0); 1139 1140 /* ishub is valid after reading UDESC_DEVICE */ 1141 ishub = (dd->bDeviceClass == UDCLASS_HUB); 1142 1143 /* dev->ud_hub is valid after reading UDESC_HUB */ 1144 if (ishub && dev->ud_hub) { 1145 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 1146 1147 cp[1] |= htole32(XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts)); 1148 cp[2] |= htole32(XHCI_SCTX_2_TT_THINK_TIME_SET( 1149 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK))); 1150 DPRINTFN(4, "nports=%d ttt=%d", 1151 hd->bNbrPorts, XHCI_SCTX_2_TT_THINK_TIME_GET(cp[2]), 0, 0); 1152 } 1153 1154 #define IS_TTHUB(dd) \ 1155 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 1156 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 1157 1158 /* 1159 * MTT flag is set if 1160 * 1. this is HS hub && MTT is enabled 1161 * or 1162 * 2. this is not hub && this is LS or FS device && 1163 * MTT of parent HS hub (and its parent, too) is enabled 1164 */ 1165 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 1166 usemtt = true; 1167 else if (!ishub && 1168 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 1169 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1170 (dev->ud_myhub != NULL && 1171 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1172 dev->ud_myhsport != NULL && 1173 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 1174 usemtt = true; 1175 else 1176 usemtt = false; 1177 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 1178 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 1179 1180 cp[0] |= htole32( 1181 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)) | 1182 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 1183 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0) 1184 ); 1185 cp[1] |= htole32(0); 1186 cp[2] |= htole32( 1187 XHCI_SCTX_2_IRQ_TARGET_SET(0) | 1188 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 1189 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum) 1190 ); 1191 cp[3] |= htole32(0); 1192 } 1193 1194 static uint32_t 1195 xhci_get_maxburst(struct usbd_pipe *pipe) 1196 { 1197 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1198 usbd_desc_iter_t iter; 1199 const usb_cdc_descriptor_t *cdcd; 1200 const usb_endpoint_ss_comp_descriptor_t * esscd = NULL; 1201 uint32_t maxb = 0; 1202 uint8_t ep; 1203 1204 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc( 1205 pipe->up_dev, UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 1206 usb_desc_iter_init(pipe->up_dev, &iter); 1207 iter.cur = (const void *)cdcd; 1208 1209 /* find endpoint_ss_comp desc for ep of this pipe */ 1210 for (ep = 0;;) { 1211 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 1212 if (cdcd == NULL) 1213 break; 1214 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 1215 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 1216 bEndpointAddress; 1217 if (UE_GET_ADDR(ep) == 1218 UE_GET_ADDR(ed->bEndpointAddress)) { 1219 cdcd = (const usb_cdc_descriptor_t *) 1220 usb_desc_iter_next(&iter); 1221 break; 1222 } 1223 ep = 0; 1224 } 1225 } 1226 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 1227 esscd = (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 1228 maxb = esscd->bMaxBurst; 1229 } 1230 1231 return maxb; 1232 } 1233 1234 /* 1235 * Convert endpoint bInterval value to endpoint context interval value 1236 * for Interrupt pipe. 1237 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 1238 */ 1239 static uint32_t 1240 xhci_bival2ival(uint32_t ival, int speed) 1241 { 1242 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 1243 int i; 1244 1245 /* 1246 * round ival down to "the nearest base 2 multiple of 1247 * bInterval * 8". 1248 * bInterval is at most 255 as its type is uByte. 1249 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 1250 */ 1251 for (i = 10; i > 0; i--) { 1252 if ((ival * 8) >= (1 << i)) 1253 break; 1254 } 1255 ival = i; 1256 } else { 1257 /* Interval = bInterval-1 for SS/HS */ 1258 ival--; 1259 } 1260 1261 return ival; 1262 } 1263 1264 /* 1265 * 4.8.2, 6.2.3.2 1266 * construct common endpoint parameters 1267 */ 1268 static void 1269 xhci_setup_endp_ctx(struct usbd_pipe *pipe, uint32_t *cp) 1270 { 1271 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1272 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1273 const u_int dci = xhci_ep_get_dci(ed); 1274 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1275 uint32_t mps = UGETW(ed->wMaxPacketSize); 1276 uint32_t maxb = 0; 1277 int speed = pipe->up_dev->ud_speed; 1278 uint32_t ival = ed->bInterval; 1279 1280 cp[0] = htole32( 1281 XHCI_EPCTX_0_EPSTATE_SET(0) | 1282 XHCI_EPCTX_0_MULT_SET(0) | /* always 0 except SS iscoh */ 1283 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 1284 XHCI_EPCTX_0_LSA_SET(0) | 1285 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0) 1286 ); 1287 cp[1] = htole32( 1288 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 1289 XHCI_EPCTX_1_HID_SET(0) | 1290 XHCI_EPCTX_1_MAXB_SET(0) 1291 ); 1292 if (xfertype != UE_ISOCHRONOUS) 1293 cp[1] |= htole32(XHCI_EPCTX_1_CERR_SET(3)); 1294 1295 /* 6.2.3.4, 4.8.2.4 */ 1296 if (USB_IS_SS(speed)) { 1297 /* UBS 3.1 9.6.6 */ 1298 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1299 /* UBS 3.1 9.6.7 */ 1300 maxb = xhci_get_maxburst(pipe); 1301 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1302 } else { 1303 /* UBS 2.0 9.6.6 */ 1304 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps))); 1305 1306 /* 6.2.3.4 */ 1307 if (speed == USB_SPEED_HIGH && 1308 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 1309 maxb = UE_GET_TRANS(mps); 1310 } else { 1311 /* LS/FS or HS CTRL or HS BULK */ 1312 maxb = 0; 1313 } 1314 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1315 } 1316 1317 if (xfertype == UE_CONTROL) 1318 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(8)); /* 6.2.3 */ 1319 else if (USB_IS_SS(speed)) 1320 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps)); 1321 else 1322 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps))); 1323 1324 switch (xfertype) { 1325 case UE_CONTROL: 1326 break; 1327 case UE_BULK: 1328 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 1329 break; 1330 case UE_INTERRUPT: 1331 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1332 ival = pipe->up_interval; 1333 1334 ival = xhci_bival2ival(ival, speed); 1335 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1336 break; 1337 case UE_ISOCHRONOUS: 1338 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1339 ival = pipe->up_interval; 1340 1341 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 1342 if (speed == USB_SPEED_FULL) 1343 ival += 3; /* 1ms -> 125us */ 1344 ival--; 1345 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1346 1347 if (USB_IS_SS(speed)) { 1348 /* XXX if LEC = 1, set ESIT instead */ 1349 cp[0] |= htole32(XHCI_EPCTX_0_MULT_SET(0)); 1350 } 1351 break; 1352 default: 1353 break; 1354 } 1355 *(uint64_t *)(&cp[2]) = htole64( 1356 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 1357 XHCI_EPCTX_2_DCS_SET(1)); 1358 } 1359 1360 /* 1361 * Construct input contexts and issue TRB 1362 */ 1363 static usbd_status 1364 xhci_configure_endpoint(struct usbd_pipe *pipe) 1365 { 1366 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1367 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1368 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1369 struct xhci_trb trb; 1370 usbd_status err; 1371 uint32_t *cp; 1372 1373 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1374 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1375 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1376 pipe->up_endpoint->ue_edesc->bmAttributes); 1377 1378 /* XXX ensure input context is available? */ 1379 1380 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1381 1382 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1383 cp[0] = htole32(0); 1384 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 1385 1386 /* set up input slot context */ 1387 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1388 xhci_setup_sctx(pipe->up_dev, cp); 1389 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1390 1391 /* set up input endpoint context */ 1392 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 1393 xhci_setup_endp_ctx(pipe, cp); 1394 1395 /* sync input contexts before they are read from memory */ 1396 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1397 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1398 sc->sc_ctxsz * 1); 1399 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1400 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1401 1402 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1403 trb.trb_2 = 0; 1404 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1405 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1406 1407 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1408 1409 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1410 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1411 sc->sc_ctxsz * 1); 1412 1413 return err; 1414 } 1415 1416 #if 0 1417 static usbd_status 1418 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1419 { 1420 #ifdef USB_DEBUG 1421 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1422 #endif 1423 1424 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1425 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1426 1427 return USBD_NORMAL_COMPLETION; 1428 } 1429 #endif 1430 1431 /* 4.6.8, 6.4.3.7 */ 1432 static usbd_status 1433 xhci_reset_endpoint(struct usbd_pipe *pipe) 1434 { 1435 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1436 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1437 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1438 struct xhci_trb trb; 1439 usbd_status err; 1440 1441 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1442 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1443 1444 KASSERT(!mutex_owned(&sc->sc_lock)); 1445 1446 trb.trb_0 = 0; 1447 trb.trb_2 = 0; 1448 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1449 XHCI_TRB_3_EP_SET(dci) | 1450 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1451 1452 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1453 1454 return err; 1455 } 1456 1457 /* 1458 * 4.6.9, 6.4.3.8 1459 * Stop execution of TDs on xfer ring. 1460 * Should be called with sc_lock held. 1461 */ 1462 static usbd_status 1463 xhci_stop_endpoint(struct usbd_pipe *pipe) 1464 { 1465 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1466 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1467 struct xhci_trb trb; 1468 usbd_status err; 1469 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1470 1471 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1472 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1473 1474 KASSERT(mutex_owned(&sc->sc_lock)); 1475 1476 trb.trb_0 = 0; 1477 trb.trb_2 = 0; 1478 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1479 XHCI_TRB_3_EP_SET(dci) | 1480 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1481 1482 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1483 1484 return err; 1485 } 1486 1487 /* 1488 * Set TR Dequeue Pointer. 1489 * xCHI 1.1 4.6.10 6.4.3.9 1490 * Purge all of the transfer requests on ring. 1491 * EPSTATE of endpoint must be ERROR or STOPPED, or CONTEXT_STATE error. 1492 */ 1493 static usbd_status 1494 xhci_set_dequeue(struct usbd_pipe *pipe) 1495 { 1496 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1497 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1498 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1499 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1500 struct xhci_trb trb; 1501 usbd_status err; 1502 1503 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1504 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1505 1506 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1507 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1508 BUS_DMASYNC_PREWRITE); 1509 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1510 1511 xr->xr_ep = 0; 1512 xr->xr_cs = 1; 1513 1514 /* set DCS */ 1515 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1516 trb.trb_2 = 0; 1517 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1518 XHCI_TRB_3_EP_SET(dci) | 1519 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1520 1521 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1522 1523 return err; 1524 } 1525 1526 /* 1527 * Open new pipe: called from usbd_setup_pipe_flags. 1528 * Fills methods of pipe. 1529 * If pipe is not for ep0, calls configure_endpoint. 1530 */ 1531 static usbd_status 1532 xhci_open(struct usbd_pipe *pipe) 1533 { 1534 struct usbd_device * const dev = pipe->up_dev; 1535 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1536 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1537 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1538 1539 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1540 DPRINTFN(1, "addr %d depth %d port %d speed %d", 1541 dev->ud_addr, dev->ud_depth, dev->ud_powersrc->up_portno, 1542 dev->ud_speed); 1543 1544 if (sc->sc_dying) 1545 return USBD_IOERROR; 1546 1547 /* Root Hub */ 1548 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1549 switch (ed->bEndpointAddress) { 1550 case USB_CONTROL_ENDPOINT: 1551 pipe->up_methods = &roothub_ctrl_methods; 1552 break; 1553 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1554 pipe->up_methods = &xhci_root_intr_methods; 1555 break; 1556 default: 1557 pipe->up_methods = NULL; 1558 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1559 ed->bEndpointAddress, 0, 0, 0); 1560 return USBD_INVAL; 1561 } 1562 return USBD_NORMAL_COMPLETION; 1563 } 1564 1565 switch (xfertype) { 1566 case UE_CONTROL: 1567 pipe->up_methods = &xhci_device_ctrl_methods; 1568 break; 1569 case UE_ISOCHRONOUS: 1570 pipe->up_methods = &xhci_device_isoc_methods; 1571 return USBD_INVAL; 1572 break; 1573 case UE_BULK: 1574 pipe->up_methods = &xhci_device_bulk_methods; 1575 break; 1576 case UE_INTERRUPT: 1577 pipe->up_methods = &xhci_device_intr_methods; 1578 break; 1579 default: 1580 return USBD_IOERROR; 1581 break; 1582 } 1583 1584 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1585 return xhci_configure_endpoint(pipe); 1586 1587 return USBD_NORMAL_COMPLETION; 1588 } 1589 1590 /* 1591 * Closes pipe, called from usbd_kill_pipe via close methods. 1592 * If the endpoint to be closed is ep0, disable_slot. 1593 * Should be called with sc_lock held. 1594 */ 1595 static void 1596 xhci_close_pipe(struct usbd_pipe *pipe) 1597 { 1598 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1599 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1600 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1601 const u_int dci = xhci_ep_get_dci(ed); 1602 struct xhci_trb trb; 1603 uint32_t *cp; 1604 1605 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1606 1607 if (sc->sc_dying) 1608 return; 1609 1610 if (xs == NULL || xs->xs_idx == 0) 1611 /* xs is uninitialized before xhci_init_slot */ 1612 return; 1613 1614 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1615 1616 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1617 KASSERT(mutex_owned(&sc->sc_lock)); 1618 1619 if (pipe->up_dev->ud_depth == 0) 1620 return; 1621 1622 if (dci == XHCI_DCI_EP_CONTROL) { 1623 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1624 xhci_disable_slot(sc, xs->xs_idx); 1625 return; 1626 } 1627 1628 /* 1629 * This may fail in the case that xhci_close_pipe is called after 1630 * xhci_abort_xfer e.g. usbd_kill_pipe. 1631 */ 1632 (void)xhci_stop_endpoint(pipe); 1633 1634 /* 1635 * set appropriate bit to be dropped. 1636 * don't set DC bit to 1, otherwise all endpoints 1637 * would be deconfigured. 1638 */ 1639 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1640 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1641 cp[1] = htole32(0); 1642 1643 /* XXX should be most significant one, not dci? */ 1644 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1645 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1646 1647 /* sync input contexts before they are read from memory */ 1648 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1649 1650 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1651 trb.trb_2 = 0; 1652 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1653 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1654 1655 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1656 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1657 } 1658 1659 /* 1660 * Abort transfer. 1661 * Called with sc_lock held. 1662 * May be called from softintr context. 1663 */ 1664 static void 1665 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1666 { 1667 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1668 1669 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1670 DPRINTFN(4, "xfer %p pipe %p status %d", 1671 xfer, xfer->ux_pipe, status, 0); 1672 1673 KASSERT(mutex_owned(&sc->sc_lock)); 1674 1675 if (sc->sc_dying) { 1676 /* If we're dying, just do the software part. */ 1677 DPRINTFN(4, "dying", 0, 0, 0, 0); 1678 xfer->ux_status = status; /* make software ignore it */ 1679 callout_stop(&xfer->ux_callout); 1680 usb_transfer_complete(xfer); 1681 return; 1682 } 1683 1684 /* XXX need more stuff */ 1685 xfer->ux_status = status; 1686 callout_stop(&xfer->ux_callout); 1687 usb_transfer_complete(xfer); 1688 DPRINTFN(14, "end", 0, 0, 0, 0); 1689 1690 KASSERT(mutex_owned(&sc->sc_lock)); 1691 } 1692 1693 /* 1694 * Recover STALLed endpoint. 1695 * xHCI 1.1 sect 4.10.2.1 1696 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1697 * all transfers on transfer ring. 1698 * These are done in thread context asynchronously. 1699 */ 1700 static void 1701 xhci_clear_endpoint_stall_async_task(void *cookie) 1702 { 1703 struct usbd_xfer * const xfer = cookie; 1704 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1705 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1706 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1707 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1708 1709 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1710 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1711 1712 xhci_reset_endpoint(xfer->ux_pipe); 1713 xhci_set_dequeue(xfer->ux_pipe); 1714 1715 mutex_enter(&sc->sc_lock); 1716 tr->is_halted = false; 1717 usb_transfer_complete(xfer); 1718 mutex_exit(&sc->sc_lock); 1719 DPRINTFN(4, "ends", 0, 0, 0, 0); 1720 } 1721 1722 static usbd_status 1723 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1724 { 1725 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1726 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1727 1728 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1729 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1730 1731 if (sc->sc_dying) { 1732 return USBD_IOERROR; 1733 } 1734 1735 usb_init_task(&xp->xp_async_task, 1736 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1737 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1738 DPRINTFN(4, "ends", 0, 0, 0, 0); 1739 1740 return USBD_NORMAL_COMPLETION; 1741 } 1742 1743 /* Process roothub port status/change events and notify to uhub_intr. */ 1744 static void 1745 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1746 { 1747 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1748 uint8_t *p; 1749 1750 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1751 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1752 port, 0, 0); 1753 1754 if (xfer == NULL) 1755 return; 1756 1757 if (port > sc->sc_maxports) 1758 return; 1759 1760 p = xfer->ux_buf; 1761 memset(p, 0, xfer->ux_length); 1762 p[port/NBBY] |= 1 << (port%NBBY); 1763 xfer->ux_actlen = xfer->ux_length; 1764 xfer->ux_status = USBD_NORMAL_COMPLETION; 1765 usb_transfer_complete(xfer); 1766 } 1767 1768 /* Process Transfer Events */ 1769 static void 1770 xhci_event_transfer(struct xhci_softc * const sc, 1771 const struct xhci_trb * const trb) 1772 { 1773 uint64_t trb_0; 1774 uint32_t trb_2, trb_3; 1775 uint8_t trbcode; 1776 u_int slot, dci; 1777 struct xhci_slot *xs; 1778 struct xhci_ring *xr; 1779 struct xhci_xfer *xx; 1780 struct usbd_xfer *xfer; 1781 usbd_status err; 1782 1783 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1784 1785 trb_0 = le64toh(trb->trb_0); 1786 trb_2 = le32toh(trb->trb_2); 1787 trb_3 = le32toh(trb->trb_3); 1788 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1789 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1790 dci = XHCI_TRB_3_EP_GET(trb_3); 1791 xs = &sc->sc_slots[slot]; 1792 xr = &xs->xs_ep[dci].xe_tr; 1793 1794 /* sanity check */ 1795 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1796 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1797 1798 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1799 /* 1800 * When ED == 0, trb_0 is physical address of the TRB 1801 * that caused this event. (6.4.2.1) 1802 */ 1803 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 1804 1805 /* trb_0 range sanity check */ 1806 if (trb_0 < trbp || 1807 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 1808 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 1809 DPRINTFN(1, "invalid trb_0 0x%"PRIx64" trbp 0x%"PRIx64, 1810 trb_0, trbp, 0, 0); 1811 return; 1812 } 1813 int idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 1814 xx = xr->xr_cookies[idx]; 1815 1816 /* 1817 * If endpoint is stopped between TDs, TRB pointer points at 1818 * next TRB, however, it is not put yet or is a garbage TRB. 1819 * That's why xr_cookies may be NULL or look like broken. 1820 * Note: this ev happens only when hciversion >= 1.0 or 1821 * hciversion == 0.96 and FSE of hcc1 is set. 1822 */ 1823 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1824 DPRINTFN(1, "xx NULL: #%u: cookie %p: code %u trb_0 %" 1825 PRIx64, idx, xx, trbcode, trb_0); 1826 } 1827 } else { 1828 /* When ED != 0, trb_0 is kaddr of struct xhci_xfer. */ 1829 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1830 } 1831 /* XXX this may not happen */ 1832 if (xx == NULL) { 1833 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1834 return; 1835 } 1836 xfer = &xx->xx_xfer; 1837 /* XXX this may happen when detaching */ 1838 if (xfer == NULL) { 1839 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1840 xx, trb_0, 0, 0); 1841 return; 1842 } 1843 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1844 /* XXX I dunno why this happens */ 1845 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1846 1847 if (!xfer->ux_pipe->up_repeat && 1848 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1849 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1850 return; 1851 } 1852 1853 /* 4.11.5.2 Event Data TRB */ 1854 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1855 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1856 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1857 if ((trb_0 & 0x3) == 0x3) { 1858 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1859 } 1860 } 1861 1862 switch (trbcode) { 1863 case XHCI_TRB_ERROR_SHORT_PKT: 1864 case XHCI_TRB_ERROR_SUCCESS: 1865 xfer->ux_actlen = 1866 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1867 err = USBD_NORMAL_COMPLETION; 1868 break; 1869 case XHCI_TRB_ERROR_STALL: 1870 case XHCI_TRB_ERROR_BABBLE: 1871 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1872 xr->is_halted = true; 1873 err = USBD_STALLED; 1874 /* 1875 * Stalled endpoints can be recoverd by issuing 1876 * command TRB TYPE_RESET_EP on xHCI instead of 1877 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1878 * on the endpoint. However, this function may be 1879 * called from softint context (e.g. from umass), 1880 * in that case driver gets KASSERT in cv_timedwait 1881 * in xhci_do_command. 1882 * To avoid this, this runs reset_endpoint and 1883 * usb_transfer_complete in usb task thread 1884 * asynchronously (and then umass issues clear 1885 * UF_ENDPOINT_HALT). 1886 */ 1887 xfer->ux_status = err; 1888 xhci_clear_endpoint_stall_async(xfer); 1889 return; 1890 default: 1891 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1892 err = USBD_IOERROR; 1893 break; 1894 } 1895 xfer->ux_status = err; 1896 1897 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1898 if ((trb_0 & 0x3) == 0x0) { 1899 callout_stop(&xfer->ux_callout); 1900 usb_transfer_complete(xfer); 1901 } 1902 } else { 1903 callout_stop(&xfer->ux_callout); 1904 usb_transfer_complete(xfer); 1905 } 1906 } 1907 1908 /* Process Command complete events */ 1909 static void 1910 xhci_event_cmd(struct xhci_softc * const sc, 1911 const struct xhci_trb * const trb) 1912 { 1913 uint64_t trb_0; 1914 uint32_t trb_2, trb_3; 1915 1916 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1917 1918 trb_0 = le64toh(trb->trb_0); 1919 trb_2 = le32toh(trb->trb_2); 1920 trb_3 = le32toh(trb->trb_3); 1921 1922 if (trb_0 == sc->sc_command_addr) { 1923 sc->sc_result_trb.trb_0 = trb_0; 1924 sc->sc_result_trb.trb_2 = trb_2; 1925 sc->sc_result_trb.trb_3 = trb_3; 1926 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1927 XHCI_TRB_ERROR_SUCCESS) { 1928 DPRINTFN(1, "command completion " 1929 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1930 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1931 } 1932 cv_signal(&sc->sc_command_cv); 1933 } else { 1934 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 1935 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1936 trb_2, trb_3); 1937 } 1938 } 1939 1940 /* 1941 * Process events. 1942 * called from xhci_softintr 1943 */ 1944 static void 1945 xhci_handle_event(struct xhci_softc * const sc, 1946 const struct xhci_trb * const trb) 1947 { 1948 uint64_t trb_0; 1949 uint32_t trb_2, trb_3; 1950 1951 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1952 1953 trb_0 = le64toh(trb->trb_0); 1954 trb_2 = le32toh(trb->trb_2); 1955 trb_3 = le32toh(trb->trb_3); 1956 1957 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1958 trb, trb_0, trb_2, trb_3); 1959 1960 /* 1961 * 4.11.3.1, 6.4.2.1 1962 * TRB Pointer is invalid for these completion codes. 1963 */ 1964 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 1965 case XHCI_TRB_ERROR_RING_UNDERRUN: 1966 case XHCI_TRB_ERROR_RING_OVERRUN: 1967 case XHCI_TRB_ERROR_VF_RING_FULL: 1968 return; 1969 default: 1970 if (trb_0 == 0) { 1971 return; 1972 } 1973 break; 1974 } 1975 1976 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 1977 case XHCI_TRB_EVENT_TRANSFER: 1978 xhci_event_transfer(sc, trb); 1979 break; 1980 case XHCI_TRB_EVENT_CMD_COMPLETE: 1981 xhci_event_cmd(sc, trb); 1982 break; 1983 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1984 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1985 break; 1986 default: 1987 break; 1988 } 1989 } 1990 1991 static void 1992 xhci_softintr(void *v) 1993 { 1994 struct usbd_bus * const bus = v; 1995 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1996 struct xhci_ring * const er = &sc->sc_er; 1997 struct xhci_trb *trb; 1998 int i, j, k; 1999 2000 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2001 2002 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2003 2004 i = er->xr_ep; 2005 j = er->xr_cs; 2006 2007 DPRINTFN(16, "xr_ep %d xr_cs %d", i, j, 0, 0); 2008 2009 while (1) { 2010 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2011 BUS_DMASYNC_POSTREAD); 2012 trb = &er->xr_trb[i]; 2013 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2014 2015 if (j != k) 2016 break; 2017 2018 xhci_handle_event(sc, trb); 2019 2020 i++; 2021 if (i == XHCI_EVENT_RING_TRBS) { 2022 i = 0; 2023 j ^= 1; 2024 } 2025 } 2026 2027 er->xr_ep = i; 2028 er->xr_cs = j; 2029 2030 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2031 XHCI_ERDP_LO_BUSY); 2032 2033 DPRINTFN(16, "ends", 0, 0, 0, 0); 2034 2035 return; 2036 } 2037 2038 static void 2039 xhci_poll(struct usbd_bus *bus) 2040 { 2041 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2042 2043 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2044 2045 mutex_spin_enter(&sc->sc_intr_lock); 2046 xhci_intr1(sc); 2047 mutex_spin_exit(&sc->sc_intr_lock); 2048 2049 return; 2050 } 2051 2052 static struct usbd_xfer * 2053 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2054 { 2055 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2056 struct usbd_xfer *xfer; 2057 2058 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2059 2060 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 2061 if (xfer != NULL) { 2062 memset(xfer, 0, sizeof(struct xhci_xfer)); 2063 #ifdef DIAGNOSTIC 2064 xfer->ux_state = XFER_BUSY; 2065 #endif 2066 } 2067 2068 return xfer; 2069 } 2070 2071 static void 2072 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2073 { 2074 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2075 2076 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2077 2078 #ifdef DIAGNOSTIC 2079 if (xfer->ux_state != XFER_BUSY) { 2080 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 2081 xfer, xfer->ux_state, 0, 0); 2082 } 2083 xfer->ux_state = XFER_FREE; 2084 #endif 2085 pool_cache_put(sc->sc_xferpool, xfer); 2086 } 2087 2088 static void 2089 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2090 { 2091 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2092 2093 *lock = &sc->sc_lock; 2094 } 2095 2096 extern uint32_t usb_cookie_no; 2097 2098 /* 2099 * Called if uhub_explore finds a new device (via usbd_new_device). 2100 * Allocate and construct dev structure of default endpoint (ep0). 2101 * Determine initial MaxPacketSize (mps) by speed. 2102 * Determine route string and roothub port for slot of dev. 2103 * Allocate pipe of ep0. 2104 * Enable and initialize slot and Set Address. 2105 * Read device descriptor. 2106 * Register this device. 2107 */ 2108 static usbd_status 2109 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2110 int speed, int port, struct usbd_port *up) 2111 { 2112 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2113 struct usbd_device *dev; 2114 usbd_status err; 2115 usb_device_descriptor_t *dd; 2116 struct usbd_device *hub; 2117 struct usbd_device *adev; 2118 int rhport = 0; 2119 struct xhci_slot *xs; 2120 uint32_t *cp; 2121 uint32_t route = 0; 2122 uint8_t slot = 0; 2123 uint8_t addr; 2124 2125 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2126 DPRINTFN(4, "port=%d depth=%d speed=%d upport %d", 2127 port, depth, speed, up->up_portno); 2128 2129 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2130 if (dev == NULL) 2131 return USBD_NOMEM; 2132 2133 dev->ud_bus = bus; 2134 2135 /* Set up default endpoint handle. */ 2136 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2137 2138 /* Set up default endpoint descriptor. */ 2139 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2140 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2141 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2142 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2143 /* 4.3, 4.8.2.1 */ 2144 if (USB_IS_SS(speed)) { 2145 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2146 } else 2147 switch (speed) { 2148 case USB_SPEED_FULL: 2149 /* XXX using 64 as initial mps of ep0 in FS */ 2150 case USB_SPEED_HIGH: 2151 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2152 break; 2153 case USB_SPEED_LOW: 2154 default: 2155 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2156 break; 2157 } 2158 dev->ud_ep0desc.bInterval = 0; 2159 2160 /* doesn't matter, just don't let it uninitialized */ 2161 dev->ud_ep0.ue_toggle = 0; 2162 2163 DPRINTFN(4, "up %p portno %d", up, up->up_portno, 0, 0); 2164 2165 dev->ud_quirks = &usbd_no_quirk; 2166 dev->ud_addr = 0; 2167 dev->ud_ddesc.bMaxPacketSize = 0; 2168 dev->ud_depth = depth; 2169 dev->ud_powersrc = up; 2170 dev->ud_myhub = up->up_parent; 2171 2172 up->up_dev = dev; 2173 2174 /* Locate root hub port */ 2175 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2176 uint32_t dep; 2177 2178 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2179 hub, hub->ud_depth, hub->ud_powersrc, 2180 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2181 2182 if (hub->ud_powersrc == NULL) 2183 break; 2184 dep = hub->ud_depth; 2185 if (dep == 0) 2186 break; 2187 rhport = hub->ud_powersrc->up_portno; 2188 if (dep > USB_HUB_MAX_DEPTH) 2189 continue; 2190 2191 route |= 2192 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2193 << ((dep - 1) * 4); 2194 } 2195 route = route >> 4; 2196 DPRINTFN(4, "rhport %d Route %05x hub %p", rhport, route, hub, 0); 2197 2198 /* Locate port on upstream high speed hub */ 2199 for (adev = dev, hub = up->up_parent; 2200 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2201 adev = hub, hub = hub->ud_myhub) 2202 ; 2203 if (hub) { 2204 int p; 2205 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2206 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2207 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2208 goto found; 2209 } 2210 } 2211 panic("xhci_new_device: cannot find HS port"); 2212 found: 2213 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2214 } else { 2215 dev->ud_myhsport = NULL; 2216 } 2217 2218 dev->ud_speed = speed; 2219 dev->ud_langid = USBD_NOLANG; 2220 dev->ud_cookie.cookie = ++usb_cookie_no; 2221 2222 /* Establish the default pipe. */ 2223 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2224 &dev->ud_pipe0); 2225 if (err) { 2226 goto bad; 2227 } 2228 2229 dd = &dev->ud_ddesc; 2230 2231 if ((depth == 0) && (port == 0)) { 2232 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2233 bus->ub_devices[dev->ud_addr] = dev; 2234 err = usbd_get_initial_ddesc(dev, dd); 2235 if (err) 2236 goto bad; 2237 err = usbd_reload_device_desc(dev); 2238 if (err) 2239 goto bad; 2240 } else { 2241 err = xhci_enable_slot(sc, &slot); 2242 if (err) 2243 goto bad; 2244 xs = &sc->sc_slots[slot]; 2245 dev->ud_hcpriv = xs; 2246 err = xhci_init_slot(dev, slot, route, rhport); 2247 if (err) { 2248 dev->ud_hcpriv = NULL; 2249 /* 2250 * We have to disable_slot here because 2251 * xs->xs_idx == 0 when xhci_init_slot fails, 2252 * in that case usbd_remove_dev won't work. 2253 */ 2254 mutex_enter(&sc->sc_lock); 2255 xhci_disable_slot(sc, slot); 2256 mutex_exit(&sc->sc_lock); 2257 goto bad; 2258 } 2259 2260 /* Allow device time to set new address */ 2261 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2262 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2263 //hexdump("slot context", cp, sc->sc_ctxsz); 2264 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2265 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2266 /* XXX ensure we know when the hardware does something 2267 we can't yet cope with */ 2268 KASSERT(addr >= 1 && addr <= 127); 2269 dev->ud_addr = addr; 2270 /* XXX dev->ud_addr not necessarily unique on bus */ 2271 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2272 bus->ub_devices[dev->ud_addr] = dev; 2273 2274 err = usbd_get_initial_ddesc(dev, dd); 2275 if (err) 2276 goto bad; 2277 /* 4.8.2.1 */ 2278 if (USB_IS_SS(speed)) { 2279 if (dd->bMaxPacketSize != 9) { 2280 printf("%s: invalid mps 2^%u for SS ep0," 2281 " using 512\n", 2282 device_xname(sc->sc_dev), 2283 dd->bMaxPacketSize); 2284 dd->bMaxPacketSize = 9; 2285 } 2286 USETW(dev->ud_ep0desc.wMaxPacketSize, 2287 (1 << dd->bMaxPacketSize)); 2288 } else 2289 USETW(dev->ud_ep0desc.wMaxPacketSize, 2290 dd->bMaxPacketSize); 2291 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2292 xhci_update_ep0_mps(sc, xs, 2293 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2294 err = usbd_reload_device_desc(dev); 2295 if (err) 2296 goto bad; 2297 2298 #if 0 2299 /* Re-establish the default pipe with the new MPS. */ 2300 /* In xhci this is done by xhci_update_ep0_mps. */ 2301 usbd_kill_pipe(dev->ud_pipe0); 2302 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2303 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2304 #endif 2305 } 2306 2307 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2308 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2309 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2310 dd->bDeviceClass, dd->bDeviceSubClass, 2311 dd->bDeviceProtocol, 0); 2312 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2313 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2314 dev->ud_speed); 2315 2316 usbd_get_device_strings(dev); 2317 2318 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2319 2320 if ((depth == 0) && (port == 0)) { 2321 usbd_attach_roothub(parent, dev); 2322 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2323 return USBD_NORMAL_COMPLETION; 2324 } 2325 2326 2327 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2328 bad: 2329 if (err != USBD_NORMAL_COMPLETION) { 2330 usbd_remove_device(dev, up); 2331 } 2332 2333 return err; 2334 } 2335 2336 static usbd_status 2337 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2338 size_t ntrb, size_t align) 2339 { 2340 usbd_status err; 2341 size_t size = ntrb * XHCI_TRB_SIZE; 2342 2343 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2344 2345 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2346 if (err) 2347 return err; 2348 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2349 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2350 xr->xr_trb = xhci_ring_trbv(xr, 0); 2351 xr->xr_ntrb = ntrb; 2352 xr->xr_ep = 0; 2353 xr->xr_cs = 1; 2354 memset(xr->xr_trb, 0, size); 2355 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 2356 xr->is_halted = false; 2357 2358 return USBD_NORMAL_COMPLETION; 2359 } 2360 2361 static void 2362 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2363 { 2364 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2365 mutex_destroy(&xr->xr_lock); 2366 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2367 } 2368 2369 static void 2370 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2371 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2372 { 2373 size_t i; 2374 u_int ri; 2375 u_int cs; 2376 uint64_t parameter; 2377 uint32_t status; 2378 uint32_t control; 2379 2380 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2381 2382 KASSERT(ntrbs <= XHCI_XFER_NTRB); 2383 for (i = 0; i < ntrbs; i++) { 2384 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2385 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2386 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2387 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2388 XHCI_TRB_TYPE_LINK); 2389 } 2390 2391 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2392 2393 ri = xr->xr_ep; 2394 cs = xr->xr_cs; 2395 2396 /* 2397 * Although the xhci hardware can do scatter/gather dma from 2398 * arbitrary sized buffers, there is a non-obvious restriction 2399 * that a LINK trb is only allowed at the end of a burst of 2400 * transfers - which might be 16kB. 2401 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2402 * The simple solution is not to allow a LINK trb in the middle 2403 * of anything - as here. 2404 * XXX: (dsl) There are xhci controllers out there (eg some made by 2405 * ASMedia) that seem to lock up if they process a LINK trb but 2406 * cannot process the linked-to trb yet. 2407 * The code should write the 'cycle' bit on the link trb AFTER 2408 * adding the other trb. 2409 */ 2410 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2411 parameter = xhci_ring_trbp(xr, 0); 2412 status = 0; 2413 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2414 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2415 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2416 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2417 BUS_DMASYNC_PREWRITE); 2418 xr->xr_cookies[ri] = NULL; 2419 xr->xr_ep = 0; 2420 xr->xr_cs ^= 1; 2421 ri = xr->xr_ep; 2422 cs = xr->xr_cs; 2423 } 2424 2425 ri++; 2426 2427 /* Write any subsequent TRB first */ 2428 for (i = 1; i < ntrbs; i++) { 2429 parameter = trbs[i].trb_0; 2430 status = trbs[i].trb_2; 2431 control = trbs[i].trb_3; 2432 2433 if (cs) { 2434 control |= XHCI_TRB_3_CYCLE_BIT; 2435 } else { 2436 control &= ~XHCI_TRB_3_CYCLE_BIT; 2437 } 2438 2439 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2440 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2441 BUS_DMASYNC_PREWRITE); 2442 xr->xr_cookies[ri] = cookie; 2443 ri++; 2444 } 2445 2446 /* Write the first TRB last */ 2447 i = 0; 2448 parameter = trbs[i].trb_0; 2449 status = trbs[i].trb_2; 2450 control = trbs[i].trb_3; 2451 2452 if (xr->xr_cs) { 2453 control |= XHCI_TRB_3_CYCLE_BIT; 2454 } else { 2455 control &= ~XHCI_TRB_3_CYCLE_BIT; 2456 } 2457 2458 xhci_trb_put(&xr->xr_trb[xr->xr_ep], parameter, status, control); 2459 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2460 BUS_DMASYNC_PREWRITE); 2461 xr->xr_cookies[xr->xr_ep] = cookie; 2462 2463 xr->xr_ep = ri; 2464 xr->xr_cs = cs; 2465 2466 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2467 } 2468 2469 /* 2470 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2471 * Command completion is notified by cv_signal from xhci_handle_event 2472 * (called from interrupt from xHCI), or timed-out. 2473 * Command validation is performed in xhci_handle_event by checking if 2474 * trb_0 in CMD_COMPLETE TRB and sc->sc_command_addr are identical. 2475 */ 2476 static usbd_status 2477 xhci_do_command1(struct xhci_softc * const sc, struct xhci_trb * const trb, 2478 int timeout, int locked) 2479 { 2480 struct xhci_ring * const cr = &sc->sc_cr; 2481 usbd_status err; 2482 2483 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2484 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2485 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2486 2487 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2488 2489 if (!locked) 2490 mutex_enter(&sc->sc_lock); 2491 2492 /* XXX KASSERT may fire when cv_timedwait unlocks sc_lock */ 2493 KASSERT(sc->sc_command_addr == 0); 2494 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2495 2496 mutex_enter(&cr->xr_lock); 2497 xhci_ring_put(sc, cr, NULL, trb, 1); 2498 mutex_exit(&cr->xr_lock); 2499 2500 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2501 2502 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2503 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2504 err = USBD_TIMEOUT; 2505 goto timedout; 2506 } 2507 2508 trb->trb_0 = sc->sc_result_trb.trb_0; 2509 trb->trb_2 = sc->sc_result_trb.trb_2; 2510 trb->trb_3 = sc->sc_result_trb.trb_3; 2511 2512 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2513 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2514 2515 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2516 case XHCI_TRB_ERROR_SUCCESS: 2517 err = USBD_NORMAL_COMPLETION; 2518 break; 2519 default: 2520 case 192 ... 223: 2521 err = USBD_IOERROR; 2522 break; 2523 case 224 ... 255: 2524 err = USBD_NORMAL_COMPLETION; 2525 break; 2526 } 2527 2528 timedout: 2529 sc->sc_command_addr = 0; 2530 if (!locked) 2531 mutex_exit(&sc->sc_lock); 2532 return err; 2533 } 2534 2535 static usbd_status 2536 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2537 int timeout) 2538 { 2539 return xhci_do_command1(sc, trb, timeout, 0); 2540 } 2541 2542 /* 2543 * This allows xhci_do_command with already sc_lock held. 2544 * This is needed as USB stack calls close methods with sc_lock_held. 2545 * (see usbdivar.h) 2546 */ 2547 static usbd_status 2548 xhci_do_command_locked(struct xhci_softc * const sc, 2549 struct xhci_trb * const trb, int timeout) 2550 { 2551 return xhci_do_command1(sc, trb, timeout, 1); 2552 } 2553 2554 static usbd_status 2555 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2556 { 2557 struct xhci_trb trb; 2558 usbd_status err; 2559 2560 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2561 2562 trb.trb_0 = 0; 2563 trb.trb_2 = 0; 2564 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2565 2566 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2567 if (err != USBD_NORMAL_COMPLETION) { 2568 return err; 2569 } 2570 2571 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2572 2573 return err; 2574 } 2575 2576 /* 2577 * Deallocate DMA buffer and ring buffer, and disable_slot. 2578 * Should be called with sc_lock held. 2579 */ 2580 static usbd_status 2581 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2582 { 2583 struct xhci_trb trb; 2584 struct xhci_slot *xs; 2585 2586 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2587 2588 if (sc->sc_dying) 2589 return USBD_IOERROR; 2590 2591 xs = &sc->sc_slots[slot]; 2592 if (xs->xs_idx != 0) { 2593 for (int i = XHCI_DCI_SLOT + 1; i < 32; i++) { 2594 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2595 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2596 } 2597 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2598 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2599 } 2600 2601 trb.trb_0 = 0; 2602 trb.trb_2 = 0; 2603 trb.trb_3 = htole32( 2604 XHCI_TRB_3_SLOT_SET(slot) | 2605 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2606 2607 return xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2608 } 2609 2610 /* 2611 * Change slot state. 2612 * bsr=0: ENABLED -> ADDRESSED 2613 * bsr=1: ENABLED -> DEFAULT 2614 * see xHCI 1.1 4.5.3, 3.3.4 2615 */ 2616 static usbd_status 2617 xhci_address_device(struct xhci_softc * const sc, 2618 uint64_t icp, uint8_t slot_id, bool bsr) 2619 { 2620 struct xhci_trb trb; 2621 usbd_status err; 2622 2623 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2624 2625 trb.trb_0 = icp; 2626 trb.trb_2 = 0; 2627 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2628 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2629 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2630 2631 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2632 2633 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2634 err = USBD_NO_ADDR; 2635 2636 return err; 2637 } 2638 2639 static usbd_status 2640 xhci_update_ep0_mps(struct xhci_softc * const sc, 2641 struct xhci_slot * const xs, u_int mps) 2642 { 2643 struct xhci_trb trb; 2644 usbd_status err; 2645 uint32_t * cp; 2646 2647 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2648 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2649 2650 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2651 cp[0] = htole32(0); 2652 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2653 2654 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2655 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2656 2657 /* sync input contexts before they are read from memory */ 2658 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2659 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2660 sc->sc_ctxsz * 4); 2661 2662 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2663 trb.trb_2 = 0; 2664 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2665 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2666 2667 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2668 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2669 return err; 2670 } 2671 2672 static void 2673 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2674 { 2675 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2676 2677 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2678 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2679 &dcbaa[si], dcba, si, 0); 2680 2681 dcbaa[si] = htole64(dcba); 2682 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2683 BUS_DMASYNC_PREWRITE); 2684 } 2685 2686 /* 2687 * Allocate DMA buffer and ring buffer for specified slot 2688 * and set Device Context Base Address 2689 * and issue Set Address device command. 2690 */ 2691 static usbd_status 2692 xhci_init_slot(struct usbd_device *dev, uint32_t slot, int route, int rhport) 2693 { 2694 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2695 struct xhci_slot *xs; 2696 usbd_status err; 2697 u_int dci; 2698 uint32_t *cp; 2699 uint32_t mps = UGETW(dev->ud_ep0desc.wMaxPacketSize); 2700 2701 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2702 DPRINTFN(4, "slot %u speed %d rhport %d route %05x", 2703 slot, dev->ud_speed, route, rhport); 2704 2705 xs = &sc->sc_slots[slot]; 2706 2707 /* allocate contexts */ 2708 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2709 &xs->xs_dc_dma); 2710 if (err) 2711 return err; 2712 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2713 2714 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2715 &xs->xs_ic_dma); 2716 if (err) 2717 goto bad1; 2718 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2719 2720 for (dci = 0; dci < 32; dci++) { 2721 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2722 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2723 if (dci == XHCI_DCI_SLOT) 2724 continue; 2725 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2726 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2727 if (err) { 2728 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2729 goto bad2; 2730 } 2731 } 2732 2733 /* set up initial input control context */ 2734 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2735 cp[0] = htole32(0); 2736 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 2737 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2738 2739 /* set up input slot context */ 2740 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2741 xhci_setup_sctx(dev, cp); 2742 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(1)); 2743 cp[0] |= htole32(XHCI_SCTX_0_ROUTE_SET(route)); 2744 cp[1] |= htole32(XHCI_SCTX_1_RH_PORT_SET(rhport)); 2745 2746 /* set up input EP0 context */ 2747 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2748 cp[0] = htole32(0); 2749 cp[1] = htole32( 2750 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 2751 XHCI_EPCTX_1_EPTYPE_SET(4) | 2752 XHCI_EPCTX_1_CERR_SET(3) 2753 ); 2754 /* can't use xhci_ep_get_dci() yet? */ 2755 *(uint64_t *)(&cp[2]) = htole64( 2756 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 2757 XHCI_EPCTX_2_DCS_SET(1)); 2758 cp[4] = htole32( 2759 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 2760 ); 2761 2762 /* sync input contexts before they are read from memory */ 2763 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2764 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2765 sc->sc_ctxsz * 3); 2766 2767 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2768 2769 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 2770 false); 2771 2772 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2773 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2774 sc->sc_ctxsz * 2); 2775 2776 bad2: 2777 if (err == USBD_NORMAL_COMPLETION) { 2778 xs->xs_idx = slot; 2779 } else { 2780 for (int i = 1; i < dci; i++) { 2781 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2782 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2783 } 2784 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2785 bad1: 2786 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2787 xs->xs_idx = 0; 2788 } 2789 2790 return err; 2791 } 2792 2793 /* ----- */ 2794 2795 static void 2796 xhci_noop(struct usbd_pipe *pipe) 2797 { 2798 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2799 } 2800 2801 /* 2802 * Process root hub request. 2803 */ 2804 static int 2805 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2806 void *buf, int buflen) 2807 { 2808 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2809 usb_port_status_t ps; 2810 int l, totlen = 0; 2811 uint16_t len, value, index; 2812 int port, i; 2813 uint32_t v; 2814 2815 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2816 2817 if (sc->sc_dying) 2818 return -1; 2819 2820 len = UGETW(req->wLength); 2821 value = UGETW(req->wValue); 2822 index = UGETW(req->wIndex); 2823 2824 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 2825 req->bmRequestType | (req->bRequest << 8), value, index, len); 2826 2827 #define C(x,y) ((x) | ((y) << 8)) 2828 switch (C(req->bRequest, req->bmRequestType)) { 2829 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2830 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 2831 if (len == 0) 2832 break; 2833 switch (value) { 2834 case C(0, UDESC_DEVICE): { 2835 usb_device_descriptor_t devd; 2836 totlen = min(buflen, sizeof(devd)); 2837 memcpy(&devd, buf, totlen); 2838 USETW(devd.idVendor, sc->sc_id_vendor); 2839 memcpy(buf, &devd, totlen); 2840 break; 2841 } 2842 #define sd ((usb_string_descriptor_t *)buf) 2843 case C(1, UDESC_STRING): 2844 /* Vendor */ 2845 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2846 break; 2847 case C(2, UDESC_STRING): 2848 /* Product */ 2849 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 2850 break; 2851 #undef sd 2852 default: 2853 /* default from usbroothub */ 2854 return buflen; 2855 } 2856 break; 2857 2858 /* Hub requests */ 2859 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2860 break; 2861 /* Clear Port Feature request */ 2862 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2863 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2864 index, value, 0, 0); 2865 if (index < 1 || index > sc->sc_maxports) { 2866 return -1; 2867 } 2868 port = XHCI_PORTSC(index); 2869 v = xhci_op_read_4(sc, port); 2870 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2871 v &= ~XHCI_PS_CLEAR; 2872 switch (value) { 2873 case UHF_PORT_ENABLE: 2874 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 2875 break; 2876 case UHF_PORT_SUSPEND: 2877 return -1; 2878 case UHF_PORT_POWER: 2879 break; 2880 case UHF_PORT_TEST: 2881 case UHF_PORT_INDICATOR: 2882 return -1; 2883 case UHF_C_PORT_CONNECTION: 2884 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2885 break; 2886 case UHF_C_PORT_ENABLE: 2887 case UHF_C_PORT_SUSPEND: 2888 case UHF_C_PORT_OVER_CURRENT: 2889 return -1; 2890 case UHF_C_BH_PORT_RESET: 2891 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 2892 break; 2893 case UHF_C_PORT_RESET: 2894 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2895 break; 2896 case UHF_C_PORT_LINK_STATE: 2897 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 2898 break; 2899 case UHF_C_PORT_CONFIG_ERROR: 2900 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 2901 break; 2902 default: 2903 return -1; 2904 } 2905 break; 2906 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2907 if (len == 0) 2908 break; 2909 if ((value & 0xff) != 0) { 2910 return -1; 2911 } 2912 usb_hub_descriptor_t hubd; 2913 2914 totlen = min(buflen, sizeof(hubd)); 2915 memcpy(&hubd, buf, totlen); 2916 hubd.bNbrPorts = sc->sc_maxports; 2917 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2918 hubd.bPwrOn2PwrGood = 200; 2919 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 2920 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2921 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2922 totlen = min(totlen, hubd.bDescLength); 2923 memcpy(buf, &hubd, totlen); 2924 break; 2925 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2926 if (len != 4) { 2927 return -1; 2928 } 2929 memset(buf, 0, len); /* ? XXX */ 2930 totlen = len; 2931 break; 2932 /* Get Port Status request */ 2933 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2934 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2935 if (index < 1 || index > sc->sc_maxports) { 2936 return -1; 2937 } 2938 if (len != 4) { 2939 return -1; 2940 } 2941 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 2942 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 2943 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 2944 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2945 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2946 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2947 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 2948 if (v & XHCI_PS_PR) i |= UPS_RESET; 2949 if (v & XHCI_PS_PP) { 2950 if (i & UPS_OTHER_SPEED) 2951 i |= UPS_PORT_POWER_SS; 2952 else 2953 i |= UPS_PORT_POWER; 2954 } 2955 if (i & UPS_OTHER_SPEED) 2956 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 2957 if (sc->sc_vendor_port_status) 2958 i = sc->sc_vendor_port_status(sc, v, i); 2959 USETW(ps.wPortStatus, i); 2960 i = 0; 2961 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2962 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2963 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2964 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2965 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 2966 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 2967 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 2968 USETW(ps.wPortChange, i); 2969 totlen = min(len, sizeof(ps)); 2970 memcpy(buf, &ps, totlen); 2971 break; 2972 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2973 return -1; 2974 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 2975 break; 2976 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2977 break; 2978 /* Set Port Feature request */ 2979 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 2980 int optval = (index >> 8) & 0xff; 2981 index &= 0xff; 2982 if (index < 1 || index > sc->sc_maxports) { 2983 return -1; 2984 } 2985 port = XHCI_PORTSC(index); 2986 v = xhci_op_read_4(sc, port); 2987 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2988 uint32_t v0 = v; 2989 v &= ~XHCI_PS_CLEAR; 2990 switch (value) { 2991 case UHF_PORT_ENABLE: 2992 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 2993 break; 2994 case UHF_PORT_SUSPEND: 2995 /* XXX suspend */ 2996 break; 2997 case UHF_PORT_RESET: 2998 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 2999 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3000 /* Wait for reset to complete. */ 3001 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3002 if (sc->sc_dying) { 3003 return -1; 3004 } 3005 v = xhci_op_read_4(sc, port); 3006 if (v & XHCI_PS_PR) { 3007 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3008 usb_delay_ms(&sc->sc_bus, 10); 3009 /* XXX */ 3010 } 3011 break; 3012 case UHF_PORT_POWER: 3013 /* XXX power control */ 3014 break; 3015 /* XXX more */ 3016 case UHF_C_PORT_RESET: 3017 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3018 break; 3019 case UHF_PORT_U1_TIMEOUT: 3020 if (XHCI_PS_SPEED_GET(v0) != XHCI_PS_SPEED_SS) { 3021 return -1; 3022 } 3023 port = XHCI_PORTPMSC(index); 3024 v = xhci_op_read_4(sc, port); 3025 v &= ~XHCI_PM3_U1TO_SET(0xff); 3026 v |= XHCI_PM3_U1TO_SET(optval); 3027 xhci_op_write_4(sc, port, v); 3028 break; 3029 case UHF_PORT_U2_TIMEOUT: 3030 if (XHCI_PS_SPEED_GET(v0) != XHCI_PS_SPEED_SS) { 3031 return -1; 3032 } 3033 port = XHCI_PORTPMSC(index); 3034 v = xhci_op_read_4(sc, port); 3035 v &= ~XHCI_PM3_U2TO_SET(0xff); 3036 v |= XHCI_PM3_U2TO_SET(optval); 3037 xhci_op_write_4(sc, port, v); 3038 break; 3039 default: 3040 return -1; 3041 } 3042 } 3043 break; 3044 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3045 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3046 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3047 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3048 break; 3049 default: 3050 /* default from usbroothub */ 3051 return buflen; 3052 } 3053 3054 return totlen; 3055 } 3056 3057 /* root hub interrupt */ 3058 3059 static usbd_status 3060 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3061 { 3062 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3063 usbd_status err; 3064 3065 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3066 3067 /* Insert last in queue. */ 3068 mutex_enter(&sc->sc_lock); 3069 err = usb_insert_transfer(xfer); 3070 mutex_exit(&sc->sc_lock); 3071 if (err) 3072 return err; 3073 3074 /* Pipe isn't running, start first */ 3075 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3076 } 3077 3078 /* Wait for roothub port status/change */ 3079 static usbd_status 3080 xhci_root_intr_start(struct usbd_xfer *xfer) 3081 { 3082 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3083 3084 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3085 3086 if (sc->sc_dying) 3087 return USBD_IOERROR; 3088 3089 mutex_enter(&sc->sc_lock); 3090 sc->sc_intrxfer = xfer; 3091 mutex_exit(&sc->sc_lock); 3092 3093 return USBD_IN_PROGRESS; 3094 } 3095 3096 static void 3097 xhci_root_intr_abort(struct usbd_xfer *xfer) 3098 { 3099 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3100 3101 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3102 3103 KASSERT(mutex_owned(&sc->sc_lock)); 3104 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3105 3106 sc->sc_intrxfer = NULL; 3107 3108 xfer->ux_status = USBD_CANCELLED; 3109 usb_transfer_complete(xfer); 3110 } 3111 3112 static void 3113 xhci_root_intr_close(struct usbd_pipe *pipe) 3114 { 3115 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3116 3117 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3118 3119 KASSERT(mutex_owned(&sc->sc_lock)); 3120 3121 sc->sc_intrxfer = NULL; 3122 } 3123 3124 static void 3125 xhci_root_intr_done(struct usbd_xfer *xfer) 3126 { 3127 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3128 3129 xfer->ux_hcpriv = NULL; 3130 } 3131 3132 /* -------------- */ 3133 /* device control */ 3134 3135 static usbd_status 3136 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3137 { 3138 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3139 usbd_status err; 3140 3141 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3142 3143 /* Insert last in queue. */ 3144 mutex_enter(&sc->sc_lock); 3145 err = usb_insert_transfer(xfer); 3146 mutex_exit(&sc->sc_lock); 3147 if (err) 3148 return err; 3149 3150 /* Pipe isn't running, start first */ 3151 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3152 } 3153 3154 static usbd_status 3155 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3156 { 3157 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3158 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3159 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3160 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3161 struct xhci_xfer * const xx = (void *)xfer; 3162 usb_device_request_t * const req = &xfer->ux_request; 3163 const int isread = usbd_xfer_isread(xfer); 3164 const uint32_t len = UGETW(req->wLength); 3165 usb_dma_t * const dma = &xfer->ux_dmabuf; 3166 uint64_t parameter; 3167 uint32_t status; 3168 uint32_t control; 3169 u_int i; 3170 3171 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3172 DPRINTFN(12, "req: %04x %04x %04x %04x", 3173 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3174 UGETW(req->wIndex), UGETW(req->wLength)); 3175 3176 #if 0 /* event handler does this */ 3177 /* XXX */ 3178 if (tr->is_halted) { 3179 DPRINTFN(1, "ctrl xfer %p halted: slot %u dci %u", 3180 xfer, xs->xs_idx, dci, 0); 3181 xhci_reset_endpoint(xfer->ux_pipe); 3182 tr->is_halted = false; 3183 xhci_set_dequeue(xfer->ux_pipe); 3184 } 3185 #endif 3186 3187 /* we rely on the bottom bits for extra info */ 3188 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 3189 3190 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3191 3192 i = 0; 3193 3194 /* setup phase */ 3195 memcpy(¶meter, req, sizeof(*req)); 3196 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3197 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3198 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3199 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3200 XHCI_TRB_3_IDT_BIT; 3201 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3202 3203 if (len != 0) { 3204 /* data phase */ 3205 parameter = DMAADDR(dma, 0); 3206 KASSERT(len <= 0x10000); 3207 status = XHCI_TRB_2_IRQ_SET(0) | 3208 XHCI_TRB_2_TDSZ_SET(1) | 3209 XHCI_TRB_2_BYTES_SET(len); 3210 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3211 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3212 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3213 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3214 3215 parameter = (uintptr_t)xfer | 0x3; 3216 status = XHCI_TRB_2_IRQ_SET(0); 3217 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3218 XHCI_TRB_3_IOC_BIT; 3219 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3220 } 3221 3222 parameter = 0; 3223 status = XHCI_TRB_2_IRQ_SET(0); 3224 /* the status stage has inverted direction */ 3225 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3226 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3227 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3228 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3229 3230 parameter = (uintptr_t)xfer | 0x0; 3231 status = XHCI_TRB_2_IRQ_SET(0); 3232 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3233 XHCI_TRB_3_IOC_BIT; 3234 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3235 3236 mutex_enter(&tr->xr_lock); 3237 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3238 mutex_exit(&tr->xr_lock); 3239 3240 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3241 3242 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3243 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3244 xhci_timeout, xfer); 3245 } 3246 3247 if (sc->sc_bus.ub_usepolling) { 3248 DPRINTFN(1, "polling", 0, 0, 0, 0); 3249 //xhci_waitintr(sc, xfer); 3250 } 3251 3252 return USBD_IN_PROGRESS; 3253 } 3254 3255 static void 3256 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3257 { 3258 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3259 usb_device_request_t *req = &xfer->ux_request; 3260 int len = UGETW(req->wLength); 3261 int rd = req->bmRequestType & UT_READ; 3262 3263 if (len) 3264 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3265 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3266 } 3267 3268 static void 3269 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3270 { 3271 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3272 3273 xhci_abort_xfer(xfer, USBD_CANCELLED); 3274 } 3275 3276 static void 3277 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3278 { 3279 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3280 3281 xhci_close_pipe(pipe); 3282 } 3283 3284 /* ------------------ */ 3285 /* device isochronous */ 3286 3287 /* ----------- */ 3288 /* device bulk */ 3289 3290 static usbd_status 3291 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3292 { 3293 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3294 usbd_status err; 3295 3296 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3297 3298 /* Insert last in queue. */ 3299 mutex_enter(&sc->sc_lock); 3300 err = usb_insert_transfer(xfer); 3301 mutex_exit(&sc->sc_lock); 3302 if (err) 3303 return err; 3304 3305 /* 3306 * Pipe isn't running (otherwise err would be USBD_INPROG), 3307 * so start it first. 3308 */ 3309 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3310 } 3311 3312 static usbd_status 3313 xhci_device_bulk_start(struct usbd_xfer *xfer) 3314 { 3315 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3316 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3317 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3318 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3319 struct xhci_xfer * const xx = (void *)xfer; 3320 const uint32_t len = xfer->ux_length; 3321 usb_dma_t * const dma = &xfer->ux_dmabuf; 3322 uint64_t parameter; 3323 uint32_t status; 3324 uint32_t control; 3325 u_int i = 0; 3326 3327 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3328 3329 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3330 3331 if (sc->sc_dying) 3332 return USBD_IOERROR; 3333 3334 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3335 3336 parameter = DMAADDR(dma, 0); 3337 /* 3338 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3339 * If the user supplied buffer crosses such a boundary then 2 3340 * (or more) TRB should be used. 3341 * If multiple TRB are used the td_size field must be set correctly. 3342 * For v1.0 devices (like ivy bridge) this is the number of usb data 3343 * blocks needed to complete the transfer. 3344 * Setting it to 1 in the last TRB causes an extra zero-length 3345 * data block be sent. 3346 * The earlier documentation differs, I don't know how it behaves. 3347 */ 3348 KASSERT(len <= 0x10000); 3349 status = XHCI_TRB_2_IRQ_SET(0) | 3350 XHCI_TRB_2_TDSZ_SET(1) | 3351 XHCI_TRB_2_BYTES_SET(len); 3352 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3353 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3354 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3355 3356 mutex_enter(&tr->xr_lock); 3357 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3358 mutex_exit(&tr->xr_lock); 3359 3360 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3361 3362 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3363 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3364 xhci_timeout, xfer); 3365 } 3366 3367 if (sc->sc_bus.ub_usepolling) { 3368 DPRINTFN(1, "polling", 0, 0, 0, 0); 3369 //xhci_waitintr(sc, xfer); 3370 } 3371 3372 return USBD_IN_PROGRESS; 3373 } 3374 3375 static void 3376 xhci_device_bulk_done(struct usbd_xfer *xfer) 3377 { 3378 #ifdef USB_DEBUG 3379 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3380 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3381 #endif 3382 const int isread = usbd_xfer_isread(xfer); 3383 3384 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3385 3386 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3387 3388 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3389 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3390 } 3391 3392 static void 3393 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3394 { 3395 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3396 3397 xhci_abort_xfer(xfer, USBD_CANCELLED); 3398 } 3399 3400 static void 3401 xhci_device_bulk_close(struct usbd_pipe *pipe) 3402 { 3403 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3404 3405 xhci_close_pipe(pipe); 3406 } 3407 3408 /* ---------------- */ 3409 /* device interrupt */ 3410 3411 static usbd_status 3412 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3413 { 3414 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3415 usbd_status err; 3416 3417 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3418 3419 /* Insert last in queue. */ 3420 mutex_enter(&sc->sc_lock); 3421 err = usb_insert_transfer(xfer); 3422 mutex_exit(&sc->sc_lock); 3423 if (err) 3424 return err; 3425 3426 /* 3427 * Pipe isn't running (otherwise err would be USBD_INPROG), 3428 * so start it first. 3429 */ 3430 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3431 } 3432 3433 static usbd_status 3434 xhci_device_intr_start(struct usbd_xfer *xfer) 3435 { 3436 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3437 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3438 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3439 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3440 struct xhci_xfer * const xx = (void *)xfer; 3441 const uint32_t len = xfer->ux_length; 3442 usb_dma_t * const dma = &xfer->ux_dmabuf; 3443 uint64_t parameter; 3444 uint32_t status; 3445 uint32_t control; 3446 u_int i = 0; 3447 3448 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3449 3450 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3451 3452 if (sc->sc_dying) 3453 return USBD_IOERROR; 3454 3455 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3456 3457 parameter = DMAADDR(dma, 0); 3458 KASSERT(len <= 0x10000); 3459 status = XHCI_TRB_2_IRQ_SET(0) | 3460 XHCI_TRB_2_TDSZ_SET(1) | 3461 XHCI_TRB_2_BYTES_SET(len); 3462 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3463 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3464 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3465 3466 mutex_enter(&tr->xr_lock); 3467 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3468 mutex_exit(&tr->xr_lock); 3469 3470 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3471 3472 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3473 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3474 xhci_timeout, xfer); 3475 } 3476 3477 if (sc->sc_bus.ub_usepolling) { 3478 DPRINTFN(1, "polling", 0, 0, 0, 0); 3479 //xhci_waitintr(sc, xfer); 3480 } 3481 3482 return USBD_IN_PROGRESS; 3483 } 3484 3485 static void 3486 xhci_device_intr_done(struct usbd_xfer *xfer) 3487 { 3488 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3489 #ifdef USB_DEBUG 3490 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3491 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3492 #endif 3493 const int isread = usbd_xfer_isread(xfer); 3494 3495 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3496 3497 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3498 3499 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3500 3501 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3502 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3503 3504 #if 0 3505 device_printf(sc->sc_dev, ""); 3506 for (size_t i = 0; i < xfer->ux_length; i++) { 3507 printf(" %02x", ((uint8_t const *)xfer->ux_buffer)[i]); 3508 } 3509 printf("\n"); 3510 #endif 3511 3512 } 3513 3514 static void 3515 xhci_device_intr_abort(struct usbd_xfer *xfer) 3516 { 3517 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3518 3519 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3520 3521 KASSERT(mutex_owned(&sc->sc_lock)); 3522 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3523 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3524 xhci_abort_xfer(xfer, USBD_CANCELLED); 3525 } 3526 3527 static void 3528 xhci_device_intr_close(struct usbd_pipe *pipe) 3529 { 3530 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3531 3532 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3533 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3534 3535 xhci_close_pipe(pipe); 3536 } 3537 3538 /* ------------ */ 3539 3540 static void 3541 xhci_timeout(void *addr) 3542 { 3543 struct xhci_xfer * const xx = addr; 3544 struct usbd_xfer * const xfer = &xx->xx_xfer; 3545 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3546 3547 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3548 3549 if (sc->sc_dying) { 3550 return; 3551 } 3552 3553 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 3554 USB_TASKQ_MPSAFE); 3555 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 3556 USB_TASKQ_HC); 3557 } 3558 3559 static void 3560 xhci_timeout_task(void *addr) 3561 { 3562 struct usbd_xfer * const xfer = addr; 3563 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3564 3565 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3566 3567 mutex_enter(&sc->sc_lock); 3568 #if 0 3569 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3570 #else 3571 xfer->ux_status = USBD_TIMEOUT; 3572 usb_transfer_complete(xfer); 3573 #endif 3574 mutex_exit(&sc->sc_lock); 3575 } 3576
Indexes created Wed Oct 01 18:09:54 GMT 2025