xhci.c revision 1.28.2.63
1 /* $NetBSD: xhci.c,v 1.28.2.63 2016/04/10 20:48:56 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 3.1 specification 31 * http://www.usb.org/developers/docs/usb_31_040315.zip 32 * USB rev 2.0 specification 33 * http://www.usb.org/developers/docs/usb20_docs/usb_20_031815.zip 34 * xHCI rev 1.1 specification 35 * http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.28.2.63 2016/04/10 20:48:56 skrll Exp $"); 40 41 #include "opt_usb.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 146 147 static usbd_status xhci_do_command(struct xhci_softc * const, 148 struct xhci_trb * const, int); 149 static usbd_status xhci_do_command1(struct xhci_softc * const, 150 struct xhci_trb * const, int, int); 151 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 152 struct xhci_trb * const, int); 153 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t, int, int); 154 static usbd_status xhci_enable_slot(struct xhci_softc * const, 155 uint8_t * const); 156 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 157 static usbd_status xhci_address_device(struct xhci_softc * const, 158 uint64_t, uint8_t, bool); 159 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 160 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 161 struct xhci_slot * const, u_int); 162 static usbd_status xhci_ring_init(struct xhci_softc * const, 163 struct xhci_ring * const, size_t, size_t); 164 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 165 166 static void xhci_noop(struct usbd_pipe *); 167 168 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 169 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 170 static void xhci_root_intr_abort(struct usbd_xfer *); 171 static void xhci_root_intr_close(struct usbd_pipe *); 172 static void xhci_root_intr_done(struct usbd_xfer *); 173 174 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 175 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 176 static void xhci_device_ctrl_abort(struct usbd_xfer *); 177 static void xhci_device_ctrl_close(struct usbd_pipe *); 178 static void xhci_device_ctrl_done(struct usbd_xfer *); 179 180 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 181 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 182 static void xhci_device_intr_abort(struct usbd_xfer *); 183 static void xhci_device_intr_close(struct usbd_pipe *); 184 static void xhci_device_intr_done(struct usbd_xfer *); 185 186 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 187 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 188 static void xhci_device_bulk_abort(struct usbd_xfer *); 189 static void xhci_device_bulk_close(struct usbd_pipe *); 190 static void xhci_device_bulk_done(struct usbd_xfer *); 191 192 static void xhci_timeout(void *); 193 static void xhci_timeout_task(void *); 194 195 static const struct usbd_bus_methods xhci_bus_methods = { 196 .ubm_open = xhci_open, 197 .ubm_softint = xhci_softintr, 198 .ubm_dopoll = xhci_poll, 199 .ubm_allocx = xhci_allocx, 200 .ubm_freex = xhci_freex, 201 .ubm_getlock = xhci_get_lock, 202 .ubm_newdev = xhci_new_device, 203 .ubm_rhctrl = xhci_roothub_ctrl, 204 }; 205 206 static const struct usbd_pipe_methods xhci_root_intr_methods = { 207 .upm_transfer = xhci_root_intr_transfer, 208 .upm_start = xhci_root_intr_start, 209 .upm_abort = xhci_root_intr_abort, 210 .upm_close = xhci_root_intr_close, 211 .upm_cleartoggle = xhci_noop, 212 .upm_done = xhci_root_intr_done, 213 }; 214 215 216 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 217 .upm_transfer = xhci_device_ctrl_transfer, 218 .upm_start = xhci_device_ctrl_start, 219 .upm_abort = xhci_device_ctrl_abort, 220 .upm_close = xhci_device_ctrl_close, 221 .upm_cleartoggle = xhci_noop, 222 .upm_done = xhci_device_ctrl_done, 223 }; 224 225 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 226 .upm_cleartoggle = xhci_noop, 227 }; 228 229 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 230 .upm_transfer = xhci_device_bulk_transfer, 231 .upm_start = xhci_device_bulk_start, 232 .upm_abort = xhci_device_bulk_abort, 233 .upm_close = xhci_device_bulk_close, 234 .upm_cleartoggle = xhci_noop, 235 .upm_done = xhci_device_bulk_done, 236 }; 237 238 static const struct usbd_pipe_methods xhci_device_intr_methods = { 239 .upm_transfer = xhci_device_intr_transfer, 240 .upm_start = xhci_device_intr_start, 241 .upm_abort = xhci_device_intr_abort, 242 .upm_close = xhci_device_intr_close, 243 .upm_cleartoggle = xhci_noop, 244 .upm_done = xhci_device_intr_done, 245 }; 246 247 static inline uint32_t 248 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 249 { 250 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 251 } 252 253 static inline uint32_t 254 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 255 { 256 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 257 } 258 259 static inline void 260 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 261 uint32_t value) 262 { 263 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 264 } 265 266 #if 0 /* unused */ 267 static inline void 268 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 269 uint32_t value) 270 { 271 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 272 } 273 #endif /* unused */ 274 275 static inline uint32_t 276 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 277 { 278 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 279 } 280 281 static inline uint32_t 282 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 283 { 284 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 285 } 286 287 static inline void 288 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 289 uint32_t value) 290 { 291 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 292 } 293 294 #if 0 /* unused */ 295 static inline uint64_t 296 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 297 { 298 uint64_t value; 299 300 if (sc->sc_ac64) { 301 #ifdef XHCI_USE_BUS_SPACE_8 302 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 303 #else 304 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 305 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 306 offset + 4) << 32; 307 #endif 308 } else { 309 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 310 } 311 312 return value; 313 } 314 #endif /* unused */ 315 316 static inline void 317 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 318 uint64_t value) 319 { 320 if (sc->sc_ac64) { 321 #ifdef XHCI_USE_BUS_SPACE_8 322 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 323 #else 324 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 325 (value >> 0) & 0xffffffff); 326 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 327 (value >> 32) & 0xffffffff); 328 #endif 329 } else { 330 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 331 } 332 } 333 334 static inline uint32_t 335 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 336 { 337 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 338 } 339 340 static inline void 341 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 342 uint32_t value) 343 { 344 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 345 } 346 347 #if 0 /* unused */ 348 static inline uint64_t 349 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 350 { 351 uint64_t value; 352 353 if (sc->sc_ac64) { 354 #ifdef XHCI_USE_BUS_SPACE_8 355 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 356 #else 357 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 358 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 359 offset + 4) << 32; 360 #endif 361 } else { 362 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 363 } 364 365 return value; 366 } 367 #endif /* unused */ 368 369 static inline void 370 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 371 uint64_t value) 372 { 373 if (sc->sc_ac64) { 374 #ifdef XHCI_USE_BUS_SPACE_8 375 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 376 #else 377 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 378 (value >> 0) & 0xffffffff); 379 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 380 (value >> 32) & 0xffffffff); 381 #endif 382 } else { 383 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 384 } 385 } 386 387 #if 0 /* unused */ 388 static inline uint32_t 389 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 390 { 391 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 392 } 393 #endif /* unused */ 394 395 static inline void 396 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 397 uint32_t value) 398 { 399 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 400 } 401 402 /* --- */ 403 404 static inline uint8_t 405 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 406 { 407 u_int eptype = 0; 408 409 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 410 case UE_CONTROL: 411 eptype = 0x0; 412 break; 413 case UE_ISOCHRONOUS: 414 eptype = 0x1; 415 break; 416 case UE_BULK: 417 eptype = 0x2; 418 break; 419 case UE_INTERRUPT: 420 eptype = 0x3; 421 break; 422 } 423 424 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 425 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 426 return eptype | 0x4; 427 else 428 return eptype; 429 } 430 431 static u_int 432 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 433 { 434 /* xHCI 1.0 section 4.5.1 */ 435 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 436 u_int in = 0; 437 438 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 439 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 440 in = 1; 441 442 return epaddr * 2 + in; 443 } 444 445 static inline u_int 446 xhci_dci_to_ici(const u_int i) 447 { 448 return i + 1; 449 } 450 451 static inline void * 452 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 453 const u_int dci) 454 { 455 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 456 } 457 458 #if 0 /* unused */ 459 static inline bus_addr_t 460 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 461 const u_int dci) 462 { 463 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 464 } 465 #endif /* unused */ 466 467 static inline void * 468 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 469 const u_int ici) 470 { 471 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 472 } 473 474 static inline bus_addr_t 475 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 476 const u_int ici) 477 { 478 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 479 } 480 481 static inline struct xhci_trb * 482 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 483 { 484 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 485 } 486 487 static inline bus_addr_t 488 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 489 { 490 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 491 } 492 493 static inline void 494 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 495 uint32_t control) 496 { 497 trb->trb_0 = htole64(parameter); 498 trb->trb_2 = htole32(status); 499 trb->trb_3 = htole32(control); 500 } 501 502 /* --- */ 503 504 void 505 xhci_childdet(device_t self, device_t child) 506 { 507 struct xhci_softc * const sc = device_private(self); 508 509 KASSERT(sc->sc_child == child); 510 if (child == sc->sc_child) 511 sc->sc_child = NULL; 512 } 513 514 int 515 xhci_detach(struct xhci_softc *sc, int flags) 516 { 517 int rv = 0; 518 519 if (sc->sc_child != NULL) 520 rv = config_detach(sc->sc_child, flags); 521 522 if (rv != 0) 523 return rv; 524 525 /* XXX unconfigure/free slots */ 526 527 /* verify: */ 528 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 529 xhci_op_write_4(sc, XHCI_USBCMD, 0); 530 /* do we need to wait for stop? */ 531 532 xhci_op_write_8(sc, XHCI_CRCR, 0); 533 xhci_ring_free(sc, &sc->sc_cr); 534 cv_destroy(&sc->sc_command_cv); 535 536 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 537 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 538 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 539 xhci_ring_free(sc, &sc->sc_er); 540 541 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 542 543 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 544 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 545 546 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 547 548 mutex_destroy(&sc->sc_lock); 549 mutex_destroy(&sc->sc_intr_lock); 550 cv_destroy(&sc->sc_softwake_cv); 551 552 pool_cache_destroy(sc->sc_xferpool); 553 554 return rv; 555 } 556 557 int 558 xhci_activate(device_t self, enum devact act) 559 { 560 struct xhci_softc * const sc = device_private(self); 561 562 switch (act) { 563 case DVACT_DEACTIVATE: 564 sc->sc_dying = true; 565 return 0; 566 default: 567 return EOPNOTSUPP; 568 } 569 } 570 571 bool 572 xhci_suspend(device_t dv, const pmf_qual_t *qual) 573 { 574 return false; 575 } 576 577 bool 578 xhci_resume(device_t dv, const pmf_qual_t *qual) 579 { 580 return false; 581 } 582 583 bool 584 xhci_shutdown(device_t self, int flags) 585 { 586 return false; 587 } 588 589 590 static void 591 hexdump(const char *msg, const void *base, size_t len) 592 { 593 #if 0 594 size_t cnt; 595 const uint32_t *p; 596 extern paddr_t vtophys(vaddr_t); 597 598 p = base; 599 cnt = 0; 600 601 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 602 (void *)vtophys((vaddr_t)base)); 603 604 while (cnt < len) { 605 if (cnt % 16 == 0) 606 printf("%p: ", p); 607 else if (cnt % 8 == 0) 608 printf(" |"); 609 printf(" %08x", *p++); 610 cnt += 4; 611 if (cnt % 16 == 0) 612 printf("\n"); 613 } 614 #endif 615 } 616 617 #define XHCI_HCCPREV1_BITS \ 618 "\177\020" /* New bitmask */ \ 619 "f\020\020XECP\0" \ 620 "f\014\4MAXPSA\0" \ 621 "b\013CFC\0" \ 622 "b\012SEC\0" \ 623 "b\011SBD\0" \ 624 "b\010FSE\0" \ 625 "b\7NSS\0" \ 626 "b\6LTC\0" \ 627 "b\5LHRC\0" \ 628 "b\4PIND\0" \ 629 "b\3PPC\0" \ 630 "b\2CZC\0" \ 631 "b\1BNC\0" \ 632 "b\0AC64\0" \ 633 "\0" 634 #define XHCI_HCCV1_x_BITS \ 635 "\177\020" /* New bitmask */ \ 636 "f\020\020XECP\0" \ 637 "f\014\4MAXPSA\0" \ 638 "b\013CFC\0" \ 639 "b\012SEC\0" \ 640 "b\011SPC\0" \ 641 "b\010PAE\0" \ 642 "b\7NSS\0" \ 643 "b\6LTC\0" \ 644 "b\5LHRC\0" \ 645 "b\4PIND\0" \ 646 "b\3PPC\0" \ 647 "b\2CSZ\0" \ 648 "b\1BNC\0" \ 649 "b\0AC64\0" \ 650 "\0" 651 652 int 653 xhci_init(struct xhci_softc *sc) 654 { 655 bus_size_t bsz; 656 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 657 uint32_t ecp, ecr; 658 uint32_t usbcmd, usbsts, pagesize, config; 659 int i; 660 uint16_t hciversion; 661 uint8_t caplength; 662 663 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 664 665 sc->sc_bus.ub_revision = USBREV_3_0; 666 sc->sc_bus.ub_usedma = true; 667 668 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 669 caplength = XHCI_CAP_CAPLENGTH(cap); 670 hciversion = XHCI_CAP_HCIVERSION(cap); 671 672 if (hciversion < XHCI_HCIVERSION_0_96 || 673 hciversion > XHCI_HCIVERSION_1_0) { 674 aprint_normal_dev(sc->sc_dev, 675 "xHCI version %x.%x not known to be supported\n", 676 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 677 } else { 678 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 679 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 680 } 681 682 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 683 &sc->sc_cbh) != 0) { 684 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 685 return ENOMEM; 686 } 687 688 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 689 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 690 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 691 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 692 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 693 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 694 aprint_debug_dev(sc->sc_dev, 695 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 696 697 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 698 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 699 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 700 701 char sbuf[128]; 702 if (hciversion < XHCI_HCIVERSION_1_0) 703 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 704 else 705 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 706 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 707 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 708 709 ecp = XHCI_HCC_XECP(hcc) * 4; 710 while (ecp != 0) { 711 ecr = xhci_read_4(sc, ecp); 712 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 713 switch (XHCI_XECP_ID(ecr)) { 714 case XHCI_ID_PROTOCOLS: { 715 uint32_t w0, w4, w8; 716 uint16_t w2; 717 w0 = xhci_read_4(sc, ecp + 0); 718 w2 = (w0 >> 16) & 0xffff; 719 w4 = xhci_read_4(sc, ecp + 4); 720 w8 = xhci_read_4(sc, ecp + 8); 721 aprint_debug_dev(sc->sc_dev, "SP: %08x %08x %08x\n", 722 w0, w4, w8); 723 if (w4 == 0x20425355 && w2 == 0x0300) { 724 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 725 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 726 } 727 if (w4 == 0x20425355 && w2 == 0x0200) { 728 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 729 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 730 } 731 break; 732 } 733 case XHCI_ID_USB_LEGACY: { 734 uint8_t bios_sem; 735 736 /* Take host controller from BIOS */ 737 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 738 if (bios_sem) { 739 /* sets xHCI to be owned by OS */ 740 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 741 aprint_debug( 742 "waiting for BIOS to give up control\n"); 743 for (i = 0; i < 5000; i++) { 744 bios_sem = xhci_read_1(sc, ecp + 745 XHCI_XECP_BIOS_SEM); 746 if (bios_sem == 0) 747 break; 748 DELAY(1000); 749 } 750 if (bios_sem) 751 printf("timed out waiting for BIOS\n"); 752 } 753 break; 754 } 755 default: 756 break; 757 } 758 ecr = xhci_read_4(sc, ecp); 759 if (XHCI_XECP_NEXT(ecr) == 0) { 760 ecp = 0; 761 } else { 762 ecp += XHCI_XECP_NEXT(ecr) * 4; 763 } 764 } 765 766 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 767 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 768 &sc->sc_obh) != 0) { 769 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 770 return ENOMEM; 771 } 772 773 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 774 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 775 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 776 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 777 return ENOMEM; 778 } 779 780 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 781 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 782 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 783 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 784 return ENOMEM; 785 } 786 787 for (i = 0; i < 100; i++) { 788 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 789 if ((usbsts & XHCI_STS_CNR) == 0) 790 break; 791 usb_delay_ms(&sc->sc_bus, 1); 792 } 793 if (i >= 100) 794 return EIO; 795 796 usbcmd = 0; 797 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 798 usb_delay_ms(&sc->sc_bus, 1); 799 800 usbcmd = XHCI_CMD_HCRST; 801 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 802 for (i = 0; i < 100; i++) { 803 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 804 if ((usbcmd & XHCI_CMD_HCRST) == 0) 805 break; 806 usb_delay_ms(&sc->sc_bus, 1); 807 } 808 if (i >= 100) 809 return EIO; 810 811 for (i = 0; i < 100; i++) { 812 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 813 if ((usbsts & XHCI_STS_CNR) == 0) 814 break; 815 usb_delay_ms(&sc->sc_bus, 1); 816 } 817 if (i >= 100) 818 return EIO; 819 820 if (sc->sc_vendor_init) 821 sc->sc_vendor_init(sc); 822 823 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 824 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 825 pagesize = ffs(pagesize); 826 if (pagesize == 0) 827 return EIO; 828 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 829 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 830 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 831 (uint32_t)sc->sc_maxslots); 832 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 833 834 usbd_status err; 835 836 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 837 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 838 if (sc->sc_maxspbuf != 0) { 839 err = usb_allocmem(&sc->sc_bus, 840 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 841 &sc->sc_spbufarray_dma); 842 if (err) 843 return err; 844 845 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * sc->sc_maxspbuf, KM_SLEEP); 846 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 847 for (i = 0; i < sc->sc_maxspbuf; i++) { 848 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 849 /* allocate contexts */ 850 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 851 sc->sc_pgsz, dma); 852 if (err) 853 return err; 854 spbufarray[i] = htole64(DMAADDR(dma, 0)); 855 usb_syncmem(dma, 0, sc->sc_pgsz, 856 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 857 } 858 859 usb_syncmem(&sc->sc_spbufarray_dma, 0, 860 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 861 } 862 863 config = xhci_op_read_4(sc, XHCI_CONFIG); 864 config &= ~0xFF; 865 config |= sc->sc_maxslots & 0xFF; 866 xhci_op_write_4(sc, XHCI_CONFIG, config); 867 868 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 869 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 870 if (err) { 871 aprint_error_dev(sc->sc_dev, "command ring init fail\n"); 872 return err; 873 } 874 875 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 876 XHCI_EVENT_RING_SEGMENTS_ALIGN); 877 if (err) { 878 aprint_error_dev(sc->sc_dev, "event ring init fail\n"); 879 return err; 880 } 881 882 usb_dma_t *dma; 883 size_t size; 884 size_t align; 885 886 dma = &sc->sc_eventst_dma; 887 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 888 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 889 KASSERT(size <= (512 * 1024)); 890 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 891 err = usb_allocmem(&sc->sc_bus, size, align, dma); 892 893 memset(KERNADDR(dma, 0), 0, size); 894 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 895 aprint_debug_dev(sc->sc_dev, "eventst: %s %016jx %p %zx\n", 896 usbd_errstr(err), 897 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 898 KERNADDR(&sc->sc_eventst_dma, 0), 899 sc->sc_eventst_dma.udma_block->size); 900 901 dma = &sc->sc_dcbaa_dma; 902 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 903 KASSERT(size <= 2048); 904 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 905 err = usb_allocmem(&sc->sc_bus, size, align, dma); 906 907 memset(KERNADDR(dma, 0), 0, size); 908 if (sc->sc_maxspbuf != 0) { 909 /* 910 * DCBA entry 0 hold the scratchbuf array pointer. 911 */ 912 *(uint64_t *)KERNADDR(dma, 0) = 913 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 914 } 915 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 916 aprint_debug_dev(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n", 917 usbd_errstr(err), 918 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 919 KERNADDR(&sc->sc_dcbaa_dma, 0), 920 sc->sc_dcbaa_dma.udma_block->size); 921 922 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 923 KM_SLEEP); 924 925 cv_init(&sc->sc_command_cv, "xhcicmd"); 926 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 927 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 928 cv_init(&sc->sc_softwake_cv, "xhciab"); 929 930 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 931 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 932 933 /* Set up the bus struct. */ 934 sc->sc_bus.ub_methods = &xhci_bus_methods; 935 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 936 937 struct xhci_erste *erst; 938 erst = KERNADDR(&sc->sc_eventst_dma, 0); 939 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 940 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 941 erst[0].erste_3 = htole32(0); 942 usb_syncmem(&sc->sc_eventst_dma, 0, 943 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 944 945 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 946 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 947 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 948 XHCI_ERDP_LO_BUSY); 949 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 950 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 951 sc->sc_cr.xr_cs); 952 953 #if 0 954 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 955 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 956 #endif 957 958 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 959 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 960 /* Intel xhci needs interrupt rate moderated. */ 961 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 962 else 963 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 964 aprint_debug_dev(sc->sc_dev, "setting IMOD %u\n", 965 xhci_rt_read_4(sc, XHCI_IMOD(0))); 966 967 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 968 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 969 xhci_op_read_4(sc, XHCI_USBCMD)); 970 971 return USBD_NORMAL_COMPLETION; 972 } 973 974 int 975 xhci_intr(void *v) 976 { 977 struct xhci_softc * const sc = v; 978 int ret = 0; 979 980 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 981 982 if (sc == NULL) 983 return 0; 984 985 mutex_spin_enter(&sc->sc_intr_lock); 986 987 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 988 goto done; 989 990 /* If we get an interrupt while polling, then just ignore it. */ 991 if (sc->sc_bus.ub_usepolling) { 992 #ifdef DIAGNOSTIC 993 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 994 #endif 995 goto done; 996 } 997 998 ret = xhci_intr1(sc); 999 done: 1000 mutex_spin_exit(&sc->sc_intr_lock); 1001 return ret; 1002 } 1003 1004 int 1005 xhci_intr1(struct xhci_softc * const sc) 1006 { 1007 uint32_t usbsts; 1008 uint32_t iman; 1009 1010 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1011 1012 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1013 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1014 #if 0 1015 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1016 return 0; 1017 } 1018 #endif 1019 xhci_op_write_4(sc, XHCI_USBSTS, 1020 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1021 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1022 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1023 1024 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1025 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1026 iman |= XHCI_IMAN_INTR_PEND; 1027 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1028 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1029 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1030 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1031 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1032 1033 usb_schedsoftintr(&sc->sc_bus); 1034 1035 return 1; 1036 } 1037 1038 /* 1039 * 3 port speed types used in USB stack 1040 * 1041 * usbdi speed 1042 * definition: USB_SPEED_* in usb.h 1043 * They are used in struct usbd_device in USB stack. 1044 * ioctl interface uses these values too. 1045 * port_status speed 1046 * definition: UPS_*_SPEED in usb.h 1047 * They are used in usb_port_status_t and valid only for USB 2.0. 1048 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1049 * of usb_port_status_ext_t indicates port speed. 1050 * Note that some 3.0 values overlap with 2.0 values. 1051 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1052 * means UPS_LOW_SPEED in HS.) 1053 * port status returned from hub also uses these values. 1054 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1055 * or more. 1056 * xspeed: 1057 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1058 * They are used in only slot context and PORTSC reg of xhci. 1059 * The difference between usbdi speed and xspeed is 1060 * that FS and LS values are swapped. 1061 */ 1062 1063 /* convert usbdi speed to xspeed */ 1064 static int 1065 xhci_speed2xspeed(int speed) 1066 { 1067 switch (speed) { 1068 case USB_SPEED_LOW: return 2; 1069 case USB_SPEED_FULL: return 1; 1070 default: return speed; 1071 } 1072 } 1073 1074 #if 0 1075 /* convert xspeed to usbdi speed */ 1076 static int 1077 xhci_xspeed2speed(int xspeed) 1078 { 1079 switch (xspeed) { 1080 case 1: return USB_SPEED_FULL; 1081 case 2: return USB_SPEED_LOW; 1082 default: return xspeed; 1083 } 1084 } 1085 #endif 1086 1087 /* convert xspeed to port status speed */ 1088 static int 1089 xhci_xspeed2psspeed(int xspeed) 1090 { 1091 switch (xspeed) { 1092 case 0: return 0; 1093 case 1: return UPS_FULL_SPEED; 1094 case 2: return UPS_LOW_SPEED; 1095 case 3: return UPS_HIGH_SPEED; 1096 default: return UPS_OTHER_SPEED; 1097 } 1098 } 1099 1100 /* construct slot context */ 1101 static void 1102 xhci_setup_sctx(struct usbd_device *dev, uint32_t *cp) 1103 { 1104 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 1105 int speed = dev->ud_speed; 1106 int tthubslot, ttportnum; 1107 bool ishub; 1108 bool usemtt; 1109 1110 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1111 1112 /* 1113 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 1114 * tthubslot: 1115 * This is the slot ID of parent HS hub 1116 * if LS/FS device is connected && connected through HS hub. 1117 * This is 0 if device is not LS/FS device || 1118 * parent hub is not HS hub || 1119 * attached to root hub. 1120 * ttportnum: 1121 * This is the downstream facing port of parent HS hub 1122 * if LS/FS device is connected. 1123 * This is 0 if device is not LS/FS device || 1124 * parent hub is not HS hub || 1125 * attached to root hub. 1126 */ 1127 if (dev->ud_myhsport != NULL && 1128 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1129 (dev->ud_myhub != NULL && 1130 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1131 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 1132 ttportnum = dev->ud_myhsport->up_portno; 1133 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 1134 } else { 1135 ttportnum = 0; 1136 tthubslot = 0; 1137 } 1138 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 1139 dev->ud_myhsport, ttportnum, tthubslot, 0); 1140 1141 /* ishub is valid after reading UDESC_DEVICE */ 1142 ishub = (dd->bDeviceClass == UDCLASS_HUB); 1143 1144 /* dev->ud_hub is valid after reading UDESC_HUB */ 1145 if (ishub && dev->ud_hub) { 1146 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 1147 1148 cp[1] |= htole32(XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts)); 1149 cp[2] |= htole32(XHCI_SCTX_2_TT_THINK_TIME_SET( 1150 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK))); 1151 DPRINTFN(4, "nports=%d ttt=%d", 1152 hd->bNbrPorts, XHCI_SCTX_2_TT_THINK_TIME_GET(cp[2]), 0, 0); 1153 } 1154 1155 #define IS_TTHUB(dd) \ 1156 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 1157 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 1158 1159 /* 1160 * MTT flag is set if 1161 * 1. this is HS hub && MTT is enabled 1162 * or 1163 * 2. this is not hub && this is LS or FS device && 1164 * MTT of parent HS hub (and its parent, too) is enabled 1165 */ 1166 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 1167 usemtt = true; 1168 else if (!ishub && 1169 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 1170 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1171 (dev->ud_myhub != NULL && 1172 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1173 dev->ud_myhsport != NULL && 1174 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 1175 usemtt = true; 1176 else 1177 usemtt = false; 1178 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 1179 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 1180 1181 cp[0] |= htole32( 1182 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)) | 1183 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 1184 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0) 1185 ); 1186 cp[1] |= htole32(0); 1187 cp[2] |= htole32( 1188 XHCI_SCTX_2_IRQ_TARGET_SET(0) | 1189 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 1190 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum) 1191 ); 1192 cp[3] |= htole32(0); 1193 } 1194 1195 static uint32_t 1196 xhci_get_maxburst(struct usbd_pipe *pipe) 1197 { 1198 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1199 usbd_desc_iter_t iter; 1200 const usb_cdc_descriptor_t *cdcd; 1201 const usb_endpoint_ss_comp_descriptor_t * esscd = NULL; 1202 uint32_t maxb = 0; 1203 uint8_t ep; 1204 1205 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc( 1206 pipe->up_dev, UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 1207 usb_desc_iter_init(pipe->up_dev, &iter); 1208 iter.cur = (const void *)cdcd; 1209 1210 /* find endpoint_ss_comp desc for ep of this pipe */ 1211 for (ep = 0;;) { 1212 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 1213 if (cdcd == NULL) 1214 break; 1215 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 1216 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 1217 bEndpointAddress; 1218 if (UE_GET_ADDR(ep) == 1219 UE_GET_ADDR(ed->bEndpointAddress)) { 1220 cdcd = (const usb_cdc_descriptor_t *) 1221 usb_desc_iter_next(&iter); 1222 break; 1223 } 1224 ep = 0; 1225 } 1226 } 1227 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 1228 esscd = (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 1229 maxb = esscd->bMaxBurst; 1230 } 1231 1232 return maxb; 1233 } 1234 1235 /* 1236 * Convert endpoint bInterval value to endpoint context interval value 1237 * for Interrupt pipe. 1238 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 1239 */ 1240 static uint32_t 1241 xhci_bival2ival(uint32_t ival, int speed) 1242 { 1243 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 1244 int i; 1245 1246 /* 1247 * round ival down to "the nearest base 2 multiple of 1248 * bInterval * 8". 1249 * bInterval is at most 255 as its type is uByte. 1250 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 1251 */ 1252 for (i = 10; i > 0; i--) { 1253 if ((ival * 8) >= (1 << i)) 1254 break; 1255 } 1256 ival = i; 1257 } else { 1258 /* Interval = bInterval-1 for SS/HS */ 1259 ival--; 1260 } 1261 1262 return ival; 1263 } 1264 1265 /* 1266 * 4.8.2, 6.2.3.2 1267 * construct common endpoint parameters 1268 */ 1269 static void 1270 xhci_setup_endp_ctx(struct usbd_pipe *pipe, uint32_t *cp) 1271 { 1272 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1273 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1274 const u_int dci = xhci_ep_get_dci(ed); 1275 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1276 uint32_t mps = UGETW(ed->wMaxPacketSize); 1277 uint32_t maxb = 0; 1278 int speed = pipe->up_dev->ud_speed; 1279 uint32_t ival = ed->bInterval; 1280 1281 cp[0] = htole32( 1282 XHCI_EPCTX_0_EPSTATE_SET(0) | 1283 XHCI_EPCTX_0_MULT_SET(0) | /* always 0 except SS iscoh */ 1284 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 1285 XHCI_EPCTX_0_LSA_SET(0) | 1286 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0) 1287 ); 1288 cp[1] = htole32( 1289 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 1290 XHCI_EPCTX_1_HID_SET(0) | 1291 XHCI_EPCTX_1_MAXB_SET(0) 1292 ); 1293 if (xfertype != UE_ISOCHRONOUS) 1294 cp[1] |= htole32(XHCI_EPCTX_1_CERR_SET(3)); 1295 1296 /* 6.2.3.4, 4.8.2.4 */ 1297 if (USB_IS_SS(speed)) { 1298 /* UBS 3.1 9.6.6 */ 1299 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1300 /* UBS 3.1 9.6.7 */ 1301 maxb = xhci_get_maxburst(pipe); 1302 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1303 } else { 1304 /* UBS 2.0 9.6.6 */ 1305 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps))); 1306 1307 /* 6.2.3.4 */ 1308 if (speed == USB_SPEED_HIGH && 1309 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 1310 maxb = UE_GET_TRANS(mps); 1311 } else { 1312 /* LS/FS or HS CTRL or HS BULK */ 1313 maxb = 0; 1314 } 1315 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1316 } 1317 1318 if (xfertype == UE_CONTROL) 1319 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(8)); /* 6.2.3 */ 1320 else if (USB_IS_SS(speed)) 1321 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps)); 1322 else 1323 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps))); 1324 1325 switch (xfertype) { 1326 case UE_CONTROL: 1327 break; 1328 case UE_BULK: 1329 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 1330 break; 1331 case UE_INTERRUPT: 1332 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1333 ival = pipe->up_interval; 1334 1335 ival = xhci_bival2ival(ival, speed); 1336 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1337 break; 1338 case UE_ISOCHRONOUS: 1339 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1340 ival = pipe->up_interval; 1341 1342 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 1343 if (speed == USB_SPEED_FULL) 1344 ival += 3; /* 1ms -> 125us */ 1345 ival--; 1346 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1347 1348 if (USB_IS_SS(speed)) { 1349 /* XXX if LEC = 1, set ESIT instead */ 1350 cp[0] |= htole32(XHCI_EPCTX_0_MULT_SET(0)); 1351 } 1352 break; 1353 default: 1354 break; 1355 } 1356 *(uint64_t *)(&cp[2]) = htole64( 1357 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 1358 XHCI_EPCTX_2_DCS_SET(1)); 1359 } 1360 1361 /* 1362 * Construct input contexts and issue TRB 1363 */ 1364 static usbd_status 1365 xhci_configure_endpoint(struct usbd_pipe *pipe) 1366 { 1367 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1368 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1369 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1370 struct xhci_trb trb; 1371 usbd_status err; 1372 uint32_t *cp; 1373 1374 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1375 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1376 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1377 pipe->up_endpoint->ue_edesc->bmAttributes); 1378 1379 /* XXX ensure input context is available? */ 1380 1381 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1382 1383 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1384 cp[0] = htole32(0); 1385 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 1386 1387 /* set up input slot context */ 1388 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1389 xhci_setup_sctx(pipe->up_dev, cp); 1390 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1391 1392 /* set up input endpoint context */ 1393 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 1394 xhci_setup_endp_ctx(pipe, cp); 1395 1396 /* sync input contexts before they are read from memory */ 1397 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1398 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1399 sc->sc_ctxsz * 1); 1400 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1401 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1402 1403 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1404 trb.trb_2 = 0; 1405 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1406 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1407 1408 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1409 1410 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1411 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1412 sc->sc_ctxsz * 1); 1413 1414 return err; 1415 } 1416 1417 #if 0 1418 static usbd_status 1419 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1420 { 1421 #ifdef USB_DEBUG 1422 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1423 #endif 1424 1425 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1426 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1427 1428 return USBD_NORMAL_COMPLETION; 1429 } 1430 #endif 1431 1432 /* 4.6.8, 6.4.3.7 */ 1433 static usbd_status 1434 xhci_reset_endpoint(struct usbd_pipe *pipe) 1435 { 1436 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1437 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1438 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1439 struct xhci_trb trb; 1440 usbd_status err; 1441 1442 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1443 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1444 1445 KASSERT(!mutex_owned(&sc->sc_lock)); 1446 1447 trb.trb_0 = 0; 1448 trb.trb_2 = 0; 1449 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1450 XHCI_TRB_3_EP_SET(dci) | 1451 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1452 1453 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1454 1455 return err; 1456 } 1457 1458 /* 1459 * 4.6.9, 6.4.3.8 1460 * Stop execution of TDs on xfer ring. 1461 * Should be called with sc_lock held. 1462 */ 1463 static usbd_status 1464 xhci_stop_endpoint(struct usbd_pipe *pipe) 1465 { 1466 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1467 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1468 struct xhci_trb trb; 1469 usbd_status err; 1470 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1471 1472 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1473 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1474 1475 KASSERT(mutex_owned(&sc->sc_lock)); 1476 1477 trb.trb_0 = 0; 1478 trb.trb_2 = 0; 1479 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1480 XHCI_TRB_3_EP_SET(dci) | 1481 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1482 1483 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1484 1485 return err; 1486 } 1487 1488 /* 1489 * Set TR Dequeue Pointer. 1490 * xCHI 1.1 4.6.10 6.4.3.9 1491 * Purge all of the transfer requests on ring. 1492 * EPSTATE of endpoint must be ERROR or STOPPED, or CONTEXT_STATE error. 1493 */ 1494 static usbd_status 1495 xhci_set_dequeue(struct usbd_pipe *pipe) 1496 { 1497 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1498 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1499 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1500 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1501 struct xhci_trb trb; 1502 usbd_status err; 1503 1504 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1505 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1506 1507 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1508 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1509 BUS_DMASYNC_PREWRITE); 1510 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1511 1512 xr->xr_ep = 0; 1513 xr->xr_cs = 1; 1514 1515 /* set DCS */ 1516 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1517 trb.trb_2 = 0; 1518 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1519 XHCI_TRB_3_EP_SET(dci) | 1520 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1521 1522 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1523 1524 return err; 1525 } 1526 1527 /* 1528 * Open new pipe: called from usbd_setup_pipe_flags. 1529 * Fills methods of pipe. 1530 * If pipe is not for ep0, calls configure_endpoint. 1531 */ 1532 static usbd_status 1533 xhci_open(struct usbd_pipe *pipe) 1534 { 1535 struct usbd_device * const dev = pipe->up_dev; 1536 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1537 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1538 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1539 1540 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1541 DPRINTFN(1, "addr %d depth %d port %d speed %d", 1542 dev->ud_addr, dev->ud_depth, dev->ud_powersrc->up_portno, 1543 dev->ud_speed); 1544 1545 if (sc->sc_dying) 1546 return USBD_IOERROR; 1547 1548 /* Root Hub */ 1549 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1550 switch (ed->bEndpointAddress) { 1551 case USB_CONTROL_ENDPOINT: 1552 pipe->up_methods = &roothub_ctrl_methods; 1553 break; 1554 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1555 pipe->up_methods = &xhci_root_intr_methods; 1556 break; 1557 default: 1558 pipe->up_methods = NULL; 1559 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1560 ed->bEndpointAddress, 0, 0, 0); 1561 return USBD_INVAL; 1562 } 1563 return USBD_NORMAL_COMPLETION; 1564 } 1565 1566 switch (xfertype) { 1567 case UE_CONTROL: 1568 pipe->up_methods = &xhci_device_ctrl_methods; 1569 break; 1570 case UE_ISOCHRONOUS: 1571 pipe->up_methods = &xhci_device_isoc_methods; 1572 return USBD_INVAL; 1573 break; 1574 case UE_BULK: 1575 pipe->up_methods = &xhci_device_bulk_methods; 1576 break; 1577 case UE_INTERRUPT: 1578 pipe->up_methods = &xhci_device_intr_methods; 1579 break; 1580 default: 1581 return USBD_IOERROR; 1582 break; 1583 } 1584 1585 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1586 return xhci_configure_endpoint(pipe); 1587 1588 return USBD_NORMAL_COMPLETION; 1589 } 1590 1591 /* 1592 * Closes pipe, called from usbd_kill_pipe via close methods. 1593 * If the endpoint to be closed is ep0, disable_slot. 1594 * Should be called with sc_lock held. 1595 */ 1596 static void 1597 xhci_close_pipe(struct usbd_pipe *pipe) 1598 { 1599 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1600 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1601 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1602 const u_int dci = xhci_ep_get_dci(ed); 1603 struct xhci_trb trb; 1604 uint32_t *cp; 1605 1606 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1607 1608 if (sc->sc_dying) 1609 return; 1610 1611 if (xs == NULL || xs->xs_idx == 0) 1612 /* xs is uninitialized before xhci_init_slot */ 1613 return; 1614 1615 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1616 1617 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1618 KASSERT(mutex_owned(&sc->sc_lock)); 1619 1620 if (pipe->up_dev->ud_depth == 0) 1621 return; 1622 1623 if (dci == XHCI_DCI_EP_CONTROL) { 1624 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1625 xhci_disable_slot(sc, xs->xs_idx); 1626 return; 1627 } 1628 1629 /* 1630 * This may fail in the case that xhci_close_pipe is called after 1631 * xhci_abort_xfer e.g. usbd_kill_pipe. 1632 */ 1633 (void)xhci_stop_endpoint(pipe); 1634 1635 /* 1636 * set appropriate bit to be dropped. 1637 * don't set DC bit to 1, otherwise all endpoints 1638 * would be deconfigured. 1639 */ 1640 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1641 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1642 cp[1] = htole32(0); 1643 1644 /* XXX should be most significant one, not dci? */ 1645 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1646 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1647 1648 /* sync input contexts before they are read from memory */ 1649 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1650 1651 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1652 trb.trb_2 = 0; 1653 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1654 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1655 1656 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1657 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1658 } 1659 1660 /* 1661 * Abort transfer. 1662 * Called with sc_lock held. 1663 * May be called from softintr context. 1664 */ 1665 static void 1666 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1667 { 1668 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1669 1670 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1671 DPRINTFN(4, "xfer %p pipe %p status %d", 1672 xfer, xfer->ux_pipe, status, 0); 1673 1674 KASSERT(mutex_owned(&sc->sc_lock)); 1675 1676 if (sc->sc_dying) { 1677 /* If we're dying, just do the software part. */ 1678 DPRINTFN(4, "dying", 0, 0, 0, 0); 1679 xfer->ux_status = status; /* make software ignore it */ 1680 callout_stop(&xfer->ux_callout); 1681 usb_transfer_complete(xfer); 1682 return; 1683 } 1684 1685 /* XXX need more stuff */ 1686 xfer->ux_status = status; 1687 callout_stop(&xfer->ux_callout); 1688 usb_transfer_complete(xfer); 1689 DPRINTFN(14, "end", 0, 0, 0, 0); 1690 1691 KASSERT(mutex_owned(&sc->sc_lock)); 1692 } 1693 1694 /* 1695 * Recover STALLed endpoint. 1696 * xHCI 1.1 sect 4.10.2.1 1697 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1698 * all transfers on transfer ring. 1699 * These are done in thread context asynchronously. 1700 */ 1701 static void 1702 xhci_clear_endpoint_stall_async_task(void *cookie) 1703 { 1704 struct usbd_xfer * const xfer = cookie; 1705 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1706 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1707 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1708 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1709 1710 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1711 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1712 1713 xhci_reset_endpoint(xfer->ux_pipe); 1714 xhci_set_dequeue(xfer->ux_pipe); 1715 1716 mutex_enter(&sc->sc_lock); 1717 tr->is_halted = false; 1718 usb_transfer_complete(xfer); 1719 mutex_exit(&sc->sc_lock); 1720 DPRINTFN(4, "ends", 0, 0, 0, 0); 1721 } 1722 1723 static usbd_status 1724 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1725 { 1726 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1727 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1728 1729 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1730 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1731 1732 if (sc->sc_dying) { 1733 return USBD_IOERROR; 1734 } 1735 1736 usb_init_task(&xp->xp_async_task, 1737 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1738 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1739 DPRINTFN(4, "ends", 0, 0, 0, 0); 1740 1741 return USBD_NORMAL_COMPLETION; 1742 } 1743 1744 /* Process roothub port status/change events and notify to uhub_intr. */ 1745 static void 1746 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1747 { 1748 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1749 uint8_t *p; 1750 1751 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1752 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1753 port, 0, 0); 1754 1755 if (xfer == NULL) 1756 return; 1757 1758 if (port > sc->sc_maxports) 1759 return; 1760 1761 p = xfer->ux_buf; 1762 memset(p, 0, xfer->ux_length); 1763 p[port/NBBY] |= 1 << (port%NBBY); 1764 xfer->ux_actlen = xfer->ux_length; 1765 xfer->ux_status = USBD_NORMAL_COMPLETION; 1766 usb_transfer_complete(xfer); 1767 } 1768 1769 /* Process Transfer Events */ 1770 static void 1771 xhci_event_transfer(struct xhci_softc * const sc, 1772 const struct xhci_trb * const trb) 1773 { 1774 uint64_t trb_0; 1775 uint32_t trb_2, trb_3; 1776 uint8_t trbcode; 1777 u_int slot, dci; 1778 struct xhci_slot *xs; 1779 struct xhci_ring *xr; 1780 struct xhci_xfer *xx; 1781 struct usbd_xfer *xfer; 1782 usbd_status err; 1783 1784 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1785 1786 trb_0 = le64toh(trb->trb_0); 1787 trb_2 = le32toh(trb->trb_2); 1788 trb_3 = le32toh(trb->trb_3); 1789 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1790 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1791 dci = XHCI_TRB_3_EP_GET(trb_3); 1792 xs = &sc->sc_slots[slot]; 1793 xr = &xs->xs_ep[dci].xe_tr; 1794 1795 /* sanity check */ 1796 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1797 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1798 1799 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1800 /* 1801 * When ED == 0, trb_0 is physical address of the TRB 1802 * that caused this event. (6.4.2.1) 1803 */ 1804 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 1805 1806 /* trb_0 range sanity check */ 1807 if (trb_0 < trbp || 1808 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 1809 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 1810 DPRINTFN(1, "invalid trb_0 0x%"PRIx64" trbp 0x%"PRIx64, 1811 trb_0, trbp, 0, 0); 1812 return; 1813 } 1814 int idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 1815 xx = xr->xr_cookies[idx]; 1816 1817 /* 1818 * If endpoint is stopped between TDs, TRB pointer points at 1819 * next TRB, however, it is not put yet or is a garbage TRB. 1820 * That's why xr_cookies may be NULL or look like broken. 1821 * Note: this ev happens only when hciversion >= 1.0 or 1822 * hciversion == 0.96 and FSE of hcc1 is set. 1823 */ 1824 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1825 DPRINTFN(1, "xx NULL: #%u: cookie %p: code %u trb_0 %" 1826 PRIx64, idx, xx, trbcode, trb_0); 1827 } 1828 } else { 1829 /* When ED != 0, trb_0 is kaddr of struct xhci_xfer. */ 1830 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1831 } 1832 /* XXX this may not happen */ 1833 if (xx == NULL) { 1834 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1835 return; 1836 } 1837 xfer = &xx->xx_xfer; 1838 /* XXX this may happen when detaching */ 1839 if (xfer == NULL) { 1840 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1841 xx, trb_0, 0, 0); 1842 return; 1843 } 1844 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1845 /* XXX I dunno why this happens */ 1846 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1847 1848 if (!xfer->ux_pipe->up_repeat && 1849 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1850 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1851 return; 1852 } 1853 1854 /* 4.11.5.2 Event Data TRB */ 1855 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1856 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1857 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1858 if ((trb_0 & 0x3) == 0x3) { 1859 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1860 } 1861 } 1862 1863 switch (trbcode) { 1864 case XHCI_TRB_ERROR_SHORT_PKT: 1865 case XHCI_TRB_ERROR_SUCCESS: 1866 xfer->ux_actlen = 1867 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1868 err = USBD_NORMAL_COMPLETION; 1869 break; 1870 case XHCI_TRB_ERROR_STALL: 1871 case XHCI_TRB_ERROR_BABBLE: 1872 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1873 xr->is_halted = true; 1874 err = USBD_STALLED; 1875 /* 1876 * Stalled endpoints can be recoverd by issuing 1877 * command TRB TYPE_RESET_EP on xHCI instead of 1878 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1879 * on the endpoint. However, this function may be 1880 * called from softint context (e.g. from umass), 1881 * in that case driver gets KASSERT in cv_timedwait 1882 * in xhci_do_command. 1883 * To avoid this, this runs reset_endpoint and 1884 * usb_transfer_complete in usb task thread 1885 * asynchronously (and then umass issues clear 1886 * UF_ENDPOINT_HALT). 1887 */ 1888 xfer->ux_status = err; 1889 xhci_clear_endpoint_stall_async(xfer); 1890 return; 1891 default: 1892 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1893 err = USBD_IOERROR; 1894 break; 1895 } 1896 xfer->ux_status = err; 1897 1898 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1899 if ((trb_0 & 0x3) == 0x0) { 1900 callout_stop(&xfer->ux_callout); 1901 usb_transfer_complete(xfer); 1902 } 1903 } else { 1904 callout_stop(&xfer->ux_callout); 1905 usb_transfer_complete(xfer); 1906 } 1907 } 1908 1909 /* Process Command complete events */ 1910 static void 1911 xhci_event_cmd(struct xhci_softc * const sc, 1912 const struct xhci_trb * const trb) 1913 { 1914 uint64_t trb_0; 1915 uint32_t trb_2, trb_3; 1916 1917 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1918 1919 trb_0 = le64toh(trb->trb_0); 1920 trb_2 = le32toh(trb->trb_2); 1921 trb_3 = le32toh(trb->trb_3); 1922 1923 if (trb_0 == sc->sc_command_addr) { 1924 sc->sc_result_trb.trb_0 = trb_0; 1925 sc->sc_result_trb.trb_2 = trb_2; 1926 sc->sc_result_trb.trb_3 = trb_3; 1927 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1928 XHCI_TRB_ERROR_SUCCESS) { 1929 DPRINTFN(1, "command completion " 1930 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1931 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1932 } 1933 cv_signal(&sc->sc_command_cv); 1934 } else { 1935 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 1936 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1937 trb_2, trb_3); 1938 } 1939 } 1940 1941 /* 1942 * Process events. 1943 * called from xhci_softintr 1944 */ 1945 static void 1946 xhci_handle_event(struct xhci_softc * const sc, 1947 const struct xhci_trb * const trb) 1948 { 1949 uint64_t trb_0; 1950 uint32_t trb_2, trb_3; 1951 1952 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1953 1954 trb_0 = le64toh(trb->trb_0); 1955 trb_2 = le32toh(trb->trb_2); 1956 trb_3 = le32toh(trb->trb_3); 1957 1958 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1959 trb, trb_0, trb_2, trb_3); 1960 1961 /* 1962 * 4.11.3.1, 6.4.2.1 1963 * TRB Pointer is invalid for these completion codes. 1964 */ 1965 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 1966 case XHCI_TRB_ERROR_RING_UNDERRUN: 1967 case XHCI_TRB_ERROR_RING_OVERRUN: 1968 case XHCI_TRB_ERROR_VF_RING_FULL: 1969 return; 1970 default: 1971 if (trb_0 == 0) { 1972 return; 1973 } 1974 break; 1975 } 1976 1977 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 1978 case XHCI_TRB_EVENT_TRANSFER: 1979 xhci_event_transfer(sc, trb); 1980 break; 1981 case XHCI_TRB_EVENT_CMD_COMPLETE: 1982 xhci_event_cmd(sc, trb); 1983 break; 1984 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1985 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1986 break; 1987 default: 1988 break; 1989 } 1990 } 1991 1992 static void 1993 xhci_softintr(void *v) 1994 { 1995 struct usbd_bus * const bus = v; 1996 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1997 struct xhci_ring * const er = &sc->sc_er; 1998 struct xhci_trb *trb; 1999 int i, j, k; 2000 2001 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2002 2003 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2004 2005 i = er->xr_ep; 2006 j = er->xr_cs; 2007 2008 DPRINTFN(16, "xr_ep %d xr_cs %d", i, j, 0, 0); 2009 2010 while (1) { 2011 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2012 BUS_DMASYNC_POSTREAD); 2013 trb = &er->xr_trb[i]; 2014 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2015 2016 if (j != k) 2017 break; 2018 2019 xhci_handle_event(sc, trb); 2020 2021 i++; 2022 if (i == XHCI_EVENT_RING_TRBS) { 2023 i = 0; 2024 j ^= 1; 2025 } 2026 } 2027 2028 er->xr_ep = i; 2029 er->xr_cs = j; 2030 2031 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2032 XHCI_ERDP_LO_BUSY); 2033 2034 DPRINTFN(16, "ends", 0, 0, 0, 0); 2035 2036 return; 2037 } 2038 2039 static void 2040 xhci_poll(struct usbd_bus *bus) 2041 { 2042 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2043 2044 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2045 2046 mutex_spin_enter(&sc->sc_intr_lock); 2047 xhci_intr1(sc); 2048 mutex_spin_exit(&sc->sc_intr_lock); 2049 2050 return; 2051 } 2052 2053 static struct usbd_xfer * 2054 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2055 { 2056 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2057 struct usbd_xfer *xfer; 2058 2059 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2060 2061 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 2062 if (xfer != NULL) { 2063 memset(xfer, 0, sizeof(struct xhci_xfer)); 2064 #ifdef DIAGNOSTIC 2065 xfer->ux_state = XFER_BUSY; 2066 #endif 2067 } 2068 2069 return xfer; 2070 } 2071 2072 static void 2073 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2074 { 2075 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2076 2077 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2078 2079 #ifdef DIAGNOSTIC 2080 if (xfer->ux_state != XFER_BUSY) { 2081 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 2082 xfer, xfer->ux_state, 0, 0); 2083 } 2084 xfer->ux_state = XFER_FREE; 2085 #endif 2086 pool_cache_put(sc->sc_xferpool, xfer); 2087 } 2088 2089 static void 2090 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2091 { 2092 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2093 2094 *lock = &sc->sc_lock; 2095 } 2096 2097 extern uint32_t usb_cookie_no; 2098 2099 /* 2100 * Called if uhub_explore finds a new device (via usbd_new_device). 2101 * Allocate and construct dev structure of default endpoint (ep0). 2102 * Determine initial MaxPacketSize (mps) by speed. 2103 * Determine route string and roothub port for slot of dev. 2104 * Allocate pipe of ep0. 2105 * Enable and initialize slot and Set Address. 2106 * Read device descriptor. 2107 * Register this device. 2108 */ 2109 static usbd_status 2110 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2111 int speed, int port, struct usbd_port *up) 2112 { 2113 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2114 struct usbd_device *dev; 2115 usbd_status err; 2116 usb_device_descriptor_t *dd; 2117 struct usbd_device *hub; 2118 struct usbd_device *adev; 2119 int rhport = 0; 2120 struct xhci_slot *xs; 2121 uint32_t *cp; 2122 uint32_t route = 0; 2123 uint8_t slot = 0; 2124 uint8_t addr; 2125 2126 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2127 DPRINTFN(4, "port=%d depth=%d speed=%d upport %d", 2128 port, depth, speed, up->up_portno); 2129 2130 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2131 if (dev == NULL) 2132 return USBD_NOMEM; 2133 2134 dev->ud_bus = bus; 2135 2136 /* Set up default endpoint handle. */ 2137 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2138 2139 /* Set up default endpoint descriptor. */ 2140 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2141 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2142 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2143 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2144 /* 4.3, 4.8.2.1 */ 2145 if (USB_IS_SS(speed)) { 2146 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2147 } else 2148 switch (speed) { 2149 case USB_SPEED_FULL: 2150 /* XXX using 64 as initial mps of ep0 in FS */ 2151 case USB_SPEED_HIGH: 2152 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2153 break; 2154 case USB_SPEED_LOW: 2155 default: 2156 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2157 break; 2158 } 2159 dev->ud_ep0desc.bInterval = 0; 2160 2161 /* doesn't matter, just don't let it uninitialized */ 2162 dev->ud_ep0.ue_toggle = 0; 2163 2164 DPRINTFN(4, "up %p portno %d", up, up->up_portno, 0, 0); 2165 2166 dev->ud_quirks = &usbd_no_quirk; 2167 dev->ud_addr = 0; 2168 dev->ud_ddesc.bMaxPacketSize = 0; 2169 dev->ud_depth = depth; 2170 dev->ud_powersrc = up; 2171 dev->ud_myhub = up->up_parent; 2172 2173 up->up_dev = dev; 2174 2175 /* Locate root hub port */ 2176 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2177 uint32_t dep; 2178 2179 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2180 hub, hub->ud_depth, hub->ud_powersrc, 2181 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2182 2183 if (hub->ud_powersrc == NULL) 2184 break; 2185 dep = hub->ud_depth; 2186 if (dep == 0) 2187 break; 2188 rhport = hub->ud_powersrc->up_portno; 2189 if (dep > USB_HUB_MAX_DEPTH) 2190 continue; 2191 2192 route |= 2193 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2194 << ((dep - 1) * 4); 2195 } 2196 route = route >> 4; 2197 DPRINTFN(4, "rhport %d Route %05x hub %p", rhport, route, hub, 0); 2198 2199 /* Locate port on upstream high speed hub */ 2200 for (adev = dev, hub = up->up_parent; 2201 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2202 adev = hub, hub = hub->ud_myhub) 2203 ; 2204 if (hub) { 2205 int p; 2206 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2207 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2208 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2209 goto found; 2210 } 2211 } 2212 panic("xhci_new_device: cannot find HS port"); 2213 found: 2214 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2215 } else { 2216 dev->ud_myhsport = NULL; 2217 } 2218 2219 dev->ud_speed = speed; 2220 dev->ud_langid = USBD_NOLANG; 2221 dev->ud_cookie.cookie = ++usb_cookie_no; 2222 2223 /* Establish the default pipe. */ 2224 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2225 &dev->ud_pipe0); 2226 if (err) { 2227 goto bad; 2228 } 2229 2230 dd = &dev->ud_ddesc; 2231 2232 if ((depth == 0) && (port == 0)) { 2233 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2234 bus->ub_devices[dev->ud_addr] = dev; 2235 err = usbd_get_initial_ddesc(dev, dd); 2236 if (err) 2237 goto bad; 2238 err = usbd_reload_device_desc(dev); 2239 if (err) 2240 goto bad; 2241 } else { 2242 err = xhci_enable_slot(sc, &slot); 2243 if (err) 2244 goto bad; 2245 xs = &sc->sc_slots[slot]; 2246 dev->ud_hcpriv = xs; 2247 err = xhci_init_slot(dev, slot, route, rhport); 2248 if (err) { 2249 dev->ud_hcpriv = NULL; 2250 /* 2251 * We have to disable_slot here because 2252 * xs->xs_idx == 0 when xhci_init_slot fails, 2253 * in that case usbd_remove_dev won't work. 2254 */ 2255 mutex_enter(&sc->sc_lock); 2256 xhci_disable_slot(sc, slot); 2257 mutex_exit(&sc->sc_lock); 2258 goto bad; 2259 } 2260 2261 /* Allow device time to set new address */ 2262 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2263 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2264 //hexdump("slot context", cp, sc->sc_ctxsz); 2265 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2266 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2267 /* XXX ensure we know when the hardware does something 2268 we can't yet cope with */ 2269 KASSERT(addr >= 1 && addr <= 127); 2270 dev->ud_addr = addr; 2271 /* XXX dev->ud_addr not necessarily unique on bus */ 2272 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2273 bus->ub_devices[dev->ud_addr] = dev; 2274 2275 err = usbd_get_initial_ddesc(dev, dd); 2276 if (err) 2277 goto bad; 2278 /* 4.8.2.1 */ 2279 if (USB_IS_SS(speed)) { 2280 if (dd->bMaxPacketSize != 9) { 2281 printf("%s: invalid mps 2^%u for SS ep0," 2282 " using 512\n", 2283 device_xname(sc->sc_dev), 2284 dd->bMaxPacketSize); 2285 dd->bMaxPacketSize = 9; 2286 } 2287 USETW(dev->ud_ep0desc.wMaxPacketSize, 2288 (1 << dd->bMaxPacketSize)); 2289 } else 2290 USETW(dev->ud_ep0desc.wMaxPacketSize, 2291 dd->bMaxPacketSize); 2292 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2293 xhci_update_ep0_mps(sc, xs, 2294 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2295 err = usbd_reload_device_desc(dev); 2296 if (err) 2297 goto bad; 2298 2299 #if 0 2300 /* Re-establish the default pipe with the new MPS. */ 2301 /* In xhci this is done by xhci_update_ep0_mps. */ 2302 usbd_kill_pipe(dev->ud_pipe0); 2303 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2304 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2305 #endif 2306 } 2307 2308 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2309 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2310 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2311 dd->bDeviceClass, dd->bDeviceSubClass, 2312 dd->bDeviceProtocol, 0); 2313 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2314 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2315 dev->ud_speed); 2316 2317 usbd_get_device_strings(dev); 2318 2319 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2320 2321 if ((depth == 0) && (port == 0)) { 2322 usbd_attach_roothub(parent, dev); 2323 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2324 return USBD_NORMAL_COMPLETION; 2325 } 2326 2327 2328 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2329 bad: 2330 if (err != USBD_NORMAL_COMPLETION) { 2331 usbd_remove_device(dev, up); 2332 } 2333 2334 return err; 2335 } 2336 2337 static usbd_status 2338 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2339 size_t ntrb, size_t align) 2340 { 2341 usbd_status err; 2342 size_t size = ntrb * XHCI_TRB_SIZE; 2343 2344 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2345 2346 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2347 if (err) 2348 return err; 2349 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2350 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2351 xr->xr_trb = xhci_ring_trbv(xr, 0); 2352 xr->xr_ntrb = ntrb; 2353 xr->xr_ep = 0; 2354 xr->xr_cs = 1; 2355 memset(xr->xr_trb, 0, size); 2356 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 2357 xr->is_halted = false; 2358 2359 return USBD_NORMAL_COMPLETION; 2360 } 2361 2362 static void 2363 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2364 { 2365 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2366 mutex_destroy(&xr->xr_lock); 2367 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2368 } 2369 2370 static void 2371 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2372 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2373 { 2374 size_t i; 2375 u_int ri; 2376 u_int cs; 2377 uint64_t parameter; 2378 uint32_t status; 2379 uint32_t control; 2380 2381 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2382 2383 KASSERT(ntrbs <= XHCI_XFER_NTRB); 2384 for (i = 0; i < ntrbs; i++) { 2385 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2386 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2387 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2388 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2389 XHCI_TRB_TYPE_LINK); 2390 } 2391 2392 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2393 2394 ri = xr->xr_ep; 2395 cs = xr->xr_cs; 2396 2397 /* 2398 * Although the xhci hardware can do scatter/gather dma from 2399 * arbitrary sized buffers, there is a non-obvious restriction 2400 * that a LINK trb is only allowed at the end of a burst of 2401 * transfers - which might be 16kB. 2402 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2403 * The simple solution is not to allow a LINK trb in the middle 2404 * of anything - as here. 2405 * XXX: (dsl) There are xhci controllers out there (eg some made by 2406 * ASMedia) that seem to lock up if they process a LINK trb but 2407 * cannot process the linked-to trb yet. 2408 * The code should write the 'cycle' bit on the link trb AFTER 2409 * adding the other trb. 2410 */ 2411 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2412 parameter = xhci_ring_trbp(xr, 0); 2413 status = 0; 2414 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2415 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2416 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2417 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2418 BUS_DMASYNC_PREWRITE); 2419 xr->xr_cookies[ri] = NULL; 2420 xr->xr_ep = 0; 2421 xr->xr_cs ^= 1; 2422 ri = xr->xr_ep; 2423 cs = xr->xr_cs; 2424 } 2425 2426 ri++; 2427 2428 /* Write any subsequent TRB first */ 2429 for (i = 1; i < ntrbs; i++) { 2430 parameter = trbs[i].trb_0; 2431 status = trbs[i].trb_2; 2432 control = trbs[i].trb_3; 2433 2434 if (cs) { 2435 control |= XHCI_TRB_3_CYCLE_BIT; 2436 } else { 2437 control &= ~XHCI_TRB_3_CYCLE_BIT; 2438 } 2439 2440 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2441 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2442 BUS_DMASYNC_PREWRITE); 2443 xr->xr_cookies[ri] = cookie; 2444 ri++; 2445 } 2446 2447 /* Write the first TRB last */ 2448 i = 0; 2449 parameter = trbs[i].trb_0; 2450 status = trbs[i].trb_2; 2451 control = trbs[i].trb_3; 2452 2453 if (xr->xr_cs) { 2454 control |= XHCI_TRB_3_CYCLE_BIT; 2455 } else { 2456 control &= ~XHCI_TRB_3_CYCLE_BIT; 2457 } 2458 2459 xhci_trb_put(&xr->xr_trb[xr->xr_ep], parameter, status, control); 2460 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2461 BUS_DMASYNC_PREWRITE); 2462 xr->xr_cookies[xr->xr_ep] = cookie; 2463 2464 xr->xr_ep = ri; 2465 xr->xr_cs = cs; 2466 2467 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2468 } 2469 2470 /* 2471 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2472 * Command completion is notified by cv_signal from xhci_handle_event 2473 * (called from interrupt from xHCI), or timed-out. 2474 * Command validation is performed in xhci_handle_event by checking if 2475 * trb_0 in CMD_COMPLETE TRB and sc->sc_command_addr are identical. 2476 */ 2477 static usbd_status 2478 xhci_do_command1(struct xhci_softc * const sc, struct xhci_trb * const trb, 2479 int timeout, int locked) 2480 { 2481 struct xhci_ring * const cr = &sc->sc_cr; 2482 usbd_status err; 2483 2484 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2485 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2486 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2487 2488 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2489 2490 if (!locked) 2491 mutex_enter(&sc->sc_lock); 2492 2493 /* XXX KASSERT may fire when cv_timedwait unlocks sc_lock */ 2494 KASSERT(sc->sc_command_addr == 0); 2495 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2496 2497 mutex_enter(&cr->xr_lock); 2498 xhci_ring_put(sc, cr, NULL, trb, 1); 2499 mutex_exit(&cr->xr_lock); 2500 2501 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2502 2503 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2504 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2505 err = USBD_TIMEOUT; 2506 goto timedout; 2507 } 2508 2509 trb->trb_0 = sc->sc_result_trb.trb_0; 2510 trb->trb_2 = sc->sc_result_trb.trb_2; 2511 trb->trb_3 = sc->sc_result_trb.trb_3; 2512 2513 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2514 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2515 2516 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2517 case XHCI_TRB_ERROR_SUCCESS: 2518 err = USBD_NORMAL_COMPLETION; 2519 break; 2520 default: 2521 case 192 ... 223: 2522 err = USBD_IOERROR; 2523 break; 2524 case 224 ... 255: 2525 err = USBD_NORMAL_COMPLETION; 2526 break; 2527 } 2528 2529 timedout: 2530 sc->sc_command_addr = 0; 2531 if (!locked) 2532 mutex_exit(&sc->sc_lock); 2533 return err; 2534 } 2535 2536 static usbd_status 2537 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2538 int timeout) 2539 { 2540 return xhci_do_command1(sc, trb, timeout, 0); 2541 } 2542 2543 /* 2544 * This allows xhci_do_command with already sc_lock held. 2545 * This is needed as USB stack calls close methods with sc_lock_held. 2546 * (see usbdivar.h) 2547 */ 2548 static usbd_status 2549 xhci_do_command_locked(struct xhci_softc * const sc, 2550 struct xhci_trb * const trb, int timeout) 2551 { 2552 return xhci_do_command1(sc, trb, timeout, 1); 2553 } 2554 2555 static usbd_status 2556 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2557 { 2558 struct xhci_trb trb; 2559 usbd_status err; 2560 2561 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2562 2563 trb.trb_0 = 0; 2564 trb.trb_2 = 0; 2565 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2566 2567 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2568 if (err != USBD_NORMAL_COMPLETION) { 2569 return err; 2570 } 2571 2572 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2573 2574 return err; 2575 } 2576 2577 /* 2578 * Deallocate DMA buffer and ring buffer, and disable_slot. 2579 * Should be called with sc_lock held. 2580 */ 2581 static usbd_status 2582 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2583 { 2584 struct xhci_trb trb; 2585 struct xhci_slot *xs; 2586 usbd_status err; 2587 2588 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2589 2590 if (sc->sc_dying) 2591 return USBD_IOERROR; 2592 2593 trb.trb_0 = 0; 2594 trb.trb_2 = 0; 2595 trb.trb_3 = htole32( 2596 XHCI_TRB_3_SLOT_SET(slot) | 2597 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2598 2599 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2600 2601 if (!err) { 2602 xs = &sc->sc_slots[slot]; 2603 if (xs->xs_idx != 0) { 2604 for (int i = XHCI_DCI_SLOT + 1; i < 32; i++) { 2605 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2606 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2607 } 2608 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2609 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2610 xhci_set_dcba(sc, 0, slot); 2611 memset(xs, 0, sizeof(*xs)); 2612 } 2613 } 2614 2615 return err; 2616 } 2617 2618 /* 2619 * Change slot state. 2620 * bsr=0: ENABLED -> ADDRESSED 2621 * bsr=1: ENABLED -> DEFAULT 2622 * see xHCI 1.1 4.5.3, 3.3.4 2623 */ 2624 static usbd_status 2625 xhci_address_device(struct xhci_softc * const sc, 2626 uint64_t icp, uint8_t slot_id, bool bsr) 2627 { 2628 struct xhci_trb trb; 2629 usbd_status err; 2630 2631 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2632 2633 trb.trb_0 = icp; 2634 trb.trb_2 = 0; 2635 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2636 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2637 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2638 2639 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2640 2641 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2642 err = USBD_NO_ADDR; 2643 2644 return err; 2645 } 2646 2647 static usbd_status 2648 xhci_update_ep0_mps(struct xhci_softc * const sc, 2649 struct xhci_slot * const xs, u_int mps) 2650 { 2651 struct xhci_trb trb; 2652 usbd_status err; 2653 uint32_t * cp; 2654 2655 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2656 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2657 2658 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2659 cp[0] = htole32(0); 2660 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2661 2662 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2663 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2664 2665 /* sync input contexts before they are read from memory */ 2666 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2667 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2668 sc->sc_ctxsz * 4); 2669 2670 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2671 trb.trb_2 = 0; 2672 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2673 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2674 2675 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2676 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2677 return err; 2678 } 2679 2680 static void 2681 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2682 { 2683 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2684 2685 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2686 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2687 &dcbaa[si], dcba, si, 0); 2688 2689 dcbaa[si] = htole64(dcba); 2690 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2691 BUS_DMASYNC_PREWRITE); 2692 } 2693 2694 /* 2695 * Allocate DMA buffer and ring buffer for specified slot 2696 * and set Device Context Base Address 2697 * and issue Set Address device command. 2698 */ 2699 static usbd_status 2700 xhci_init_slot(struct usbd_device *dev, uint32_t slot, int route, int rhport) 2701 { 2702 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2703 struct xhci_slot *xs; 2704 usbd_status err; 2705 u_int dci; 2706 uint32_t *cp; 2707 uint32_t mps = UGETW(dev->ud_ep0desc.wMaxPacketSize); 2708 2709 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2710 DPRINTFN(4, "slot %u speed %d route %05x rhport %d", 2711 slot, dev->ud_speed, route, rhport); 2712 2713 xs = &sc->sc_slots[slot]; 2714 2715 /* allocate contexts */ 2716 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2717 &xs->xs_dc_dma); 2718 if (err) 2719 return err; 2720 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2721 2722 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2723 &xs->xs_ic_dma); 2724 if (err) 2725 goto bad1; 2726 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2727 2728 for (dci = 0; dci < 32; dci++) { 2729 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2730 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2731 if (dci == XHCI_DCI_SLOT) 2732 continue; 2733 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2734 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2735 if (err) { 2736 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2737 goto bad2; 2738 } 2739 } 2740 2741 /* set up initial input control context */ 2742 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2743 cp[0] = htole32(0); 2744 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 2745 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2746 2747 /* set up input slot context */ 2748 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2749 xhci_setup_sctx(dev, cp); 2750 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(1)); 2751 cp[0] |= htole32(XHCI_SCTX_0_ROUTE_SET(route)); 2752 cp[1] |= htole32(XHCI_SCTX_1_RH_PORT_SET(rhport)); 2753 2754 /* set up input EP0 context */ 2755 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2756 cp[0] = htole32(0); 2757 cp[1] = htole32( 2758 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 2759 XHCI_EPCTX_1_EPTYPE_SET(4) | 2760 XHCI_EPCTX_1_CERR_SET(3) 2761 ); 2762 /* can't use xhci_ep_get_dci() yet? */ 2763 *(uint64_t *)(&cp[2]) = htole64( 2764 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 2765 XHCI_EPCTX_2_DCS_SET(1)); 2766 cp[4] = htole32( 2767 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 2768 ); 2769 2770 /* sync input contexts before they are read from memory */ 2771 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2772 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2773 sc->sc_ctxsz * 3); 2774 2775 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2776 2777 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 2778 false); 2779 2780 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2781 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2782 sc->sc_ctxsz * 2); 2783 2784 bad2: 2785 if (err == USBD_NORMAL_COMPLETION) { 2786 xs->xs_idx = slot; 2787 } else { 2788 for (int i = 1; i < dci; i++) { 2789 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2790 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2791 } 2792 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2793 bad1: 2794 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2795 xs->xs_idx = 0; 2796 } 2797 2798 return err; 2799 } 2800 2801 /* ----- */ 2802 2803 static void 2804 xhci_noop(struct usbd_pipe *pipe) 2805 { 2806 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2807 } 2808 2809 /* 2810 * Process root hub request. 2811 */ 2812 static int 2813 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2814 void *buf, int buflen) 2815 { 2816 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2817 usb_port_status_t ps; 2818 int l, totlen = 0; 2819 uint16_t len, value, index; 2820 int port, i; 2821 uint32_t v; 2822 2823 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2824 2825 if (sc->sc_dying) 2826 return -1; 2827 2828 len = UGETW(req->wLength); 2829 value = UGETW(req->wValue); 2830 index = UGETW(req->wIndex); 2831 2832 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 2833 req->bmRequestType | (req->bRequest << 8), value, index, len); 2834 2835 #define C(x,y) ((x) | ((y) << 8)) 2836 switch (C(req->bRequest, req->bmRequestType)) { 2837 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2838 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 2839 if (len == 0) 2840 break; 2841 switch (value) { 2842 case C(0, UDESC_DEVICE): { 2843 usb_device_descriptor_t devd; 2844 totlen = min(buflen, sizeof(devd)); 2845 memcpy(&devd, buf, totlen); 2846 USETW(devd.idVendor, sc->sc_id_vendor); 2847 memcpy(buf, &devd, totlen); 2848 break; 2849 } 2850 #define sd ((usb_string_descriptor_t *)buf) 2851 case C(1, UDESC_STRING): 2852 /* Vendor */ 2853 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2854 break; 2855 case C(2, UDESC_STRING): 2856 /* Product */ 2857 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 2858 break; 2859 #undef sd 2860 default: 2861 /* default from usbroothub */ 2862 return buflen; 2863 } 2864 break; 2865 2866 /* Hub requests */ 2867 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2868 break; 2869 /* Clear Port Feature request */ 2870 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2871 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2872 index, value, 0, 0); 2873 if (index < 1 || index > sc->sc_maxports) { 2874 return -1; 2875 } 2876 port = XHCI_PORTSC(index); 2877 v = xhci_op_read_4(sc, port); 2878 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2879 v &= ~XHCI_PS_CLEAR; 2880 switch (value) { 2881 case UHF_PORT_ENABLE: 2882 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 2883 break; 2884 case UHF_PORT_SUSPEND: 2885 return -1; 2886 case UHF_PORT_POWER: 2887 break; 2888 case UHF_PORT_TEST: 2889 case UHF_PORT_INDICATOR: 2890 return -1; 2891 case UHF_C_PORT_CONNECTION: 2892 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2893 break; 2894 case UHF_C_PORT_ENABLE: 2895 case UHF_C_PORT_SUSPEND: 2896 case UHF_C_PORT_OVER_CURRENT: 2897 return -1; 2898 case UHF_C_BH_PORT_RESET: 2899 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 2900 break; 2901 case UHF_C_PORT_RESET: 2902 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2903 break; 2904 case UHF_C_PORT_LINK_STATE: 2905 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 2906 break; 2907 case UHF_C_PORT_CONFIG_ERROR: 2908 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 2909 break; 2910 default: 2911 return -1; 2912 } 2913 break; 2914 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2915 if (len == 0) 2916 break; 2917 if ((value & 0xff) != 0) { 2918 return -1; 2919 } 2920 usb_hub_descriptor_t hubd; 2921 2922 totlen = min(buflen, sizeof(hubd)); 2923 memcpy(&hubd, buf, totlen); 2924 hubd.bNbrPorts = sc->sc_maxports; 2925 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2926 hubd.bPwrOn2PwrGood = 200; 2927 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 2928 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2929 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2930 totlen = min(totlen, hubd.bDescLength); 2931 memcpy(buf, &hubd, totlen); 2932 break; 2933 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2934 if (len != 4) { 2935 return -1; 2936 } 2937 memset(buf, 0, len); /* ? XXX */ 2938 totlen = len; 2939 break; 2940 /* Get Port Status request */ 2941 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2942 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2943 if (index < 1 || index > sc->sc_maxports) { 2944 return -1; 2945 } 2946 if (len != 4) { 2947 return -1; 2948 } 2949 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 2950 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 2951 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 2952 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2953 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2954 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2955 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 2956 if (v & XHCI_PS_PR) i |= UPS_RESET; 2957 if (v & XHCI_PS_PP) { 2958 if (i & UPS_OTHER_SPEED) 2959 i |= UPS_PORT_POWER_SS; 2960 else 2961 i |= UPS_PORT_POWER; 2962 } 2963 if (i & UPS_OTHER_SPEED) 2964 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 2965 if (sc->sc_vendor_port_status) 2966 i = sc->sc_vendor_port_status(sc, v, i); 2967 USETW(ps.wPortStatus, i); 2968 i = 0; 2969 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2970 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2971 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2972 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2973 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 2974 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 2975 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 2976 USETW(ps.wPortChange, i); 2977 totlen = min(len, sizeof(ps)); 2978 memcpy(buf, &ps, totlen); 2979 break; 2980 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2981 return -1; 2982 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 2983 break; 2984 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2985 break; 2986 /* Set Port Feature request */ 2987 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 2988 int optval = (index >> 8) & 0xff; 2989 index &= 0xff; 2990 if (index < 1 || index > sc->sc_maxports) { 2991 return -1; 2992 } 2993 port = XHCI_PORTSC(index); 2994 v = xhci_op_read_4(sc, port); 2995 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2996 v &= ~XHCI_PS_CLEAR; 2997 switch (value) { 2998 case UHF_PORT_ENABLE: 2999 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3000 break; 3001 case UHF_PORT_SUSPEND: 3002 /* XXX suspend */ 3003 break; 3004 case UHF_PORT_RESET: 3005 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3006 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3007 /* Wait for reset to complete. */ 3008 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3009 if (sc->sc_dying) { 3010 return -1; 3011 } 3012 v = xhci_op_read_4(sc, port); 3013 if (v & XHCI_PS_PR) { 3014 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3015 usb_delay_ms(&sc->sc_bus, 10); 3016 /* XXX */ 3017 } 3018 break; 3019 case UHF_PORT_POWER: 3020 /* XXX power control */ 3021 break; 3022 /* XXX more */ 3023 case UHF_C_PORT_RESET: 3024 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3025 break; 3026 case UHF_PORT_U1_TIMEOUT: 3027 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3028 return -1; 3029 } 3030 port = XHCI_PORTPMSC(index); 3031 v = xhci_op_read_4(sc, port); 3032 v &= ~XHCI_PM3_U1TO_SET(0xff); 3033 v |= XHCI_PM3_U1TO_SET(optval); 3034 xhci_op_write_4(sc, port, v); 3035 break; 3036 case UHF_PORT_U2_TIMEOUT: 3037 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3038 return -1; 3039 } 3040 port = XHCI_PORTPMSC(index); 3041 v = xhci_op_read_4(sc, port); 3042 v &= ~XHCI_PM3_U2TO_SET(0xff); 3043 v |= XHCI_PM3_U2TO_SET(optval); 3044 xhci_op_write_4(sc, port, v); 3045 break; 3046 default: 3047 return -1; 3048 } 3049 } 3050 break; 3051 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3052 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3053 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3054 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3055 break; 3056 default: 3057 /* default from usbroothub */ 3058 return buflen; 3059 } 3060 3061 return totlen; 3062 } 3063 3064 /* root hub interrupt */ 3065 3066 static usbd_status 3067 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3068 { 3069 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3070 usbd_status err; 3071 3072 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3073 3074 /* Insert last in queue. */ 3075 mutex_enter(&sc->sc_lock); 3076 err = usb_insert_transfer(xfer); 3077 mutex_exit(&sc->sc_lock); 3078 if (err) 3079 return err; 3080 3081 /* Pipe isn't running, start first */ 3082 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3083 } 3084 3085 /* Wait for roothub port status/change */ 3086 static usbd_status 3087 xhci_root_intr_start(struct usbd_xfer *xfer) 3088 { 3089 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3090 3091 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3092 3093 if (sc->sc_dying) 3094 return USBD_IOERROR; 3095 3096 mutex_enter(&sc->sc_lock); 3097 sc->sc_intrxfer = xfer; 3098 mutex_exit(&sc->sc_lock); 3099 3100 return USBD_IN_PROGRESS; 3101 } 3102 3103 static void 3104 xhci_root_intr_abort(struct usbd_xfer *xfer) 3105 { 3106 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3107 3108 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3109 3110 KASSERT(mutex_owned(&sc->sc_lock)); 3111 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3112 3113 sc->sc_intrxfer = NULL; 3114 3115 xfer->ux_status = USBD_CANCELLED; 3116 usb_transfer_complete(xfer); 3117 } 3118 3119 static void 3120 xhci_root_intr_close(struct usbd_pipe *pipe) 3121 { 3122 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3123 3124 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3125 3126 KASSERT(mutex_owned(&sc->sc_lock)); 3127 3128 sc->sc_intrxfer = NULL; 3129 } 3130 3131 static void 3132 xhci_root_intr_done(struct usbd_xfer *xfer) 3133 { 3134 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3135 3136 xfer->ux_hcpriv = NULL; 3137 } 3138 3139 /* -------------- */ 3140 /* device control */ 3141 3142 static usbd_status 3143 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3144 { 3145 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3146 usbd_status err; 3147 3148 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3149 3150 /* Insert last in queue. */ 3151 mutex_enter(&sc->sc_lock); 3152 err = usb_insert_transfer(xfer); 3153 mutex_exit(&sc->sc_lock); 3154 if (err) 3155 return err; 3156 3157 /* Pipe isn't running, start first */ 3158 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3159 } 3160 3161 static usbd_status 3162 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3163 { 3164 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3165 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3166 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3167 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3168 struct xhci_xfer * const xx = (void *)xfer; 3169 usb_device_request_t * const req = &xfer->ux_request; 3170 const int isread = usbd_xfer_isread(xfer); 3171 const uint32_t len = UGETW(req->wLength); 3172 usb_dma_t * const dma = &xfer->ux_dmabuf; 3173 uint64_t parameter; 3174 uint32_t status; 3175 uint32_t control; 3176 u_int i; 3177 3178 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3179 DPRINTFN(12, "req: %04x %04x %04x %04x", 3180 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3181 UGETW(req->wIndex), UGETW(req->wLength)); 3182 3183 #if 0 /* event handler does this */ 3184 /* XXX */ 3185 if (tr->is_halted) { 3186 DPRINTFN(1, "ctrl xfer %p halted: slot %u dci %u", 3187 xfer, xs->xs_idx, dci, 0); 3188 xhci_reset_endpoint(xfer->ux_pipe); 3189 tr->is_halted = false; 3190 xhci_set_dequeue(xfer->ux_pipe); 3191 } 3192 #endif 3193 3194 /* we rely on the bottom bits for extra info */ 3195 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 3196 3197 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3198 3199 i = 0; 3200 3201 /* setup phase */ 3202 memcpy(¶meter, req, sizeof(*req)); 3203 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3204 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3205 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3206 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3207 XHCI_TRB_3_IDT_BIT; 3208 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3209 3210 if (len != 0) { 3211 /* data phase */ 3212 parameter = DMAADDR(dma, 0); 3213 KASSERT(len <= 0x10000); 3214 status = XHCI_TRB_2_IRQ_SET(0) | 3215 XHCI_TRB_2_TDSZ_SET(1) | 3216 XHCI_TRB_2_BYTES_SET(len); 3217 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3218 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3219 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3220 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3221 3222 parameter = (uintptr_t)xfer | 0x3; 3223 status = XHCI_TRB_2_IRQ_SET(0); 3224 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3225 XHCI_TRB_3_IOC_BIT; 3226 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3227 } 3228 3229 parameter = 0; 3230 status = XHCI_TRB_2_IRQ_SET(0); 3231 /* the status stage has inverted direction */ 3232 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3233 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3234 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3235 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3236 3237 parameter = (uintptr_t)xfer | 0x0; 3238 status = XHCI_TRB_2_IRQ_SET(0); 3239 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3240 XHCI_TRB_3_IOC_BIT; 3241 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3242 3243 mutex_enter(&tr->xr_lock); 3244 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3245 mutex_exit(&tr->xr_lock); 3246 3247 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3248 3249 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3250 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3251 xhci_timeout, xfer); 3252 } 3253 3254 if (sc->sc_bus.ub_usepolling) { 3255 DPRINTFN(1, "polling", 0, 0, 0, 0); 3256 //xhci_waitintr(sc, xfer); 3257 } 3258 3259 return USBD_IN_PROGRESS; 3260 } 3261 3262 static void 3263 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3264 { 3265 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3266 usb_device_request_t *req = &xfer->ux_request; 3267 int len = UGETW(req->wLength); 3268 int rd = req->bmRequestType & UT_READ; 3269 3270 if (len) 3271 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3272 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3273 } 3274 3275 static void 3276 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3277 { 3278 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3279 3280 xhci_abort_xfer(xfer, USBD_CANCELLED); 3281 } 3282 3283 static void 3284 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3285 { 3286 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3287 3288 xhci_close_pipe(pipe); 3289 } 3290 3291 /* ------------------ */ 3292 /* device isochronous */ 3293 3294 /* ----------- */ 3295 /* device bulk */ 3296 3297 static usbd_status 3298 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3299 { 3300 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3301 usbd_status err; 3302 3303 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3304 3305 /* Insert last in queue. */ 3306 mutex_enter(&sc->sc_lock); 3307 err = usb_insert_transfer(xfer); 3308 mutex_exit(&sc->sc_lock); 3309 if (err) 3310 return err; 3311 3312 /* 3313 * Pipe isn't running (otherwise err would be USBD_INPROG), 3314 * so start it first. 3315 */ 3316 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3317 } 3318 3319 static usbd_status 3320 xhci_device_bulk_start(struct usbd_xfer *xfer) 3321 { 3322 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3323 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3324 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3325 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3326 struct xhci_xfer * const xx = (void *)xfer; 3327 const uint32_t len = xfer->ux_length; 3328 usb_dma_t * const dma = &xfer->ux_dmabuf; 3329 uint64_t parameter; 3330 uint32_t status; 3331 uint32_t control; 3332 u_int i = 0; 3333 3334 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3335 3336 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3337 3338 if (sc->sc_dying) 3339 return USBD_IOERROR; 3340 3341 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3342 3343 parameter = DMAADDR(dma, 0); 3344 /* 3345 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3346 * If the user supplied buffer crosses such a boundary then 2 3347 * (or more) TRB should be used. 3348 * If multiple TRB are used the td_size field must be set correctly. 3349 * For v1.0 devices (like ivy bridge) this is the number of usb data 3350 * blocks needed to complete the transfer. 3351 * Setting it to 1 in the last TRB causes an extra zero-length 3352 * data block be sent. 3353 * The earlier documentation differs, I don't know how it behaves. 3354 */ 3355 KASSERT(len <= 0x10000); 3356 status = XHCI_TRB_2_IRQ_SET(0) | 3357 XHCI_TRB_2_TDSZ_SET(1) | 3358 XHCI_TRB_2_BYTES_SET(len); 3359 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3360 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3361 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3362 3363 mutex_enter(&tr->xr_lock); 3364 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3365 mutex_exit(&tr->xr_lock); 3366 3367 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3368 3369 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3370 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3371 xhci_timeout, xfer); 3372 } 3373 3374 if (sc->sc_bus.ub_usepolling) { 3375 DPRINTFN(1, "polling", 0, 0, 0, 0); 3376 //xhci_waitintr(sc, xfer); 3377 } 3378 3379 return USBD_IN_PROGRESS; 3380 } 3381 3382 static void 3383 xhci_device_bulk_done(struct usbd_xfer *xfer) 3384 { 3385 #ifdef USB_DEBUG 3386 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3387 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3388 #endif 3389 const int isread = usbd_xfer_isread(xfer); 3390 3391 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3392 3393 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3394 3395 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3396 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3397 } 3398 3399 static void 3400 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3401 { 3402 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3403 3404 xhci_abort_xfer(xfer, USBD_CANCELLED); 3405 } 3406 3407 static void 3408 xhci_device_bulk_close(struct usbd_pipe *pipe) 3409 { 3410 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3411 3412 xhci_close_pipe(pipe); 3413 } 3414 3415 /* ---------------- */ 3416 /* device interrupt */ 3417 3418 static usbd_status 3419 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3420 { 3421 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3422 usbd_status err; 3423 3424 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3425 3426 /* Insert last in queue. */ 3427 mutex_enter(&sc->sc_lock); 3428 err = usb_insert_transfer(xfer); 3429 mutex_exit(&sc->sc_lock); 3430 if (err) 3431 return err; 3432 3433 /* 3434 * Pipe isn't running (otherwise err would be USBD_INPROG), 3435 * so start it first. 3436 */ 3437 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3438 } 3439 3440 static usbd_status 3441 xhci_device_intr_start(struct usbd_xfer *xfer) 3442 { 3443 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3444 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3445 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3446 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3447 struct xhci_xfer * const xx = (void *)xfer; 3448 const uint32_t len = xfer->ux_length; 3449 usb_dma_t * const dma = &xfer->ux_dmabuf; 3450 uint64_t parameter; 3451 uint32_t status; 3452 uint32_t control; 3453 u_int i = 0; 3454 3455 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3456 3457 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3458 3459 if (sc->sc_dying) 3460 return USBD_IOERROR; 3461 3462 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3463 3464 parameter = DMAADDR(dma, 0); 3465 KASSERT(len <= 0x10000); 3466 status = XHCI_TRB_2_IRQ_SET(0) | 3467 XHCI_TRB_2_TDSZ_SET(1) | 3468 XHCI_TRB_2_BYTES_SET(len); 3469 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3470 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3471 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3472 3473 mutex_enter(&tr->xr_lock); 3474 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3475 mutex_exit(&tr->xr_lock); 3476 3477 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3478 3479 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3480 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3481 xhci_timeout, xfer); 3482 } 3483 3484 if (sc->sc_bus.ub_usepolling) { 3485 DPRINTFN(1, "polling", 0, 0, 0, 0); 3486 //xhci_waitintr(sc, xfer); 3487 } 3488 3489 return USBD_IN_PROGRESS; 3490 } 3491 3492 static void 3493 xhci_device_intr_done(struct usbd_xfer *xfer) 3494 { 3495 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3496 #ifdef USB_DEBUG 3497 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3498 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3499 #endif 3500 const int isread = usbd_xfer_isread(xfer); 3501 3502 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3503 3504 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3505 3506 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3507 3508 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3509 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3510 3511 #if 0 3512 device_printf(sc->sc_dev, ""); 3513 for (size_t i = 0; i < xfer->ux_length; i++) { 3514 printf(" %02x", ((uint8_t const *)xfer->ux_buffer)[i]); 3515 } 3516 printf("\n"); 3517 #endif 3518 3519 } 3520 3521 static void 3522 xhci_device_intr_abort(struct usbd_xfer *xfer) 3523 { 3524 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3525 3526 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3527 3528 KASSERT(mutex_owned(&sc->sc_lock)); 3529 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3530 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3531 xhci_abort_xfer(xfer, USBD_CANCELLED); 3532 } 3533 3534 static void 3535 xhci_device_intr_close(struct usbd_pipe *pipe) 3536 { 3537 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3538 3539 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3540 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3541 3542 xhci_close_pipe(pipe); 3543 } 3544 3545 /* ------------ */ 3546 3547 static void 3548 xhci_timeout(void *addr) 3549 { 3550 struct xhci_xfer * const xx = addr; 3551 struct usbd_xfer * const xfer = &xx->xx_xfer; 3552 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3553 3554 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3555 3556 if (sc->sc_dying) { 3557 return; 3558 } 3559 3560 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 3561 USB_TASKQ_MPSAFE); 3562 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 3563 USB_TASKQ_HC); 3564 } 3565 3566 static void 3567 xhci_timeout_task(void *addr) 3568 { 3569 struct usbd_xfer * const xfer = addr; 3570 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3571 3572 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3573 3574 mutex_enter(&sc->sc_lock); 3575 #if 0 3576 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3577 #else 3578 xfer->ux_status = USBD_TIMEOUT; 3579 usb_transfer_complete(xfer); 3580 #endif 3581 mutex_exit(&sc->sc_lock); 3582 } 3583
Indexes created Wed Oct 01 15:09:59 GMT 2025