xhci.c revision 1.28.2.71
1 /* $NetBSD: xhci.c,v 1.28.2.71 2016/06/05 10:50:36 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.28.2.71 2016/06/05 10:50:36 skrll Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static void xhci_host_dequeue(struct xhci_ring * const); 146 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 147 148 static usbd_status xhci_do_command(struct xhci_softc * const, 149 struct xhci_trb * const, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 153 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 154 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 155 static usbd_status xhci_enable_slot(struct xhci_softc * const, 156 uint8_t * const); 157 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 158 static usbd_status xhci_address_device(struct xhci_softc * const, 159 uint64_t, uint8_t, bool); 160 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 161 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 162 struct xhci_slot * const, u_int); 163 static usbd_status xhci_ring_init(struct xhci_softc * const, 164 struct xhci_ring * const, size_t, size_t); 165 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 166 167 static void xhci_setup_ctx(struct usbd_pipe *); 168 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 169 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 170 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 171 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 172 173 static void xhci_noop(struct usbd_pipe *); 174 175 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 176 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 177 static void xhci_root_intr_abort(struct usbd_xfer *); 178 static void xhci_root_intr_close(struct usbd_pipe *); 179 static void xhci_root_intr_done(struct usbd_xfer *); 180 181 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 182 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 183 static void xhci_device_ctrl_abort(struct usbd_xfer *); 184 static void xhci_device_ctrl_close(struct usbd_pipe *); 185 static void xhci_device_ctrl_done(struct usbd_xfer *); 186 187 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 188 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 189 static void xhci_device_intr_abort(struct usbd_xfer *); 190 static void xhci_device_intr_close(struct usbd_pipe *); 191 static void xhci_device_intr_done(struct usbd_xfer *); 192 193 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 194 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 195 static void xhci_device_bulk_abort(struct usbd_xfer *); 196 static void xhci_device_bulk_close(struct usbd_pipe *); 197 static void xhci_device_bulk_done(struct usbd_xfer *); 198 199 static void xhci_timeout(void *); 200 static void xhci_timeout_task(void *); 201 202 static const struct usbd_bus_methods xhci_bus_methods = { 203 .ubm_open = xhci_open, 204 .ubm_softint = xhci_softintr, 205 .ubm_dopoll = xhci_poll, 206 .ubm_allocx = xhci_allocx, 207 .ubm_freex = xhci_freex, 208 .ubm_getlock = xhci_get_lock, 209 .ubm_newdev = xhci_new_device, 210 .ubm_rhctrl = xhci_roothub_ctrl, 211 }; 212 213 static const struct usbd_pipe_methods xhci_root_intr_methods = { 214 .upm_transfer = xhci_root_intr_transfer, 215 .upm_start = xhci_root_intr_start, 216 .upm_abort = xhci_root_intr_abort, 217 .upm_close = xhci_root_intr_close, 218 .upm_cleartoggle = xhci_noop, 219 .upm_done = xhci_root_intr_done, 220 }; 221 222 223 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 224 .upm_transfer = xhci_device_ctrl_transfer, 225 .upm_start = xhci_device_ctrl_start, 226 .upm_abort = xhci_device_ctrl_abort, 227 .upm_close = xhci_device_ctrl_close, 228 .upm_cleartoggle = xhci_noop, 229 .upm_done = xhci_device_ctrl_done, 230 }; 231 232 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 233 .upm_cleartoggle = xhci_noop, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 237 .upm_transfer = xhci_device_bulk_transfer, 238 .upm_start = xhci_device_bulk_start, 239 .upm_abort = xhci_device_bulk_abort, 240 .upm_close = xhci_device_bulk_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_bulk_done, 243 }; 244 245 static const struct usbd_pipe_methods xhci_device_intr_methods = { 246 .upm_transfer = xhci_device_intr_transfer, 247 .upm_start = xhci_device_intr_start, 248 .upm_abort = xhci_device_intr_abort, 249 .upm_close = xhci_device_intr_close, 250 .upm_cleartoggle = xhci_noop, 251 .upm_done = xhci_device_intr_done, 252 }; 253 254 static inline uint32_t 255 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 256 { 257 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 258 } 259 260 static inline uint32_t 261 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 262 { 263 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 264 } 265 266 static inline void 267 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 268 uint32_t value) 269 { 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 271 } 272 273 #if 0 /* unused */ 274 static inline void 275 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 276 uint32_t value) 277 { 278 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 279 } 280 #endif /* unused */ 281 282 static inline uint32_t 283 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 284 { 285 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 286 } 287 288 static inline uint32_t 289 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 290 { 291 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 292 } 293 294 static inline void 295 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 296 uint32_t value) 297 { 298 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 299 } 300 301 static inline uint64_t 302 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 303 { 304 uint64_t value; 305 306 if (sc->sc_ac64) { 307 #ifdef XHCI_USE_BUS_SPACE_8 308 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 309 #else 310 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 311 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 312 offset + 4) << 32; 313 #endif 314 } else { 315 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 316 } 317 318 return value; 319 } 320 321 static inline void 322 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 336 } 337 } 338 339 static inline uint32_t 340 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 341 { 342 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 343 } 344 345 static inline void 346 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 347 uint32_t value) 348 { 349 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 350 } 351 352 #if 0 /* unused */ 353 static inline uint64_t 354 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 355 { 356 uint64_t value; 357 358 if (sc->sc_ac64) { 359 #ifdef XHCI_USE_BUS_SPACE_8 360 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 361 #else 362 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 363 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 364 offset + 4) << 32; 365 #endif 366 } else { 367 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 368 } 369 370 return value; 371 } 372 #endif /* unused */ 373 374 static inline void 375 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 376 uint64_t value) 377 { 378 if (sc->sc_ac64) { 379 #ifdef XHCI_USE_BUS_SPACE_8 380 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 381 #else 382 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 383 (value >> 0) & 0xffffffff); 384 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 385 (value >> 32) & 0xffffffff); 386 #endif 387 } else { 388 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 389 } 390 } 391 392 #if 0 /* unused */ 393 static inline uint32_t 394 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 395 { 396 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 397 } 398 #endif /* unused */ 399 400 static inline void 401 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 402 uint32_t value) 403 { 404 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 405 } 406 407 /* --- */ 408 409 static inline uint8_t 410 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 411 { 412 u_int eptype = 0; 413 414 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 415 case UE_CONTROL: 416 eptype = 0x0; 417 break; 418 case UE_ISOCHRONOUS: 419 eptype = 0x1; 420 break; 421 case UE_BULK: 422 eptype = 0x2; 423 break; 424 case UE_INTERRUPT: 425 eptype = 0x3; 426 break; 427 } 428 429 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 430 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 431 return eptype | 0x4; 432 else 433 return eptype; 434 } 435 436 static u_int 437 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 438 { 439 /* xHCI 1.0 section 4.5.1 */ 440 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 441 u_int in = 0; 442 443 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 444 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 445 in = 1; 446 447 return epaddr * 2 + in; 448 } 449 450 static inline u_int 451 xhci_dci_to_ici(const u_int i) 452 { 453 return i + 1; 454 } 455 456 static inline void * 457 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 458 const u_int dci) 459 { 460 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 461 } 462 463 #if 0 /* unused */ 464 static inline bus_addr_t 465 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 466 const u_int dci) 467 { 468 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 469 } 470 #endif /* unused */ 471 472 static inline void * 473 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline bus_addr_t 480 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 481 const u_int ici) 482 { 483 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 484 } 485 486 static inline struct xhci_trb * 487 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 488 { 489 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 490 } 491 492 static inline bus_addr_t 493 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 494 { 495 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 496 } 497 498 static inline void 499 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 500 uint32_t control) 501 { 502 trb->trb_0 = htole64(parameter); 503 trb->trb_2 = htole32(status); 504 trb->trb_3 = htole32(control); 505 } 506 507 static int 508 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 509 { 510 /* base address of TRBs */ 511 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 512 513 /* trb_0 range sanity check */ 514 if (trb_0 == 0 || trb_0 < trbp || 515 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 516 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 517 return 1; 518 } 519 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 520 return 0; 521 } 522 523 /* --- */ 524 525 void 526 xhci_childdet(device_t self, device_t child) 527 { 528 struct xhci_softc * const sc = device_private(self); 529 530 KASSERT(sc->sc_child == child); 531 if (child == sc->sc_child) 532 sc->sc_child = NULL; 533 } 534 535 int 536 xhci_detach(struct xhci_softc *sc, int flags) 537 { 538 int rv = 0; 539 540 if (sc->sc_child != NULL) 541 rv = config_detach(sc->sc_child, flags); 542 543 if (rv != 0) 544 return rv; 545 546 /* XXX unconfigure/free slots */ 547 548 /* verify: */ 549 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 550 xhci_op_write_4(sc, XHCI_USBCMD, 0); 551 /* do we need to wait for stop? */ 552 553 xhci_op_write_8(sc, XHCI_CRCR, 0); 554 xhci_ring_free(sc, &sc->sc_cr); 555 cv_destroy(&sc->sc_command_cv); 556 557 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 558 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 559 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 560 xhci_ring_free(sc, &sc->sc_er); 561 562 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 563 564 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 565 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 566 567 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 568 569 mutex_destroy(&sc->sc_lock); 570 mutex_destroy(&sc->sc_intr_lock); 571 572 pool_cache_destroy(sc->sc_xferpool); 573 574 return rv; 575 } 576 577 int 578 xhci_activate(device_t self, enum devact act) 579 { 580 struct xhci_softc * const sc = device_private(self); 581 582 switch (act) { 583 case DVACT_DEACTIVATE: 584 sc->sc_dying = true; 585 return 0; 586 default: 587 return EOPNOTSUPP; 588 } 589 } 590 591 bool 592 xhci_suspend(device_t dv, const pmf_qual_t *qual) 593 { 594 return false; 595 } 596 597 bool 598 xhci_resume(device_t dv, const pmf_qual_t *qual) 599 { 600 return false; 601 } 602 603 bool 604 xhci_shutdown(device_t self, int flags) 605 { 606 return false; 607 } 608 609 static int 610 xhci_hc_reset(struct xhci_softc * const sc) 611 { 612 uint32_t usbcmd, usbsts; 613 int i; 614 615 /* Check controller not ready */ 616 for (i = 0; i < XHCI_WAIT_CNR; i++) { 617 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 618 if ((usbsts & XHCI_STS_CNR) == 0) 619 break; 620 usb_delay_ms(&sc->sc_bus, 1); 621 } 622 if (i >= XHCI_WAIT_CNR) { 623 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 624 return EIO; 625 } 626 627 /* Halt controller */ 628 usbcmd = 0; 629 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 630 usb_delay_ms(&sc->sc_bus, 1); 631 632 /* Reset controller */ 633 usbcmd = XHCI_CMD_HCRST; 634 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 635 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 636 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 637 if ((usbcmd & XHCI_CMD_HCRST) == 0) 638 break; 639 usb_delay_ms(&sc->sc_bus, 1); 640 } 641 if (i >= XHCI_WAIT_HCRST) { 642 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 643 return EIO; 644 } 645 646 /* Check controller not ready */ 647 for (i = 0; i < XHCI_WAIT_CNR; i++) { 648 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 649 if ((usbsts & XHCI_STS_CNR) == 0) 650 break; 651 usb_delay_ms(&sc->sc_bus, 1); 652 } 653 if (i >= XHCI_WAIT_CNR) { 654 aprint_error_dev(sc->sc_dev, 655 "controller not ready timeout after reset\n"); 656 return EIO; 657 } 658 659 return 0; 660 } 661 662 663 static void 664 hexdump(const char *msg, const void *base, size_t len) 665 { 666 #if 0 667 size_t cnt; 668 const uint32_t *p; 669 extern paddr_t vtophys(vaddr_t); 670 671 p = base; 672 cnt = 0; 673 674 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 675 (void *)vtophys((vaddr_t)base)); 676 677 while (cnt < len) { 678 if (cnt % 16 == 0) 679 printf("%p: ", p); 680 else if (cnt % 8 == 0) 681 printf(" |"); 682 printf(" %08x", *p++); 683 cnt += 4; 684 if (cnt % 16 == 0) 685 printf("\n"); 686 } 687 if (cnt % 16 != 0) 688 printf("\n"); 689 #endif 690 } 691 692 /* Process extended capabilities */ 693 static void 694 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 695 { 696 uint32_t ecp, ecr; 697 698 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 699 700 ecp = XHCI_HCC_XECP(hcc) * 4; 701 while (ecp != 0) { 702 ecr = xhci_read_4(sc, ecp); 703 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 704 switch (XHCI_XECP_ID(ecr)) { 705 case XHCI_ID_PROTOCOLS: { 706 uint32_t w4, w8, wc; 707 uint16_t w2; 708 w2 = (ecr >> 16) & 0xffff; 709 w4 = xhci_read_4(sc, ecp + 4); 710 w8 = xhci_read_4(sc, ecp + 8); 711 wc = xhci_read_4(sc, ecp + 0xc); 712 aprint_debug_dev(sc->sc_dev, 713 " SP: %08x %08x %08x %08x\n", ecr, w4, w8, wc); 714 /* unused */ 715 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0300) { 716 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 717 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 718 } 719 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0200) { 720 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 721 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 722 } 723 break; 724 } 725 case XHCI_ID_USB_LEGACY: { 726 uint8_t bios_sem; 727 728 /* Take host controller ownership from BIOS */ 729 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 730 if (bios_sem) { 731 /* sets xHCI to be owned by OS */ 732 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 733 aprint_debug_dev(sc->sc_dev, 734 "waiting for BIOS to give up control\n"); 735 for (int i = 0; i < 5000; i++) { 736 bios_sem = xhci_read_1(sc, ecp + 737 XHCI_XECP_BIOS_SEM); 738 if (bios_sem == 0) 739 break; 740 DELAY(1000); 741 } 742 if (bios_sem) { 743 aprint_error_dev(sc->sc_dev, 744 "timed out waiting for BIOS\n"); 745 } 746 } 747 break; 748 } 749 default: 750 break; 751 } 752 ecr = xhci_read_4(sc, ecp); 753 if (XHCI_XECP_NEXT(ecr) == 0) { 754 ecp = 0; 755 } else { 756 ecp += XHCI_XECP_NEXT(ecr) * 4; 757 } 758 } 759 } 760 761 #define XHCI_HCCPREV1_BITS \ 762 "\177\020" /* New bitmask */ \ 763 "f\020\020XECP\0" \ 764 "f\014\4MAXPSA\0" \ 765 "b\013CFC\0" \ 766 "b\012SEC\0" \ 767 "b\011SBD\0" \ 768 "b\010FSE\0" \ 769 "b\7NSS\0" \ 770 "b\6LTC\0" \ 771 "b\5LHRC\0" \ 772 "b\4PIND\0" \ 773 "b\3PPC\0" \ 774 "b\2CZC\0" \ 775 "b\1BNC\0" \ 776 "b\0AC64\0" \ 777 "\0" 778 #define XHCI_HCCV1_x_BITS \ 779 "\177\020" /* New bitmask */ \ 780 "f\020\020XECP\0" \ 781 "f\014\4MAXPSA\0" \ 782 "b\013CFC\0" \ 783 "b\012SEC\0" \ 784 "b\011SPC\0" \ 785 "b\010PAE\0" \ 786 "b\7NSS\0" \ 787 "b\6LTC\0" \ 788 "b\5LHRC\0" \ 789 "b\4PIND\0" \ 790 "b\3PPC\0" \ 791 "b\2CSZ\0" \ 792 "b\1BNC\0" \ 793 "b\0AC64\0" \ 794 "\0" 795 796 int 797 xhci_init(struct xhci_softc *sc) 798 { 799 bus_size_t bsz; 800 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 801 uint32_t pagesize, config; 802 int i = 0; 803 uint16_t hciversion; 804 uint8_t caplength; 805 806 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 807 808 sc->sc_bus.ub_revision = USBREV_3_0; 809 sc->sc_bus.ub_usedma = true; 810 811 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 812 caplength = XHCI_CAP_CAPLENGTH(cap); 813 hciversion = XHCI_CAP_HCIVERSION(cap); 814 815 if (hciversion < XHCI_HCIVERSION_0_96 || 816 hciversion > XHCI_HCIVERSION_1_0) { 817 aprint_normal_dev(sc->sc_dev, 818 "xHCI version %x.%x not known to be supported\n", 819 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 820 } else { 821 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 822 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 823 } 824 825 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 826 &sc->sc_cbh) != 0) { 827 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 828 return ENOMEM; 829 } 830 831 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 832 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 833 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 834 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 835 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 836 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 837 aprint_debug_dev(sc->sc_dev, 838 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 839 840 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 841 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 842 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 843 844 char sbuf[128]; 845 if (hciversion < XHCI_HCIVERSION_1_0) 846 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 847 else 848 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 849 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 850 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 851 852 /* print PSI and take ownership from BIOS */ 853 xhci_ecp(sc, hcc); 854 855 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 856 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 857 &sc->sc_obh) != 0) { 858 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 859 return ENOMEM; 860 } 861 862 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 863 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 864 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 865 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 866 return ENOMEM; 867 } 868 869 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 870 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 871 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 872 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 873 return ENOMEM; 874 } 875 876 int rv; 877 rv = xhci_hc_reset(sc); 878 if (rv != 0) { 879 return rv; 880 } 881 882 if (sc->sc_vendor_init) 883 sc->sc_vendor_init(sc); 884 885 if (sc->sc_vendor_init) 886 sc->sc_vendor_init(sc); 887 888 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 889 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 890 pagesize = ffs(pagesize); 891 if (pagesize == 0) { 892 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 893 return EIO; 894 } 895 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 896 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 897 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 898 (uint32_t)sc->sc_maxslots); 899 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 900 901 usbd_status err; 902 903 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 904 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 905 if (sc->sc_maxspbuf != 0) { 906 err = usb_allocmem(&sc->sc_bus, 907 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 908 &sc->sc_spbufarray_dma); 909 if (err) { 910 aprint_error_dev(sc->sc_dev, 911 "spbufarray init fail, err %d\n", err); 912 return ENOMEM; 913 } 914 915 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 916 sc->sc_maxspbuf, KM_SLEEP); 917 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 918 for (i = 0; i < sc->sc_maxspbuf; i++) { 919 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 920 /* allocate contexts */ 921 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 922 sc->sc_pgsz, dma); 923 if (err) { 924 aprint_error_dev(sc->sc_dev, 925 "spbufarray_dma init fail, err %d\n", err); 926 rv = ENOMEM; 927 goto bad1; 928 } 929 spbufarray[i] = htole64(DMAADDR(dma, 0)); 930 usb_syncmem(dma, 0, sc->sc_pgsz, 931 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 932 } 933 934 usb_syncmem(&sc->sc_spbufarray_dma, 0, 935 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 936 } 937 938 config = xhci_op_read_4(sc, XHCI_CONFIG); 939 config &= ~0xFF; 940 config |= sc->sc_maxslots & 0xFF; 941 xhci_op_write_4(sc, XHCI_CONFIG, config); 942 943 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 944 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 945 if (err) { 946 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 947 err); 948 rv = ENOMEM; 949 goto bad1; 950 } 951 952 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 953 XHCI_EVENT_RING_SEGMENTS_ALIGN); 954 if (err) { 955 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 956 err); 957 rv = ENOMEM; 958 goto bad2; 959 } 960 961 usb_dma_t *dma; 962 size_t size; 963 size_t align; 964 965 dma = &sc->sc_eventst_dma; 966 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 967 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 968 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 969 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 970 err = usb_allocmem(&sc->sc_bus, size, align, dma); 971 if (err) { 972 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 973 err); 974 rv = ENOMEM; 975 goto bad3; 976 } 977 978 memset(KERNADDR(dma, 0), 0, size); 979 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 980 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 981 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 982 KERNADDR(&sc->sc_eventst_dma, 0), 983 sc->sc_eventst_dma.udma_block->size); 984 985 dma = &sc->sc_dcbaa_dma; 986 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 987 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 988 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 989 err = usb_allocmem(&sc->sc_bus, size, align, dma); 990 if (err) { 991 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 992 rv = ENOMEM; 993 goto bad4; 994 } 995 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 996 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 997 KERNADDR(&sc->sc_dcbaa_dma, 0), 998 sc->sc_dcbaa_dma.udma_block->size); 999 1000 memset(KERNADDR(dma, 0), 0, size); 1001 if (sc->sc_maxspbuf != 0) { 1002 /* 1003 * DCBA entry 0 hold the scratchbuf array pointer. 1004 */ 1005 *(uint64_t *)KERNADDR(dma, 0) = 1006 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1007 } 1008 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1009 1010 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1011 KM_SLEEP); 1012 if (sc->sc_slots == NULL) { 1013 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1014 rv = ENOMEM; 1015 goto bad; 1016 } 1017 1018 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1019 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1020 if (sc->sc_xferpool == NULL) { 1021 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1022 err); 1023 rv = ENOMEM; 1024 goto bad; 1025 } 1026 1027 cv_init(&sc->sc_command_cv, "xhcicmd"); 1028 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1029 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1030 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1031 1032 /* Set up the bus struct. */ 1033 sc->sc_bus.ub_methods = &xhci_bus_methods; 1034 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 1035 1036 struct xhci_erste *erst; 1037 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1038 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1039 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1040 erst[0].erste_3 = htole32(0); 1041 usb_syncmem(&sc->sc_eventst_dma, 0, 1042 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1043 1044 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1045 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1046 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1047 XHCI_ERDP_LO_BUSY); 1048 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1049 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1050 sc->sc_cr.xr_cs); 1051 1052 #if 0 1053 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1054 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1055 #endif 1056 1057 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1058 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1059 /* Intel xhci needs interrupt rate moderated. */ 1060 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1061 else 1062 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1063 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 1064 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1065 1066 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 1067 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1068 xhci_op_read_4(sc, XHCI_USBCMD)); 1069 1070 return 0; 1071 1072 bad: 1073 if (sc->sc_xferpool) { 1074 pool_cache_destroy(sc->sc_xferpool); 1075 sc->sc_xferpool = NULL; 1076 } 1077 1078 if (sc->sc_slots) { 1079 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1080 sc->sc_maxslots); 1081 sc->sc_slots = NULL; 1082 } 1083 1084 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1085 bad4: 1086 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1087 bad3: 1088 xhci_ring_free(sc, &sc->sc_er); 1089 bad2: 1090 xhci_ring_free(sc, &sc->sc_cr); 1091 i = sc->sc_maxspbuf; 1092 bad1: 1093 for (int j = 0; j < i; j++) 1094 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1095 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1096 1097 return rv; 1098 } 1099 1100 int 1101 xhci_intr(void *v) 1102 { 1103 struct xhci_softc * const sc = v; 1104 int ret = 0; 1105 1106 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1107 1108 if (sc == NULL) 1109 return 0; 1110 1111 mutex_spin_enter(&sc->sc_intr_lock); 1112 1113 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1114 goto done; 1115 1116 /* If we get an interrupt while polling, then just ignore it. */ 1117 if (sc->sc_bus.ub_usepolling) { 1118 #ifdef DIAGNOSTIC 1119 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1120 #endif 1121 goto done; 1122 } 1123 1124 ret = xhci_intr1(sc); 1125 done: 1126 mutex_spin_exit(&sc->sc_intr_lock); 1127 return ret; 1128 } 1129 1130 int 1131 xhci_intr1(struct xhci_softc * const sc) 1132 { 1133 uint32_t usbsts; 1134 uint32_t iman; 1135 1136 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1137 1138 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1139 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1140 #if 0 1141 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1142 return 0; 1143 } 1144 #endif 1145 xhci_op_write_4(sc, XHCI_USBSTS, 1146 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1147 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1148 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1149 1150 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1151 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1152 iman |= XHCI_IMAN_INTR_PEND; 1153 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1154 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1155 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1156 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1157 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1158 1159 usb_schedsoftintr(&sc->sc_bus); 1160 1161 return 1; 1162 } 1163 1164 /* 1165 * 3 port speed types used in USB stack 1166 * 1167 * usbdi speed 1168 * definition: USB_SPEED_* in usb.h 1169 * They are used in struct usbd_device in USB stack. 1170 * ioctl interface uses these values too. 1171 * port_status speed 1172 * definition: UPS_*_SPEED in usb.h 1173 * They are used in usb_port_status_t and valid only for USB 2.0. 1174 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1175 * of usb_port_status_ext_t indicates port speed. 1176 * Note that some 3.0 values overlap with 2.0 values. 1177 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1178 * means UPS_LOW_SPEED in HS.) 1179 * port status returned from hub also uses these values. 1180 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1181 * or more. 1182 * xspeed: 1183 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1184 * They are used in only slot context and PORTSC reg of xhci. 1185 * The difference between usbdi speed and xspeed is 1186 * that FS and LS values are swapped. 1187 */ 1188 1189 /* convert usbdi speed to xspeed */ 1190 static int 1191 xhci_speed2xspeed(int speed) 1192 { 1193 switch (speed) { 1194 case USB_SPEED_LOW: return 2; 1195 case USB_SPEED_FULL: return 1; 1196 default: return speed; 1197 } 1198 } 1199 1200 #if 0 1201 /* convert xspeed to usbdi speed */ 1202 static int 1203 xhci_xspeed2speed(int xspeed) 1204 { 1205 switch (xspeed) { 1206 case 1: return USB_SPEED_FULL; 1207 case 2: return USB_SPEED_LOW; 1208 default: return xspeed; 1209 } 1210 } 1211 #endif 1212 1213 /* convert xspeed to port status speed */ 1214 static int 1215 xhci_xspeed2psspeed(int xspeed) 1216 { 1217 switch (xspeed) { 1218 case 0: return 0; 1219 case 1: return UPS_FULL_SPEED; 1220 case 2: return UPS_LOW_SPEED; 1221 case 3: return UPS_HIGH_SPEED; 1222 default: return UPS_OTHER_SPEED; 1223 } 1224 } 1225 1226 /* 1227 * Construct input contexts and issue TRB to open pipe. 1228 */ 1229 static usbd_status 1230 xhci_configure_endpoint(struct usbd_pipe *pipe) 1231 { 1232 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1233 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1234 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1235 struct xhci_trb trb; 1236 usbd_status err; 1237 1238 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1239 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1240 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1241 pipe->up_endpoint->ue_edesc->bmAttributes); 1242 1243 KASSERT(!mutex_owned(&sc->sc_lock)); 1244 1245 /* XXX ensure input context is available? */ 1246 1247 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1248 1249 /* set up context */ 1250 xhci_setup_ctx(pipe); 1251 1252 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1253 sc->sc_ctxsz * 1); 1254 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1255 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1256 1257 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1258 trb.trb_2 = 0; 1259 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1260 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1261 1262 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1263 1264 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1265 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1266 sc->sc_ctxsz * 1); 1267 1268 return err; 1269 } 1270 1271 #if 0 1272 static usbd_status 1273 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1274 { 1275 #ifdef USB_DEBUG 1276 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1277 #endif 1278 1279 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1280 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1281 1282 return USBD_NORMAL_COMPLETION; 1283 } 1284 #endif 1285 1286 /* 4.6.8, 6.4.3.7 */ 1287 static usbd_status 1288 xhci_reset_endpoint(struct usbd_pipe *pipe) 1289 { 1290 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1291 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1292 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1293 struct xhci_trb trb; 1294 usbd_status err; 1295 1296 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1297 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1298 1299 KASSERT(!mutex_owned(&sc->sc_lock)); 1300 1301 trb.trb_0 = 0; 1302 trb.trb_2 = 0; 1303 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1304 XHCI_TRB_3_EP_SET(dci) | 1305 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1306 1307 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1308 1309 return err; 1310 } 1311 1312 /* 1313 * 4.6.9, 6.4.3.8 1314 * Stop execution of TDs on xfer ring. 1315 * Should be called with sc_lock held. 1316 */ 1317 static usbd_status 1318 xhci_stop_endpoint(struct usbd_pipe *pipe) 1319 { 1320 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1321 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1322 struct xhci_trb trb; 1323 usbd_status err; 1324 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1325 1326 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1327 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1328 1329 KASSERT(mutex_owned(&sc->sc_lock)); 1330 1331 trb.trb_0 = 0; 1332 trb.trb_2 = 0; 1333 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1334 XHCI_TRB_3_EP_SET(dci) | 1335 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1336 1337 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1338 1339 return err; 1340 } 1341 1342 /* 1343 * Set TR Dequeue Pointer. 1344 * xHCI 1.1 4.6.10 6.4.3.9 1345 * Purge all of the TRBs on ring and reinitialize ring. 1346 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1347 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1348 * error will be generated. 1349 */ 1350 static usbd_status 1351 xhci_set_dequeue(struct usbd_pipe *pipe) 1352 { 1353 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1354 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1355 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1356 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1357 struct xhci_trb trb; 1358 usbd_status err; 1359 1360 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1361 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1362 1363 xhci_host_dequeue(xr); 1364 1365 /* set DCS */ 1366 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1367 trb.trb_2 = 0; 1368 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1369 XHCI_TRB_3_EP_SET(dci) | 1370 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1371 1372 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1373 1374 return err; 1375 } 1376 1377 /* 1378 * Open new pipe: called from usbd_setup_pipe_flags. 1379 * Fills methods of pipe. 1380 * If pipe is not for ep0, calls configure_endpoint. 1381 */ 1382 static usbd_status 1383 xhci_open(struct usbd_pipe *pipe) 1384 { 1385 struct usbd_device * const dev = pipe->up_dev; 1386 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1387 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1388 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1389 1390 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1391 DPRINTFN(1, "addr %d depth %d port %d speed %d", dev->ud_addr, 1392 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1393 DPRINTFN(1, " dci %u type 0x%02x epaddr 0x%02x attr 0x%02x", 1394 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1395 ed->bmAttributes); 1396 DPRINTFN(1, " mps %u ival %u", UGETW(ed->wMaxPacketSize), ed->bInterval, 1397 0, 0); 1398 1399 if (sc->sc_dying) 1400 return USBD_IOERROR; 1401 1402 /* Root Hub */ 1403 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1404 switch (ed->bEndpointAddress) { 1405 case USB_CONTROL_ENDPOINT: 1406 pipe->up_methods = &roothub_ctrl_methods; 1407 break; 1408 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1409 pipe->up_methods = &xhci_root_intr_methods; 1410 break; 1411 default: 1412 pipe->up_methods = NULL; 1413 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1414 ed->bEndpointAddress, 0, 0, 0); 1415 return USBD_INVAL; 1416 } 1417 return USBD_NORMAL_COMPLETION; 1418 } 1419 1420 switch (xfertype) { 1421 case UE_CONTROL: 1422 pipe->up_methods = &xhci_device_ctrl_methods; 1423 break; 1424 case UE_ISOCHRONOUS: 1425 pipe->up_methods = &xhci_device_isoc_methods; 1426 return USBD_INVAL; 1427 break; 1428 case UE_BULK: 1429 pipe->up_methods = &xhci_device_bulk_methods; 1430 break; 1431 case UE_INTERRUPT: 1432 pipe->up_methods = &xhci_device_intr_methods; 1433 break; 1434 default: 1435 return USBD_IOERROR; 1436 break; 1437 } 1438 1439 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1440 return xhci_configure_endpoint(pipe); 1441 1442 return USBD_NORMAL_COMPLETION; 1443 } 1444 1445 /* 1446 * Closes pipe, called from usbd_kill_pipe via close methods. 1447 * If the endpoint to be closed is ep0, disable_slot. 1448 * Should be called with sc_lock held. 1449 */ 1450 static void 1451 xhci_close_pipe(struct usbd_pipe *pipe) 1452 { 1453 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1454 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1455 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1456 const u_int dci = xhci_ep_get_dci(ed); 1457 struct xhci_trb trb; 1458 uint32_t *cp; 1459 1460 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1461 1462 if (sc->sc_dying) 1463 return; 1464 1465 /* xs is uninitialized before xhci_init_slot */ 1466 if (xs == NULL || xs->xs_idx == 0) 1467 return; 1468 1469 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1470 1471 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1472 KASSERT(mutex_owned(&sc->sc_lock)); 1473 1474 if (pipe->up_dev->ud_depth == 0) 1475 return; 1476 1477 if (dci == XHCI_DCI_EP_CONTROL) { 1478 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1479 xhci_disable_slot(sc, xs->xs_idx); 1480 return; 1481 } 1482 1483 /* 1484 * This may fail in the case that xhci_close_pipe is called after 1485 * xhci_abort_xfer e.g. usbd_kill_pipe. 1486 */ 1487 (void)xhci_stop_endpoint(pipe); 1488 1489 /* 1490 * set appropriate bit to be dropped. 1491 * don't set DC bit to 1, otherwise all endpoints 1492 * would be deconfigured. 1493 */ 1494 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1495 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1496 cp[1] = htole32(0); 1497 1498 /* XXX should be most significant one, not dci? */ 1499 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1500 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1501 1502 /* configure ep context performs an implicit dequeue */ 1503 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 1504 1505 /* sync input contexts before they are read from memory */ 1506 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1507 1508 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1509 trb.trb_2 = 0; 1510 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1511 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1512 1513 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1514 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1515 } 1516 1517 /* 1518 * Abort transfer. 1519 * May be called from softintr context. 1520 */ 1521 static void 1522 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1523 { 1524 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1525 1526 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1527 DPRINTFN(4, "xfer %p pipe %p status %d", 1528 xfer, xfer->ux_pipe, status, 0); 1529 1530 KASSERT(mutex_owned(&sc->sc_lock)); 1531 1532 if (sc->sc_dying) { 1533 /* If we're dying, just do the software part. */ 1534 DPRINTFN(4, "xfer %p dying %u", xfer, xfer->ux_status, 0, 0); 1535 xfer->ux_status = status; 1536 callout_stop(&xfer->ux_callout); 1537 usb_transfer_complete(xfer); 1538 return; 1539 } 1540 1541 /* XXX need more stuff */ 1542 xfer->ux_status = status; 1543 callout_stop(&xfer->ux_callout); 1544 usb_transfer_complete(xfer); 1545 DPRINTFN(14, "end", 0, 0, 0, 0); 1546 1547 KASSERT(mutex_owned(&sc->sc_lock)); 1548 } 1549 1550 static void 1551 xhci_host_dequeue(struct xhci_ring * const xr) 1552 { 1553 /* When dequeueing the controller, update our struct copy too */ 1554 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1555 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1556 BUS_DMASYNC_PREWRITE); 1557 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1558 1559 xr->xr_ep = 0; 1560 xr->xr_cs = 1; 1561 } 1562 1563 /* 1564 * Recover STALLed endpoint. 1565 * xHCI 1.1 sect 4.10.2.1 1566 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1567 * all transfers on transfer ring. 1568 * These are done in thread context asynchronously. 1569 */ 1570 static void 1571 xhci_clear_endpoint_stall_async_task(void *cookie) 1572 { 1573 struct usbd_xfer * const xfer = cookie; 1574 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1575 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1576 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1577 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1578 1579 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1580 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1581 1582 xhci_reset_endpoint(xfer->ux_pipe); 1583 xhci_set_dequeue(xfer->ux_pipe); 1584 1585 mutex_enter(&sc->sc_lock); 1586 tr->is_halted = false; 1587 usb_transfer_complete(xfer); 1588 mutex_exit(&sc->sc_lock); 1589 DPRINTFN(4, "ends", 0, 0, 0, 0); 1590 } 1591 1592 static usbd_status 1593 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1594 { 1595 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1596 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1597 1598 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1599 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1600 1601 if (sc->sc_dying) { 1602 return USBD_IOERROR; 1603 } 1604 1605 usb_init_task(&xp->xp_async_task, 1606 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1607 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1608 DPRINTFN(4, "ends", 0, 0, 0, 0); 1609 1610 return USBD_NORMAL_COMPLETION; 1611 } 1612 1613 /* Process roothub port status/change events and notify to uhub_intr. */ 1614 static void 1615 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1616 { 1617 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1618 uint8_t *p; 1619 1620 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1621 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1622 port, 0, 0); 1623 1624 if (xfer == NULL) 1625 return; 1626 1627 if (port > sc->sc_maxports) 1628 return; 1629 1630 p = xfer->ux_buf; 1631 memset(p, 0, xfer->ux_length); 1632 p[port/NBBY] |= 1 << (port%NBBY); 1633 xfer->ux_actlen = xfer->ux_length; 1634 xfer->ux_status = USBD_NORMAL_COMPLETION; 1635 usb_transfer_complete(xfer); 1636 } 1637 1638 /* Process Transfer Events */ 1639 static void 1640 xhci_event_transfer(struct xhci_softc * const sc, 1641 const struct xhci_trb * const trb) 1642 { 1643 uint64_t trb_0; 1644 uint32_t trb_2, trb_3; 1645 uint8_t trbcode; 1646 u_int slot, dci; 1647 struct xhci_slot *xs; 1648 struct xhci_ring *xr; 1649 struct xhci_xfer *xx; 1650 struct usbd_xfer *xfer; 1651 usbd_status err; 1652 1653 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1654 1655 trb_0 = le64toh(trb->trb_0); 1656 trb_2 = le32toh(trb->trb_2); 1657 trb_3 = le32toh(trb->trb_3); 1658 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1659 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1660 dci = XHCI_TRB_3_EP_GET(trb_3); 1661 xs = &sc->sc_slots[slot]; 1662 xr = &xs->xs_ep[dci].xe_tr; 1663 1664 /* sanity check */ 1665 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1666 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1667 1668 int idx = 0; 1669 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1670 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1671 DPRINTFN(0, "invalid trb_0 0x%"PRIx64, trb_0, 0, 0, 0); 1672 return; 1673 } 1674 xx = xr->xr_cookies[idx]; 1675 1676 /* 1677 * If endpoint is stopped between TDs, TRB pointer points at 1678 * next TRB, however, it is not put yet or is a garbage TRB. 1679 * That's why xr_cookies may be NULL or look like broken. 1680 * Note: this ev happens only when hciversion >= 1.0 or 1681 * hciversion == 0.96 and FSE of hcc1 is set. 1682 */ 1683 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1684 DPRINTFN(1, "Ignore #%u: cookie %p cc %u dci %u", 1685 idx, xx, trbcode, dci); 1686 DPRINTFN(1, " orig TRB %"PRIx64" type %u", trb_0, 1687 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1688 0, 0); 1689 } 1690 } else { 1691 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1692 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1693 } 1694 /* XXX this may not happen */ 1695 if (xx == NULL) { 1696 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1697 return; 1698 } 1699 xfer = &xx->xx_xfer; 1700 /* XXX this may happen when detaching */ 1701 if (xfer == NULL) { 1702 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1703 xx, trb_0, 0, 0); 1704 return; 1705 } 1706 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1707 /* XXX I dunno why this happens */ 1708 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1709 1710 if (!xfer->ux_pipe->up_repeat && 1711 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1712 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1713 return; 1714 } 1715 1716 /* 4.11.5.2 Event Data TRB */ 1717 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1718 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1719 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1720 if ((trb_0 & 0x3) == 0x3) { 1721 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1722 } 1723 } 1724 1725 switch (trbcode) { 1726 case XHCI_TRB_ERROR_SHORT_PKT: 1727 case XHCI_TRB_ERROR_SUCCESS: 1728 /* 1729 * A ctrl transfer generates two events if it has a Data stage. 1730 * After a successful Data stage we cannot call call 1731 * usb_transfer_complete - this can only happen after the Data 1732 * stage. 1733 * 1734 * Note: Data and Status stage events point at same xfer. 1735 * ux_actlen and ux_dmabuf will be passed to 1736 * usb_transfer_complete after the Status stage event. 1737 * 1738 * It can be distingished which stage generates the event: 1739 * + by checking least 3 bits of trb_0 if ED==1. 1740 * (see xhci_device_ctrl_start). 1741 * + by checking the type of original TRB if ED==0. 1742 * 1743 * In addition, intr, bulk, and isoc transfer currently 1744 * consists of single TD, so the "skip" is not needed. 1745 * ctrl xfer uses EVENT_DATA, and others do not. 1746 * Thus driver can switch the flow by checking ED bit. 1747 */ 1748 xfer->ux_actlen = 1749 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1750 err = USBD_NORMAL_COMPLETION; 1751 break; 1752 case XHCI_TRB_ERROR_STALL: 1753 case XHCI_TRB_ERROR_BABBLE: 1754 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1755 xr->is_halted = true; 1756 err = USBD_STALLED; 1757 /* 1758 * Stalled endpoints can be recoverd by issuing 1759 * command TRB TYPE_RESET_EP on xHCI instead of 1760 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1761 * on the endpoint. However, this function may be 1762 * called from softint context (e.g. from umass), 1763 * in that case driver gets KASSERT in cv_timedwait 1764 * in xhci_do_command. 1765 * To avoid this, this runs reset_endpoint and 1766 * usb_transfer_complete in usb task thread 1767 * asynchronously (and then umass issues clear 1768 * UF_ENDPOINT_HALT). 1769 */ 1770 xfer->ux_status = err; 1771 xhci_clear_endpoint_stall_async(xfer); 1772 return; 1773 default: 1774 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1775 err = USBD_IOERROR; 1776 break; 1777 } 1778 xfer->ux_status = err; 1779 1780 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1781 if ((trb_0 & 0x3) == 0x0) { 1782 callout_stop(&xfer->ux_callout); 1783 usb_transfer_complete(xfer); 1784 } 1785 } else { 1786 callout_stop(&xfer->ux_callout); 1787 usb_transfer_complete(xfer); 1788 } 1789 } 1790 1791 /* Process Command complete events */ 1792 static void 1793 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 1794 { 1795 uint64_t trb_0; 1796 uint32_t trb_2, trb_3; 1797 1798 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1799 1800 KASSERT(mutex_owned(&sc->sc_lock)); 1801 1802 trb_0 = le64toh(trb->trb_0); 1803 trb_2 = le32toh(trb->trb_2); 1804 trb_3 = le32toh(trb->trb_3); 1805 1806 if (trb_0 == sc->sc_command_addr) { 1807 sc->sc_resultpending = false; 1808 1809 sc->sc_result_trb.trb_0 = trb_0; 1810 sc->sc_result_trb.trb_2 = trb_2; 1811 sc->sc_result_trb.trb_3 = trb_3; 1812 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1813 XHCI_TRB_ERROR_SUCCESS) { 1814 DPRINTFN(1, "command completion " 1815 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1816 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1817 } 1818 cv_signal(&sc->sc_command_cv); 1819 } else { 1820 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 1821 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1822 trb_2, trb_3); 1823 } 1824 } 1825 1826 /* 1827 * Process events. 1828 * called from xhci_softintr 1829 */ 1830 static void 1831 xhci_handle_event(struct xhci_softc * const sc, 1832 const struct xhci_trb * const trb) 1833 { 1834 uint64_t trb_0; 1835 uint32_t trb_2, trb_3; 1836 1837 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1838 1839 trb_0 = le64toh(trb->trb_0); 1840 trb_2 = le32toh(trb->trb_2); 1841 trb_3 = le32toh(trb->trb_3); 1842 1843 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1844 trb, trb_0, trb_2, trb_3); 1845 1846 /* 1847 * 4.11.3.1, 6.4.2.1 1848 * TRB Pointer is invalid for these completion codes. 1849 */ 1850 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 1851 case XHCI_TRB_ERROR_RING_UNDERRUN: 1852 case XHCI_TRB_ERROR_RING_OVERRUN: 1853 case XHCI_TRB_ERROR_VF_RING_FULL: 1854 return; 1855 default: 1856 if (trb_0 == 0) { 1857 return; 1858 } 1859 break; 1860 } 1861 1862 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 1863 case XHCI_TRB_EVENT_TRANSFER: 1864 xhci_event_transfer(sc, trb); 1865 break; 1866 case XHCI_TRB_EVENT_CMD_COMPLETE: 1867 xhci_event_cmd(sc, trb); 1868 break; 1869 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1870 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1871 break; 1872 default: 1873 break; 1874 } 1875 } 1876 1877 static void 1878 xhci_softintr(void *v) 1879 { 1880 struct usbd_bus * const bus = v; 1881 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1882 struct xhci_ring * const er = &sc->sc_er; 1883 struct xhci_trb *trb; 1884 int i, j, k; 1885 1886 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1887 1888 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1889 1890 i = er->xr_ep; 1891 j = er->xr_cs; 1892 1893 DPRINTFN(16, "er: xr_ep %d xr_cs %d", i, j, 0, 0); 1894 1895 while (1) { 1896 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 1897 BUS_DMASYNC_POSTREAD); 1898 trb = &er->xr_trb[i]; 1899 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1900 1901 if (j != k) 1902 break; 1903 1904 xhci_handle_event(sc, trb); 1905 1906 i++; 1907 if (i == er->xr_ntrb) { 1908 i = 0; 1909 j ^= 1; 1910 } 1911 } 1912 1913 er->xr_ep = i; 1914 er->xr_cs = j; 1915 1916 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 1917 XHCI_ERDP_LO_BUSY); 1918 1919 DPRINTFN(16, "ends", 0, 0, 0, 0); 1920 1921 return; 1922 } 1923 1924 static void 1925 xhci_poll(struct usbd_bus *bus) 1926 { 1927 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1928 1929 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1930 1931 mutex_spin_enter(&sc->sc_intr_lock); 1932 xhci_intr1(sc); 1933 mutex_spin_exit(&sc->sc_intr_lock); 1934 1935 return; 1936 } 1937 1938 static struct usbd_xfer * 1939 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 1940 { 1941 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1942 struct usbd_xfer *xfer; 1943 1944 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1945 1946 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1947 if (xfer != NULL) { 1948 memset(xfer, 0, sizeof(struct xhci_xfer)); 1949 #ifdef DIAGNOSTIC 1950 xfer->ux_state = XFER_BUSY; 1951 #endif 1952 } 1953 1954 return xfer; 1955 } 1956 1957 static void 1958 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1959 { 1960 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1961 1962 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1963 1964 #ifdef DIAGNOSTIC 1965 if (xfer->ux_state != XFER_BUSY) { 1966 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 1967 xfer, xfer->ux_state, 0, 0); 1968 } 1969 xfer->ux_state = XFER_FREE; 1970 #endif 1971 pool_cache_put(sc->sc_xferpool, xfer); 1972 } 1973 1974 static void 1975 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1976 { 1977 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1978 1979 *lock = &sc->sc_lock; 1980 } 1981 1982 extern uint32_t usb_cookie_no; 1983 1984 /* 1985 * xHCI 4.3 1986 * Called when uhub_explore finds a new device (via usbd_new_device). 1987 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 1988 * This function does: 1989 * Allocate and construct dev structure of default endpoint (ep0). 1990 * Allocate and open pipe of ep0. 1991 * Enable slot and initialize slot context. 1992 * Set Address. 1993 * Read initial device descriptor. 1994 * Determine initial MaxPacketSize (mps) by speed. 1995 * Read full device descriptor. 1996 * Register this device. 1997 * Finally state of device transitions ADDRESSED. 1998 */ 1999 static usbd_status 2000 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2001 int speed, int port, struct usbd_port *up) 2002 { 2003 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2004 struct usbd_device *dev; 2005 usbd_status err; 2006 usb_device_descriptor_t *dd; 2007 struct xhci_slot *xs; 2008 uint32_t *cp; 2009 2010 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2011 DPRINTFN(4, "port %u depth %u speed %u up %p", port, depth, speed, up); 2012 2013 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2014 if (dev == NULL) 2015 return USBD_NOMEM; 2016 2017 dev->ud_bus = bus; 2018 dev->ud_quirks = &usbd_no_quirk; 2019 dev->ud_addr = 0; 2020 dev->ud_ddesc.bMaxPacketSize = 0; 2021 dev->ud_depth = depth; 2022 dev->ud_powersrc = up; 2023 dev->ud_myhub = up->up_parent; 2024 dev->ud_speed = speed; 2025 dev->ud_langid = USBD_NOLANG; 2026 dev->ud_cookie.cookie = ++usb_cookie_no; 2027 2028 /* Set up default endpoint handle. */ 2029 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2030 /* doesn't matter, just don't let it uninitialized */ 2031 dev->ud_ep0.ue_toggle = 0; 2032 2033 /* Set up default endpoint descriptor. */ 2034 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2035 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2036 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2037 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2038 dev->ud_ep0desc.bInterval = 0; 2039 2040 /* 4.3, 4.8.2.1 */ 2041 switch (speed) { 2042 case USB_SPEED_SUPER: 2043 case USB_SPEED_SUPER_PLUS: 2044 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2045 break; 2046 case USB_SPEED_FULL: 2047 /* XXX using 64 as initial mps of ep0 in FS */ 2048 case USB_SPEED_HIGH: 2049 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2050 break; 2051 case USB_SPEED_LOW: 2052 default: 2053 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2054 break; 2055 } 2056 2057 up->up_dev = dev; 2058 2059 /* Establish the default pipe. */ 2060 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2061 &dev->ud_pipe0); 2062 if (err) { 2063 goto bad; 2064 } 2065 2066 dd = &dev->ud_ddesc; 2067 2068 if ((depth == 0) && (port == 0)) { 2069 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2070 bus->ub_devices[dev->ud_addr] = dev; 2071 err = usbd_get_initial_ddesc(dev, dd); 2072 if (err) 2073 goto bad; 2074 err = usbd_reload_device_desc(dev); 2075 if (err) 2076 goto bad; 2077 } else { 2078 uint8_t slot = 0; 2079 2080 /* 4.3.2 */ 2081 err = xhci_enable_slot(sc, &slot); 2082 if (err) 2083 goto bad; 2084 2085 xs = &sc->sc_slots[slot]; 2086 dev->ud_hcpriv = xs; 2087 2088 /* 4.3.3 initialize slot structure */ 2089 err = xhci_init_slot(dev, slot); 2090 if (err) { 2091 dev->ud_hcpriv = NULL; 2092 /* 2093 * We have to disable_slot here because 2094 * xs->xs_idx == 0 when xhci_init_slot fails, 2095 * in that case usbd_remove_dev won't work. 2096 */ 2097 mutex_enter(&sc->sc_lock); 2098 xhci_disable_slot(sc, slot); 2099 mutex_exit(&sc->sc_lock); 2100 goto bad; 2101 } 2102 2103 /* 4.3.4 Address Assignment */ 2104 err = xhci_set_address(dev, slot, false); 2105 if (err) 2106 goto bad; 2107 2108 /* Allow device time to set new address */ 2109 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2110 2111 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2112 //hexdump("slot context", cp, sc->sc_ctxsz); 2113 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2114 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2115 /* XXX ensure we know when the hardware does something 2116 we can't yet cope with */ 2117 KASSERT(addr >= 1 && addr <= 127); 2118 dev->ud_addr = addr; 2119 /* XXX dev->ud_addr not necessarily unique on bus */ 2120 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2121 bus->ub_devices[dev->ud_addr] = dev; 2122 2123 err = usbd_get_initial_ddesc(dev, dd); 2124 if (err) 2125 goto bad; 2126 2127 /* 4.8.2.1 */ 2128 if (USB_IS_SS(speed)) { 2129 if (dd->bMaxPacketSize != 9) { 2130 printf("%s: invalid mps 2^%u for SS ep0," 2131 " using 512\n", 2132 device_xname(sc->sc_dev), 2133 dd->bMaxPacketSize); 2134 dd->bMaxPacketSize = 9; 2135 } 2136 USETW(dev->ud_ep0desc.wMaxPacketSize, 2137 (1 << dd->bMaxPacketSize)); 2138 } else 2139 USETW(dev->ud_ep0desc.wMaxPacketSize, 2140 dd->bMaxPacketSize); 2141 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2142 xhci_update_ep0_mps(sc, xs, 2143 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2144 2145 err = usbd_reload_device_desc(dev); 2146 if (err) 2147 goto bad; 2148 } 2149 2150 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2151 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2152 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2153 dd->bDeviceClass, dd->bDeviceSubClass, 2154 dd->bDeviceProtocol, 0); 2155 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2156 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2157 dev->ud_speed); 2158 2159 usbd_get_device_strings(dev); 2160 2161 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2162 2163 if ((depth == 0) && (port == 0)) { 2164 usbd_attach_roothub(parent, dev); 2165 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2166 return USBD_NORMAL_COMPLETION; 2167 } 2168 2169 2170 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2171 bad: 2172 if (err != USBD_NORMAL_COMPLETION) { 2173 usbd_remove_device(dev, up); 2174 } 2175 2176 return err; 2177 } 2178 2179 static usbd_status 2180 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2181 size_t ntrb, size_t align) 2182 { 2183 usbd_status err; 2184 size_t size = ntrb * XHCI_TRB_SIZE; 2185 2186 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2187 2188 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2189 if (err) 2190 return err; 2191 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2192 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2193 xr->xr_trb = xhci_ring_trbv(xr, 0); 2194 xr->xr_ntrb = ntrb; 2195 xr->is_halted = false; 2196 xhci_host_dequeue(xr); 2197 2198 return USBD_NORMAL_COMPLETION; 2199 } 2200 2201 static void 2202 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2203 { 2204 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2205 mutex_destroy(&xr->xr_lock); 2206 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2207 } 2208 2209 static void 2210 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2211 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2212 { 2213 size_t i; 2214 u_int ri; 2215 u_int cs; 2216 uint64_t parameter; 2217 uint32_t status; 2218 uint32_t control; 2219 2220 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2221 2222 KASSERT(ntrbs <= XHCI_XFER_NTRB); 2223 for (i = 0; i < ntrbs; i++) { 2224 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2225 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2226 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2227 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2228 XHCI_TRB_TYPE_LINK); 2229 } 2230 2231 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2232 2233 ri = xr->xr_ep; 2234 cs = xr->xr_cs; 2235 2236 /* 2237 * Although the xhci hardware can do scatter/gather dma from 2238 * arbitrary sized buffers, there is a non-obvious restriction 2239 * that a LINK trb is only allowed at the end of a burst of 2240 * transfers - which might be 16kB. 2241 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2242 * The simple solution is not to allow a LINK trb in the middle 2243 * of anything - as here. 2244 * XXX: (dsl) There are xhci controllers out there (eg some made by 2245 * ASMedia) that seem to lock up if they process a LINK trb but 2246 * cannot process the linked-to trb yet. 2247 * The code should write the 'cycle' bit on the link trb AFTER 2248 * adding the other trb. 2249 */ 2250 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2251 parameter = xhci_ring_trbp(xr, 0); 2252 status = 0; 2253 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2254 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2255 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2256 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2257 BUS_DMASYNC_PREWRITE); 2258 xr->xr_cookies[ri] = NULL; 2259 xr->xr_ep = 0; 2260 xr->xr_cs ^= 1; 2261 ri = xr->xr_ep; 2262 cs = xr->xr_cs; 2263 } 2264 2265 ri++; 2266 2267 /* Write any subsequent TRB first */ 2268 for (i = 1; i < ntrbs; i++) { 2269 parameter = trbs[i].trb_0; 2270 status = trbs[i].trb_2; 2271 control = trbs[i].trb_3; 2272 2273 if (cs) { 2274 control |= XHCI_TRB_3_CYCLE_BIT; 2275 } else { 2276 control &= ~XHCI_TRB_3_CYCLE_BIT; 2277 } 2278 2279 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2280 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2281 BUS_DMASYNC_PREWRITE); 2282 xr->xr_cookies[ri] = cookie; 2283 ri++; 2284 } 2285 2286 /* Write the first TRB last */ 2287 i = 0; 2288 parameter = trbs[i].trb_0; 2289 status = trbs[i].trb_2; 2290 control = trbs[i].trb_3; 2291 2292 if (xr->xr_cs) { 2293 control |= XHCI_TRB_3_CYCLE_BIT; 2294 } else { 2295 control &= ~XHCI_TRB_3_CYCLE_BIT; 2296 } 2297 2298 xhci_trb_put(&xr->xr_trb[xr->xr_ep], parameter, status, control); 2299 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * xr->xr_ep, XHCI_TRB_SIZE * 1, 2300 BUS_DMASYNC_PREWRITE); 2301 xr->xr_cookies[xr->xr_ep] = cookie; 2302 2303 xr->xr_ep = ri; 2304 xr->xr_cs = cs; 2305 2306 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2307 } 2308 2309 /* 2310 * Stop execution commands, purge all commands on command ring, and 2311 * rewind dequeue pointer. 2312 */ 2313 static void 2314 xhci_abort_command(struct xhci_softc *sc) 2315 { 2316 struct xhci_ring * const cr = &sc->sc_cr; 2317 uint64_t crcr; 2318 int i; 2319 2320 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2321 DPRINTFN(14, "command %#"PRIx64" timeout, aborting", 2322 sc->sc_command_addr, 0, 0, 0); 2323 2324 mutex_enter(&cr->xr_lock); 2325 2326 /* 4.6.1.2 Aborting a Command */ 2327 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2328 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2329 2330 for (i = 0; i < 500; i++) { 2331 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2332 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2333 break; 2334 usb_delay_ms(&sc->sc_bus, 1); 2335 } 2336 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2337 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2338 /* reset HC here? */ 2339 } 2340 2341 /* reset command ring dequeue pointer */ 2342 cr->xr_ep = 0; 2343 cr->xr_cs = 1; 2344 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2345 2346 mutex_exit(&cr->xr_lock); 2347 } 2348 2349 /* 2350 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2351 * Command completion is notified by cv_signal from xhci_event_cmd() 2352 * (called from xhci_softint), or timed-out. 2353 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2354 * then do_command examines it. 2355 */ 2356 static usbd_status 2357 xhci_do_command_locked(struct xhci_softc * const sc, 2358 struct xhci_trb * const trb, int timeout) 2359 { 2360 struct xhci_ring * const cr = &sc->sc_cr; 2361 usbd_status err; 2362 2363 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2364 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2365 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2366 2367 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2368 KASSERT(mutex_owned(&sc->sc_lock)); 2369 2370 while (sc->sc_command_addr != 0) 2371 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 2372 2373 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2374 sc->sc_resultpending = true; 2375 2376 mutex_enter(&cr->xr_lock); 2377 xhci_ring_put(sc, cr, NULL, trb, 1); 2378 mutex_exit(&cr->xr_lock); 2379 2380 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2381 2382 while (sc->sc_resultpending) { 2383 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2384 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2385 xhci_abort_command(sc); 2386 err = USBD_TIMEOUT; 2387 goto timedout; 2388 } 2389 } 2390 2391 trb->trb_0 = sc->sc_result_trb.trb_0; 2392 trb->trb_2 = sc->sc_result_trb.trb_2; 2393 trb->trb_3 = sc->sc_result_trb.trb_3; 2394 2395 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2396 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2397 2398 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2399 case XHCI_TRB_ERROR_SUCCESS: 2400 err = USBD_NORMAL_COMPLETION; 2401 break; 2402 default: 2403 case 192 ... 223: 2404 err = USBD_IOERROR; 2405 break; 2406 case 224 ... 255: 2407 err = USBD_NORMAL_COMPLETION; 2408 break; 2409 } 2410 2411 timedout: 2412 sc->sc_resultpending = false; 2413 sc->sc_command_addr = 0; 2414 cv_broadcast(&sc->sc_cmdbusy_cv); 2415 2416 return err; 2417 } 2418 2419 static usbd_status 2420 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2421 int timeout) 2422 { 2423 2424 mutex_enter(&sc->sc_lock); 2425 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2426 mutex_exit(&sc->sc_lock); 2427 2428 return ret; 2429 } 2430 2431 static usbd_status 2432 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2433 { 2434 struct xhci_trb trb; 2435 usbd_status err; 2436 2437 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2438 2439 trb.trb_0 = 0; 2440 trb.trb_2 = 0; 2441 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2442 2443 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2444 if (err != USBD_NORMAL_COMPLETION) { 2445 return err; 2446 } 2447 2448 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2449 2450 return err; 2451 } 2452 2453 /* 2454 * xHCI 4.6.4 2455 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2456 * All endpoints in the slot should be stopped. 2457 * Should be called with sc_lock held. 2458 */ 2459 static usbd_status 2460 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2461 { 2462 struct xhci_trb trb; 2463 struct xhci_slot *xs; 2464 usbd_status err; 2465 2466 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2467 2468 if (sc->sc_dying) 2469 return USBD_IOERROR; 2470 2471 trb.trb_0 = 0; 2472 trb.trb_2 = 0; 2473 trb.trb_3 = htole32( 2474 XHCI_TRB_3_SLOT_SET(slot) | 2475 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2476 2477 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2478 2479 if (!err) { 2480 xs = &sc->sc_slots[slot]; 2481 if (xs->xs_idx != 0) { 2482 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2483 xhci_set_dcba(sc, 0, slot); 2484 memset(xs, 0, sizeof(*xs)); 2485 } 2486 } 2487 2488 return err; 2489 } 2490 2491 /* 2492 * Set address of device and transition slot state from ENABLED to ADDRESSED 2493 * if Block Setaddress Request (BSR) is false. 2494 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2495 * see xHCI 1.1 4.5.3, 3.3.4 2496 * Should be called without sc_lock held. 2497 */ 2498 static usbd_status 2499 xhci_address_device(struct xhci_softc * const sc, 2500 uint64_t icp, uint8_t slot_id, bool bsr) 2501 { 2502 struct xhci_trb trb; 2503 usbd_status err; 2504 2505 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2506 2507 trb.trb_0 = icp; 2508 trb.trb_2 = 0; 2509 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2510 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2511 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2512 2513 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2514 2515 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2516 err = USBD_NO_ADDR; 2517 2518 return err; 2519 } 2520 2521 static usbd_status 2522 xhci_update_ep0_mps(struct xhci_softc * const sc, 2523 struct xhci_slot * const xs, u_int mps) 2524 { 2525 struct xhci_trb trb; 2526 usbd_status err; 2527 uint32_t * cp; 2528 2529 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2530 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2531 2532 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2533 cp[0] = htole32(0); 2534 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2535 2536 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2537 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2538 2539 /* sync input contexts before they are read from memory */ 2540 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2541 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2542 sc->sc_ctxsz * 4); 2543 2544 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2545 trb.trb_2 = 0; 2546 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2547 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2548 2549 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2550 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2551 return err; 2552 } 2553 2554 static void 2555 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2556 { 2557 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2558 2559 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2560 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2561 &dcbaa[si], dcba, si, 0); 2562 2563 dcbaa[si] = htole64(dcba); 2564 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2565 BUS_DMASYNC_PREWRITE); 2566 } 2567 2568 /* 2569 * Allocate device and input context DMA buffer, and 2570 * TRB DMA buffer for each endpoint. 2571 */ 2572 static usbd_status 2573 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2574 { 2575 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2576 struct xhci_slot *xs; 2577 usbd_status err; 2578 u_int dci; 2579 2580 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2581 DPRINTFN(4, "slot %u", slot, 0, 0, 0); 2582 2583 xs = &sc->sc_slots[slot]; 2584 2585 /* allocate contexts */ 2586 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2587 &xs->xs_dc_dma); 2588 if (err) 2589 return err; 2590 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2591 2592 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2593 &xs->xs_ic_dma); 2594 if (err) 2595 goto bad1; 2596 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2597 2598 for (dci = 0; dci < 32; dci++) { 2599 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2600 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2601 if (dci == XHCI_DCI_SLOT) 2602 continue; 2603 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2604 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2605 if (err) { 2606 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2607 goto bad2; 2608 } 2609 } 2610 2611 bad2: 2612 if (err == USBD_NORMAL_COMPLETION) { 2613 xs->xs_idx = slot; 2614 } else { 2615 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2616 } 2617 2618 return err; 2619 2620 bad1: 2621 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2622 xs->xs_idx = 0; 2623 return err; 2624 } 2625 2626 static void 2627 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2628 int end_dci) 2629 { 2630 u_int dci; 2631 2632 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2633 DPRINTFN(4, "slot %u start %u end %u", xs->xs_idx, start_dci, end_dci, 2634 0); 2635 2636 for (dci = start_dci; dci < end_dci; dci++) { 2637 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2638 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2639 } 2640 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2641 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2642 xs->xs_idx = 0; 2643 } 2644 2645 /* 2646 * Setup slot context, set Device Context Base Address, and issue 2647 * Set Address Device command. 2648 */ 2649 static usbd_status 2650 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 2651 { 2652 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2653 struct xhci_slot *xs; 2654 usbd_status err; 2655 2656 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2657 DPRINTFN(4, "slot %u bsr %u", slot, bsr, 0, 0); 2658 2659 xs = &sc->sc_slots[slot]; 2660 2661 xhci_setup_ctx(dev->ud_pipe0); 2662 2663 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2664 sc->sc_ctxsz * 3); 2665 2666 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2667 2668 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 2669 2670 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2671 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2672 sc->sc_ctxsz * 2); 2673 2674 return err; 2675 } 2676 2677 /* 2678 * 4.8.2, 6.2.3.2 2679 * construct slot/endpoint context parameters and do syncmem 2680 */ 2681 static void 2682 xhci_setup_ctx(struct usbd_pipe *pipe) 2683 { 2684 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2685 struct usbd_device *dev = pipe->up_dev; 2686 struct xhci_slot * const xs = dev->ud_hcpriv; 2687 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2688 const u_int dci = xhci_ep_get_dci(ed); 2689 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2690 uint32_t *cp; 2691 uint16_t mps = UGETW(ed->wMaxPacketSize); 2692 uint8_t speed = dev->ud_speed; 2693 uint8_t ival = ed->bInterval; 2694 2695 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2696 DPRINTFN(4, "pipe %p: slot %u dci %u speed %u", pipe, xs->xs_idx, dci, 2697 speed); 2698 2699 /* set up initial input control context */ 2700 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2701 cp[0] = htole32(0); 2702 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 2703 if (dci == XHCI_DCI_EP_CONTROL) 2704 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2705 cp[7] = htole32(0); 2706 2707 /* set up input slot context */ 2708 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2709 cp[0] = 2710 XHCI_SCTX_0_CTX_NUM_SET(dci) | 2711 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 2712 cp[1] = 0; 2713 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2714 cp[3] = 0; 2715 xhci_setup_route(pipe, cp); 2716 xhci_setup_tthub(pipe, cp); 2717 2718 cp[0] = htole32(cp[0]); 2719 cp[1] = htole32(cp[1]); 2720 cp[2] = htole32(cp[2]); 2721 cp[3] = htole32(cp[3]); 2722 2723 /* set up input endpoint context */ 2724 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 2725 cp[0] = 2726 XHCI_EPCTX_0_EPSTATE_SET(0) | 2727 XHCI_EPCTX_0_MULT_SET(0) | 2728 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2729 XHCI_EPCTX_0_LSA_SET(0) | 2730 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 2731 cp[1] = 2732 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 2733 XHCI_EPCTX_1_HID_SET(0) | 2734 XHCI_EPCTX_1_MAXB_SET(0); 2735 2736 if (xfertype != UE_ISOCHRONOUS) 2737 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 2738 2739 if (xfertype == UE_CONTROL) 2740 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 2741 else if (USB_IS_SS(speed)) 2742 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 2743 else 2744 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 2745 2746 xhci_setup_maxburst(pipe, cp); 2747 2748 switch (xfertype) { 2749 case UE_CONTROL: 2750 break; 2751 case UE_BULK: 2752 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 2753 break; 2754 case UE_INTERRUPT: 2755 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 2756 ival = pipe->up_interval; 2757 2758 ival = xhci_bival2ival(ival, speed); 2759 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 2760 break; 2761 case UE_ISOCHRONOUS: 2762 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 2763 ival = pipe->up_interval; 2764 2765 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 2766 if (speed == USB_SPEED_FULL) 2767 ival += 3; /* 1ms -> 125us */ 2768 ival--; 2769 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 2770 break; 2771 default: 2772 break; 2773 } 2774 DPRINTFN(4, "setting ival %u MaxBurst %#x", 2775 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 2776 2777 /* rewind TR dequeue pointer in xHC */ 2778 /* can't use xhci_ep_get_dci() yet? */ 2779 *(uint64_t *)(&cp[2]) = htole64( 2780 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 2781 XHCI_EPCTX_2_DCS_SET(1)); 2782 2783 cp[0] = htole32(cp[0]); 2784 cp[1] = htole32(cp[1]); 2785 cp[4] = htole32(cp[4]); 2786 2787 /* rewind TR dequeue pointer in driver */ 2788 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 2789 mutex_enter(&xr->xr_lock); 2790 xhci_host_dequeue(xr); 2791 mutex_exit(&xr->xr_lock); 2792 2793 /* sync input contexts before they are read from memory */ 2794 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2795 } 2796 2797 /* 2798 * Setup route string and roothub port of given device for slot context 2799 */ 2800 static void 2801 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 2802 { 2803 struct usbd_device *dev = pipe->up_dev; 2804 struct usbd_port *up = dev->ud_powersrc; 2805 struct usbd_device *hub; 2806 struct usbd_device *adev; 2807 uint8_t rhport = 0; 2808 uint32_t route = 0; 2809 2810 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2811 2812 /* Locate root hub port and Determine route string */ 2813 /* 4.3.3 route string does not include roothub port */ 2814 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2815 uint32_t dep; 2816 2817 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2818 hub, hub->ud_depth, hub->ud_powersrc, 2819 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2820 2821 if (hub->ud_powersrc == NULL) 2822 break; 2823 dep = hub->ud_depth; 2824 if (dep == 0) 2825 break; 2826 rhport = hub->ud_powersrc->up_portno; 2827 if (dep > USB_HUB_MAX_DEPTH) 2828 continue; 2829 2830 route |= 2831 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2832 << ((dep - 1) * 4); 2833 } 2834 route = route >> 4; 2835 DPRINTFN(4, "rhport %u Route %05x hub %p", rhport, route, hub, 0); 2836 2837 /* Locate port on upstream high speed hub */ 2838 for (adev = dev, hub = up->up_parent; 2839 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2840 adev = hub, hub = hub->ud_myhub) 2841 ; 2842 if (hub) { 2843 int p; 2844 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2845 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2846 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2847 goto found; 2848 } 2849 } 2850 panic("xhci_setup_route: cannot find HS port"); 2851 found: 2852 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2853 } else { 2854 dev->ud_myhsport = NULL; 2855 } 2856 2857 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 2858 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(rhport); 2859 } 2860 2861 /* 2862 * Setup whether device is hub, whether device uses MTT, and 2863 * TT informations if it uses MTT. 2864 */ 2865 static void 2866 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 2867 { 2868 struct usbd_device *dev = pipe->up_dev; 2869 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 2870 uint32_t speed = dev->ud_speed; 2871 uint8_t tthubslot, ttportnum; 2872 bool ishub; 2873 bool usemtt; 2874 2875 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2876 2877 /* 2878 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 2879 * tthubslot: 2880 * This is the slot ID of parent HS hub 2881 * if LS/FS device is connected && connected through HS hub. 2882 * This is 0 if device is not LS/FS device || 2883 * parent hub is not HS hub || 2884 * attached to root hub. 2885 * ttportnum: 2886 * This is the downstream facing port of parent HS hub 2887 * if LS/FS device is connected. 2888 * This is 0 if device is not LS/FS device || 2889 * parent hub is not HS hub || 2890 * attached to root hub. 2891 */ 2892 if (dev->ud_myhsport != NULL && 2893 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 2894 (dev->ud_myhub != NULL && 2895 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 2896 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 2897 ttportnum = dev->ud_myhsport->up_portno; 2898 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 2899 } else { 2900 ttportnum = 0; 2901 tthubslot = 0; 2902 } 2903 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 2904 dev->ud_myhsport, ttportnum, tthubslot, 0); 2905 2906 /* ishub is valid after reading UDESC_DEVICE */ 2907 ishub = (dd->bDeviceClass == UDCLASS_HUB); 2908 2909 /* dev->ud_hub is valid after reading UDESC_HUB */ 2910 if (ishub && dev->ud_hub) { 2911 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 2912 uint8_t ttt = 2913 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 2914 2915 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 2916 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 2917 DPRINTFN(4, "nports=%d ttt=%d", hd->bNbrPorts, ttt, 0, 0); 2918 } 2919 2920 #define IS_TTHUB(dd) \ 2921 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 2922 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 2923 2924 /* 2925 * MTT flag is set if 2926 * 1. this is HS hub && MTT is enabled 2927 * or 2928 * 2. this is not hub && this is LS or FS device && 2929 * MTT of parent HS hub (and its parent, too) is enabled 2930 */ 2931 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 2932 usemtt = true; 2933 else if (!ishub && 2934 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 2935 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 2936 (dev->ud_myhub != NULL && 2937 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 2938 dev->ud_myhsport != NULL && 2939 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 2940 usemtt = true; 2941 else 2942 usemtt = false; 2943 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 2944 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 2945 2946 #undef IS_TTHUB 2947 2948 cp[0] |= 2949 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 2950 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 2951 cp[2] |= 2952 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 2953 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 2954 } 2955 2956 /* set up params for periodic endpoint */ 2957 static void 2958 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 2959 { 2960 struct usbd_device *dev = pipe->up_dev; 2961 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2962 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2963 usbd_desc_iter_t iter; 2964 const usb_cdc_descriptor_t *cdcd; 2965 uint32_t maxb = 0; 2966 uint16_t mps = UGETW(ed->wMaxPacketSize); 2967 uint8_t speed = dev->ud_speed; 2968 uint8_t ep; 2969 2970 /* config desc is NULL when opening ep0 */ 2971 if (dev == NULL || dev->ud_cdesc == NULL) 2972 goto no_cdcd; 2973 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 2974 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 2975 if (cdcd == NULL) 2976 goto no_cdcd; 2977 usb_desc_iter_init(dev, &iter); 2978 iter.cur = (const void *)cdcd; 2979 2980 /* find endpoint_ss_comp desc for ep of this pipe */ 2981 for (ep = 0;;) { 2982 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 2983 if (cdcd == NULL) 2984 break; 2985 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 2986 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 2987 bEndpointAddress; 2988 if (UE_GET_ADDR(ep) == 2989 UE_GET_ADDR(ed->bEndpointAddress)) { 2990 cdcd = (const usb_cdc_descriptor_t *) 2991 usb_desc_iter_next(&iter); 2992 break; 2993 } 2994 ep = 0; 2995 } 2996 } 2997 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 2998 const usb_endpoint_ss_comp_descriptor_t * esscd = 2999 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3000 maxb = esscd->bMaxBurst; 3001 } 3002 3003 no_cdcd: 3004 /* 6.2.3.4, 4.8.2.4 */ 3005 if (USB_IS_SS(speed)) { 3006 /* UBS 3.1 9.6.6 */ 3007 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3008 /* UBS 3.1 9.6.7 */ 3009 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3010 #ifdef notyet 3011 if (xfertype == UE_ISOCHRONOUS) { 3012 } 3013 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3014 /* use ESIT */ 3015 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3016 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3017 3018 /* XXX if LEC = 1, set ESIT instead */ 3019 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3020 } else { 3021 /* use ival */ 3022 } 3023 #endif 3024 } else { 3025 /* UBS 2.0 9.6.6 */ 3026 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3027 3028 /* 6.2.3.4 */ 3029 if (speed == USB_SPEED_HIGH && 3030 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3031 maxb = UE_GET_TRANS(mps); 3032 } else { 3033 /* LS/FS or HS CTRL or HS BULK */ 3034 maxb = 0; 3035 } 3036 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3037 } 3038 } 3039 3040 /* 3041 * Convert endpoint bInterval value to endpoint context interval value 3042 * for Interrupt pipe. 3043 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3044 */ 3045 static uint32_t 3046 xhci_bival2ival(uint32_t ival, uint32_t speed) 3047 { 3048 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3049 int i; 3050 3051 /* 3052 * round ival down to "the nearest base 2 multiple of 3053 * bInterval * 8". 3054 * bInterval is at most 255 as its type is uByte. 3055 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3056 */ 3057 for (i = 10; i > 0; i--) { 3058 if ((ival * 8) >= (1 << i)) 3059 break; 3060 } 3061 ival = i; 3062 } else { 3063 /* Interval = bInterval-1 for SS/HS */ 3064 ival--; 3065 } 3066 3067 return ival; 3068 } 3069 3070 /* ----- */ 3071 3072 static void 3073 xhci_noop(struct usbd_pipe *pipe) 3074 { 3075 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3076 } 3077 3078 /* 3079 * Process root hub request. 3080 */ 3081 static int 3082 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3083 void *buf, int buflen) 3084 { 3085 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3086 usb_port_status_t ps; 3087 int l, totlen = 0; 3088 uint16_t len, value, index; 3089 int port, i; 3090 uint32_t v; 3091 3092 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3093 3094 if (sc->sc_dying) 3095 return -1; 3096 3097 len = UGETW(req->wLength); 3098 value = UGETW(req->wValue); 3099 index = UGETW(req->wIndex); 3100 3101 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 3102 req->bmRequestType | (req->bRequest << 8), value, index, len); 3103 3104 #define C(x,y) ((x) | ((y) << 8)) 3105 switch (C(req->bRequest, req->bmRequestType)) { 3106 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3107 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 3108 if (len == 0) 3109 break; 3110 switch (value) { 3111 case C(0, UDESC_DEVICE): { 3112 usb_device_descriptor_t devd; 3113 totlen = min(buflen, sizeof(devd)); 3114 memcpy(&devd, buf, totlen); 3115 USETW(devd.idVendor, sc->sc_id_vendor); 3116 memcpy(buf, &devd, totlen); 3117 break; 3118 } 3119 #define sd ((usb_string_descriptor_t *)buf) 3120 case C(1, UDESC_STRING): 3121 /* Vendor */ 3122 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3123 break; 3124 case C(2, UDESC_STRING): 3125 /* Product */ 3126 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3127 break; 3128 #undef sd 3129 default: 3130 /* default from usbroothub */ 3131 return buflen; 3132 } 3133 break; 3134 3135 /* Hub requests */ 3136 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3137 break; 3138 /* Clear Port Feature request */ 3139 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3140 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 3141 index, value, 0, 0); 3142 if (index < 1 || index > sc->sc_maxports) { 3143 return -1; 3144 } 3145 port = XHCI_PORTSC(index); 3146 v = xhci_op_read_4(sc, port); 3147 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3148 v &= ~XHCI_PS_CLEAR; 3149 switch (value) { 3150 case UHF_PORT_ENABLE: 3151 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3152 break; 3153 case UHF_PORT_SUSPEND: 3154 return -1; 3155 case UHF_PORT_POWER: 3156 break; 3157 case UHF_PORT_TEST: 3158 case UHF_PORT_INDICATOR: 3159 return -1; 3160 case UHF_C_PORT_CONNECTION: 3161 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3162 break; 3163 case UHF_C_PORT_ENABLE: 3164 case UHF_C_PORT_SUSPEND: 3165 case UHF_C_PORT_OVER_CURRENT: 3166 return -1; 3167 case UHF_C_BH_PORT_RESET: 3168 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3169 break; 3170 case UHF_C_PORT_RESET: 3171 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3172 break; 3173 case UHF_C_PORT_LINK_STATE: 3174 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3175 break; 3176 case UHF_C_PORT_CONFIG_ERROR: 3177 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3178 break; 3179 default: 3180 return -1; 3181 } 3182 break; 3183 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3184 if (len == 0) 3185 break; 3186 if ((value & 0xff) != 0) { 3187 return -1; 3188 } 3189 usb_hub_descriptor_t hubd; 3190 3191 totlen = min(buflen, sizeof(hubd)); 3192 memcpy(&hubd, buf, totlen); 3193 hubd.bNbrPorts = sc->sc_maxports; 3194 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3195 hubd.bPwrOn2PwrGood = 200; 3196 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 3197 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 3198 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3199 totlen = min(totlen, hubd.bDescLength); 3200 memcpy(buf, &hubd, totlen); 3201 break; 3202 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3203 if (len != 4) { 3204 return -1; 3205 } 3206 memset(buf, 0, len); /* ? XXX */ 3207 totlen = len; 3208 break; 3209 /* Get Port Status request */ 3210 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3211 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 3212 if (index < 1 || index > sc->sc_maxports) { 3213 return -1; 3214 } 3215 if (len != 4) { 3216 return -1; 3217 } 3218 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 3219 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 3220 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3221 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3222 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3223 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3224 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3225 if (v & XHCI_PS_PR) i |= UPS_RESET; 3226 if (v & XHCI_PS_PP) { 3227 if (i & UPS_OTHER_SPEED) 3228 i |= UPS_PORT_POWER_SS; 3229 else 3230 i |= UPS_PORT_POWER; 3231 } 3232 if (i & UPS_OTHER_SPEED) 3233 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3234 if (sc->sc_vendor_port_status) 3235 i = sc->sc_vendor_port_status(sc, v, i); 3236 USETW(ps.wPortStatus, i); 3237 i = 0; 3238 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3239 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3240 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3241 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3242 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3243 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3244 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3245 USETW(ps.wPortChange, i); 3246 totlen = min(len, sizeof(ps)); 3247 memcpy(buf, &ps, totlen); 3248 break; 3249 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3250 return -1; 3251 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3252 break; 3253 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3254 break; 3255 /* Set Port Feature request */ 3256 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3257 int optval = (index >> 8) & 0xff; 3258 index &= 0xff; 3259 if (index < 1 || index > sc->sc_maxports) { 3260 return -1; 3261 } 3262 port = XHCI_PORTSC(index); 3263 v = xhci_op_read_4(sc, port); 3264 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3265 v &= ~XHCI_PS_CLEAR; 3266 switch (value) { 3267 case UHF_PORT_ENABLE: 3268 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3269 break; 3270 case UHF_PORT_SUSPEND: 3271 /* XXX suspend */ 3272 break; 3273 case UHF_PORT_RESET: 3274 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3275 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3276 /* Wait for reset to complete. */ 3277 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3278 if (sc->sc_dying) { 3279 return -1; 3280 } 3281 v = xhci_op_read_4(sc, port); 3282 if (v & XHCI_PS_PR) { 3283 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3284 usb_delay_ms(&sc->sc_bus, 10); 3285 /* XXX */ 3286 } 3287 break; 3288 case UHF_PORT_POWER: 3289 /* XXX power control */ 3290 break; 3291 /* XXX more */ 3292 case UHF_C_PORT_RESET: 3293 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3294 break; 3295 case UHF_PORT_U1_TIMEOUT: 3296 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3297 return -1; 3298 } 3299 port = XHCI_PORTPMSC(index); 3300 v = xhci_op_read_4(sc, port); 3301 v &= ~XHCI_PM3_U1TO_SET(0xff); 3302 v |= XHCI_PM3_U1TO_SET(optval); 3303 xhci_op_write_4(sc, port, v); 3304 break; 3305 case UHF_PORT_U2_TIMEOUT: 3306 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3307 return -1; 3308 } 3309 port = XHCI_PORTPMSC(index); 3310 v = xhci_op_read_4(sc, port); 3311 v &= ~XHCI_PM3_U2TO_SET(0xff); 3312 v |= XHCI_PM3_U2TO_SET(optval); 3313 xhci_op_write_4(sc, port, v); 3314 break; 3315 default: 3316 return -1; 3317 } 3318 } 3319 break; 3320 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3321 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3322 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3323 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3324 break; 3325 default: 3326 /* default from usbroothub */ 3327 return buflen; 3328 } 3329 3330 return totlen; 3331 } 3332 3333 /* root hub interrupt */ 3334 3335 static usbd_status 3336 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3337 { 3338 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3339 usbd_status err; 3340 3341 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3342 3343 /* Insert last in queue. */ 3344 mutex_enter(&sc->sc_lock); 3345 err = usb_insert_transfer(xfer); 3346 mutex_exit(&sc->sc_lock); 3347 if (err) 3348 return err; 3349 3350 /* Pipe isn't running, start first */ 3351 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3352 } 3353 3354 /* Wait for roothub port status/change */ 3355 static usbd_status 3356 xhci_root_intr_start(struct usbd_xfer *xfer) 3357 { 3358 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3359 3360 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3361 3362 if (sc->sc_dying) 3363 return USBD_IOERROR; 3364 3365 mutex_enter(&sc->sc_lock); 3366 sc->sc_intrxfer = xfer; 3367 mutex_exit(&sc->sc_lock); 3368 3369 return USBD_IN_PROGRESS; 3370 } 3371 3372 static void 3373 xhci_root_intr_abort(struct usbd_xfer *xfer) 3374 { 3375 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3376 3377 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3378 3379 KASSERT(mutex_owned(&sc->sc_lock)); 3380 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3381 3382 sc->sc_intrxfer = NULL; 3383 3384 xfer->ux_status = USBD_CANCELLED; 3385 usb_transfer_complete(xfer); 3386 } 3387 3388 static void 3389 xhci_root_intr_close(struct usbd_pipe *pipe) 3390 { 3391 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3392 3393 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3394 3395 KASSERT(mutex_owned(&sc->sc_lock)); 3396 3397 sc->sc_intrxfer = NULL; 3398 } 3399 3400 static void 3401 xhci_root_intr_done(struct usbd_xfer *xfer) 3402 { 3403 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3404 3405 } 3406 3407 /* -------------- */ 3408 /* device control */ 3409 3410 static usbd_status 3411 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3412 { 3413 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3414 usbd_status err; 3415 3416 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3417 3418 /* Insert last in queue. */ 3419 mutex_enter(&sc->sc_lock); 3420 err = usb_insert_transfer(xfer); 3421 mutex_exit(&sc->sc_lock); 3422 if (err) 3423 return err; 3424 3425 /* Pipe isn't running, start first */ 3426 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3427 } 3428 3429 static usbd_status 3430 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3431 { 3432 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3433 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3434 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3435 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3436 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3437 usb_device_request_t * const req = &xfer->ux_request; 3438 const int isread = usbd_xfer_isread(xfer); 3439 const uint32_t len = UGETW(req->wLength); 3440 usb_dma_t * const dma = &xfer->ux_dmabuf; 3441 uint64_t parameter; 3442 uint32_t status; 3443 uint32_t control; 3444 u_int i; 3445 3446 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3447 DPRINTFN(12, "req: %04x %04x %04x %04x", 3448 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3449 UGETW(req->wIndex), UGETW(req->wLength)); 3450 3451 /* we rely on the bottom bits for extra info */ 3452 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 3453 3454 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3455 3456 i = 0; 3457 3458 /* setup phase */ 3459 memcpy(¶meter, req, sizeof(*req)); 3460 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3461 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3462 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3463 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3464 XHCI_TRB_3_IDT_BIT; 3465 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3466 3467 if (len != 0) { 3468 /* data phase */ 3469 parameter = DMAADDR(dma, 0); 3470 KASSERT(len <= 0x10000); 3471 status = XHCI_TRB_2_IRQ_SET(0) | 3472 XHCI_TRB_2_TDSZ_SET(1) | 3473 XHCI_TRB_2_BYTES_SET(len); 3474 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3475 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3476 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3477 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3478 3479 parameter = (uintptr_t)xfer | 0x3; 3480 status = XHCI_TRB_2_IRQ_SET(0); 3481 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3482 XHCI_TRB_3_IOC_BIT; 3483 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3484 } 3485 3486 parameter = 0; 3487 status = XHCI_TRB_2_IRQ_SET(0); 3488 /* the status stage has inverted direction */ 3489 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3490 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3491 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3492 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3493 3494 parameter = (uintptr_t)xfer | 0x0; 3495 status = XHCI_TRB_2_IRQ_SET(0); 3496 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3497 XHCI_TRB_3_IOC_BIT; 3498 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3499 3500 mutex_enter(&tr->xr_lock); 3501 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3502 mutex_exit(&tr->xr_lock); 3503 3504 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3505 3506 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3507 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3508 xhci_timeout, xfer); 3509 } 3510 3511 return USBD_IN_PROGRESS; 3512 } 3513 3514 static void 3515 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3516 { 3517 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3518 usb_device_request_t *req = &xfer->ux_request; 3519 int len = UGETW(req->wLength); 3520 int rd = req->bmRequestType & UT_READ; 3521 3522 if (len) 3523 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3524 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3525 } 3526 3527 static void 3528 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3529 { 3530 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3531 3532 xhci_abort_xfer(xfer, USBD_CANCELLED); 3533 } 3534 3535 static void 3536 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3537 { 3538 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3539 3540 xhci_close_pipe(pipe); 3541 } 3542 3543 /* ------------------ */ 3544 /* device isochronous */ 3545 3546 /* ----------- */ 3547 /* device bulk */ 3548 3549 static usbd_status 3550 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3551 { 3552 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3553 usbd_status err; 3554 3555 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3556 3557 /* Insert last in queue. */ 3558 mutex_enter(&sc->sc_lock); 3559 err = usb_insert_transfer(xfer); 3560 mutex_exit(&sc->sc_lock); 3561 if (err) 3562 return err; 3563 3564 /* 3565 * Pipe isn't running (otherwise err would be USBD_INPROG), 3566 * so start it first. 3567 */ 3568 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3569 } 3570 3571 static usbd_status 3572 xhci_device_bulk_start(struct usbd_xfer *xfer) 3573 { 3574 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3575 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3576 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3577 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3578 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3579 const uint32_t len = xfer->ux_length; 3580 usb_dma_t * const dma = &xfer->ux_dmabuf; 3581 uint64_t parameter; 3582 uint32_t status; 3583 uint32_t control; 3584 u_int i = 0; 3585 3586 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3587 3588 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3589 3590 if (sc->sc_dying) 3591 return USBD_IOERROR; 3592 3593 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3594 3595 parameter = DMAADDR(dma, 0); 3596 /* 3597 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3598 * If the user supplied buffer crosses such a boundary then 2 3599 * (or more) TRB should be used. 3600 * If multiple TRB are used the td_size field must be set correctly. 3601 * For v1.0 devices (like ivy bridge) this is the number of usb data 3602 * blocks needed to complete the transfer. 3603 * Setting it to 1 in the last TRB causes an extra zero-length 3604 * data block be sent. 3605 * The earlier documentation differs, I don't know how it behaves. 3606 */ 3607 KASSERT(len <= 0x10000); 3608 status = XHCI_TRB_2_IRQ_SET(0) | 3609 XHCI_TRB_2_TDSZ_SET(1) | 3610 XHCI_TRB_2_BYTES_SET(len); 3611 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3612 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3613 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3614 3615 mutex_enter(&tr->xr_lock); 3616 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3617 mutex_exit(&tr->xr_lock); 3618 3619 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3620 3621 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3622 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3623 xhci_timeout, xfer); 3624 } 3625 3626 return USBD_IN_PROGRESS; 3627 } 3628 3629 static void 3630 xhci_device_bulk_done(struct usbd_xfer *xfer) 3631 { 3632 #ifdef USB_DEBUG 3633 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3634 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3635 #endif 3636 const int isread = usbd_xfer_isread(xfer); 3637 3638 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3639 3640 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3641 3642 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3643 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3644 } 3645 3646 static void 3647 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3648 { 3649 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3650 3651 xhci_abort_xfer(xfer, USBD_CANCELLED); 3652 } 3653 3654 static void 3655 xhci_device_bulk_close(struct usbd_pipe *pipe) 3656 { 3657 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3658 3659 xhci_close_pipe(pipe); 3660 } 3661 3662 /* ---------------- */ 3663 /* device interrupt */ 3664 3665 static usbd_status 3666 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3667 { 3668 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3669 usbd_status err; 3670 3671 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3672 3673 /* Insert last in queue. */ 3674 mutex_enter(&sc->sc_lock); 3675 err = usb_insert_transfer(xfer); 3676 mutex_exit(&sc->sc_lock); 3677 if (err) 3678 return err; 3679 3680 /* 3681 * Pipe isn't running (otherwise err would be USBD_INPROG), 3682 * so start it first. 3683 */ 3684 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3685 } 3686 3687 static usbd_status 3688 xhci_device_intr_start(struct usbd_xfer *xfer) 3689 { 3690 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3691 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3692 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3693 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3694 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3695 const uint32_t len = xfer->ux_length; 3696 usb_dma_t * const dma = &xfer->ux_dmabuf; 3697 uint64_t parameter; 3698 uint32_t status; 3699 uint32_t control; 3700 u_int i = 0; 3701 3702 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3703 3704 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3705 3706 if (sc->sc_dying) 3707 return USBD_IOERROR; 3708 3709 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3710 3711 parameter = DMAADDR(dma, 0); 3712 KASSERT(len <= 0x10000); 3713 status = XHCI_TRB_2_IRQ_SET(0) | 3714 XHCI_TRB_2_TDSZ_SET(1) | 3715 XHCI_TRB_2_BYTES_SET(len); 3716 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3717 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3718 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3719 3720 mutex_enter(&tr->xr_lock); 3721 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3722 mutex_exit(&tr->xr_lock); 3723 3724 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3725 3726 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3727 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3728 xhci_timeout, xfer); 3729 } 3730 3731 return USBD_IN_PROGRESS; 3732 } 3733 3734 static void 3735 xhci_device_intr_done(struct usbd_xfer *xfer) 3736 { 3737 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3738 #ifdef USB_DEBUG 3739 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3740 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3741 #endif 3742 const int isread = usbd_xfer_isread(xfer); 3743 3744 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3745 3746 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3747 3748 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3749 3750 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3751 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3752 } 3753 3754 static void 3755 xhci_device_intr_abort(struct usbd_xfer *xfer) 3756 { 3757 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3758 3759 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3760 3761 KASSERT(mutex_owned(&sc->sc_lock)); 3762 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3763 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3764 xhci_abort_xfer(xfer, USBD_CANCELLED); 3765 } 3766 3767 static void 3768 xhci_device_intr_close(struct usbd_pipe *pipe) 3769 { 3770 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3771 3772 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3773 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3774 3775 xhci_close_pipe(pipe); 3776 } 3777 3778 /* ------------ */ 3779 3780 static void 3781 xhci_timeout(void *addr) 3782 { 3783 struct xhci_xfer * const xx = addr; 3784 struct usbd_xfer * const xfer = &xx->xx_xfer; 3785 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3786 3787 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3788 3789 if (sc->sc_dying) { 3790 return; 3791 } 3792 3793 usb_init_task(&xfer->ux_aborttask, xhci_timeout_task, addr, 3794 USB_TASKQ_MPSAFE); 3795 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xfer->ux_aborttask, 3796 USB_TASKQ_HC); 3797 } 3798 3799 static void 3800 xhci_timeout_task(void *addr) 3801 { 3802 struct usbd_xfer * const xfer = addr; 3803 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3804 3805 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3806 3807 mutex_enter(&sc->sc_lock); 3808 #if 0 3809 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3810 #else 3811 xfer->ux_status = USBD_TIMEOUT; 3812 usb_transfer_complete(xfer); 3813 #endif 3814 mutex_exit(&sc->sc_lock); 3815 } 3816
Indexes created Wed Oct 01 18:09:54 GMT 2025