xhci.c revision 1.28.2.73
1 /* $NetBSD: xhci.c,v 1.28.2.73 2016/06/10 14:44:56 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.28.2.73 2016/06/10 14:44:56 skrll Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static void xhci_host_dequeue(struct xhci_ring * const); 146 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 147 148 static usbd_status xhci_do_command(struct xhci_softc * const, 149 struct xhci_trb * const, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 153 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 154 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 155 static usbd_status xhci_enable_slot(struct xhci_softc * const, 156 uint8_t * const); 157 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 158 static usbd_status xhci_address_device(struct xhci_softc * const, 159 uint64_t, uint8_t, bool); 160 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 161 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 162 struct xhci_slot * const, u_int); 163 static usbd_status xhci_ring_init(struct xhci_softc * const, 164 struct xhci_ring * const, size_t, size_t); 165 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 166 167 static void xhci_setup_ctx(struct usbd_pipe *); 168 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 169 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 170 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 171 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 172 173 static void xhci_noop(struct usbd_pipe *); 174 175 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 176 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 177 static void xhci_root_intr_abort(struct usbd_xfer *); 178 static void xhci_root_intr_close(struct usbd_pipe *); 179 static void xhci_root_intr_done(struct usbd_xfer *); 180 181 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 182 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 183 static void xhci_device_ctrl_abort(struct usbd_xfer *); 184 static void xhci_device_ctrl_close(struct usbd_pipe *); 185 static void xhci_device_ctrl_done(struct usbd_xfer *); 186 187 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 188 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 189 static void xhci_device_intr_abort(struct usbd_xfer *); 190 static void xhci_device_intr_close(struct usbd_pipe *); 191 static void xhci_device_intr_done(struct usbd_xfer *); 192 193 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 194 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 195 static void xhci_device_bulk_abort(struct usbd_xfer *); 196 static void xhci_device_bulk_close(struct usbd_pipe *); 197 static void xhci_device_bulk_done(struct usbd_xfer *); 198 199 static void xhci_timeout(void *); 200 static void xhci_timeout_task(void *); 201 202 static const struct usbd_bus_methods xhci_bus_methods = { 203 .ubm_open = xhci_open, 204 .ubm_softint = xhci_softintr, 205 .ubm_dopoll = xhci_poll, 206 .ubm_allocx = xhci_allocx, 207 .ubm_freex = xhci_freex, 208 .ubm_getlock = xhci_get_lock, 209 .ubm_newdev = xhci_new_device, 210 .ubm_rhctrl = xhci_roothub_ctrl, 211 }; 212 213 static const struct usbd_pipe_methods xhci_root_intr_methods = { 214 .upm_transfer = xhci_root_intr_transfer, 215 .upm_start = xhci_root_intr_start, 216 .upm_abort = xhci_root_intr_abort, 217 .upm_close = xhci_root_intr_close, 218 .upm_cleartoggle = xhci_noop, 219 .upm_done = xhci_root_intr_done, 220 }; 221 222 223 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 224 .upm_transfer = xhci_device_ctrl_transfer, 225 .upm_start = xhci_device_ctrl_start, 226 .upm_abort = xhci_device_ctrl_abort, 227 .upm_close = xhci_device_ctrl_close, 228 .upm_cleartoggle = xhci_noop, 229 .upm_done = xhci_device_ctrl_done, 230 }; 231 232 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 233 .upm_cleartoggle = xhci_noop, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 237 .upm_transfer = xhci_device_bulk_transfer, 238 .upm_start = xhci_device_bulk_start, 239 .upm_abort = xhci_device_bulk_abort, 240 .upm_close = xhci_device_bulk_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_bulk_done, 243 }; 244 245 static const struct usbd_pipe_methods xhci_device_intr_methods = { 246 .upm_transfer = xhci_device_intr_transfer, 247 .upm_start = xhci_device_intr_start, 248 .upm_abort = xhci_device_intr_abort, 249 .upm_close = xhci_device_intr_close, 250 .upm_cleartoggle = xhci_noop, 251 .upm_done = xhci_device_intr_done, 252 }; 253 254 static inline uint32_t 255 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 256 { 257 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 258 } 259 260 static inline uint32_t 261 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 262 { 263 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 264 } 265 266 static inline void 267 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 268 uint32_t value) 269 { 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 271 } 272 273 #if 0 /* unused */ 274 static inline void 275 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 276 uint32_t value) 277 { 278 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 279 } 280 #endif /* unused */ 281 282 static inline uint32_t 283 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 284 { 285 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 286 } 287 288 static inline uint32_t 289 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 290 { 291 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 292 } 293 294 static inline void 295 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 296 uint32_t value) 297 { 298 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 299 } 300 301 static inline uint64_t 302 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 303 { 304 uint64_t value; 305 306 if (sc->sc_ac64) { 307 #ifdef XHCI_USE_BUS_SPACE_8 308 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 309 #else 310 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 311 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 312 offset + 4) << 32; 313 #endif 314 } else { 315 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 316 } 317 318 return value; 319 } 320 321 static inline void 322 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 336 } 337 } 338 339 static inline uint32_t 340 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 341 { 342 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 343 } 344 345 static inline void 346 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 347 uint32_t value) 348 { 349 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 350 } 351 352 #if 0 /* unused */ 353 static inline uint64_t 354 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 355 { 356 uint64_t value; 357 358 if (sc->sc_ac64) { 359 #ifdef XHCI_USE_BUS_SPACE_8 360 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 361 #else 362 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 363 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 364 offset + 4) << 32; 365 #endif 366 } else { 367 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 368 } 369 370 return value; 371 } 372 #endif /* unused */ 373 374 static inline void 375 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 376 uint64_t value) 377 { 378 if (sc->sc_ac64) { 379 #ifdef XHCI_USE_BUS_SPACE_8 380 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 381 #else 382 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 383 (value >> 0) & 0xffffffff); 384 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 385 (value >> 32) & 0xffffffff); 386 #endif 387 } else { 388 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 389 } 390 } 391 392 #if 0 /* unused */ 393 static inline uint32_t 394 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 395 { 396 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 397 } 398 #endif /* unused */ 399 400 static inline void 401 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 402 uint32_t value) 403 { 404 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 405 } 406 407 /* --- */ 408 409 static inline uint8_t 410 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 411 { 412 u_int eptype = 0; 413 414 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 415 case UE_CONTROL: 416 eptype = 0x0; 417 break; 418 case UE_ISOCHRONOUS: 419 eptype = 0x1; 420 break; 421 case UE_BULK: 422 eptype = 0x2; 423 break; 424 case UE_INTERRUPT: 425 eptype = 0x3; 426 break; 427 } 428 429 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 430 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 431 return eptype | 0x4; 432 else 433 return eptype; 434 } 435 436 static u_int 437 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 438 { 439 /* xHCI 1.0 section 4.5.1 */ 440 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 441 u_int in = 0; 442 443 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 444 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 445 in = 1; 446 447 return epaddr * 2 + in; 448 } 449 450 static inline u_int 451 xhci_dci_to_ici(const u_int i) 452 { 453 return i + 1; 454 } 455 456 static inline void * 457 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 458 const u_int dci) 459 { 460 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 461 } 462 463 #if 0 /* unused */ 464 static inline bus_addr_t 465 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 466 const u_int dci) 467 { 468 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 469 } 470 #endif /* unused */ 471 472 static inline void * 473 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline bus_addr_t 480 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 481 const u_int ici) 482 { 483 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 484 } 485 486 static inline struct xhci_trb * 487 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 488 { 489 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 490 } 491 492 static inline bus_addr_t 493 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 494 { 495 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 496 } 497 498 static inline void 499 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 500 uint32_t control) 501 { 502 trb->trb_0 = htole64(parameter); 503 trb->trb_2 = htole32(status); 504 trb->trb_3 = htole32(control); 505 } 506 507 static int 508 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 509 { 510 /* base address of TRBs */ 511 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 512 513 /* trb_0 range sanity check */ 514 if (trb_0 == 0 || trb_0 < trbp || 515 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 516 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 517 return 1; 518 } 519 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 520 return 0; 521 } 522 523 /* --- */ 524 525 void 526 xhci_childdet(device_t self, device_t child) 527 { 528 struct xhci_softc * const sc = device_private(self); 529 530 KASSERT(sc->sc_child == child); 531 if (child == sc->sc_child) 532 sc->sc_child = NULL; 533 } 534 535 int 536 xhci_detach(struct xhci_softc *sc, int flags) 537 { 538 int rv = 0; 539 540 if (sc->sc_child != NULL) 541 rv = config_detach(sc->sc_child, flags); 542 543 if (rv != 0) 544 return rv; 545 546 /* XXX unconfigure/free slots */ 547 548 /* verify: */ 549 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 550 xhci_op_write_4(sc, XHCI_USBCMD, 0); 551 /* do we need to wait for stop? */ 552 553 xhci_op_write_8(sc, XHCI_CRCR, 0); 554 xhci_ring_free(sc, &sc->sc_cr); 555 cv_destroy(&sc->sc_command_cv); 556 cv_destroy(&sc->sc_cmdbusy_cv); 557 558 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 559 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 560 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 561 xhci_ring_free(sc, &sc->sc_er); 562 563 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 564 565 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 566 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 567 568 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 569 570 mutex_destroy(&sc->sc_lock); 571 mutex_destroy(&sc->sc_intr_lock); 572 573 pool_cache_destroy(sc->sc_xferpool); 574 575 return rv; 576 } 577 578 int 579 xhci_activate(device_t self, enum devact act) 580 { 581 struct xhci_softc * const sc = device_private(self); 582 583 switch (act) { 584 case DVACT_DEACTIVATE: 585 sc->sc_dying = true; 586 return 0; 587 default: 588 return EOPNOTSUPP; 589 } 590 } 591 592 bool 593 xhci_suspend(device_t dv, const pmf_qual_t *qual) 594 { 595 return false; 596 } 597 598 bool 599 xhci_resume(device_t dv, const pmf_qual_t *qual) 600 { 601 return false; 602 } 603 604 bool 605 xhci_shutdown(device_t self, int flags) 606 { 607 return false; 608 } 609 610 static int 611 xhci_hc_reset(struct xhci_softc * const sc) 612 { 613 uint32_t usbcmd, usbsts; 614 int i; 615 616 /* Check controller not ready */ 617 for (i = 0; i < XHCI_WAIT_CNR; i++) { 618 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 619 if ((usbsts & XHCI_STS_CNR) == 0) 620 break; 621 usb_delay_ms(&sc->sc_bus, 1); 622 } 623 if (i >= XHCI_WAIT_CNR) { 624 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 625 return EIO; 626 } 627 628 /* Halt controller */ 629 usbcmd = 0; 630 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 631 usb_delay_ms(&sc->sc_bus, 1); 632 633 /* Reset controller */ 634 usbcmd = XHCI_CMD_HCRST; 635 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 636 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 637 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 638 if ((usbcmd & XHCI_CMD_HCRST) == 0) 639 break; 640 usb_delay_ms(&sc->sc_bus, 1); 641 } 642 if (i >= XHCI_WAIT_HCRST) { 643 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 644 return EIO; 645 } 646 647 /* Check controller not ready */ 648 for (i = 0; i < XHCI_WAIT_CNR; i++) { 649 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 650 if ((usbsts & XHCI_STS_CNR) == 0) 651 break; 652 usb_delay_ms(&sc->sc_bus, 1); 653 } 654 if (i >= XHCI_WAIT_CNR) { 655 aprint_error_dev(sc->sc_dev, 656 "controller not ready timeout after reset\n"); 657 return EIO; 658 } 659 660 return 0; 661 } 662 663 664 static void 665 hexdump(const char *msg, const void *base, size_t len) 666 { 667 #if 0 668 size_t cnt; 669 const uint32_t *p; 670 extern paddr_t vtophys(vaddr_t); 671 672 p = base; 673 cnt = 0; 674 675 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 676 (void *)vtophys((vaddr_t)base)); 677 678 while (cnt < len) { 679 if (cnt % 16 == 0) 680 printf("%p: ", p); 681 else if (cnt % 8 == 0) 682 printf(" |"); 683 printf(" %08x", *p++); 684 cnt += 4; 685 if (cnt % 16 == 0) 686 printf("\n"); 687 } 688 if (cnt % 16 != 0) 689 printf("\n"); 690 #endif 691 } 692 693 /* Process extended capabilities */ 694 static void 695 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 696 { 697 uint32_t ecp, ecr; 698 699 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 700 701 ecp = XHCI_HCC_XECP(hcc) * 4; 702 while (ecp != 0) { 703 ecr = xhci_read_4(sc, ecp); 704 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 705 switch (XHCI_XECP_ID(ecr)) { 706 case XHCI_ID_PROTOCOLS: { 707 uint32_t w4, w8, wc; 708 uint16_t w2; 709 w2 = (ecr >> 16) & 0xffff; 710 w4 = xhci_read_4(sc, ecp + 4); 711 w8 = xhci_read_4(sc, ecp + 8); 712 wc = xhci_read_4(sc, ecp + 0xc); 713 aprint_debug_dev(sc->sc_dev, 714 " SP: %08x %08x %08x %08x\n", ecr, w4, w8, wc); 715 /* unused */ 716 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0300) { 717 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 718 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 719 } 720 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0200) { 721 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 722 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 723 } 724 break; 725 } 726 case XHCI_ID_USB_LEGACY: { 727 uint8_t bios_sem; 728 729 /* Take host controller ownership from BIOS */ 730 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 731 if (bios_sem) { 732 /* sets xHCI to be owned by OS */ 733 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 734 aprint_debug_dev(sc->sc_dev, 735 "waiting for BIOS to give up control\n"); 736 for (int i = 0; i < 5000; i++) { 737 bios_sem = xhci_read_1(sc, ecp + 738 XHCI_XECP_BIOS_SEM); 739 if (bios_sem == 0) 740 break; 741 DELAY(1000); 742 } 743 if (bios_sem) { 744 aprint_error_dev(sc->sc_dev, 745 "timed out waiting for BIOS\n"); 746 } 747 } 748 break; 749 } 750 default: 751 break; 752 } 753 ecr = xhci_read_4(sc, ecp); 754 if (XHCI_XECP_NEXT(ecr) == 0) { 755 ecp = 0; 756 } else { 757 ecp += XHCI_XECP_NEXT(ecr) * 4; 758 } 759 } 760 } 761 762 #define XHCI_HCCPREV1_BITS \ 763 "\177\020" /* New bitmask */ \ 764 "f\020\020XECP\0" \ 765 "f\014\4MAXPSA\0" \ 766 "b\013CFC\0" \ 767 "b\012SEC\0" \ 768 "b\011SBD\0" \ 769 "b\010FSE\0" \ 770 "b\7NSS\0" \ 771 "b\6LTC\0" \ 772 "b\5LHRC\0" \ 773 "b\4PIND\0" \ 774 "b\3PPC\0" \ 775 "b\2CZC\0" \ 776 "b\1BNC\0" \ 777 "b\0AC64\0" \ 778 "\0" 779 #define XHCI_HCCV1_x_BITS \ 780 "\177\020" /* New bitmask */ \ 781 "f\020\020XECP\0" \ 782 "f\014\4MAXPSA\0" \ 783 "b\013CFC\0" \ 784 "b\012SEC\0" \ 785 "b\011SPC\0" \ 786 "b\010PAE\0" \ 787 "b\7NSS\0" \ 788 "b\6LTC\0" \ 789 "b\5LHRC\0" \ 790 "b\4PIND\0" \ 791 "b\3PPC\0" \ 792 "b\2CSZ\0" \ 793 "b\1BNC\0" \ 794 "b\0AC64\0" \ 795 "\0" 796 797 int 798 xhci_init(struct xhci_softc *sc) 799 { 800 bus_size_t bsz; 801 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 802 uint32_t pagesize, config; 803 int i = 0; 804 uint16_t hciversion; 805 uint8_t caplength; 806 807 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 808 809 sc->sc_bus.ub_revision = USBREV_3_0; 810 sc->sc_bus.ub_usedma = true; 811 812 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 813 caplength = XHCI_CAP_CAPLENGTH(cap); 814 hciversion = XHCI_CAP_HCIVERSION(cap); 815 816 if (hciversion < XHCI_HCIVERSION_0_96 || 817 hciversion > XHCI_HCIVERSION_1_0) { 818 aprint_normal_dev(sc->sc_dev, 819 "xHCI version %x.%x not known to be supported\n", 820 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 821 } else { 822 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 823 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 824 } 825 826 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 827 &sc->sc_cbh) != 0) { 828 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 829 return ENOMEM; 830 } 831 832 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 833 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 834 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 835 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 836 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 837 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 838 aprint_debug_dev(sc->sc_dev, 839 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 840 841 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 842 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 843 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 844 845 char sbuf[128]; 846 if (hciversion < XHCI_HCIVERSION_1_0) 847 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 848 else 849 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 850 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 851 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 852 853 /* print PSI and take ownership from BIOS */ 854 xhci_ecp(sc, hcc); 855 856 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 857 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 858 &sc->sc_obh) != 0) { 859 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 860 return ENOMEM; 861 } 862 863 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 864 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 865 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 866 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 867 return ENOMEM; 868 } 869 870 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 871 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 872 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 873 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 874 return ENOMEM; 875 } 876 877 int rv; 878 rv = xhci_hc_reset(sc); 879 if (rv != 0) { 880 return rv; 881 } 882 883 if (sc->sc_vendor_init) 884 sc->sc_vendor_init(sc); 885 886 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 887 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 888 pagesize = ffs(pagesize); 889 if (pagesize == 0) { 890 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 891 return EIO; 892 } 893 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 894 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 895 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 896 (uint32_t)sc->sc_maxslots); 897 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 898 899 usbd_status err; 900 901 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 902 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 903 if (sc->sc_maxspbuf != 0) { 904 err = usb_allocmem(&sc->sc_bus, 905 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 906 &sc->sc_spbufarray_dma); 907 if (err) { 908 aprint_error_dev(sc->sc_dev, 909 "spbufarray init fail, err %d\n", err); 910 return ENOMEM; 911 } 912 913 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 914 sc->sc_maxspbuf, KM_SLEEP); 915 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 916 for (i = 0; i < sc->sc_maxspbuf; i++) { 917 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 918 /* allocate contexts */ 919 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 920 sc->sc_pgsz, dma); 921 if (err) { 922 aprint_error_dev(sc->sc_dev, 923 "spbufarray_dma init fail, err %d\n", err); 924 rv = ENOMEM; 925 goto bad1; 926 } 927 spbufarray[i] = htole64(DMAADDR(dma, 0)); 928 usb_syncmem(dma, 0, sc->sc_pgsz, 929 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 930 } 931 932 usb_syncmem(&sc->sc_spbufarray_dma, 0, 933 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 934 } 935 936 config = xhci_op_read_4(sc, XHCI_CONFIG); 937 config &= ~0xFF; 938 config |= sc->sc_maxslots & 0xFF; 939 xhci_op_write_4(sc, XHCI_CONFIG, config); 940 941 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 942 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 943 if (err) { 944 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 945 err); 946 rv = ENOMEM; 947 goto bad1; 948 } 949 950 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 951 XHCI_EVENT_RING_SEGMENTS_ALIGN); 952 if (err) { 953 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 954 err); 955 rv = ENOMEM; 956 goto bad2; 957 } 958 959 usb_dma_t *dma; 960 size_t size; 961 size_t align; 962 963 dma = &sc->sc_eventst_dma; 964 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 965 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 966 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 967 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 968 err = usb_allocmem(&sc->sc_bus, size, align, dma); 969 if (err) { 970 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 971 err); 972 rv = ENOMEM; 973 goto bad3; 974 } 975 976 memset(KERNADDR(dma, 0), 0, size); 977 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 978 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 979 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 980 KERNADDR(&sc->sc_eventst_dma, 0), 981 sc->sc_eventst_dma.udma_block->size); 982 983 dma = &sc->sc_dcbaa_dma; 984 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 985 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 986 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 987 err = usb_allocmem(&sc->sc_bus, size, align, dma); 988 if (err) { 989 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 990 rv = ENOMEM; 991 goto bad4; 992 } 993 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 994 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 995 KERNADDR(&sc->sc_dcbaa_dma, 0), 996 sc->sc_dcbaa_dma.udma_block->size); 997 998 memset(KERNADDR(dma, 0), 0, size); 999 if (sc->sc_maxspbuf != 0) { 1000 /* 1001 * DCBA entry 0 hold the scratchbuf array pointer. 1002 */ 1003 *(uint64_t *)KERNADDR(dma, 0) = 1004 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1005 } 1006 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1007 1008 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1009 KM_SLEEP); 1010 if (sc->sc_slots == NULL) { 1011 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1012 rv = ENOMEM; 1013 goto bad; 1014 } 1015 1016 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1017 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1018 if (sc->sc_xferpool == NULL) { 1019 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1020 err); 1021 rv = ENOMEM; 1022 goto bad; 1023 } 1024 1025 cv_init(&sc->sc_command_cv, "xhcicmd"); 1026 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1027 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1028 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1029 1030 /* Set up the bus struct. */ 1031 sc->sc_bus.ub_methods = &xhci_bus_methods; 1032 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 1033 1034 struct xhci_erste *erst; 1035 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1036 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1037 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1038 erst[0].erste_3 = htole32(0); 1039 usb_syncmem(&sc->sc_eventst_dma, 0, 1040 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1041 1042 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1043 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1044 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1045 XHCI_ERDP_LO_BUSY); 1046 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1047 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1048 sc->sc_cr.xr_cs); 1049 1050 #if 0 1051 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1052 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1053 #endif 1054 1055 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1056 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1057 /* Intel xhci needs interrupt rate moderated. */ 1058 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1059 else 1060 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1061 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 1062 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1063 1064 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 1065 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1066 xhci_op_read_4(sc, XHCI_USBCMD)); 1067 1068 return 0; 1069 1070 bad: 1071 if (sc->sc_xferpool) { 1072 pool_cache_destroy(sc->sc_xferpool); 1073 sc->sc_xferpool = NULL; 1074 } 1075 1076 if (sc->sc_slots) { 1077 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1078 sc->sc_maxslots); 1079 sc->sc_slots = NULL; 1080 } 1081 1082 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1083 bad4: 1084 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1085 bad3: 1086 xhci_ring_free(sc, &sc->sc_er); 1087 bad2: 1088 xhci_ring_free(sc, &sc->sc_cr); 1089 i = sc->sc_maxspbuf; 1090 bad1: 1091 for (int j = 0; j < i; j++) 1092 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1093 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1094 1095 return rv; 1096 } 1097 1098 int 1099 xhci_intr(void *v) 1100 { 1101 struct xhci_softc * const sc = v; 1102 int ret = 0; 1103 1104 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1105 1106 if (sc == NULL) 1107 return 0; 1108 1109 mutex_spin_enter(&sc->sc_intr_lock); 1110 1111 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1112 goto done; 1113 1114 /* If we get an interrupt while polling, then just ignore it. */ 1115 if (sc->sc_bus.ub_usepolling) { 1116 #ifdef DIAGNOSTIC 1117 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1118 #endif 1119 goto done; 1120 } 1121 1122 ret = xhci_intr1(sc); 1123 done: 1124 mutex_spin_exit(&sc->sc_intr_lock); 1125 return ret; 1126 } 1127 1128 int 1129 xhci_intr1(struct xhci_softc * const sc) 1130 { 1131 uint32_t usbsts; 1132 uint32_t iman; 1133 1134 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1135 1136 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1137 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1138 #if 0 1139 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1140 return 0; 1141 } 1142 #endif 1143 xhci_op_write_4(sc, XHCI_USBSTS, 1144 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1145 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1146 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1147 1148 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1149 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1150 iman |= XHCI_IMAN_INTR_PEND; 1151 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1152 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1153 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1154 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1155 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1156 1157 usb_schedsoftintr(&sc->sc_bus); 1158 1159 return 1; 1160 } 1161 1162 /* 1163 * 3 port speed types used in USB stack 1164 * 1165 * usbdi speed 1166 * definition: USB_SPEED_* in usb.h 1167 * They are used in struct usbd_device in USB stack. 1168 * ioctl interface uses these values too. 1169 * port_status speed 1170 * definition: UPS_*_SPEED in usb.h 1171 * They are used in usb_port_status_t and valid only for USB 2.0. 1172 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1173 * of usb_port_status_ext_t indicates port speed. 1174 * Note that some 3.0 values overlap with 2.0 values. 1175 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1176 * means UPS_LOW_SPEED in HS.) 1177 * port status returned from hub also uses these values. 1178 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1179 * or more. 1180 * xspeed: 1181 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1182 * They are used in only slot context and PORTSC reg of xhci. 1183 * The difference between usbdi speed and xspeed is 1184 * that FS and LS values are swapped. 1185 */ 1186 1187 /* convert usbdi speed to xspeed */ 1188 static int 1189 xhci_speed2xspeed(int speed) 1190 { 1191 switch (speed) { 1192 case USB_SPEED_LOW: return 2; 1193 case USB_SPEED_FULL: return 1; 1194 default: return speed; 1195 } 1196 } 1197 1198 #if 0 1199 /* convert xspeed to usbdi speed */ 1200 static int 1201 xhci_xspeed2speed(int xspeed) 1202 { 1203 switch (xspeed) { 1204 case 1: return USB_SPEED_FULL; 1205 case 2: return USB_SPEED_LOW; 1206 default: return xspeed; 1207 } 1208 } 1209 #endif 1210 1211 /* convert xspeed to port status speed */ 1212 static int 1213 xhci_xspeed2psspeed(int xspeed) 1214 { 1215 switch (xspeed) { 1216 case 0: return 0; 1217 case 1: return UPS_FULL_SPEED; 1218 case 2: return UPS_LOW_SPEED; 1219 case 3: return UPS_HIGH_SPEED; 1220 default: return UPS_OTHER_SPEED; 1221 } 1222 } 1223 1224 /* 1225 * Construct input contexts and issue TRB to open pipe. 1226 */ 1227 static usbd_status 1228 xhci_configure_endpoint(struct usbd_pipe *pipe) 1229 { 1230 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1231 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1232 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1233 struct xhci_trb trb; 1234 usbd_status err; 1235 1236 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1237 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1238 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1239 pipe->up_endpoint->ue_edesc->bmAttributes); 1240 1241 KASSERT(!mutex_owned(&sc->sc_lock)); 1242 1243 /* XXX ensure input context is available? */ 1244 1245 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1246 1247 /* set up context */ 1248 xhci_setup_ctx(pipe); 1249 1250 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1251 sc->sc_ctxsz * 1); 1252 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1253 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1254 1255 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1256 trb.trb_2 = 0; 1257 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1258 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1259 1260 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1261 1262 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1263 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1264 sc->sc_ctxsz * 1); 1265 1266 return err; 1267 } 1268 1269 #if 0 1270 static usbd_status 1271 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1272 { 1273 #ifdef USB_DEBUG 1274 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1275 #endif 1276 1277 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1278 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1279 1280 return USBD_NORMAL_COMPLETION; 1281 } 1282 #endif 1283 1284 /* 4.6.8, 6.4.3.7 */ 1285 static usbd_status 1286 xhci_reset_endpoint(struct usbd_pipe *pipe) 1287 { 1288 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1289 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1290 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1291 struct xhci_trb trb; 1292 usbd_status err; 1293 1294 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1295 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1296 1297 KASSERT(!mutex_owned(&sc->sc_lock)); 1298 1299 trb.trb_0 = 0; 1300 trb.trb_2 = 0; 1301 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1302 XHCI_TRB_3_EP_SET(dci) | 1303 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1304 1305 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1306 1307 return err; 1308 } 1309 1310 /* 1311 * 4.6.9, 6.4.3.8 1312 * Stop execution of TDs on xfer ring. 1313 * Should be called with sc_lock held. 1314 */ 1315 static usbd_status 1316 xhci_stop_endpoint(struct usbd_pipe *pipe) 1317 { 1318 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1319 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1320 struct xhci_trb trb; 1321 usbd_status err; 1322 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1323 1324 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1325 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1326 1327 KASSERT(mutex_owned(&sc->sc_lock)); 1328 1329 trb.trb_0 = 0; 1330 trb.trb_2 = 0; 1331 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1332 XHCI_TRB_3_EP_SET(dci) | 1333 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1334 1335 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1336 1337 return err; 1338 } 1339 1340 /* 1341 * Set TR Dequeue Pointer. 1342 * xHCI 1.1 4.6.10 6.4.3.9 1343 * Purge all of the TRBs on ring and reinitialize ring. 1344 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1345 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1346 * error will be generated. 1347 */ 1348 static usbd_status 1349 xhci_set_dequeue(struct usbd_pipe *pipe) 1350 { 1351 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1352 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1353 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1354 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1355 struct xhci_trb trb; 1356 usbd_status err; 1357 1358 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1359 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1360 1361 xhci_host_dequeue(xr); 1362 1363 /* set DCS */ 1364 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1365 trb.trb_2 = 0; 1366 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1367 XHCI_TRB_3_EP_SET(dci) | 1368 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1369 1370 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1371 1372 return err; 1373 } 1374 1375 /* 1376 * Open new pipe: called from usbd_setup_pipe_flags. 1377 * Fills methods of pipe. 1378 * If pipe is not for ep0, calls configure_endpoint. 1379 */ 1380 static usbd_status 1381 xhci_open(struct usbd_pipe *pipe) 1382 { 1383 struct usbd_device * const dev = pipe->up_dev; 1384 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1385 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1386 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1387 1388 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1389 DPRINTFN(1, "addr %d depth %d port %d speed %d", dev->ud_addr, 1390 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1391 DPRINTFN(1, " dci %u type 0x%02x epaddr 0x%02x attr 0x%02x", 1392 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1393 ed->bmAttributes); 1394 DPRINTFN(1, " mps %u ival %u", UGETW(ed->wMaxPacketSize), ed->bInterval, 1395 0, 0); 1396 1397 if (sc->sc_dying) 1398 return USBD_IOERROR; 1399 1400 /* Root Hub */ 1401 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1402 switch (ed->bEndpointAddress) { 1403 case USB_CONTROL_ENDPOINT: 1404 pipe->up_methods = &roothub_ctrl_methods; 1405 break; 1406 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1407 pipe->up_methods = &xhci_root_intr_methods; 1408 break; 1409 default: 1410 pipe->up_methods = NULL; 1411 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1412 ed->bEndpointAddress, 0, 0, 0); 1413 return USBD_INVAL; 1414 } 1415 return USBD_NORMAL_COMPLETION; 1416 } 1417 1418 switch (xfertype) { 1419 case UE_CONTROL: 1420 pipe->up_methods = &xhci_device_ctrl_methods; 1421 break; 1422 case UE_ISOCHRONOUS: 1423 pipe->up_methods = &xhci_device_isoc_methods; 1424 return USBD_INVAL; 1425 break; 1426 case UE_BULK: 1427 pipe->up_methods = &xhci_device_bulk_methods; 1428 break; 1429 case UE_INTERRUPT: 1430 pipe->up_methods = &xhci_device_intr_methods; 1431 break; 1432 default: 1433 return USBD_IOERROR; 1434 break; 1435 } 1436 1437 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1438 return xhci_configure_endpoint(pipe); 1439 1440 return USBD_NORMAL_COMPLETION; 1441 } 1442 1443 /* 1444 * Closes pipe, called from usbd_kill_pipe via close methods. 1445 * If the endpoint to be closed is ep0, disable_slot. 1446 * Should be called with sc_lock held. 1447 */ 1448 static void 1449 xhci_close_pipe(struct usbd_pipe *pipe) 1450 { 1451 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1452 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1453 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1454 const u_int dci = xhci_ep_get_dci(ed); 1455 struct xhci_trb trb; 1456 uint32_t *cp; 1457 1458 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1459 1460 if (sc->sc_dying) 1461 return; 1462 1463 /* xs is uninitialized before xhci_init_slot */ 1464 if (xs == NULL || xs->xs_idx == 0) 1465 return; 1466 1467 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1468 1469 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1470 KASSERT(mutex_owned(&sc->sc_lock)); 1471 1472 if (pipe->up_dev->ud_depth == 0) 1473 return; 1474 1475 if (dci == XHCI_DCI_EP_CONTROL) { 1476 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1477 xhci_disable_slot(sc, xs->xs_idx); 1478 return; 1479 } 1480 1481 /* 1482 * This may fail in the case that xhci_close_pipe is called after 1483 * xhci_abort_xfer e.g. usbd_kill_pipe. 1484 */ 1485 (void)xhci_stop_endpoint(pipe); 1486 1487 /* 1488 * set appropriate bit to be dropped. 1489 * don't set DC bit to 1, otherwise all endpoints 1490 * would be deconfigured. 1491 */ 1492 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1493 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1494 cp[1] = htole32(0); 1495 1496 /* XXX should be most significant one, not dci? */ 1497 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1498 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1499 1500 /* configure ep context performs an implicit dequeue */ 1501 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 1502 1503 /* sync input contexts before they are read from memory */ 1504 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1505 1506 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1507 trb.trb_2 = 0; 1508 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1509 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1510 1511 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1512 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1513 } 1514 1515 /* 1516 * Abort transfer. 1517 * May be called from softintr context. 1518 */ 1519 static void 1520 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1521 { 1522 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1523 1524 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1525 DPRINTFN(4, "xfer %p pipe %p status %d", 1526 xfer, xfer->ux_pipe, status, 0); 1527 1528 KASSERT(mutex_owned(&sc->sc_lock)); 1529 1530 if (sc->sc_dying) { 1531 /* If we're dying, just do the software part. */ 1532 DPRINTFN(4, "xfer %p dying %u", xfer, xfer->ux_status, 0, 0); 1533 xfer->ux_status = status; 1534 callout_stop(&xfer->ux_callout); 1535 usb_transfer_complete(xfer); 1536 return; 1537 } 1538 1539 /* XXX need more stuff */ 1540 xfer->ux_status = status; 1541 callout_stop(&xfer->ux_callout); 1542 usb_transfer_complete(xfer); 1543 DPRINTFN(14, "end", 0, 0, 0, 0); 1544 1545 KASSERT(mutex_owned(&sc->sc_lock)); 1546 } 1547 1548 static void 1549 xhci_host_dequeue(struct xhci_ring * const xr) 1550 { 1551 /* When dequeueing the controller, update our struct copy too */ 1552 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1553 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1554 BUS_DMASYNC_PREWRITE); 1555 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1556 1557 xr->xr_ep = 0; 1558 xr->xr_cs = 1; 1559 } 1560 1561 /* 1562 * Recover STALLed endpoint. 1563 * xHCI 1.1 sect 4.10.2.1 1564 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1565 * all transfers on transfer ring. 1566 * These are done in thread context asynchronously. 1567 */ 1568 static void 1569 xhci_clear_endpoint_stall_async_task(void *cookie) 1570 { 1571 struct usbd_xfer * const xfer = cookie; 1572 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1573 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1574 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1575 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1576 1577 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1578 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1579 1580 xhci_reset_endpoint(xfer->ux_pipe); 1581 xhci_set_dequeue(xfer->ux_pipe); 1582 1583 mutex_enter(&sc->sc_lock); 1584 tr->is_halted = false; 1585 usb_transfer_complete(xfer); 1586 mutex_exit(&sc->sc_lock); 1587 DPRINTFN(4, "ends", 0, 0, 0, 0); 1588 } 1589 1590 static usbd_status 1591 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1592 { 1593 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1594 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1595 1596 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1597 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1598 1599 if (sc->sc_dying) { 1600 return USBD_IOERROR; 1601 } 1602 1603 usb_init_task(&xp->xp_async_task, 1604 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1605 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1606 DPRINTFN(4, "ends", 0, 0, 0, 0); 1607 1608 return USBD_NORMAL_COMPLETION; 1609 } 1610 1611 /* Process roothub port status/change events and notify to uhub_intr. */ 1612 static void 1613 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1614 { 1615 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1616 uint8_t *p; 1617 1618 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1619 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1620 port, 0, 0); 1621 1622 if (xfer == NULL) 1623 return; 1624 1625 if (port > sc->sc_maxports) 1626 return; 1627 1628 p = xfer->ux_buf; 1629 memset(p, 0, xfer->ux_length); 1630 p[port/NBBY] |= 1 << (port%NBBY); 1631 xfer->ux_actlen = xfer->ux_length; 1632 xfer->ux_status = USBD_NORMAL_COMPLETION; 1633 usb_transfer_complete(xfer); 1634 } 1635 1636 /* Process Transfer Events */ 1637 static void 1638 xhci_event_transfer(struct xhci_softc * const sc, 1639 const struct xhci_trb * const trb) 1640 { 1641 uint64_t trb_0; 1642 uint32_t trb_2, trb_3; 1643 uint8_t trbcode; 1644 u_int slot, dci; 1645 struct xhci_slot *xs; 1646 struct xhci_ring *xr; 1647 struct xhci_xfer *xx; 1648 struct usbd_xfer *xfer; 1649 usbd_status err; 1650 1651 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1652 1653 trb_0 = le64toh(trb->trb_0); 1654 trb_2 = le32toh(trb->trb_2); 1655 trb_3 = le32toh(trb->trb_3); 1656 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1657 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1658 dci = XHCI_TRB_3_EP_GET(trb_3); 1659 xs = &sc->sc_slots[slot]; 1660 xr = &xs->xs_ep[dci].xe_tr; 1661 1662 /* sanity check */ 1663 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1664 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1665 1666 int idx = 0; 1667 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1668 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1669 DPRINTFN(0, "invalid trb_0 0x%"PRIx64, trb_0, 0, 0, 0); 1670 return; 1671 } 1672 xx = xr->xr_cookies[idx]; 1673 1674 /* 1675 * If endpoint is stopped between TDs, TRB pointer points at 1676 * next TRB, however, it is not put yet or is a garbage TRB. 1677 * That's why xr_cookies may be NULL or look like broken. 1678 * Note: this ev happens only when hciversion >= 1.0 or 1679 * hciversion == 0.96 and FSE of hcc1 is set. 1680 */ 1681 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1682 DPRINTFN(1, "Ignore #%u: cookie %p cc %u dci %u", 1683 idx, xx, trbcode, dci); 1684 DPRINTFN(1, " orig TRB %"PRIx64" type %u", trb_0, 1685 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1686 0, 0); 1687 } 1688 } else { 1689 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1690 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1691 } 1692 /* XXX this may not happen */ 1693 if (xx == NULL) { 1694 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1695 return; 1696 } 1697 xfer = &xx->xx_xfer; 1698 /* XXX this may happen when detaching */ 1699 if (xfer == NULL) { 1700 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1701 xx, trb_0, 0, 0); 1702 return; 1703 } 1704 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1705 /* XXX I dunno why this happens */ 1706 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1707 1708 if (!xfer->ux_pipe->up_repeat && 1709 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1710 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1711 return; 1712 } 1713 1714 /* 4.11.5.2 Event Data TRB */ 1715 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1716 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1717 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1718 if ((trb_0 & 0x3) == 0x3) { 1719 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1720 } 1721 } 1722 1723 switch (trbcode) { 1724 case XHCI_TRB_ERROR_SHORT_PKT: 1725 case XHCI_TRB_ERROR_SUCCESS: 1726 /* 1727 * A ctrl transfer generates two events if it has a Data stage. 1728 * After a successful Data stage we cannot call call 1729 * usb_transfer_complete - this can only happen after the Data 1730 * stage. 1731 * 1732 * Note: Data and Status stage events point at same xfer. 1733 * ux_actlen and ux_dmabuf will be passed to 1734 * usb_transfer_complete after the Status stage event. 1735 * 1736 * It can be distingished which stage generates the event: 1737 * + by checking least 3 bits of trb_0 if ED==1. 1738 * (see xhci_device_ctrl_start). 1739 * + by checking the type of original TRB if ED==0. 1740 * 1741 * In addition, intr, bulk, and isoc transfer currently 1742 * consists of single TD, so the "skip" is not needed. 1743 * ctrl xfer uses EVENT_DATA, and others do not. 1744 * Thus driver can switch the flow by checking ED bit. 1745 */ 1746 xfer->ux_actlen = 1747 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1748 err = USBD_NORMAL_COMPLETION; 1749 break; 1750 case XHCI_TRB_ERROR_STALL: 1751 case XHCI_TRB_ERROR_BABBLE: 1752 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1753 xr->is_halted = true; 1754 err = USBD_STALLED; 1755 /* 1756 * Stalled endpoints can be recoverd by issuing 1757 * command TRB TYPE_RESET_EP on xHCI instead of 1758 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1759 * on the endpoint. However, this function may be 1760 * called from softint context (e.g. from umass), 1761 * in that case driver gets KASSERT in cv_timedwait 1762 * in xhci_do_command. 1763 * To avoid this, this runs reset_endpoint and 1764 * usb_transfer_complete in usb task thread 1765 * asynchronously (and then umass issues clear 1766 * UF_ENDPOINT_HALT). 1767 */ 1768 xfer->ux_status = err; 1769 xhci_clear_endpoint_stall_async(xfer); 1770 return; 1771 default: 1772 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1773 err = USBD_IOERROR; 1774 break; 1775 } 1776 xfer->ux_status = err; 1777 1778 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1779 if ((trb_0 & 0x3) == 0x0) { 1780 callout_stop(&xfer->ux_callout); 1781 usb_transfer_complete(xfer); 1782 } 1783 } else { 1784 callout_stop(&xfer->ux_callout); 1785 usb_transfer_complete(xfer); 1786 } 1787 } 1788 1789 /* Process Command complete events */ 1790 static void 1791 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 1792 { 1793 uint64_t trb_0; 1794 uint32_t trb_2, trb_3; 1795 1796 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1797 1798 KASSERT(mutex_owned(&sc->sc_lock)); 1799 1800 trb_0 = le64toh(trb->trb_0); 1801 trb_2 = le32toh(trb->trb_2); 1802 trb_3 = le32toh(trb->trb_3); 1803 1804 if (trb_0 == sc->sc_command_addr) { 1805 sc->sc_resultpending = false; 1806 1807 sc->sc_result_trb.trb_0 = trb_0; 1808 sc->sc_result_trb.trb_2 = trb_2; 1809 sc->sc_result_trb.trb_3 = trb_3; 1810 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1811 XHCI_TRB_ERROR_SUCCESS) { 1812 DPRINTFN(1, "command completion " 1813 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1814 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1815 } 1816 cv_signal(&sc->sc_command_cv); 1817 } else { 1818 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 1819 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1820 trb_2, trb_3); 1821 } 1822 } 1823 1824 /* 1825 * Process events. 1826 * called from xhci_softintr 1827 */ 1828 static void 1829 xhci_handle_event(struct xhci_softc * const sc, 1830 const struct xhci_trb * const trb) 1831 { 1832 uint64_t trb_0; 1833 uint32_t trb_2, trb_3; 1834 1835 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1836 1837 trb_0 = le64toh(trb->trb_0); 1838 trb_2 = le32toh(trb->trb_2); 1839 trb_3 = le32toh(trb->trb_3); 1840 1841 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1842 trb, trb_0, trb_2, trb_3); 1843 1844 /* 1845 * 4.11.3.1, 6.4.2.1 1846 * TRB Pointer is invalid for these completion codes. 1847 */ 1848 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 1849 case XHCI_TRB_ERROR_RING_UNDERRUN: 1850 case XHCI_TRB_ERROR_RING_OVERRUN: 1851 case XHCI_TRB_ERROR_VF_RING_FULL: 1852 return; 1853 default: 1854 if (trb_0 == 0) { 1855 return; 1856 } 1857 break; 1858 } 1859 1860 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 1861 case XHCI_TRB_EVENT_TRANSFER: 1862 xhci_event_transfer(sc, trb); 1863 break; 1864 case XHCI_TRB_EVENT_CMD_COMPLETE: 1865 xhci_event_cmd(sc, trb); 1866 break; 1867 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1868 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1869 break; 1870 default: 1871 break; 1872 } 1873 } 1874 1875 static void 1876 xhci_softintr(void *v) 1877 { 1878 struct usbd_bus * const bus = v; 1879 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1880 struct xhci_ring * const er = &sc->sc_er; 1881 struct xhci_trb *trb; 1882 int i, j, k; 1883 1884 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1885 1886 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1887 1888 i = er->xr_ep; 1889 j = er->xr_cs; 1890 1891 DPRINTFN(16, "er: xr_ep %d xr_cs %d", i, j, 0, 0); 1892 1893 while (1) { 1894 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 1895 BUS_DMASYNC_POSTREAD); 1896 trb = &er->xr_trb[i]; 1897 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1898 1899 if (j != k) 1900 break; 1901 1902 xhci_handle_event(sc, trb); 1903 1904 i++; 1905 if (i == er->xr_ntrb) { 1906 i = 0; 1907 j ^= 1; 1908 } 1909 } 1910 1911 er->xr_ep = i; 1912 er->xr_cs = j; 1913 1914 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 1915 XHCI_ERDP_LO_BUSY); 1916 1917 DPRINTFN(16, "ends", 0, 0, 0, 0); 1918 1919 return; 1920 } 1921 1922 static void 1923 xhci_poll(struct usbd_bus *bus) 1924 { 1925 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1926 1927 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1928 1929 mutex_spin_enter(&sc->sc_intr_lock); 1930 xhci_intr1(sc); 1931 mutex_spin_exit(&sc->sc_intr_lock); 1932 1933 return; 1934 } 1935 1936 static struct usbd_xfer * 1937 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 1938 { 1939 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1940 struct usbd_xfer *xfer; 1941 1942 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1943 1944 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1945 if (xfer != NULL) { 1946 memset(xfer, 0, sizeof(struct xhci_xfer)); 1947 #ifdef DIAGNOSTIC 1948 xfer->ux_state = XFER_BUSY; 1949 #endif 1950 } 1951 1952 return xfer; 1953 } 1954 1955 static void 1956 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1957 { 1958 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1959 1960 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1961 1962 #ifdef DIAGNOSTIC 1963 if (xfer->ux_state != XFER_BUSY) { 1964 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 1965 xfer, xfer->ux_state, 0, 0); 1966 } 1967 xfer->ux_state = XFER_FREE; 1968 #endif 1969 pool_cache_put(sc->sc_xferpool, xfer); 1970 } 1971 1972 static void 1973 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1974 { 1975 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1976 1977 *lock = &sc->sc_lock; 1978 } 1979 1980 extern uint32_t usb_cookie_no; 1981 1982 /* 1983 * xHCI 4.3 1984 * Called when uhub_explore finds a new device (via usbd_new_device). 1985 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 1986 * This function does: 1987 * Allocate and construct dev structure of default endpoint (ep0). 1988 * Allocate and open pipe of ep0. 1989 * Enable slot and initialize slot context. 1990 * Set Address. 1991 * Read initial device descriptor. 1992 * Determine initial MaxPacketSize (mps) by speed. 1993 * Read full device descriptor. 1994 * Register this device. 1995 * Finally state of device transitions ADDRESSED. 1996 */ 1997 static usbd_status 1998 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 1999 int speed, int port, struct usbd_port *up) 2000 { 2001 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2002 struct usbd_device *dev; 2003 usbd_status err; 2004 usb_device_descriptor_t *dd; 2005 struct xhci_slot *xs; 2006 uint32_t *cp; 2007 2008 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2009 DPRINTFN(4, "port %u depth %u speed %u up %p", port, depth, speed, up); 2010 2011 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2012 if (dev == NULL) 2013 return USBD_NOMEM; 2014 2015 dev->ud_bus = bus; 2016 dev->ud_quirks = &usbd_no_quirk; 2017 dev->ud_addr = 0; 2018 dev->ud_ddesc.bMaxPacketSize = 0; 2019 dev->ud_depth = depth; 2020 dev->ud_powersrc = up; 2021 dev->ud_myhub = up->up_parent; 2022 dev->ud_speed = speed; 2023 dev->ud_langid = USBD_NOLANG; 2024 dev->ud_cookie.cookie = ++usb_cookie_no; 2025 2026 /* Set up default endpoint handle. */ 2027 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2028 /* doesn't matter, just don't let it uninitialized */ 2029 dev->ud_ep0.ue_toggle = 0; 2030 2031 /* Set up default endpoint descriptor. */ 2032 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2033 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2034 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2035 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2036 dev->ud_ep0desc.bInterval = 0; 2037 2038 /* 4.3, 4.8.2.1 */ 2039 switch (speed) { 2040 case USB_SPEED_SUPER: 2041 case USB_SPEED_SUPER_PLUS: 2042 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2043 break; 2044 case USB_SPEED_FULL: 2045 /* XXX using 64 as initial mps of ep0 in FS */ 2046 case USB_SPEED_HIGH: 2047 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2048 break; 2049 case USB_SPEED_LOW: 2050 default: 2051 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2052 break; 2053 } 2054 2055 up->up_dev = dev; 2056 2057 /* Establish the default pipe. */ 2058 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2059 &dev->ud_pipe0); 2060 if (err) { 2061 goto bad; 2062 } 2063 2064 dd = &dev->ud_ddesc; 2065 2066 if ((depth == 0) && (port == 0)) { 2067 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2068 bus->ub_devices[dev->ud_addr] = dev; 2069 err = usbd_get_initial_ddesc(dev, dd); 2070 if (err) 2071 goto bad; 2072 err = usbd_reload_device_desc(dev); 2073 if (err) 2074 goto bad; 2075 } else { 2076 uint8_t slot = 0; 2077 2078 /* 4.3.2 */ 2079 err = xhci_enable_slot(sc, &slot); 2080 if (err) 2081 goto bad; 2082 2083 xs = &sc->sc_slots[slot]; 2084 dev->ud_hcpriv = xs; 2085 2086 /* 4.3.3 initialize slot structure */ 2087 err = xhci_init_slot(dev, slot); 2088 if (err) { 2089 dev->ud_hcpriv = NULL; 2090 /* 2091 * We have to disable_slot here because 2092 * xs->xs_idx == 0 when xhci_init_slot fails, 2093 * in that case usbd_remove_dev won't work. 2094 */ 2095 mutex_enter(&sc->sc_lock); 2096 xhci_disable_slot(sc, slot); 2097 mutex_exit(&sc->sc_lock); 2098 goto bad; 2099 } 2100 2101 /* 4.3.4 Address Assignment */ 2102 err = xhci_set_address(dev, slot, false); 2103 if (err) 2104 goto bad; 2105 2106 /* Allow device time to set new address */ 2107 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2108 2109 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2110 //hexdump("slot context", cp, sc->sc_ctxsz); 2111 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2112 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2113 /* XXX ensure we know when the hardware does something 2114 we can't yet cope with */ 2115 KASSERT(addr >= 1 && addr <= 127); 2116 dev->ud_addr = addr; 2117 /* XXX dev->ud_addr not necessarily unique on bus */ 2118 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2119 bus->ub_devices[dev->ud_addr] = dev; 2120 2121 err = usbd_get_initial_ddesc(dev, dd); 2122 if (err) 2123 goto bad; 2124 2125 /* 4.8.2.1 */ 2126 if (USB_IS_SS(speed)) { 2127 if (dd->bMaxPacketSize != 9) { 2128 printf("%s: invalid mps 2^%u for SS ep0," 2129 " using 512\n", 2130 device_xname(sc->sc_dev), 2131 dd->bMaxPacketSize); 2132 dd->bMaxPacketSize = 9; 2133 } 2134 USETW(dev->ud_ep0desc.wMaxPacketSize, 2135 (1 << dd->bMaxPacketSize)); 2136 } else 2137 USETW(dev->ud_ep0desc.wMaxPacketSize, 2138 dd->bMaxPacketSize); 2139 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2140 xhci_update_ep0_mps(sc, xs, 2141 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2142 2143 err = usbd_reload_device_desc(dev); 2144 if (err) 2145 goto bad; 2146 } 2147 2148 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2149 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2150 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2151 dd->bDeviceClass, dd->bDeviceSubClass, 2152 dd->bDeviceProtocol, 0); 2153 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2154 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2155 dev->ud_speed); 2156 2157 usbd_get_device_strings(dev); 2158 2159 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2160 2161 if ((depth == 0) && (port == 0)) { 2162 usbd_attach_roothub(parent, dev); 2163 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2164 return USBD_NORMAL_COMPLETION; 2165 } 2166 2167 2168 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2169 bad: 2170 if (err != USBD_NORMAL_COMPLETION) { 2171 usbd_remove_device(dev, up); 2172 } 2173 2174 return err; 2175 } 2176 2177 static usbd_status 2178 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2179 size_t ntrb, size_t align) 2180 { 2181 usbd_status err; 2182 size_t size = ntrb * XHCI_TRB_SIZE; 2183 2184 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2185 2186 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2187 if (err) 2188 return err; 2189 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2190 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2191 xr->xr_trb = xhci_ring_trbv(xr, 0); 2192 xr->xr_ntrb = ntrb; 2193 xr->is_halted = false; 2194 xhci_host_dequeue(xr); 2195 2196 return USBD_NORMAL_COMPLETION; 2197 } 2198 2199 static void 2200 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2201 { 2202 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2203 mutex_destroy(&xr->xr_lock); 2204 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2205 } 2206 2207 static void 2208 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2209 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2210 { 2211 size_t i; 2212 u_int ri; 2213 u_int cs; 2214 uint64_t parameter; 2215 uint32_t status; 2216 uint32_t control; 2217 2218 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2219 2220 KASSERT(ntrbs <= XHCI_XFER_NTRB); 2221 for (i = 0; i < ntrbs; i++) { 2222 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2223 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2224 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2225 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2226 XHCI_TRB_TYPE_LINK); 2227 } 2228 2229 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2230 2231 ri = xr->xr_ep; 2232 cs = xr->xr_cs; 2233 2234 /* 2235 * Although the xhci hardware can do scatter/gather dma from 2236 * arbitrary sized buffers, there is a non-obvious restriction 2237 * that a LINK trb is only allowed at the end of a burst of 2238 * transfers - which might be 16kB. 2239 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2240 * The simple solution is not to allow a LINK trb in the middle 2241 * of anything - as here. 2242 * XXX: (dsl) There are xhci controllers out there (eg some made by 2243 * ASMedia) that seem to lock up if they process a LINK trb but 2244 * cannot process the linked-to trb yet. 2245 * The code should write the 'cycle' bit on the link trb AFTER 2246 * adding the other trb. 2247 */ 2248 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2249 parameter = xhci_ring_trbp(xr, 0); 2250 status = 0; 2251 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2252 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2253 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2254 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2255 BUS_DMASYNC_PREWRITE); 2256 xr->xr_cookies[ri] = NULL; 2257 xr->xr_ep = 0; 2258 xr->xr_cs ^= 1; 2259 ri = xr->xr_ep; 2260 cs = xr->xr_cs; 2261 } 2262 2263 ri++; 2264 2265 /* Write any subsequent TRB first */ 2266 for (i = 1; i < ntrbs; i++) { 2267 parameter = trbs[i].trb_0; 2268 status = trbs[i].trb_2; 2269 control = trbs[i].trb_3; 2270 2271 if (cs) { 2272 control |= XHCI_TRB_3_CYCLE_BIT; 2273 } else { 2274 control &= ~XHCI_TRB_3_CYCLE_BIT; 2275 } 2276 2277 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2278 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2279 BUS_DMASYNC_PREWRITE); 2280 xr->xr_cookies[ri] = cookie; 2281 ri++; 2282 } 2283 2284 /* Write the first TRB last */ 2285 i = 0; 2286 parameter = trbs[i].trb_0; 2287 status = trbs[i].trb_2; 2288 control = trbs[i].trb_3; 2289 2290 if (xr->xr_cs) { 2291 control |= XHCI_TRB_3_CYCLE_BIT; 2292 } else { 2293 control &= ~XHCI_TRB_3_CYCLE_BIT; 2294 } 2295 2296 xhci_trb_put(&xr->xr_trb[xr->xr_ep], parameter, status, control); 2297 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * xr->xr_ep, XHCI_TRB_SIZE * 1, 2298 BUS_DMASYNC_PREWRITE); 2299 xr->xr_cookies[xr->xr_ep] = cookie; 2300 2301 xr->xr_ep = ri; 2302 xr->xr_cs = cs; 2303 2304 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2305 } 2306 2307 /* 2308 * Stop execution commands, purge all commands on command ring, and 2309 * rewind dequeue pointer. 2310 */ 2311 static void 2312 xhci_abort_command(struct xhci_softc *sc) 2313 { 2314 struct xhci_ring * const cr = &sc->sc_cr; 2315 uint64_t crcr; 2316 int i; 2317 2318 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2319 DPRINTFN(14, "command %#"PRIx64" timeout, aborting", 2320 sc->sc_command_addr, 0, 0, 0); 2321 2322 mutex_enter(&cr->xr_lock); 2323 2324 /* 4.6.1.2 Aborting a Command */ 2325 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2326 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2327 2328 for (i = 0; i < 500; i++) { 2329 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2330 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2331 break; 2332 usb_delay_ms(&sc->sc_bus, 1); 2333 } 2334 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2335 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2336 /* reset HC here? */ 2337 } 2338 2339 /* reset command ring dequeue pointer */ 2340 cr->xr_ep = 0; 2341 cr->xr_cs = 1; 2342 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2343 2344 mutex_exit(&cr->xr_lock); 2345 } 2346 2347 /* 2348 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2349 * Command completion is notified by cv_signal from xhci_event_cmd() 2350 * (called from xhci_softint), or timed-out. 2351 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2352 * then do_command examines it. 2353 */ 2354 static usbd_status 2355 xhci_do_command_locked(struct xhci_softc * const sc, 2356 struct xhci_trb * const trb, int timeout) 2357 { 2358 struct xhci_ring * const cr = &sc->sc_cr; 2359 usbd_status err; 2360 2361 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2362 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2363 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2364 2365 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2366 KASSERT(mutex_owned(&sc->sc_lock)); 2367 2368 while (sc->sc_command_addr != 0) 2369 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 2370 2371 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2372 sc->sc_resultpending = true; 2373 2374 mutex_enter(&cr->xr_lock); 2375 xhci_ring_put(sc, cr, NULL, trb, 1); 2376 mutex_exit(&cr->xr_lock); 2377 2378 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2379 2380 while (sc->sc_resultpending) { 2381 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2382 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2383 xhci_abort_command(sc); 2384 err = USBD_TIMEOUT; 2385 goto timedout; 2386 } 2387 } 2388 2389 trb->trb_0 = sc->sc_result_trb.trb_0; 2390 trb->trb_2 = sc->sc_result_trb.trb_2; 2391 trb->trb_3 = sc->sc_result_trb.trb_3; 2392 2393 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2394 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2395 2396 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2397 case XHCI_TRB_ERROR_SUCCESS: 2398 err = USBD_NORMAL_COMPLETION; 2399 break; 2400 default: 2401 case 192 ... 223: 2402 err = USBD_IOERROR; 2403 break; 2404 case 224 ... 255: 2405 err = USBD_NORMAL_COMPLETION; 2406 break; 2407 } 2408 2409 timedout: 2410 sc->sc_resultpending = false; 2411 sc->sc_command_addr = 0; 2412 cv_broadcast(&sc->sc_cmdbusy_cv); 2413 2414 return err; 2415 } 2416 2417 static usbd_status 2418 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2419 int timeout) 2420 { 2421 2422 mutex_enter(&sc->sc_lock); 2423 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2424 mutex_exit(&sc->sc_lock); 2425 2426 return ret; 2427 } 2428 2429 static usbd_status 2430 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2431 { 2432 struct xhci_trb trb; 2433 usbd_status err; 2434 2435 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2436 2437 trb.trb_0 = 0; 2438 trb.trb_2 = 0; 2439 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2440 2441 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2442 if (err != USBD_NORMAL_COMPLETION) { 2443 return err; 2444 } 2445 2446 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2447 2448 return err; 2449 } 2450 2451 /* 2452 * xHCI 4.6.4 2453 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2454 * All endpoints in the slot should be stopped. 2455 * Should be called with sc_lock held. 2456 */ 2457 static usbd_status 2458 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2459 { 2460 struct xhci_trb trb; 2461 struct xhci_slot *xs; 2462 usbd_status err; 2463 2464 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2465 2466 if (sc->sc_dying) 2467 return USBD_IOERROR; 2468 2469 trb.trb_0 = 0; 2470 trb.trb_2 = 0; 2471 trb.trb_3 = htole32( 2472 XHCI_TRB_3_SLOT_SET(slot) | 2473 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2474 2475 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2476 2477 if (!err) { 2478 xs = &sc->sc_slots[slot]; 2479 if (xs->xs_idx != 0) { 2480 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2481 xhci_set_dcba(sc, 0, slot); 2482 memset(xs, 0, sizeof(*xs)); 2483 } 2484 } 2485 2486 return err; 2487 } 2488 2489 /* 2490 * Set address of device and transition slot state from ENABLED to ADDRESSED 2491 * if Block Setaddress Request (BSR) is false. 2492 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2493 * see xHCI 1.1 4.5.3, 3.3.4 2494 * Should be called without sc_lock held. 2495 */ 2496 static usbd_status 2497 xhci_address_device(struct xhci_softc * const sc, 2498 uint64_t icp, uint8_t slot_id, bool bsr) 2499 { 2500 struct xhci_trb trb; 2501 usbd_status err; 2502 2503 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2504 2505 trb.trb_0 = icp; 2506 trb.trb_2 = 0; 2507 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2508 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2509 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2510 2511 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2512 2513 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2514 err = USBD_NO_ADDR; 2515 2516 return err; 2517 } 2518 2519 static usbd_status 2520 xhci_update_ep0_mps(struct xhci_softc * const sc, 2521 struct xhci_slot * const xs, u_int mps) 2522 { 2523 struct xhci_trb trb; 2524 usbd_status err; 2525 uint32_t * cp; 2526 2527 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2528 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2529 2530 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2531 cp[0] = htole32(0); 2532 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2533 2534 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2535 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2536 2537 /* sync input contexts before they are read from memory */ 2538 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2539 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2540 sc->sc_ctxsz * 4); 2541 2542 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2543 trb.trb_2 = 0; 2544 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2545 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2546 2547 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2548 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2549 return err; 2550 } 2551 2552 static void 2553 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2554 { 2555 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2556 2557 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2558 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2559 &dcbaa[si], dcba, si, 0); 2560 2561 dcbaa[si] = htole64(dcba); 2562 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2563 BUS_DMASYNC_PREWRITE); 2564 } 2565 2566 /* 2567 * Allocate device and input context DMA buffer, and 2568 * TRB DMA buffer for each endpoint. 2569 */ 2570 static usbd_status 2571 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2572 { 2573 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2574 struct xhci_slot *xs; 2575 usbd_status err; 2576 u_int dci; 2577 2578 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2579 DPRINTFN(4, "slot %u", slot, 0, 0, 0); 2580 2581 xs = &sc->sc_slots[slot]; 2582 2583 /* allocate contexts */ 2584 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2585 &xs->xs_dc_dma); 2586 if (err) 2587 return err; 2588 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2589 2590 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2591 &xs->xs_ic_dma); 2592 if (err) 2593 goto bad1; 2594 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2595 2596 for (dci = 0; dci < 32; dci++) { 2597 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2598 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2599 if (dci == XHCI_DCI_SLOT) 2600 continue; 2601 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2602 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2603 if (err) { 2604 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2605 goto bad2; 2606 } 2607 } 2608 2609 bad2: 2610 if (err == USBD_NORMAL_COMPLETION) { 2611 xs->xs_idx = slot; 2612 } else { 2613 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2614 } 2615 2616 return err; 2617 2618 bad1: 2619 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2620 xs->xs_idx = 0; 2621 return err; 2622 } 2623 2624 static void 2625 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2626 int end_dci) 2627 { 2628 u_int dci; 2629 2630 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2631 DPRINTFN(4, "slot %u start %u end %u", xs->xs_idx, start_dci, end_dci, 2632 0); 2633 2634 for (dci = start_dci; dci < end_dci; dci++) { 2635 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2636 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2637 } 2638 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2639 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2640 xs->xs_idx = 0; 2641 } 2642 2643 /* 2644 * Setup slot context, set Device Context Base Address, and issue 2645 * Set Address Device command. 2646 */ 2647 static usbd_status 2648 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 2649 { 2650 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2651 struct xhci_slot *xs; 2652 usbd_status err; 2653 2654 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2655 DPRINTFN(4, "slot %u bsr %u", slot, bsr, 0, 0); 2656 2657 xs = &sc->sc_slots[slot]; 2658 2659 xhci_setup_ctx(dev->ud_pipe0); 2660 2661 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2662 sc->sc_ctxsz * 3); 2663 2664 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2665 2666 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 2667 2668 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2669 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2670 sc->sc_ctxsz * 2); 2671 2672 return err; 2673 } 2674 2675 /* 2676 * 4.8.2, 6.2.3.2 2677 * construct slot/endpoint context parameters and do syncmem 2678 */ 2679 static void 2680 xhci_setup_ctx(struct usbd_pipe *pipe) 2681 { 2682 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2683 struct usbd_device *dev = pipe->up_dev; 2684 struct xhci_slot * const xs = dev->ud_hcpriv; 2685 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2686 const u_int dci = xhci_ep_get_dci(ed); 2687 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2688 uint32_t *cp; 2689 uint16_t mps = UGETW(ed->wMaxPacketSize); 2690 uint8_t speed = dev->ud_speed; 2691 uint8_t ival = ed->bInterval; 2692 2693 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2694 DPRINTFN(4, "pipe %p: slot %u dci %u speed %u", pipe, xs->xs_idx, dci, 2695 speed); 2696 2697 /* set up initial input control context */ 2698 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2699 cp[0] = htole32(0); 2700 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 2701 if (dci == XHCI_DCI_EP_CONTROL) 2702 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2703 cp[7] = htole32(0); 2704 2705 /* set up input slot context */ 2706 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2707 cp[0] = 2708 XHCI_SCTX_0_CTX_NUM_SET(dci) | 2709 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 2710 cp[1] = 0; 2711 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2712 cp[3] = 0; 2713 xhci_setup_route(pipe, cp); 2714 xhci_setup_tthub(pipe, cp); 2715 2716 cp[0] = htole32(cp[0]); 2717 cp[1] = htole32(cp[1]); 2718 cp[2] = htole32(cp[2]); 2719 cp[3] = htole32(cp[3]); 2720 2721 /* set up input endpoint context */ 2722 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 2723 cp[0] = 2724 XHCI_EPCTX_0_EPSTATE_SET(0) | 2725 XHCI_EPCTX_0_MULT_SET(0) | 2726 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2727 XHCI_EPCTX_0_LSA_SET(0) | 2728 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 2729 cp[1] = 2730 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 2731 XHCI_EPCTX_1_HID_SET(0) | 2732 XHCI_EPCTX_1_MAXB_SET(0); 2733 2734 if (xfertype != UE_ISOCHRONOUS) 2735 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 2736 2737 if (xfertype == UE_CONTROL) 2738 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 2739 else if (USB_IS_SS(speed)) 2740 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 2741 else 2742 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 2743 2744 xhci_setup_maxburst(pipe, cp); 2745 2746 switch (xfertype) { 2747 case UE_CONTROL: 2748 break; 2749 case UE_BULK: 2750 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 2751 break; 2752 case UE_INTERRUPT: 2753 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 2754 ival = pipe->up_interval; 2755 2756 ival = xhci_bival2ival(ival, speed); 2757 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 2758 break; 2759 case UE_ISOCHRONOUS: 2760 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 2761 ival = pipe->up_interval; 2762 2763 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 2764 if (speed == USB_SPEED_FULL) 2765 ival += 3; /* 1ms -> 125us */ 2766 ival--; 2767 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 2768 break; 2769 default: 2770 break; 2771 } 2772 DPRINTFN(4, "setting ival %u MaxBurst %#x", 2773 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 2774 2775 /* rewind TR dequeue pointer in xHC */ 2776 /* can't use xhci_ep_get_dci() yet? */ 2777 *(uint64_t *)(&cp[2]) = htole64( 2778 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 2779 XHCI_EPCTX_2_DCS_SET(1)); 2780 2781 cp[0] = htole32(cp[0]); 2782 cp[1] = htole32(cp[1]); 2783 cp[4] = htole32(cp[4]); 2784 2785 /* rewind TR dequeue pointer in driver */ 2786 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 2787 mutex_enter(&xr->xr_lock); 2788 xhci_host_dequeue(xr); 2789 mutex_exit(&xr->xr_lock); 2790 2791 /* sync input contexts before they are read from memory */ 2792 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2793 } 2794 2795 /* 2796 * Setup route string and roothub port of given device for slot context 2797 */ 2798 static void 2799 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 2800 { 2801 struct usbd_device *dev = pipe->up_dev; 2802 struct usbd_port *up = dev->ud_powersrc; 2803 struct usbd_device *hub; 2804 struct usbd_device *adev; 2805 uint8_t rhport = 0; 2806 uint32_t route = 0; 2807 2808 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2809 2810 /* Locate root hub port and Determine route string */ 2811 /* 4.3.3 route string does not include roothub port */ 2812 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2813 uint32_t dep; 2814 2815 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2816 hub, hub->ud_depth, hub->ud_powersrc, 2817 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2818 2819 if (hub->ud_powersrc == NULL) 2820 break; 2821 dep = hub->ud_depth; 2822 if (dep == 0) 2823 break; 2824 rhport = hub->ud_powersrc->up_portno; 2825 if (dep > USB_HUB_MAX_DEPTH) 2826 continue; 2827 2828 route |= 2829 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2830 << ((dep - 1) * 4); 2831 } 2832 route = route >> 4; 2833 DPRINTFN(4, "rhport %u Route %05x hub %p", rhport, route, hub, 0); 2834 2835 /* Locate port on upstream high speed hub */ 2836 for (adev = dev, hub = up->up_parent; 2837 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2838 adev = hub, hub = hub->ud_myhub) 2839 ; 2840 if (hub) { 2841 int p; 2842 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2843 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2844 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2845 goto found; 2846 } 2847 } 2848 panic("xhci_setup_route: cannot find HS port"); 2849 found: 2850 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2851 } else { 2852 dev->ud_myhsport = NULL; 2853 } 2854 2855 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 2856 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(rhport); 2857 } 2858 2859 /* 2860 * Setup whether device is hub, whether device uses MTT, and 2861 * TT informations if it uses MTT. 2862 */ 2863 static void 2864 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 2865 { 2866 struct usbd_device *dev = pipe->up_dev; 2867 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 2868 uint32_t speed = dev->ud_speed; 2869 uint8_t tthubslot, ttportnum; 2870 bool ishub; 2871 bool usemtt; 2872 2873 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2874 2875 /* 2876 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 2877 * tthubslot: 2878 * This is the slot ID of parent HS hub 2879 * if LS/FS device is connected && connected through HS hub. 2880 * This is 0 if device is not LS/FS device || 2881 * parent hub is not HS hub || 2882 * attached to root hub. 2883 * ttportnum: 2884 * This is the downstream facing port of parent HS hub 2885 * if LS/FS device is connected. 2886 * This is 0 if device is not LS/FS device || 2887 * parent hub is not HS hub || 2888 * attached to root hub. 2889 */ 2890 if (dev->ud_myhsport != NULL && 2891 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 2892 (dev->ud_myhub != NULL && 2893 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 2894 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 2895 ttportnum = dev->ud_myhsport->up_portno; 2896 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 2897 } else { 2898 ttportnum = 0; 2899 tthubslot = 0; 2900 } 2901 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 2902 dev->ud_myhsport, ttportnum, tthubslot, 0); 2903 2904 /* ishub is valid after reading UDESC_DEVICE */ 2905 ishub = (dd->bDeviceClass == UDCLASS_HUB); 2906 2907 /* dev->ud_hub is valid after reading UDESC_HUB */ 2908 if (ishub && dev->ud_hub) { 2909 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 2910 uint8_t ttt = 2911 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 2912 2913 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 2914 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 2915 DPRINTFN(4, "nports=%d ttt=%d", hd->bNbrPorts, ttt, 0, 0); 2916 } 2917 2918 #define IS_TTHUB(dd) \ 2919 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 2920 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 2921 2922 /* 2923 * MTT flag is set if 2924 * 1. this is HS hub && MTT is enabled 2925 * or 2926 * 2. this is not hub && this is LS or FS device && 2927 * MTT of parent HS hub (and its parent, too) is enabled 2928 */ 2929 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 2930 usemtt = true; 2931 else if (!ishub && 2932 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 2933 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 2934 (dev->ud_myhub != NULL && 2935 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 2936 dev->ud_myhsport != NULL && 2937 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 2938 usemtt = true; 2939 else 2940 usemtt = false; 2941 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 2942 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 2943 2944 #undef IS_TTHUB 2945 2946 cp[0] |= 2947 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 2948 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 2949 cp[2] |= 2950 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 2951 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 2952 } 2953 2954 /* set up params for periodic endpoint */ 2955 static void 2956 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 2957 { 2958 struct usbd_device *dev = pipe->up_dev; 2959 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2960 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2961 usbd_desc_iter_t iter; 2962 const usb_cdc_descriptor_t *cdcd; 2963 uint32_t maxb = 0; 2964 uint16_t mps = UGETW(ed->wMaxPacketSize); 2965 uint8_t speed = dev->ud_speed; 2966 uint8_t ep; 2967 2968 /* config desc is NULL when opening ep0 */ 2969 if (dev == NULL || dev->ud_cdesc == NULL) 2970 goto no_cdcd; 2971 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 2972 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 2973 if (cdcd == NULL) 2974 goto no_cdcd; 2975 usb_desc_iter_init(dev, &iter); 2976 iter.cur = (const void *)cdcd; 2977 2978 /* find endpoint_ss_comp desc for ep of this pipe */ 2979 for (ep = 0;;) { 2980 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 2981 if (cdcd == NULL) 2982 break; 2983 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 2984 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 2985 bEndpointAddress; 2986 if (UE_GET_ADDR(ep) == 2987 UE_GET_ADDR(ed->bEndpointAddress)) { 2988 cdcd = (const usb_cdc_descriptor_t *) 2989 usb_desc_iter_next(&iter); 2990 break; 2991 } 2992 ep = 0; 2993 } 2994 } 2995 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 2996 const usb_endpoint_ss_comp_descriptor_t * esscd = 2997 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 2998 maxb = esscd->bMaxBurst; 2999 } 3000 3001 no_cdcd: 3002 /* 6.2.3.4, 4.8.2.4 */ 3003 if (USB_IS_SS(speed)) { 3004 /* UBS 3.1 9.6.6 */ 3005 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3006 /* UBS 3.1 9.6.7 */ 3007 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3008 #ifdef notyet 3009 if (xfertype == UE_ISOCHRONOUS) { 3010 } 3011 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3012 /* use ESIT */ 3013 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3014 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3015 3016 /* XXX if LEC = 1, set ESIT instead */ 3017 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3018 } else { 3019 /* use ival */ 3020 } 3021 #endif 3022 } else { 3023 /* UBS 2.0 9.6.6 */ 3024 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3025 3026 /* 6.2.3.4 */ 3027 if (speed == USB_SPEED_HIGH && 3028 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3029 maxb = UE_GET_TRANS(mps); 3030 } else { 3031 /* LS/FS or HS CTRL or HS BULK */ 3032 maxb = 0; 3033 } 3034 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3035 } 3036 } 3037 3038 /* 3039 * Convert endpoint bInterval value to endpoint context interval value 3040 * for Interrupt pipe. 3041 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3042 */ 3043 static uint32_t 3044 xhci_bival2ival(uint32_t ival, uint32_t speed) 3045 { 3046 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3047 int i; 3048 3049 /* 3050 * round ival down to "the nearest base 2 multiple of 3051 * bInterval * 8". 3052 * bInterval is at most 255 as its type is uByte. 3053 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3054 */ 3055 for (i = 10; i > 0; i--) { 3056 if ((ival * 8) >= (1 << i)) 3057 break; 3058 } 3059 ival = i; 3060 } else { 3061 /* Interval = bInterval-1 for SS/HS */ 3062 ival--; 3063 } 3064 3065 return ival; 3066 } 3067 3068 /* ----- */ 3069 3070 static void 3071 xhci_noop(struct usbd_pipe *pipe) 3072 { 3073 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3074 } 3075 3076 /* 3077 * Process root hub request. 3078 */ 3079 static int 3080 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3081 void *buf, int buflen) 3082 { 3083 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3084 usb_port_status_t ps; 3085 int l, totlen = 0; 3086 uint16_t len, value, index; 3087 int port, i; 3088 uint32_t v; 3089 3090 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3091 3092 if (sc->sc_dying) 3093 return -1; 3094 3095 len = UGETW(req->wLength); 3096 value = UGETW(req->wValue); 3097 index = UGETW(req->wIndex); 3098 3099 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 3100 req->bmRequestType | (req->bRequest << 8), value, index, len); 3101 3102 #define C(x,y) ((x) | ((y) << 8)) 3103 switch (C(req->bRequest, req->bmRequestType)) { 3104 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3105 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 3106 if (len == 0) 3107 break; 3108 switch (value) { 3109 case C(0, UDESC_DEVICE): { 3110 usb_device_descriptor_t devd; 3111 totlen = min(buflen, sizeof(devd)); 3112 memcpy(&devd, buf, totlen); 3113 USETW(devd.idVendor, sc->sc_id_vendor); 3114 memcpy(buf, &devd, totlen); 3115 break; 3116 } 3117 #define sd ((usb_string_descriptor_t *)buf) 3118 case C(1, UDESC_STRING): 3119 /* Vendor */ 3120 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3121 break; 3122 case C(2, UDESC_STRING): 3123 /* Product */ 3124 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3125 break; 3126 #undef sd 3127 default: 3128 /* default from usbroothub */ 3129 return buflen; 3130 } 3131 break; 3132 3133 /* Hub requests */ 3134 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3135 break; 3136 /* Clear Port Feature request */ 3137 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3138 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 3139 index, value, 0, 0); 3140 if (index < 1 || index > sc->sc_maxports) { 3141 return -1; 3142 } 3143 port = XHCI_PORTSC(index); 3144 v = xhci_op_read_4(sc, port); 3145 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3146 v &= ~XHCI_PS_CLEAR; 3147 switch (value) { 3148 case UHF_PORT_ENABLE: 3149 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3150 break; 3151 case UHF_PORT_SUSPEND: 3152 return -1; 3153 case UHF_PORT_POWER: 3154 break; 3155 case UHF_PORT_TEST: 3156 case UHF_PORT_INDICATOR: 3157 return -1; 3158 case UHF_C_PORT_CONNECTION: 3159 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3160 break; 3161 case UHF_C_PORT_ENABLE: 3162 case UHF_C_PORT_SUSPEND: 3163 case UHF_C_PORT_OVER_CURRENT: 3164 return -1; 3165 case UHF_C_BH_PORT_RESET: 3166 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3167 break; 3168 case UHF_C_PORT_RESET: 3169 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3170 break; 3171 case UHF_C_PORT_LINK_STATE: 3172 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3173 break; 3174 case UHF_C_PORT_CONFIG_ERROR: 3175 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3176 break; 3177 default: 3178 return -1; 3179 } 3180 break; 3181 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3182 if (len == 0) 3183 break; 3184 if ((value & 0xff) != 0) { 3185 return -1; 3186 } 3187 usb_hub_descriptor_t hubd; 3188 3189 totlen = min(buflen, sizeof(hubd)); 3190 memcpy(&hubd, buf, totlen); 3191 hubd.bNbrPorts = sc->sc_maxports; 3192 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3193 hubd.bPwrOn2PwrGood = 200; 3194 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 3195 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 3196 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3197 totlen = min(totlen, hubd.bDescLength); 3198 memcpy(buf, &hubd, totlen); 3199 break; 3200 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3201 if (len != 4) { 3202 return -1; 3203 } 3204 memset(buf, 0, len); /* ? XXX */ 3205 totlen = len; 3206 break; 3207 /* Get Port Status request */ 3208 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3209 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 3210 if (index < 1 || index > sc->sc_maxports) { 3211 return -1; 3212 } 3213 if (len != 4) { 3214 return -1; 3215 } 3216 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 3217 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 3218 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3219 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3220 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3221 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3222 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3223 if (v & XHCI_PS_PR) i |= UPS_RESET; 3224 if (v & XHCI_PS_PP) { 3225 if (i & UPS_OTHER_SPEED) 3226 i |= UPS_PORT_POWER_SS; 3227 else 3228 i |= UPS_PORT_POWER; 3229 } 3230 if (i & UPS_OTHER_SPEED) 3231 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3232 if (sc->sc_vendor_port_status) 3233 i = sc->sc_vendor_port_status(sc, v, i); 3234 USETW(ps.wPortStatus, i); 3235 i = 0; 3236 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3237 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3238 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3239 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3240 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3241 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3242 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3243 USETW(ps.wPortChange, i); 3244 totlen = min(len, sizeof(ps)); 3245 memcpy(buf, &ps, totlen); 3246 break; 3247 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3248 return -1; 3249 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3250 break; 3251 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3252 break; 3253 /* Set Port Feature request */ 3254 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3255 int optval = (index >> 8) & 0xff; 3256 index &= 0xff; 3257 if (index < 1 || index > sc->sc_maxports) { 3258 return -1; 3259 } 3260 port = XHCI_PORTSC(index); 3261 v = xhci_op_read_4(sc, port); 3262 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3263 v &= ~XHCI_PS_CLEAR; 3264 switch (value) { 3265 case UHF_PORT_ENABLE: 3266 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3267 break; 3268 case UHF_PORT_SUSPEND: 3269 /* XXX suspend */ 3270 break; 3271 case UHF_PORT_RESET: 3272 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3273 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3274 /* Wait for reset to complete. */ 3275 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3276 if (sc->sc_dying) { 3277 return -1; 3278 } 3279 v = xhci_op_read_4(sc, port); 3280 if (v & XHCI_PS_PR) { 3281 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3282 usb_delay_ms(&sc->sc_bus, 10); 3283 /* XXX */ 3284 } 3285 break; 3286 case UHF_PORT_POWER: 3287 /* XXX power control */ 3288 break; 3289 /* XXX more */ 3290 case UHF_C_PORT_RESET: 3291 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3292 break; 3293 case UHF_PORT_U1_TIMEOUT: 3294 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3295 return -1; 3296 } 3297 port = XHCI_PORTPMSC(index); 3298 v = xhci_op_read_4(sc, port); 3299 v &= ~XHCI_PM3_U1TO_SET(0xff); 3300 v |= XHCI_PM3_U1TO_SET(optval); 3301 xhci_op_write_4(sc, port, v); 3302 break; 3303 case UHF_PORT_U2_TIMEOUT: 3304 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3305 return -1; 3306 } 3307 port = XHCI_PORTPMSC(index); 3308 v = xhci_op_read_4(sc, port); 3309 v &= ~XHCI_PM3_U2TO_SET(0xff); 3310 v |= XHCI_PM3_U2TO_SET(optval); 3311 xhci_op_write_4(sc, port, v); 3312 break; 3313 default: 3314 return -1; 3315 } 3316 } 3317 break; 3318 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3319 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3320 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3321 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3322 break; 3323 default: 3324 /* default from usbroothub */ 3325 return buflen; 3326 } 3327 3328 return totlen; 3329 } 3330 3331 /* root hub interrupt */ 3332 3333 static usbd_status 3334 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3335 { 3336 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3337 usbd_status err; 3338 3339 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3340 3341 /* Insert last in queue. */ 3342 mutex_enter(&sc->sc_lock); 3343 err = usb_insert_transfer(xfer); 3344 mutex_exit(&sc->sc_lock); 3345 if (err) 3346 return err; 3347 3348 /* Pipe isn't running, start first */ 3349 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3350 } 3351 3352 /* Wait for roothub port status/change */ 3353 static usbd_status 3354 xhci_root_intr_start(struct usbd_xfer *xfer) 3355 { 3356 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3357 3358 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3359 3360 if (sc->sc_dying) 3361 return USBD_IOERROR; 3362 3363 mutex_enter(&sc->sc_lock); 3364 sc->sc_intrxfer = xfer; 3365 mutex_exit(&sc->sc_lock); 3366 3367 return USBD_IN_PROGRESS; 3368 } 3369 3370 static void 3371 xhci_root_intr_abort(struct usbd_xfer *xfer) 3372 { 3373 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3374 3375 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3376 3377 KASSERT(mutex_owned(&sc->sc_lock)); 3378 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3379 3380 sc->sc_intrxfer = NULL; 3381 3382 xfer->ux_status = USBD_CANCELLED; 3383 usb_transfer_complete(xfer); 3384 } 3385 3386 static void 3387 xhci_root_intr_close(struct usbd_pipe *pipe) 3388 { 3389 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3390 3391 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3392 3393 KASSERT(mutex_owned(&sc->sc_lock)); 3394 3395 sc->sc_intrxfer = NULL; 3396 } 3397 3398 static void 3399 xhci_root_intr_done(struct usbd_xfer *xfer) 3400 { 3401 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3402 3403 } 3404 3405 /* -------------- */ 3406 /* device control */ 3407 3408 static usbd_status 3409 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3410 { 3411 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3412 usbd_status err; 3413 3414 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3415 3416 /* Insert last in queue. */ 3417 mutex_enter(&sc->sc_lock); 3418 err = usb_insert_transfer(xfer); 3419 mutex_exit(&sc->sc_lock); 3420 if (err) 3421 return err; 3422 3423 /* Pipe isn't running, start first */ 3424 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3425 } 3426 3427 static usbd_status 3428 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3429 { 3430 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3431 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3432 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3433 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3434 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3435 usb_device_request_t * const req = &xfer->ux_request; 3436 const int isread = usbd_xfer_isread(xfer); 3437 const uint32_t len = UGETW(req->wLength); 3438 usb_dma_t * const dma = &xfer->ux_dmabuf; 3439 uint64_t parameter; 3440 uint32_t status; 3441 uint32_t control; 3442 u_int i; 3443 3444 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3445 DPRINTFN(12, "req: %04x %04x %04x %04x", 3446 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3447 UGETW(req->wIndex), UGETW(req->wLength)); 3448 3449 /* we rely on the bottom bits for extra info */ 3450 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 3451 3452 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3453 3454 i = 0; 3455 3456 /* setup phase */ 3457 memcpy(¶meter, req, sizeof(*req)); 3458 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3459 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3460 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3461 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3462 XHCI_TRB_3_IDT_BIT; 3463 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3464 3465 if (len != 0) { 3466 /* data phase */ 3467 parameter = DMAADDR(dma, 0); 3468 KASSERT(len <= 0x10000); 3469 status = XHCI_TRB_2_IRQ_SET(0) | 3470 XHCI_TRB_2_TDSZ_SET(1) | 3471 XHCI_TRB_2_BYTES_SET(len); 3472 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3473 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3474 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3475 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3476 3477 parameter = (uintptr_t)xfer | 0x3; 3478 status = XHCI_TRB_2_IRQ_SET(0); 3479 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3480 XHCI_TRB_3_IOC_BIT; 3481 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3482 } 3483 3484 parameter = 0; 3485 status = XHCI_TRB_2_IRQ_SET(0); 3486 /* the status stage has inverted direction */ 3487 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3488 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3489 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3490 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3491 3492 parameter = (uintptr_t)xfer | 0x0; 3493 status = XHCI_TRB_2_IRQ_SET(0); 3494 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3495 XHCI_TRB_3_IOC_BIT; 3496 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3497 3498 mutex_enter(&tr->xr_lock); 3499 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3500 mutex_exit(&tr->xr_lock); 3501 3502 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3503 3504 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3505 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3506 xhci_timeout, xfer); 3507 } 3508 3509 return USBD_IN_PROGRESS; 3510 } 3511 3512 static void 3513 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3514 { 3515 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3516 usb_device_request_t *req = &xfer->ux_request; 3517 int len = UGETW(req->wLength); 3518 int rd = req->bmRequestType & UT_READ; 3519 3520 if (len) 3521 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3522 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3523 } 3524 3525 static void 3526 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3527 { 3528 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3529 3530 xhci_abort_xfer(xfer, USBD_CANCELLED); 3531 } 3532 3533 static void 3534 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3535 { 3536 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3537 3538 xhci_close_pipe(pipe); 3539 } 3540 3541 /* ------------------ */ 3542 /* device isochronous */ 3543 3544 /* ----------- */ 3545 /* device bulk */ 3546 3547 static usbd_status 3548 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3549 { 3550 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3551 usbd_status err; 3552 3553 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3554 3555 /* Insert last in queue. */ 3556 mutex_enter(&sc->sc_lock); 3557 err = usb_insert_transfer(xfer); 3558 mutex_exit(&sc->sc_lock); 3559 if (err) 3560 return err; 3561 3562 /* 3563 * Pipe isn't running (otherwise err would be USBD_INPROG), 3564 * so start it first. 3565 */ 3566 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3567 } 3568 3569 static usbd_status 3570 xhci_device_bulk_start(struct usbd_xfer *xfer) 3571 { 3572 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3573 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3574 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3575 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3576 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3577 const uint32_t len = xfer->ux_length; 3578 usb_dma_t * const dma = &xfer->ux_dmabuf; 3579 uint64_t parameter; 3580 uint32_t status; 3581 uint32_t control; 3582 u_int i = 0; 3583 3584 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3585 3586 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3587 3588 if (sc->sc_dying) 3589 return USBD_IOERROR; 3590 3591 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3592 3593 parameter = DMAADDR(dma, 0); 3594 /* 3595 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3596 * If the user supplied buffer crosses such a boundary then 2 3597 * (or more) TRB should be used. 3598 * If multiple TRB are used the td_size field must be set correctly. 3599 * For v1.0 devices (like ivy bridge) this is the number of usb data 3600 * blocks needed to complete the transfer. 3601 * Setting it to 1 in the last TRB causes an extra zero-length 3602 * data block be sent. 3603 * The earlier documentation differs, I don't know how it behaves. 3604 */ 3605 KASSERT(len <= 0x10000); 3606 status = XHCI_TRB_2_IRQ_SET(0) | 3607 XHCI_TRB_2_TDSZ_SET(1) | 3608 XHCI_TRB_2_BYTES_SET(len); 3609 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3610 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3611 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3612 3613 mutex_enter(&tr->xr_lock); 3614 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3615 mutex_exit(&tr->xr_lock); 3616 3617 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3618 3619 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3620 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3621 xhci_timeout, xfer); 3622 } 3623 3624 return USBD_IN_PROGRESS; 3625 } 3626 3627 static void 3628 xhci_device_bulk_done(struct usbd_xfer *xfer) 3629 { 3630 #ifdef USB_DEBUG 3631 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3632 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3633 #endif 3634 const int isread = usbd_xfer_isread(xfer); 3635 3636 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3637 3638 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3639 3640 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3641 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3642 } 3643 3644 static void 3645 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3646 { 3647 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3648 3649 xhci_abort_xfer(xfer, USBD_CANCELLED); 3650 } 3651 3652 static void 3653 xhci_device_bulk_close(struct usbd_pipe *pipe) 3654 { 3655 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3656 3657 xhci_close_pipe(pipe); 3658 } 3659 3660 /* ---------------- */ 3661 /* device interrupt */ 3662 3663 static usbd_status 3664 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3665 { 3666 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3667 usbd_status err; 3668 3669 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3670 3671 /* Insert last in queue. */ 3672 mutex_enter(&sc->sc_lock); 3673 err = usb_insert_transfer(xfer); 3674 mutex_exit(&sc->sc_lock); 3675 if (err) 3676 return err; 3677 3678 /* 3679 * Pipe isn't running (otherwise err would be USBD_INPROG), 3680 * so start it first. 3681 */ 3682 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3683 } 3684 3685 static usbd_status 3686 xhci_device_intr_start(struct usbd_xfer *xfer) 3687 { 3688 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3689 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3690 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3691 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3692 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3693 const uint32_t len = xfer->ux_length; 3694 usb_dma_t * const dma = &xfer->ux_dmabuf; 3695 uint64_t parameter; 3696 uint32_t status; 3697 uint32_t control; 3698 u_int i = 0; 3699 3700 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3701 3702 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3703 3704 if (sc->sc_dying) 3705 return USBD_IOERROR; 3706 3707 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3708 3709 parameter = DMAADDR(dma, 0); 3710 KASSERT(len <= 0x10000); 3711 status = XHCI_TRB_2_IRQ_SET(0) | 3712 XHCI_TRB_2_TDSZ_SET(1) | 3713 XHCI_TRB_2_BYTES_SET(len); 3714 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3715 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3716 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3717 3718 mutex_enter(&tr->xr_lock); 3719 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3720 mutex_exit(&tr->xr_lock); 3721 3722 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3723 3724 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3725 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3726 xhci_timeout, xfer); 3727 } 3728 3729 return USBD_IN_PROGRESS; 3730 } 3731 3732 static void 3733 xhci_device_intr_done(struct usbd_xfer *xfer) 3734 { 3735 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3736 #ifdef USB_DEBUG 3737 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3738 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3739 #endif 3740 const int isread = usbd_xfer_isread(xfer); 3741 3742 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3743 3744 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3745 3746 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3747 3748 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3749 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3750 } 3751 3752 static void 3753 xhci_device_intr_abort(struct usbd_xfer *xfer) 3754 { 3755 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3756 3757 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3758 3759 KASSERT(mutex_owned(&sc->sc_lock)); 3760 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3761 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3762 xhci_abort_xfer(xfer, USBD_CANCELLED); 3763 } 3764 3765 static void 3766 xhci_device_intr_close(struct usbd_pipe *pipe) 3767 { 3768 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3769 3770 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3771 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3772 3773 xhci_close_pipe(pipe); 3774 } 3775 3776 /* ------------ */ 3777 3778 static void 3779 xhci_timeout(void *addr) 3780 { 3781 struct xhci_xfer * const xx = addr; 3782 struct usbd_xfer * const xfer = &xx->xx_xfer; 3783 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3784 3785 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3786 3787 if (sc->sc_dying) { 3788 return; 3789 } 3790 3791 usb_init_task(&xfer->ux_aborttask, xhci_timeout_task, addr, 3792 USB_TASKQ_MPSAFE); 3793 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xfer->ux_aborttask, 3794 USB_TASKQ_HC); 3795 } 3796 3797 static void 3798 xhci_timeout_task(void *addr) 3799 { 3800 struct usbd_xfer * const xfer = addr; 3801 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3802 3803 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3804 3805 mutex_enter(&sc->sc_lock); 3806 #if 0 3807 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3808 #else 3809 xfer->ux_status = USBD_TIMEOUT; 3810 usb_transfer_complete(xfer); 3811 #endif 3812 mutex_exit(&sc->sc_lock); 3813 } 3814
Indexes created Wed Oct 01 18:09:54 GMT 2025