xhci.c revision 1.28.2.74
1 /* $NetBSD: xhci.c,v 1.28.2.74 2016/06/10 14:53:31 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.28.2.74 2016/06/10 14:53:31 skrll Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static void xhci_host_dequeue(struct xhci_ring * const); 146 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 147 148 static usbd_status xhci_do_command(struct xhci_softc * const, 149 struct xhci_trb * const, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 153 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 154 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 155 static usbd_status xhci_enable_slot(struct xhci_softc * const, 156 uint8_t * const); 157 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 158 static usbd_status xhci_address_device(struct xhci_softc * const, 159 uint64_t, uint8_t, bool); 160 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 161 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 162 struct xhci_slot * const, u_int); 163 static usbd_status xhci_ring_init(struct xhci_softc * const, 164 struct xhci_ring * const, size_t, size_t); 165 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 166 167 static void xhci_setup_ctx(struct usbd_pipe *); 168 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 169 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 170 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 171 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 172 173 static void xhci_noop(struct usbd_pipe *); 174 175 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 176 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 177 static void xhci_root_intr_abort(struct usbd_xfer *); 178 static void xhci_root_intr_close(struct usbd_pipe *); 179 static void xhci_root_intr_done(struct usbd_xfer *); 180 181 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 182 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 183 static void xhci_device_ctrl_abort(struct usbd_xfer *); 184 static void xhci_device_ctrl_close(struct usbd_pipe *); 185 static void xhci_device_ctrl_done(struct usbd_xfer *); 186 187 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 188 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 189 static void xhci_device_intr_abort(struct usbd_xfer *); 190 static void xhci_device_intr_close(struct usbd_pipe *); 191 static void xhci_device_intr_done(struct usbd_xfer *); 192 193 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 194 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 195 static void xhci_device_bulk_abort(struct usbd_xfer *); 196 static void xhci_device_bulk_close(struct usbd_pipe *); 197 static void xhci_device_bulk_done(struct usbd_xfer *); 198 199 static void xhci_timeout(void *); 200 static void xhci_timeout_task(void *); 201 202 static const struct usbd_bus_methods xhci_bus_methods = { 203 .ubm_open = xhci_open, 204 .ubm_softint = xhci_softintr, 205 .ubm_dopoll = xhci_poll, 206 .ubm_allocx = xhci_allocx, 207 .ubm_freex = xhci_freex, 208 .ubm_getlock = xhci_get_lock, 209 .ubm_newdev = xhci_new_device, 210 .ubm_rhctrl = xhci_roothub_ctrl, 211 }; 212 213 static const struct usbd_pipe_methods xhci_root_intr_methods = { 214 .upm_transfer = xhci_root_intr_transfer, 215 .upm_start = xhci_root_intr_start, 216 .upm_abort = xhci_root_intr_abort, 217 .upm_close = xhci_root_intr_close, 218 .upm_cleartoggle = xhci_noop, 219 .upm_done = xhci_root_intr_done, 220 }; 221 222 223 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 224 .upm_transfer = xhci_device_ctrl_transfer, 225 .upm_start = xhci_device_ctrl_start, 226 .upm_abort = xhci_device_ctrl_abort, 227 .upm_close = xhci_device_ctrl_close, 228 .upm_cleartoggle = xhci_noop, 229 .upm_done = xhci_device_ctrl_done, 230 }; 231 232 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 233 .upm_cleartoggle = xhci_noop, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 237 .upm_transfer = xhci_device_bulk_transfer, 238 .upm_start = xhci_device_bulk_start, 239 .upm_abort = xhci_device_bulk_abort, 240 .upm_close = xhci_device_bulk_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_bulk_done, 243 }; 244 245 static const struct usbd_pipe_methods xhci_device_intr_methods = { 246 .upm_transfer = xhci_device_intr_transfer, 247 .upm_start = xhci_device_intr_start, 248 .upm_abort = xhci_device_intr_abort, 249 .upm_close = xhci_device_intr_close, 250 .upm_cleartoggle = xhci_noop, 251 .upm_done = xhci_device_intr_done, 252 }; 253 254 static inline uint32_t 255 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 256 { 257 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 258 } 259 260 static inline uint32_t 261 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 262 { 263 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 264 } 265 266 static inline void 267 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 268 uint32_t value) 269 { 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 271 } 272 273 #if 0 /* unused */ 274 static inline void 275 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 276 uint32_t value) 277 { 278 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 279 } 280 #endif /* unused */ 281 282 static inline uint32_t 283 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 284 { 285 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 286 } 287 288 static inline uint32_t 289 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 290 { 291 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 292 } 293 294 static inline void 295 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 296 uint32_t value) 297 { 298 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 299 } 300 301 static inline uint64_t 302 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 303 { 304 uint64_t value; 305 306 if (sc->sc_ac64) { 307 #ifdef XHCI_USE_BUS_SPACE_8 308 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 309 #else 310 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 311 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 312 offset + 4) << 32; 313 #endif 314 } else { 315 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 316 } 317 318 return value; 319 } 320 321 static inline void 322 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 336 } 337 } 338 339 static inline uint32_t 340 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 341 { 342 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 343 } 344 345 static inline void 346 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 347 uint32_t value) 348 { 349 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 350 } 351 352 #if 0 /* unused */ 353 static inline uint64_t 354 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 355 { 356 uint64_t value; 357 358 if (sc->sc_ac64) { 359 #ifdef XHCI_USE_BUS_SPACE_8 360 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 361 #else 362 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 363 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 364 offset + 4) << 32; 365 #endif 366 } else { 367 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 368 } 369 370 return value; 371 } 372 #endif /* unused */ 373 374 static inline void 375 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 376 uint64_t value) 377 { 378 if (sc->sc_ac64) { 379 #ifdef XHCI_USE_BUS_SPACE_8 380 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 381 #else 382 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 383 (value >> 0) & 0xffffffff); 384 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 385 (value >> 32) & 0xffffffff); 386 #endif 387 } else { 388 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 389 } 390 } 391 392 #if 0 /* unused */ 393 static inline uint32_t 394 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 395 { 396 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 397 } 398 #endif /* unused */ 399 400 static inline void 401 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 402 uint32_t value) 403 { 404 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 405 } 406 407 /* --- */ 408 409 static inline uint8_t 410 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 411 { 412 u_int eptype = 0; 413 414 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 415 case UE_CONTROL: 416 eptype = 0x0; 417 break; 418 case UE_ISOCHRONOUS: 419 eptype = 0x1; 420 break; 421 case UE_BULK: 422 eptype = 0x2; 423 break; 424 case UE_INTERRUPT: 425 eptype = 0x3; 426 break; 427 } 428 429 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 430 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 431 return eptype | 0x4; 432 else 433 return eptype; 434 } 435 436 static u_int 437 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 438 { 439 /* xHCI 1.0 section 4.5.1 */ 440 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 441 u_int in = 0; 442 443 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 444 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 445 in = 1; 446 447 return epaddr * 2 + in; 448 } 449 450 static inline u_int 451 xhci_dci_to_ici(const u_int i) 452 { 453 return i + 1; 454 } 455 456 static inline void * 457 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 458 const u_int dci) 459 { 460 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 461 } 462 463 #if 0 /* unused */ 464 static inline bus_addr_t 465 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 466 const u_int dci) 467 { 468 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 469 } 470 #endif /* unused */ 471 472 static inline void * 473 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline bus_addr_t 480 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 481 const u_int ici) 482 { 483 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 484 } 485 486 static inline struct xhci_trb * 487 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 488 { 489 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 490 } 491 492 static inline bus_addr_t 493 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 494 { 495 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 496 } 497 498 static inline void 499 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 500 uint32_t control) 501 { 502 trb->trb_0 = htole64(parameter); 503 trb->trb_2 = htole32(status); 504 trb->trb_3 = htole32(control); 505 } 506 507 static int 508 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 509 { 510 /* base address of TRBs */ 511 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 512 513 /* trb_0 range sanity check */ 514 if (trb_0 == 0 || trb_0 < trbp || 515 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 516 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 517 return 1; 518 } 519 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 520 return 0; 521 } 522 523 /* --- */ 524 525 void 526 xhci_childdet(device_t self, device_t child) 527 { 528 struct xhci_softc * const sc = device_private(self); 529 530 KASSERT(sc->sc_child == child); 531 if (child == sc->sc_child) 532 sc->sc_child = NULL; 533 } 534 535 int 536 xhci_detach(struct xhci_softc *sc, int flags) 537 { 538 int rv = 0; 539 540 if (sc->sc_child != NULL) 541 rv = config_detach(sc->sc_child, flags); 542 543 if (rv != 0) 544 return rv; 545 546 /* XXX unconfigure/free slots */ 547 548 /* verify: */ 549 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 550 xhci_op_write_4(sc, XHCI_USBCMD, 0); 551 /* do we need to wait for stop? */ 552 553 xhci_op_write_8(sc, XHCI_CRCR, 0); 554 xhci_ring_free(sc, &sc->sc_cr); 555 cv_destroy(&sc->sc_command_cv); 556 cv_destroy(&sc->sc_cmdbusy_cv); 557 558 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 559 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 560 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 561 xhci_ring_free(sc, &sc->sc_er); 562 563 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 564 565 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 566 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 567 568 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 569 570 mutex_destroy(&sc->sc_lock); 571 mutex_destroy(&sc->sc_intr_lock); 572 573 pool_cache_destroy(sc->sc_xferpool); 574 575 return rv; 576 } 577 578 int 579 xhci_activate(device_t self, enum devact act) 580 { 581 struct xhci_softc * const sc = device_private(self); 582 583 switch (act) { 584 case DVACT_DEACTIVATE: 585 sc->sc_dying = true; 586 return 0; 587 default: 588 return EOPNOTSUPP; 589 } 590 } 591 592 bool 593 xhci_suspend(device_t dv, const pmf_qual_t *qual) 594 { 595 return false; 596 } 597 598 bool 599 xhci_resume(device_t dv, const pmf_qual_t *qual) 600 { 601 return false; 602 } 603 604 bool 605 xhci_shutdown(device_t self, int flags) 606 { 607 return false; 608 } 609 610 static int 611 xhci_hc_reset(struct xhci_softc * const sc) 612 { 613 uint32_t usbcmd, usbsts; 614 int i; 615 616 /* Check controller not ready */ 617 for (i = 0; i < XHCI_WAIT_CNR; i++) { 618 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 619 if ((usbsts & XHCI_STS_CNR) == 0) 620 break; 621 usb_delay_ms(&sc->sc_bus, 1); 622 } 623 if (i >= XHCI_WAIT_CNR) { 624 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 625 return EIO; 626 } 627 628 /* Halt controller */ 629 usbcmd = 0; 630 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 631 usb_delay_ms(&sc->sc_bus, 1); 632 633 /* Reset controller */ 634 usbcmd = XHCI_CMD_HCRST; 635 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 636 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 637 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 638 if ((usbcmd & XHCI_CMD_HCRST) == 0) 639 break; 640 usb_delay_ms(&sc->sc_bus, 1); 641 } 642 if (i >= XHCI_WAIT_HCRST) { 643 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 644 return EIO; 645 } 646 647 /* Check controller not ready */ 648 for (i = 0; i < XHCI_WAIT_CNR; i++) { 649 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 650 if ((usbsts & XHCI_STS_CNR) == 0) 651 break; 652 usb_delay_ms(&sc->sc_bus, 1); 653 } 654 if (i >= XHCI_WAIT_CNR) { 655 aprint_error_dev(sc->sc_dev, 656 "controller not ready timeout after reset\n"); 657 return EIO; 658 } 659 660 return 0; 661 } 662 663 664 static void 665 hexdump(const char *msg, const void *base, size_t len) 666 { 667 #if 0 668 size_t cnt; 669 const uint32_t *p; 670 extern paddr_t vtophys(vaddr_t); 671 672 p = base; 673 cnt = 0; 674 675 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 676 (void *)vtophys((vaddr_t)base)); 677 678 while (cnt < len) { 679 if (cnt % 16 == 0) 680 printf("%p: ", p); 681 else if (cnt % 8 == 0) 682 printf(" |"); 683 printf(" %08x", *p++); 684 cnt += 4; 685 if (cnt % 16 == 0) 686 printf("\n"); 687 } 688 if (cnt % 16 != 0) 689 printf("\n"); 690 #endif 691 } 692 693 /* Process extended capabilities */ 694 static void 695 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 696 { 697 uint32_t ecp, ecr; 698 699 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 700 701 ecp = XHCI_HCC_XECP(hcc) * 4; 702 while (ecp != 0) { 703 ecr = xhci_read_4(sc, ecp); 704 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 705 switch (XHCI_XECP_ID(ecr)) { 706 case XHCI_ID_PROTOCOLS: { 707 uint32_t w4, w8, wc; 708 uint16_t w2; 709 w2 = (ecr >> 16) & 0xffff; 710 w4 = xhci_read_4(sc, ecp + 4); 711 w8 = xhci_read_4(sc, ecp + 8); 712 wc = xhci_read_4(sc, ecp + 0xc); 713 aprint_debug_dev(sc->sc_dev, 714 " SP: %08x %08x %08x %08x\n", ecr, w4, w8, wc); 715 /* unused */ 716 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0300) { 717 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 718 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 719 } 720 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0200) { 721 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 722 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 723 } 724 break; 725 } 726 case XHCI_ID_USB_LEGACY: { 727 uint8_t bios_sem; 728 729 /* Take host controller ownership from BIOS */ 730 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 731 if (bios_sem) { 732 /* sets xHCI to be owned by OS */ 733 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 734 aprint_debug_dev(sc->sc_dev, 735 "waiting for BIOS to give up control\n"); 736 for (int i = 0; i < 5000; i++) { 737 bios_sem = xhci_read_1(sc, ecp + 738 XHCI_XECP_BIOS_SEM); 739 if (bios_sem == 0) 740 break; 741 DELAY(1000); 742 } 743 if (bios_sem) { 744 aprint_error_dev(sc->sc_dev, 745 "timed out waiting for BIOS\n"); 746 } 747 } 748 break; 749 } 750 default: 751 break; 752 } 753 ecr = xhci_read_4(sc, ecp); 754 if (XHCI_XECP_NEXT(ecr) == 0) { 755 ecp = 0; 756 } else { 757 ecp += XHCI_XECP_NEXT(ecr) * 4; 758 } 759 } 760 } 761 762 #define XHCI_HCCPREV1_BITS \ 763 "\177\020" /* New bitmask */ \ 764 "f\020\020XECP\0" \ 765 "f\014\4MAXPSA\0" \ 766 "b\013CFC\0" \ 767 "b\012SEC\0" \ 768 "b\011SBD\0" \ 769 "b\010FSE\0" \ 770 "b\7NSS\0" \ 771 "b\6LTC\0" \ 772 "b\5LHRC\0" \ 773 "b\4PIND\0" \ 774 "b\3PPC\0" \ 775 "b\2CZC\0" \ 776 "b\1BNC\0" \ 777 "b\0AC64\0" \ 778 "\0" 779 #define XHCI_HCCV1_x_BITS \ 780 "\177\020" /* New bitmask */ \ 781 "f\020\020XECP\0" \ 782 "f\014\4MAXPSA\0" \ 783 "b\013CFC\0" \ 784 "b\012SEC\0" \ 785 "b\011SPC\0" \ 786 "b\010PAE\0" \ 787 "b\7NSS\0" \ 788 "b\6LTC\0" \ 789 "b\5LHRC\0" \ 790 "b\4PIND\0" \ 791 "b\3PPC\0" \ 792 "b\2CSZ\0" \ 793 "b\1BNC\0" \ 794 "b\0AC64\0" \ 795 "\0" 796 797 int 798 xhci_init(struct xhci_softc *sc) 799 { 800 bus_size_t bsz; 801 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 802 uint32_t pagesize, config; 803 int i = 0; 804 uint16_t hciversion; 805 uint8_t caplength; 806 807 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 808 809 sc->sc_bus.ub_revision = USBREV_3_0; 810 sc->sc_bus.ub_usedma = true; 811 812 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 813 caplength = XHCI_CAP_CAPLENGTH(cap); 814 hciversion = XHCI_CAP_HCIVERSION(cap); 815 816 if (hciversion < XHCI_HCIVERSION_0_96 || 817 hciversion > XHCI_HCIVERSION_1_0) { 818 aprint_normal_dev(sc->sc_dev, 819 "xHCI version %x.%x not known to be supported\n", 820 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 821 } else { 822 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 823 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 824 } 825 826 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 827 &sc->sc_cbh) != 0) { 828 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 829 return ENOMEM; 830 } 831 832 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 833 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 834 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 835 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 836 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 837 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 838 aprint_debug_dev(sc->sc_dev, 839 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 840 841 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 842 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 843 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 844 845 char sbuf[128]; 846 if (hciversion < XHCI_HCIVERSION_1_0) 847 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 848 else 849 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 850 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 851 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 852 853 /* print PSI and take ownership from BIOS */ 854 xhci_ecp(sc, hcc); 855 856 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 857 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 858 &sc->sc_obh) != 0) { 859 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 860 return ENOMEM; 861 } 862 863 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 864 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 865 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 866 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 867 return ENOMEM; 868 } 869 870 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 871 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 872 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 873 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 874 return ENOMEM; 875 } 876 877 int rv; 878 rv = xhci_hc_reset(sc); 879 if (rv != 0) { 880 return rv; 881 } 882 883 if (sc->sc_vendor_init) 884 sc->sc_vendor_init(sc); 885 886 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 887 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 888 pagesize = ffs(pagesize); 889 if (pagesize == 0) { 890 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 891 return EIO; 892 } 893 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 894 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 895 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 896 (uint32_t)sc->sc_maxslots); 897 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 898 899 usbd_status err; 900 901 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 902 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 903 if (sc->sc_maxspbuf != 0) { 904 err = usb_allocmem(&sc->sc_bus, 905 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 906 &sc->sc_spbufarray_dma); 907 if (err) { 908 aprint_error_dev(sc->sc_dev, 909 "spbufarray init fail, err %d\n", err); 910 return ENOMEM; 911 } 912 913 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 914 sc->sc_maxspbuf, KM_SLEEP); 915 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 916 for (i = 0; i < sc->sc_maxspbuf; i++) { 917 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 918 /* allocate contexts */ 919 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 920 sc->sc_pgsz, dma); 921 if (err) { 922 aprint_error_dev(sc->sc_dev, 923 "spbufarray_dma init fail, err %d\n", err); 924 rv = ENOMEM; 925 goto bad1; 926 } 927 spbufarray[i] = htole64(DMAADDR(dma, 0)); 928 usb_syncmem(dma, 0, sc->sc_pgsz, 929 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 930 } 931 932 usb_syncmem(&sc->sc_spbufarray_dma, 0, 933 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 934 } 935 936 config = xhci_op_read_4(sc, XHCI_CONFIG); 937 config &= ~0xFF; 938 config |= sc->sc_maxslots & 0xFF; 939 xhci_op_write_4(sc, XHCI_CONFIG, config); 940 941 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 942 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 943 if (err) { 944 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 945 err); 946 rv = ENOMEM; 947 goto bad1; 948 } 949 950 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 951 XHCI_EVENT_RING_SEGMENTS_ALIGN); 952 if (err) { 953 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 954 err); 955 rv = ENOMEM; 956 goto bad2; 957 } 958 959 usb_dma_t *dma; 960 size_t size; 961 size_t align; 962 963 dma = &sc->sc_eventst_dma; 964 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 965 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 966 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 967 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 968 err = usb_allocmem(&sc->sc_bus, size, align, dma); 969 if (err) { 970 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 971 err); 972 rv = ENOMEM; 973 goto bad3; 974 } 975 976 memset(KERNADDR(dma, 0), 0, size); 977 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 978 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 979 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 980 KERNADDR(&sc->sc_eventst_dma, 0), 981 sc->sc_eventst_dma.udma_block->size); 982 983 dma = &sc->sc_dcbaa_dma; 984 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 985 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 986 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 987 err = usb_allocmem(&sc->sc_bus, size, align, dma); 988 if (err) { 989 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 990 rv = ENOMEM; 991 goto bad4; 992 } 993 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 994 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 995 KERNADDR(&sc->sc_dcbaa_dma, 0), 996 sc->sc_dcbaa_dma.udma_block->size); 997 998 memset(KERNADDR(dma, 0), 0, size); 999 if (sc->sc_maxspbuf != 0) { 1000 /* 1001 * DCBA entry 0 hold the scratchbuf array pointer. 1002 */ 1003 *(uint64_t *)KERNADDR(dma, 0) = 1004 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1005 } 1006 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1007 1008 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1009 KM_SLEEP); 1010 if (sc->sc_slots == NULL) { 1011 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1012 rv = ENOMEM; 1013 goto bad; 1014 } 1015 1016 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1017 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1018 if (sc->sc_xferpool == NULL) { 1019 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1020 err); 1021 rv = ENOMEM; 1022 goto bad; 1023 } 1024 1025 cv_init(&sc->sc_command_cv, "xhcicmd"); 1026 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1027 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1028 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1029 1030 /* Set up the bus struct. */ 1031 sc->sc_bus.ub_methods = &xhci_bus_methods; 1032 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 1033 1034 struct xhci_erste *erst; 1035 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1036 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1037 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1038 erst[0].erste_3 = htole32(0); 1039 usb_syncmem(&sc->sc_eventst_dma, 0, 1040 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1041 1042 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1043 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1044 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1045 XHCI_ERDP_LO_BUSY); 1046 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1047 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1048 sc->sc_cr.xr_cs); 1049 1050 #if 0 1051 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1052 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1053 #endif 1054 1055 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1056 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1057 /* Intel xhci needs interrupt rate moderated. */ 1058 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1059 else 1060 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1061 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 1062 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1063 1064 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 1065 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1066 xhci_op_read_4(sc, XHCI_USBCMD)); 1067 1068 return 0; 1069 1070 bad: 1071 if (sc->sc_xferpool) { 1072 pool_cache_destroy(sc->sc_xferpool); 1073 sc->sc_xferpool = NULL; 1074 } 1075 1076 if (sc->sc_slots) { 1077 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1078 sc->sc_maxslots); 1079 sc->sc_slots = NULL; 1080 } 1081 1082 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1083 bad4: 1084 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1085 bad3: 1086 xhci_ring_free(sc, &sc->sc_er); 1087 bad2: 1088 xhci_ring_free(sc, &sc->sc_cr); 1089 i = sc->sc_maxspbuf; 1090 bad1: 1091 for (int j = 0; j < i; j++) 1092 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1093 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1094 1095 return rv; 1096 } 1097 1098 int 1099 xhci_intr(void *v) 1100 { 1101 struct xhci_softc * const sc = v; 1102 int ret = 0; 1103 1104 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1105 1106 if (sc == NULL) 1107 return 0; 1108 1109 mutex_spin_enter(&sc->sc_intr_lock); 1110 1111 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1112 goto done; 1113 1114 /* If we get an interrupt while polling, then just ignore it. */ 1115 if (sc->sc_bus.ub_usepolling) { 1116 #ifdef DIAGNOSTIC 1117 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1118 #endif 1119 goto done; 1120 } 1121 1122 ret = xhci_intr1(sc); 1123 done: 1124 mutex_spin_exit(&sc->sc_intr_lock); 1125 return ret; 1126 } 1127 1128 int 1129 xhci_intr1(struct xhci_softc * const sc) 1130 { 1131 uint32_t usbsts; 1132 uint32_t iman; 1133 1134 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1135 1136 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1137 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1138 #if 0 1139 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1140 return 0; 1141 } 1142 #endif 1143 xhci_op_write_4(sc, XHCI_USBSTS, 1144 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1145 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1146 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1147 1148 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1149 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1150 iman |= XHCI_IMAN_INTR_PEND; 1151 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1152 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1153 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1154 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1155 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1156 1157 usb_schedsoftintr(&sc->sc_bus); 1158 1159 return 1; 1160 } 1161 1162 /* 1163 * 3 port speed types used in USB stack 1164 * 1165 * usbdi speed 1166 * definition: USB_SPEED_* in usb.h 1167 * They are used in struct usbd_device in USB stack. 1168 * ioctl interface uses these values too. 1169 * port_status speed 1170 * definition: UPS_*_SPEED in usb.h 1171 * They are used in usb_port_status_t and valid only for USB 2.0. 1172 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1173 * of usb_port_status_ext_t indicates port speed. 1174 * Note that some 3.0 values overlap with 2.0 values. 1175 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1176 * means UPS_LOW_SPEED in HS.) 1177 * port status returned from hub also uses these values. 1178 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1179 * or more. 1180 * xspeed: 1181 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1182 * They are used in only slot context and PORTSC reg of xhci. 1183 * The difference between usbdi speed and xspeed is 1184 * that FS and LS values are swapped. 1185 */ 1186 1187 /* convert usbdi speed to xspeed */ 1188 static int 1189 xhci_speed2xspeed(int speed) 1190 { 1191 switch (speed) { 1192 case USB_SPEED_LOW: return 2; 1193 case USB_SPEED_FULL: return 1; 1194 default: return speed; 1195 } 1196 } 1197 1198 #if 0 1199 /* convert xspeed to usbdi speed */ 1200 static int 1201 xhci_xspeed2speed(int xspeed) 1202 { 1203 switch (xspeed) { 1204 case 1: return USB_SPEED_FULL; 1205 case 2: return USB_SPEED_LOW; 1206 default: return xspeed; 1207 } 1208 } 1209 #endif 1210 1211 /* convert xspeed to port status speed */ 1212 static int 1213 xhci_xspeed2psspeed(int xspeed) 1214 { 1215 switch (xspeed) { 1216 case 0: return 0; 1217 case 1: return UPS_FULL_SPEED; 1218 case 2: return UPS_LOW_SPEED; 1219 case 3: return UPS_HIGH_SPEED; 1220 default: return UPS_OTHER_SPEED; 1221 } 1222 } 1223 1224 /* 1225 * Construct input contexts and issue TRB to open pipe. 1226 */ 1227 static usbd_status 1228 xhci_configure_endpoint(struct usbd_pipe *pipe) 1229 { 1230 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1231 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1232 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1233 struct xhci_trb trb; 1234 usbd_status err; 1235 1236 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1237 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1238 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1239 pipe->up_endpoint->ue_edesc->bmAttributes); 1240 1241 KASSERT(!mutex_owned(&sc->sc_lock)); 1242 1243 /* XXX ensure input context is available? */ 1244 1245 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1246 1247 /* set up context */ 1248 xhci_setup_ctx(pipe); 1249 1250 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1251 sc->sc_ctxsz * 1); 1252 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1253 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1254 1255 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1256 trb.trb_2 = 0; 1257 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1258 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1259 1260 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1261 1262 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1263 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1264 sc->sc_ctxsz * 1); 1265 1266 return err; 1267 } 1268 1269 #if 0 1270 static usbd_status 1271 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1272 { 1273 #ifdef USB_DEBUG 1274 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1275 #endif 1276 1277 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1278 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1279 1280 return USBD_NORMAL_COMPLETION; 1281 } 1282 #endif 1283 1284 /* 4.6.8, 6.4.3.7 */ 1285 static usbd_status 1286 xhci_reset_endpoint(struct usbd_pipe *pipe) 1287 { 1288 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1289 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1290 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1291 struct xhci_trb trb; 1292 usbd_status err; 1293 1294 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1295 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1296 1297 KASSERT(!mutex_owned(&sc->sc_lock)); 1298 1299 trb.trb_0 = 0; 1300 trb.trb_2 = 0; 1301 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1302 XHCI_TRB_3_EP_SET(dci) | 1303 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1304 1305 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1306 1307 return err; 1308 } 1309 1310 /* 1311 * 4.6.9, 6.4.3.8 1312 * Stop execution of TDs on xfer ring. 1313 * Should be called with sc_lock held. 1314 */ 1315 static usbd_status 1316 xhci_stop_endpoint(struct usbd_pipe *pipe) 1317 { 1318 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1319 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1320 struct xhci_trb trb; 1321 usbd_status err; 1322 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1323 1324 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1325 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1326 1327 KASSERT(mutex_owned(&sc->sc_lock)); 1328 1329 trb.trb_0 = 0; 1330 trb.trb_2 = 0; 1331 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1332 XHCI_TRB_3_EP_SET(dci) | 1333 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1334 1335 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1336 1337 return err; 1338 } 1339 1340 /* 1341 * Set TR Dequeue Pointer. 1342 * xHCI 1.1 4.6.10 6.4.3.9 1343 * Purge all of the TRBs on ring and reinitialize ring. 1344 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1345 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1346 * error will be generated. 1347 */ 1348 static usbd_status 1349 xhci_set_dequeue(struct usbd_pipe *pipe) 1350 { 1351 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1352 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1353 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1354 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1355 struct xhci_trb trb; 1356 usbd_status err; 1357 1358 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1359 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1360 1361 xhci_host_dequeue(xr); 1362 1363 /* set DCS */ 1364 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1365 trb.trb_2 = 0; 1366 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1367 XHCI_TRB_3_EP_SET(dci) | 1368 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1369 1370 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1371 1372 return err; 1373 } 1374 1375 /* 1376 * Open new pipe: called from usbd_setup_pipe_flags. 1377 * Fills methods of pipe. 1378 * If pipe is not for ep0, calls configure_endpoint. 1379 */ 1380 static usbd_status 1381 xhci_open(struct usbd_pipe *pipe) 1382 { 1383 struct usbd_device * const dev = pipe->up_dev; 1384 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1385 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1386 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1387 1388 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1389 DPRINTFN(1, "addr %d depth %d port %d speed %d", dev->ud_addr, 1390 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1391 DPRINTFN(1, " dci %u type 0x%02x epaddr 0x%02x attr 0x%02x", 1392 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1393 ed->bmAttributes); 1394 DPRINTFN(1, " mps %u ival %u", UGETW(ed->wMaxPacketSize), ed->bInterval, 1395 0, 0); 1396 1397 if (sc->sc_dying) 1398 return USBD_IOERROR; 1399 1400 /* Root Hub */ 1401 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1402 switch (ed->bEndpointAddress) { 1403 case USB_CONTROL_ENDPOINT: 1404 pipe->up_methods = &roothub_ctrl_methods; 1405 break; 1406 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1407 pipe->up_methods = &xhci_root_intr_methods; 1408 break; 1409 default: 1410 pipe->up_methods = NULL; 1411 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1412 ed->bEndpointAddress, 0, 0, 0); 1413 return USBD_INVAL; 1414 } 1415 return USBD_NORMAL_COMPLETION; 1416 } 1417 1418 switch (xfertype) { 1419 case UE_CONTROL: 1420 pipe->up_methods = &xhci_device_ctrl_methods; 1421 break; 1422 case UE_ISOCHRONOUS: 1423 pipe->up_methods = &xhci_device_isoc_methods; 1424 return USBD_INVAL; 1425 break; 1426 case UE_BULK: 1427 pipe->up_methods = &xhci_device_bulk_methods; 1428 break; 1429 case UE_INTERRUPT: 1430 pipe->up_methods = &xhci_device_intr_methods; 1431 break; 1432 default: 1433 return USBD_IOERROR; 1434 break; 1435 } 1436 1437 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1438 return xhci_configure_endpoint(pipe); 1439 1440 return USBD_NORMAL_COMPLETION; 1441 } 1442 1443 /* 1444 * Closes pipe, called from usbd_kill_pipe via close methods. 1445 * If the endpoint to be closed is ep0, disable_slot. 1446 * Should be called with sc_lock held. 1447 */ 1448 static void 1449 xhci_close_pipe(struct usbd_pipe *pipe) 1450 { 1451 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1452 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1453 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1454 const u_int dci = xhci_ep_get_dci(ed); 1455 struct xhci_trb trb; 1456 uint32_t *cp; 1457 1458 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1459 1460 if (sc->sc_dying) 1461 return; 1462 1463 /* xs is uninitialized before xhci_init_slot */ 1464 if (xs == NULL || xs->xs_idx == 0) 1465 return; 1466 1467 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1468 1469 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1470 KASSERT(mutex_owned(&sc->sc_lock)); 1471 1472 if (pipe->up_dev->ud_depth == 0) 1473 return; 1474 1475 if (dci == XHCI_DCI_EP_CONTROL) { 1476 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1477 xhci_disable_slot(sc, xs->xs_idx); 1478 return; 1479 } 1480 1481 /* 1482 * This may fail in the case that xhci_close_pipe is called after 1483 * xhci_abort_xfer e.g. usbd_kill_pipe. 1484 */ 1485 (void)xhci_stop_endpoint(pipe); 1486 1487 /* 1488 * set appropriate bit to be dropped. 1489 * don't set DC bit to 1, otherwise all endpoints 1490 * would be deconfigured. 1491 */ 1492 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1493 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1494 cp[1] = htole32(0); 1495 1496 /* XXX should be most significant one, not dci? */ 1497 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1498 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1499 1500 /* configure ep context performs an implicit dequeue */ 1501 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 1502 1503 /* sync input contexts before they are read from memory */ 1504 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1505 1506 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1507 trb.trb_2 = 0; 1508 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1509 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1510 1511 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1512 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1513 } 1514 1515 /* 1516 * Abort transfer. 1517 * May be called from softintr context. 1518 */ 1519 static void 1520 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1521 { 1522 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1523 1524 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1525 DPRINTFN(4, "xfer %p pipe %p status %d", 1526 xfer, xfer->ux_pipe, status, 0); 1527 1528 KASSERT(mutex_owned(&sc->sc_lock)); 1529 1530 if (sc->sc_dying) { 1531 /* If we're dying, just do the software part. */ 1532 DPRINTFN(4, "xfer %p dying %u", xfer, xfer->ux_status, 0, 0); 1533 xfer->ux_status = status; 1534 callout_stop(&xfer->ux_callout); 1535 usb_transfer_complete(xfer); 1536 return; 1537 } 1538 1539 /* XXX need more stuff */ 1540 xfer->ux_status = status; 1541 callout_stop(&xfer->ux_callout); 1542 usb_transfer_complete(xfer); 1543 DPRINTFN(14, "end", 0, 0, 0, 0); 1544 1545 KASSERT(mutex_owned(&sc->sc_lock)); 1546 } 1547 1548 static void 1549 xhci_host_dequeue(struct xhci_ring * const xr) 1550 { 1551 /* When dequeueing the controller, update our struct copy too */ 1552 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1553 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1554 BUS_DMASYNC_PREWRITE); 1555 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1556 1557 xr->xr_ep = 0; 1558 xr->xr_cs = 1; 1559 } 1560 1561 /* 1562 * Recover STALLed endpoint. 1563 * xHCI 1.1 sect 4.10.2.1 1564 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1565 * all transfers on transfer ring. 1566 * These are done in thread context asynchronously. 1567 */ 1568 static void 1569 xhci_clear_endpoint_stall_async_task(void *cookie) 1570 { 1571 struct usbd_xfer * const xfer = cookie; 1572 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1573 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1574 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1575 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1576 1577 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1578 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1579 1580 xhci_reset_endpoint(xfer->ux_pipe); 1581 xhci_set_dequeue(xfer->ux_pipe); 1582 1583 mutex_enter(&sc->sc_lock); 1584 tr->is_halted = false; 1585 usb_transfer_complete(xfer); 1586 mutex_exit(&sc->sc_lock); 1587 DPRINTFN(4, "ends", 0, 0, 0, 0); 1588 } 1589 1590 static usbd_status 1591 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1592 { 1593 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1594 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1595 1596 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1597 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1598 1599 if (sc->sc_dying) { 1600 return USBD_IOERROR; 1601 } 1602 1603 usb_init_task(&xp->xp_async_task, 1604 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1605 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1606 DPRINTFN(4, "ends", 0, 0, 0, 0); 1607 1608 return USBD_NORMAL_COMPLETION; 1609 } 1610 1611 /* Process roothub port status/change events and notify to uhub_intr. */ 1612 static void 1613 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1614 { 1615 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1616 uint8_t *p; 1617 1618 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1619 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1620 port, 0, 0); 1621 1622 if (xfer == NULL) 1623 return; 1624 1625 if (port > sc->sc_maxports) 1626 return; 1627 1628 p = xfer->ux_buf; 1629 memset(p, 0, xfer->ux_length); 1630 p[port/NBBY] |= 1 << (port%NBBY); 1631 xfer->ux_actlen = xfer->ux_length; 1632 xfer->ux_status = USBD_NORMAL_COMPLETION; 1633 usb_transfer_complete(xfer); 1634 } 1635 1636 /* Process Transfer Events */ 1637 static void 1638 xhci_event_transfer(struct xhci_softc * const sc, 1639 const struct xhci_trb * const trb) 1640 { 1641 uint64_t trb_0; 1642 uint32_t trb_2, trb_3; 1643 uint8_t trbcode; 1644 u_int slot, dci; 1645 struct xhci_slot *xs; 1646 struct xhci_ring *xr; 1647 struct xhci_xfer *xx; 1648 struct usbd_xfer *xfer; 1649 usbd_status err; 1650 1651 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1652 1653 trb_0 = le64toh(trb->trb_0); 1654 trb_2 = le32toh(trb->trb_2); 1655 trb_3 = le32toh(trb->trb_3); 1656 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1657 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1658 dci = XHCI_TRB_3_EP_GET(trb_3); 1659 xs = &sc->sc_slots[slot]; 1660 xr = &xs->xs_ep[dci].xe_tr; 1661 1662 /* sanity check */ 1663 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1664 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1665 1666 int idx = 0; 1667 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1668 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1669 DPRINTFN(0, "invalid trb_0 0x%"PRIx64, trb_0, 0, 0, 0); 1670 return; 1671 } 1672 xx = xr->xr_cookies[idx]; 1673 1674 /* 1675 * If endpoint is stopped between TDs, TRB pointer points at 1676 * next TRB, however, it is not put yet or is a garbage TRB. 1677 * That's why xr_cookies may be NULL or look like broken. 1678 * Note: this ev happens only when hciversion >= 1.0 or 1679 * hciversion == 0.96 and FSE of hcc1 is set. 1680 */ 1681 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1682 DPRINTFN(1, "Ignore #%u: cookie %p cc %u dci %u", 1683 idx, xx, trbcode, dci); 1684 DPRINTFN(1, " orig TRB %"PRIx64" type %u", trb_0, 1685 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1686 0, 0); 1687 } 1688 } else { 1689 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1690 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1691 } 1692 /* XXX this may not happen */ 1693 if (xx == NULL) { 1694 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1695 return; 1696 } 1697 xfer = &xx->xx_xfer; 1698 /* XXX this may happen when detaching */ 1699 if (xfer == NULL) { 1700 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1701 xx, trb_0, 0, 0); 1702 return; 1703 } 1704 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1705 /* XXX I dunno why this happens */ 1706 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1707 1708 if (!xfer->ux_pipe->up_repeat && 1709 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1710 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1711 return; 1712 } 1713 1714 /* 4.11.5.2 Event Data TRB */ 1715 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1716 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1717 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1718 if ((trb_0 & 0x3) == 0x3) { 1719 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1720 } 1721 } 1722 1723 switch (trbcode) { 1724 case XHCI_TRB_ERROR_SHORT_PKT: 1725 case XHCI_TRB_ERROR_SUCCESS: 1726 /* 1727 * A ctrl transfer generates two events if it has a Data stage. 1728 * After a successful Data stage we cannot call call 1729 * usb_transfer_complete - this can only happen after the Data 1730 * stage. 1731 * 1732 * Note: Data and Status stage events point at same xfer. 1733 * ux_actlen and ux_dmabuf will be passed to 1734 * usb_transfer_complete after the Status stage event. 1735 * 1736 * It can be distingished which stage generates the event: 1737 * + by checking least 3 bits of trb_0 if ED==1. 1738 * (see xhci_device_ctrl_start). 1739 * + by checking the type of original TRB if ED==0. 1740 * 1741 * In addition, intr, bulk, and isoc transfer currently 1742 * consists of single TD, so the "skip" is not needed. 1743 * ctrl xfer uses EVENT_DATA, and others do not. 1744 * Thus driver can switch the flow by checking ED bit. 1745 */ 1746 xfer->ux_actlen = 1747 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1748 err = USBD_NORMAL_COMPLETION; 1749 break; 1750 case XHCI_TRB_ERROR_STALL: 1751 case XHCI_TRB_ERROR_BABBLE: 1752 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1753 xr->is_halted = true; 1754 err = USBD_STALLED; 1755 /* 1756 * Stalled endpoints can be recoverd by issuing 1757 * command TRB TYPE_RESET_EP on xHCI instead of 1758 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1759 * on the endpoint. However, this function may be 1760 * called from softint context (e.g. from umass), 1761 * in that case driver gets KASSERT in cv_timedwait 1762 * in xhci_do_command. 1763 * To avoid this, this runs reset_endpoint and 1764 * usb_transfer_complete in usb task thread 1765 * asynchronously (and then umass issues clear 1766 * UF_ENDPOINT_HALT). 1767 */ 1768 xfer->ux_status = err; 1769 callout_stop(&xfer->ux_callout); 1770 xhci_clear_endpoint_stall_async(xfer); 1771 return; 1772 default: 1773 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1774 err = USBD_IOERROR; 1775 break; 1776 } 1777 xfer->ux_status = err; 1778 1779 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1780 if ((trb_0 & 0x3) == 0x0) { 1781 callout_stop(&xfer->ux_callout); 1782 usb_transfer_complete(xfer); 1783 } 1784 } else { 1785 callout_stop(&xfer->ux_callout); 1786 usb_transfer_complete(xfer); 1787 } 1788 } 1789 1790 /* Process Command complete events */ 1791 static void 1792 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 1793 { 1794 uint64_t trb_0; 1795 uint32_t trb_2, trb_3; 1796 1797 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1798 1799 KASSERT(mutex_owned(&sc->sc_lock)); 1800 1801 trb_0 = le64toh(trb->trb_0); 1802 trb_2 = le32toh(trb->trb_2); 1803 trb_3 = le32toh(trb->trb_3); 1804 1805 if (trb_0 == sc->sc_command_addr) { 1806 sc->sc_resultpending = false; 1807 1808 sc->sc_result_trb.trb_0 = trb_0; 1809 sc->sc_result_trb.trb_2 = trb_2; 1810 sc->sc_result_trb.trb_3 = trb_3; 1811 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1812 XHCI_TRB_ERROR_SUCCESS) { 1813 DPRINTFN(1, "command completion " 1814 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1815 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1816 } 1817 cv_signal(&sc->sc_command_cv); 1818 } else { 1819 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 1820 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1821 trb_2, trb_3); 1822 } 1823 } 1824 1825 /* 1826 * Process events. 1827 * called from xhci_softintr 1828 */ 1829 static void 1830 xhci_handle_event(struct xhci_softc * const sc, 1831 const struct xhci_trb * const trb) 1832 { 1833 uint64_t trb_0; 1834 uint32_t trb_2, trb_3; 1835 1836 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1837 1838 trb_0 = le64toh(trb->trb_0); 1839 trb_2 = le32toh(trb->trb_2); 1840 trb_3 = le32toh(trb->trb_3); 1841 1842 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1843 trb, trb_0, trb_2, trb_3); 1844 1845 /* 1846 * 4.11.3.1, 6.4.2.1 1847 * TRB Pointer is invalid for these completion codes. 1848 */ 1849 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 1850 case XHCI_TRB_ERROR_RING_UNDERRUN: 1851 case XHCI_TRB_ERROR_RING_OVERRUN: 1852 case XHCI_TRB_ERROR_VF_RING_FULL: 1853 return; 1854 default: 1855 if (trb_0 == 0) { 1856 return; 1857 } 1858 break; 1859 } 1860 1861 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 1862 case XHCI_TRB_EVENT_TRANSFER: 1863 xhci_event_transfer(sc, trb); 1864 break; 1865 case XHCI_TRB_EVENT_CMD_COMPLETE: 1866 xhci_event_cmd(sc, trb); 1867 break; 1868 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1869 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1870 break; 1871 default: 1872 break; 1873 } 1874 } 1875 1876 static void 1877 xhci_softintr(void *v) 1878 { 1879 struct usbd_bus * const bus = v; 1880 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1881 struct xhci_ring * const er = &sc->sc_er; 1882 struct xhci_trb *trb; 1883 int i, j, k; 1884 1885 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1886 1887 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1888 1889 i = er->xr_ep; 1890 j = er->xr_cs; 1891 1892 DPRINTFN(16, "er: xr_ep %d xr_cs %d", i, j, 0, 0); 1893 1894 while (1) { 1895 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 1896 BUS_DMASYNC_POSTREAD); 1897 trb = &er->xr_trb[i]; 1898 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1899 1900 if (j != k) 1901 break; 1902 1903 xhci_handle_event(sc, trb); 1904 1905 i++; 1906 if (i == er->xr_ntrb) { 1907 i = 0; 1908 j ^= 1; 1909 } 1910 } 1911 1912 er->xr_ep = i; 1913 er->xr_cs = j; 1914 1915 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 1916 XHCI_ERDP_LO_BUSY); 1917 1918 DPRINTFN(16, "ends", 0, 0, 0, 0); 1919 1920 return; 1921 } 1922 1923 static void 1924 xhci_poll(struct usbd_bus *bus) 1925 { 1926 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1927 1928 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1929 1930 mutex_spin_enter(&sc->sc_intr_lock); 1931 xhci_intr1(sc); 1932 mutex_spin_exit(&sc->sc_intr_lock); 1933 1934 return; 1935 } 1936 1937 static struct usbd_xfer * 1938 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 1939 { 1940 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1941 struct usbd_xfer *xfer; 1942 1943 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1944 1945 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1946 if (xfer != NULL) { 1947 memset(xfer, 0, sizeof(struct xhci_xfer)); 1948 #ifdef DIAGNOSTIC 1949 xfer->ux_state = XFER_BUSY; 1950 #endif 1951 } 1952 1953 return xfer; 1954 } 1955 1956 static void 1957 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1958 { 1959 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1960 1961 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1962 1963 #ifdef DIAGNOSTIC 1964 if (xfer->ux_state != XFER_BUSY) { 1965 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 1966 xfer, xfer->ux_state, 0, 0); 1967 } 1968 xfer->ux_state = XFER_FREE; 1969 #endif 1970 pool_cache_put(sc->sc_xferpool, xfer); 1971 } 1972 1973 static void 1974 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1975 { 1976 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1977 1978 *lock = &sc->sc_lock; 1979 } 1980 1981 extern uint32_t usb_cookie_no; 1982 1983 /* 1984 * xHCI 4.3 1985 * Called when uhub_explore finds a new device (via usbd_new_device). 1986 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 1987 * This function does: 1988 * Allocate and construct dev structure of default endpoint (ep0). 1989 * Allocate and open pipe of ep0. 1990 * Enable slot and initialize slot context. 1991 * Set Address. 1992 * Read initial device descriptor. 1993 * Determine initial MaxPacketSize (mps) by speed. 1994 * Read full device descriptor. 1995 * Register this device. 1996 * Finally state of device transitions ADDRESSED. 1997 */ 1998 static usbd_status 1999 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2000 int speed, int port, struct usbd_port *up) 2001 { 2002 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2003 struct usbd_device *dev; 2004 usbd_status err; 2005 usb_device_descriptor_t *dd; 2006 struct xhci_slot *xs; 2007 uint32_t *cp; 2008 2009 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2010 DPRINTFN(4, "port %u depth %u speed %u up %p", port, depth, speed, up); 2011 2012 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2013 if (dev == NULL) 2014 return USBD_NOMEM; 2015 2016 dev->ud_bus = bus; 2017 dev->ud_quirks = &usbd_no_quirk; 2018 dev->ud_addr = 0; 2019 dev->ud_ddesc.bMaxPacketSize = 0; 2020 dev->ud_depth = depth; 2021 dev->ud_powersrc = up; 2022 dev->ud_myhub = up->up_parent; 2023 dev->ud_speed = speed; 2024 dev->ud_langid = USBD_NOLANG; 2025 dev->ud_cookie.cookie = ++usb_cookie_no; 2026 2027 /* Set up default endpoint handle. */ 2028 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2029 /* doesn't matter, just don't let it uninitialized */ 2030 dev->ud_ep0.ue_toggle = 0; 2031 2032 /* Set up default endpoint descriptor. */ 2033 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2034 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2035 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2036 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2037 dev->ud_ep0desc.bInterval = 0; 2038 2039 /* 4.3, 4.8.2.1 */ 2040 switch (speed) { 2041 case USB_SPEED_SUPER: 2042 case USB_SPEED_SUPER_PLUS: 2043 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2044 break; 2045 case USB_SPEED_FULL: 2046 /* XXX using 64 as initial mps of ep0 in FS */ 2047 case USB_SPEED_HIGH: 2048 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2049 break; 2050 case USB_SPEED_LOW: 2051 default: 2052 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2053 break; 2054 } 2055 2056 up->up_dev = dev; 2057 2058 /* Establish the default pipe. */ 2059 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2060 &dev->ud_pipe0); 2061 if (err) { 2062 goto bad; 2063 } 2064 2065 dd = &dev->ud_ddesc; 2066 2067 if ((depth == 0) && (port == 0)) { 2068 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2069 bus->ub_devices[dev->ud_addr] = dev; 2070 err = usbd_get_initial_ddesc(dev, dd); 2071 if (err) 2072 goto bad; 2073 err = usbd_reload_device_desc(dev); 2074 if (err) 2075 goto bad; 2076 } else { 2077 uint8_t slot = 0; 2078 2079 /* 4.3.2 */ 2080 err = xhci_enable_slot(sc, &slot); 2081 if (err) 2082 goto bad; 2083 2084 xs = &sc->sc_slots[slot]; 2085 dev->ud_hcpriv = xs; 2086 2087 /* 4.3.3 initialize slot structure */ 2088 err = xhci_init_slot(dev, slot); 2089 if (err) { 2090 dev->ud_hcpriv = NULL; 2091 /* 2092 * We have to disable_slot here because 2093 * xs->xs_idx == 0 when xhci_init_slot fails, 2094 * in that case usbd_remove_dev won't work. 2095 */ 2096 mutex_enter(&sc->sc_lock); 2097 xhci_disable_slot(sc, slot); 2098 mutex_exit(&sc->sc_lock); 2099 goto bad; 2100 } 2101 2102 /* 4.3.4 Address Assignment */ 2103 err = xhci_set_address(dev, slot, false); 2104 if (err) 2105 goto bad; 2106 2107 /* Allow device time to set new address */ 2108 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2109 2110 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2111 //hexdump("slot context", cp, sc->sc_ctxsz); 2112 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2113 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2114 /* XXX ensure we know when the hardware does something 2115 we can't yet cope with */ 2116 KASSERT(addr >= 1 && addr <= 127); 2117 dev->ud_addr = addr; 2118 /* XXX dev->ud_addr not necessarily unique on bus */ 2119 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2120 bus->ub_devices[dev->ud_addr] = dev; 2121 2122 err = usbd_get_initial_ddesc(dev, dd); 2123 if (err) 2124 goto bad; 2125 2126 /* 4.8.2.1 */ 2127 if (USB_IS_SS(speed)) { 2128 if (dd->bMaxPacketSize != 9) { 2129 printf("%s: invalid mps 2^%u for SS ep0," 2130 " using 512\n", 2131 device_xname(sc->sc_dev), 2132 dd->bMaxPacketSize); 2133 dd->bMaxPacketSize = 9; 2134 } 2135 USETW(dev->ud_ep0desc.wMaxPacketSize, 2136 (1 << dd->bMaxPacketSize)); 2137 } else 2138 USETW(dev->ud_ep0desc.wMaxPacketSize, 2139 dd->bMaxPacketSize); 2140 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2141 xhci_update_ep0_mps(sc, xs, 2142 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2143 2144 err = usbd_reload_device_desc(dev); 2145 if (err) 2146 goto bad; 2147 } 2148 2149 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2150 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2151 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2152 dd->bDeviceClass, dd->bDeviceSubClass, 2153 dd->bDeviceProtocol, 0); 2154 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2155 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2156 dev->ud_speed); 2157 2158 usbd_get_device_strings(dev); 2159 2160 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2161 2162 if ((depth == 0) && (port == 0)) { 2163 usbd_attach_roothub(parent, dev); 2164 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2165 return USBD_NORMAL_COMPLETION; 2166 } 2167 2168 2169 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2170 bad: 2171 if (err != USBD_NORMAL_COMPLETION) { 2172 usbd_remove_device(dev, up); 2173 } 2174 2175 return err; 2176 } 2177 2178 static usbd_status 2179 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2180 size_t ntrb, size_t align) 2181 { 2182 usbd_status err; 2183 size_t size = ntrb * XHCI_TRB_SIZE; 2184 2185 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2186 2187 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2188 if (err) 2189 return err; 2190 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2191 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2192 xr->xr_trb = xhci_ring_trbv(xr, 0); 2193 xr->xr_ntrb = ntrb; 2194 xr->is_halted = false; 2195 xhci_host_dequeue(xr); 2196 2197 return USBD_NORMAL_COMPLETION; 2198 } 2199 2200 static void 2201 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2202 { 2203 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2204 mutex_destroy(&xr->xr_lock); 2205 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2206 } 2207 2208 static void 2209 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2210 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2211 { 2212 size_t i; 2213 u_int ri; 2214 u_int cs; 2215 uint64_t parameter; 2216 uint32_t status; 2217 uint32_t control; 2218 2219 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2220 2221 KASSERT(ntrbs <= XHCI_XFER_NTRB); 2222 for (i = 0; i < ntrbs; i++) { 2223 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2224 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2225 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2226 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2227 XHCI_TRB_TYPE_LINK); 2228 } 2229 2230 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2231 2232 ri = xr->xr_ep; 2233 cs = xr->xr_cs; 2234 2235 /* 2236 * Although the xhci hardware can do scatter/gather dma from 2237 * arbitrary sized buffers, there is a non-obvious restriction 2238 * that a LINK trb is only allowed at the end of a burst of 2239 * transfers - which might be 16kB. 2240 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2241 * The simple solution is not to allow a LINK trb in the middle 2242 * of anything - as here. 2243 * XXX: (dsl) There are xhci controllers out there (eg some made by 2244 * ASMedia) that seem to lock up if they process a LINK trb but 2245 * cannot process the linked-to trb yet. 2246 * The code should write the 'cycle' bit on the link trb AFTER 2247 * adding the other trb. 2248 */ 2249 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2250 parameter = xhci_ring_trbp(xr, 0); 2251 status = 0; 2252 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2253 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2254 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2255 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2256 BUS_DMASYNC_PREWRITE); 2257 xr->xr_cookies[ri] = NULL; 2258 xr->xr_ep = 0; 2259 xr->xr_cs ^= 1; 2260 ri = xr->xr_ep; 2261 cs = xr->xr_cs; 2262 } 2263 2264 ri++; 2265 2266 /* Write any subsequent TRB first */ 2267 for (i = 1; i < ntrbs; i++) { 2268 parameter = trbs[i].trb_0; 2269 status = trbs[i].trb_2; 2270 control = trbs[i].trb_3; 2271 2272 if (cs) { 2273 control |= XHCI_TRB_3_CYCLE_BIT; 2274 } else { 2275 control &= ~XHCI_TRB_3_CYCLE_BIT; 2276 } 2277 2278 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2279 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2280 BUS_DMASYNC_PREWRITE); 2281 xr->xr_cookies[ri] = cookie; 2282 ri++; 2283 } 2284 2285 /* Write the first TRB last */ 2286 i = 0; 2287 parameter = trbs[i].trb_0; 2288 status = trbs[i].trb_2; 2289 control = trbs[i].trb_3; 2290 2291 if (xr->xr_cs) { 2292 control |= XHCI_TRB_3_CYCLE_BIT; 2293 } else { 2294 control &= ~XHCI_TRB_3_CYCLE_BIT; 2295 } 2296 2297 xhci_trb_put(&xr->xr_trb[xr->xr_ep], parameter, status, control); 2298 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * xr->xr_ep, XHCI_TRB_SIZE * 1, 2299 BUS_DMASYNC_PREWRITE); 2300 xr->xr_cookies[xr->xr_ep] = cookie; 2301 2302 xr->xr_ep = ri; 2303 xr->xr_cs = cs; 2304 2305 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2306 } 2307 2308 /* 2309 * Stop execution commands, purge all commands on command ring, and 2310 * rewind dequeue pointer. 2311 */ 2312 static void 2313 xhci_abort_command(struct xhci_softc *sc) 2314 { 2315 struct xhci_ring * const cr = &sc->sc_cr; 2316 uint64_t crcr; 2317 int i; 2318 2319 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2320 DPRINTFN(14, "command %#"PRIx64" timeout, aborting", 2321 sc->sc_command_addr, 0, 0, 0); 2322 2323 mutex_enter(&cr->xr_lock); 2324 2325 /* 4.6.1.2 Aborting a Command */ 2326 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2327 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2328 2329 for (i = 0; i < 500; i++) { 2330 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2331 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2332 break; 2333 usb_delay_ms(&sc->sc_bus, 1); 2334 } 2335 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2336 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2337 /* reset HC here? */ 2338 } 2339 2340 /* reset command ring dequeue pointer */ 2341 cr->xr_ep = 0; 2342 cr->xr_cs = 1; 2343 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2344 2345 mutex_exit(&cr->xr_lock); 2346 } 2347 2348 /* 2349 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2350 * Command completion is notified by cv_signal from xhci_event_cmd() 2351 * (called from xhci_softint), or timed-out. 2352 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2353 * then do_command examines it. 2354 */ 2355 static usbd_status 2356 xhci_do_command_locked(struct xhci_softc * const sc, 2357 struct xhci_trb * const trb, int timeout) 2358 { 2359 struct xhci_ring * const cr = &sc->sc_cr; 2360 usbd_status err; 2361 2362 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2363 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2364 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2365 2366 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2367 KASSERT(mutex_owned(&sc->sc_lock)); 2368 2369 while (sc->sc_command_addr != 0) 2370 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 2371 2372 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2373 sc->sc_resultpending = true; 2374 2375 mutex_enter(&cr->xr_lock); 2376 xhci_ring_put(sc, cr, NULL, trb, 1); 2377 mutex_exit(&cr->xr_lock); 2378 2379 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2380 2381 while (sc->sc_resultpending) { 2382 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2383 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2384 xhci_abort_command(sc); 2385 err = USBD_TIMEOUT; 2386 goto timedout; 2387 } 2388 } 2389 2390 trb->trb_0 = sc->sc_result_trb.trb_0; 2391 trb->trb_2 = sc->sc_result_trb.trb_2; 2392 trb->trb_3 = sc->sc_result_trb.trb_3; 2393 2394 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2395 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2396 2397 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2398 case XHCI_TRB_ERROR_SUCCESS: 2399 err = USBD_NORMAL_COMPLETION; 2400 break; 2401 default: 2402 case 192 ... 223: 2403 err = USBD_IOERROR; 2404 break; 2405 case 224 ... 255: 2406 err = USBD_NORMAL_COMPLETION; 2407 break; 2408 } 2409 2410 timedout: 2411 sc->sc_resultpending = false; 2412 sc->sc_command_addr = 0; 2413 cv_broadcast(&sc->sc_cmdbusy_cv); 2414 2415 return err; 2416 } 2417 2418 static usbd_status 2419 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2420 int timeout) 2421 { 2422 2423 mutex_enter(&sc->sc_lock); 2424 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2425 mutex_exit(&sc->sc_lock); 2426 2427 return ret; 2428 } 2429 2430 static usbd_status 2431 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2432 { 2433 struct xhci_trb trb; 2434 usbd_status err; 2435 2436 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2437 2438 trb.trb_0 = 0; 2439 trb.trb_2 = 0; 2440 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2441 2442 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2443 if (err != USBD_NORMAL_COMPLETION) { 2444 return err; 2445 } 2446 2447 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2448 2449 return err; 2450 } 2451 2452 /* 2453 * xHCI 4.6.4 2454 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2455 * All endpoints in the slot should be stopped. 2456 * Should be called with sc_lock held. 2457 */ 2458 static usbd_status 2459 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2460 { 2461 struct xhci_trb trb; 2462 struct xhci_slot *xs; 2463 usbd_status err; 2464 2465 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2466 2467 if (sc->sc_dying) 2468 return USBD_IOERROR; 2469 2470 trb.trb_0 = 0; 2471 trb.trb_2 = 0; 2472 trb.trb_3 = htole32( 2473 XHCI_TRB_3_SLOT_SET(slot) | 2474 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2475 2476 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2477 2478 if (!err) { 2479 xs = &sc->sc_slots[slot]; 2480 if (xs->xs_idx != 0) { 2481 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2482 xhci_set_dcba(sc, 0, slot); 2483 memset(xs, 0, sizeof(*xs)); 2484 } 2485 } 2486 2487 return err; 2488 } 2489 2490 /* 2491 * Set address of device and transition slot state from ENABLED to ADDRESSED 2492 * if Block Setaddress Request (BSR) is false. 2493 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2494 * see xHCI 1.1 4.5.3, 3.3.4 2495 * Should be called without sc_lock held. 2496 */ 2497 static usbd_status 2498 xhci_address_device(struct xhci_softc * const sc, 2499 uint64_t icp, uint8_t slot_id, bool bsr) 2500 { 2501 struct xhci_trb trb; 2502 usbd_status err; 2503 2504 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2505 2506 trb.trb_0 = icp; 2507 trb.trb_2 = 0; 2508 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2509 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2510 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2511 2512 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2513 2514 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2515 err = USBD_NO_ADDR; 2516 2517 return err; 2518 } 2519 2520 static usbd_status 2521 xhci_update_ep0_mps(struct xhci_softc * const sc, 2522 struct xhci_slot * const xs, u_int mps) 2523 { 2524 struct xhci_trb trb; 2525 usbd_status err; 2526 uint32_t * cp; 2527 2528 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2529 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2530 2531 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2532 cp[0] = htole32(0); 2533 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2534 2535 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2536 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2537 2538 /* sync input contexts before they are read from memory */ 2539 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2540 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2541 sc->sc_ctxsz * 4); 2542 2543 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2544 trb.trb_2 = 0; 2545 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2546 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2547 2548 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2549 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2550 return err; 2551 } 2552 2553 static void 2554 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2555 { 2556 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2557 2558 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2559 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2560 &dcbaa[si], dcba, si, 0); 2561 2562 dcbaa[si] = htole64(dcba); 2563 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2564 BUS_DMASYNC_PREWRITE); 2565 } 2566 2567 /* 2568 * Allocate device and input context DMA buffer, and 2569 * TRB DMA buffer for each endpoint. 2570 */ 2571 static usbd_status 2572 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2573 { 2574 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2575 struct xhci_slot *xs; 2576 usbd_status err; 2577 u_int dci; 2578 2579 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2580 DPRINTFN(4, "slot %u", slot, 0, 0, 0); 2581 2582 xs = &sc->sc_slots[slot]; 2583 2584 /* allocate contexts */ 2585 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2586 &xs->xs_dc_dma); 2587 if (err) 2588 return err; 2589 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2590 2591 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2592 &xs->xs_ic_dma); 2593 if (err) 2594 goto bad1; 2595 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2596 2597 for (dci = 0; dci < 32; dci++) { 2598 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2599 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2600 if (dci == XHCI_DCI_SLOT) 2601 continue; 2602 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2603 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2604 if (err) { 2605 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2606 goto bad2; 2607 } 2608 } 2609 2610 bad2: 2611 if (err == USBD_NORMAL_COMPLETION) { 2612 xs->xs_idx = slot; 2613 } else { 2614 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2615 } 2616 2617 return err; 2618 2619 bad1: 2620 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2621 xs->xs_idx = 0; 2622 return err; 2623 } 2624 2625 static void 2626 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2627 int end_dci) 2628 { 2629 u_int dci; 2630 2631 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2632 DPRINTFN(4, "slot %u start %u end %u", xs->xs_idx, start_dci, end_dci, 2633 0); 2634 2635 for (dci = start_dci; dci < end_dci; dci++) { 2636 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2637 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2638 } 2639 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2640 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2641 xs->xs_idx = 0; 2642 } 2643 2644 /* 2645 * Setup slot context, set Device Context Base Address, and issue 2646 * Set Address Device command. 2647 */ 2648 static usbd_status 2649 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 2650 { 2651 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2652 struct xhci_slot *xs; 2653 usbd_status err; 2654 2655 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2656 DPRINTFN(4, "slot %u bsr %u", slot, bsr, 0, 0); 2657 2658 xs = &sc->sc_slots[slot]; 2659 2660 xhci_setup_ctx(dev->ud_pipe0); 2661 2662 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2663 sc->sc_ctxsz * 3); 2664 2665 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2666 2667 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 2668 2669 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2670 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2671 sc->sc_ctxsz * 2); 2672 2673 return err; 2674 } 2675 2676 /* 2677 * 4.8.2, 6.2.3.2 2678 * construct slot/endpoint context parameters and do syncmem 2679 */ 2680 static void 2681 xhci_setup_ctx(struct usbd_pipe *pipe) 2682 { 2683 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2684 struct usbd_device *dev = pipe->up_dev; 2685 struct xhci_slot * const xs = dev->ud_hcpriv; 2686 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2687 const u_int dci = xhci_ep_get_dci(ed); 2688 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2689 uint32_t *cp; 2690 uint16_t mps = UGETW(ed->wMaxPacketSize); 2691 uint8_t speed = dev->ud_speed; 2692 uint8_t ival = ed->bInterval; 2693 2694 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2695 DPRINTFN(4, "pipe %p: slot %u dci %u speed %u", pipe, xs->xs_idx, dci, 2696 speed); 2697 2698 /* set up initial input control context */ 2699 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2700 cp[0] = htole32(0); 2701 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 2702 if (dci == XHCI_DCI_EP_CONTROL) 2703 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2704 cp[7] = htole32(0); 2705 2706 /* set up input slot context */ 2707 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2708 cp[0] = 2709 XHCI_SCTX_0_CTX_NUM_SET(dci) | 2710 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 2711 cp[1] = 0; 2712 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2713 cp[3] = 0; 2714 xhci_setup_route(pipe, cp); 2715 xhci_setup_tthub(pipe, cp); 2716 2717 cp[0] = htole32(cp[0]); 2718 cp[1] = htole32(cp[1]); 2719 cp[2] = htole32(cp[2]); 2720 cp[3] = htole32(cp[3]); 2721 2722 /* set up input endpoint context */ 2723 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 2724 cp[0] = 2725 XHCI_EPCTX_0_EPSTATE_SET(0) | 2726 XHCI_EPCTX_0_MULT_SET(0) | 2727 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2728 XHCI_EPCTX_0_LSA_SET(0) | 2729 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 2730 cp[1] = 2731 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 2732 XHCI_EPCTX_1_HID_SET(0) | 2733 XHCI_EPCTX_1_MAXB_SET(0); 2734 2735 if (xfertype != UE_ISOCHRONOUS) 2736 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 2737 2738 if (xfertype == UE_CONTROL) 2739 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 2740 else if (USB_IS_SS(speed)) 2741 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 2742 else 2743 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 2744 2745 xhci_setup_maxburst(pipe, cp); 2746 2747 switch (xfertype) { 2748 case UE_CONTROL: 2749 break; 2750 case UE_BULK: 2751 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 2752 break; 2753 case UE_INTERRUPT: 2754 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 2755 ival = pipe->up_interval; 2756 2757 ival = xhci_bival2ival(ival, speed); 2758 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 2759 break; 2760 case UE_ISOCHRONOUS: 2761 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 2762 ival = pipe->up_interval; 2763 2764 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 2765 if (speed == USB_SPEED_FULL) 2766 ival += 3; /* 1ms -> 125us */ 2767 ival--; 2768 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 2769 break; 2770 default: 2771 break; 2772 } 2773 DPRINTFN(4, "setting ival %u MaxBurst %#x", 2774 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 2775 2776 /* rewind TR dequeue pointer in xHC */ 2777 /* can't use xhci_ep_get_dci() yet? */ 2778 *(uint64_t *)(&cp[2]) = htole64( 2779 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 2780 XHCI_EPCTX_2_DCS_SET(1)); 2781 2782 cp[0] = htole32(cp[0]); 2783 cp[1] = htole32(cp[1]); 2784 cp[4] = htole32(cp[4]); 2785 2786 /* rewind TR dequeue pointer in driver */ 2787 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 2788 mutex_enter(&xr->xr_lock); 2789 xhci_host_dequeue(xr); 2790 mutex_exit(&xr->xr_lock); 2791 2792 /* sync input contexts before they are read from memory */ 2793 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2794 } 2795 2796 /* 2797 * Setup route string and roothub port of given device for slot context 2798 */ 2799 static void 2800 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 2801 { 2802 struct usbd_device *dev = pipe->up_dev; 2803 struct usbd_port *up = dev->ud_powersrc; 2804 struct usbd_device *hub; 2805 struct usbd_device *adev; 2806 uint8_t rhport = 0; 2807 uint32_t route = 0; 2808 2809 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2810 2811 /* Locate root hub port and Determine route string */ 2812 /* 4.3.3 route string does not include roothub port */ 2813 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2814 uint32_t dep; 2815 2816 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2817 hub, hub->ud_depth, hub->ud_powersrc, 2818 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2819 2820 if (hub->ud_powersrc == NULL) 2821 break; 2822 dep = hub->ud_depth; 2823 if (dep == 0) 2824 break; 2825 rhport = hub->ud_powersrc->up_portno; 2826 if (dep > USB_HUB_MAX_DEPTH) 2827 continue; 2828 2829 route |= 2830 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2831 << ((dep - 1) * 4); 2832 } 2833 route = route >> 4; 2834 DPRINTFN(4, "rhport %u Route %05x hub %p", rhport, route, hub, 0); 2835 2836 /* Locate port on upstream high speed hub */ 2837 for (adev = dev, hub = up->up_parent; 2838 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2839 adev = hub, hub = hub->ud_myhub) 2840 ; 2841 if (hub) { 2842 int p; 2843 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2844 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2845 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2846 goto found; 2847 } 2848 } 2849 panic("xhci_setup_route: cannot find HS port"); 2850 found: 2851 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2852 } else { 2853 dev->ud_myhsport = NULL; 2854 } 2855 2856 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 2857 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(rhport); 2858 } 2859 2860 /* 2861 * Setup whether device is hub, whether device uses MTT, and 2862 * TT informations if it uses MTT. 2863 */ 2864 static void 2865 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 2866 { 2867 struct usbd_device *dev = pipe->up_dev; 2868 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 2869 uint32_t speed = dev->ud_speed; 2870 uint8_t tthubslot, ttportnum; 2871 bool ishub; 2872 bool usemtt; 2873 2874 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2875 2876 /* 2877 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 2878 * tthubslot: 2879 * This is the slot ID of parent HS hub 2880 * if LS/FS device is connected && connected through HS hub. 2881 * This is 0 if device is not LS/FS device || 2882 * parent hub is not HS hub || 2883 * attached to root hub. 2884 * ttportnum: 2885 * This is the downstream facing port of parent HS hub 2886 * if LS/FS device is connected. 2887 * This is 0 if device is not LS/FS device || 2888 * parent hub is not HS hub || 2889 * attached to root hub. 2890 */ 2891 if (dev->ud_myhsport != NULL && 2892 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 2893 (dev->ud_myhub != NULL && 2894 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 2895 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 2896 ttportnum = dev->ud_myhsport->up_portno; 2897 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 2898 } else { 2899 ttportnum = 0; 2900 tthubslot = 0; 2901 } 2902 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 2903 dev->ud_myhsport, ttportnum, tthubslot, 0); 2904 2905 /* ishub is valid after reading UDESC_DEVICE */ 2906 ishub = (dd->bDeviceClass == UDCLASS_HUB); 2907 2908 /* dev->ud_hub is valid after reading UDESC_HUB */ 2909 if (ishub && dev->ud_hub) { 2910 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 2911 uint8_t ttt = 2912 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 2913 2914 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 2915 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 2916 DPRINTFN(4, "nports=%d ttt=%d", hd->bNbrPorts, ttt, 0, 0); 2917 } 2918 2919 #define IS_TTHUB(dd) \ 2920 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 2921 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 2922 2923 /* 2924 * MTT flag is set if 2925 * 1. this is HS hub && MTT is enabled 2926 * or 2927 * 2. this is not hub && this is LS or FS device && 2928 * MTT of parent HS hub (and its parent, too) is enabled 2929 */ 2930 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 2931 usemtt = true; 2932 else if (!ishub && 2933 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 2934 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 2935 (dev->ud_myhub != NULL && 2936 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 2937 dev->ud_myhsport != NULL && 2938 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 2939 usemtt = true; 2940 else 2941 usemtt = false; 2942 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 2943 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 2944 2945 #undef IS_TTHUB 2946 2947 cp[0] |= 2948 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 2949 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 2950 cp[2] |= 2951 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 2952 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 2953 } 2954 2955 /* set up params for periodic endpoint */ 2956 static void 2957 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 2958 { 2959 struct usbd_device *dev = pipe->up_dev; 2960 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2961 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2962 usbd_desc_iter_t iter; 2963 const usb_cdc_descriptor_t *cdcd; 2964 uint32_t maxb = 0; 2965 uint16_t mps = UGETW(ed->wMaxPacketSize); 2966 uint8_t speed = dev->ud_speed; 2967 uint8_t ep; 2968 2969 /* config desc is NULL when opening ep0 */ 2970 if (dev == NULL || dev->ud_cdesc == NULL) 2971 goto no_cdcd; 2972 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 2973 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 2974 if (cdcd == NULL) 2975 goto no_cdcd; 2976 usb_desc_iter_init(dev, &iter); 2977 iter.cur = (const void *)cdcd; 2978 2979 /* find endpoint_ss_comp desc for ep of this pipe */ 2980 for (ep = 0;;) { 2981 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 2982 if (cdcd == NULL) 2983 break; 2984 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 2985 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 2986 bEndpointAddress; 2987 if (UE_GET_ADDR(ep) == 2988 UE_GET_ADDR(ed->bEndpointAddress)) { 2989 cdcd = (const usb_cdc_descriptor_t *) 2990 usb_desc_iter_next(&iter); 2991 break; 2992 } 2993 ep = 0; 2994 } 2995 } 2996 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 2997 const usb_endpoint_ss_comp_descriptor_t * esscd = 2998 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 2999 maxb = esscd->bMaxBurst; 3000 } 3001 3002 no_cdcd: 3003 /* 6.2.3.4, 4.8.2.4 */ 3004 if (USB_IS_SS(speed)) { 3005 /* UBS 3.1 9.6.6 */ 3006 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3007 /* UBS 3.1 9.6.7 */ 3008 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3009 #ifdef notyet 3010 if (xfertype == UE_ISOCHRONOUS) { 3011 } 3012 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3013 /* use ESIT */ 3014 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3015 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3016 3017 /* XXX if LEC = 1, set ESIT instead */ 3018 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3019 } else { 3020 /* use ival */ 3021 } 3022 #endif 3023 } else { 3024 /* UBS 2.0 9.6.6 */ 3025 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3026 3027 /* 6.2.3.4 */ 3028 if (speed == USB_SPEED_HIGH && 3029 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3030 maxb = UE_GET_TRANS(mps); 3031 } else { 3032 /* LS/FS or HS CTRL or HS BULK */ 3033 maxb = 0; 3034 } 3035 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3036 } 3037 } 3038 3039 /* 3040 * Convert endpoint bInterval value to endpoint context interval value 3041 * for Interrupt pipe. 3042 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3043 */ 3044 static uint32_t 3045 xhci_bival2ival(uint32_t ival, uint32_t speed) 3046 { 3047 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3048 int i; 3049 3050 /* 3051 * round ival down to "the nearest base 2 multiple of 3052 * bInterval * 8". 3053 * bInterval is at most 255 as its type is uByte. 3054 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3055 */ 3056 for (i = 10; i > 0; i--) { 3057 if ((ival * 8) >= (1 << i)) 3058 break; 3059 } 3060 ival = i; 3061 } else { 3062 /* Interval = bInterval-1 for SS/HS */ 3063 ival--; 3064 } 3065 3066 return ival; 3067 } 3068 3069 /* ----- */ 3070 3071 static void 3072 xhci_noop(struct usbd_pipe *pipe) 3073 { 3074 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3075 } 3076 3077 /* 3078 * Process root hub request. 3079 */ 3080 static int 3081 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3082 void *buf, int buflen) 3083 { 3084 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3085 usb_port_status_t ps; 3086 int l, totlen = 0; 3087 uint16_t len, value, index; 3088 int port, i; 3089 uint32_t v; 3090 3091 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3092 3093 if (sc->sc_dying) 3094 return -1; 3095 3096 len = UGETW(req->wLength); 3097 value = UGETW(req->wValue); 3098 index = UGETW(req->wIndex); 3099 3100 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 3101 req->bmRequestType | (req->bRequest << 8), value, index, len); 3102 3103 #define C(x,y) ((x) | ((y) << 8)) 3104 switch (C(req->bRequest, req->bmRequestType)) { 3105 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3106 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 3107 if (len == 0) 3108 break; 3109 switch (value) { 3110 case C(0, UDESC_DEVICE): { 3111 usb_device_descriptor_t devd; 3112 totlen = min(buflen, sizeof(devd)); 3113 memcpy(&devd, buf, totlen); 3114 USETW(devd.idVendor, sc->sc_id_vendor); 3115 memcpy(buf, &devd, totlen); 3116 break; 3117 } 3118 #define sd ((usb_string_descriptor_t *)buf) 3119 case C(1, UDESC_STRING): 3120 /* Vendor */ 3121 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3122 break; 3123 case C(2, UDESC_STRING): 3124 /* Product */ 3125 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3126 break; 3127 #undef sd 3128 default: 3129 /* default from usbroothub */ 3130 return buflen; 3131 } 3132 break; 3133 3134 /* Hub requests */ 3135 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3136 break; 3137 /* Clear Port Feature request */ 3138 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3139 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 3140 index, value, 0, 0); 3141 if (index < 1 || index > sc->sc_maxports) { 3142 return -1; 3143 } 3144 port = XHCI_PORTSC(index); 3145 v = xhci_op_read_4(sc, port); 3146 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3147 v &= ~XHCI_PS_CLEAR; 3148 switch (value) { 3149 case UHF_PORT_ENABLE: 3150 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3151 break; 3152 case UHF_PORT_SUSPEND: 3153 return -1; 3154 case UHF_PORT_POWER: 3155 break; 3156 case UHF_PORT_TEST: 3157 case UHF_PORT_INDICATOR: 3158 return -1; 3159 case UHF_C_PORT_CONNECTION: 3160 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3161 break; 3162 case UHF_C_PORT_ENABLE: 3163 case UHF_C_PORT_SUSPEND: 3164 case UHF_C_PORT_OVER_CURRENT: 3165 return -1; 3166 case UHF_C_BH_PORT_RESET: 3167 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3168 break; 3169 case UHF_C_PORT_RESET: 3170 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3171 break; 3172 case UHF_C_PORT_LINK_STATE: 3173 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3174 break; 3175 case UHF_C_PORT_CONFIG_ERROR: 3176 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3177 break; 3178 default: 3179 return -1; 3180 } 3181 break; 3182 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3183 if (len == 0) 3184 break; 3185 if ((value & 0xff) != 0) { 3186 return -1; 3187 } 3188 usb_hub_descriptor_t hubd; 3189 3190 totlen = min(buflen, sizeof(hubd)); 3191 memcpy(&hubd, buf, totlen); 3192 hubd.bNbrPorts = sc->sc_maxports; 3193 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3194 hubd.bPwrOn2PwrGood = 200; 3195 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 3196 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 3197 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3198 totlen = min(totlen, hubd.bDescLength); 3199 memcpy(buf, &hubd, totlen); 3200 break; 3201 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3202 if (len != 4) { 3203 return -1; 3204 } 3205 memset(buf, 0, len); /* ? XXX */ 3206 totlen = len; 3207 break; 3208 /* Get Port Status request */ 3209 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3210 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 3211 if (index < 1 || index > sc->sc_maxports) { 3212 return -1; 3213 } 3214 if (len != 4) { 3215 return -1; 3216 } 3217 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 3218 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 3219 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3220 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3221 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3222 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3223 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3224 if (v & XHCI_PS_PR) i |= UPS_RESET; 3225 if (v & XHCI_PS_PP) { 3226 if (i & UPS_OTHER_SPEED) 3227 i |= UPS_PORT_POWER_SS; 3228 else 3229 i |= UPS_PORT_POWER; 3230 } 3231 if (i & UPS_OTHER_SPEED) 3232 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3233 if (sc->sc_vendor_port_status) 3234 i = sc->sc_vendor_port_status(sc, v, i); 3235 USETW(ps.wPortStatus, i); 3236 i = 0; 3237 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3238 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3239 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3240 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3241 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3242 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3243 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3244 USETW(ps.wPortChange, i); 3245 totlen = min(len, sizeof(ps)); 3246 memcpy(buf, &ps, totlen); 3247 break; 3248 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3249 return -1; 3250 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3251 break; 3252 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3253 break; 3254 /* Set Port Feature request */ 3255 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3256 int optval = (index >> 8) & 0xff; 3257 index &= 0xff; 3258 if (index < 1 || index > sc->sc_maxports) { 3259 return -1; 3260 } 3261 port = XHCI_PORTSC(index); 3262 v = xhci_op_read_4(sc, port); 3263 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3264 v &= ~XHCI_PS_CLEAR; 3265 switch (value) { 3266 case UHF_PORT_ENABLE: 3267 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3268 break; 3269 case UHF_PORT_SUSPEND: 3270 /* XXX suspend */ 3271 break; 3272 case UHF_PORT_RESET: 3273 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3274 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3275 /* Wait for reset to complete. */ 3276 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3277 if (sc->sc_dying) { 3278 return -1; 3279 } 3280 v = xhci_op_read_4(sc, port); 3281 if (v & XHCI_PS_PR) { 3282 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3283 usb_delay_ms(&sc->sc_bus, 10); 3284 /* XXX */ 3285 } 3286 break; 3287 case UHF_PORT_POWER: 3288 /* XXX power control */ 3289 break; 3290 /* XXX more */ 3291 case UHF_C_PORT_RESET: 3292 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3293 break; 3294 case UHF_PORT_U1_TIMEOUT: 3295 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3296 return -1; 3297 } 3298 port = XHCI_PORTPMSC(index); 3299 v = xhci_op_read_4(sc, port); 3300 v &= ~XHCI_PM3_U1TO_SET(0xff); 3301 v |= XHCI_PM3_U1TO_SET(optval); 3302 xhci_op_write_4(sc, port, v); 3303 break; 3304 case UHF_PORT_U2_TIMEOUT: 3305 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3306 return -1; 3307 } 3308 port = XHCI_PORTPMSC(index); 3309 v = xhci_op_read_4(sc, port); 3310 v &= ~XHCI_PM3_U2TO_SET(0xff); 3311 v |= XHCI_PM3_U2TO_SET(optval); 3312 xhci_op_write_4(sc, port, v); 3313 break; 3314 default: 3315 return -1; 3316 } 3317 } 3318 break; 3319 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3320 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3321 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3322 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3323 break; 3324 default: 3325 /* default from usbroothub */ 3326 return buflen; 3327 } 3328 3329 return totlen; 3330 } 3331 3332 /* root hub interrupt */ 3333 3334 static usbd_status 3335 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3336 { 3337 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3338 usbd_status err; 3339 3340 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3341 3342 /* Insert last in queue. */ 3343 mutex_enter(&sc->sc_lock); 3344 err = usb_insert_transfer(xfer); 3345 mutex_exit(&sc->sc_lock); 3346 if (err) 3347 return err; 3348 3349 /* Pipe isn't running, start first */ 3350 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3351 } 3352 3353 /* Wait for roothub port status/change */ 3354 static usbd_status 3355 xhci_root_intr_start(struct usbd_xfer *xfer) 3356 { 3357 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3358 3359 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3360 3361 if (sc->sc_dying) 3362 return USBD_IOERROR; 3363 3364 mutex_enter(&sc->sc_lock); 3365 sc->sc_intrxfer = xfer; 3366 mutex_exit(&sc->sc_lock); 3367 3368 return USBD_IN_PROGRESS; 3369 } 3370 3371 static void 3372 xhci_root_intr_abort(struct usbd_xfer *xfer) 3373 { 3374 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3375 3376 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3377 3378 KASSERT(mutex_owned(&sc->sc_lock)); 3379 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3380 3381 sc->sc_intrxfer = NULL; 3382 3383 xfer->ux_status = USBD_CANCELLED; 3384 usb_transfer_complete(xfer); 3385 } 3386 3387 static void 3388 xhci_root_intr_close(struct usbd_pipe *pipe) 3389 { 3390 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3391 3392 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3393 3394 KASSERT(mutex_owned(&sc->sc_lock)); 3395 3396 sc->sc_intrxfer = NULL; 3397 } 3398 3399 static void 3400 xhci_root_intr_done(struct usbd_xfer *xfer) 3401 { 3402 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3403 3404 } 3405 3406 /* -------------- */ 3407 /* device control */ 3408 3409 static usbd_status 3410 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3411 { 3412 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3413 usbd_status err; 3414 3415 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3416 3417 /* Insert last in queue. */ 3418 mutex_enter(&sc->sc_lock); 3419 err = usb_insert_transfer(xfer); 3420 mutex_exit(&sc->sc_lock); 3421 if (err) 3422 return err; 3423 3424 /* Pipe isn't running, start first */ 3425 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3426 } 3427 3428 static usbd_status 3429 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3430 { 3431 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3432 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3433 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3434 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3435 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3436 usb_device_request_t * const req = &xfer->ux_request; 3437 const int isread = usbd_xfer_isread(xfer); 3438 const uint32_t len = UGETW(req->wLength); 3439 usb_dma_t * const dma = &xfer->ux_dmabuf; 3440 uint64_t parameter; 3441 uint32_t status; 3442 uint32_t control; 3443 u_int i; 3444 3445 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3446 DPRINTFN(12, "req: %04x %04x %04x %04x", 3447 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3448 UGETW(req->wIndex), UGETW(req->wLength)); 3449 3450 /* we rely on the bottom bits for extra info */ 3451 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 3452 3453 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3454 3455 i = 0; 3456 3457 /* setup phase */ 3458 memcpy(¶meter, req, sizeof(*req)); 3459 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3460 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3461 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3462 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3463 XHCI_TRB_3_IDT_BIT; 3464 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3465 3466 if (len != 0) { 3467 /* data phase */ 3468 parameter = DMAADDR(dma, 0); 3469 KASSERT(len <= 0x10000); 3470 status = XHCI_TRB_2_IRQ_SET(0) | 3471 XHCI_TRB_2_TDSZ_SET(1) | 3472 XHCI_TRB_2_BYTES_SET(len); 3473 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3474 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3475 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3476 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3477 3478 parameter = (uintptr_t)xfer | 0x3; 3479 status = XHCI_TRB_2_IRQ_SET(0); 3480 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3481 XHCI_TRB_3_IOC_BIT; 3482 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3483 } 3484 3485 parameter = 0; 3486 status = XHCI_TRB_2_IRQ_SET(0); 3487 /* the status stage has inverted direction */ 3488 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3489 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3490 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3491 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3492 3493 parameter = (uintptr_t)xfer | 0x0; 3494 status = XHCI_TRB_2_IRQ_SET(0); 3495 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3496 XHCI_TRB_3_IOC_BIT; 3497 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3498 3499 mutex_enter(&tr->xr_lock); 3500 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3501 mutex_exit(&tr->xr_lock); 3502 3503 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3504 3505 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3506 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3507 xhci_timeout, xfer); 3508 } 3509 3510 return USBD_IN_PROGRESS; 3511 } 3512 3513 static void 3514 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3515 { 3516 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3517 usb_device_request_t *req = &xfer->ux_request; 3518 int len = UGETW(req->wLength); 3519 int rd = req->bmRequestType & UT_READ; 3520 3521 if (len) 3522 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3523 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3524 } 3525 3526 static void 3527 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3528 { 3529 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3530 3531 xhci_abort_xfer(xfer, USBD_CANCELLED); 3532 } 3533 3534 static void 3535 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3536 { 3537 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3538 3539 xhci_close_pipe(pipe); 3540 } 3541 3542 /* ------------------ */ 3543 /* device isochronous */ 3544 3545 /* ----------- */ 3546 /* device bulk */ 3547 3548 static usbd_status 3549 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3550 { 3551 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3552 usbd_status err; 3553 3554 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3555 3556 /* Insert last in queue. */ 3557 mutex_enter(&sc->sc_lock); 3558 err = usb_insert_transfer(xfer); 3559 mutex_exit(&sc->sc_lock); 3560 if (err) 3561 return err; 3562 3563 /* 3564 * Pipe isn't running (otherwise err would be USBD_INPROG), 3565 * so start it first. 3566 */ 3567 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3568 } 3569 3570 static usbd_status 3571 xhci_device_bulk_start(struct usbd_xfer *xfer) 3572 { 3573 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3574 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3575 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3576 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3577 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3578 const uint32_t len = xfer->ux_length; 3579 usb_dma_t * const dma = &xfer->ux_dmabuf; 3580 uint64_t parameter; 3581 uint32_t status; 3582 uint32_t control; 3583 u_int i = 0; 3584 3585 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3586 3587 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3588 3589 if (sc->sc_dying) 3590 return USBD_IOERROR; 3591 3592 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3593 3594 parameter = DMAADDR(dma, 0); 3595 /* 3596 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3597 * If the user supplied buffer crosses such a boundary then 2 3598 * (or more) TRB should be used. 3599 * If multiple TRB are used the td_size field must be set correctly. 3600 * For v1.0 devices (like ivy bridge) this is the number of usb data 3601 * blocks needed to complete the transfer. 3602 * Setting it to 1 in the last TRB causes an extra zero-length 3603 * data block be sent. 3604 * The earlier documentation differs, I don't know how it behaves. 3605 */ 3606 KASSERT(len <= 0x10000); 3607 status = XHCI_TRB_2_IRQ_SET(0) | 3608 XHCI_TRB_2_TDSZ_SET(1) | 3609 XHCI_TRB_2_BYTES_SET(len); 3610 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3611 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3612 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3613 3614 mutex_enter(&tr->xr_lock); 3615 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3616 mutex_exit(&tr->xr_lock); 3617 3618 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3619 3620 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3621 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3622 xhci_timeout, xfer); 3623 } 3624 3625 return USBD_IN_PROGRESS; 3626 } 3627 3628 static void 3629 xhci_device_bulk_done(struct usbd_xfer *xfer) 3630 { 3631 #ifdef USB_DEBUG 3632 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3633 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3634 #endif 3635 const int isread = usbd_xfer_isread(xfer); 3636 3637 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3638 3639 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3640 3641 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3642 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3643 } 3644 3645 static void 3646 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3647 { 3648 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3649 3650 xhci_abort_xfer(xfer, USBD_CANCELLED); 3651 } 3652 3653 static void 3654 xhci_device_bulk_close(struct usbd_pipe *pipe) 3655 { 3656 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3657 3658 xhci_close_pipe(pipe); 3659 } 3660 3661 /* ---------------- */ 3662 /* device interrupt */ 3663 3664 static usbd_status 3665 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3666 { 3667 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3668 usbd_status err; 3669 3670 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3671 3672 /* Insert last in queue. */ 3673 mutex_enter(&sc->sc_lock); 3674 err = usb_insert_transfer(xfer); 3675 mutex_exit(&sc->sc_lock); 3676 if (err) 3677 return err; 3678 3679 /* 3680 * Pipe isn't running (otherwise err would be USBD_INPROG), 3681 * so start it first. 3682 */ 3683 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3684 } 3685 3686 static usbd_status 3687 xhci_device_intr_start(struct usbd_xfer *xfer) 3688 { 3689 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3690 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3691 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3692 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3693 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3694 const uint32_t len = xfer->ux_length; 3695 usb_dma_t * const dma = &xfer->ux_dmabuf; 3696 uint64_t parameter; 3697 uint32_t status; 3698 uint32_t control; 3699 u_int i = 0; 3700 3701 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3702 3703 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3704 3705 if (sc->sc_dying) 3706 return USBD_IOERROR; 3707 3708 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3709 3710 parameter = DMAADDR(dma, 0); 3711 KASSERT(len <= 0x10000); 3712 status = XHCI_TRB_2_IRQ_SET(0) | 3713 XHCI_TRB_2_TDSZ_SET(1) | 3714 XHCI_TRB_2_BYTES_SET(len); 3715 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3716 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3717 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3718 3719 mutex_enter(&tr->xr_lock); 3720 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3721 mutex_exit(&tr->xr_lock); 3722 3723 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3724 3725 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3726 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3727 xhci_timeout, xfer); 3728 } 3729 3730 return USBD_IN_PROGRESS; 3731 } 3732 3733 static void 3734 xhci_device_intr_done(struct usbd_xfer *xfer) 3735 { 3736 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3737 #ifdef USB_DEBUG 3738 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3739 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3740 #endif 3741 const int isread = usbd_xfer_isread(xfer); 3742 3743 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3744 3745 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3746 3747 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3748 3749 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3750 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3751 } 3752 3753 static void 3754 xhci_device_intr_abort(struct usbd_xfer *xfer) 3755 { 3756 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3757 3758 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3759 3760 KASSERT(mutex_owned(&sc->sc_lock)); 3761 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3762 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3763 xhci_abort_xfer(xfer, USBD_CANCELLED); 3764 } 3765 3766 static void 3767 xhci_device_intr_close(struct usbd_pipe *pipe) 3768 { 3769 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3770 3771 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3772 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3773 3774 xhci_close_pipe(pipe); 3775 } 3776 3777 /* ------------ */ 3778 3779 static void 3780 xhci_timeout(void *addr) 3781 { 3782 struct xhci_xfer * const xx = addr; 3783 struct usbd_xfer * const xfer = &xx->xx_xfer; 3784 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3785 3786 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3787 3788 if (sc->sc_dying) { 3789 return; 3790 } 3791 3792 usb_init_task(&xfer->ux_aborttask, xhci_timeout_task, addr, 3793 USB_TASKQ_MPSAFE); 3794 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xfer->ux_aborttask, 3795 USB_TASKQ_HC); 3796 } 3797 3798 static void 3799 xhci_timeout_task(void *addr) 3800 { 3801 struct usbd_xfer * const xfer = addr; 3802 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3803 3804 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3805 3806 mutex_enter(&sc->sc_lock); 3807 #if 0 3808 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3809 #else 3810 xfer->ux_status = USBD_TIMEOUT; 3811 usb_transfer_complete(xfer); 3812 #endif 3813 mutex_exit(&sc->sc_lock); 3814 } 3815
Indexes created Wed Oct 01 15:09:59 GMT 2025