xhci.c revision 1.28.2.77
1 /* $NetBSD: xhci.c,v 1.28.2.77 2016/10/05 20:55:59 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.28.2.77 2016/10/05 20:55:59 skrll Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static void xhci_host_dequeue(struct xhci_ring * const); 146 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 147 148 static usbd_status xhci_do_command(struct xhci_softc * const, 149 struct xhci_trb * const, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 153 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 154 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 155 static usbd_status xhci_enable_slot(struct xhci_softc * const, 156 uint8_t * const); 157 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 158 static usbd_status xhci_address_device(struct xhci_softc * const, 159 uint64_t, uint8_t, bool); 160 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 161 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 162 struct xhci_slot * const, u_int); 163 static usbd_status xhci_ring_init(struct xhci_softc * const, 164 struct xhci_ring * const, size_t, size_t); 165 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 166 167 static void xhci_setup_ctx(struct usbd_pipe *); 168 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 169 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 170 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 171 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 172 173 static void xhci_noop(struct usbd_pipe *); 174 175 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 176 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 177 static void xhci_root_intr_abort(struct usbd_xfer *); 178 static void xhci_root_intr_close(struct usbd_pipe *); 179 static void xhci_root_intr_done(struct usbd_xfer *); 180 181 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 182 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 183 static void xhci_device_ctrl_abort(struct usbd_xfer *); 184 static void xhci_device_ctrl_close(struct usbd_pipe *); 185 static void xhci_device_ctrl_done(struct usbd_xfer *); 186 187 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 188 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 189 static void xhci_device_intr_abort(struct usbd_xfer *); 190 static void xhci_device_intr_close(struct usbd_pipe *); 191 static void xhci_device_intr_done(struct usbd_xfer *); 192 193 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 194 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 195 static void xhci_device_bulk_abort(struct usbd_xfer *); 196 static void xhci_device_bulk_close(struct usbd_pipe *); 197 static void xhci_device_bulk_done(struct usbd_xfer *); 198 199 static void xhci_timeout(void *); 200 static void xhci_timeout_task(void *); 201 202 static const struct usbd_bus_methods xhci_bus_methods = { 203 .ubm_open = xhci_open, 204 .ubm_softint = xhci_softintr, 205 .ubm_dopoll = xhci_poll, 206 .ubm_allocx = xhci_allocx, 207 .ubm_freex = xhci_freex, 208 .ubm_getlock = xhci_get_lock, 209 .ubm_newdev = xhci_new_device, 210 .ubm_rhctrl = xhci_roothub_ctrl, 211 }; 212 213 static const struct usbd_pipe_methods xhci_root_intr_methods = { 214 .upm_transfer = xhci_root_intr_transfer, 215 .upm_start = xhci_root_intr_start, 216 .upm_abort = xhci_root_intr_abort, 217 .upm_close = xhci_root_intr_close, 218 .upm_cleartoggle = xhci_noop, 219 .upm_done = xhci_root_intr_done, 220 }; 221 222 223 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 224 .upm_transfer = xhci_device_ctrl_transfer, 225 .upm_start = xhci_device_ctrl_start, 226 .upm_abort = xhci_device_ctrl_abort, 227 .upm_close = xhci_device_ctrl_close, 228 .upm_cleartoggle = xhci_noop, 229 .upm_done = xhci_device_ctrl_done, 230 }; 231 232 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 233 .upm_cleartoggle = xhci_noop, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 237 .upm_transfer = xhci_device_bulk_transfer, 238 .upm_start = xhci_device_bulk_start, 239 .upm_abort = xhci_device_bulk_abort, 240 .upm_close = xhci_device_bulk_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_bulk_done, 243 }; 244 245 static const struct usbd_pipe_methods xhci_device_intr_methods = { 246 .upm_transfer = xhci_device_intr_transfer, 247 .upm_start = xhci_device_intr_start, 248 .upm_abort = xhci_device_intr_abort, 249 .upm_close = xhci_device_intr_close, 250 .upm_cleartoggle = xhci_noop, 251 .upm_done = xhci_device_intr_done, 252 }; 253 254 static inline uint32_t 255 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 256 { 257 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 258 } 259 260 static inline uint32_t 261 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 262 { 263 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 264 } 265 266 static inline void 267 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 268 uint32_t value) 269 { 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 271 } 272 273 #if 0 /* unused */ 274 static inline void 275 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 276 uint32_t value) 277 { 278 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 279 } 280 #endif /* unused */ 281 282 static inline uint32_t 283 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 284 { 285 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 286 } 287 288 static inline uint32_t 289 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 290 { 291 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 292 } 293 294 static inline void 295 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 296 uint32_t value) 297 { 298 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 299 } 300 301 static inline uint64_t 302 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 303 { 304 uint64_t value; 305 306 if (sc->sc_ac64) { 307 #ifdef XHCI_USE_BUS_SPACE_8 308 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 309 #else 310 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 311 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 312 offset + 4) << 32; 313 #endif 314 } else { 315 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 316 } 317 318 return value; 319 } 320 321 static inline void 322 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 336 } 337 } 338 339 static inline uint32_t 340 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 341 { 342 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 343 } 344 345 static inline void 346 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 347 uint32_t value) 348 { 349 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 350 } 351 352 #if 0 /* unused */ 353 static inline uint64_t 354 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 355 { 356 uint64_t value; 357 358 if (sc->sc_ac64) { 359 #ifdef XHCI_USE_BUS_SPACE_8 360 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 361 #else 362 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 363 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 364 offset + 4) << 32; 365 #endif 366 } else { 367 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 368 } 369 370 return value; 371 } 372 #endif /* unused */ 373 374 static inline void 375 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 376 uint64_t value) 377 { 378 if (sc->sc_ac64) { 379 #ifdef XHCI_USE_BUS_SPACE_8 380 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 381 #else 382 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 383 (value >> 0) & 0xffffffff); 384 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 385 (value >> 32) & 0xffffffff); 386 #endif 387 } else { 388 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 389 } 390 } 391 392 #if 0 /* unused */ 393 static inline uint32_t 394 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 395 { 396 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 397 } 398 #endif /* unused */ 399 400 static inline void 401 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 402 uint32_t value) 403 { 404 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 405 } 406 407 /* --- */ 408 409 static inline uint8_t 410 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 411 { 412 u_int eptype = 0; 413 414 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 415 case UE_CONTROL: 416 eptype = 0x0; 417 break; 418 case UE_ISOCHRONOUS: 419 eptype = 0x1; 420 break; 421 case UE_BULK: 422 eptype = 0x2; 423 break; 424 case UE_INTERRUPT: 425 eptype = 0x3; 426 break; 427 } 428 429 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 430 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 431 return eptype | 0x4; 432 else 433 return eptype; 434 } 435 436 static u_int 437 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 438 { 439 /* xHCI 1.0 section 4.5.1 */ 440 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 441 u_int in = 0; 442 443 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 444 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 445 in = 1; 446 447 return epaddr * 2 + in; 448 } 449 450 static inline u_int 451 xhci_dci_to_ici(const u_int i) 452 { 453 return i + 1; 454 } 455 456 static inline void * 457 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 458 const u_int dci) 459 { 460 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 461 } 462 463 #if 0 /* unused */ 464 static inline bus_addr_t 465 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 466 const u_int dci) 467 { 468 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 469 } 470 #endif /* unused */ 471 472 static inline void * 473 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline bus_addr_t 480 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 481 const u_int ici) 482 { 483 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 484 } 485 486 static inline struct xhci_trb * 487 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 488 { 489 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 490 } 491 492 static inline bus_addr_t 493 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 494 { 495 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 496 } 497 498 static inline void 499 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 500 uint32_t control) 501 { 502 trb->trb_0 = htole64(parameter); 503 trb->trb_2 = htole32(status); 504 trb->trb_3 = htole32(control); 505 } 506 507 static int 508 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 509 { 510 /* base address of TRBs */ 511 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 512 513 /* trb_0 range sanity check */ 514 if (trb_0 == 0 || trb_0 < trbp || 515 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 516 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 517 return 1; 518 } 519 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 520 return 0; 521 } 522 523 static unsigned int 524 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 525 u_int dci) 526 { 527 uint32_t *cp; 528 529 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 530 cp = xhci_slot_get_dcv(sc, xs, dci); 531 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 532 } 533 534 /* --- */ 535 536 void 537 xhci_childdet(device_t self, device_t child) 538 { 539 struct xhci_softc * const sc = device_private(self); 540 541 KASSERT(sc->sc_child == child); 542 if (child == sc->sc_child) 543 sc->sc_child = NULL; 544 } 545 546 int 547 xhci_detach(struct xhci_softc *sc, int flags) 548 { 549 int rv = 0; 550 551 if (sc->sc_child != NULL) 552 rv = config_detach(sc->sc_child, flags); 553 554 if (rv != 0) 555 return rv; 556 557 /* XXX unconfigure/free slots */ 558 559 /* verify: */ 560 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 561 xhci_op_write_4(sc, XHCI_USBCMD, 0); 562 /* do we need to wait for stop? */ 563 564 xhci_op_write_8(sc, XHCI_CRCR, 0); 565 xhci_ring_free(sc, &sc->sc_cr); 566 cv_destroy(&sc->sc_command_cv); 567 cv_destroy(&sc->sc_cmdbusy_cv); 568 569 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 570 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 571 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 572 xhci_ring_free(sc, &sc->sc_er); 573 574 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 575 576 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 577 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 578 579 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 580 581 mutex_destroy(&sc->sc_lock); 582 mutex_destroy(&sc->sc_intr_lock); 583 584 pool_cache_destroy(sc->sc_xferpool); 585 586 return rv; 587 } 588 589 int 590 xhci_activate(device_t self, enum devact act) 591 { 592 struct xhci_softc * const sc = device_private(self); 593 594 switch (act) { 595 case DVACT_DEACTIVATE: 596 sc->sc_dying = true; 597 return 0; 598 default: 599 return EOPNOTSUPP; 600 } 601 } 602 603 bool 604 xhci_suspend(device_t dv, const pmf_qual_t *qual) 605 { 606 return false; 607 } 608 609 bool 610 xhci_resume(device_t dv, const pmf_qual_t *qual) 611 { 612 return false; 613 } 614 615 bool 616 xhci_shutdown(device_t self, int flags) 617 { 618 return false; 619 } 620 621 static int 622 xhci_hc_reset(struct xhci_softc * const sc) 623 { 624 uint32_t usbcmd, usbsts; 625 int i; 626 627 /* Check controller not ready */ 628 for (i = 0; i < XHCI_WAIT_CNR; i++) { 629 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 630 if ((usbsts & XHCI_STS_CNR) == 0) 631 break; 632 usb_delay_ms(&sc->sc_bus, 1); 633 } 634 if (i >= XHCI_WAIT_CNR) { 635 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 636 return EIO; 637 } 638 639 /* Halt controller */ 640 usbcmd = 0; 641 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 642 usb_delay_ms(&sc->sc_bus, 1); 643 644 /* Reset controller */ 645 usbcmd = XHCI_CMD_HCRST; 646 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 647 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 648 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 649 if ((usbcmd & XHCI_CMD_HCRST) == 0) 650 break; 651 usb_delay_ms(&sc->sc_bus, 1); 652 } 653 if (i >= XHCI_WAIT_HCRST) { 654 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 655 return EIO; 656 } 657 658 /* Check controller not ready */ 659 for (i = 0; i < XHCI_WAIT_CNR; i++) { 660 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 661 if ((usbsts & XHCI_STS_CNR) == 0) 662 break; 663 usb_delay_ms(&sc->sc_bus, 1); 664 } 665 if (i >= XHCI_WAIT_CNR) { 666 aprint_error_dev(sc->sc_dev, 667 "controller not ready timeout after reset\n"); 668 return EIO; 669 } 670 671 return 0; 672 } 673 674 675 static void 676 hexdump(const char *msg, const void *base, size_t len) 677 { 678 #if 0 679 size_t cnt; 680 const uint32_t *p; 681 extern paddr_t vtophys(vaddr_t); 682 683 p = base; 684 cnt = 0; 685 686 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 687 (void *)vtophys((vaddr_t)base)); 688 689 while (cnt < len) { 690 if (cnt % 16 == 0) 691 printf("%p: ", p); 692 else if (cnt % 8 == 0) 693 printf(" |"); 694 printf(" %08x", *p++); 695 cnt += 4; 696 if (cnt % 16 == 0) 697 printf("\n"); 698 } 699 if (cnt % 16 != 0) 700 printf("\n"); 701 #endif 702 } 703 704 /* Process extended capabilities */ 705 static void 706 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 707 { 708 uint32_t ecp, ecr; 709 710 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 711 712 ecp = XHCI_HCC_XECP(hcc) * 4; 713 while (ecp != 0) { 714 ecr = xhci_read_4(sc, ecp); 715 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 716 switch (XHCI_XECP_ID(ecr)) { 717 case XHCI_ID_PROTOCOLS: { 718 uint32_t w4, w8, wc; 719 uint16_t w2; 720 w2 = (ecr >> 16) & 0xffff; 721 w4 = xhci_read_4(sc, ecp + 4); 722 w8 = xhci_read_4(sc, ecp + 8); 723 wc = xhci_read_4(sc, ecp + 0xc); 724 aprint_debug_dev(sc->sc_dev, 725 " SP: %08x %08x %08x %08x\n", ecr, w4, w8, wc); 726 /* unused */ 727 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0300) { 728 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 729 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 730 } 731 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0200) { 732 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 733 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 734 } 735 break; 736 } 737 case XHCI_ID_USB_LEGACY: { 738 uint8_t bios_sem; 739 740 /* Take host controller ownership from BIOS */ 741 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 742 if (bios_sem) { 743 /* sets xHCI to be owned by OS */ 744 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 745 aprint_debug_dev(sc->sc_dev, 746 "waiting for BIOS to give up control\n"); 747 for (int i = 0; i < 5000; i++) { 748 bios_sem = xhci_read_1(sc, ecp + 749 XHCI_XECP_BIOS_SEM); 750 if (bios_sem == 0) 751 break; 752 DELAY(1000); 753 } 754 if (bios_sem) { 755 aprint_error_dev(sc->sc_dev, 756 "timed out waiting for BIOS\n"); 757 } 758 } 759 break; 760 } 761 default: 762 break; 763 } 764 ecr = xhci_read_4(sc, ecp); 765 if (XHCI_XECP_NEXT(ecr) == 0) { 766 ecp = 0; 767 } else { 768 ecp += XHCI_XECP_NEXT(ecr) * 4; 769 } 770 } 771 } 772 773 #define XHCI_HCCPREV1_BITS \ 774 "\177\020" /* New bitmask */ \ 775 "f\020\020XECP\0" \ 776 "f\014\4MAXPSA\0" \ 777 "b\013CFC\0" \ 778 "b\012SEC\0" \ 779 "b\011SBD\0" \ 780 "b\010FSE\0" \ 781 "b\7NSS\0" \ 782 "b\6LTC\0" \ 783 "b\5LHRC\0" \ 784 "b\4PIND\0" \ 785 "b\3PPC\0" \ 786 "b\2CZC\0" \ 787 "b\1BNC\0" \ 788 "b\0AC64\0" \ 789 "\0" 790 #define XHCI_HCCV1_x_BITS \ 791 "\177\020" /* New bitmask */ \ 792 "f\020\020XECP\0" \ 793 "f\014\4MAXPSA\0" \ 794 "b\013CFC\0" \ 795 "b\012SEC\0" \ 796 "b\011SPC\0" \ 797 "b\010PAE\0" \ 798 "b\7NSS\0" \ 799 "b\6LTC\0" \ 800 "b\5LHRC\0" \ 801 "b\4PIND\0" \ 802 "b\3PPC\0" \ 803 "b\2CSZ\0" \ 804 "b\1BNC\0" \ 805 "b\0AC64\0" \ 806 "\0" 807 808 int 809 xhci_init(struct xhci_softc *sc) 810 { 811 bus_size_t bsz; 812 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 813 uint32_t pagesize, config; 814 int i = 0; 815 uint16_t hciversion; 816 uint8_t caplength; 817 818 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 819 820 sc->sc_bus.ub_revision = USBREV_3_0; 821 sc->sc_bus.ub_usedma = true; 822 823 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 824 caplength = XHCI_CAP_CAPLENGTH(cap); 825 hciversion = XHCI_CAP_HCIVERSION(cap); 826 827 if (hciversion < XHCI_HCIVERSION_0_96 || 828 hciversion > XHCI_HCIVERSION_1_0) { 829 aprint_normal_dev(sc->sc_dev, 830 "xHCI version %x.%x not known to be supported\n", 831 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 832 } else { 833 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 834 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 835 } 836 837 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 838 &sc->sc_cbh) != 0) { 839 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 840 return ENOMEM; 841 } 842 843 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 844 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 845 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 846 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 847 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 848 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 849 aprint_debug_dev(sc->sc_dev, 850 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 851 852 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 853 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 854 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 855 856 char sbuf[128]; 857 if (hciversion < XHCI_HCIVERSION_1_0) 858 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 859 else 860 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 861 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 862 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 863 864 /* print PSI and take ownership from BIOS */ 865 xhci_ecp(sc, hcc); 866 867 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 868 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 869 &sc->sc_obh) != 0) { 870 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 871 return ENOMEM; 872 } 873 874 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 875 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 876 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 877 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 878 return ENOMEM; 879 } 880 881 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 882 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 883 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 884 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 885 return ENOMEM; 886 } 887 888 int rv; 889 rv = xhci_hc_reset(sc); 890 if (rv != 0) { 891 return rv; 892 } 893 894 if (sc->sc_vendor_init) 895 sc->sc_vendor_init(sc); 896 897 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 898 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 899 pagesize = ffs(pagesize); 900 if (pagesize == 0) { 901 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 902 return EIO; 903 } 904 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 905 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 906 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 907 (uint32_t)sc->sc_maxslots); 908 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 909 910 usbd_status err; 911 912 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 913 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 914 if (sc->sc_maxspbuf != 0) { 915 err = usb_allocmem(&sc->sc_bus, 916 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 917 &sc->sc_spbufarray_dma); 918 if (err) { 919 aprint_error_dev(sc->sc_dev, 920 "spbufarray init fail, err %d\n", err); 921 return ENOMEM; 922 } 923 924 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 925 sc->sc_maxspbuf, KM_SLEEP); 926 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 927 for (i = 0; i < sc->sc_maxspbuf; i++) { 928 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 929 /* allocate contexts */ 930 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 931 sc->sc_pgsz, dma); 932 if (err) { 933 aprint_error_dev(sc->sc_dev, 934 "spbufarray_dma init fail, err %d\n", err); 935 rv = ENOMEM; 936 goto bad1; 937 } 938 spbufarray[i] = htole64(DMAADDR(dma, 0)); 939 usb_syncmem(dma, 0, sc->sc_pgsz, 940 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 941 } 942 943 usb_syncmem(&sc->sc_spbufarray_dma, 0, 944 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 945 } 946 947 config = xhci_op_read_4(sc, XHCI_CONFIG); 948 config &= ~0xFF; 949 config |= sc->sc_maxslots & 0xFF; 950 xhci_op_write_4(sc, XHCI_CONFIG, config); 951 952 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 953 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 954 if (err) { 955 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 956 err); 957 rv = ENOMEM; 958 goto bad1; 959 } 960 961 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 962 XHCI_EVENT_RING_SEGMENTS_ALIGN); 963 if (err) { 964 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 965 err); 966 rv = ENOMEM; 967 goto bad2; 968 } 969 970 usb_dma_t *dma; 971 size_t size; 972 size_t align; 973 974 dma = &sc->sc_eventst_dma; 975 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 976 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 977 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 978 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 979 err = usb_allocmem(&sc->sc_bus, size, align, dma); 980 if (err) { 981 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 982 err); 983 rv = ENOMEM; 984 goto bad3; 985 } 986 987 memset(KERNADDR(dma, 0), 0, size); 988 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 989 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 990 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 991 KERNADDR(&sc->sc_eventst_dma, 0), 992 sc->sc_eventst_dma.udma_block->size); 993 994 dma = &sc->sc_dcbaa_dma; 995 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 996 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 997 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 998 err = usb_allocmem(&sc->sc_bus, size, align, dma); 999 if (err) { 1000 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1001 rv = ENOMEM; 1002 goto bad4; 1003 } 1004 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 1005 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1006 KERNADDR(&sc->sc_dcbaa_dma, 0), 1007 sc->sc_dcbaa_dma.udma_block->size); 1008 1009 memset(KERNADDR(dma, 0), 0, size); 1010 if (sc->sc_maxspbuf != 0) { 1011 /* 1012 * DCBA entry 0 hold the scratchbuf array pointer. 1013 */ 1014 *(uint64_t *)KERNADDR(dma, 0) = 1015 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1016 } 1017 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1018 1019 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1020 KM_SLEEP); 1021 if (sc->sc_slots == NULL) { 1022 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1023 rv = ENOMEM; 1024 goto bad; 1025 } 1026 1027 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1028 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1029 if (sc->sc_xferpool == NULL) { 1030 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1031 err); 1032 rv = ENOMEM; 1033 goto bad; 1034 } 1035 1036 cv_init(&sc->sc_command_cv, "xhcicmd"); 1037 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1038 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1039 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1040 1041 /* Set up the bus struct. */ 1042 sc->sc_bus.ub_methods = &xhci_bus_methods; 1043 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 1044 1045 struct xhci_erste *erst; 1046 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1047 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1048 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1049 erst[0].erste_3 = htole32(0); 1050 usb_syncmem(&sc->sc_eventst_dma, 0, 1051 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1052 1053 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1054 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1055 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1056 XHCI_ERDP_LO_BUSY); 1057 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1058 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1059 sc->sc_cr.xr_cs); 1060 1061 #if 0 1062 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1063 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1064 #endif 1065 1066 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1067 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1068 /* Intel xhci needs interrupt rate moderated. */ 1069 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1070 else 1071 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1072 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 1073 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1074 1075 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 1076 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1077 xhci_op_read_4(sc, XHCI_USBCMD)); 1078 1079 return 0; 1080 1081 bad: 1082 if (sc->sc_xferpool) { 1083 pool_cache_destroy(sc->sc_xferpool); 1084 sc->sc_xferpool = NULL; 1085 } 1086 1087 if (sc->sc_slots) { 1088 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1089 sc->sc_maxslots); 1090 sc->sc_slots = NULL; 1091 } 1092 1093 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1094 bad4: 1095 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1096 bad3: 1097 xhci_ring_free(sc, &sc->sc_er); 1098 bad2: 1099 xhci_ring_free(sc, &sc->sc_cr); 1100 i = sc->sc_maxspbuf; 1101 bad1: 1102 for (int j = 0; j < i; j++) 1103 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1104 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1105 1106 return rv; 1107 } 1108 1109 int 1110 xhci_intr(void *v) 1111 { 1112 struct xhci_softc * const sc = v; 1113 int ret = 0; 1114 1115 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1116 1117 if (sc == NULL) 1118 return 0; 1119 1120 mutex_spin_enter(&sc->sc_intr_lock); 1121 1122 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1123 goto done; 1124 1125 /* If we get an interrupt while polling, then just ignore it. */ 1126 if (sc->sc_bus.ub_usepolling) { 1127 #ifdef DIAGNOSTIC 1128 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1129 #endif 1130 goto done; 1131 } 1132 1133 ret = xhci_intr1(sc); 1134 done: 1135 mutex_spin_exit(&sc->sc_intr_lock); 1136 return ret; 1137 } 1138 1139 int 1140 xhci_intr1(struct xhci_softc * const sc) 1141 { 1142 uint32_t usbsts; 1143 uint32_t iman; 1144 1145 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1146 1147 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1148 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1149 #if 0 1150 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1151 return 0; 1152 } 1153 #endif 1154 xhci_op_write_4(sc, XHCI_USBSTS, 1155 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1156 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1157 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1158 1159 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1160 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1161 iman |= XHCI_IMAN_INTR_PEND; 1162 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1163 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1164 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1165 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1166 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1167 1168 usb_schedsoftintr(&sc->sc_bus); 1169 1170 return 1; 1171 } 1172 1173 /* 1174 * 3 port speed types used in USB stack 1175 * 1176 * usbdi speed 1177 * definition: USB_SPEED_* in usb.h 1178 * They are used in struct usbd_device in USB stack. 1179 * ioctl interface uses these values too. 1180 * port_status speed 1181 * definition: UPS_*_SPEED in usb.h 1182 * They are used in usb_port_status_t and valid only for USB 2.0. 1183 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1184 * of usb_port_status_ext_t indicates port speed. 1185 * Note that some 3.0 values overlap with 2.0 values. 1186 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1187 * means UPS_LOW_SPEED in HS.) 1188 * port status returned from hub also uses these values. 1189 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1190 * or more. 1191 * xspeed: 1192 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1193 * They are used in only slot context and PORTSC reg of xhci. 1194 * The difference between usbdi speed and xspeed is 1195 * that FS and LS values are swapped. 1196 */ 1197 1198 /* convert usbdi speed to xspeed */ 1199 static int 1200 xhci_speed2xspeed(int speed) 1201 { 1202 switch (speed) { 1203 case USB_SPEED_LOW: return 2; 1204 case USB_SPEED_FULL: return 1; 1205 default: return speed; 1206 } 1207 } 1208 1209 #if 0 1210 /* convert xspeed to usbdi speed */ 1211 static int 1212 xhci_xspeed2speed(int xspeed) 1213 { 1214 switch (xspeed) { 1215 case 1: return USB_SPEED_FULL; 1216 case 2: return USB_SPEED_LOW; 1217 default: return xspeed; 1218 } 1219 } 1220 #endif 1221 1222 /* convert xspeed to port status speed */ 1223 static int 1224 xhci_xspeed2psspeed(int xspeed) 1225 { 1226 switch (xspeed) { 1227 case 0: return 0; 1228 case 1: return UPS_FULL_SPEED; 1229 case 2: return UPS_LOW_SPEED; 1230 case 3: return UPS_HIGH_SPEED; 1231 default: return UPS_OTHER_SPEED; 1232 } 1233 } 1234 1235 /* 1236 * Construct input contexts and issue TRB to open pipe. 1237 */ 1238 static usbd_status 1239 xhci_configure_endpoint(struct usbd_pipe *pipe) 1240 { 1241 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1242 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1243 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1244 struct xhci_trb trb; 1245 usbd_status err; 1246 1247 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1248 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1249 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1250 pipe->up_endpoint->ue_edesc->bmAttributes); 1251 1252 /* XXX ensure input context is available? */ 1253 1254 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1255 1256 /* set up context */ 1257 xhci_setup_ctx(pipe); 1258 1259 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1260 sc->sc_ctxsz * 1); 1261 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1262 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1263 1264 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1265 trb.trb_2 = 0; 1266 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1267 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1268 1269 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1270 1271 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1272 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1273 sc->sc_ctxsz * 1); 1274 1275 return err; 1276 } 1277 1278 #if 0 1279 static usbd_status 1280 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1281 { 1282 #ifdef USB_DEBUG 1283 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1284 #endif 1285 1286 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1287 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1288 1289 return USBD_NORMAL_COMPLETION; 1290 } 1291 #endif 1292 1293 /* 4.6.8, 6.4.3.7 */ 1294 static usbd_status 1295 xhci_reset_endpoint_locked(struct usbd_pipe *pipe) 1296 { 1297 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1298 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1299 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1300 struct xhci_trb trb; 1301 usbd_status err; 1302 1303 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1304 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1305 1306 KASSERT(mutex_owned(&sc->sc_lock)); 1307 1308 trb.trb_0 = 0; 1309 trb.trb_2 = 0; 1310 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1311 XHCI_TRB_3_EP_SET(dci) | 1312 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1313 1314 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1315 1316 return err; 1317 } 1318 1319 static usbd_status 1320 xhci_reset_endpoint(struct usbd_pipe *pipe) 1321 { 1322 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1323 1324 mutex_enter(&sc->sc_lock); 1325 usbd_status ret = xhci_reset_endpoint_locked(pipe); 1326 mutex_exit(&sc->sc_lock); 1327 1328 return ret; 1329 } 1330 1331 /* 1332 * 4.6.9, 6.4.3.8 1333 * Stop execution of TDs on xfer ring. 1334 * Should be called with sc_lock held. 1335 */ 1336 static usbd_status 1337 xhci_stop_endpoint(struct usbd_pipe *pipe) 1338 { 1339 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1340 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1341 struct xhci_trb trb; 1342 usbd_status err; 1343 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1344 1345 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1346 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1347 1348 KASSERT(mutex_owned(&sc->sc_lock)); 1349 1350 trb.trb_0 = 0; 1351 trb.trb_2 = 0; 1352 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1353 XHCI_TRB_3_EP_SET(dci) | 1354 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1355 1356 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1357 1358 return err; 1359 } 1360 1361 /* 1362 * Set TR Dequeue Pointer. 1363 * xHCI 1.1 4.6.10 6.4.3.9 1364 * Purge all of the TRBs on ring and reinitialize ring. 1365 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1366 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1367 * error will be generated. 1368 */ 1369 static usbd_status 1370 xhci_set_dequeue_locked(struct usbd_pipe *pipe) 1371 { 1372 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1373 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1374 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1375 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1376 struct xhci_trb trb; 1377 usbd_status err; 1378 1379 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1380 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1381 1382 KASSERT(mutex_owned(&sc->sc_lock)); 1383 1384 xhci_host_dequeue(xr); 1385 1386 /* set DCS */ 1387 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1388 trb.trb_2 = 0; 1389 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1390 XHCI_TRB_3_EP_SET(dci) | 1391 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1392 1393 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1394 1395 return err; 1396 } 1397 1398 static usbd_status 1399 xhci_set_dequeue(struct usbd_pipe *pipe) 1400 { 1401 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1402 1403 mutex_enter(&sc->sc_lock); 1404 usbd_status ret = xhci_set_dequeue_locked(pipe); 1405 mutex_exit(&sc->sc_lock); 1406 1407 return ret; 1408 } 1409 1410 /* 1411 * Open new pipe: called from usbd_setup_pipe_flags. 1412 * Fills methods of pipe. 1413 * If pipe is not for ep0, calls configure_endpoint. 1414 */ 1415 static usbd_status 1416 xhci_open(struct usbd_pipe *pipe) 1417 { 1418 struct usbd_device * const dev = pipe->up_dev; 1419 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1420 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1421 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1422 1423 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1424 DPRINTFN(1, "addr %d depth %d port %d speed %d", dev->ud_addr, 1425 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1426 DPRINTFN(1, " dci %u type 0x%02x epaddr 0x%02x attr 0x%02x", 1427 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1428 ed->bmAttributes); 1429 DPRINTFN(1, " mps %u ival %u", UGETW(ed->wMaxPacketSize), ed->bInterval, 1430 0, 0); 1431 1432 if (sc->sc_dying) 1433 return USBD_IOERROR; 1434 1435 /* Root Hub */ 1436 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1437 switch (ed->bEndpointAddress) { 1438 case USB_CONTROL_ENDPOINT: 1439 pipe->up_methods = &roothub_ctrl_methods; 1440 break; 1441 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1442 pipe->up_methods = &xhci_root_intr_methods; 1443 break; 1444 default: 1445 pipe->up_methods = NULL; 1446 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1447 ed->bEndpointAddress, 0, 0, 0); 1448 return USBD_INVAL; 1449 } 1450 return USBD_NORMAL_COMPLETION; 1451 } 1452 1453 switch (xfertype) { 1454 case UE_CONTROL: 1455 pipe->up_methods = &xhci_device_ctrl_methods; 1456 break; 1457 case UE_ISOCHRONOUS: 1458 pipe->up_methods = &xhci_device_isoc_methods; 1459 return USBD_INVAL; 1460 break; 1461 case UE_BULK: 1462 pipe->up_methods = &xhci_device_bulk_methods; 1463 break; 1464 case UE_INTERRUPT: 1465 pipe->up_methods = &xhci_device_intr_methods; 1466 break; 1467 default: 1468 return USBD_IOERROR; 1469 break; 1470 } 1471 1472 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1473 return xhci_configure_endpoint(pipe); 1474 1475 return USBD_NORMAL_COMPLETION; 1476 } 1477 1478 /* 1479 * Closes pipe, called from usbd_kill_pipe via close methods. 1480 * If the endpoint to be closed is ep0, disable_slot. 1481 * Should be called with sc_lock held. 1482 */ 1483 static void 1484 xhci_close_pipe(struct usbd_pipe *pipe) 1485 { 1486 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1487 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1488 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1489 const u_int dci = xhci_ep_get_dci(ed); 1490 struct xhci_trb trb; 1491 uint32_t *cp; 1492 1493 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1494 1495 if (sc->sc_dying) 1496 return; 1497 1498 /* xs is uninitialized before xhci_init_slot */ 1499 if (xs == NULL || xs->xs_idx == 0) 1500 return; 1501 1502 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1503 1504 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1505 KASSERT(mutex_owned(&sc->sc_lock)); 1506 1507 if (pipe->up_dev->ud_depth == 0) 1508 return; 1509 1510 if (dci == XHCI_DCI_EP_CONTROL) { 1511 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1512 xhci_disable_slot(sc, xs->xs_idx); 1513 return; 1514 } 1515 1516 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED) 1517 (void)xhci_stop_endpoint(pipe); 1518 1519 /* 1520 * set appropriate bit to be dropped. 1521 * don't set DC bit to 1, otherwise all endpoints 1522 * would be deconfigured. 1523 */ 1524 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1525 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1526 cp[1] = htole32(0); 1527 1528 /* XXX should be most significant one, not dci? */ 1529 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1530 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1531 1532 /* configure ep context performs an implicit dequeue */ 1533 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 1534 1535 /* sync input contexts before they are read from memory */ 1536 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1537 1538 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1539 trb.trb_2 = 0; 1540 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1541 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1542 1543 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1544 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1545 } 1546 1547 /* 1548 * Abort transfer. 1549 * Should be called with sc_lock held. 1550 */ 1551 static void 1552 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1553 { 1554 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1555 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1556 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1557 1558 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1559 DPRINTFN(4, "xfer %p pipe %p status %d", 1560 xfer, xfer->ux_pipe, status, 0); 1561 1562 KASSERT(mutex_owned(&sc->sc_lock)); 1563 1564 if (sc->sc_dying) { 1565 /* If we're dying, just do the software part. */ 1566 DPRINTFN(4, "xfer %p dying %u", xfer, xfer->ux_status, 0, 0); 1567 xfer->ux_status = status; 1568 callout_stop(&xfer->ux_callout); 1569 usb_transfer_complete(xfer); 1570 return; 1571 } 1572 1573 /* 1574 * If an abort is already in progress then just wait for it to 1575 * complete and return. 1576 */ 1577 if (xfer->ux_hcflags & UXFER_ABORTING) { 1578 DPRINTFN(4, "already aborting", 0, 0, 0, 0); 1579 #ifdef DIAGNOSTIC 1580 if (status == USBD_TIMEOUT) 1581 DPRINTFN(4, "TIMEOUT while aborting", 0, 0, 0, 0); 1582 #endif 1583 /* Override the status which might be USBD_TIMEOUT. */ 1584 xfer->ux_status = status; 1585 DPRINTFN(4, "xfer %p waiting for abort to finish", xfer, 0, 0, 1586 0); 1587 xfer->ux_hcflags |= UXFER_ABORTWAIT; 1588 while (xfer->ux_hcflags & UXFER_ABORTING) 1589 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 1590 return; 1591 } 1592 xfer->ux_hcflags |= UXFER_ABORTING; 1593 1594 /* 1595 * Step 1: Stop xfer timeout timer. 1596 */ 1597 xfer->ux_status = status; 1598 callout_stop(&xfer->ux_callout); 1599 1600 /* 1601 * Step 2: Stop execution of TD on the ring. 1602 */ 1603 switch (xhci_get_epstate(sc, xs, dci)) { 1604 case XHCI_EPSTATE_HALTED: 1605 (void)xhci_reset_endpoint_locked(xfer->ux_pipe); 1606 break; 1607 case XHCI_EPSTATE_STOPPED: 1608 break; 1609 default: 1610 (void)xhci_stop_endpoint(xfer->ux_pipe); 1611 break; 1612 } 1613 #ifdef DIAGNOSTIC 1614 uint32_t epst = xhci_get_epstate(sc, xs, dci); 1615 if (epst != XHCI_EPSTATE_STOPPED) 1616 DPRINTFN(4, "dci %u not stopped %u", dci, epst, 0, 0); 1617 #endif 1618 1619 /* 1620 * Step 3: Remove any vestiges of the xfer from the ring. 1621 */ 1622 xhci_set_dequeue_locked(xfer->ux_pipe); 1623 1624 /* 1625 * Step 4: Notify completion to waiting xfers. 1626 */ 1627 int wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 1628 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 1629 usb_transfer_complete(xfer); 1630 if (wake) { 1631 cv_broadcast(&xfer->ux_hccv); 1632 } 1633 DPRINTFN(14, "end", 0, 0, 0, 0); 1634 1635 KASSERT(mutex_owned(&sc->sc_lock)); 1636 } 1637 1638 static void 1639 xhci_host_dequeue(struct xhci_ring * const xr) 1640 { 1641 /* When dequeueing the controller, update our struct copy too */ 1642 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1643 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1644 BUS_DMASYNC_PREWRITE); 1645 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1646 1647 xr->xr_ep = 0; 1648 xr->xr_cs = 1; 1649 } 1650 1651 /* 1652 * Recover STALLed endpoint. 1653 * xHCI 1.1 sect 4.10.2.1 1654 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1655 * all transfers on transfer ring. 1656 * These are done in thread context asynchronously. 1657 */ 1658 static void 1659 xhci_clear_endpoint_stall_async_task(void *cookie) 1660 { 1661 struct usbd_xfer * const xfer = cookie; 1662 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1663 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1664 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1665 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1666 1667 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1668 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1669 1670 xhci_reset_endpoint(xfer->ux_pipe); 1671 xhci_set_dequeue(xfer->ux_pipe); 1672 1673 mutex_enter(&sc->sc_lock); 1674 tr->is_halted = false; 1675 usb_transfer_complete(xfer); 1676 mutex_exit(&sc->sc_lock); 1677 DPRINTFN(4, "ends", 0, 0, 0, 0); 1678 } 1679 1680 static usbd_status 1681 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1682 { 1683 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1684 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1685 1686 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1687 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1688 1689 if (sc->sc_dying) { 1690 return USBD_IOERROR; 1691 } 1692 1693 usb_init_task(&xp->xp_async_task, 1694 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1695 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1696 DPRINTFN(4, "ends", 0, 0, 0, 0); 1697 1698 return USBD_NORMAL_COMPLETION; 1699 } 1700 1701 /* Process roothub port status/change events and notify to uhub_intr. */ 1702 static void 1703 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1704 { 1705 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1706 uint8_t *p; 1707 1708 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1709 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1710 port, 0, 0); 1711 1712 if (xfer == NULL) 1713 return; 1714 1715 if (port > sc->sc_maxports) 1716 return; 1717 1718 p = xfer->ux_buf; 1719 memset(p, 0, xfer->ux_length); 1720 p[port/NBBY] |= 1 << (port%NBBY); 1721 xfer->ux_actlen = xfer->ux_length; 1722 xfer->ux_status = USBD_NORMAL_COMPLETION; 1723 usb_transfer_complete(xfer); 1724 } 1725 1726 /* Process Transfer Events */ 1727 static void 1728 xhci_event_transfer(struct xhci_softc * const sc, 1729 const struct xhci_trb * const trb) 1730 { 1731 uint64_t trb_0; 1732 uint32_t trb_2, trb_3; 1733 uint8_t trbcode; 1734 u_int slot, dci; 1735 struct xhci_slot *xs; 1736 struct xhci_ring *xr; 1737 struct xhci_xfer *xx; 1738 struct usbd_xfer *xfer; 1739 usbd_status err; 1740 1741 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1742 1743 trb_0 = le64toh(trb->trb_0); 1744 trb_2 = le32toh(trb->trb_2); 1745 trb_3 = le32toh(trb->trb_3); 1746 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1747 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1748 dci = XHCI_TRB_3_EP_GET(trb_3); 1749 xs = &sc->sc_slots[slot]; 1750 xr = &xs->xs_ep[dci].xe_tr; 1751 1752 /* sanity check */ 1753 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1754 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1755 1756 int idx = 0; 1757 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1758 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1759 DPRINTFN(0, "invalid trb_0 0x%"PRIx64, trb_0, 0, 0, 0); 1760 return; 1761 } 1762 xx = xr->xr_cookies[idx]; 1763 1764 /* clear cookie of consumed TRB */ 1765 xr->xr_cookies[idx] = NULL; 1766 1767 /* 1768 * xx is NULL if pipe is opened but xfer is not started. 1769 * It happens when stopping idle pipe. 1770 */ 1771 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1772 DPRINTFN(1, "Ignore #%u: cookie %p cc %u dci %u", 1773 idx, xx, trbcode, dci); 1774 DPRINTFN(1, " orig TRB %"PRIx64" type %u", trb_0, 1775 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1776 0, 0); 1777 return; 1778 } 1779 } else { 1780 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1781 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1782 } 1783 /* XXX this may not happen */ 1784 if (xx == NULL) { 1785 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1786 return; 1787 } 1788 xfer = &xx->xx_xfer; 1789 /* XXX this may happen when detaching */ 1790 if (xfer == NULL) { 1791 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1792 xx, trb_0, 0, 0); 1793 return; 1794 } 1795 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1796 /* XXX I dunno why this happens */ 1797 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1798 1799 if (!xfer->ux_pipe->up_repeat && 1800 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1801 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1802 return; 1803 } 1804 1805 /* 4.11.5.2 Event Data TRB */ 1806 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1807 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1808 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1809 if ((trb_0 & 0x3) == 0x3) { 1810 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1811 } 1812 } 1813 1814 switch (trbcode) { 1815 case XHCI_TRB_ERROR_SHORT_PKT: 1816 case XHCI_TRB_ERROR_SUCCESS: 1817 /* 1818 * A ctrl transfer can generate two events if it has a Data 1819 * stage. A short data stage can be OK and should not 1820 * complete the transfer as the status stage needs to be 1821 * performed. 1822 * 1823 * Note: Data and Status stage events point at same xfer. 1824 * ux_actlen and ux_dmabuf will be passed to 1825 * usb_transfer_complete after the Status stage event. 1826 * 1827 * It can be distingished which stage generates the event: 1828 * + by checking least 3 bits of trb_0 if ED==1. 1829 * (see xhci_device_ctrl_start). 1830 * + by checking the type of original TRB if ED==0. 1831 * 1832 * In addition, intr, bulk, and isoc transfer currently 1833 * consists of single TD, so the "skip" is not needed. 1834 * ctrl xfer uses EVENT_DATA, and others do not. 1835 * Thus driver can switch the flow by checking ED bit. 1836 */ 1837 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1838 if (xfer->ux_actlen == 0) 1839 xfer->ux_actlen = xfer->ux_length - 1840 XHCI_TRB_2_REM_GET(trb_2); 1841 if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)) 1842 == XHCI_TRB_TYPE_DATA_STAGE) { 1843 return; 1844 } 1845 } else if ((trb_0 & 0x3) == 0x3) { 1846 return; 1847 } 1848 err = USBD_NORMAL_COMPLETION; 1849 break; 1850 case XHCI_TRB_ERROR_STOPPED: 1851 case XHCI_TRB_ERROR_LENGTH: 1852 case XHCI_TRB_ERROR_STOPPED_SHORT: 1853 /* 1854 * don't complete the transfer being aborted 1855 * as abort_xfer does instead. 1856 */ 1857 if (xfer->ux_hcflags & UXFER_ABORTING) { 1858 DPRINTFN(14, "ignore aborting xfer %p", xfer, 0, 0, 0); 1859 return; 1860 } 1861 err = USBD_CANCELLED; 1862 break; 1863 case XHCI_TRB_ERROR_STALL: 1864 case XHCI_TRB_ERROR_BABBLE: 1865 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1866 xr->is_halted = true; 1867 err = USBD_STALLED; 1868 /* 1869 * Stalled endpoints can be recoverd by issuing 1870 * command TRB TYPE_RESET_EP on xHCI instead of 1871 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1872 * on the endpoint. However, this function may be 1873 * called from softint context (e.g. from umass), 1874 * in that case driver gets KASSERT in cv_timedwait 1875 * in xhci_do_command. 1876 * To avoid this, this runs reset_endpoint and 1877 * usb_transfer_complete in usb task thread 1878 * asynchronously (and then umass issues clear 1879 * UF_ENDPOINT_HALT). 1880 */ 1881 xfer->ux_status = err; 1882 callout_stop(&xfer->ux_callout); 1883 xhci_clear_endpoint_stall_async(xfer); 1884 return; 1885 default: 1886 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1887 err = USBD_IOERROR; 1888 break; 1889 } 1890 xfer->ux_status = err; 1891 1892 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1893 if ((trb_0 & 0x3) == 0x0) { 1894 callout_stop(&xfer->ux_callout); 1895 usb_transfer_complete(xfer); 1896 } 1897 } else { 1898 callout_stop(&xfer->ux_callout); 1899 usb_transfer_complete(xfer); 1900 } 1901 } 1902 1903 /* Process Command complete events */ 1904 static void 1905 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 1906 { 1907 uint64_t trb_0; 1908 uint32_t trb_2, trb_3; 1909 1910 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1911 1912 KASSERT(mutex_owned(&sc->sc_lock)); 1913 1914 trb_0 = le64toh(trb->trb_0); 1915 trb_2 = le32toh(trb->trb_2); 1916 trb_3 = le32toh(trb->trb_3); 1917 1918 if (trb_0 == sc->sc_command_addr) { 1919 sc->sc_resultpending = false; 1920 1921 sc->sc_result_trb.trb_0 = trb_0; 1922 sc->sc_result_trb.trb_2 = trb_2; 1923 sc->sc_result_trb.trb_3 = trb_3; 1924 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1925 XHCI_TRB_ERROR_SUCCESS) { 1926 DPRINTFN(1, "command completion " 1927 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1928 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1929 } 1930 cv_signal(&sc->sc_command_cv); 1931 } else { 1932 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 1933 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1934 trb_2, trb_3); 1935 } 1936 } 1937 1938 /* 1939 * Process events. 1940 * called from xhci_softintr 1941 */ 1942 static void 1943 xhci_handle_event(struct xhci_softc * const sc, 1944 const struct xhci_trb * const trb) 1945 { 1946 uint64_t trb_0; 1947 uint32_t trb_2, trb_3; 1948 1949 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1950 1951 trb_0 = le64toh(trb->trb_0); 1952 trb_2 = le32toh(trb->trb_2); 1953 trb_3 = le32toh(trb->trb_3); 1954 1955 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1956 trb, trb_0, trb_2, trb_3); 1957 1958 /* 1959 * 4.11.3.1, 6.4.2.1 1960 * TRB Pointer is invalid for these completion codes. 1961 */ 1962 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 1963 case XHCI_TRB_ERROR_RING_UNDERRUN: 1964 case XHCI_TRB_ERROR_RING_OVERRUN: 1965 case XHCI_TRB_ERROR_VF_RING_FULL: 1966 return; 1967 default: 1968 if (trb_0 == 0) { 1969 return; 1970 } 1971 break; 1972 } 1973 1974 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 1975 case XHCI_TRB_EVENT_TRANSFER: 1976 xhci_event_transfer(sc, trb); 1977 break; 1978 case XHCI_TRB_EVENT_CMD_COMPLETE: 1979 xhci_event_cmd(sc, trb); 1980 break; 1981 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1982 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1983 break; 1984 default: 1985 break; 1986 } 1987 } 1988 1989 static void 1990 xhci_softintr(void *v) 1991 { 1992 struct usbd_bus * const bus = v; 1993 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1994 struct xhci_ring * const er = &sc->sc_er; 1995 struct xhci_trb *trb; 1996 int i, j, k; 1997 1998 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1999 2000 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2001 2002 i = er->xr_ep; 2003 j = er->xr_cs; 2004 2005 DPRINTFN(16, "er: xr_ep %d xr_cs %d", i, j, 0, 0); 2006 2007 while (1) { 2008 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2009 BUS_DMASYNC_POSTREAD); 2010 trb = &er->xr_trb[i]; 2011 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2012 2013 if (j != k) 2014 break; 2015 2016 xhci_handle_event(sc, trb); 2017 2018 i++; 2019 if (i == er->xr_ntrb) { 2020 i = 0; 2021 j ^= 1; 2022 } 2023 } 2024 2025 er->xr_ep = i; 2026 er->xr_cs = j; 2027 2028 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2029 XHCI_ERDP_LO_BUSY); 2030 2031 DPRINTFN(16, "ends", 0, 0, 0, 0); 2032 2033 return; 2034 } 2035 2036 static void 2037 xhci_poll(struct usbd_bus *bus) 2038 { 2039 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2040 2041 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2042 2043 mutex_spin_enter(&sc->sc_intr_lock); 2044 xhci_intr1(sc); 2045 mutex_spin_exit(&sc->sc_intr_lock); 2046 2047 return; 2048 } 2049 2050 static struct usbd_xfer * 2051 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2052 { 2053 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2054 struct usbd_xfer *xfer; 2055 2056 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2057 2058 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 2059 if (xfer != NULL) { 2060 memset(xfer, 0, sizeof(struct xhci_xfer)); 2061 #ifdef DIAGNOSTIC 2062 xfer->ux_state = XFER_BUSY; 2063 #endif 2064 } 2065 2066 return xfer; 2067 } 2068 2069 static void 2070 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2071 { 2072 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2073 2074 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2075 2076 #ifdef DIAGNOSTIC 2077 if (xfer->ux_state != XFER_BUSY) { 2078 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 2079 xfer, xfer->ux_state, 0, 0); 2080 } 2081 xfer->ux_state = XFER_FREE; 2082 #endif 2083 pool_cache_put(sc->sc_xferpool, xfer); 2084 } 2085 2086 static void 2087 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2088 { 2089 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2090 2091 *lock = &sc->sc_lock; 2092 } 2093 2094 extern uint32_t usb_cookie_no; 2095 2096 /* 2097 * xHCI 4.3 2098 * Called when uhub_explore finds a new device (via usbd_new_device). 2099 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2100 * This function does: 2101 * Allocate and construct dev structure of default endpoint (ep0). 2102 * Allocate and open pipe of ep0. 2103 * Enable slot and initialize slot context. 2104 * Set Address. 2105 * Read initial device descriptor. 2106 * Determine initial MaxPacketSize (mps) by speed. 2107 * Read full device descriptor. 2108 * Register this device. 2109 * Finally state of device transitions ADDRESSED. 2110 */ 2111 static usbd_status 2112 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2113 int speed, int port, struct usbd_port *up) 2114 { 2115 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2116 struct usbd_device *dev; 2117 usbd_status err; 2118 usb_device_descriptor_t *dd; 2119 struct xhci_slot *xs; 2120 uint32_t *cp; 2121 2122 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2123 DPRINTFN(4, "port %u depth %u speed %u up %p", port, depth, speed, up); 2124 2125 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2126 if (dev == NULL) 2127 return USBD_NOMEM; 2128 2129 dev->ud_bus = bus; 2130 dev->ud_quirks = &usbd_no_quirk; 2131 dev->ud_addr = 0; 2132 dev->ud_ddesc.bMaxPacketSize = 0; 2133 dev->ud_depth = depth; 2134 dev->ud_powersrc = up; 2135 dev->ud_myhub = up->up_parent; 2136 dev->ud_speed = speed; 2137 dev->ud_langid = USBD_NOLANG; 2138 dev->ud_cookie.cookie = ++usb_cookie_no; 2139 2140 /* Set up default endpoint handle. */ 2141 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2142 /* doesn't matter, just don't let it uninitialized */ 2143 dev->ud_ep0.ue_toggle = 0; 2144 2145 /* Set up default endpoint descriptor. */ 2146 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2147 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2148 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2149 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2150 dev->ud_ep0desc.bInterval = 0; 2151 2152 /* 4.3, 4.8.2.1 */ 2153 switch (speed) { 2154 case USB_SPEED_SUPER: 2155 case USB_SPEED_SUPER_PLUS: 2156 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2157 break; 2158 case USB_SPEED_FULL: 2159 /* XXX using 64 as initial mps of ep0 in FS */ 2160 case USB_SPEED_HIGH: 2161 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2162 break; 2163 case USB_SPEED_LOW: 2164 default: 2165 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2166 break; 2167 } 2168 2169 up->up_dev = dev; 2170 2171 /* Establish the default pipe. */ 2172 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2173 &dev->ud_pipe0); 2174 if (err) { 2175 goto bad; 2176 } 2177 2178 dd = &dev->ud_ddesc; 2179 2180 if ((depth == 0) && (port == 0)) { 2181 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2182 bus->ub_devices[dev->ud_addr] = dev; 2183 err = usbd_get_initial_ddesc(dev, dd); 2184 if (err) { 2185 DPRINTFN(1, "get_initial_ddesc %u", err, 0, 0, 0); 2186 goto bad; 2187 } 2188 2189 err = usbd_reload_device_desc(dev); 2190 if (err) { 2191 DPRINTFN(1, "reload desc %u", err, 0, 0, 0); 2192 goto bad; 2193 } 2194 } else { 2195 uint8_t slot = 0; 2196 2197 /* 4.3.2 */ 2198 err = xhci_enable_slot(sc, &slot); 2199 if (err) { 2200 DPRINTFN(1, "enable slot %u", err, 0, 0, 0); 2201 goto bad; 2202 } 2203 2204 xs = &sc->sc_slots[slot]; 2205 dev->ud_hcpriv = xs; 2206 2207 /* 4.3.3 initialize slot structure */ 2208 err = xhci_init_slot(dev, slot); 2209 if (err) { 2210 DPRINTFN(1, "init slot %u", err, 0, 0, 0); 2211 dev->ud_hcpriv = NULL; 2212 /* 2213 * We have to disable_slot here because 2214 * xs->xs_idx == 0 when xhci_init_slot fails, 2215 * in that case usbd_remove_dev won't work. 2216 */ 2217 mutex_enter(&sc->sc_lock); 2218 xhci_disable_slot(sc, slot); 2219 mutex_exit(&sc->sc_lock); 2220 goto bad; 2221 } 2222 2223 /* 4.3.4 Address Assignment */ 2224 err = xhci_set_address(dev, slot, false); 2225 if (err) { 2226 DPRINTFN(1, "set address w/o bsr %u", err, 0, 0, 0); 2227 goto bad; 2228 } 2229 2230 /* Allow device time to set new address */ 2231 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2232 2233 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2234 //hexdump("slot context", cp, sc->sc_ctxsz); 2235 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3])); 2236 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2237 /* XXX ensure we know when the hardware does something 2238 we can't yet cope with */ 2239 KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr); 2240 dev->ud_addr = addr; 2241 /* XXX dev->ud_addr not necessarily unique on bus */ 2242 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2243 bus->ub_devices[dev->ud_addr] = dev; 2244 2245 err = usbd_get_initial_ddesc(dev, dd); 2246 if (err) { 2247 DPRINTFN(1, "get_initial_ddesc %u", err, 0, 0, 0); 2248 goto bad; 2249 } 2250 2251 /* 4.8.2.1 */ 2252 if (USB_IS_SS(speed)) { 2253 if (dd->bMaxPacketSize != 9) { 2254 printf("%s: invalid mps 2^%u for SS ep0," 2255 " using 512\n", 2256 device_xname(sc->sc_dev), 2257 dd->bMaxPacketSize); 2258 dd->bMaxPacketSize = 9; 2259 } 2260 USETW(dev->ud_ep0desc.wMaxPacketSize, 2261 (1 << dd->bMaxPacketSize)); 2262 } else 2263 USETW(dev->ud_ep0desc.wMaxPacketSize, 2264 dd->bMaxPacketSize); 2265 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2266 err = xhci_update_ep0_mps(sc, xs, 2267 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2268 if (err) { 2269 DPRINTFN(1, "update mps of ep0 %u", err, 0, 0, 0); 2270 goto bad; 2271 } 2272 2273 err = usbd_reload_device_desc(dev); 2274 if (err) { 2275 DPRINTFN(1, "reload desc %u", err, 0, 0, 0); 2276 goto bad; 2277 } 2278 } 2279 2280 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2281 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2282 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2283 dd->bDeviceClass, dd->bDeviceSubClass, 2284 dd->bDeviceProtocol, 0); 2285 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2286 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2287 dev->ud_speed); 2288 2289 usbd_get_device_strings(dev); 2290 2291 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2292 2293 if ((depth == 0) && (port == 0)) { 2294 usbd_attach_roothub(parent, dev); 2295 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2296 return USBD_NORMAL_COMPLETION; 2297 } 2298 2299 2300 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2301 bad: 2302 if (err != USBD_NORMAL_COMPLETION) { 2303 usbd_remove_device(dev, up); 2304 } 2305 2306 return err; 2307 } 2308 2309 static usbd_status 2310 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2311 size_t ntrb, size_t align) 2312 { 2313 usbd_status err; 2314 size_t size = ntrb * XHCI_TRB_SIZE; 2315 2316 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2317 2318 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2319 if (err) 2320 return err; 2321 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2322 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2323 xr->xr_trb = xhci_ring_trbv(xr, 0); 2324 xr->xr_ntrb = ntrb; 2325 xr->is_halted = false; 2326 xhci_host_dequeue(xr); 2327 2328 return USBD_NORMAL_COMPLETION; 2329 } 2330 2331 static void 2332 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2333 { 2334 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2335 mutex_destroy(&xr->xr_lock); 2336 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2337 } 2338 2339 static void 2340 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2341 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2342 { 2343 size_t i; 2344 u_int ri; 2345 u_int cs; 2346 uint64_t parameter; 2347 uint32_t status; 2348 uint32_t control; 2349 2350 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2351 2352 KASSERTMSG(ntrbs <= XHCI_XFER_NTRB, "ntrbs %zu", ntrbs); 2353 for (i = 0; i < ntrbs; i++) { 2354 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2355 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2356 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2357 KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2358 XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3); 2359 } 2360 2361 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2362 2363 ri = xr->xr_ep; 2364 cs = xr->xr_cs; 2365 2366 /* 2367 * Although the xhci hardware can do scatter/gather dma from 2368 * arbitrary sized buffers, there is a non-obvious restriction 2369 * that a LINK trb is only allowed at the end of a burst of 2370 * transfers - which might be 16kB. 2371 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2372 * The simple solution is not to allow a LINK trb in the middle 2373 * of anything - as here. 2374 * XXX: (dsl) There are xhci controllers out there (eg some made by 2375 * ASMedia) that seem to lock up if they process a LINK trb but 2376 * cannot process the linked-to trb yet. 2377 * The code should write the 'cycle' bit on the link trb AFTER 2378 * adding the other trb. 2379 */ 2380 u_int firstep = xr->xr_ep; 2381 u_int firstcs = xr->xr_cs; 2382 2383 for (i = 0; i < ntrbs; ) { 2384 u_int oldri = ri; 2385 u_int oldcs = cs; 2386 2387 if (ri >= (xr->xr_ntrb - 1)) { 2388 /* Put Link TD at the end of ring */ 2389 parameter = xhci_ring_trbp(xr, 0); 2390 status = 0; 2391 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2392 XHCI_TRB_3_TC_BIT; 2393 xr->xr_cookies[ri] = NULL; 2394 xr->xr_ep = 0; 2395 xr->xr_cs ^= 1; 2396 ri = xr->xr_ep; 2397 cs = xr->xr_cs; 2398 } else { 2399 parameter = trbs[i].trb_0; 2400 status = trbs[i].trb_2; 2401 control = trbs[i].trb_3; 2402 2403 xr->xr_cookies[ri] = cookie; 2404 ri++; 2405 i++; 2406 } 2407 /* 2408 * If this is a first TRB, mark it invalid to prevent 2409 * xHC from running it immediately. 2410 */ 2411 if (oldri == firstep) { 2412 if (oldcs) { 2413 control &= ~XHCI_TRB_3_CYCLE_BIT; 2414 } else { 2415 control |= XHCI_TRB_3_CYCLE_BIT; 2416 } 2417 } else { 2418 if (oldcs) { 2419 control |= XHCI_TRB_3_CYCLE_BIT; 2420 } else { 2421 control &= ~XHCI_TRB_3_CYCLE_BIT; 2422 } 2423 } 2424 xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control); 2425 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri, 2426 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2427 } 2428 2429 /* Now invert cycle bit of first TRB */ 2430 if (firstcs) { 2431 xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 2432 } else { 2433 xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 2434 } 2435 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep, 2436 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2437 2438 xr->xr_ep = ri; 2439 xr->xr_cs = cs; 2440 2441 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2442 } 2443 2444 /* 2445 * Stop execution commands, purge all commands on command ring, and 2446 * rewind dequeue pointer. 2447 */ 2448 static void 2449 xhci_abort_command(struct xhci_softc *sc) 2450 { 2451 struct xhci_ring * const cr = &sc->sc_cr; 2452 uint64_t crcr; 2453 int i; 2454 2455 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2456 DPRINTFN(14, "command %#"PRIx64" timeout, aborting", 2457 sc->sc_command_addr, 0, 0, 0); 2458 2459 mutex_enter(&cr->xr_lock); 2460 2461 /* 4.6.1.2 Aborting a Command */ 2462 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2463 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2464 2465 for (i = 0; i < 500; i++) { 2466 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2467 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2468 break; 2469 usb_delay_ms(&sc->sc_bus, 1); 2470 } 2471 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2472 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2473 /* reset HC here? */ 2474 } 2475 2476 /* reset command ring dequeue pointer */ 2477 cr->xr_ep = 0; 2478 cr->xr_cs = 1; 2479 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2480 2481 mutex_exit(&cr->xr_lock); 2482 } 2483 2484 /* 2485 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2486 * Command completion is notified by cv_signal from xhci_event_cmd() 2487 * (called from xhci_softint), or timed-out. 2488 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2489 * then do_command examines it. 2490 */ 2491 static usbd_status 2492 xhci_do_command_locked(struct xhci_softc * const sc, 2493 struct xhci_trb * const trb, int timeout) 2494 { 2495 struct xhci_ring * const cr = &sc->sc_cr; 2496 usbd_status err; 2497 2498 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2499 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2500 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2501 2502 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2503 KASSERT(mutex_owned(&sc->sc_lock)); 2504 2505 while (sc->sc_command_addr != 0) 2506 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 2507 2508 /* 2509 * If enqueue pointer points at last of ring, it's Link TRB, 2510 * command TRB will be stored in 0th TRB. 2511 */ 2512 if (cr->xr_ep == cr->xr_ntrb - 1) 2513 sc->sc_command_addr = xhci_ring_trbp(cr, 0); 2514 else 2515 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2516 2517 sc->sc_resultpending = true; 2518 2519 mutex_enter(&cr->xr_lock); 2520 xhci_ring_put(sc, cr, NULL, trb, 1); 2521 mutex_exit(&cr->xr_lock); 2522 2523 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2524 2525 while (sc->sc_resultpending) { 2526 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2527 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2528 xhci_abort_command(sc); 2529 err = USBD_TIMEOUT; 2530 goto timedout; 2531 } 2532 } 2533 2534 trb->trb_0 = sc->sc_result_trb.trb_0; 2535 trb->trb_2 = sc->sc_result_trb.trb_2; 2536 trb->trb_3 = sc->sc_result_trb.trb_3; 2537 2538 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2539 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2540 2541 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2542 case XHCI_TRB_ERROR_SUCCESS: 2543 err = USBD_NORMAL_COMPLETION; 2544 break; 2545 default: 2546 case 192 ... 223: 2547 err = USBD_IOERROR; 2548 break; 2549 case 224 ... 255: 2550 err = USBD_NORMAL_COMPLETION; 2551 break; 2552 } 2553 2554 timedout: 2555 sc->sc_resultpending = false; 2556 sc->sc_command_addr = 0; 2557 cv_broadcast(&sc->sc_cmdbusy_cv); 2558 2559 return err; 2560 } 2561 2562 static usbd_status 2563 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2564 int timeout) 2565 { 2566 2567 mutex_enter(&sc->sc_lock); 2568 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2569 mutex_exit(&sc->sc_lock); 2570 2571 return ret; 2572 } 2573 2574 static usbd_status 2575 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2576 { 2577 struct xhci_trb trb; 2578 usbd_status err; 2579 2580 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2581 2582 trb.trb_0 = 0; 2583 trb.trb_2 = 0; 2584 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2585 2586 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2587 if (err != USBD_NORMAL_COMPLETION) { 2588 return err; 2589 } 2590 2591 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2592 2593 return err; 2594 } 2595 2596 /* 2597 * xHCI 4.6.4 2598 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2599 * All endpoints in the slot should be stopped. 2600 * Should be called with sc_lock held. 2601 */ 2602 static usbd_status 2603 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2604 { 2605 struct xhci_trb trb; 2606 struct xhci_slot *xs; 2607 usbd_status err; 2608 2609 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2610 2611 if (sc->sc_dying) 2612 return USBD_IOERROR; 2613 2614 trb.trb_0 = 0; 2615 trb.trb_2 = 0; 2616 trb.trb_3 = htole32( 2617 XHCI_TRB_3_SLOT_SET(slot) | 2618 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2619 2620 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2621 2622 if (!err) { 2623 xs = &sc->sc_slots[slot]; 2624 if (xs->xs_idx != 0) { 2625 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2626 xhci_set_dcba(sc, 0, slot); 2627 memset(xs, 0, sizeof(*xs)); 2628 } 2629 } 2630 2631 return err; 2632 } 2633 2634 /* 2635 * Set address of device and transition slot state from ENABLED to ADDRESSED 2636 * if Block Setaddress Request (BSR) is false. 2637 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2638 * see xHCI 1.1 4.5.3, 3.3.4 2639 * Should be called without sc_lock held. 2640 */ 2641 static usbd_status 2642 xhci_address_device(struct xhci_softc * const sc, 2643 uint64_t icp, uint8_t slot_id, bool bsr) 2644 { 2645 struct xhci_trb trb; 2646 usbd_status err; 2647 2648 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2649 2650 trb.trb_0 = icp; 2651 trb.trb_2 = 0; 2652 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2653 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2654 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2655 2656 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2657 2658 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2659 err = USBD_NO_ADDR; 2660 2661 return err; 2662 } 2663 2664 static usbd_status 2665 xhci_update_ep0_mps(struct xhci_softc * const sc, 2666 struct xhci_slot * const xs, u_int mps) 2667 { 2668 struct xhci_trb trb; 2669 usbd_status err; 2670 uint32_t * cp; 2671 2672 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2673 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2674 2675 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2676 cp[0] = htole32(0); 2677 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2678 2679 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2680 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2681 2682 /* sync input contexts before they are read from memory */ 2683 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2684 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2685 sc->sc_ctxsz * 4); 2686 2687 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2688 trb.trb_2 = 0; 2689 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2690 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2691 2692 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2693 return err; 2694 } 2695 2696 static void 2697 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2698 { 2699 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2700 2701 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2702 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2703 &dcbaa[si], dcba, si, 0); 2704 2705 dcbaa[si] = htole64(dcba); 2706 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2707 BUS_DMASYNC_PREWRITE); 2708 } 2709 2710 /* 2711 * Allocate device and input context DMA buffer, and 2712 * TRB DMA buffer for each endpoint. 2713 */ 2714 static usbd_status 2715 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2716 { 2717 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2718 struct xhci_slot *xs; 2719 usbd_status err; 2720 u_int dci; 2721 2722 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2723 DPRINTFN(4, "slot %u", slot, 0, 0, 0); 2724 2725 xs = &sc->sc_slots[slot]; 2726 2727 /* allocate contexts */ 2728 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2729 &xs->xs_dc_dma); 2730 if (err) 2731 return err; 2732 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2733 2734 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2735 &xs->xs_ic_dma); 2736 if (err) 2737 goto bad1; 2738 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2739 2740 for (dci = 0; dci < 32; dci++) { 2741 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2742 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2743 if (dci == XHCI_DCI_SLOT) 2744 continue; 2745 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2746 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2747 if (err) { 2748 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2749 goto bad2; 2750 } 2751 } 2752 2753 bad2: 2754 if (err == USBD_NORMAL_COMPLETION) { 2755 xs->xs_idx = slot; 2756 } else { 2757 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2758 } 2759 2760 return err; 2761 2762 bad1: 2763 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2764 xs->xs_idx = 0; 2765 return err; 2766 } 2767 2768 static void 2769 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2770 int end_dci) 2771 { 2772 u_int dci; 2773 2774 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2775 DPRINTFN(4, "slot %u start %u end %u", xs->xs_idx, start_dci, end_dci, 2776 0); 2777 2778 for (dci = start_dci; dci < end_dci; dci++) { 2779 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2780 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2781 } 2782 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2783 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2784 xs->xs_idx = 0; 2785 } 2786 2787 /* 2788 * Setup slot context, set Device Context Base Address, and issue 2789 * Set Address Device command. 2790 */ 2791 static usbd_status 2792 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 2793 { 2794 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2795 struct xhci_slot *xs; 2796 usbd_status err; 2797 2798 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2799 DPRINTFN(4, "slot %u bsr %u", slot, bsr, 0, 0); 2800 2801 xs = &sc->sc_slots[slot]; 2802 2803 xhci_setup_ctx(dev->ud_pipe0); 2804 2805 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2806 sc->sc_ctxsz * 3); 2807 2808 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2809 2810 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 2811 2812 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2813 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2814 sc->sc_ctxsz * 2); 2815 2816 return err; 2817 } 2818 2819 /* 2820 * 4.8.2, 6.2.3.2 2821 * construct slot/endpoint context parameters and do syncmem 2822 */ 2823 static void 2824 xhci_setup_ctx(struct usbd_pipe *pipe) 2825 { 2826 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2827 struct usbd_device *dev = pipe->up_dev; 2828 struct xhci_slot * const xs = dev->ud_hcpriv; 2829 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2830 const u_int dci = xhci_ep_get_dci(ed); 2831 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2832 uint32_t *cp; 2833 uint16_t mps = UGETW(ed->wMaxPacketSize); 2834 uint8_t speed = dev->ud_speed; 2835 uint8_t ival = ed->bInterval; 2836 2837 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2838 DPRINTFN(4, "pipe %p: slot %u dci %u speed %u", pipe, xs->xs_idx, dci, 2839 speed); 2840 2841 /* set up initial input control context */ 2842 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2843 cp[0] = htole32(0); 2844 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 2845 if (dci == XHCI_DCI_EP_CONTROL) 2846 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2847 cp[7] = htole32(0); 2848 2849 /* set up input slot context */ 2850 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2851 cp[0] = 2852 XHCI_SCTX_0_CTX_NUM_SET(dci) | 2853 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 2854 cp[1] = 0; 2855 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2856 cp[3] = 0; 2857 xhci_setup_route(pipe, cp); 2858 xhci_setup_tthub(pipe, cp); 2859 2860 cp[0] = htole32(cp[0]); 2861 cp[1] = htole32(cp[1]); 2862 cp[2] = htole32(cp[2]); 2863 cp[3] = htole32(cp[3]); 2864 2865 /* set up input endpoint context */ 2866 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 2867 cp[0] = 2868 XHCI_EPCTX_0_EPSTATE_SET(0) | 2869 XHCI_EPCTX_0_MULT_SET(0) | 2870 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2871 XHCI_EPCTX_0_LSA_SET(0) | 2872 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 2873 cp[1] = 2874 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 2875 XHCI_EPCTX_1_HID_SET(0) | 2876 XHCI_EPCTX_1_MAXB_SET(0); 2877 2878 if (xfertype != UE_ISOCHRONOUS) 2879 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 2880 2881 if (xfertype == UE_CONTROL) 2882 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 2883 else if (USB_IS_SS(speed)) 2884 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 2885 else 2886 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 2887 2888 xhci_setup_maxburst(pipe, cp); 2889 2890 switch (xfertype) { 2891 case UE_CONTROL: 2892 break; 2893 case UE_BULK: 2894 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 2895 break; 2896 case UE_INTERRUPT: 2897 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 2898 ival = pipe->up_interval; 2899 2900 ival = xhci_bival2ival(ival, speed); 2901 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 2902 break; 2903 case UE_ISOCHRONOUS: 2904 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 2905 ival = pipe->up_interval; 2906 2907 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 2908 if (speed == USB_SPEED_FULL) 2909 ival += 3; /* 1ms -> 125us */ 2910 ival--; 2911 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 2912 break; 2913 default: 2914 break; 2915 } 2916 DPRINTFN(4, "setting ival %u MaxBurst %#x", 2917 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 2918 2919 /* rewind TR dequeue pointer in xHC */ 2920 /* can't use xhci_ep_get_dci() yet? */ 2921 *(uint64_t *)(&cp[2]) = htole64( 2922 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 2923 XHCI_EPCTX_2_DCS_SET(1)); 2924 2925 cp[0] = htole32(cp[0]); 2926 cp[1] = htole32(cp[1]); 2927 cp[4] = htole32(cp[4]); 2928 2929 /* rewind TR dequeue pointer in driver */ 2930 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 2931 mutex_enter(&xr->xr_lock); 2932 xhci_host_dequeue(xr); 2933 mutex_exit(&xr->xr_lock); 2934 2935 /* sync input contexts before they are read from memory */ 2936 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2937 } 2938 2939 /* 2940 * Setup route string and roothub port of given device for slot context 2941 */ 2942 static void 2943 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 2944 { 2945 struct usbd_device *dev = pipe->up_dev; 2946 struct usbd_port *up = dev->ud_powersrc; 2947 struct usbd_device *hub; 2948 struct usbd_device *adev; 2949 uint8_t rhport = 0; 2950 uint32_t route = 0; 2951 2952 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2953 2954 /* Locate root hub port and Determine route string */ 2955 /* 4.3.3 route string does not include roothub port */ 2956 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2957 uint32_t dep; 2958 2959 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2960 hub, hub->ud_depth, hub->ud_powersrc, 2961 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2962 2963 if (hub->ud_powersrc == NULL) 2964 break; 2965 dep = hub->ud_depth; 2966 if (dep == 0) 2967 break; 2968 rhport = hub->ud_powersrc->up_portno; 2969 if (dep > USB_HUB_MAX_DEPTH) 2970 continue; 2971 2972 route |= 2973 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2974 << ((dep - 1) * 4); 2975 } 2976 route = route >> 4; 2977 DPRINTFN(4, "rhport %u Route %05x hub %p", rhport, route, hub, 0); 2978 2979 /* Locate port on upstream high speed hub */ 2980 for (adev = dev, hub = up->up_parent; 2981 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2982 adev = hub, hub = hub->ud_myhub) 2983 ; 2984 if (hub) { 2985 int p; 2986 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2987 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2988 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2989 goto found; 2990 } 2991 } 2992 panic("xhci_setup_route: cannot find HS port"); 2993 found: 2994 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2995 } else { 2996 dev->ud_myhsport = NULL; 2997 } 2998 2999 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 3000 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(rhport); 3001 } 3002 3003 /* 3004 * Setup whether device is hub, whether device uses MTT, and 3005 * TT informations if it uses MTT. 3006 */ 3007 static void 3008 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 3009 { 3010 struct usbd_device *dev = pipe->up_dev; 3011 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 3012 uint32_t speed = dev->ud_speed; 3013 uint8_t tthubslot, ttportnum; 3014 bool ishub; 3015 bool usemtt; 3016 3017 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3018 3019 /* 3020 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 3021 * tthubslot: 3022 * This is the slot ID of parent HS hub 3023 * if LS/FS device is connected && connected through HS hub. 3024 * This is 0 if device is not LS/FS device || 3025 * parent hub is not HS hub || 3026 * attached to root hub. 3027 * ttportnum: 3028 * This is the downstream facing port of parent HS hub 3029 * if LS/FS device is connected. 3030 * This is 0 if device is not LS/FS device || 3031 * parent hub is not HS hub || 3032 * attached to root hub. 3033 */ 3034 if (dev->ud_myhsport != NULL && 3035 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3036 (dev->ud_myhub != NULL && 3037 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3038 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 3039 ttportnum = dev->ud_myhsport->up_portno; 3040 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 3041 } else { 3042 ttportnum = 0; 3043 tthubslot = 0; 3044 } 3045 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 3046 dev->ud_myhsport, ttportnum, tthubslot, 0); 3047 3048 /* ishub is valid after reading UDESC_DEVICE */ 3049 ishub = (dd->bDeviceClass == UDCLASS_HUB); 3050 3051 /* dev->ud_hub is valid after reading UDESC_HUB */ 3052 if (ishub && dev->ud_hub) { 3053 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 3054 uint8_t ttt = 3055 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 3056 3057 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 3058 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 3059 DPRINTFN(4, "nports=%d ttt=%d", hd->bNbrPorts, ttt, 0, 0); 3060 } 3061 3062 #define IS_TTHUB(dd) \ 3063 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 3064 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 3065 3066 /* 3067 * MTT flag is set if 3068 * 1. this is HS hub && MTT is enabled 3069 * or 3070 * 2. this is not hub && this is LS or FS device && 3071 * MTT of parent HS hub (and its parent, too) is enabled 3072 */ 3073 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 3074 usemtt = true; 3075 else if (!ishub && 3076 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 3077 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3078 (dev->ud_myhub != NULL && 3079 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3080 dev->ud_myhsport != NULL && 3081 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 3082 usemtt = true; 3083 else 3084 usemtt = false; 3085 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 3086 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 3087 3088 #undef IS_TTHUB 3089 3090 cp[0] |= 3091 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 3092 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 3093 cp[2] |= 3094 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 3095 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 3096 } 3097 3098 /* set up params for periodic endpoint */ 3099 static void 3100 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 3101 { 3102 struct usbd_device *dev = pipe->up_dev; 3103 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3104 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3105 usbd_desc_iter_t iter; 3106 const usb_cdc_descriptor_t *cdcd; 3107 uint32_t maxb = 0; 3108 uint16_t mps = UGETW(ed->wMaxPacketSize); 3109 uint8_t speed = dev->ud_speed; 3110 uint8_t ep; 3111 3112 /* config desc is NULL when opening ep0 */ 3113 if (dev == NULL || dev->ud_cdesc == NULL) 3114 goto no_cdcd; 3115 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 3116 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 3117 if (cdcd == NULL) 3118 goto no_cdcd; 3119 usb_desc_iter_init(dev, &iter); 3120 iter.cur = (const void *)cdcd; 3121 3122 /* find endpoint_ss_comp desc for ep of this pipe */ 3123 for (ep = 0;;) { 3124 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 3125 if (cdcd == NULL) 3126 break; 3127 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 3128 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 3129 bEndpointAddress; 3130 if (UE_GET_ADDR(ep) == 3131 UE_GET_ADDR(ed->bEndpointAddress)) { 3132 cdcd = (const usb_cdc_descriptor_t *) 3133 usb_desc_iter_next(&iter); 3134 break; 3135 } 3136 ep = 0; 3137 } 3138 } 3139 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 3140 const usb_endpoint_ss_comp_descriptor_t * esscd = 3141 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3142 maxb = esscd->bMaxBurst; 3143 } 3144 3145 no_cdcd: 3146 /* 6.2.3.4, 4.8.2.4 */ 3147 if (USB_IS_SS(speed)) { 3148 /* USB 3.1 9.6.6 */ 3149 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3150 /* USB 3.1 9.6.7 */ 3151 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3152 #ifdef notyet 3153 if (xfertype == UE_ISOCHRONOUS) { 3154 } 3155 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3156 /* use ESIT */ 3157 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3158 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3159 3160 /* XXX if LEC = 1, set ESIT instead */ 3161 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3162 } else { 3163 /* use ival */ 3164 } 3165 #endif 3166 } else { 3167 /* USB 2.0 9.6.6 */ 3168 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3169 3170 /* 6.2.3.4 */ 3171 if (speed == USB_SPEED_HIGH && 3172 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3173 maxb = UE_GET_TRANS(mps); 3174 } else { 3175 /* LS/FS or HS CTRL or HS BULK */ 3176 maxb = 0; 3177 } 3178 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3179 } 3180 } 3181 3182 /* 3183 * Convert endpoint bInterval value to endpoint context interval value 3184 * for Interrupt pipe. 3185 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3186 */ 3187 static uint32_t 3188 xhci_bival2ival(uint32_t ival, uint32_t speed) 3189 { 3190 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3191 int i; 3192 3193 /* 3194 * round ival down to "the nearest base 2 multiple of 3195 * bInterval * 8". 3196 * bInterval is at most 255 as its type is uByte. 3197 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3198 */ 3199 for (i = 10; i > 0; i--) { 3200 if ((ival * 8) >= (1 << i)) 3201 break; 3202 } 3203 ival = i; 3204 } else { 3205 /* Interval = bInterval-1 for SS/HS */ 3206 ival--; 3207 } 3208 3209 return ival; 3210 } 3211 3212 /* ----- */ 3213 3214 static void 3215 xhci_noop(struct usbd_pipe *pipe) 3216 { 3217 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3218 } 3219 3220 /* 3221 * Process root hub request. 3222 */ 3223 static int 3224 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3225 void *buf, int buflen) 3226 { 3227 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3228 usb_port_status_t ps; 3229 int l, totlen = 0; 3230 uint16_t len, value, index; 3231 int port, i; 3232 uint32_t v; 3233 3234 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3235 3236 if (sc->sc_dying) 3237 return -1; 3238 3239 len = UGETW(req->wLength); 3240 value = UGETW(req->wValue); 3241 index = UGETW(req->wIndex); 3242 3243 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 3244 req->bmRequestType | (req->bRequest << 8), value, index, len); 3245 3246 #define C(x,y) ((x) | ((y) << 8)) 3247 switch (C(req->bRequest, req->bmRequestType)) { 3248 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3249 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 3250 if (len == 0) 3251 break; 3252 switch (value) { 3253 case C(0, UDESC_DEVICE): { 3254 usb_device_descriptor_t devd; 3255 totlen = min(buflen, sizeof(devd)); 3256 memcpy(&devd, buf, totlen); 3257 USETW(devd.idVendor, sc->sc_id_vendor); 3258 memcpy(buf, &devd, totlen); 3259 break; 3260 } 3261 #define sd ((usb_string_descriptor_t *)buf) 3262 case C(1, UDESC_STRING): 3263 /* Vendor */ 3264 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3265 break; 3266 case C(2, UDESC_STRING): 3267 /* Product */ 3268 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3269 break; 3270 #undef sd 3271 default: 3272 /* default from usbroothub */ 3273 return buflen; 3274 } 3275 break; 3276 3277 /* Hub requests */ 3278 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3279 break; 3280 /* Clear Port Feature request */ 3281 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3282 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 3283 index, value, 0, 0); 3284 if (index < 1 || index > sc->sc_maxports) { 3285 return -1; 3286 } 3287 port = XHCI_PORTSC(index); 3288 v = xhci_op_read_4(sc, port); 3289 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3290 v &= ~XHCI_PS_CLEAR; 3291 switch (value) { 3292 case UHF_PORT_ENABLE: 3293 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3294 break; 3295 case UHF_PORT_SUSPEND: 3296 return -1; 3297 case UHF_PORT_POWER: 3298 break; 3299 case UHF_PORT_TEST: 3300 case UHF_PORT_INDICATOR: 3301 return -1; 3302 case UHF_C_PORT_CONNECTION: 3303 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3304 break; 3305 case UHF_C_PORT_ENABLE: 3306 case UHF_C_PORT_SUSPEND: 3307 case UHF_C_PORT_OVER_CURRENT: 3308 return -1; 3309 case UHF_C_BH_PORT_RESET: 3310 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3311 break; 3312 case UHF_C_PORT_RESET: 3313 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3314 break; 3315 case UHF_C_PORT_LINK_STATE: 3316 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3317 break; 3318 case UHF_C_PORT_CONFIG_ERROR: 3319 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3320 break; 3321 default: 3322 return -1; 3323 } 3324 break; 3325 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3326 if (len == 0) 3327 break; 3328 if ((value & 0xff) != 0) { 3329 return -1; 3330 } 3331 usb_hub_descriptor_t hubd; 3332 3333 totlen = min(buflen, sizeof(hubd)); 3334 memcpy(&hubd, buf, totlen); 3335 hubd.bNbrPorts = sc->sc_maxports; 3336 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3337 hubd.bPwrOn2PwrGood = 200; 3338 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 3339 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 3340 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3341 totlen = min(totlen, hubd.bDescLength); 3342 memcpy(buf, &hubd, totlen); 3343 break; 3344 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3345 if (len != 4) { 3346 return -1; 3347 } 3348 memset(buf, 0, len); /* ? XXX */ 3349 totlen = len; 3350 break; 3351 /* Get Port Status request */ 3352 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3353 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 3354 if (index < 1 || index > sc->sc_maxports) { 3355 return -1; 3356 } 3357 if (len != 4) { 3358 return -1; 3359 } 3360 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 3361 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 3362 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3363 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3364 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3365 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3366 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3367 if (v & XHCI_PS_PR) i |= UPS_RESET; 3368 if (v & XHCI_PS_PP) { 3369 if (i & UPS_OTHER_SPEED) 3370 i |= UPS_PORT_POWER_SS; 3371 else 3372 i |= UPS_PORT_POWER; 3373 } 3374 if (i & UPS_OTHER_SPEED) 3375 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3376 if (sc->sc_vendor_port_status) 3377 i = sc->sc_vendor_port_status(sc, v, i); 3378 USETW(ps.wPortStatus, i); 3379 i = 0; 3380 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3381 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3382 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3383 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3384 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3385 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3386 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3387 USETW(ps.wPortChange, i); 3388 totlen = min(len, sizeof(ps)); 3389 memcpy(buf, &ps, totlen); 3390 break; 3391 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3392 return -1; 3393 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3394 break; 3395 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3396 break; 3397 /* Set Port Feature request */ 3398 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3399 int optval = (index >> 8) & 0xff; 3400 index &= 0xff; 3401 if (index < 1 || index > sc->sc_maxports) { 3402 return -1; 3403 } 3404 port = XHCI_PORTSC(index); 3405 v = xhci_op_read_4(sc, port); 3406 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3407 v &= ~XHCI_PS_CLEAR; 3408 switch (value) { 3409 case UHF_PORT_ENABLE: 3410 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3411 break; 3412 case UHF_PORT_SUSPEND: 3413 /* XXX suspend */ 3414 break; 3415 case UHF_PORT_RESET: 3416 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3417 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3418 /* Wait for reset to complete. */ 3419 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3420 if (sc->sc_dying) { 3421 return -1; 3422 } 3423 v = xhci_op_read_4(sc, port); 3424 if (v & XHCI_PS_PR) { 3425 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3426 usb_delay_ms(&sc->sc_bus, 10); 3427 /* XXX */ 3428 } 3429 break; 3430 case UHF_PORT_POWER: 3431 /* XXX power control */ 3432 break; 3433 /* XXX more */ 3434 case UHF_C_PORT_RESET: 3435 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3436 break; 3437 case UHF_PORT_U1_TIMEOUT: 3438 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3439 return -1; 3440 } 3441 port = XHCI_PORTPMSC(index); 3442 v = xhci_op_read_4(sc, port); 3443 v &= ~XHCI_PM3_U1TO_SET(0xff); 3444 v |= XHCI_PM3_U1TO_SET(optval); 3445 xhci_op_write_4(sc, port, v); 3446 break; 3447 case UHF_PORT_U2_TIMEOUT: 3448 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3449 return -1; 3450 } 3451 port = XHCI_PORTPMSC(index); 3452 v = xhci_op_read_4(sc, port); 3453 v &= ~XHCI_PM3_U2TO_SET(0xff); 3454 v |= XHCI_PM3_U2TO_SET(optval); 3455 xhci_op_write_4(sc, port, v); 3456 break; 3457 default: 3458 return -1; 3459 } 3460 } 3461 break; 3462 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3463 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3464 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3465 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3466 break; 3467 default: 3468 /* default from usbroothub */ 3469 return buflen; 3470 } 3471 3472 return totlen; 3473 } 3474 3475 /* root hub interrupt */ 3476 3477 static usbd_status 3478 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3479 { 3480 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3481 usbd_status err; 3482 3483 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3484 3485 /* Insert last in queue. */ 3486 mutex_enter(&sc->sc_lock); 3487 err = usb_insert_transfer(xfer); 3488 mutex_exit(&sc->sc_lock); 3489 if (err) 3490 return err; 3491 3492 /* Pipe isn't running, start first */ 3493 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3494 } 3495 3496 /* Wait for roothub port status/change */ 3497 static usbd_status 3498 xhci_root_intr_start(struct usbd_xfer *xfer) 3499 { 3500 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3501 3502 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3503 3504 if (sc->sc_dying) 3505 return USBD_IOERROR; 3506 3507 mutex_enter(&sc->sc_lock); 3508 sc->sc_intrxfer = xfer; 3509 mutex_exit(&sc->sc_lock); 3510 3511 return USBD_IN_PROGRESS; 3512 } 3513 3514 static void 3515 xhci_root_intr_abort(struct usbd_xfer *xfer) 3516 { 3517 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3518 3519 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3520 3521 KASSERT(mutex_owned(&sc->sc_lock)); 3522 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3523 3524 sc->sc_intrxfer = NULL; 3525 3526 xfer->ux_status = USBD_CANCELLED; 3527 usb_transfer_complete(xfer); 3528 } 3529 3530 static void 3531 xhci_root_intr_close(struct usbd_pipe *pipe) 3532 { 3533 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3534 3535 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3536 3537 KASSERT(mutex_owned(&sc->sc_lock)); 3538 3539 sc->sc_intrxfer = NULL; 3540 } 3541 3542 static void 3543 xhci_root_intr_done(struct usbd_xfer *xfer) 3544 { 3545 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3546 3547 } 3548 3549 /* -------------- */ 3550 /* device control */ 3551 3552 static usbd_status 3553 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3554 { 3555 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3556 usbd_status err; 3557 3558 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3559 3560 /* Insert last in queue. */ 3561 mutex_enter(&sc->sc_lock); 3562 err = usb_insert_transfer(xfer); 3563 mutex_exit(&sc->sc_lock); 3564 if (err) 3565 return err; 3566 3567 /* Pipe isn't running, start first */ 3568 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3569 } 3570 3571 static usbd_status 3572 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3573 { 3574 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3575 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3576 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3577 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3578 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3579 usb_device_request_t * const req = &xfer->ux_request; 3580 const int isread = usbd_xfer_isread(xfer); 3581 const uint32_t len = UGETW(req->wLength); 3582 usb_dma_t * const dma = &xfer->ux_dmabuf; 3583 uint64_t parameter; 3584 uint32_t status; 3585 uint32_t control; 3586 u_int i; 3587 3588 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3589 DPRINTFN(12, "req: %04x %04x %04x %04x", 3590 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3591 UGETW(req->wIndex), UGETW(req->wLength)); 3592 3593 /* we rely on the bottom bits for extra info */ 3594 KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx", 3595 (uintptr_t) xfer); 3596 3597 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3598 3599 i = 0; 3600 3601 /* setup phase */ 3602 memcpy(¶meter, req, sizeof(parameter)); 3603 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3604 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3605 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3606 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3607 XHCI_TRB_3_IDT_BIT; 3608 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3609 3610 if (len != 0) { 3611 /* data phase */ 3612 parameter = DMAADDR(dma, 0); 3613 KASSERTMSG(len <= 0x10000, "len %d", len); 3614 status = XHCI_TRB_2_IRQ_SET(0) | 3615 XHCI_TRB_2_TDSZ_SET(1) | 3616 XHCI_TRB_2_BYTES_SET(len); 3617 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3618 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3619 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3620 XHCI_TRB_3_IOC_BIT; 3621 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3622 } 3623 3624 parameter = 0; 3625 status = XHCI_TRB_2_IRQ_SET(0); 3626 /* the status stage has inverted direction */ 3627 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3628 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3629 XHCI_TRB_3_IOC_BIT; 3630 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3631 3632 mutex_enter(&tr->xr_lock); 3633 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3634 mutex_exit(&tr->xr_lock); 3635 3636 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3637 3638 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3639 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3640 xhci_timeout, xfer); 3641 } 3642 3643 return USBD_IN_PROGRESS; 3644 } 3645 3646 static void 3647 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3648 { 3649 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3650 usb_device_request_t *req = &xfer->ux_request; 3651 int len = UGETW(req->wLength); 3652 int rd = req->bmRequestType & UT_READ; 3653 3654 if (len) 3655 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3656 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3657 } 3658 3659 static void 3660 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3661 { 3662 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3663 3664 xhci_abort_xfer(xfer, USBD_CANCELLED); 3665 } 3666 3667 static void 3668 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3669 { 3670 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3671 3672 xhci_close_pipe(pipe); 3673 } 3674 3675 /* ------------------ */ 3676 /* device isochronous */ 3677 3678 /* ----------- */ 3679 /* device bulk */ 3680 3681 static usbd_status 3682 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3683 { 3684 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3685 usbd_status err; 3686 3687 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3688 3689 /* Insert last in queue. */ 3690 mutex_enter(&sc->sc_lock); 3691 err = usb_insert_transfer(xfer); 3692 mutex_exit(&sc->sc_lock); 3693 if (err) 3694 return err; 3695 3696 /* 3697 * Pipe isn't running (otherwise err would be USBD_INPROG), 3698 * so start it first. 3699 */ 3700 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3701 } 3702 3703 static usbd_status 3704 xhci_device_bulk_start(struct usbd_xfer *xfer) 3705 { 3706 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3707 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3708 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3709 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3710 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3711 const uint32_t len = xfer->ux_length; 3712 usb_dma_t * const dma = &xfer->ux_dmabuf; 3713 uint64_t parameter; 3714 uint32_t status; 3715 uint32_t control; 3716 u_int i = 0; 3717 3718 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3719 3720 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3721 3722 if (sc->sc_dying) 3723 return USBD_IOERROR; 3724 3725 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3726 3727 parameter = DMAADDR(dma, 0); 3728 /* 3729 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3730 * If the user supplied buffer crosses such a boundary then 2 3731 * (or more) TRB should be used. 3732 * If multiple TRB are used the td_size field must be set correctly. 3733 * For v1.0 devices (like ivy bridge) this is the number of usb data 3734 * blocks needed to complete the transfer. 3735 * Setting it to 1 in the last TRB causes an extra zero-length 3736 * data block be sent. 3737 * The earlier documentation differs, I don't know how it behaves. 3738 */ 3739 KASSERTMSG(len <= 0x10000, "len %d", len); 3740 status = XHCI_TRB_2_IRQ_SET(0) | 3741 XHCI_TRB_2_TDSZ_SET(1) | 3742 XHCI_TRB_2_BYTES_SET(len); 3743 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3744 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3745 XHCI_TRB_3_IOC_BIT; 3746 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3747 3748 mutex_enter(&tr->xr_lock); 3749 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3750 mutex_exit(&tr->xr_lock); 3751 3752 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3753 3754 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3755 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3756 xhci_timeout, xfer); 3757 } 3758 3759 return USBD_IN_PROGRESS; 3760 } 3761 3762 static void 3763 xhci_device_bulk_done(struct usbd_xfer *xfer) 3764 { 3765 #ifdef USB_DEBUG 3766 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3767 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3768 #endif 3769 const int isread = usbd_xfer_isread(xfer); 3770 3771 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3772 3773 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3774 3775 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3776 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3777 } 3778 3779 static void 3780 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3781 { 3782 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3783 3784 xhci_abort_xfer(xfer, USBD_CANCELLED); 3785 } 3786 3787 static void 3788 xhci_device_bulk_close(struct usbd_pipe *pipe) 3789 { 3790 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3791 3792 xhci_close_pipe(pipe); 3793 } 3794 3795 /* ---------------- */ 3796 /* device interrupt */ 3797 3798 static usbd_status 3799 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3800 { 3801 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3802 usbd_status err; 3803 3804 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3805 3806 /* Insert last in queue. */ 3807 mutex_enter(&sc->sc_lock); 3808 err = usb_insert_transfer(xfer); 3809 mutex_exit(&sc->sc_lock); 3810 if (err) 3811 return err; 3812 3813 /* 3814 * Pipe isn't running (otherwise err would be USBD_INPROG), 3815 * so start it first. 3816 */ 3817 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3818 } 3819 3820 static usbd_status 3821 xhci_device_intr_start(struct usbd_xfer *xfer) 3822 { 3823 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3824 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3825 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3826 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3827 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3828 const uint32_t len = xfer->ux_length; 3829 usb_dma_t * const dma = &xfer->ux_dmabuf; 3830 uint64_t parameter; 3831 uint32_t status; 3832 uint32_t control; 3833 u_int i = 0; 3834 3835 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3836 3837 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3838 3839 if (sc->sc_dying) 3840 return USBD_IOERROR; 3841 3842 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3843 3844 parameter = DMAADDR(dma, 0); 3845 KASSERTMSG(len <= 0x10000, "len %d", len); 3846 status = XHCI_TRB_2_IRQ_SET(0) | 3847 XHCI_TRB_2_TDSZ_SET(1) | 3848 XHCI_TRB_2_BYTES_SET(len); 3849 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3850 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3851 XHCI_TRB_3_IOC_BIT; 3852 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3853 3854 mutex_enter(&tr->xr_lock); 3855 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3856 mutex_exit(&tr->xr_lock); 3857 3858 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3859 3860 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3861 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3862 xhci_timeout, xfer); 3863 } 3864 3865 return USBD_IN_PROGRESS; 3866 } 3867 3868 static void 3869 xhci_device_intr_done(struct usbd_xfer *xfer) 3870 { 3871 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3872 #ifdef USB_DEBUG 3873 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3874 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3875 #endif 3876 const int isread = usbd_xfer_isread(xfer); 3877 3878 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3879 3880 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3881 3882 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3883 3884 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3885 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3886 } 3887 3888 static void 3889 xhci_device_intr_abort(struct usbd_xfer *xfer) 3890 { 3891 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3892 3893 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3894 3895 KASSERT(mutex_owned(&sc->sc_lock)); 3896 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3897 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3898 xhci_abort_xfer(xfer, USBD_CANCELLED); 3899 } 3900 3901 static void 3902 xhci_device_intr_close(struct usbd_pipe *pipe) 3903 { 3904 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3905 3906 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3907 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3908 3909 xhci_close_pipe(pipe); 3910 } 3911 3912 /* ------------ */ 3913 3914 static void 3915 xhci_timeout(void *addr) 3916 { 3917 struct xhci_xfer * const xx = addr; 3918 struct usbd_xfer * const xfer = &xx->xx_xfer; 3919 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3920 3921 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3922 3923 if (sc->sc_dying) { 3924 return; 3925 } 3926 3927 usb_init_task(&xfer->ux_aborttask, xhci_timeout_task, addr, 3928 USB_TASKQ_MPSAFE); 3929 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xfer->ux_aborttask, 3930 USB_TASKQ_HC); 3931 } 3932 3933 static void 3934 xhci_timeout_task(void *addr) 3935 { 3936 struct usbd_xfer * const xfer = addr; 3937 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3938 3939 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3940 3941 mutex_enter(&sc->sc_lock); 3942 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3943 mutex_exit(&sc->sc_lock); 3944 } 3945
Indexes created Wed Oct 01 15:09:59 GMT 2025