xhci.c revision 1.28.2.79
1 /* $NetBSD: xhci.c,v 1.28.2.79 2017/01/02 16:32:23 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.28.2.79 2017/01/02 16:32:23 skrll Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static void xhci_host_dequeue(struct xhci_ring * const); 146 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 147 148 static usbd_status xhci_do_command(struct xhci_softc * const, 149 struct xhci_trb * const, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 153 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 154 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 155 static usbd_status xhci_enable_slot(struct xhci_softc * const, 156 uint8_t * const); 157 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 158 static usbd_status xhci_address_device(struct xhci_softc * const, 159 uint64_t, uint8_t, bool); 160 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 161 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 162 struct xhci_slot * const, u_int); 163 static usbd_status xhci_ring_init(struct xhci_softc * const, 164 struct xhci_ring * const, size_t, size_t); 165 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 166 167 static void xhci_setup_ctx(struct usbd_pipe *); 168 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 169 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 170 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 171 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 172 173 static void xhci_noop(struct usbd_pipe *); 174 175 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 176 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 177 static void xhci_root_intr_abort(struct usbd_xfer *); 178 static void xhci_root_intr_close(struct usbd_pipe *); 179 static void xhci_root_intr_done(struct usbd_xfer *); 180 181 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 182 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 183 static void xhci_device_ctrl_abort(struct usbd_xfer *); 184 static void xhci_device_ctrl_close(struct usbd_pipe *); 185 static void xhci_device_ctrl_done(struct usbd_xfer *); 186 187 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 188 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 189 static void xhci_device_intr_abort(struct usbd_xfer *); 190 static void xhci_device_intr_close(struct usbd_pipe *); 191 static void xhci_device_intr_done(struct usbd_xfer *); 192 193 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 194 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 195 static void xhci_device_bulk_abort(struct usbd_xfer *); 196 static void xhci_device_bulk_close(struct usbd_pipe *); 197 static void xhci_device_bulk_done(struct usbd_xfer *); 198 199 static void xhci_timeout(void *); 200 static void xhci_timeout_task(void *); 201 202 static const struct usbd_bus_methods xhci_bus_methods = { 203 .ubm_open = xhci_open, 204 .ubm_softint = xhci_softintr, 205 .ubm_dopoll = xhci_poll, 206 .ubm_allocx = xhci_allocx, 207 .ubm_freex = xhci_freex, 208 .ubm_getlock = xhci_get_lock, 209 .ubm_newdev = xhci_new_device, 210 .ubm_rhctrl = xhci_roothub_ctrl, 211 }; 212 213 static const struct usbd_pipe_methods xhci_root_intr_methods = { 214 .upm_transfer = xhci_root_intr_transfer, 215 .upm_start = xhci_root_intr_start, 216 .upm_abort = xhci_root_intr_abort, 217 .upm_close = xhci_root_intr_close, 218 .upm_cleartoggle = xhci_noop, 219 .upm_done = xhci_root_intr_done, 220 }; 221 222 223 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 224 .upm_transfer = xhci_device_ctrl_transfer, 225 .upm_start = xhci_device_ctrl_start, 226 .upm_abort = xhci_device_ctrl_abort, 227 .upm_close = xhci_device_ctrl_close, 228 .upm_cleartoggle = xhci_noop, 229 .upm_done = xhci_device_ctrl_done, 230 }; 231 232 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 233 .upm_cleartoggle = xhci_noop, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 237 .upm_transfer = xhci_device_bulk_transfer, 238 .upm_start = xhci_device_bulk_start, 239 .upm_abort = xhci_device_bulk_abort, 240 .upm_close = xhci_device_bulk_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_bulk_done, 243 }; 244 245 static const struct usbd_pipe_methods xhci_device_intr_methods = { 246 .upm_transfer = xhci_device_intr_transfer, 247 .upm_start = xhci_device_intr_start, 248 .upm_abort = xhci_device_intr_abort, 249 .upm_close = xhci_device_intr_close, 250 .upm_cleartoggle = xhci_noop, 251 .upm_done = xhci_device_intr_done, 252 }; 253 254 static inline uint32_t 255 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 256 { 257 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 258 } 259 260 static inline uint32_t 261 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 262 { 263 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 264 } 265 266 static inline void 267 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 268 uint32_t value) 269 { 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 271 } 272 273 #if 0 /* unused */ 274 static inline void 275 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 276 uint32_t value) 277 { 278 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 279 } 280 #endif /* unused */ 281 282 static inline uint32_t 283 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 284 { 285 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 286 } 287 288 static inline uint32_t 289 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 290 { 291 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 292 } 293 294 static inline void 295 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 296 uint32_t value) 297 { 298 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 299 } 300 301 static inline uint64_t 302 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 303 { 304 uint64_t value; 305 306 if (sc->sc_ac64) { 307 #ifdef XHCI_USE_BUS_SPACE_8 308 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 309 #else 310 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 311 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 312 offset + 4) << 32; 313 #endif 314 } else { 315 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 316 } 317 318 return value; 319 } 320 321 static inline void 322 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 336 } 337 } 338 339 static inline uint32_t 340 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 341 { 342 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 343 } 344 345 static inline void 346 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 347 uint32_t value) 348 { 349 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 350 } 351 352 #if 0 /* unused */ 353 static inline uint64_t 354 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 355 { 356 uint64_t value; 357 358 if (sc->sc_ac64) { 359 #ifdef XHCI_USE_BUS_SPACE_8 360 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 361 #else 362 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 363 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 364 offset + 4) << 32; 365 #endif 366 } else { 367 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 368 } 369 370 return value; 371 } 372 #endif /* unused */ 373 374 static inline void 375 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 376 uint64_t value) 377 { 378 if (sc->sc_ac64) { 379 #ifdef XHCI_USE_BUS_SPACE_8 380 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 381 #else 382 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 383 (value >> 0) & 0xffffffff); 384 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 385 (value >> 32) & 0xffffffff); 386 #endif 387 } else { 388 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 389 } 390 } 391 392 #if 0 /* unused */ 393 static inline uint32_t 394 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 395 { 396 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 397 } 398 #endif /* unused */ 399 400 static inline void 401 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 402 uint32_t value) 403 { 404 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 405 } 406 407 /* --- */ 408 409 static inline uint8_t 410 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 411 { 412 u_int eptype = 0; 413 414 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 415 case UE_CONTROL: 416 eptype = 0x0; 417 break; 418 case UE_ISOCHRONOUS: 419 eptype = 0x1; 420 break; 421 case UE_BULK: 422 eptype = 0x2; 423 break; 424 case UE_INTERRUPT: 425 eptype = 0x3; 426 break; 427 } 428 429 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 430 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 431 return eptype | 0x4; 432 else 433 return eptype; 434 } 435 436 static u_int 437 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 438 { 439 /* xHCI 1.0 section 4.5.1 */ 440 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 441 u_int in = 0; 442 443 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 444 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 445 in = 1; 446 447 return epaddr * 2 + in; 448 } 449 450 static inline u_int 451 xhci_dci_to_ici(const u_int i) 452 { 453 return i + 1; 454 } 455 456 static inline void * 457 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 458 const u_int dci) 459 { 460 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 461 } 462 463 #if 0 /* unused */ 464 static inline bus_addr_t 465 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 466 const u_int dci) 467 { 468 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 469 } 470 #endif /* unused */ 471 472 static inline void * 473 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline bus_addr_t 480 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 481 const u_int ici) 482 { 483 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 484 } 485 486 static inline struct xhci_trb * 487 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 488 { 489 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 490 } 491 492 static inline bus_addr_t 493 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 494 { 495 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 496 } 497 498 static inline void 499 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 500 uint32_t control) 501 { 502 trb->trb_0 = htole64(parameter); 503 trb->trb_2 = htole32(status); 504 trb->trb_3 = htole32(control); 505 } 506 507 static int 508 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 509 { 510 /* base address of TRBs */ 511 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 512 513 /* trb_0 range sanity check */ 514 if (trb_0 == 0 || trb_0 < trbp || 515 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 516 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 517 return 1; 518 } 519 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 520 return 0; 521 } 522 523 static unsigned int 524 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 525 u_int dci) 526 { 527 uint32_t *cp; 528 529 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 530 cp = xhci_slot_get_dcv(sc, xs, dci); 531 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 532 } 533 534 /* --- */ 535 536 void 537 xhci_childdet(device_t self, device_t child) 538 { 539 struct xhci_softc * const sc = device_private(self); 540 541 KASSERT(sc->sc_child == child); 542 if (child == sc->sc_child) 543 sc->sc_child = NULL; 544 } 545 546 int 547 xhci_detach(struct xhci_softc *sc, int flags) 548 { 549 int rv = 0; 550 551 if (sc->sc_child != NULL) 552 rv = config_detach(sc->sc_child, flags); 553 554 if (rv != 0) 555 return rv; 556 557 /* XXX unconfigure/free slots */ 558 559 /* verify: */ 560 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 561 xhci_op_write_4(sc, XHCI_USBCMD, 0); 562 /* do we need to wait for stop? */ 563 564 xhci_op_write_8(sc, XHCI_CRCR, 0); 565 xhci_ring_free(sc, &sc->sc_cr); 566 cv_destroy(&sc->sc_command_cv); 567 cv_destroy(&sc->sc_cmdbusy_cv); 568 569 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 570 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 571 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 572 xhci_ring_free(sc, &sc->sc_er); 573 574 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 575 576 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 577 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 578 579 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 580 581 mutex_destroy(&sc->sc_lock); 582 mutex_destroy(&sc->sc_intr_lock); 583 584 pool_cache_destroy(sc->sc_xferpool); 585 586 return rv; 587 } 588 589 int 590 xhci_activate(device_t self, enum devact act) 591 { 592 struct xhci_softc * const sc = device_private(self); 593 594 switch (act) { 595 case DVACT_DEACTIVATE: 596 sc->sc_dying = true; 597 return 0; 598 default: 599 return EOPNOTSUPP; 600 } 601 } 602 603 bool 604 xhci_suspend(device_t dv, const pmf_qual_t *qual) 605 { 606 return false; 607 } 608 609 bool 610 xhci_resume(device_t dv, const pmf_qual_t *qual) 611 { 612 return false; 613 } 614 615 bool 616 xhci_shutdown(device_t self, int flags) 617 { 618 return false; 619 } 620 621 static int 622 xhci_hc_reset(struct xhci_softc * const sc) 623 { 624 uint32_t usbcmd, usbsts; 625 int i; 626 627 /* Check controller not ready */ 628 for (i = 0; i < XHCI_WAIT_CNR; i++) { 629 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 630 if ((usbsts & XHCI_STS_CNR) == 0) 631 break; 632 usb_delay_ms(&sc->sc_bus, 1); 633 } 634 if (i >= XHCI_WAIT_CNR) { 635 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 636 return EIO; 637 } 638 639 /* Halt controller */ 640 usbcmd = 0; 641 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 642 usb_delay_ms(&sc->sc_bus, 1); 643 644 /* Reset controller */ 645 usbcmd = XHCI_CMD_HCRST; 646 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 647 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 648 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 649 if ((usbcmd & XHCI_CMD_HCRST) == 0) 650 break; 651 usb_delay_ms(&sc->sc_bus, 1); 652 } 653 if (i >= XHCI_WAIT_HCRST) { 654 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 655 return EIO; 656 } 657 658 /* Check controller not ready */ 659 for (i = 0; i < XHCI_WAIT_CNR; i++) { 660 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 661 if ((usbsts & XHCI_STS_CNR) == 0) 662 break; 663 usb_delay_ms(&sc->sc_bus, 1); 664 } 665 if (i >= XHCI_WAIT_CNR) { 666 aprint_error_dev(sc->sc_dev, 667 "controller not ready timeout after reset\n"); 668 return EIO; 669 } 670 671 return 0; 672 } 673 674 675 static void 676 hexdump(const char *msg, const void *base, size_t len) 677 { 678 #if 0 679 size_t cnt; 680 const uint32_t *p; 681 extern paddr_t vtophys(vaddr_t); 682 683 p = base; 684 cnt = 0; 685 686 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 687 (void *)vtophys((vaddr_t)base)); 688 689 while (cnt < len) { 690 if (cnt % 16 == 0) 691 printf("%p: ", p); 692 else if (cnt % 8 == 0) 693 printf(" |"); 694 printf(" %08x", *p++); 695 cnt += 4; 696 if (cnt % 16 == 0) 697 printf("\n"); 698 } 699 if (cnt % 16 != 0) 700 printf("\n"); 701 #endif 702 } 703 704 /* Process extended capabilities */ 705 static void 706 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 707 { 708 uint32_t ecp, ecr; 709 710 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 711 712 ecp = XHCI_HCC_XECP(hcc) * 4; 713 while (ecp != 0) { 714 ecr = xhci_read_4(sc, ecp); 715 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 716 switch (XHCI_XECP_ID(ecr)) { 717 case XHCI_ID_PROTOCOLS: { 718 uint32_t w4, w8, wc; 719 uint16_t w2; 720 w2 = (ecr >> 16) & 0xffff; 721 w4 = xhci_read_4(sc, ecp + 4); 722 w8 = xhci_read_4(sc, ecp + 8); 723 wc = xhci_read_4(sc, ecp + 0xc); 724 aprint_debug_dev(sc->sc_dev, 725 " SP: %08x %08x %08x %08x\n", ecr, w4, w8, wc); 726 /* unused */ 727 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0300) { 728 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 729 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 730 } 731 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0200) { 732 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 733 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 734 } 735 break; 736 } 737 case XHCI_ID_USB_LEGACY: { 738 uint8_t bios_sem; 739 740 /* Take host controller ownership from BIOS */ 741 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 742 if (bios_sem) { 743 /* sets xHCI to be owned by OS */ 744 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 745 aprint_debug_dev(sc->sc_dev, 746 "waiting for BIOS to give up control\n"); 747 for (int i = 0; i < 5000; i++) { 748 bios_sem = xhci_read_1(sc, ecp + 749 XHCI_XECP_BIOS_SEM); 750 if (bios_sem == 0) 751 break; 752 DELAY(1000); 753 } 754 if (bios_sem) { 755 aprint_error_dev(sc->sc_dev, 756 "timed out waiting for BIOS\n"); 757 } 758 } 759 break; 760 } 761 default: 762 break; 763 } 764 ecr = xhci_read_4(sc, ecp); 765 if (XHCI_XECP_NEXT(ecr) == 0) { 766 ecp = 0; 767 } else { 768 ecp += XHCI_XECP_NEXT(ecr) * 4; 769 } 770 } 771 } 772 773 #define XHCI_HCCPREV1_BITS \ 774 "\177\020" /* New bitmask */ \ 775 "f\020\020XECP\0" \ 776 "f\014\4MAXPSA\0" \ 777 "b\013CFC\0" \ 778 "b\012SEC\0" \ 779 "b\011SBD\0" \ 780 "b\010FSE\0" \ 781 "b\7NSS\0" \ 782 "b\6LTC\0" \ 783 "b\5LHRC\0" \ 784 "b\4PIND\0" \ 785 "b\3PPC\0" \ 786 "b\2CZC\0" \ 787 "b\1BNC\0" \ 788 "b\0AC64\0" \ 789 "\0" 790 #define XHCI_HCCV1_x_BITS \ 791 "\177\020" /* New bitmask */ \ 792 "f\020\020XECP\0" \ 793 "f\014\4MAXPSA\0" \ 794 "b\013CFC\0" \ 795 "b\012SEC\0" \ 796 "b\011SPC\0" \ 797 "b\010PAE\0" \ 798 "b\7NSS\0" \ 799 "b\6LTC\0" \ 800 "b\5LHRC\0" \ 801 "b\4PIND\0" \ 802 "b\3PPC\0" \ 803 "b\2CSZ\0" \ 804 "b\1BNC\0" \ 805 "b\0AC64\0" \ 806 "\0" 807 808 int 809 xhci_init(struct xhci_softc *sc) 810 { 811 bus_size_t bsz; 812 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 813 uint32_t pagesize, config; 814 int i = 0; 815 uint16_t hciversion; 816 uint8_t caplength; 817 818 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 819 820 sc->sc_bus.ub_revision = USBREV_3_0; 821 sc->sc_bus.ub_usedma = true; 822 823 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 824 caplength = XHCI_CAP_CAPLENGTH(cap); 825 hciversion = XHCI_CAP_HCIVERSION(cap); 826 827 if (hciversion < XHCI_HCIVERSION_0_96 || 828 hciversion > XHCI_HCIVERSION_1_0) { 829 aprint_normal_dev(sc->sc_dev, 830 "xHCI version %x.%x not known to be supported\n", 831 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 832 } else { 833 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 834 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 835 } 836 837 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 838 &sc->sc_cbh) != 0) { 839 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 840 return ENOMEM; 841 } 842 843 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 844 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 845 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 846 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 847 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 848 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 849 aprint_debug_dev(sc->sc_dev, 850 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 851 852 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 853 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 854 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 855 856 char sbuf[128]; 857 if (hciversion < XHCI_HCIVERSION_1_0) 858 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 859 else 860 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 861 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 862 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 863 864 /* print PSI and take ownership from BIOS */ 865 xhci_ecp(sc, hcc); 866 867 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 868 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 869 &sc->sc_obh) != 0) { 870 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 871 return ENOMEM; 872 } 873 874 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 875 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 876 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 877 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 878 return ENOMEM; 879 } 880 881 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 882 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 883 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 884 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 885 return ENOMEM; 886 } 887 888 int rv; 889 rv = xhci_hc_reset(sc); 890 if (rv != 0) { 891 return rv; 892 } 893 894 if (sc->sc_vendor_init) 895 sc->sc_vendor_init(sc); 896 897 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 898 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 899 pagesize = ffs(pagesize); 900 if (pagesize == 0) { 901 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 902 return EIO; 903 } 904 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 905 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 906 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 907 (uint32_t)sc->sc_maxslots); 908 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 909 910 usbd_status err; 911 912 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 913 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 914 if (sc->sc_maxspbuf != 0) { 915 err = usb_allocmem(&sc->sc_bus, 916 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 917 &sc->sc_spbufarray_dma); 918 if (err) { 919 aprint_error_dev(sc->sc_dev, 920 "spbufarray init fail, err %d\n", err); 921 return ENOMEM; 922 } 923 924 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 925 sc->sc_maxspbuf, KM_SLEEP); 926 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 927 for (i = 0; i < sc->sc_maxspbuf; i++) { 928 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 929 /* allocate contexts */ 930 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 931 sc->sc_pgsz, dma); 932 if (err) { 933 aprint_error_dev(sc->sc_dev, 934 "spbufarray_dma init fail, err %d\n", err); 935 rv = ENOMEM; 936 goto bad1; 937 } 938 spbufarray[i] = htole64(DMAADDR(dma, 0)); 939 usb_syncmem(dma, 0, sc->sc_pgsz, 940 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 941 } 942 943 usb_syncmem(&sc->sc_spbufarray_dma, 0, 944 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 945 } 946 947 config = xhci_op_read_4(sc, XHCI_CONFIG); 948 config &= ~0xFF; 949 config |= sc->sc_maxslots & 0xFF; 950 xhci_op_write_4(sc, XHCI_CONFIG, config); 951 952 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 953 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 954 if (err) { 955 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 956 err); 957 rv = ENOMEM; 958 goto bad1; 959 } 960 961 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 962 XHCI_EVENT_RING_SEGMENTS_ALIGN); 963 if (err) { 964 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 965 err); 966 rv = ENOMEM; 967 goto bad2; 968 } 969 970 usb_dma_t *dma; 971 size_t size; 972 size_t align; 973 974 dma = &sc->sc_eventst_dma; 975 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 976 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 977 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 978 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 979 err = usb_allocmem(&sc->sc_bus, size, align, dma); 980 if (err) { 981 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 982 err); 983 rv = ENOMEM; 984 goto bad3; 985 } 986 987 memset(KERNADDR(dma, 0), 0, size); 988 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 989 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 990 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 991 KERNADDR(&sc->sc_eventst_dma, 0), 992 sc->sc_eventst_dma.udma_block->size); 993 994 dma = &sc->sc_dcbaa_dma; 995 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 996 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 997 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 998 err = usb_allocmem(&sc->sc_bus, size, align, dma); 999 if (err) { 1000 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1001 rv = ENOMEM; 1002 goto bad4; 1003 } 1004 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 1005 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1006 KERNADDR(&sc->sc_dcbaa_dma, 0), 1007 sc->sc_dcbaa_dma.udma_block->size); 1008 1009 memset(KERNADDR(dma, 0), 0, size); 1010 if (sc->sc_maxspbuf != 0) { 1011 /* 1012 * DCBA entry 0 hold the scratchbuf array pointer. 1013 */ 1014 *(uint64_t *)KERNADDR(dma, 0) = 1015 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1016 } 1017 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1018 1019 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1020 KM_SLEEP); 1021 if (sc->sc_slots == NULL) { 1022 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1023 rv = ENOMEM; 1024 goto bad; 1025 } 1026 1027 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1028 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1029 if (sc->sc_xferpool == NULL) { 1030 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1031 err); 1032 rv = ENOMEM; 1033 goto bad; 1034 } 1035 1036 cv_init(&sc->sc_command_cv, "xhcicmd"); 1037 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1038 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1039 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1040 1041 /* Set up the bus struct. */ 1042 sc->sc_bus.ub_methods = &xhci_bus_methods; 1043 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 1044 1045 struct xhci_erste *erst; 1046 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1047 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1048 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1049 erst[0].erste_3 = htole32(0); 1050 usb_syncmem(&sc->sc_eventst_dma, 0, 1051 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1052 1053 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1054 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1055 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1056 XHCI_ERDP_LO_BUSY); 1057 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1058 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1059 sc->sc_cr.xr_cs); 1060 1061 #if 0 1062 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1063 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1064 #endif 1065 1066 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1067 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1068 /* Intel xhci needs interrupt rate moderated. */ 1069 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1070 else 1071 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1072 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 1073 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1074 1075 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 1076 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1077 xhci_op_read_4(sc, XHCI_USBCMD)); 1078 1079 return 0; 1080 1081 bad: 1082 if (sc->sc_xferpool) { 1083 pool_cache_destroy(sc->sc_xferpool); 1084 sc->sc_xferpool = NULL; 1085 } 1086 1087 if (sc->sc_slots) { 1088 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1089 sc->sc_maxslots); 1090 sc->sc_slots = NULL; 1091 } 1092 1093 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1094 bad4: 1095 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1096 bad3: 1097 xhci_ring_free(sc, &sc->sc_er); 1098 bad2: 1099 xhci_ring_free(sc, &sc->sc_cr); 1100 i = sc->sc_maxspbuf; 1101 bad1: 1102 for (int j = 0; j < i; j++) 1103 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1104 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1105 1106 return rv; 1107 } 1108 1109 int 1110 xhci_intr(void *v) 1111 { 1112 struct xhci_softc * const sc = v; 1113 int ret = 0; 1114 1115 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1116 1117 if (sc == NULL) 1118 return 0; 1119 1120 mutex_spin_enter(&sc->sc_intr_lock); 1121 1122 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1123 goto done; 1124 1125 /* If we get an interrupt while polling, then just ignore it. */ 1126 if (sc->sc_bus.ub_usepolling) { 1127 #ifdef DIAGNOSTIC 1128 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1129 #endif 1130 goto done; 1131 } 1132 1133 ret = xhci_intr1(sc); 1134 done: 1135 mutex_spin_exit(&sc->sc_intr_lock); 1136 return ret; 1137 } 1138 1139 int 1140 xhci_intr1(struct xhci_softc * const sc) 1141 { 1142 uint32_t usbsts; 1143 uint32_t iman; 1144 1145 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1146 1147 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1148 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1149 #if 0 1150 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1151 return 0; 1152 } 1153 #endif 1154 xhci_op_write_4(sc, XHCI_USBSTS, 1155 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1156 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1157 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1158 1159 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1160 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1161 iman |= XHCI_IMAN_INTR_PEND; 1162 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1163 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1164 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1165 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1166 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1167 1168 usb_schedsoftintr(&sc->sc_bus); 1169 1170 return 1; 1171 } 1172 1173 /* 1174 * 3 port speed types used in USB stack 1175 * 1176 * usbdi speed 1177 * definition: USB_SPEED_* in usb.h 1178 * They are used in struct usbd_device in USB stack. 1179 * ioctl interface uses these values too. 1180 * port_status speed 1181 * definition: UPS_*_SPEED in usb.h 1182 * They are used in usb_port_status_t and valid only for USB 2.0. 1183 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1184 * of usb_port_status_ext_t indicates port speed. 1185 * Note that some 3.0 values overlap with 2.0 values. 1186 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1187 * means UPS_LOW_SPEED in HS.) 1188 * port status returned from hub also uses these values. 1189 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1190 * or more. 1191 * xspeed: 1192 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1193 * They are used in only slot context and PORTSC reg of xhci. 1194 * The difference between usbdi speed and xspeed is 1195 * that FS and LS values are swapped. 1196 */ 1197 1198 /* convert usbdi speed to xspeed */ 1199 static int 1200 xhci_speed2xspeed(int speed) 1201 { 1202 switch (speed) { 1203 case USB_SPEED_LOW: return 2; 1204 case USB_SPEED_FULL: return 1; 1205 default: return speed; 1206 } 1207 } 1208 1209 #if 0 1210 /* convert xspeed to usbdi speed */ 1211 static int 1212 xhci_xspeed2speed(int xspeed) 1213 { 1214 switch (xspeed) { 1215 case 1: return USB_SPEED_FULL; 1216 case 2: return USB_SPEED_LOW; 1217 default: return xspeed; 1218 } 1219 } 1220 #endif 1221 1222 /* convert xspeed to port status speed */ 1223 static int 1224 xhci_xspeed2psspeed(int xspeed) 1225 { 1226 switch (xspeed) { 1227 case 0: return 0; 1228 case 1: return UPS_FULL_SPEED; 1229 case 2: return UPS_LOW_SPEED; 1230 case 3: return UPS_HIGH_SPEED; 1231 default: return UPS_OTHER_SPEED; 1232 } 1233 } 1234 1235 /* 1236 * Construct input contexts and issue TRB to open pipe. 1237 */ 1238 static usbd_status 1239 xhci_configure_endpoint(struct usbd_pipe *pipe) 1240 { 1241 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1242 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1243 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1244 struct xhci_trb trb; 1245 usbd_status err; 1246 1247 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1248 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1249 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1250 pipe->up_endpoint->ue_edesc->bmAttributes); 1251 1252 /* XXX ensure input context is available? */ 1253 1254 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1255 1256 /* set up context */ 1257 xhci_setup_ctx(pipe); 1258 1259 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1260 sc->sc_ctxsz * 1); 1261 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1262 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1263 1264 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1265 trb.trb_2 = 0; 1266 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1267 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1268 1269 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1270 1271 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1272 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1273 sc->sc_ctxsz * 1); 1274 1275 return err; 1276 } 1277 1278 #if 0 1279 static usbd_status 1280 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1281 { 1282 #ifdef USB_DEBUG 1283 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1284 #endif 1285 1286 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1287 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1288 1289 return USBD_NORMAL_COMPLETION; 1290 } 1291 #endif 1292 1293 /* 4.6.8, 6.4.3.7 */ 1294 static usbd_status 1295 xhci_reset_endpoint_locked(struct usbd_pipe *pipe) 1296 { 1297 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1298 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1299 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1300 struct xhci_trb trb; 1301 usbd_status err; 1302 1303 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1304 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1305 1306 KASSERT(mutex_owned(&sc->sc_lock)); 1307 1308 trb.trb_0 = 0; 1309 trb.trb_2 = 0; 1310 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1311 XHCI_TRB_3_EP_SET(dci) | 1312 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1313 1314 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1315 1316 return err; 1317 } 1318 1319 static usbd_status 1320 xhci_reset_endpoint(struct usbd_pipe *pipe) 1321 { 1322 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1323 1324 mutex_enter(&sc->sc_lock); 1325 usbd_status ret = xhci_reset_endpoint_locked(pipe); 1326 mutex_exit(&sc->sc_lock); 1327 1328 return ret; 1329 } 1330 1331 /* 1332 * 4.6.9, 6.4.3.8 1333 * Stop execution of TDs on xfer ring. 1334 * Should be called with sc_lock held. 1335 */ 1336 static usbd_status 1337 xhci_stop_endpoint(struct usbd_pipe *pipe) 1338 { 1339 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1340 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1341 struct xhci_trb trb; 1342 usbd_status err; 1343 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1344 1345 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1346 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1347 1348 KASSERT(mutex_owned(&sc->sc_lock)); 1349 1350 trb.trb_0 = 0; 1351 trb.trb_2 = 0; 1352 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1353 XHCI_TRB_3_EP_SET(dci) | 1354 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1355 1356 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1357 1358 return err; 1359 } 1360 1361 /* 1362 * Set TR Dequeue Pointer. 1363 * xHCI 1.1 4.6.10 6.4.3.9 1364 * Purge all of the TRBs on ring and reinitialize ring. 1365 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1366 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1367 * error will be generated. 1368 */ 1369 static usbd_status 1370 xhci_set_dequeue_locked(struct usbd_pipe *pipe) 1371 { 1372 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1373 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1374 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1375 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1376 struct xhci_trb trb; 1377 usbd_status err; 1378 1379 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1380 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1381 1382 KASSERT(mutex_owned(&sc->sc_lock)); 1383 1384 xhci_host_dequeue(xr); 1385 1386 /* set DCS */ 1387 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1388 trb.trb_2 = 0; 1389 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1390 XHCI_TRB_3_EP_SET(dci) | 1391 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1392 1393 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1394 1395 return err; 1396 } 1397 1398 static usbd_status 1399 xhci_set_dequeue(struct usbd_pipe *pipe) 1400 { 1401 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1402 1403 mutex_enter(&sc->sc_lock); 1404 usbd_status ret = xhci_set_dequeue_locked(pipe); 1405 mutex_exit(&sc->sc_lock); 1406 1407 return ret; 1408 } 1409 1410 /* 1411 * Open new pipe: called from usbd_setup_pipe_flags. 1412 * Fills methods of pipe. 1413 * If pipe is not for ep0, calls configure_endpoint. 1414 */ 1415 static usbd_status 1416 xhci_open(struct usbd_pipe *pipe) 1417 { 1418 struct usbd_device * const dev = pipe->up_dev; 1419 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1420 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1421 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1422 1423 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1424 DPRINTFN(1, "addr %d depth %d port %d speed %d", dev->ud_addr, 1425 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1426 DPRINTFN(1, " dci %u type 0x%02x epaddr 0x%02x attr 0x%02x", 1427 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1428 ed->bmAttributes); 1429 DPRINTFN(1, " mps %u ival %u", UGETW(ed->wMaxPacketSize), ed->bInterval, 1430 0, 0); 1431 1432 if (sc->sc_dying) 1433 return USBD_IOERROR; 1434 1435 /* Root Hub */ 1436 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1437 switch (ed->bEndpointAddress) { 1438 case USB_CONTROL_ENDPOINT: 1439 pipe->up_methods = &roothub_ctrl_methods; 1440 break; 1441 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1442 pipe->up_methods = &xhci_root_intr_methods; 1443 break; 1444 default: 1445 pipe->up_methods = NULL; 1446 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1447 ed->bEndpointAddress, 0, 0, 0); 1448 return USBD_INVAL; 1449 } 1450 return USBD_NORMAL_COMPLETION; 1451 } 1452 1453 switch (xfertype) { 1454 case UE_CONTROL: 1455 pipe->up_methods = &xhci_device_ctrl_methods; 1456 break; 1457 case UE_ISOCHRONOUS: 1458 pipe->up_methods = &xhci_device_isoc_methods; 1459 return USBD_INVAL; 1460 break; 1461 case UE_BULK: 1462 pipe->up_methods = &xhci_device_bulk_methods; 1463 break; 1464 case UE_INTERRUPT: 1465 pipe->up_methods = &xhci_device_intr_methods; 1466 break; 1467 default: 1468 return USBD_IOERROR; 1469 break; 1470 } 1471 1472 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1473 return xhci_configure_endpoint(pipe); 1474 1475 return USBD_NORMAL_COMPLETION; 1476 } 1477 1478 /* 1479 * Closes pipe, called from usbd_kill_pipe via close methods. 1480 * If the endpoint to be closed is ep0, disable_slot. 1481 * Should be called with sc_lock held. 1482 */ 1483 static void 1484 xhci_close_pipe(struct usbd_pipe *pipe) 1485 { 1486 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1487 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1488 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1489 const u_int dci = xhci_ep_get_dci(ed); 1490 struct xhci_trb trb; 1491 uint32_t *cp; 1492 1493 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1494 1495 if (sc->sc_dying) 1496 return; 1497 1498 /* xs is uninitialized before xhci_init_slot */ 1499 if (xs == NULL || xs->xs_idx == 0) 1500 return; 1501 1502 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1503 1504 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1505 KASSERT(mutex_owned(&sc->sc_lock)); 1506 1507 if (pipe->up_dev->ud_depth == 0) 1508 return; 1509 1510 if (dci == XHCI_DCI_EP_CONTROL) { 1511 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1512 xhci_disable_slot(sc, xs->xs_idx); 1513 return; 1514 } 1515 1516 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED) 1517 (void)xhci_stop_endpoint(pipe); 1518 1519 /* 1520 * set appropriate bit to be dropped. 1521 * don't set DC bit to 1, otherwise all endpoints 1522 * would be deconfigured. 1523 */ 1524 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1525 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1526 cp[1] = htole32(0); 1527 1528 /* XXX should be most significant one, not dci? */ 1529 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1530 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1531 1532 /* configure ep context performs an implicit dequeue */ 1533 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 1534 1535 /* sync input contexts before they are read from memory */ 1536 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1537 1538 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1539 trb.trb_2 = 0; 1540 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1541 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1542 1543 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1544 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1545 } 1546 1547 /* 1548 * Abort transfer. 1549 * Should be called with sc_lock held. 1550 */ 1551 static void 1552 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1553 { 1554 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1555 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1556 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1557 1558 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1559 DPRINTFN(4, "xfer %p pipe %p status %d", 1560 xfer, xfer->ux_pipe, status, 0); 1561 1562 KASSERT(mutex_owned(&sc->sc_lock)); 1563 ASSERT_SLEEPABLE(); 1564 1565 if (sc->sc_dying) { 1566 /* If we're dying, just do the software part. */ 1567 DPRINTFN(4, "xfer %p dying %u", xfer, xfer->ux_status, 0, 0); 1568 xfer->ux_status = status; 1569 callout_halt(&xfer->ux_callout, &sc->sc_lock); 1570 usb_transfer_complete(xfer); 1571 return; 1572 } 1573 1574 /* 1575 * If an abort is already in progress then just wait for it to 1576 * complete and return. 1577 */ 1578 if (xfer->ux_hcflags & UXFER_ABORTING) { 1579 DPRINTFN(4, "already aborting", 0, 0, 0, 0); 1580 #ifdef DIAGNOSTIC 1581 if (status == USBD_TIMEOUT) 1582 DPRINTFN(4, "TIMEOUT while aborting", 0, 0, 0, 0); 1583 #endif 1584 /* Override the status which might be USBD_TIMEOUT. */ 1585 xfer->ux_status = status; 1586 DPRINTFN(4, "xfer %p waiting for abort to finish", xfer, 0, 0, 1587 0); 1588 xfer->ux_hcflags |= UXFER_ABORTWAIT; 1589 while (xfer->ux_hcflags & UXFER_ABORTING) 1590 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 1591 return; 1592 } 1593 xfer->ux_hcflags |= UXFER_ABORTING; 1594 1595 /* 1596 * Step 1: When cancelling a transfer make sure the timeout handler 1597 * didn't run or ran to the end and saw the USBD_CANCELLED status. 1598 * Otherwise we must have got here via a timeout. 1599 */ 1600 if (status == USBD_CANCELLED) { 1601 xfer->ux_status = status; 1602 callout_halt(&xfer->ux_callout, &sc->sc_lock); 1603 } else { 1604 KASSERT(xfer->ux_status == USBD_TIMEOUT); 1605 } 1606 1607 /* 1608 * Step 2: Stop execution of TD on the ring. 1609 */ 1610 switch (xhci_get_epstate(sc, xs, dci)) { 1611 case XHCI_EPSTATE_HALTED: 1612 (void)xhci_reset_endpoint_locked(xfer->ux_pipe); 1613 break; 1614 case XHCI_EPSTATE_STOPPED: 1615 break; 1616 default: 1617 (void)xhci_stop_endpoint(xfer->ux_pipe); 1618 break; 1619 } 1620 #ifdef DIAGNOSTIC 1621 uint32_t epst = xhci_get_epstate(sc, xs, dci); 1622 if (epst != XHCI_EPSTATE_STOPPED) 1623 DPRINTFN(4, "dci %u not stopped %u", dci, epst, 0, 0); 1624 #endif 1625 1626 /* 1627 * Step 3: Remove any vestiges of the xfer from the ring. 1628 */ 1629 xhci_set_dequeue_locked(xfer->ux_pipe); 1630 1631 /* 1632 * Step 4: Notify completion to waiting xfers. 1633 */ 1634 int wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 1635 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 1636 usb_transfer_complete(xfer); 1637 if (wake) { 1638 cv_broadcast(&xfer->ux_hccv); 1639 } 1640 DPRINTFN(14, "end", 0, 0, 0, 0); 1641 1642 KASSERT(mutex_owned(&sc->sc_lock)); 1643 } 1644 1645 static void 1646 xhci_host_dequeue(struct xhci_ring * const xr) 1647 { 1648 /* When dequeueing the controller, update our struct copy too */ 1649 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1650 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1651 BUS_DMASYNC_PREWRITE); 1652 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1653 1654 xr->xr_ep = 0; 1655 xr->xr_cs = 1; 1656 } 1657 1658 /* 1659 * Recover STALLed endpoint. 1660 * xHCI 1.1 sect 4.10.2.1 1661 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1662 * all transfers on transfer ring. 1663 * These are done in thread context asynchronously. 1664 */ 1665 static void 1666 xhci_clear_endpoint_stall_async_task(void *cookie) 1667 { 1668 struct usbd_xfer * const xfer = cookie; 1669 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1670 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1671 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1672 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1673 1674 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1675 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1676 1677 xhci_reset_endpoint(xfer->ux_pipe); 1678 xhci_set_dequeue(xfer->ux_pipe); 1679 1680 mutex_enter(&sc->sc_lock); 1681 tr->is_halted = false; 1682 usb_transfer_complete(xfer); 1683 mutex_exit(&sc->sc_lock); 1684 DPRINTFN(4, "ends", 0, 0, 0, 0); 1685 } 1686 1687 static usbd_status 1688 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1689 { 1690 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1691 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1692 1693 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1694 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1695 1696 if (sc->sc_dying) { 1697 return USBD_IOERROR; 1698 } 1699 1700 usb_init_task(&xp->xp_async_task, 1701 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1702 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1703 DPRINTFN(4, "ends", 0, 0, 0, 0); 1704 1705 return USBD_NORMAL_COMPLETION; 1706 } 1707 1708 /* Process roothub port status/change events and notify to uhub_intr. */ 1709 static void 1710 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1711 { 1712 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1713 uint8_t *p; 1714 1715 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1716 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1717 port, 0, 0); 1718 1719 if (xfer == NULL) 1720 return; 1721 1722 if (port > sc->sc_maxports) 1723 return; 1724 1725 p = xfer->ux_buf; 1726 memset(p, 0, xfer->ux_length); 1727 p[port/NBBY] |= 1 << (port%NBBY); 1728 xfer->ux_actlen = xfer->ux_length; 1729 xfer->ux_status = USBD_NORMAL_COMPLETION; 1730 usb_transfer_complete(xfer); 1731 } 1732 1733 /* Process Transfer Events */ 1734 static void 1735 xhci_event_transfer(struct xhci_softc * const sc, 1736 const struct xhci_trb * const trb) 1737 { 1738 uint64_t trb_0; 1739 uint32_t trb_2, trb_3; 1740 uint8_t trbcode; 1741 u_int slot, dci; 1742 struct xhci_slot *xs; 1743 struct xhci_ring *xr; 1744 struct xhci_xfer *xx; 1745 struct usbd_xfer *xfer; 1746 usbd_status err; 1747 1748 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1749 1750 trb_0 = le64toh(trb->trb_0); 1751 trb_2 = le32toh(trb->trb_2); 1752 trb_3 = le32toh(trb->trb_3); 1753 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1754 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1755 dci = XHCI_TRB_3_EP_GET(trb_3); 1756 xs = &sc->sc_slots[slot]; 1757 xr = &xs->xs_ep[dci].xe_tr; 1758 1759 /* sanity check */ 1760 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1761 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1762 1763 int idx = 0; 1764 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1765 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1766 DPRINTFN(0, "invalid trb_0 0x%"PRIx64, trb_0, 0, 0, 0); 1767 return; 1768 } 1769 xx = xr->xr_cookies[idx]; 1770 1771 /* clear cookie of consumed TRB */ 1772 xr->xr_cookies[idx] = NULL; 1773 1774 /* 1775 * xx is NULL if pipe is opened but xfer is not started. 1776 * It happens when stopping idle pipe. 1777 */ 1778 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1779 DPRINTFN(1, "Ignore #%u: cookie %p cc %u dci %u", 1780 idx, xx, trbcode, dci); 1781 DPRINTFN(1, " orig TRB %"PRIx64" type %u", trb_0, 1782 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1783 0, 0); 1784 return; 1785 } 1786 } else { 1787 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1788 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1789 } 1790 /* XXX this may not happen */ 1791 if (xx == NULL) { 1792 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1793 return; 1794 } 1795 xfer = &xx->xx_xfer; 1796 /* XXX this may happen when detaching */ 1797 if (xfer == NULL) { 1798 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1799 xx, trb_0, 0, 0); 1800 return; 1801 } 1802 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1803 /* XXX I dunno why this happens */ 1804 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1805 1806 if (!xfer->ux_pipe->up_repeat && 1807 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1808 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1809 return; 1810 } 1811 1812 /* 4.11.5.2 Event Data TRB */ 1813 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1814 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1815 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1816 if ((trb_0 & 0x3) == 0x3) { 1817 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1818 } 1819 } 1820 1821 switch (trbcode) { 1822 case XHCI_TRB_ERROR_SHORT_PKT: 1823 case XHCI_TRB_ERROR_SUCCESS: 1824 /* 1825 * A ctrl transfer can generate two events if it has a Data 1826 * stage. A short data stage can be OK and should not 1827 * complete the transfer as the status stage needs to be 1828 * performed. 1829 * 1830 * Note: Data and Status stage events point at same xfer. 1831 * ux_actlen and ux_dmabuf will be passed to 1832 * usb_transfer_complete after the Status stage event. 1833 * 1834 * It can be distingished which stage generates the event: 1835 * + by checking least 3 bits of trb_0 if ED==1. 1836 * (see xhci_device_ctrl_start). 1837 * + by checking the type of original TRB if ED==0. 1838 * 1839 * In addition, intr, bulk, and isoc transfer currently 1840 * consists of single TD, so the "skip" is not needed. 1841 * ctrl xfer uses EVENT_DATA, and others do not. 1842 * Thus driver can switch the flow by checking ED bit. 1843 */ 1844 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1845 if (xfer->ux_actlen == 0) 1846 xfer->ux_actlen = xfer->ux_length - 1847 XHCI_TRB_2_REM_GET(trb_2); 1848 if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)) 1849 == XHCI_TRB_TYPE_DATA_STAGE) { 1850 return; 1851 } 1852 } else if ((trb_0 & 0x3) == 0x3) { 1853 return; 1854 } 1855 err = USBD_NORMAL_COMPLETION; 1856 break; 1857 case XHCI_TRB_ERROR_STOPPED: 1858 case XHCI_TRB_ERROR_LENGTH: 1859 case XHCI_TRB_ERROR_STOPPED_SHORT: 1860 /* 1861 * don't complete the transfer being aborted 1862 * as abort_xfer does instead. 1863 */ 1864 if (xfer->ux_hcflags & UXFER_ABORTING) { 1865 DPRINTFN(14, "ignore aborting xfer %p", xfer, 0, 0, 0); 1866 return; 1867 } 1868 err = USBD_CANCELLED; 1869 break; 1870 case XHCI_TRB_ERROR_STALL: 1871 case XHCI_TRB_ERROR_BABBLE: 1872 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1873 xr->is_halted = true; 1874 err = USBD_STALLED; 1875 /* 1876 * Stalled endpoints can be recoverd by issuing 1877 * command TRB TYPE_RESET_EP on xHCI instead of 1878 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1879 * on the endpoint. However, this function may be 1880 * called from softint context (e.g. from umass), 1881 * in that case driver gets KASSERT in cv_timedwait 1882 * in xhci_do_command. 1883 * To avoid this, this runs reset_endpoint and 1884 * usb_transfer_complete in usb task thread 1885 * asynchronously (and then umass issues clear 1886 * UF_ENDPOINT_HALT). 1887 */ 1888 xfer->ux_status = err; 1889 callout_halt(&xfer->ux_callout, &sc->sc_lock); 1890 xhci_clear_endpoint_stall_async(xfer); 1891 return; 1892 default: 1893 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1894 err = USBD_IOERROR; 1895 break; 1896 } 1897 xfer->ux_status = err; 1898 1899 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1900 if ((trb_0 & 0x3) == 0x0) { 1901 callout_stop(&xfer->ux_callout); 1902 usb_transfer_complete(xfer); 1903 } 1904 } else { 1905 callout_stop(&xfer->ux_callout); 1906 usb_transfer_complete(xfer); 1907 } 1908 } 1909 1910 /* Process Command complete events */ 1911 static void 1912 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 1913 { 1914 uint64_t trb_0; 1915 uint32_t trb_2, trb_3; 1916 1917 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1918 1919 KASSERT(mutex_owned(&sc->sc_lock)); 1920 1921 trb_0 = le64toh(trb->trb_0); 1922 trb_2 = le32toh(trb->trb_2); 1923 trb_3 = le32toh(trb->trb_3); 1924 1925 if (trb_0 == sc->sc_command_addr) { 1926 sc->sc_resultpending = false; 1927 1928 sc->sc_result_trb.trb_0 = trb_0; 1929 sc->sc_result_trb.trb_2 = trb_2; 1930 sc->sc_result_trb.trb_3 = trb_3; 1931 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1932 XHCI_TRB_ERROR_SUCCESS) { 1933 DPRINTFN(1, "command completion " 1934 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1935 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1936 } 1937 cv_signal(&sc->sc_command_cv); 1938 } else { 1939 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 1940 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1941 trb_2, trb_3); 1942 } 1943 } 1944 1945 /* 1946 * Process events. 1947 * called from xhci_softintr 1948 */ 1949 static void 1950 xhci_handle_event(struct xhci_softc * const sc, 1951 const struct xhci_trb * const trb) 1952 { 1953 uint64_t trb_0; 1954 uint32_t trb_2, trb_3; 1955 1956 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1957 1958 trb_0 = le64toh(trb->trb_0); 1959 trb_2 = le32toh(trb->trb_2); 1960 trb_3 = le32toh(trb->trb_3); 1961 1962 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1963 trb, trb_0, trb_2, trb_3); 1964 1965 /* 1966 * 4.11.3.1, 6.4.2.1 1967 * TRB Pointer is invalid for these completion codes. 1968 */ 1969 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 1970 case XHCI_TRB_ERROR_RING_UNDERRUN: 1971 case XHCI_TRB_ERROR_RING_OVERRUN: 1972 case XHCI_TRB_ERROR_VF_RING_FULL: 1973 return; 1974 default: 1975 if (trb_0 == 0) { 1976 return; 1977 } 1978 break; 1979 } 1980 1981 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 1982 case XHCI_TRB_EVENT_TRANSFER: 1983 xhci_event_transfer(sc, trb); 1984 break; 1985 case XHCI_TRB_EVENT_CMD_COMPLETE: 1986 xhci_event_cmd(sc, trb); 1987 break; 1988 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1989 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1990 break; 1991 default: 1992 break; 1993 } 1994 } 1995 1996 static void 1997 xhci_softintr(void *v) 1998 { 1999 struct usbd_bus * const bus = v; 2000 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2001 struct xhci_ring * const er = &sc->sc_er; 2002 struct xhci_trb *trb; 2003 int i, j, k; 2004 2005 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2006 2007 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2008 2009 i = er->xr_ep; 2010 j = er->xr_cs; 2011 2012 DPRINTFN(16, "er: xr_ep %d xr_cs %d", i, j, 0, 0); 2013 2014 while (1) { 2015 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2016 BUS_DMASYNC_POSTREAD); 2017 trb = &er->xr_trb[i]; 2018 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2019 2020 if (j != k) 2021 break; 2022 2023 xhci_handle_event(sc, trb); 2024 2025 i++; 2026 if (i == er->xr_ntrb) { 2027 i = 0; 2028 j ^= 1; 2029 } 2030 } 2031 2032 er->xr_ep = i; 2033 er->xr_cs = j; 2034 2035 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2036 XHCI_ERDP_LO_BUSY); 2037 2038 DPRINTFN(16, "ends", 0, 0, 0, 0); 2039 2040 return; 2041 } 2042 2043 static void 2044 xhci_poll(struct usbd_bus *bus) 2045 { 2046 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2047 2048 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2049 2050 mutex_spin_enter(&sc->sc_intr_lock); 2051 xhci_intr1(sc); 2052 mutex_spin_exit(&sc->sc_intr_lock); 2053 2054 return; 2055 } 2056 2057 static struct usbd_xfer * 2058 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2059 { 2060 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2061 struct usbd_xfer *xfer; 2062 2063 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2064 2065 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 2066 if (xfer != NULL) { 2067 memset(xfer, 0, sizeof(struct xhci_xfer)); 2068 #ifdef DIAGNOSTIC 2069 xfer->ux_state = XFER_BUSY; 2070 #endif 2071 } 2072 2073 return xfer; 2074 } 2075 2076 static void 2077 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2078 { 2079 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2080 2081 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2082 2083 #ifdef DIAGNOSTIC 2084 if (xfer->ux_state != XFER_BUSY) { 2085 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 2086 xfer, xfer->ux_state, 0, 0); 2087 } 2088 xfer->ux_state = XFER_FREE; 2089 #endif 2090 pool_cache_put(sc->sc_xferpool, xfer); 2091 } 2092 2093 static void 2094 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2095 { 2096 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2097 2098 *lock = &sc->sc_lock; 2099 } 2100 2101 extern uint32_t usb_cookie_no; 2102 2103 /* 2104 * xHCI 4.3 2105 * Called when uhub_explore finds a new device (via usbd_new_device). 2106 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2107 * This function does: 2108 * Allocate and construct dev structure of default endpoint (ep0). 2109 * Allocate and open pipe of ep0. 2110 * Enable slot and initialize slot context. 2111 * Set Address. 2112 * Read initial device descriptor. 2113 * Determine initial MaxPacketSize (mps) by speed. 2114 * Read full device descriptor. 2115 * Register this device. 2116 * Finally state of device transitions ADDRESSED. 2117 */ 2118 static usbd_status 2119 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2120 int speed, int port, struct usbd_port *up) 2121 { 2122 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2123 struct usbd_device *dev; 2124 usbd_status err; 2125 usb_device_descriptor_t *dd; 2126 struct xhci_slot *xs; 2127 uint32_t *cp; 2128 2129 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2130 DPRINTFN(4, "port %u depth %u speed %u up %p", port, depth, speed, up); 2131 2132 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2133 if (dev == NULL) 2134 return USBD_NOMEM; 2135 2136 dev->ud_bus = bus; 2137 dev->ud_quirks = &usbd_no_quirk; 2138 dev->ud_addr = 0; 2139 dev->ud_ddesc.bMaxPacketSize = 0; 2140 dev->ud_depth = depth; 2141 dev->ud_powersrc = up; 2142 dev->ud_myhub = up->up_parent; 2143 dev->ud_speed = speed; 2144 dev->ud_langid = USBD_NOLANG; 2145 dev->ud_cookie.cookie = ++usb_cookie_no; 2146 2147 /* Set up default endpoint handle. */ 2148 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2149 /* doesn't matter, just don't let it uninitialized */ 2150 dev->ud_ep0.ue_toggle = 0; 2151 2152 /* Set up default endpoint descriptor. */ 2153 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2154 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2155 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2156 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2157 dev->ud_ep0desc.bInterval = 0; 2158 2159 /* 4.3, 4.8.2.1 */ 2160 switch (speed) { 2161 case USB_SPEED_SUPER: 2162 case USB_SPEED_SUPER_PLUS: 2163 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2164 break; 2165 case USB_SPEED_FULL: 2166 /* XXX using 64 as initial mps of ep0 in FS */ 2167 case USB_SPEED_HIGH: 2168 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2169 break; 2170 case USB_SPEED_LOW: 2171 default: 2172 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2173 break; 2174 } 2175 2176 up->up_dev = dev; 2177 2178 /* Establish the default pipe. */ 2179 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2180 &dev->ud_pipe0); 2181 if (err) { 2182 goto bad; 2183 } 2184 2185 dd = &dev->ud_ddesc; 2186 2187 if (depth == 0 && port == 0) { 2188 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2189 bus->ub_devices[dev->ud_addr] = dev; 2190 err = usbd_get_initial_ddesc(dev, dd); 2191 if (err) { 2192 DPRINTFN(1, "get_initial_ddesc %u", err, 0, 0, 0); 2193 goto bad; 2194 } 2195 2196 err = usbd_reload_device_desc(dev); 2197 if (err) { 2198 DPRINTFN(1, "reload desc %u", err, 0, 0, 0); 2199 goto bad; 2200 } 2201 } else { 2202 uint8_t slot = 0; 2203 2204 /* 4.3.2 */ 2205 err = xhci_enable_slot(sc, &slot); 2206 if (err) { 2207 DPRINTFN(1, "enable slot %u", err, 0, 0, 0); 2208 goto bad; 2209 } 2210 2211 xs = &sc->sc_slots[slot]; 2212 dev->ud_hcpriv = xs; 2213 2214 /* 4.3.3 initialize slot structure */ 2215 err = xhci_init_slot(dev, slot); 2216 if (err) { 2217 DPRINTFN(1, "init slot %u", err, 0, 0, 0); 2218 dev->ud_hcpriv = NULL; 2219 /* 2220 * We have to disable_slot here because 2221 * xs->xs_idx == 0 when xhci_init_slot fails, 2222 * in that case usbd_remove_dev won't work. 2223 */ 2224 mutex_enter(&sc->sc_lock); 2225 xhci_disable_slot(sc, slot); 2226 mutex_exit(&sc->sc_lock); 2227 goto bad; 2228 } 2229 2230 /* 4.3.4 Address Assignment */ 2231 err = xhci_set_address(dev, slot, false); 2232 if (err) { 2233 DPRINTFN(1, "set address w/o bsr %u", err, 0, 0, 0); 2234 goto bad; 2235 } 2236 2237 /* Allow device time to set new address */ 2238 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2239 2240 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2241 //hexdump("slot context", cp, sc->sc_ctxsz); 2242 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3])); 2243 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2244 /* XXX ensure we know when the hardware does something 2245 we can't yet cope with */ 2246 KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr); 2247 dev->ud_addr = addr; 2248 /* XXX dev->ud_addr not necessarily unique on bus */ 2249 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2250 bus->ub_devices[dev->ud_addr] = dev; 2251 2252 err = usbd_get_initial_ddesc(dev, dd); 2253 if (err) { 2254 DPRINTFN(1, "get_initial_ddesc %u", err, 0, 0, 0); 2255 goto bad; 2256 } 2257 2258 /* 4.8.2.1 */ 2259 if (USB_IS_SS(speed)) { 2260 if (dd->bMaxPacketSize != 9) { 2261 printf("%s: invalid mps 2^%u for SS ep0," 2262 " using 512\n", 2263 device_xname(sc->sc_dev), 2264 dd->bMaxPacketSize); 2265 dd->bMaxPacketSize = 9; 2266 } 2267 USETW(dev->ud_ep0desc.wMaxPacketSize, 2268 (1 << dd->bMaxPacketSize)); 2269 } else 2270 USETW(dev->ud_ep0desc.wMaxPacketSize, 2271 dd->bMaxPacketSize); 2272 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2273 err = xhci_update_ep0_mps(sc, xs, 2274 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2275 if (err) { 2276 DPRINTFN(1, "update mps of ep0 %u", err, 0, 0, 0); 2277 goto bad; 2278 } 2279 2280 err = usbd_reload_device_desc(dev); 2281 if (err) { 2282 DPRINTFN(1, "reload desc %u", err, 0, 0, 0); 2283 goto bad; 2284 } 2285 } 2286 2287 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2288 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2289 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2290 dd->bDeviceClass, dd->bDeviceSubClass, 2291 dd->bDeviceProtocol, 0); 2292 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2293 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2294 dev->ud_speed); 2295 2296 usbd_get_device_strings(dev); 2297 2298 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2299 2300 if (depth == 0 && port == 0) { 2301 usbd_attach_roothub(parent, dev); 2302 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2303 return USBD_NORMAL_COMPLETION; 2304 } 2305 2306 2307 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2308 bad: 2309 if (err != USBD_NORMAL_COMPLETION) { 2310 usbd_remove_device(dev, up); 2311 } 2312 2313 return err; 2314 } 2315 2316 static usbd_status 2317 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2318 size_t ntrb, size_t align) 2319 { 2320 usbd_status err; 2321 size_t size = ntrb * XHCI_TRB_SIZE; 2322 2323 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2324 2325 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2326 if (err) 2327 return err; 2328 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2329 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2330 xr->xr_trb = xhci_ring_trbv(xr, 0); 2331 xr->xr_ntrb = ntrb; 2332 xr->is_halted = false; 2333 xhci_host_dequeue(xr); 2334 2335 return USBD_NORMAL_COMPLETION; 2336 } 2337 2338 static void 2339 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2340 { 2341 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2342 mutex_destroy(&xr->xr_lock); 2343 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2344 } 2345 2346 static void 2347 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2348 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2349 { 2350 size_t i; 2351 u_int ri; 2352 u_int cs; 2353 uint64_t parameter; 2354 uint32_t status; 2355 uint32_t control; 2356 2357 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2358 2359 KASSERTMSG(ntrbs <= XHCI_XFER_NTRB, "ntrbs %zu", ntrbs); 2360 for (i = 0; i < ntrbs; i++) { 2361 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2362 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2363 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2364 KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2365 XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3); 2366 } 2367 2368 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2369 2370 ri = xr->xr_ep; 2371 cs = xr->xr_cs; 2372 2373 /* 2374 * Although the xhci hardware can do scatter/gather dma from 2375 * arbitrary sized buffers, there is a non-obvious restriction 2376 * that a LINK trb is only allowed at the end of a burst of 2377 * transfers - which might be 16kB. 2378 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2379 * The simple solution is not to allow a LINK trb in the middle 2380 * of anything - as here. 2381 * XXX: (dsl) There are xhci controllers out there (eg some made by 2382 * ASMedia) that seem to lock up if they process a LINK trb but 2383 * cannot process the linked-to trb yet. 2384 * The code should write the 'cycle' bit on the link trb AFTER 2385 * adding the other trb. 2386 */ 2387 u_int firstep = xr->xr_ep; 2388 u_int firstcs = xr->xr_cs; 2389 2390 for (i = 0; i < ntrbs; ) { 2391 u_int oldri = ri; 2392 u_int oldcs = cs; 2393 2394 if (ri >= (xr->xr_ntrb - 1)) { 2395 /* Put Link TD at the end of ring */ 2396 parameter = xhci_ring_trbp(xr, 0); 2397 status = 0; 2398 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2399 XHCI_TRB_3_TC_BIT; 2400 xr->xr_cookies[ri] = NULL; 2401 xr->xr_ep = 0; 2402 xr->xr_cs ^= 1; 2403 ri = xr->xr_ep; 2404 cs = xr->xr_cs; 2405 } else { 2406 parameter = trbs[i].trb_0; 2407 status = trbs[i].trb_2; 2408 control = trbs[i].trb_3; 2409 2410 xr->xr_cookies[ri] = cookie; 2411 ri++; 2412 i++; 2413 } 2414 /* 2415 * If this is a first TRB, mark it invalid to prevent 2416 * xHC from running it immediately. 2417 */ 2418 if (oldri == firstep) { 2419 if (oldcs) { 2420 control &= ~XHCI_TRB_3_CYCLE_BIT; 2421 } else { 2422 control |= XHCI_TRB_3_CYCLE_BIT; 2423 } 2424 } else { 2425 if (oldcs) { 2426 control |= XHCI_TRB_3_CYCLE_BIT; 2427 } else { 2428 control &= ~XHCI_TRB_3_CYCLE_BIT; 2429 } 2430 } 2431 xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control); 2432 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri, 2433 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2434 } 2435 2436 /* Now invert cycle bit of first TRB */ 2437 if (firstcs) { 2438 xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 2439 } else { 2440 xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 2441 } 2442 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep, 2443 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2444 2445 xr->xr_ep = ri; 2446 xr->xr_cs = cs; 2447 2448 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2449 } 2450 2451 /* 2452 * Stop execution commands, purge all commands on command ring, and 2453 * rewind dequeue pointer. 2454 */ 2455 static void 2456 xhci_abort_command(struct xhci_softc *sc) 2457 { 2458 struct xhci_ring * const cr = &sc->sc_cr; 2459 uint64_t crcr; 2460 int i; 2461 2462 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2463 DPRINTFN(14, "command %#"PRIx64" timeout, aborting", 2464 sc->sc_command_addr, 0, 0, 0); 2465 2466 mutex_enter(&cr->xr_lock); 2467 2468 /* 4.6.1.2 Aborting a Command */ 2469 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2470 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2471 2472 for (i = 0; i < 500; i++) { 2473 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2474 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2475 break; 2476 usb_delay_ms(&sc->sc_bus, 1); 2477 } 2478 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2479 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2480 /* reset HC here? */ 2481 } 2482 2483 /* reset command ring dequeue pointer */ 2484 cr->xr_ep = 0; 2485 cr->xr_cs = 1; 2486 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2487 2488 mutex_exit(&cr->xr_lock); 2489 } 2490 2491 /* 2492 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2493 * Command completion is notified by cv_signal from xhci_event_cmd() 2494 * (called from xhci_softint), or timed-out. 2495 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2496 * then do_command examines it. 2497 */ 2498 static usbd_status 2499 xhci_do_command_locked(struct xhci_softc * const sc, 2500 struct xhci_trb * const trb, int timeout) 2501 { 2502 struct xhci_ring * const cr = &sc->sc_cr; 2503 usbd_status err; 2504 2505 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2506 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2507 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2508 2509 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2510 KASSERT(mutex_owned(&sc->sc_lock)); 2511 2512 while (sc->sc_command_addr != 0) 2513 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 2514 2515 /* 2516 * If enqueue pointer points at last of ring, it's Link TRB, 2517 * command TRB will be stored in 0th TRB. 2518 */ 2519 if (cr->xr_ep == cr->xr_ntrb - 1) 2520 sc->sc_command_addr = xhci_ring_trbp(cr, 0); 2521 else 2522 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2523 2524 sc->sc_resultpending = true; 2525 2526 mutex_enter(&cr->xr_lock); 2527 xhci_ring_put(sc, cr, NULL, trb, 1); 2528 mutex_exit(&cr->xr_lock); 2529 2530 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2531 2532 while (sc->sc_resultpending) { 2533 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2534 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2535 xhci_abort_command(sc); 2536 err = USBD_TIMEOUT; 2537 goto timedout; 2538 } 2539 } 2540 2541 trb->trb_0 = sc->sc_result_trb.trb_0; 2542 trb->trb_2 = sc->sc_result_trb.trb_2; 2543 trb->trb_3 = sc->sc_result_trb.trb_3; 2544 2545 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2546 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2547 2548 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2549 case XHCI_TRB_ERROR_SUCCESS: 2550 err = USBD_NORMAL_COMPLETION; 2551 break; 2552 default: 2553 case 192 ... 223: 2554 err = USBD_IOERROR; 2555 break; 2556 case 224 ... 255: 2557 err = USBD_NORMAL_COMPLETION; 2558 break; 2559 } 2560 2561 timedout: 2562 sc->sc_resultpending = false; 2563 sc->sc_command_addr = 0; 2564 cv_broadcast(&sc->sc_cmdbusy_cv); 2565 2566 return err; 2567 } 2568 2569 static usbd_status 2570 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2571 int timeout) 2572 { 2573 2574 mutex_enter(&sc->sc_lock); 2575 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2576 mutex_exit(&sc->sc_lock); 2577 2578 return ret; 2579 } 2580 2581 static usbd_status 2582 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2583 { 2584 struct xhci_trb trb; 2585 usbd_status err; 2586 2587 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2588 2589 trb.trb_0 = 0; 2590 trb.trb_2 = 0; 2591 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2592 2593 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2594 if (err != USBD_NORMAL_COMPLETION) { 2595 return err; 2596 } 2597 2598 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2599 2600 return err; 2601 } 2602 2603 /* 2604 * xHCI 4.6.4 2605 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2606 * All endpoints in the slot should be stopped. 2607 * Should be called with sc_lock held. 2608 */ 2609 static usbd_status 2610 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2611 { 2612 struct xhci_trb trb; 2613 struct xhci_slot *xs; 2614 usbd_status err; 2615 2616 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2617 2618 if (sc->sc_dying) 2619 return USBD_IOERROR; 2620 2621 trb.trb_0 = 0; 2622 trb.trb_2 = 0; 2623 trb.trb_3 = htole32( 2624 XHCI_TRB_3_SLOT_SET(slot) | 2625 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2626 2627 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2628 2629 if (!err) { 2630 xs = &sc->sc_slots[slot]; 2631 if (xs->xs_idx != 0) { 2632 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2633 xhci_set_dcba(sc, 0, slot); 2634 memset(xs, 0, sizeof(*xs)); 2635 } 2636 } 2637 2638 return err; 2639 } 2640 2641 /* 2642 * Set address of device and transition slot state from ENABLED to ADDRESSED 2643 * if Block Setaddress Request (BSR) is false. 2644 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2645 * see xHCI 1.1 4.5.3, 3.3.4 2646 * Should be called without sc_lock held. 2647 */ 2648 static usbd_status 2649 xhci_address_device(struct xhci_softc * const sc, 2650 uint64_t icp, uint8_t slot_id, bool bsr) 2651 { 2652 struct xhci_trb trb; 2653 usbd_status err; 2654 2655 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2656 2657 trb.trb_0 = icp; 2658 trb.trb_2 = 0; 2659 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2660 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2661 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2662 2663 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2664 2665 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2666 err = USBD_NO_ADDR; 2667 2668 return err; 2669 } 2670 2671 static usbd_status 2672 xhci_update_ep0_mps(struct xhci_softc * const sc, 2673 struct xhci_slot * const xs, u_int mps) 2674 { 2675 struct xhci_trb trb; 2676 usbd_status err; 2677 uint32_t * cp; 2678 2679 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2680 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2681 2682 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2683 cp[0] = htole32(0); 2684 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2685 2686 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2687 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2688 2689 /* sync input contexts before they are read from memory */ 2690 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2691 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2692 sc->sc_ctxsz * 4); 2693 2694 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2695 trb.trb_2 = 0; 2696 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2697 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2698 2699 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2700 return err; 2701 } 2702 2703 static void 2704 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2705 { 2706 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2707 2708 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2709 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2710 &dcbaa[si], dcba, si, 0); 2711 2712 dcbaa[si] = htole64(dcba); 2713 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2714 BUS_DMASYNC_PREWRITE); 2715 } 2716 2717 /* 2718 * Allocate device and input context DMA buffer, and 2719 * TRB DMA buffer for each endpoint. 2720 */ 2721 static usbd_status 2722 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2723 { 2724 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2725 struct xhci_slot *xs; 2726 usbd_status err; 2727 u_int dci; 2728 2729 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2730 DPRINTFN(4, "slot %u", slot, 0, 0, 0); 2731 2732 xs = &sc->sc_slots[slot]; 2733 2734 /* allocate contexts */ 2735 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2736 &xs->xs_dc_dma); 2737 if (err) 2738 return err; 2739 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2740 2741 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2742 &xs->xs_ic_dma); 2743 if (err) 2744 goto bad1; 2745 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2746 2747 for (dci = 0; dci < 32; dci++) { 2748 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2749 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2750 if (dci == XHCI_DCI_SLOT) 2751 continue; 2752 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2753 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2754 if (err) { 2755 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2756 goto bad2; 2757 } 2758 } 2759 2760 bad2: 2761 if (err == USBD_NORMAL_COMPLETION) { 2762 xs->xs_idx = slot; 2763 } else { 2764 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2765 } 2766 2767 return err; 2768 2769 bad1: 2770 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2771 xs->xs_idx = 0; 2772 return err; 2773 } 2774 2775 static void 2776 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2777 int end_dci) 2778 { 2779 u_int dci; 2780 2781 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2782 DPRINTFN(4, "slot %u start %u end %u", xs->xs_idx, start_dci, end_dci, 2783 0); 2784 2785 for (dci = start_dci; dci < end_dci; dci++) { 2786 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2787 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2788 } 2789 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2790 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2791 xs->xs_idx = 0; 2792 } 2793 2794 /* 2795 * Setup slot context, set Device Context Base Address, and issue 2796 * Set Address Device command. 2797 */ 2798 static usbd_status 2799 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 2800 { 2801 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2802 struct xhci_slot *xs; 2803 usbd_status err; 2804 2805 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2806 DPRINTFN(4, "slot %u bsr %u", slot, bsr, 0, 0); 2807 2808 xs = &sc->sc_slots[slot]; 2809 2810 xhci_setup_ctx(dev->ud_pipe0); 2811 2812 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2813 sc->sc_ctxsz * 3); 2814 2815 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2816 2817 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 2818 2819 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2820 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2821 sc->sc_ctxsz * 2); 2822 2823 return err; 2824 } 2825 2826 /* 2827 * 4.8.2, 6.2.3.2 2828 * construct slot/endpoint context parameters and do syncmem 2829 */ 2830 static void 2831 xhci_setup_ctx(struct usbd_pipe *pipe) 2832 { 2833 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2834 struct usbd_device *dev = pipe->up_dev; 2835 struct xhci_slot * const xs = dev->ud_hcpriv; 2836 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2837 const u_int dci = xhci_ep_get_dci(ed); 2838 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2839 uint32_t *cp; 2840 uint16_t mps = UGETW(ed->wMaxPacketSize); 2841 uint8_t speed = dev->ud_speed; 2842 uint8_t ival = ed->bInterval; 2843 2844 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2845 DPRINTFN(4, "pipe %p: slot %u dci %u speed %u", pipe, xs->xs_idx, dci, 2846 speed); 2847 2848 /* set up initial input control context */ 2849 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2850 cp[0] = htole32(0); 2851 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 2852 if (dci == XHCI_DCI_EP_CONTROL) 2853 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2854 cp[7] = htole32(0); 2855 2856 /* set up input slot context */ 2857 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2858 cp[0] = 2859 XHCI_SCTX_0_CTX_NUM_SET(dci) | 2860 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 2861 cp[1] = 0; 2862 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2863 cp[3] = 0; 2864 xhci_setup_route(pipe, cp); 2865 xhci_setup_tthub(pipe, cp); 2866 2867 cp[0] = htole32(cp[0]); 2868 cp[1] = htole32(cp[1]); 2869 cp[2] = htole32(cp[2]); 2870 cp[3] = htole32(cp[3]); 2871 2872 /* set up input endpoint context */ 2873 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 2874 cp[0] = 2875 XHCI_EPCTX_0_EPSTATE_SET(0) | 2876 XHCI_EPCTX_0_MULT_SET(0) | 2877 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2878 XHCI_EPCTX_0_LSA_SET(0) | 2879 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 2880 cp[1] = 2881 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 2882 XHCI_EPCTX_1_HID_SET(0) | 2883 XHCI_EPCTX_1_MAXB_SET(0); 2884 2885 if (xfertype != UE_ISOCHRONOUS) 2886 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 2887 2888 if (xfertype == UE_CONTROL) 2889 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 2890 else if (USB_IS_SS(speed)) 2891 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 2892 else 2893 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 2894 2895 xhci_setup_maxburst(pipe, cp); 2896 2897 switch (xfertype) { 2898 case UE_CONTROL: 2899 break; 2900 case UE_BULK: 2901 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 2902 break; 2903 case UE_INTERRUPT: 2904 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 2905 ival = pipe->up_interval; 2906 2907 ival = xhci_bival2ival(ival, speed); 2908 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 2909 break; 2910 case UE_ISOCHRONOUS: 2911 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 2912 ival = pipe->up_interval; 2913 2914 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 2915 if (speed == USB_SPEED_FULL) 2916 ival += 3; /* 1ms -> 125us */ 2917 ival--; 2918 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 2919 break; 2920 default: 2921 break; 2922 } 2923 DPRINTFN(4, "setting ival %u MaxBurst %#x", 2924 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 2925 2926 /* rewind TR dequeue pointer in xHC */ 2927 /* can't use xhci_ep_get_dci() yet? */ 2928 *(uint64_t *)(&cp[2]) = htole64( 2929 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 2930 XHCI_EPCTX_2_DCS_SET(1)); 2931 2932 cp[0] = htole32(cp[0]); 2933 cp[1] = htole32(cp[1]); 2934 cp[4] = htole32(cp[4]); 2935 2936 /* rewind TR dequeue pointer in driver */ 2937 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 2938 mutex_enter(&xr->xr_lock); 2939 xhci_host_dequeue(xr); 2940 mutex_exit(&xr->xr_lock); 2941 2942 /* sync input contexts before they are read from memory */ 2943 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2944 } 2945 2946 /* 2947 * Setup route string and roothub port of given device for slot context 2948 */ 2949 static void 2950 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 2951 { 2952 struct usbd_device *dev = pipe->up_dev; 2953 struct usbd_port *up = dev->ud_powersrc; 2954 struct usbd_device *hub; 2955 struct usbd_device *adev; 2956 uint8_t rhport = 0; 2957 uint32_t route = 0; 2958 2959 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2960 2961 /* Locate root hub port and Determine route string */ 2962 /* 4.3.3 route string does not include roothub port */ 2963 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2964 uint32_t dep; 2965 2966 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2967 hub, hub->ud_depth, hub->ud_powersrc, 2968 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2969 2970 if (hub->ud_powersrc == NULL) 2971 break; 2972 dep = hub->ud_depth; 2973 if (dep == 0) 2974 break; 2975 rhport = hub->ud_powersrc->up_portno; 2976 if (dep > USB_HUB_MAX_DEPTH) 2977 continue; 2978 2979 route |= 2980 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2981 << ((dep - 1) * 4); 2982 } 2983 route = route >> 4; 2984 DPRINTFN(4, "rhport %u Route %05x hub %p", rhport, route, hub, 0); 2985 2986 /* Locate port on upstream high speed hub */ 2987 for (adev = dev, hub = up->up_parent; 2988 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2989 adev = hub, hub = hub->ud_myhub) 2990 ; 2991 if (hub) { 2992 int p; 2993 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2994 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2995 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2996 goto found; 2997 } 2998 } 2999 panic("xhci_setup_route: cannot find HS port"); 3000 found: 3001 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 3002 } else { 3003 dev->ud_myhsport = NULL; 3004 } 3005 3006 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 3007 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(rhport); 3008 } 3009 3010 /* 3011 * Setup whether device is hub, whether device uses MTT, and 3012 * TT informations if it uses MTT. 3013 */ 3014 static void 3015 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 3016 { 3017 struct usbd_device *dev = pipe->up_dev; 3018 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 3019 uint32_t speed = dev->ud_speed; 3020 uint8_t tthubslot, ttportnum; 3021 bool ishub; 3022 bool usemtt; 3023 3024 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3025 3026 /* 3027 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 3028 * tthubslot: 3029 * This is the slot ID of parent HS hub 3030 * if LS/FS device is connected && connected through HS hub. 3031 * This is 0 if device is not LS/FS device || 3032 * parent hub is not HS hub || 3033 * attached to root hub. 3034 * ttportnum: 3035 * This is the downstream facing port of parent HS hub 3036 * if LS/FS device is connected. 3037 * This is 0 if device is not LS/FS device || 3038 * parent hub is not HS hub || 3039 * attached to root hub. 3040 */ 3041 if (dev->ud_myhsport != NULL && 3042 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3043 (dev->ud_myhub != NULL && 3044 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3045 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 3046 ttportnum = dev->ud_myhsport->up_portno; 3047 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 3048 } else { 3049 ttportnum = 0; 3050 tthubslot = 0; 3051 } 3052 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 3053 dev->ud_myhsport, ttportnum, tthubslot, 0); 3054 3055 /* ishub is valid after reading UDESC_DEVICE */ 3056 ishub = (dd->bDeviceClass == UDCLASS_HUB); 3057 3058 /* dev->ud_hub is valid after reading UDESC_HUB */ 3059 if (ishub && dev->ud_hub) { 3060 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 3061 uint8_t ttt = 3062 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 3063 3064 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 3065 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 3066 DPRINTFN(4, "nports=%d ttt=%d", hd->bNbrPorts, ttt, 0, 0); 3067 } 3068 3069 #define IS_TTHUB(dd) \ 3070 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 3071 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 3072 3073 /* 3074 * MTT flag is set if 3075 * 1. this is HS hub && MTT is enabled 3076 * or 3077 * 2. this is not hub && this is LS or FS device && 3078 * MTT of parent HS hub (and its parent, too) is enabled 3079 */ 3080 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 3081 usemtt = true; 3082 else if (!ishub && 3083 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 3084 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3085 (dev->ud_myhub != NULL && 3086 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3087 dev->ud_myhsport != NULL && 3088 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 3089 usemtt = true; 3090 else 3091 usemtt = false; 3092 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 3093 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 3094 3095 #undef IS_TTHUB 3096 3097 cp[0] |= 3098 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 3099 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 3100 cp[2] |= 3101 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 3102 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 3103 } 3104 3105 /* set up params for periodic endpoint */ 3106 static void 3107 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 3108 { 3109 struct usbd_device *dev = pipe->up_dev; 3110 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3111 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3112 usbd_desc_iter_t iter; 3113 const usb_cdc_descriptor_t *cdcd; 3114 uint32_t maxb = 0; 3115 uint16_t mps = UGETW(ed->wMaxPacketSize); 3116 uint8_t speed = dev->ud_speed; 3117 uint8_t ep; 3118 3119 /* config desc is NULL when opening ep0 */ 3120 if (dev == NULL || dev->ud_cdesc == NULL) 3121 goto no_cdcd; 3122 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 3123 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 3124 if (cdcd == NULL) 3125 goto no_cdcd; 3126 usb_desc_iter_init(dev, &iter); 3127 iter.cur = (const void *)cdcd; 3128 3129 /* find endpoint_ss_comp desc for ep of this pipe */ 3130 for (ep = 0;;) { 3131 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 3132 if (cdcd == NULL) 3133 break; 3134 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 3135 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 3136 bEndpointAddress; 3137 if (UE_GET_ADDR(ep) == 3138 UE_GET_ADDR(ed->bEndpointAddress)) { 3139 cdcd = (const usb_cdc_descriptor_t *) 3140 usb_desc_iter_next(&iter); 3141 break; 3142 } 3143 ep = 0; 3144 } 3145 } 3146 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 3147 const usb_endpoint_ss_comp_descriptor_t * esscd = 3148 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3149 maxb = esscd->bMaxBurst; 3150 } 3151 3152 no_cdcd: 3153 /* 6.2.3.4, 4.8.2.4 */ 3154 if (USB_IS_SS(speed)) { 3155 /* USB 3.1 9.6.6 */ 3156 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3157 /* USB 3.1 9.6.7 */ 3158 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3159 #ifdef notyet 3160 if (xfertype == UE_ISOCHRONOUS) { 3161 } 3162 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3163 /* use ESIT */ 3164 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3165 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3166 3167 /* XXX if LEC = 1, set ESIT instead */ 3168 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3169 } else { 3170 /* use ival */ 3171 } 3172 #endif 3173 } else { 3174 /* USB 2.0 9.6.6 */ 3175 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3176 3177 /* 6.2.3.4 */ 3178 if (speed == USB_SPEED_HIGH && 3179 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3180 maxb = UE_GET_TRANS(mps); 3181 } else { 3182 /* LS/FS or HS CTRL or HS BULK */ 3183 maxb = 0; 3184 } 3185 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3186 } 3187 } 3188 3189 /* 3190 * Convert endpoint bInterval value to endpoint context interval value 3191 * for Interrupt pipe. 3192 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3193 */ 3194 static uint32_t 3195 xhci_bival2ival(uint32_t ival, uint32_t speed) 3196 { 3197 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3198 int i; 3199 3200 /* 3201 * round ival down to "the nearest base 2 multiple of 3202 * bInterval * 8". 3203 * bInterval is at most 255 as its type is uByte. 3204 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3205 */ 3206 for (i = 10; i > 0; i--) { 3207 if ((ival * 8) >= (1 << i)) 3208 break; 3209 } 3210 ival = i; 3211 } else { 3212 /* Interval = bInterval-1 for SS/HS */ 3213 ival--; 3214 } 3215 3216 return ival; 3217 } 3218 3219 /* ----- */ 3220 3221 static void 3222 xhci_noop(struct usbd_pipe *pipe) 3223 { 3224 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3225 } 3226 3227 /* 3228 * Process root hub request. 3229 */ 3230 static int 3231 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3232 void *buf, int buflen) 3233 { 3234 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3235 usb_port_status_t ps; 3236 int l, totlen = 0; 3237 uint16_t len, value, index; 3238 int port, i; 3239 uint32_t v; 3240 3241 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3242 3243 if (sc->sc_dying) 3244 return -1; 3245 3246 len = UGETW(req->wLength); 3247 value = UGETW(req->wValue); 3248 index = UGETW(req->wIndex); 3249 3250 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 3251 req->bmRequestType | (req->bRequest << 8), value, index, len); 3252 3253 #define C(x,y) ((x) | ((y) << 8)) 3254 switch (C(req->bRequest, req->bmRequestType)) { 3255 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3256 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 3257 if (len == 0) 3258 break; 3259 switch (value) { 3260 case C(0, UDESC_DEVICE): { 3261 usb_device_descriptor_t devd; 3262 totlen = min(buflen, sizeof(devd)); 3263 memcpy(&devd, buf, totlen); 3264 USETW(devd.idVendor, sc->sc_id_vendor); 3265 memcpy(buf, &devd, totlen); 3266 break; 3267 } 3268 #define sd ((usb_string_descriptor_t *)buf) 3269 case C(1, UDESC_STRING): 3270 /* Vendor */ 3271 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3272 break; 3273 case C(2, UDESC_STRING): 3274 /* Product */ 3275 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3276 break; 3277 #undef sd 3278 default: 3279 /* default from usbroothub */ 3280 return buflen; 3281 } 3282 break; 3283 3284 /* Hub requests */ 3285 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3286 break; 3287 /* Clear Port Feature request */ 3288 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3289 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 3290 index, value, 0, 0); 3291 if (index < 1 || index > sc->sc_maxports) { 3292 return -1; 3293 } 3294 port = XHCI_PORTSC(index); 3295 v = xhci_op_read_4(sc, port); 3296 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3297 v &= ~XHCI_PS_CLEAR; 3298 switch (value) { 3299 case UHF_PORT_ENABLE: 3300 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3301 break; 3302 case UHF_PORT_SUSPEND: 3303 return -1; 3304 case UHF_PORT_POWER: 3305 break; 3306 case UHF_PORT_TEST: 3307 case UHF_PORT_INDICATOR: 3308 return -1; 3309 case UHF_C_PORT_CONNECTION: 3310 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3311 break; 3312 case UHF_C_PORT_ENABLE: 3313 case UHF_C_PORT_SUSPEND: 3314 case UHF_C_PORT_OVER_CURRENT: 3315 return -1; 3316 case UHF_C_BH_PORT_RESET: 3317 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3318 break; 3319 case UHF_C_PORT_RESET: 3320 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3321 break; 3322 case UHF_C_PORT_LINK_STATE: 3323 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3324 break; 3325 case UHF_C_PORT_CONFIG_ERROR: 3326 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3327 break; 3328 default: 3329 return -1; 3330 } 3331 break; 3332 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3333 if (len == 0) 3334 break; 3335 if ((value & 0xff) != 0) { 3336 return -1; 3337 } 3338 usb_hub_descriptor_t hubd; 3339 3340 totlen = min(buflen, sizeof(hubd)); 3341 memcpy(&hubd, buf, totlen); 3342 hubd.bNbrPorts = sc->sc_maxports; 3343 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3344 hubd.bPwrOn2PwrGood = 200; 3345 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 3346 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 3347 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3348 totlen = min(totlen, hubd.bDescLength); 3349 memcpy(buf, &hubd, totlen); 3350 break; 3351 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3352 if (len != 4) { 3353 return -1; 3354 } 3355 memset(buf, 0, len); /* ? XXX */ 3356 totlen = len; 3357 break; 3358 /* Get Port Status request */ 3359 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3360 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 3361 if (index < 1 || index > sc->sc_maxports) { 3362 return -1; 3363 } 3364 if (len != 4) { 3365 return -1; 3366 } 3367 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 3368 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 3369 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3370 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3371 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3372 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3373 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3374 if (v & XHCI_PS_PR) i |= UPS_RESET; 3375 if (v & XHCI_PS_PP) { 3376 if (i & UPS_OTHER_SPEED) 3377 i |= UPS_PORT_POWER_SS; 3378 else 3379 i |= UPS_PORT_POWER; 3380 } 3381 if (i & UPS_OTHER_SPEED) 3382 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3383 if (sc->sc_vendor_port_status) 3384 i = sc->sc_vendor_port_status(sc, v, i); 3385 USETW(ps.wPortStatus, i); 3386 i = 0; 3387 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3388 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3389 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3390 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3391 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3392 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3393 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3394 USETW(ps.wPortChange, i); 3395 totlen = min(len, sizeof(ps)); 3396 memcpy(buf, &ps, totlen); 3397 break; 3398 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3399 return -1; 3400 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3401 break; 3402 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3403 break; 3404 /* Set Port Feature request */ 3405 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3406 int optval = (index >> 8) & 0xff; 3407 index &= 0xff; 3408 if (index < 1 || index > sc->sc_maxports) { 3409 return -1; 3410 } 3411 port = XHCI_PORTSC(index); 3412 v = xhci_op_read_4(sc, port); 3413 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3414 v &= ~XHCI_PS_CLEAR; 3415 switch (value) { 3416 case UHF_PORT_ENABLE: 3417 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3418 break; 3419 case UHF_PORT_SUSPEND: 3420 /* XXX suspend */ 3421 break; 3422 case UHF_PORT_RESET: 3423 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3424 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3425 /* Wait for reset to complete. */ 3426 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3427 if (sc->sc_dying) { 3428 return -1; 3429 } 3430 v = xhci_op_read_4(sc, port); 3431 if (v & XHCI_PS_PR) { 3432 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3433 usb_delay_ms(&sc->sc_bus, 10); 3434 /* XXX */ 3435 } 3436 break; 3437 case UHF_PORT_POWER: 3438 /* XXX power control */ 3439 break; 3440 /* XXX more */ 3441 case UHF_C_PORT_RESET: 3442 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3443 break; 3444 case UHF_PORT_U1_TIMEOUT: 3445 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3446 return -1; 3447 } 3448 port = XHCI_PORTPMSC(index); 3449 v = xhci_op_read_4(sc, port); 3450 v &= ~XHCI_PM3_U1TO_SET(0xff); 3451 v |= XHCI_PM3_U1TO_SET(optval); 3452 xhci_op_write_4(sc, port, v); 3453 break; 3454 case UHF_PORT_U2_TIMEOUT: 3455 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3456 return -1; 3457 } 3458 port = XHCI_PORTPMSC(index); 3459 v = xhci_op_read_4(sc, port); 3460 v &= ~XHCI_PM3_U2TO_SET(0xff); 3461 v |= XHCI_PM3_U2TO_SET(optval); 3462 xhci_op_write_4(sc, port, v); 3463 break; 3464 default: 3465 return -1; 3466 } 3467 } 3468 break; 3469 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3470 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3471 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3472 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3473 break; 3474 default: 3475 /* default from usbroothub */ 3476 return buflen; 3477 } 3478 3479 return totlen; 3480 } 3481 3482 /* root hub interrupt */ 3483 3484 static usbd_status 3485 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3486 { 3487 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3488 usbd_status err; 3489 3490 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3491 3492 /* Insert last in queue. */ 3493 mutex_enter(&sc->sc_lock); 3494 err = usb_insert_transfer(xfer); 3495 mutex_exit(&sc->sc_lock); 3496 if (err) 3497 return err; 3498 3499 /* Pipe isn't running, start first */ 3500 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3501 } 3502 3503 /* Wait for roothub port status/change */ 3504 static usbd_status 3505 xhci_root_intr_start(struct usbd_xfer *xfer) 3506 { 3507 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3508 3509 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3510 3511 if (sc->sc_dying) 3512 return USBD_IOERROR; 3513 3514 mutex_enter(&sc->sc_lock); 3515 sc->sc_intrxfer = xfer; 3516 mutex_exit(&sc->sc_lock); 3517 3518 return USBD_IN_PROGRESS; 3519 } 3520 3521 static void 3522 xhci_root_intr_abort(struct usbd_xfer *xfer) 3523 { 3524 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3525 3526 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3527 3528 KASSERT(mutex_owned(&sc->sc_lock)); 3529 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3530 3531 sc->sc_intrxfer = NULL; 3532 3533 xfer->ux_status = USBD_CANCELLED; 3534 usb_transfer_complete(xfer); 3535 } 3536 3537 static void 3538 xhci_root_intr_close(struct usbd_pipe *pipe) 3539 { 3540 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3541 3542 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3543 3544 KASSERT(mutex_owned(&sc->sc_lock)); 3545 3546 sc->sc_intrxfer = NULL; 3547 } 3548 3549 static void 3550 xhci_root_intr_done(struct usbd_xfer *xfer) 3551 { 3552 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3553 3554 } 3555 3556 /* -------------- */ 3557 /* device control */ 3558 3559 static usbd_status 3560 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3561 { 3562 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3563 usbd_status err; 3564 3565 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3566 3567 /* Insert last in queue. */ 3568 mutex_enter(&sc->sc_lock); 3569 err = usb_insert_transfer(xfer); 3570 mutex_exit(&sc->sc_lock); 3571 if (err) 3572 return err; 3573 3574 /* Pipe isn't running, start first */ 3575 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3576 } 3577 3578 static usbd_status 3579 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3580 { 3581 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3582 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3583 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3584 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3585 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3586 usb_device_request_t * const req = &xfer->ux_request; 3587 const int isread = usbd_xfer_isread(xfer); 3588 const uint32_t len = UGETW(req->wLength); 3589 usb_dma_t * const dma = &xfer->ux_dmabuf; 3590 uint64_t parameter; 3591 uint32_t status; 3592 uint32_t control; 3593 u_int i; 3594 3595 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3596 DPRINTFN(12, "req: %04x %04x %04x %04x", 3597 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3598 UGETW(req->wIndex), UGETW(req->wLength)); 3599 3600 /* we rely on the bottom bits for extra info */ 3601 KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx", 3602 (uintptr_t) xfer); 3603 3604 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3605 3606 i = 0; 3607 3608 /* setup phase */ 3609 memcpy(¶meter, req, sizeof(parameter)); 3610 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3611 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3612 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3613 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3614 XHCI_TRB_3_IDT_BIT; 3615 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3616 3617 if (len != 0) { 3618 /* data phase */ 3619 parameter = DMAADDR(dma, 0); 3620 KASSERTMSG(len <= 0x10000, "len %d", len); 3621 status = XHCI_TRB_2_IRQ_SET(0) | 3622 XHCI_TRB_2_TDSZ_SET(1) | 3623 XHCI_TRB_2_BYTES_SET(len); 3624 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3625 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3626 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3627 XHCI_TRB_3_IOC_BIT; 3628 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3629 } 3630 3631 parameter = 0; 3632 status = XHCI_TRB_2_IRQ_SET(0); 3633 /* the status stage has inverted direction */ 3634 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3635 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3636 XHCI_TRB_3_IOC_BIT; 3637 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3638 3639 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3640 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3641 xhci_timeout, xfer); 3642 } 3643 xfer->ux_status = USBD_IN_PROGRESS; 3644 3645 mutex_enter(&tr->xr_lock); 3646 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3647 mutex_exit(&tr->xr_lock); 3648 3649 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3650 3651 return USBD_IN_PROGRESS; 3652 } 3653 3654 static void 3655 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3656 { 3657 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3658 usb_device_request_t *req = &xfer->ux_request; 3659 int len = UGETW(req->wLength); 3660 int rd = req->bmRequestType & UT_READ; 3661 3662 if (len) 3663 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3664 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3665 } 3666 3667 static void 3668 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3669 { 3670 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3671 3672 xhci_abort_xfer(xfer, USBD_CANCELLED); 3673 } 3674 3675 static void 3676 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3677 { 3678 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3679 3680 xhci_close_pipe(pipe); 3681 } 3682 3683 /* ------------------ */ 3684 /* device isochronous */ 3685 3686 /* ----------- */ 3687 /* device bulk */ 3688 3689 static usbd_status 3690 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3691 { 3692 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3693 usbd_status err; 3694 3695 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3696 3697 /* Insert last in queue. */ 3698 mutex_enter(&sc->sc_lock); 3699 err = usb_insert_transfer(xfer); 3700 mutex_exit(&sc->sc_lock); 3701 if (err) 3702 return err; 3703 3704 /* 3705 * Pipe isn't running (otherwise err would be USBD_INPROG), 3706 * so start it first. 3707 */ 3708 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3709 } 3710 3711 static usbd_status 3712 xhci_device_bulk_start(struct usbd_xfer *xfer) 3713 { 3714 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3715 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3716 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3717 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3718 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3719 const uint32_t len = xfer->ux_length; 3720 usb_dma_t * const dma = &xfer->ux_dmabuf; 3721 uint64_t parameter; 3722 uint32_t status; 3723 uint32_t control; 3724 u_int i = 0; 3725 3726 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3727 3728 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3729 3730 if (sc->sc_dying) 3731 return USBD_IOERROR; 3732 3733 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3734 3735 parameter = DMAADDR(dma, 0); 3736 /* 3737 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3738 * If the user supplied buffer crosses such a boundary then 2 3739 * (or more) TRB should be used. 3740 * If multiple TRB are used the td_size field must be set correctly. 3741 * For v1.0 devices (like ivy bridge) this is the number of usb data 3742 * blocks needed to complete the transfer. 3743 * Setting it to 1 in the last TRB causes an extra zero-length 3744 * data block be sent. 3745 * The earlier documentation differs, I don't know how it behaves. 3746 */ 3747 KASSERTMSG(len <= 0x10000, "len %d", len); 3748 status = XHCI_TRB_2_IRQ_SET(0) | 3749 XHCI_TRB_2_TDSZ_SET(1) | 3750 XHCI_TRB_2_BYTES_SET(len); 3751 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3752 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3753 XHCI_TRB_3_IOC_BIT; 3754 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3755 3756 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3757 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3758 xhci_timeout, xfer); 3759 } 3760 xfer->ux_status = USBD_IN_PROGRESS; 3761 3762 mutex_enter(&tr->xr_lock); 3763 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3764 mutex_exit(&tr->xr_lock); 3765 3766 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3767 3768 return USBD_IN_PROGRESS; 3769 } 3770 3771 static void 3772 xhci_device_bulk_done(struct usbd_xfer *xfer) 3773 { 3774 #ifdef USB_DEBUG 3775 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3776 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3777 #endif 3778 const int isread = usbd_xfer_isread(xfer); 3779 3780 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3781 3782 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3783 3784 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3785 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3786 } 3787 3788 static void 3789 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3790 { 3791 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3792 3793 xhci_abort_xfer(xfer, USBD_CANCELLED); 3794 } 3795 3796 static void 3797 xhci_device_bulk_close(struct usbd_pipe *pipe) 3798 { 3799 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3800 3801 xhci_close_pipe(pipe); 3802 } 3803 3804 /* ---------------- */ 3805 /* device interrupt */ 3806 3807 static usbd_status 3808 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3809 { 3810 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3811 usbd_status err; 3812 3813 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3814 3815 /* Insert last in queue. */ 3816 mutex_enter(&sc->sc_lock); 3817 err = usb_insert_transfer(xfer); 3818 mutex_exit(&sc->sc_lock); 3819 if (err) 3820 return err; 3821 3822 /* 3823 * Pipe isn't running (otherwise err would be USBD_INPROG), 3824 * so start it first. 3825 */ 3826 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3827 } 3828 3829 static usbd_status 3830 xhci_device_intr_start(struct usbd_xfer *xfer) 3831 { 3832 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3833 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3834 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3835 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3836 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3837 const uint32_t len = xfer->ux_length; 3838 usb_dma_t * const dma = &xfer->ux_dmabuf; 3839 uint64_t parameter; 3840 uint32_t status; 3841 uint32_t control; 3842 u_int i = 0; 3843 3844 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3845 3846 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3847 3848 if (sc->sc_dying) 3849 return USBD_IOERROR; 3850 3851 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3852 3853 parameter = DMAADDR(dma, 0); 3854 KASSERTMSG(len <= 0x10000, "len %d", len); 3855 status = XHCI_TRB_2_IRQ_SET(0) | 3856 XHCI_TRB_2_TDSZ_SET(1) | 3857 XHCI_TRB_2_BYTES_SET(len); 3858 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3859 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3860 XHCI_TRB_3_IOC_BIT; 3861 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3862 3863 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3864 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3865 xhci_timeout, xfer); 3866 } 3867 xfer->ux_status = USBD_IN_PROGRESS; 3868 3869 mutex_enter(&tr->xr_lock); 3870 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3871 mutex_exit(&tr->xr_lock); 3872 3873 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3874 3875 return USBD_IN_PROGRESS; 3876 } 3877 3878 static void 3879 xhci_device_intr_done(struct usbd_xfer *xfer) 3880 { 3881 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3882 #ifdef USB_DEBUG 3883 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3884 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3885 #endif 3886 const int isread = usbd_xfer_isread(xfer); 3887 3888 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3889 3890 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3891 3892 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3893 3894 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3895 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3896 } 3897 3898 static void 3899 xhci_device_intr_abort(struct usbd_xfer *xfer) 3900 { 3901 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3902 3903 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3904 3905 KASSERT(mutex_owned(&sc->sc_lock)); 3906 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3907 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3908 xhci_abort_xfer(xfer, USBD_CANCELLED); 3909 } 3910 3911 static void 3912 xhci_device_intr_close(struct usbd_pipe *pipe) 3913 { 3914 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3915 3916 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3917 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3918 3919 xhci_close_pipe(pipe); 3920 } 3921 3922 /* ------------ */ 3923 3924 static void 3925 xhci_timeout(void *addr) 3926 { 3927 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3928 struct xhci_xfer * const xx = addr; 3929 struct usbd_xfer * const xfer = &xx->xx_xfer; 3930 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3931 bool timeout = false; 3932 3933 mutex_enter(&sc->sc_lock); 3934 if (sc->sc_dying) { 3935 mutex_exit(&sc->sc_lock); 3936 return; 3937 } 3938 if (xfer->ux_status != USBD_CANCELLED) { 3939 xfer->ux_status = USBD_TIMEOUT; 3940 timeout = true; 3941 } 3942 mutex_exit(&sc->sc_lock); 3943 3944 if (timeout) { 3945 struct usbd_device *dev = xfer->ux_pipe->up_dev; 3946 3947 /* Execute the abort in a process context. */ 3948 usb_init_task(&xfer->ux_aborttask, xhci_timeout_task, xfer, 3949 USB_TASKQ_MPSAFE); 3950 usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC); 3951 } 3952 } 3953 3954 static void 3955 xhci_timeout_task(void *addr) 3956 { 3957 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3958 struct usbd_xfer * const xfer = addr; 3959 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3960 3961 mutex_enter(&sc->sc_lock); 3962 KASSERT(xfer->ux_status == USBD_TIMEOUT); 3963 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3964 mutex_exit(&sc->sc_lock); 3965 } 3966
Indexes created Wed Oct 01 18:09:54 GMT 2025