xhci.c revision 1.28.2.8
1 /* $NetBSD: xhci.c,v 1.28.2.8 2014/12/03 14:18:07 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.28.2.8 2014/12/03 14:18:07 skrll Exp $"); 31 32 #include "opt_usb.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/kmem.h> 38 #include <sys/malloc.h> 39 #include <sys/device.h> 40 #include <sys/select.h> 41 #include <sys/proc.h> 42 #include <sys/queue.h> 43 #include <sys/mutex.h> 44 #include <sys/condvar.h> 45 #include <sys/bus.h> 46 #include <sys/cpu.h> 47 #include <sys/sysctl.h> 48 49 #include <machine/endian.h> 50 51 #include <dev/usb/usb.h> 52 #include <dev/usb/usbdi.h> 53 #include <dev/usb/usbdivar.h> 54 #include <dev/usb/usbhist.h> 55 #include <dev/usb/usb_mem.h> 56 #include <dev/usb/usb_quirks.h> 57 58 #include <dev/usb/xhcireg.h> 59 #include <dev/usb/xhcivar.h> 60 #include <dev/usb/usbroothub_subr.h> 61 62 63 #ifdef USB_DEBUG 64 #ifndef XHCI_DEBUG 65 #define xhcidebug 0 66 #else 67 static int xhcidebug = 0; 68 69 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 70 { 71 int err; 72 const struct sysctlnode *rnode; 73 const struct sysctlnode *cnode; 74 75 err = sysctl_createv(clog, 0, NULL, &rnode, 76 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 77 SYSCTL_DESCR("xhci global controls"), 78 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 79 80 if (err) 81 goto fail; 82 83 /* control debugging printfs */ 84 err = sysctl_createv(clog, 0, &rnode, &cnode, 85 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 86 "debug", SYSCTL_DESCR("Enable debugging output"), 87 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 88 if (err) 89 goto fail; 90 91 return; 92 fail: 93 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 94 } 95 96 #endif /* XHCI_DEBUG */ 97 #endif /* USB_DEBUG */ 98 99 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 100 #define XHCIHIST_FUNC() USBHIST_FUNC() 101 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 102 103 #define XHCI_DCI_SLOT 0 104 #define XHCI_DCI_EP_CONTROL 1 105 106 #define XHCI_ICI_INPUT_CONTROL 0 107 108 struct xhci_pipe { 109 struct usbd_pipe xp_pipe; 110 }; 111 112 #define XHCI_INTR_ENDPT 1 113 #define XHCI_COMMAND_RING_TRBS 256 114 #define XHCI_EVENT_RING_TRBS 256 115 #define XHCI_EVENT_RING_SEGMENTS 1 116 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 117 118 static usbd_status xhci_open(usbd_pipe_handle); 119 static int xhci_intr1(struct xhci_softc * const); 120 static void xhci_softintr(void *); 121 static void xhci_poll(struct usbd_bus *); 122 static usbd_xfer_handle xhci_allocx(struct usbd_bus *); 123 static void xhci_freex(struct usbd_bus *, usbd_xfer_handle); 124 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 125 static usbd_status xhci_new_device(device_t, usbd_bus_handle, int, int, int, 126 struct usbd_port *); 127 128 static usbd_status xhci_configure_endpoint(usbd_pipe_handle); 129 static usbd_status xhci_unconfigure_endpoint(usbd_pipe_handle); 130 static usbd_status xhci_reset_endpoint(usbd_pipe_handle); 131 //static usbd_status xhci_stop_endpoint(usbd_pipe_handle); 132 133 static usbd_status xhci_set_dequeue(usbd_pipe_handle); 134 135 static usbd_status xhci_do_command(struct xhci_softc * const, 136 struct xhci_trb * const, int); 137 static usbd_status xhci_init_slot(struct xhci_softc * const, uint32_t, 138 int, int, int, int); 139 static usbd_status xhci_enable_slot(struct xhci_softc * const, 140 uint8_t * const); 141 static usbd_status xhci_address_device(struct xhci_softc * const, 142 uint64_t, uint8_t, bool); 143 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 144 struct xhci_slot * const, u_int); 145 static usbd_status xhci_ring_init(struct xhci_softc * const, 146 struct xhci_ring * const, size_t, size_t); 147 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 148 149 static void xhci_noop(usbd_pipe_handle); 150 151 static usbd_status xhci_root_ctrl_transfer(usbd_xfer_handle); 152 static usbd_status xhci_root_ctrl_start(usbd_xfer_handle); 153 static void xhci_root_ctrl_abort(usbd_xfer_handle); 154 static void xhci_root_ctrl_close(usbd_pipe_handle); 155 static void xhci_root_ctrl_done(usbd_xfer_handle); 156 157 static usbd_status xhci_root_intr_transfer(usbd_xfer_handle); 158 static usbd_status xhci_root_intr_start(usbd_xfer_handle); 159 static void xhci_root_intr_abort(usbd_xfer_handle); 160 static void xhci_root_intr_close(usbd_pipe_handle); 161 static void xhci_root_intr_done(usbd_xfer_handle); 162 163 static usbd_status xhci_device_ctrl_transfer(usbd_xfer_handle); 164 static usbd_status xhci_device_ctrl_start(usbd_xfer_handle); 165 static void xhci_device_ctrl_abort(usbd_xfer_handle); 166 static void xhci_device_ctrl_close(usbd_pipe_handle); 167 static void xhci_device_ctrl_done(usbd_xfer_handle); 168 169 static usbd_status xhci_device_intr_transfer(usbd_xfer_handle); 170 static usbd_status xhci_device_intr_start(usbd_xfer_handle); 171 static void xhci_device_intr_abort(usbd_xfer_handle); 172 static void xhci_device_intr_close(usbd_pipe_handle); 173 static void xhci_device_intr_done(usbd_xfer_handle); 174 175 static usbd_status xhci_device_bulk_transfer(usbd_xfer_handle); 176 static usbd_status xhci_device_bulk_start(usbd_xfer_handle); 177 static void xhci_device_bulk_abort(usbd_xfer_handle); 178 static void xhci_device_bulk_close(usbd_pipe_handle); 179 static void xhci_device_bulk_done(usbd_xfer_handle); 180 181 static void xhci_timeout(void *); 182 static void xhci_timeout_task(void *); 183 184 static const struct usbd_bus_methods xhci_bus_methods = { 185 .ubm_open = xhci_open, 186 .ubm_softint = xhci_softintr, 187 .ubm_dopoll = xhci_poll, 188 .ubm_allocx = xhci_allocx, 189 .ubm_freex = xhci_freex, 190 .ubm_getlock = xhci_get_lock, 191 .ubm_newdev = xhci_new_device, 192 }; 193 194 static const struct usbd_pipe_methods xhci_root_ctrl_methods = { 195 .upm_transfer = xhci_root_ctrl_transfer, 196 .upm_start = xhci_root_ctrl_start, 197 .upm_abort = xhci_root_ctrl_abort, 198 .upm_close = xhci_root_ctrl_close, 199 .upm_cleartoggle = xhci_noop, 200 .upm_done = xhci_root_ctrl_done, 201 }; 202 203 static const struct usbd_pipe_methods xhci_root_intr_methods = { 204 .upm_transfer = xhci_root_intr_transfer, 205 .upm_start = xhci_root_intr_start, 206 .upm_abort = xhci_root_intr_abort, 207 .upm_close = xhci_root_intr_close, 208 .upm_cleartoggle = xhci_noop, 209 .upm_done = xhci_root_intr_done, 210 }; 211 212 213 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 214 .upm_transfer = xhci_device_ctrl_transfer, 215 .upm_start = xhci_device_ctrl_start, 216 .upm_abort = xhci_device_ctrl_abort, 217 .upm_close = xhci_device_ctrl_close, 218 .upm_cleartoggle = xhci_noop, 219 .upm_done = xhci_device_ctrl_done, 220 }; 221 222 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 223 .upm_cleartoggle = xhci_noop, 224 }; 225 226 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 227 .upm_transfer = xhci_device_bulk_transfer, 228 .upm_start = xhci_device_bulk_start, 229 .upm_abort = xhci_device_bulk_abort, 230 .upm_close = xhci_device_bulk_close, 231 .upm_cleartoggle = xhci_noop, 232 .upm_done = xhci_device_bulk_done, 233 }; 234 235 static const struct usbd_pipe_methods xhci_device_intr_methods = { 236 .upm_transfer = xhci_device_intr_transfer, 237 .upm_start = xhci_device_intr_start, 238 .upm_abort = xhci_device_intr_abort, 239 .upm_close = xhci_device_intr_close, 240 .upm_cleartoggle = xhci_noop, 241 .upm_done = xhci_device_intr_done, 242 }; 243 244 static inline uint32_t 245 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 246 { 247 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 248 } 249 250 #if 0 /* unused */ 251 static inline void 252 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 253 uint32_t value) 254 { 255 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 256 } 257 #endif /* unused */ 258 259 static inline uint32_t 260 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 261 { 262 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 263 } 264 265 static inline uint32_t 266 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 267 { 268 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 269 } 270 271 static inline void 272 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 273 uint32_t value) 274 { 275 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 276 } 277 278 #if 0 /* unused */ 279 static inline uint64_t 280 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 281 { 282 uint64_t value; 283 284 if (sc->sc_ac64) { 285 #ifdef XHCI_USE_BUS_SPACE_8 286 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 287 #else 288 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 289 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 290 offset + 4) << 32; 291 #endif 292 } else { 293 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 294 } 295 296 return value; 297 } 298 #endif /* unused */ 299 300 static inline void 301 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 302 uint64_t value) 303 { 304 if (sc->sc_ac64) { 305 #ifdef XHCI_USE_BUS_SPACE_8 306 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 307 #else 308 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 309 (value >> 0) & 0xffffffff); 310 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 311 (value >> 32) & 0xffffffff); 312 #endif 313 } else { 314 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 315 } 316 } 317 318 static inline uint32_t 319 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 320 { 321 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 322 } 323 324 static inline void 325 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 326 uint32_t value) 327 { 328 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 329 } 330 331 #if 0 /* unused */ 332 static inline uint64_t 333 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 334 { 335 uint64_t value; 336 337 if (sc->sc_ac64) { 338 #ifdef XHCI_USE_BUS_SPACE_8 339 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 340 #else 341 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 342 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 343 offset + 4) << 32; 344 #endif 345 } else { 346 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 347 } 348 349 return value; 350 } 351 #endif /* unused */ 352 353 static inline void 354 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 355 uint64_t value) 356 { 357 if (sc->sc_ac64) { 358 #ifdef XHCI_USE_BUS_SPACE_8 359 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 360 #else 361 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 362 (value >> 0) & 0xffffffff); 363 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 364 (value >> 32) & 0xffffffff); 365 #endif 366 } else { 367 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 368 } 369 } 370 371 #if 0 /* unused */ 372 static inline uint32_t 373 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 374 { 375 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 376 } 377 #endif /* unused */ 378 379 static inline void 380 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 381 uint32_t value) 382 { 383 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 384 } 385 386 /* --- */ 387 388 static inline uint8_t 389 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 390 { 391 u_int eptype; 392 393 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 394 case UE_CONTROL: 395 eptype = 0x0; 396 break; 397 case UE_ISOCHRONOUS: 398 eptype = 0x1; 399 break; 400 case UE_BULK: 401 eptype = 0x2; 402 break; 403 case UE_INTERRUPT: 404 eptype = 0x3; 405 break; 406 } 407 408 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 409 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 410 return eptype | 0x4; 411 else 412 return eptype; 413 } 414 415 static u_int 416 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 417 { 418 /* xHCI 1.0 section 4.5.1 */ 419 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 420 u_int in = 0; 421 422 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 423 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 424 in = 1; 425 426 return epaddr * 2 + in; 427 } 428 429 static inline u_int 430 xhci_dci_to_ici(const u_int i) 431 { 432 return i + 1; 433 } 434 435 static inline void * 436 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 437 const u_int dci) 438 { 439 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 440 } 441 442 #if 0 /* unused */ 443 static inline bus_addr_t 444 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 445 const u_int dci) 446 { 447 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 448 } 449 #endif /* unused */ 450 451 static inline void * 452 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 453 const u_int ici) 454 { 455 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 456 } 457 458 static inline bus_addr_t 459 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 460 const u_int ici) 461 { 462 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 463 } 464 465 static inline struct xhci_trb * 466 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 467 { 468 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 469 } 470 471 static inline bus_addr_t 472 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 473 { 474 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 475 } 476 477 static inline void 478 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 479 uint32_t control) 480 { 481 trb->trb_0 = parameter; 482 trb->trb_2 = status; 483 trb->trb_3 = control; 484 } 485 486 /* --- */ 487 488 void 489 xhci_childdet(device_t self, device_t child) 490 { 491 struct xhci_softc * const sc = device_private(self); 492 493 KASSERT(sc->sc_child == child); 494 if (child == sc->sc_child) 495 sc->sc_child = NULL; 496 } 497 498 int 499 xhci_detach(struct xhci_softc *sc, int flags) 500 { 501 int rv = 0; 502 503 if (sc->sc_child != NULL) 504 rv = config_detach(sc->sc_child, flags); 505 506 if (rv != 0) 507 return (rv); 508 509 /* XXX unconfigure/free slots */ 510 511 /* verify: */ 512 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 513 xhci_op_write_4(sc, XHCI_USBCMD, 0); 514 /* do we need to wait for stop? */ 515 516 xhci_op_write_8(sc, XHCI_CRCR, 0); 517 xhci_ring_free(sc, &sc->sc_cr); 518 cv_destroy(&sc->sc_command_cv); 519 520 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 521 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 522 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 523 xhci_ring_free(sc, &sc->sc_er); 524 525 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 526 527 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 528 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 529 530 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 531 532 mutex_destroy(&sc->sc_lock); 533 mutex_destroy(&sc->sc_intr_lock); 534 535 pool_cache_destroy(sc->sc_xferpool); 536 537 return rv; 538 } 539 540 int 541 xhci_activate(device_t self, enum devact act) 542 { 543 struct xhci_softc * const sc = device_private(self); 544 545 switch (act) { 546 case DVACT_DEACTIVATE: 547 sc->sc_dying = true; 548 return 0; 549 default: 550 return EOPNOTSUPP; 551 } 552 } 553 554 bool 555 xhci_suspend(device_t dv, const pmf_qual_t *qual) 556 { 557 return false; 558 } 559 560 bool 561 xhci_resume(device_t dv, const pmf_qual_t *qual) 562 { 563 return false; 564 } 565 566 bool 567 xhci_shutdown(device_t self, int flags) 568 { 569 return false; 570 } 571 572 573 static void 574 hexdump(const char *msg, const void *base, size_t len) 575 { 576 #if 0 577 size_t cnt; 578 const uint32_t *p; 579 extern paddr_t vtophys(vaddr_t); 580 581 p = base; 582 cnt = 0; 583 584 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 585 (void *)vtophys((vaddr_t)base)); 586 587 while (cnt < len) { 588 if (cnt % 16 == 0) 589 printf("%p: ", p); 590 else if (cnt % 8 == 0) 591 printf(" |"); 592 printf(" %08x", *p++); 593 cnt += 4; 594 if (cnt % 16 == 0) 595 printf("\n"); 596 } 597 #endif 598 } 599 600 601 int 602 xhci_init(struct xhci_softc *sc) 603 { 604 bus_size_t bsz; 605 uint32_t cap, hcs1, hcs2, hcc, dboff, rtsoff; 606 uint32_t ecp, ecr; 607 uint32_t usbcmd, usbsts, pagesize, config; 608 int i; 609 uint16_t hciversion; 610 uint8_t caplength; 611 612 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 613 614 /* XXX Low/Full/High speeds for now */ 615 sc->sc_bus.ub_revision = USBREV_2_0; 616 sc->sc_bus.ub_usedma = true; 617 618 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 619 caplength = XHCI_CAP_CAPLENGTH(cap); 620 hciversion = XHCI_CAP_HCIVERSION(cap); 621 622 if ((hciversion < 0x0096) || (hciversion > 0x0100)) { 623 aprint_normal_dev(sc->sc_dev, 624 "xHCI version %x.%x not known to be supported\n", 625 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 626 } else { 627 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 628 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 629 } 630 631 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 632 &sc->sc_cbh) != 0) { 633 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 634 return ENOMEM; 635 } 636 637 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 638 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 639 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 640 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 641 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 642 (void)xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 643 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 644 645 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 646 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 647 aprint_debug_dev(sc->sc_dev, "ac64 %d ctxsz %d\n", sc->sc_ac64, 648 sc->sc_ctxsz); 649 650 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 651 ecp = XHCI_HCC_XECP(hcc) * 4; 652 while (ecp != 0) { 653 ecr = xhci_read_4(sc, ecp); 654 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 655 switch (XHCI_XECP_ID(ecr)) { 656 case XHCI_ID_PROTOCOLS: { 657 uint32_t w0, w4, w8; 658 uint16_t w2; 659 w0 = xhci_read_4(sc, ecp + 0); 660 w2 = (w0 >> 16) & 0xffff; 661 w4 = xhci_read_4(sc, ecp + 4); 662 w8 = xhci_read_4(sc, ecp + 8); 663 aprint_debug_dev(sc->sc_dev, "SP: %08x %08x %08x\n", 664 w0, w4, w8); 665 if (w4 == 0x20425355 && w2 == 0x0300) { 666 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 667 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 668 } 669 if (w4 == 0x20425355 && w2 == 0x0200) { 670 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 671 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 672 } 673 break; 674 } 675 default: 676 break; 677 } 678 ecr = xhci_read_4(sc, ecp); 679 if (XHCI_XECP_NEXT(ecr) == 0) { 680 ecp = 0; 681 } else { 682 ecp += XHCI_XECP_NEXT(ecr) * 4; 683 } 684 } 685 686 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 687 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 688 &sc->sc_obh) != 0) { 689 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 690 return ENOMEM; 691 } 692 693 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 694 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 695 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 696 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 697 return ENOMEM; 698 } 699 700 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 701 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 702 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 703 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 704 return ENOMEM; 705 } 706 707 for (i = 0; i < 100; i++) { 708 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 709 if ((usbsts & XHCI_STS_CNR) == 0) 710 break; 711 usb_delay_ms(&sc->sc_bus, 1); 712 } 713 if (i >= 100) 714 return EIO; 715 716 usbcmd = 0; 717 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 718 usb_delay_ms(&sc->sc_bus, 1); 719 720 usbcmd = XHCI_CMD_HCRST; 721 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 722 for (i = 0; i < 100; i++) { 723 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 724 if ((usbcmd & XHCI_CMD_HCRST) == 0) 725 break; 726 usb_delay_ms(&sc->sc_bus, 1); 727 } 728 if (i >= 100) 729 return EIO; 730 731 for (i = 0; i < 100; i++) { 732 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 733 if ((usbsts & XHCI_STS_CNR) == 0) 734 break; 735 usb_delay_ms(&sc->sc_bus, 1); 736 } 737 if (i >= 100) 738 return EIO; 739 740 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 741 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 742 pagesize = ffs(pagesize); 743 if (pagesize == 0) 744 return EIO; 745 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 746 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 747 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 748 (uint32_t)sc->sc_maxslots); 749 750 usbd_status err; 751 752 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 753 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 754 if (sc->sc_maxspbuf != 0) { 755 err = usb_allocmem(&sc->sc_bus, 756 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 757 &sc->sc_spbufarray_dma); 758 if (err) 759 return err; 760 761 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * sc->sc_maxspbuf, KM_SLEEP); 762 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 763 for (i = 0; i < sc->sc_maxspbuf; i++) { 764 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 765 /* allocate contexts */ 766 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 767 sc->sc_pgsz, dma); 768 if (err) 769 return err; 770 spbufarray[i] = htole64(DMAADDR(dma, 0)); 771 usb_syncmem(dma, 0, sc->sc_pgsz, 772 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 773 } 774 775 usb_syncmem(&sc->sc_spbufarray_dma, 0, 776 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 777 } 778 779 config = xhci_op_read_4(sc, XHCI_CONFIG); 780 config &= ~0xFF; 781 config |= sc->sc_maxslots & 0xFF; 782 xhci_op_write_4(sc, XHCI_CONFIG, config); 783 784 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 785 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 786 if (err) { 787 aprint_error_dev(sc->sc_dev, "command ring init fail\n"); 788 return err; 789 } 790 791 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 792 XHCI_EVENT_RING_SEGMENTS_ALIGN); 793 if (err) { 794 aprint_error_dev(sc->sc_dev, "event ring init fail\n"); 795 return err; 796 } 797 798 usb_dma_t *dma; 799 size_t size; 800 size_t align; 801 802 dma = &sc->sc_eventst_dma; 803 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 804 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 805 KASSERT(size <= (512 * 1024)); 806 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 807 err = usb_allocmem(&sc->sc_bus, size, align, dma); 808 809 memset(KERNADDR(dma, 0), 0, size); 810 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 811 aprint_debug_dev(sc->sc_dev, "eventst: %s %016jx %p %zx\n", 812 usbd_errstr(err), 813 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 814 KERNADDR(&sc->sc_eventst_dma, 0), 815 sc->sc_eventst_dma.udma_block->size); 816 817 dma = &sc->sc_dcbaa_dma; 818 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 819 KASSERT(size <= 2048); 820 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 821 err = usb_allocmem(&sc->sc_bus, size, align, dma); 822 823 memset(KERNADDR(dma, 0), 0, size); 824 if (sc->sc_maxspbuf != 0) { 825 /* 826 * DCBA entry 0 hold the scratchbuf array pointer. 827 */ 828 *(uint64_t *)KERNADDR(dma, 0) = 829 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 830 } 831 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 832 aprint_debug_dev(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n", 833 usbd_errstr(err), 834 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 835 KERNADDR(&sc->sc_dcbaa_dma, 0), 836 sc->sc_dcbaa_dma.udma_block->size); 837 838 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 839 KM_SLEEP); 840 841 cv_init(&sc->sc_command_cv, "xhcicmd"); 842 843 struct xhci_erste *erst; 844 erst = KERNADDR(&sc->sc_eventst_dma, 0); 845 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 846 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 847 erst[0].erste_3 = htole32(0); 848 usb_syncmem(&sc->sc_eventst_dma, 0, 849 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 850 851 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 852 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 853 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 854 XHCI_ERDP_LO_BUSY); 855 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 856 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 857 sc->sc_cr.xr_cs); 858 859 #if 0 860 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 861 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 862 #endif 863 864 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 865 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 866 867 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 868 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 869 xhci_op_read_4(sc, XHCI_USBCMD)); 870 871 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 872 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 873 cv_init(&sc->sc_softwake_cv, "xhciab"); 874 875 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 876 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 877 878 /* Set up the bus struct. */ 879 sc->sc_bus.ub_methods = &xhci_bus_methods; 880 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 881 882 return USBD_NORMAL_COMPLETION; 883 } 884 885 int 886 xhci_intr(void *v) 887 { 888 struct xhci_softc * const sc = v; 889 int ret = 0; 890 891 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 892 893 if (sc == NULL) 894 return 0; 895 896 mutex_spin_enter(&sc->sc_intr_lock); 897 898 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 899 goto done; 900 901 /* If we get an interrupt while polling, then just ignore it. */ 902 if (sc->sc_bus.ub_usepolling) { 903 #ifdef DIAGNOSTIC 904 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 905 #endif 906 goto done; 907 } 908 909 ret = xhci_intr1(sc); 910 done: 911 mutex_spin_exit(&sc->sc_intr_lock); 912 return ret; 913 } 914 915 int 916 xhci_intr1(struct xhci_softc * const sc) 917 { 918 uint32_t usbsts; 919 uint32_t iman; 920 921 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 922 923 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 924 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 925 #if 0 926 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 927 return 0; 928 } 929 #endif 930 xhci_op_write_4(sc, XHCI_USBSTS, 931 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 932 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 933 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 934 935 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 936 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 937 if ((iman & XHCI_IMAN_INTR_PEND) == 0) { 938 return 0; 939 } 940 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 941 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 942 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 943 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 944 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 945 946 usb_schedsoftintr(&sc->sc_bus); 947 948 return 1; 949 } 950 951 static usbd_status 952 xhci_configure_endpoint(usbd_pipe_handle pipe) 953 { 954 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 955 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 956 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 957 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 958 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 959 struct xhci_trb trb; 960 usbd_status err; 961 uint32_t *cp; 962 963 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 964 DPRINTFN(4, "dci %u epaddr 0x%02x attr 0x%02x", 965 dci, ed->bEndpointAddress, ed->bmAttributes, 0); 966 967 /* XXX ensure input context is available? */ 968 969 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 970 971 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 972 cp[0] = htole32(0); 973 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 974 975 /* set up input slot context */ 976 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 977 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 978 cp[1] = htole32(0); 979 cp[2] = htole32(0); 980 cp[3] = htole32(0); 981 982 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 983 if (xfertype == UE_INTERRUPT) { 984 cp[0] = htole32( 985 XHCI_EPCTX_0_IVAL_SET(3) /* XXX */ 986 ); 987 cp[1] = htole32( 988 XHCI_EPCTX_1_CERR_SET(3) | 989 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(pipe->up_endpoint->ue_edesc)) | 990 XHCI_EPCTX_1_MAXB_SET(0) | 991 XHCI_EPCTX_1_MAXP_SIZE_SET(8) /* XXX */ 992 ); 993 cp[4] = htole32( 994 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 995 ); 996 } else { 997 cp[0] = htole32(0); 998 cp[1] = htole32( 999 XHCI_EPCTX_1_CERR_SET(3) | 1000 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(pipe->up_endpoint->ue_edesc)) | 1001 XHCI_EPCTX_1_MAXB_SET(0) | 1002 XHCI_EPCTX_1_MAXP_SIZE_SET(512) /* XXX */ 1003 ); 1004 } 1005 *(uint64_t *)(&cp[2]) = htole64( 1006 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 1007 XHCI_EPCTX_2_DCS_SET(1)); 1008 1009 /* sync input contexts before they are read from memory */ 1010 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1011 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1012 sc->sc_ctxsz * 1); 1013 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1014 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1015 1016 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1017 trb.trb_2 = 0; 1018 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1019 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1020 1021 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1022 1023 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1024 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1025 sc->sc_ctxsz * 1); 1026 1027 return err; 1028 } 1029 1030 static usbd_status 1031 xhci_unconfigure_endpoint(usbd_pipe_handle pipe) 1032 { 1033 #ifdef USB_DEBUG 1034 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1035 #endif 1036 1037 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1038 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1039 1040 return USBD_NORMAL_COMPLETION; 1041 } 1042 1043 static usbd_status 1044 xhci_reset_endpoint(usbd_pipe_handle pipe) 1045 { 1046 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1047 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1048 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1049 struct xhci_trb trb; 1050 usbd_status err; 1051 1052 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1053 DPRINTFN(4, "dci %u", dci, 0, 0, 0); 1054 1055 trb.trb_0 = 0; 1056 trb.trb_2 = 0; 1057 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1058 XHCI_TRB_3_EP_SET(dci) | 1059 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1060 1061 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1062 1063 return err; 1064 } 1065 1066 #if 0 1067 static usbd_status 1068 xhci_stop_endpoint(usbd_pipe_handle pipe) 1069 { 1070 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1071 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1072 struct xhci_trb trb; 1073 usbd_status err; 1074 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1075 1076 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1077 DPRINTFN(4, "dci %u", dci, 0, 0, 0); 1078 1079 trb.trb_0 = 0; 1080 trb.trb_2 = 0; 1081 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1082 XHCI_TRB_3_EP_SET(dci) | 1083 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1084 1085 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1086 1087 return err; 1088 } 1089 #endif 1090 1091 static usbd_status 1092 xhci_set_dequeue(usbd_pipe_handle pipe) 1093 { 1094 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 1095 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1096 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1097 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1098 struct xhci_trb trb; 1099 usbd_status err; 1100 1101 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1102 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1103 1104 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1105 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1106 BUS_DMASYNC_PREWRITE); 1107 1108 xr->xr_ep = 0; 1109 xr->xr_cs = 1; 1110 1111 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1112 trb.trb_2 = 0; 1113 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1114 XHCI_TRB_3_EP_SET(dci) | 1115 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1116 1117 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1118 1119 return err; 1120 } 1121 1122 static usbd_status 1123 xhci_open(usbd_pipe_handle pipe) 1124 { 1125 usbd_device_handle const dev = pipe->up_dev; 1126 struct xhci_softc * const sc = dev->ud_bus->ub_hcpriv; 1127 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1128 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1129 1130 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1131 DPRINTFN(1, "addr %d depth %d port %d speed %d", 1132 dev->ud_addr, dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1133 1134 if (sc->sc_dying) 1135 return USBD_IOERROR; 1136 1137 /* Root Hub */ 1138 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0 && 1139 dev->ud_speed != USB_SPEED_SUPER) { 1140 switch (ed->bEndpointAddress) { 1141 case USB_CONTROL_ENDPOINT: 1142 pipe->up_methods = &xhci_root_ctrl_methods; 1143 break; 1144 case UE_DIR_IN | XHCI_INTR_ENDPT: 1145 pipe->up_methods = &xhci_root_intr_methods; 1146 break; 1147 default: 1148 pipe->up_methods = NULL; 1149 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1150 ed->bEndpointAddress, 0, 0, 0); 1151 return USBD_INVAL; 1152 } 1153 return USBD_NORMAL_COMPLETION; 1154 } 1155 1156 switch (xfertype) { 1157 case UE_CONTROL: 1158 pipe->up_methods = &xhci_device_ctrl_methods; 1159 break; 1160 case UE_ISOCHRONOUS: 1161 pipe->up_methods = &xhci_device_isoc_methods; 1162 return USBD_INVAL; 1163 break; 1164 case UE_BULK: 1165 pipe->up_methods = &xhci_device_bulk_methods; 1166 break; 1167 case UE_INTERRUPT: 1168 pipe->up_methods = &xhci_device_intr_methods; 1169 break; 1170 default: 1171 return USBD_IOERROR; 1172 break; 1173 } 1174 1175 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1176 xhci_configure_endpoint(pipe); 1177 1178 return USBD_NORMAL_COMPLETION; 1179 } 1180 1181 static void 1182 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1183 { 1184 usbd_xfer_handle const xfer = sc->sc_intrxfer; 1185 uint8_t *p; 1186 1187 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1188 DPRINTFN(4, "port %u status change", port, 0, 0, 0); 1189 1190 if (xfer == NULL) 1191 return; 1192 1193 if (!(port >= sc->sc_hs_port_start && 1194 port < sc->sc_hs_port_start + sc->sc_hs_port_count)) 1195 return; 1196 1197 port -= sc->sc_hs_port_start; 1198 port += 1; 1199 DPRINTFN(4, "hs port %u status change", port, 0, 0, 0); 1200 1201 p = xfer->ux_buf; 1202 memset(p, 0, xfer->ux_length); 1203 p[port/NBBY] |= 1 << (port%NBBY); 1204 xfer->ux_actlen = xfer->ux_length; 1205 xfer->ux_status = USBD_NORMAL_COMPLETION; 1206 usb_transfer_complete(xfer); 1207 } 1208 1209 static void 1210 xhci_handle_event(struct xhci_softc * const sc, 1211 const struct xhci_trb * const trb) 1212 { 1213 uint64_t trb_0; 1214 uint32_t trb_2, trb_3; 1215 1216 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1217 1218 trb_0 = le64toh(trb->trb_0); 1219 trb_2 = le32toh(trb->trb_2); 1220 trb_3 = le32toh(trb->trb_3); 1221 1222 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1223 trb, trb_0, trb_2, trb_3); 1224 1225 switch (XHCI_TRB_3_TYPE_GET(trb_3)){ 1226 case XHCI_TRB_EVENT_TRANSFER: { 1227 u_int slot, dci; 1228 struct xhci_slot *xs; 1229 struct xhci_ring *xr; 1230 struct xhci_xfer *xx; 1231 usbd_xfer_handle xfer; 1232 usbd_status err; 1233 1234 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1235 dci = XHCI_TRB_3_EP_GET(trb_3); 1236 1237 xs = &sc->sc_slots[slot]; 1238 xr = &xs->xs_ep[dci].xe_tr; 1239 1240 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1241 xx = xr->xr_cookies[(trb_0 - xhci_ring_trbp(xr, 0))/ 1242 sizeof(struct xhci_trb)]; 1243 } else { 1244 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1245 } 1246 xfer = &xx->xx_xfer; 1247 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1248 1249 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1250 DPRINTFN(14, "transfer event data: " 1251 "0x%016"PRIx64" 0x%08"PRIx32" %02x", 1252 trb_0, XHCI_TRB_2_REM_GET(trb_2), 1253 XHCI_TRB_2_ERROR_GET(trb_2), 0); 1254 if ((trb_0 & 0x3) == 0x3) { 1255 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1256 } 1257 } 1258 1259 if (XHCI_TRB_2_ERROR_GET(trb_2) == 1260 XHCI_TRB_ERROR_SUCCESS) { 1261 xfer->ux_actlen = xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1262 err = USBD_NORMAL_COMPLETION; 1263 } else if (XHCI_TRB_2_ERROR_GET(trb_2) == 1264 XHCI_TRB_ERROR_SHORT_PKT) { 1265 xfer->ux_actlen = xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1266 err = USBD_NORMAL_COMPLETION; 1267 } else if (XHCI_TRB_2_ERROR_GET(trb_2) == 1268 XHCI_TRB_ERROR_STALL) { 1269 err = USBD_STALLED; 1270 xr->is_halted = true; 1271 DPRINTFN(1, "ev: xfer done: err %u slot %u dci %u", 1272 XHCI_TRB_2_ERROR_GET(trb_2), slot, dci, 0); 1273 } else { 1274 err = USBD_IOERROR; 1275 } 1276 xfer->ux_status = err; 1277 1278 //mutex_enter(&sc->sc_lock); /* XXX ??? */ 1279 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1280 if ((trb_0 & 0x3) == 0x0) { 1281 usb_transfer_complete(xfer); 1282 } 1283 } else { 1284 usb_transfer_complete(xfer); 1285 } 1286 //mutex_exit(&sc->sc_lock); /* XXX ??? */ 1287 1288 } 1289 break; 1290 case XHCI_TRB_EVENT_CMD_COMPLETE: 1291 if (trb_0 == sc->sc_command_addr) { 1292 sc->sc_result_trb.trb_0 = trb_0; 1293 sc->sc_result_trb.trb_2 = trb_2; 1294 sc->sc_result_trb.trb_3 = trb_3; 1295 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1296 XHCI_TRB_ERROR_SUCCESS) { 1297 DPRINTFN(1, "command completion " 1298 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1299 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1300 } 1301 cv_signal(&sc->sc_command_cv); 1302 } else { 1303 DPRINTFN(1, "event: %p 0x%016"PRIx64" " 1304 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1305 trb_2, trb_3); 1306 } 1307 break; 1308 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1309 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1310 break; 1311 default: 1312 break; 1313 } 1314 } 1315 1316 static void 1317 xhci_softintr(void *v) 1318 { 1319 struct usbd_bus * const bus = v; 1320 struct xhci_softc * const sc = bus->ub_hcpriv; 1321 struct xhci_ring * const er = &sc->sc_er; 1322 struct xhci_trb *trb; 1323 int i, j, k; 1324 1325 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1326 1327 i = er->xr_ep; 1328 j = er->xr_cs; 1329 1330 DPRINTFN(16, "xr_ep %d xr_cs %d", i, j, 0, 0); 1331 1332 while (1) { 1333 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 1334 BUS_DMASYNC_POSTREAD); 1335 trb = &er->xr_trb[i]; 1336 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1337 1338 if (j != k) 1339 break; 1340 1341 xhci_handle_event(sc, trb); 1342 1343 i++; 1344 if (i == XHCI_EVENT_RING_TRBS) { 1345 i = 0; 1346 j ^= 1; 1347 } 1348 } 1349 1350 er->xr_ep = i; 1351 er->xr_cs = j; 1352 1353 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 1354 XHCI_ERDP_LO_BUSY); 1355 1356 DPRINTFN(16, "ends", 0, 0, 0, 0); 1357 1358 return; 1359 } 1360 1361 static void 1362 xhci_poll(struct usbd_bus *bus) 1363 { 1364 struct xhci_softc * const sc = bus->ub_hcpriv; 1365 1366 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1367 1368 mutex_spin_enter(&sc->sc_intr_lock); 1369 xhci_intr1(sc); 1370 mutex_spin_exit(&sc->sc_intr_lock); 1371 1372 return; 1373 } 1374 1375 static usbd_xfer_handle 1376 xhci_allocx(struct usbd_bus *bus) 1377 { 1378 struct xhci_softc * const sc = bus->ub_hcpriv; 1379 usbd_xfer_handle xfer; 1380 1381 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1382 1383 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1384 if (xfer != NULL) { 1385 memset(xfer, 0, sizeof(struct xhci_xfer)); 1386 #ifdef DIAGNOSTIC 1387 xfer->ux_state = XFER_BUSY; 1388 #endif 1389 } 1390 1391 return xfer; 1392 } 1393 1394 static void 1395 xhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1396 { 1397 struct xhci_softc * const sc = bus->ub_hcpriv; 1398 1399 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1400 1401 #ifdef DIAGNOSTIC 1402 if (xfer->ux_state != XFER_BUSY) { 1403 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 1404 xfer, xfer->ux_state, 0, 0); 1405 } 1406 xfer->ux_state = XFER_FREE; 1407 #endif 1408 pool_cache_put(sc->sc_xferpool, xfer); 1409 } 1410 1411 static void 1412 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1413 { 1414 struct xhci_softc * const sc = bus->ub_hcpriv; 1415 1416 *lock = &sc->sc_lock; 1417 } 1418 1419 extern uint32_t usb_cookie_no; 1420 1421 static usbd_status 1422 xhci_new_device(device_t parent, usbd_bus_handle bus, int depth, 1423 int speed, int port, struct usbd_port *up) 1424 { 1425 struct xhci_softc * const sc = bus->ub_hcpriv; 1426 usbd_device_handle dev; 1427 usbd_status err; 1428 usb_device_descriptor_t *dd; 1429 struct usbd_device *hub; 1430 struct usbd_device *adev; 1431 int rhport = 0; 1432 struct xhci_slot *xs; 1433 uint32_t *cp; 1434 uint8_t slot; 1435 uint8_t addr; 1436 1437 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1438 DPRINTFN(4, "port=%d depth=%d speed=%d upport %d", 1439 port, depth, speed, up->up_portno); 1440 1441 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 1442 if (dev == NULL) 1443 return USBD_NOMEM; 1444 1445 dev->ud_bus = bus; 1446 1447 /* Set up default endpoint handle. */ 1448 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 1449 1450 /* Set up default endpoint descriptor. */ 1451 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 1452 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 1453 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 1454 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 1455 /* XXX */ 1456 if (speed == USB_SPEED_LOW) 1457 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 1458 else 1459 USETW(dev->ud_ep0desc.wMaxPacketSize, 64); 1460 dev->ud_ep0desc.bInterval = 0; 1461 1462 /* doesn't matter, just don't let it uninitialized */ 1463 dev->ud_ep0.ue_toggle = 0; 1464 1465 DPRINTFN(4, "up %p portno %d", up, up->up_portno, 0, 0); 1466 1467 dev->ud_quirks = &usbd_no_quirk; 1468 dev->ud_addr = 0; 1469 dev->ud_ddesc.bMaxPacketSize = 0; 1470 dev->ud_depth = depth; 1471 dev->ud_powersrc = up; 1472 dev->ud_myhub = up->up_parent; 1473 1474 up->up_dev = dev; 1475 1476 /* Locate root hub port */ 1477 for (adev = dev, hub = dev; 1478 hub != NULL; 1479 adev = hub, hub = hub->ud_myhub) { 1480 DPRINTFN(4, "hub %p", hub, 0, 0, 0); 1481 } 1482 DPRINTFN(4, "hub %p", hub, 0, 0, 0); 1483 1484 if (hub != NULL) { 1485 for (int p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 1486 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 1487 rhport = p; 1488 } 1489 } 1490 } else { 1491 rhport = port; 1492 } 1493 if (speed == USB_SPEED_SUPER) { 1494 rhport += sc->sc_ss_port_start - 1; 1495 } else { 1496 rhport += sc->sc_hs_port_start - 1; 1497 } 1498 DPRINTFN(4, "rhport %d", rhport, 0, 0, 0); 1499 1500 dev->ud_speed = speed; 1501 dev->ud_langid = USBD_NOLANG; 1502 dev->ud_cookie.cookie = ++usb_cookie_no; 1503 1504 /* Establish the default pipe. */ 1505 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 1506 &dev->ud_pipe0); 1507 if (err) { 1508 usbd_remove_device(dev, up); 1509 return (err); 1510 } 1511 1512 dd = &dev->ud_ddesc; 1513 1514 if ((depth == 0) && (port == 0)) { 1515 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 1516 bus->ub_devices[dev->ud_addr] = dev; 1517 err = usbd_get_initial_ddesc(dev, dd); 1518 if (err) 1519 return err; 1520 err = usbd_reload_device_desc(dev); 1521 if (err) 1522 return err; 1523 } else { 1524 err = xhci_enable_slot(sc, &slot); 1525 if (err) 1526 return err; 1527 err = xhci_init_slot(sc, slot, depth, speed, port, rhport); 1528 if (err) 1529 return err; 1530 xs = &sc->sc_slots[slot]; 1531 dev->ud_hcpriv = xs; 1532 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 1533 //hexdump("slot context", cp, sc->sc_ctxsz); 1534 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 1535 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 1536 /* XXX ensure we know when the hardware does something 1537 we can't yet cope with */ 1538 KASSERT(addr >= 1 && addr <= 127); 1539 dev->ud_addr = addr; 1540 /* XXX dev->ud_addr not necessarily unique on bus */ 1541 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 1542 bus->ub_devices[dev->ud_addr] = dev; 1543 1544 err = usbd_get_initial_ddesc(dev, dd); 1545 if (err) 1546 return err; 1547 /* 4.8.2.1 */ 1548 if (speed == USB_SPEED_SUPER) 1549 USETW(dev->ud_ep0desc.wMaxPacketSize, 1550 (1 << dd->bMaxPacketSize)); 1551 else 1552 USETW(dev->ud_ep0desc.wMaxPacketSize, 1553 dd->bMaxPacketSize); 1554 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 1555 xhci_update_ep0_mps(sc, xs, 1556 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 1557 err = usbd_reload_device_desc(dev); 1558 if (err) 1559 return err; 1560 1561 usbd_kill_pipe(dev->ud_pipe0); 1562 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 1563 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 1564 } 1565 1566 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 1567 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 1568 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 1569 dd->bDeviceClass, dd->bDeviceSubClass, 1570 dd->bDeviceProtocol, 0); 1571 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 1572 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 1573 dev->ud_speed); 1574 1575 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 1576 1577 if ((depth == 0) && (port == 0)) { 1578 usbd_attach_roothub(parent, dev); 1579 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 1580 return USBD_NORMAL_COMPLETION; 1581 } 1582 1583 1584 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 1585 if (err) { 1586 usbd_remove_device(dev, up); 1587 return (err); 1588 } 1589 1590 return USBD_NORMAL_COMPLETION; 1591 } 1592 1593 static usbd_status 1594 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 1595 size_t ntrb, size_t align) 1596 { 1597 usbd_status err; 1598 size_t size = ntrb * XHCI_TRB_SIZE; 1599 1600 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1601 1602 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 1603 if (err) 1604 return err; 1605 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1606 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 1607 xr->xr_trb = xhci_ring_trbv(xr, 0); 1608 xr->xr_ntrb = ntrb; 1609 xr->xr_ep = 0; 1610 xr->xr_cs = 1; 1611 memset(xr->xr_trb, 0, size); 1612 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 1613 xr->is_halted = false; 1614 1615 return USBD_NORMAL_COMPLETION; 1616 } 1617 1618 static void 1619 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 1620 { 1621 usb_freemem(&sc->sc_bus, &xr->xr_dma); 1622 mutex_destroy(&xr->xr_lock); 1623 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 1624 } 1625 1626 static void 1627 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 1628 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 1629 { 1630 size_t i; 1631 u_int ri; 1632 u_int cs; 1633 uint64_t parameter; 1634 uint32_t status; 1635 uint32_t control; 1636 1637 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1638 1639 for (i = 0; i < ntrbs; i++) { 1640 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 1641 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 1642 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 1643 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 1644 XHCI_TRB_TYPE_LINK); 1645 } 1646 1647 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 1648 1649 ri = xr->xr_ep; 1650 cs = xr->xr_cs; 1651 1652 /* 1653 * Although the xhci hardware can do scatter/gather dma from 1654 * arbitrary sized buffers, there is a non-obvious restriction 1655 * that a LINK trb is only allowed at the end of a burst of 1656 * transfers - which might be 16kB. 1657 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 1658 * The simple solution is not to allow a LINK trb in the middle 1659 * of anything - as here. 1660 * XXX: (dsl) There are xhci controllers out there (eg some made by 1661 * ASMedia) that seem to lock up if they process a LINK trb but 1662 * cannot process the linked-to trb yet. 1663 * The code should write the 'cycle' bit on the link trb AFTER 1664 * adding the other trb. 1665 */ 1666 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 1667 parameter = xhci_ring_trbp(xr, 0); 1668 status = 0; 1669 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1670 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 1671 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 1672 htole32(status), htole32(control)); 1673 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1674 BUS_DMASYNC_PREWRITE); 1675 xr->xr_cookies[ri] = NULL; 1676 xr->xr_ep = 0; 1677 xr->xr_cs ^= 1; 1678 ri = xr->xr_ep; 1679 cs = xr->xr_cs; 1680 } 1681 1682 ri++; 1683 1684 /* Write any subsequent TRB first */ 1685 for (i = 1; i < ntrbs; i++) { 1686 parameter = trbs[i].trb_0; 1687 status = trbs[i].trb_2; 1688 control = trbs[i].trb_3; 1689 1690 if (cs) { 1691 control |= XHCI_TRB_3_CYCLE_BIT; 1692 } else { 1693 control &= ~XHCI_TRB_3_CYCLE_BIT; 1694 } 1695 1696 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 1697 htole32(status), htole32(control)); 1698 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1699 BUS_DMASYNC_PREWRITE); 1700 xr->xr_cookies[ri] = cookie; 1701 ri++; 1702 } 1703 1704 /* Write the first TRB last */ 1705 i = 0; 1706 { 1707 parameter = trbs[i].trb_0; 1708 status = trbs[i].trb_2; 1709 control = trbs[i].trb_3; 1710 1711 if (xr->xr_cs) { 1712 control |= XHCI_TRB_3_CYCLE_BIT; 1713 } else { 1714 control &= ~XHCI_TRB_3_CYCLE_BIT; 1715 } 1716 1717 xhci_trb_put(&xr->xr_trb[xr->xr_ep], htole64(parameter), 1718 htole32(status), htole32(control)); 1719 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1720 BUS_DMASYNC_PREWRITE); 1721 xr->xr_cookies[xr->xr_ep] = cookie; 1722 } 1723 1724 xr->xr_ep = ri; 1725 xr->xr_cs = cs; 1726 1727 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 1728 } 1729 1730 static usbd_status 1731 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 1732 int timeout) 1733 { 1734 struct xhci_ring * const cr = &sc->sc_cr; 1735 usbd_status err; 1736 1737 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1738 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1739 trb->trb_0, trb->trb_2, trb->trb_3, 0); 1740 1741 mutex_enter(&sc->sc_lock); 1742 1743 KASSERT(sc->sc_command_addr == 0); 1744 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 1745 1746 mutex_enter(&cr->xr_lock); 1747 xhci_ring_put(sc, cr, NULL, trb, 1); 1748 mutex_exit(&cr->xr_lock); 1749 1750 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 1751 1752 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 1753 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 1754 err = USBD_TIMEOUT; 1755 goto timedout; 1756 } 1757 1758 trb->trb_0 = sc->sc_result_trb.trb_0; 1759 trb->trb_2 = sc->sc_result_trb.trb_2; 1760 trb->trb_3 = sc->sc_result_trb.trb_3; 1761 1762 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 1763 trb->trb_0, trb->trb_2, trb->trb_3, 0); 1764 1765 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 1766 case XHCI_TRB_ERROR_SUCCESS: 1767 err = USBD_NORMAL_COMPLETION; 1768 break; 1769 default: 1770 case 192 ... 223: 1771 err = USBD_IOERROR; 1772 break; 1773 case 224 ... 255: 1774 err = USBD_NORMAL_COMPLETION; 1775 break; 1776 } 1777 1778 timedout: 1779 sc->sc_command_addr = 0; 1780 mutex_exit(&sc->sc_lock); 1781 return err; 1782 } 1783 1784 static usbd_status 1785 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 1786 { 1787 struct xhci_trb trb; 1788 usbd_status err; 1789 1790 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1791 1792 trb.trb_0 = 0; 1793 trb.trb_2 = 0; 1794 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 1795 1796 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1797 if (err != USBD_NORMAL_COMPLETION) { 1798 return err; 1799 } 1800 1801 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 1802 1803 return err; 1804 } 1805 1806 static usbd_status 1807 xhci_address_device(struct xhci_softc * const sc, 1808 uint64_t icp, uint8_t slot_id, bool bsr) 1809 { 1810 struct xhci_trb trb; 1811 usbd_status err; 1812 1813 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1814 1815 trb.trb_0 = icp; 1816 trb.trb_2 = 0; 1817 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 1818 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1819 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 1820 1821 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1822 return err; 1823 } 1824 1825 static usbd_status 1826 xhci_update_ep0_mps(struct xhci_softc * const sc, 1827 struct xhci_slot * const xs, u_int mps) 1828 { 1829 struct xhci_trb trb; 1830 usbd_status err; 1831 uint32_t * cp; 1832 1833 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1834 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 1835 1836 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1837 cp[0] = htole32(0); 1838 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 1839 1840 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 1841 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1842 1843 /* sync input contexts before they are read from memory */ 1844 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1845 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 1846 sc->sc_ctxsz * 4); 1847 1848 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1849 trb.trb_2 = 0; 1850 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1851 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 1852 1853 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1854 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 1855 return err; 1856 } 1857 1858 static void 1859 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 1860 { 1861 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 1862 1863 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1864 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 1865 &dcbaa[si], dcba, si, 0); 1866 1867 dcbaa[si] = htole64(dcba); 1868 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 1869 BUS_DMASYNC_PREWRITE); 1870 } 1871 1872 static usbd_status 1873 xhci_init_slot(struct xhci_softc * const sc, uint32_t slot, int depth, 1874 int speed, int port, int rhport) 1875 { 1876 struct xhci_slot *xs; 1877 usbd_status err; 1878 u_int dci; 1879 uint32_t *cp; 1880 uint32_t mps; 1881 uint32_t xspeed; 1882 1883 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1884 DPRINTFN(4, "slot %u depth %d speed %d", 1885 slot, depth, speed, 0); 1886 DPRINTFN(4, " port %d rhport %d", 1887 port, rhport, 0, 0); 1888 1889 switch (speed) { 1890 case USB_SPEED_LOW: 1891 xspeed = 2; 1892 mps = USB_MAX_IPACKET; 1893 break; 1894 case USB_SPEED_FULL: 1895 xspeed = 1; 1896 mps = 64; 1897 break; 1898 case USB_SPEED_HIGH: 1899 xspeed = 3; 1900 mps = USB_2_MAX_CTRL_PACKET; 1901 break; 1902 case USB_SPEED_SUPER: 1903 xspeed = 4; 1904 mps = USB_3_MAX_CTRL_PACKET; 1905 break; 1906 default: 1907 DPRINTFN(0, "impossible speed: %x", speed, 0, 0, 0); 1908 return USBD_INVAL; 1909 } 1910 1911 xs = &sc->sc_slots[slot]; 1912 xs->xs_idx = slot; 1913 1914 /* allocate contexts */ 1915 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 1916 &xs->xs_dc_dma); 1917 if (err) 1918 return err; 1919 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 1920 1921 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 1922 &xs->xs_ic_dma); 1923 if (err) 1924 return err; 1925 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 1926 1927 for (dci = 0; dci < 32; dci++) { 1928 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 1929 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 1930 if (dci == XHCI_DCI_SLOT) 1931 continue; 1932 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 1933 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 1934 if (err) { 1935 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 1936 return err; 1937 } 1938 } 1939 1940 /* set up initial input control context */ 1941 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1942 cp[0] = htole32(0); 1943 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 1944 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 1945 1946 /* set up input slot context */ 1947 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1948 cp[0] = htole32( 1949 XHCI_SCTX_0_CTX_NUM_SET(1) | 1950 XHCI_SCTX_0_SPEED_SET(xspeed) 1951 ); 1952 cp[1] = htole32( 1953 XHCI_SCTX_1_RH_PORT_SET(rhport) 1954 ); 1955 cp[2] = htole32( 1956 XHCI_SCTX_2_IRQ_TARGET_SET(0) 1957 ); 1958 cp[3] = htole32(0); 1959 1960 /* set up input EP0 context */ 1961 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 1962 cp[0] = htole32(0); 1963 cp[1] = htole32( 1964 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 1965 XHCI_EPCTX_1_EPTYPE_SET(4) | 1966 XHCI_EPCTX_1_CERR_SET(3) 1967 ); 1968 /* can't use xhci_ep_get_dci() yet? */ 1969 *(uint64_t *)(&cp[2]) = htole64( 1970 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 1971 XHCI_EPCTX_2_DCS_SET(1)); 1972 cp[4] = htole32( 1973 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 1974 ); 1975 1976 /* sync input contexts before they are read from memory */ 1977 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1978 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 1979 sc->sc_ctxsz * 3); 1980 1981 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 1982 1983 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 1984 false); 1985 1986 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1987 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 1988 sc->sc_ctxsz * 2); 1989 1990 return err; 1991 } 1992 1993 /* ----- */ 1994 1995 static void 1996 xhci_noop(usbd_pipe_handle pipe) 1997 { 1998 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1999 } 2000 2001 /* root hub descriptors */ 2002 2003 static const usb_device_descriptor_t xhci_devd = { 2004 .bLength = USB_DEVICE_DESCRIPTOR_SIZE, 2005 .bDescriptorType = UDESC_DEVICE, 2006 .bcdUSB = {0x00, 0x02}, 2007 .bDeviceClass = UDCLASS_HUB, 2008 .bDeviceSubClass = UDSUBCLASS_HUB, 2009 .bDeviceProtocol = UDPROTO_HSHUBSTT, 2010 .bMaxPacketSize = 64, 2011 .idVendor = {0}, 2012 .idProduct = {0}, 2013 .bcdDevice = {0x00,0x01}, 2014 .iManufacturer = 1, 2015 .iProduct = 2, 2016 .iSerialNumber = 0, 2017 .bNumConfigurations = 1 2018 }; 2019 2020 static const usb_device_qualifier_t xhci_odevd = { 2021 .bLength = USB_DEVICE_DESCRIPTOR_SIZE, 2022 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 2023 .bcdUSB = {0x00, 0x02}, 2024 .bDeviceClass = UDCLASS_HUB, 2025 .bDeviceSubClass = UDSUBCLASS_HUB, 2026 .bDeviceProtocol = UDPROTO_FSHUB, 2027 .bMaxPacketSize0 = 64, 2028 .bNumConfigurations = 1, 2029 }; 2030 2031 static const usb_config_descriptor_t xhci_confd = { 2032 .bLength = USB_CONFIG_DESCRIPTOR_SIZE, 2033 .bDescriptorType = UDESC_CONFIG, 2034 .wTotalLength = { 2035 USB_CONFIG_DESCRIPTOR_SIZE + 2036 USB_INTERFACE_DESCRIPTOR_SIZE + 2037 USB_ENDPOINT_DESCRIPTOR_SIZE 2038 }, 2039 .bNumInterface = 1, 2040 .bConfigurationValue = 1, 2041 .iConfiguration = 0, 2042 .bmAttributes = UC_ATTR_MBO | UC_SELF_POWERED, 2043 .bMaxPower = 0 2044 }; 2045 2046 static const usb_interface_descriptor_t xhci_ifcd = { 2047 .bLength = USB_INTERFACE_DESCRIPTOR_SIZE, 2048 .bDescriptorType = UDESC_INTERFACE, 2049 .bInterfaceNumber = 0, 2050 .bAlternateSetting = 0, 2051 .bNumEndpoints = 1, 2052 .bInterfaceClass = UICLASS_HUB, 2053 .bInterfaceSubClass = UISUBCLASS_HUB, 2054 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 2055 .iInterface = 0 2056 }; 2057 2058 static const usb_endpoint_descriptor_t xhci_endpd = { 2059 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 2060 .bDescriptorType = UDESC_ENDPOINT, 2061 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 2062 .bmAttributes = UE_INTERRUPT, 2063 .wMaxPacketSize = {8, 0}, 2064 .bInterval = 12 2065 }; 2066 2067 static const usb_hub_descriptor_t xhci_hubd = { 2068 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 2069 .bDescriptorType = UDESC_HUB, 2070 .bNbrPorts = 0, 2071 .wHubCharacteristics = {0,0}, 2072 .bPwrOn2PwrGood = 0, 2073 .bHubContrCurrent = 0, 2074 .DeviceRemovable = {""}, 2075 .PortPowerCtrlMask = {""}, 2076 }; 2077 2078 /* root hub control */ 2079 2080 static usbd_status 2081 xhci_root_ctrl_transfer(usbd_xfer_handle xfer) 2082 { 2083 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2084 usbd_status err; 2085 2086 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2087 2088 /* Insert last in queue. */ 2089 mutex_enter(&sc->sc_lock); 2090 err = usb_insert_transfer(xfer); 2091 mutex_exit(&sc->sc_lock); 2092 if (err) 2093 return err; 2094 2095 /* Pipe isn't running, start first */ 2096 return (xhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 2097 } 2098 2099 static usbd_status 2100 xhci_root_ctrl_start(usbd_xfer_handle xfer) 2101 { 2102 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2103 usb_port_status_t ps; 2104 usb_device_request_t *req; 2105 void *buf = NULL; 2106 usb_hub_descriptor_t hubd; 2107 usbd_status err; 2108 int len, value, index; 2109 int l, totlen = 0; 2110 int port, i; 2111 uint32_t v; 2112 2113 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2114 2115 if (sc->sc_dying) 2116 return USBD_IOERROR; 2117 2118 req = &xfer->ux_request; 2119 2120 value = UGETW(req->wValue); 2121 index = UGETW(req->wIndex); 2122 len = UGETW(req->wLength); 2123 2124 if (len != 0) 2125 buf = xfer->ux_buf; 2126 2127 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 2128 req->bmRequestType | (req->bRequest << 8), value, index, len); 2129 2130 #define C(x,y) ((x) | ((y) << 8)) 2131 switch(C(req->bRequest, req->bmRequestType)) { 2132 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2133 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2134 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2135 /* 2136 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2137 * for the integrated root hub. 2138 */ 2139 break; 2140 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2141 if (len > 0) { 2142 *(uint8_t *)buf = sc->sc_conf; 2143 totlen = 1; 2144 } 2145 break; 2146 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2147 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 2148 if (len == 0) 2149 break; 2150 switch(value >> 8) { 2151 case UDESC_DEVICE: 2152 if ((value & 0xff) != 0) { 2153 err = USBD_IOERROR; 2154 goto ret; 2155 } 2156 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2157 memcpy(buf, &xhci_devd, min(l, sizeof(xhci_devd))); 2158 break; 2159 case UDESC_DEVICE_QUALIFIER: 2160 if ((value & 0xff) != 0) { 2161 } 2162 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2163 memcpy(buf, &xhci_odevd, min(l, sizeof(xhci_odevd))); 2164 break; 2165 case UDESC_OTHER_SPEED_CONFIGURATION: 2166 case UDESC_CONFIG: 2167 if ((value & 0xff) != 0) { 2168 err = USBD_IOERROR; 2169 goto ret; 2170 } 2171 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2172 memcpy(buf, &xhci_confd, min(l, sizeof(xhci_confd))); 2173 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2174 value >> 8; 2175 buf = (char *)buf + l; 2176 len -= l; 2177 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2178 totlen += l; 2179 memcpy(buf, &xhci_ifcd, min(l, sizeof(xhci_ifcd))); 2180 buf = (char *)buf + l; 2181 len -= l; 2182 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2183 totlen += l; 2184 memcpy(buf, &xhci_endpd, min(l, sizeof(xhci_endpd))); 2185 break; 2186 case UDESC_STRING: 2187 #define sd ((usb_string_descriptor_t *)buf) 2188 switch (value & 0xff) { 2189 case 0: /* Language table */ 2190 totlen = usb_makelangtbl(sd, len); 2191 break; 2192 case 1: /* Vendor */ 2193 totlen = usb_makestrdesc(sd, len, "NetBSD"); 2194 break; 2195 case 2: /* Product */ 2196 totlen = usb_makestrdesc(sd, len, 2197 "xHCI Root Hub"); 2198 break; 2199 } 2200 #undef sd 2201 break; 2202 default: 2203 err = USBD_IOERROR; 2204 goto ret; 2205 } 2206 break; 2207 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2208 if (len > 0) { 2209 *(uint8_t *)buf = 0; 2210 totlen = 1; 2211 } 2212 break; 2213 case C(UR_GET_STATUS, UT_READ_DEVICE): 2214 if (len > 1) { 2215 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2216 totlen = 2; 2217 } 2218 break; 2219 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2220 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2221 if (len > 1) { 2222 USETW(((usb_status_t *)buf)->wStatus, 0); 2223 totlen = 2; 2224 } 2225 break; 2226 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2227 if (value >= USB_MAX_DEVICES) { 2228 err = USBD_IOERROR; 2229 goto ret; 2230 } 2231 //sc->sc_addr = value; 2232 break; 2233 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2234 if (value != 0 && value != 1) { 2235 err = USBD_IOERROR; 2236 goto ret; 2237 } 2238 sc->sc_conf = value; 2239 break; 2240 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2241 break; 2242 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2243 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2244 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2245 err = USBD_IOERROR; 2246 goto ret; 2247 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2248 break; 2249 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2250 break; 2251 /* Hub requests */ 2252 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2253 break; 2254 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2255 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2256 index, value, 0, 0); 2257 if (index < 1 || index > sc->sc_hs_port_count) { 2258 err = USBD_IOERROR; 2259 goto ret; 2260 } 2261 port = XHCI_PORTSC(sc->sc_hs_port_start - 1 + index); 2262 v = xhci_op_read_4(sc, port); 2263 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2264 v &= ~XHCI_PS_CLEAR; 2265 switch (value) { 2266 case UHF_PORT_ENABLE: 2267 xhci_op_write_4(sc, port, v &~ XHCI_PS_PED); 2268 break; 2269 case UHF_PORT_SUSPEND: 2270 err = USBD_IOERROR; 2271 goto ret; 2272 case UHF_PORT_POWER: 2273 break; 2274 case UHF_PORT_TEST: 2275 case UHF_PORT_INDICATOR: 2276 err = USBD_IOERROR; 2277 goto ret; 2278 case UHF_C_PORT_CONNECTION: 2279 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2280 break; 2281 case UHF_C_PORT_ENABLE: 2282 case UHF_C_PORT_SUSPEND: 2283 case UHF_C_PORT_OVER_CURRENT: 2284 err = USBD_IOERROR; 2285 goto ret; 2286 case UHF_C_PORT_RESET: 2287 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2288 break; 2289 default: 2290 err = USBD_IOERROR; 2291 goto ret; 2292 } 2293 2294 break; 2295 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2296 if (len == 0) 2297 break; 2298 if ((value & 0xff) != 0) { 2299 err = USBD_IOERROR; 2300 goto ret; 2301 } 2302 hubd = xhci_hubd; 2303 hubd.bNbrPorts = sc->sc_hs_port_count; 2304 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2305 hubd.bPwrOn2PwrGood = 200; 2306 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 2307 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2308 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2309 l = min(len, hubd.bDescLength); 2310 totlen = l; 2311 memcpy(buf, &hubd, l); 2312 break; 2313 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2314 if (len != 4) { 2315 err = USBD_IOERROR; 2316 goto ret; 2317 } 2318 memset(buf, 0, len); /* ? XXX */ 2319 totlen = len; 2320 break; 2321 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2322 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2323 if (index < 1 || index > sc->sc_maxports) { 2324 err = USBD_IOERROR; 2325 goto ret; 2326 } 2327 if (len != 4) { 2328 err = USBD_IOERROR; 2329 goto ret; 2330 } 2331 v = xhci_op_read_4(sc, XHCI_PORTSC(sc->sc_hs_port_start - 1 + 2332 index)); 2333 DPRINTFN(4, "READ_CLASS_OTHER GET_STATUS PORTSC %d (%d) %08x", 2334 index, sc->sc_hs_port_start - 1 + index, v, 0); 2335 switch (XHCI_PS_SPEED_GET(v)) { 2336 case 1: 2337 i = UPS_FULL_SPEED; 2338 break; 2339 case 2: 2340 i = UPS_LOW_SPEED; 2341 break; 2342 case 3: 2343 i = UPS_HIGH_SPEED; 2344 break; 2345 default: 2346 i = 0; 2347 break; 2348 } 2349 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2350 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2351 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2352 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 2353 if (v & XHCI_PS_PR) i |= UPS_RESET; 2354 if (v & XHCI_PS_PP) i |= UPS_PORT_POWER; 2355 USETW(ps.wPortStatus, i); 2356 i = 0; 2357 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2358 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2359 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2360 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2361 USETW(ps.wPortChange, i); 2362 l = min(len, sizeof ps); 2363 memcpy(buf, &ps, l); 2364 totlen = l; 2365 break; 2366 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2367 err = USBD_IOERROR; 2368 goto ret; 2369 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2370 break; 2371 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2372 if (index < 1 || index > sc->sc_hs_port_count) { 2373 err = USBD_IOERROR; 2374 goto ret; 2375 } 2376 port = XHCI_PORTSC(sc->sc_hs_port_start - 1 + index); 2377 v = xhci_op_read_4(sc, port); 2378 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2379 v &= ~XHCI_PS_CLEAR; 2380 switch (value) { 2381 case UHF_PORT_ENABLE: 2382 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 2383 break; 2384 case UHF_PORT_SUSPEND: 2385 /* XXX suspend */ 2386 break; 2387 case UHF_PORT_RESET: 2388 v &= ~ (XHCI_PS_PED | XHCI_PS_PR); 2389 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 2390 /* Wait for reset to complete. */ 2391 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2392 if (sc->sc_dying) { 2393 err = USBD_IOERROR; 2394 goto ret; 2395 } 2396 v = xhci_op_read_4(sc, port); 2397 if (v & XHCI_PS_PR) { 2398 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 2399 usb_delay_ms(&sc->sc_bus, 10); 2400 /* XXX */ 2401 } 2402 break; 2403 case UHF_PORT_POWER: 2404 /* XXX power control */ 2405 break; 2406 /* XXX more */ 2407 case UHF_C_PORT_RESET: 2408 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2409 break; 2410 default: 2411 err = USBD_IOERROR; 2412 goto ret; 2413 } 2414 break; 2415 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2416 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2417 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2418 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2419 break; 2420 default: 2421 err = USBD_IOERROR; 2422 goto ret; 2423 } 2424 xfer->ux_actlen = totlen; 2425 err = USBD_NORMAL_COMPLETION; 2426 ret: 2427 xfer->ux_status = err; 2428 mutex_enter(&sc->sc_lock); 2429 usb_transfer_complete(xfer); 2430 mutex_exit(&sc->sc_lock); 2431 return USBD_IN_PROGRESS; 2432 } 2433 2434 2435 static void 2436 xhci_root_ctrl_abort(usbd_xfer_handle xfer) 2437 { 2438 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2439 /* Nothing to do, all transfers are synchronous. */ 2440 } 2441 2442 2443 static void 2444 xhci_root_ctrl_close(usbd_pipe_handle pipe) 2445 { 2446 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2447 /* Nothing to do. */ 2448 } 2449 2450 static void 2451 xhci_root_ctrl_done(usbd_xfer_handle xfer) 2452 { 2453 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2454 2455 xfer->ux_hcpriv = NULL; 2456 } 2457 2458 /* root hub interrupt */ 2459 2460 static usbd_status 2461 xhci_root_intr_transfer(usbd_xfer_handle xfer) 2462 { 2463 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2464 usbd_status err; 2465 2466 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2467 2468 /* Insert last in queue. */ 2469 mutex_enter(&sc->sc_lock); 2470 err = usb_insert_transfer(xfer); 2471 mutex_exit(&sc->sc_lock); 2472 if (err) 2473 return err; 2474 2475 /* Pipe isn't running, start first */ 2476 return (xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 2477 } 2478 2479 static usbd_status 2480 xhci_root_intr_start(usbd_xfer_handle xfer) 2481 { 2482 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2483 2484 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2485 2486 if (sc->sc_dying) 2487 return USBD_IOERROR; 2488 2489 mutex_enter(&sc->sc_lock); 2490 sc->sc_intrxfer = xfer; 2491 mutex_exit(&sc->sc_lock); 2492 2493 return USBD_IN_PROGRESS; 2494 } 2495 2496 static void 2497 xhci_root_intr_abort(usbd_xfer_handle xfer) 2498 { 2499 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2500 2501 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2502 2503 KASSERT(mutex_owned(&sc->sc_lock)); 2504 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2505 2506 DPRINTFN(1, "remove", 0, 0, 0, 0); 2507 2508 sc->sc_intrxfer = NULL; 2509 2510 xfer->ux_status = USBD_CANCELLED; 2511 usb_transfer_complete(xfer); 2512 } 2513 2514 static void 2515 xhci_root_intr_close(usbd_pipe_handle pipe) 2516 { 2517 struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 2518 2519 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2520 2521 KASSERT(mutex_owned(&sc->sc_lock)); 2522 2523 sc->sc_intrxfer = NULL; 2524 } 2525 2526 static void 2527 xhci_root_intr_done(usbd_xfer_handle xfer) 2528 { 2529 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2530 2531 xfer->ux_hcpriv = NULL; 2532 } 2533 2534 /* -------------- */ 2535 /* device control */ 2536 2537 static usbd_status 2538 xhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2539 { 2540 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2541 usbd_status err; 2542 2543 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2544 2545 /* Insert last in queue. */ 2546 mutex_enter(&sc->sc_lock); 2547 err = usb_insert_transfer(xfer); 2548 mutex_exit(&sc->sc_lock); 2549 if (err) 2550 return (err); 2551 2552 /* Pipe isn't running, start first */ 2553 return (xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 2554 } 2555 2556 static usbd_status 2557 xhci_device_ctrl_start(usbd_xfer_handle xfer) 2558 { 2559 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2560 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 2561 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 2562 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2563 struct xhci_xfer * const xx = (void *)xfer; 2564 usb_device_request_t * const req = &xfer->ux_request; 2565 const bool isread = UT_GET_DIR(req->bmRequestType) == UT_READ; 2566 const uint32_t len = UGETW(req->wLength); 2567 usb_dma_t * const dma = &xfer->ux_dmabuf; 2568 uint64_t parameter; 2569 uint32_t status; 2570 uint32_t control; 2571 u_int i; 2572 2573 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2574 DPRINTFN(12, "req: %04x %04x %04x %04x", 2575 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 2576 UGETW(req->wIndex), UGETW(req->wLength)); 2577 2578 /* XXX */ 2579 if (tr->is_halted) { 2580 xhci_reset_endpoint(xfer->ux_pipe); 2581 tr->is_halted = false; 2582 xhci_set_dequeue(xfer->ux_pipe); 2583 } 2584 2585 /* we rely on the bottom bits for extra info */ 2586 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 2587 2588 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 2589 2590 i = 0; 2591 2592 /* setup phase */ 2593 memcpy(¶meter, req, sizeof(*req)); 2594 parameter = le64toh(parameter); 2595 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 2596 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 2597 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 2598 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 2599 XHCI_TRB_3_IDT_BIT; 2600 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2601 2602 if (len == 0) 2603 goto no_data; 2604 2605 /* data phase */ 2606 parameter = DMAADDR(dma, 0); 2607 KASSERT(len <= 0x10000); 2608 status = XHCI_TRB_2_IRQ_SET(0) | 2609 XHCI_TRB_2_TDSZ_SET(1) | 2610 XHCI_TRB_2_BYTES_SET(len); 2611 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 2612 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 2613 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 2614 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2615 2616 parameter = (uintptr_t)xfer | 0x3; 2617 status = XHCI_TRB_2_IRQ_SET(0); 2618 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 2619 XHCI_TRB_3_IOC_BIT; 2620 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2621 2622 no_data: 2623 parameter = 0; 2624 status = XHCI_TRB_2_IRQ_SET(0); 2625 /* the status stage has inverted direction */ 2626 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 2627 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 2628 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 2629 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2630 2631 parameter = (uintptr_t)xfer | 0x0; 2632 status = XHCI_TRB_2_IRQ_SET(0); 2633 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 2634 XHCI_TRB_3_IOC_BIT; 2635 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2636 2637 mutex_enter(&tr->xr_lock); 2638 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2639 mutex_exit(&tr->xr_lock); 2640 2641 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2642 2643 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2644 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2645 xhci_timeout, xfer); 2646 } 2647 2648 if (sc->sc_bus.ub_usepolling) { 2649 DPRINTFN(1, "polling", 0, 0, 0, 0); 2650 //xhci_waitintr(sc, xfer); 2651 } 2652 2653 return USBD_IN_PROGRESS; 2654 } 2655 2656 static void 2657 xhci_device_ctrl_done(usbd_xfer_handle xfer) 2658 { 2659 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2660 2661 callout_stop(&xfer->ux_callout); /* XXX wrong place */ 2662 2663 } 2664 2665 static void 2666 xhci_device_ctrl_abort(usbd_xfer_handle xfer) 2667 { 2668 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2669 } 2670 2671 static void 2672 xhci_device_ctrl_close(usbd_pipe_handle pipe) 2673 { 2674 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2675 } 2676 2677 /* ----------------- */ 2678 /* device isochronus */ 2679 2680 /* ----------- */ 2681 /* device bulk */ 2682 2683 static usbd_status 2684 xhci_device_bulk_transfer(usbd_xfer_handle xfer) 2685 { 2686 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2687 usbd_status err; 2688 2689 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2690 2691 /* Insert last in queue. */ 2692 mutex_enter(&sc->sc_lock); 2693 err = usb_insert_transfer(xfer); 2694 mutex_exit(&sc->sc_lock); 2695 if (err) 2696 return err; 2697 2698 /* 2699 * Pipe isn't running (otherwise err would be USBD_INPROG), 2700 * so start it first. 2701 */ 2702 return (xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 2703 } 2704 2705 static usbd_status 2706 xhci_device_bulk_start(usbd_xfer_handle xfer) 2707 { 2708 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2709 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 2710 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 2711 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2712 struct xhci_xfer * const xx = (void *)xfer; 2713 const uint32_t len = xfer->ux_length; 2714 usb_dma_t * const dma = &xfer->ux_dmabuf; 2715 uint64_t parameter; 2716 uint32_t status; 2717 uint32_t control; 2718 u_int i = 0; 2719 2720 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2721 2722 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 2723 2724 if (sc->sc_dying) 2725 return USBD_IOERROR; 2726 2727 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 2728 2729 parameter = DMAADDR(dma, 0); 2730 /* 2731 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 2732 * If the user supplied buffer crosses such a boundary then 2 2733 * (or more) TRB should be used. 2734 * If multiple TRB are used the td_size field must be set correctly. 2735 * For v1.0 devices (like ivy bridge) this is the number of usb data 2736 * blocks needed to complete the transfer. 2737 * Setting it to 1 in the last TRB causes an extra zero-length 2738 * data block be sent. 2739 * The earlier documentation differs, I don't know how it behaves. 2740 */ 2741 KASSERT(len <= 0x10000); 2742 status = XHCI_TRB_2_IRQ_SET(0) | 2743 XHCI_TRB_2_TDSZ_SET(1) | 2744 XHCI_TRB_2_BYTES_SET(len); 2745 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 2746 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 2747 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2748 2749 mutex_enter(&tr->xr_lock); 2750 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2751 mutex_exit(&tr->xr_lock); 2752 2753 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2754 2755 if (sc->sc_bus.ub_usepolling) { 2756 DPRINTFN(1, "polling", 0, 0, 0, 0); 2757 //xhci_waitintr(sc, xfer); 2758 } 2759 2760 return USBD_IN_PROGRESS; 2761 } 2762 2763 static void 2764 xhci_device_bulk_done(usbd_xfer_handle xfer) 2765 { 2766 #ifdef USB_DEBUG 2767 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 2768 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 2769 #endif 2770 const u_int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2771 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2772 2773 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2774 2775 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 2776 2777 callout_stop(&xfer->ux_callout); /* XXX wrong place */ 2778 2779 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 2780 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2781 2782 2783 } 2784 2785 static void 2786 xhci_device_bulk_abort(usbd_xfer_handle xfer) 2787 { 2788 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2789 } 2790 2791 static void 2792 xhci_device_bulk_close(usbd_pipe_handle pipe) 2793 { 2794 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2795 } 2796 2797 /* --------------- */ 2798 /* device intrrupt */ 2799 2800 static usbd_status 2801 xhci_device_intr_transfer(usbd_xfer_handle xfer) 2802 { 2803 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2804 usbd_status err; 2805 2806 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2807 2808 /* Insert last in queue. */ 2809 mutex_enter(&sc->sc_lock); 2810 err = usb_insert_transfer(xfer); 2811 mutex_exit(&sc->sc_lock); 2812 if (err) 2813 return err; 2814 2815 /* 2816 * Pipe isn't running (otherwise err would be USBD_INPROG), 2817 * so start it first. 2818 */ 2819 return (xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 2820 } 2821 2822 static usbd_status 2823 xhci_device_intr_start(usbd_xfer_handle xfer) 2824 { 2825 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2826 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 2827 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 2828 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2829 struct xhci_xfer * const xx = (void *)xfer; 2830 const uint32_t len = xfer->ux_length; 2831 usb_dma_t * const dma = &xfer->ux_dmabuf; 2832 uint64_t parameter; 2833 uint32_t status; 2834 uint32_t control; 2835 u_int i = 0; 2836 2837 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2838 2839 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 2840 2841 if (sc->sc_dying) 2842 return USBD_IOERROR; 2843 2844 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 2845 2846 parameter = DMAADDR(dma, 0); 2847 KASSERT(len <= 0x10000); 2848 status = XHCI_TRB_2_IRQ_SET(0) | 2849 XHCI_TRB_2_TDSZ_SET(1) | 2850 XHCI_TRB_2_BYTES_SET(len); 2851 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 2852 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 2853 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2854 2855 mutex_enter(&tr->xr_lock); 2856 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2857 mutex_exit(&tr->xr_lock); 2858 2859 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2860 2861 if (sc->sc_bus.ub_usepolling) { 2862 DPRINTFN(1, "polling", 0, 0, 0, 0); 2863 //xhci_waitintr(sc, xfer); 2864 } 2865 2866 return USBD_IN_PROGRESS; 2867 } 2868 2869 static void 2870 xhci_device_intr_done(usbd_xfer_handle xfer) 2871 { 2872 struct xhci_softc * const sc __diagused = 2873 xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2874 #ifdef USB_DEBUG 2875 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 2876 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 2877 #endif 2878 const u_int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2879 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2880 2881 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2882 2883 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 2884 2885 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2886 2887 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 2888 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2889 2890 #if 0 2891 device_printf(sc->sc_dev, ""); 2892 for (size_t i = 0; i < xfer->ux_length; i++) { 2893 printf(" %02x", ((uint8_t const *)xfer->ux_buffer)[i]); 2894 } 2895 printf("\n"); 2896 #endif 2897 2898 if (xfer->ux_pipe->up_repeat) { 2899 xfer->ux_status = xhci_device_intr_start(xfer); 2900 } else { 2901 callout_stop(&xfer->ux_callout); /* XXX */ 2902 } 2903 2904 } 2905 2906 static void 2907 xhci_device_intr_abort(usbd_xfer_handle xfer) 2908 { 2909 struct xhci_softc * const sc __diagused = 2910 xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2911 2912 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2913 2914 KASSERT(mutex_owned(&sc->sc_lock)); 2915 DPRINTFN(15, "%p", xfer, 0, 0, 0); 2916 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2917 xfer->ux_status = USBD_CANCELLED; 2918 usb_transfer_complete(xfer); 2919 } 2920 2921 static void 2922 xhci_device_intr_close(usbd_pipe_handle pipe) 2923 { 2924 //struct xhci_softc * const sc = pipe->up_dev->ud_bus->ub_hcpriv; 2925 2926 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2927 DPRINTFN(15, "%p", pipe, 0, 0, 0); 2928 2929 xhci_unconfigure_endpoint(pipe); 2930 } 2931 2932 /* ------------ */ 2933 2934 static void 2935 xhci_timeout(void *addr) 2936 { 2937 struct xhci_xfer * const xx = addr; 2938 usbd_xfer_handle const xfer = &xx->xx_xfer; 2939 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2940 2941 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2942 2943 if (sc->sc_dying) { 2944 return; 2945 } 2946 2947 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 2948 USB_TASKQ_MPSAFE); 2949 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 2950 USB_TASKQ_HC); 2951 } 2952 2953 static void 2954 xhci_timeout_task(void *addr) 2955 { 2956 usbd_xfer_handle const xfer = addr; 2957 struct xhci_softc * const sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2958 2959 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2960 2961 mutex_enter(&sc->sc_lock); 2962 #if 0 2963 xhci_abort_xfer(xfer, USBD_TIMEOUT); 2964 #else 2965 xfer->ux_status = USBD_TIMEOUT; 2966 usb_transfer_complete(xfer); 2967 #endif 2968 mutex_exit(&sc->sc_lock); 2969 } 2970
Indexes created Wed Oct 01 18:09:54 GMT 2025