xhci.c revision 1.28.2.83
1 /* $NetBSD: xhci.c,v 1.28.2.83 2017/01/02 16:55:50 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.28.2.83 2017/01/02 16:55:50 skrll Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static void xhci_host_dequeue(struct xhci_ring * const); 146 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 147 148 static usbd_status xhci_do_command(struct xhci_softc * const, 149 struct xhci_trb * const, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 153 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 154 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 155 static usbd_status xhci_enable_slot(struct xhci_softc * const, 156 uint8_t * const); 157 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 158 static usbd_status xhci_address_device(struct xhci_softc * const, 159 uint64_t, uint8_t, bool); 160 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 161 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 162 struct xhci_slot * const, u_int); 163 static usbd_status xhci_ring_init(struct xhci_softc * const, 164 struct xhci_ring * const, size_t, size_t); 165 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 166 167 static void xhci_setup_ctx(struct usbd_pipe *); 168 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 169 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 170 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 171 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 172 173 static void xhci_noop(struct usbd_pipe *); 174 175 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 176 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 177 static void xhci_root_intr_abort(struct usbd_xfer *); 178 static void xhci_root_intr_close(struct usbd_pipe *); 179 static void xhci_root_intr_done(struct usbd_xfer *); 180 181 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 182 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 183 static void xhci_device_ctrl_abort(struct usbd_xfer *); 184 static void xhci_device_ctrl_close(struct usbd_pipe *); 185 static void xhci_device_ctrl_done(struct usbd_xfer *); 186 187 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 188 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 189 static void xhci_device_intr_abort(struct usbd_xfer *); 190 static void xhci_device_intr_close(struct usbd_pipe *); 191 static void xhci_device_intr_done(struct usbd_xfer *); 192 193 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 194 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 195 static void xhci_device_bulk_abort(struct usbd_xfer *); 196 static void xhci_device_bulk_close(struct usbd_pipe *); 197 static void xhci_device_bulk_done(struct usbd_xfer *); 198 199 static void xhci_timeout(void *); 200 static void xhci_timeout_task(void *); 201 202 static const struct usbd_bus_methods xhci_bus_methods = { 203 .ubm_open = xhci_open, 204 .ubm_softint = xhci_softintr, 205 .ubm_dopoll = xhci_poll, 206 .ubm_allocx = xhci_allocx, 207 .ubm_freex = xhci_freex, 208 .ubm_getlock = xhci_get_lock, 209 .ubm_newdev = xhci_new_device, 210 .ubm_rhctrl = xhci_roothub_ctrl, 211 }; 212 213 static const struct usbd_pipe_methods xhci_root_intr_methods = { 214 .upm_transfer = xhci_root_intr_transfer, 215 .upm_start = xhci_root_intr_start, 216 .upm_abort = xhci_root_intr_abort, 217 .upm_close = xhci_root_intr_close, 218 .upm_cleartoggle = xhci_noop, 219 .upm_done = xhci_root_intr_done, 220 }; 221 222 223 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 224 .upm_transfer = xhci_device_ctrl_transfer, 225 .upm_start = xhci_device_ctrl_start, 226 .upm_abort = xhci_device_ctrl_abort, 227 .upm_close = xhci_device_ctrl_close, 228 .upm_cleartoggle = xhci_noop, 229 .upm_done = xhci_device_ctrl_done, 230 }; 231 232 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 233 .upm_cleartoggle = xhci_noop, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 237 .upm_transfer = xhci_device_bulk_transfer, 238 .upm_start = xhci_device_bulk_start, 239 .upm_abort = xhci_device_bulk_abort, 240 .upm_close = xhci_device_bulk_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_bulk_done, 243 }; 244 245 static const struct usbd_pipe_methods xhci_device_intr_methods = { 246 .upm_transfer = xhci_device_intr_transfer, 247 .upm_start = xhci_device_intr_start, 248 .upm_abort = xhci_device_intr_abort, 249 .upm_close = xhci_device_intr_close, 250 .upm_cleartoggle = xhci_noop, 251 .upm_done = xhci_device_intr_done, 252 }; 253 254 static inline uint32_t 255 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 256 { 257 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 258 } 259 260 static inline uint32_t 261 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 262 { 263 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 264 } 265 266 static inline void 267 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 268 uint32_t value) 269 { 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 271 } 272 273 #if 0 /* unused */ 274 static inline void 275 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 276 uint32_t value) 277 { 278 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 279 } 280 #endif /* unused */ 281 282 static inline uint32_t 283 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 284 { 285 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 286 } 287 288 static inline uint32_t 289 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 290 { 291 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 292 } 293 294 static inline void 295 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 296 uint32_t value) 297 { 298 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 299 } 300 301 static inline uint64_t 302 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 303 { 304 uint64_t value; 305 306 if (sc->sc_ac64) { 307 #ifdef XHCI_USE_BUS_SPACE_8 308 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 309 #else 310 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 311 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 312 offset + 4) << 32; 313 #endif 314 } else { 315 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 316 } 317 318 return value; 319 } 320 321 static inline void 322 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 336 } 337 } 338 339 static inline uint32_t 340 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 341 { 342 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 343 } 344 345 static inline void 346 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 347 uint32_t value) 348 { 349 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 350 } 351 352 #if 0 /* unused */ 353 static inline uint64_t 354 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 355 { 356 uint64_t value; 357 358 if (sc->sc_ac64) { 359 #ifdef XHCI_USE_BUS_SPACE_8 360 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 361 #else 362 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 363 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 364 offset + 4) << 32; 365 #endif 366 } else { 367 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 368 } 369 370 return value; 371 } 372 #endif /* unused */ 373 374 static inline void 375 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 376 uint64_t value) 377 { 378 if (sc->sc_ac64) { 379 #ifdef XHCI_USE_BUS_SPACE_8 380 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 381 #else 382 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 383 (value >> 0) & 0xffffffff); 384 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 385 (value >> 32) & 0xffffffff); 386 #endif 387 } else { 388 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 389 } 390 } 391 392 #if 0 /* unused */ 393 static inline uint32_t 394 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 395 { 396 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 397 } 398 #endif /* unused */ 399 400 static inline void 401 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 402 uint32_t value) 403 { 404 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 405 } 406 407 /* --- */ 408 409 static inline uint8_t 410 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 411 { 412 u_int eptype = 0; 413 414 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 415 case UE_CONTROL: 416 eptype = 0x0; 417 break; 418 case UE_ISOCHRONOUS: 419 eptype = 0x1; 420 break; 421 case UE_BULK: 422 eptype = 0x2; 423 break; 424 case UE_INTERRUPT: 425 eptype = 0x3; 426 break; 427 } 428 429 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 430 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 431 return eptype | 0x4; 432 else 433 return eptype; 434 } 435 436 static u_int 437 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 438 { 439 /* xHCI 1.0 section 4.5.1 */ 440 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 441 u_int in = 0; 442 443 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 444 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 445 in = 1; 446 447 return epaddr * 2 + in; 448 } 449 450 static inline u_int 451 xhci_dci_to_ici(const u_int i) 452 { 453 return i + 1; 454 } 455 456 static inline void * 457 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 458 const u_int dci) 459 { 460 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 461 } 462 463 #if 0 /* unused */ 464 static inline bus_addr_t 465 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 466 const u_int dci) 467 { 468 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 469 } 470 #endif /* unused */ 471 472 static inline void * 473 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline bus_addr_t 480 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 481 const u_int ici) 482 { 483 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 484 } 485 486 static inline struct xhci_trb * 487 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 488 { 489 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 490 } 491 492 static inline bus_addr_t 493 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 494 { 495 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 496 } 497 498 static inline void 499 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 500 uint32_t control) 501 { 502 trb->trb_0 = htole64(parameter); 503 trb->trb_2 = htole32(status); 504 trb->trb_3 = htole32(control); 505 } 506 507 static int 508 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 509 { 510 /* base address of TRBs */ 511 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 512 513 /* trb_0 range sanity check */ 514 if (trb_0 == 0 || trb_0 < trbp || 515 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 516 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 517 return 1; 518 } 519 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 520 return 0; 521 } 522 523 static unsigned int 524 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 525 u_int dci) 526 { 527 uint32_t *cp; 528 529 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 530 cp = xhci_slot_get_dcv(sc, xs, dci); 531 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 532 } 533 534 static inline unsigned int 535 xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport) 536 { 537 const unsigned int port = ctlrport - 1; 538 const uint8_t bit = __BIT(port % NBBY); 539 540 return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit); 541 } 542 543 /* 544 * Return the roothub port for a controller port. Both are 1..n. 545 */ 546 static inline unsigned int 547 xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport) 548 { 549 550 return sc->sc_ctlrportmap[ctrlport - 1]; 551 } 552 553 /* 554 * Return the controller port for a bus roothub port. Both are 1..n. 555 */ 556 static inline unsigned int 557 xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn, 558 unsigned int rhport) 559 { 560 561 return sc->sc_rhportmap[bn][rhport - 1]; 562 } 563 564 /* --- */ 565 566 void 567 xhci_childdet(device_t self, device_t child) 568 { 569 struct xhci_softc * const sc = device_private(self); 570 571 KASSERT(sc->sc_child == child); 572 if (child == sc->sc_child) 573 sc->sc_child = NULL; 574 } 575 576 int 577 xhci_detach(struct xhci_softc *sc, int flags) 578 { 579 int rv = 0; 580 581 if (sc->sc_child2 != NULL) { 582 rv = config_detach(sc->sc_child2, flags); 583 if (rv != 0) 584 return rv; 585 } 586 587 if (sc->sc_child != NULL) { 588 rv = config_detach(sc->sc_child, flags); 589 if (rv != 0) 590 return rv; 591 } 592 593 /* XXX unconfigure/free slots */ 594 595 /* verify: */ 596 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 597 xhci_op_write_4(sc, XHCI_USBCMD, 0); 598 /* do we need to wait for stop? */ 599 600 xhci_op_write_8(sc, XHCI_CRCR, 0); 601 xhci_ring_free(sc, &sc->sc_cr); 602 cv_destroy(&sc->sc_command_cv); 603 cv_destroy(&sc->sc_cmdbusy_cv); 604 605 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 606 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 607 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 608 xhci_ring_free(sc, &sc->sc_er); 609 610 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 611 612 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 613 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 614 615 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 616 617 kmem_free(sc->sc_ctlrportbus, sc->sc_maxports * sizeof(uint8_t) / NBBY); 618 kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int)); 619 620 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 621 kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int)); 622 } 623 624 mutex_destroy(&sc->sc_lock); 625 mutex_destroy(&sc->sc_intr_lock); 626 627 pool_cache_destroy(sc->sc_xferpool); 628 629 return rv; 630 } 631 632 int 633 xhci_activate(device_t self, enum devact act) 634 { 635 struct xhci_softc * const sc = device_private(self); 636 637 switch (act) { 638 case DVACT_DEACTIVATE: 639 sc->sc_dying = true; 640 return 0; 641 default: 642 return EOPNOTSUPP; 643 } 644 } 645 646 bool 647 xhci_suspend(device_t dv, const pmf_qual_t *qual) 648 { 649 return false; 650 } 651 652 bool 653 xhci_resume(device_t dv, const pmf_qual_t *qual) 654 { 655 return false; 656 } 657 658 bool 659 xhci_shutdown(device_t self, int flags) 660 { 661 return false; 662 } 663 664 static int 665 xhci_hc_reset(struct xhci_softc * const sc) 666 { 667 uint32_t usbcmd, usbsts; 668 int i; 669 670 /* Check controller not ready */ 671 for (i = 0; i < XHCI_WAIT_CNR; i++) { 672 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 673 if ((usbsts & XHCI_STS_CNR) == 0) 674 break; 675 usb_delay_ms(&sc->sc_bus, 1); 676 } 677 if (i >= XHCI_WAIT_CNR) { 678 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 679 return EIO; 680 } 681 682 /* Halt controller */ 683 usbcmd = 0; 684 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 685 usb_delay_ms(&sc->sc_bus, 1); 686 687 /* Reset controller */ 688 usbcmd = XHCI_CMD_HCRST; 689 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 690 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 691 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 692 if ((usbcmd & XHCI_CMD_HCRST) == 0) 693 break; 694 usb_delay_ms(&sc->sc_bus, 1); 695 } 696 if (i >= XHCI_WAIT_HCRST) { 697 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 698 return EIO; 699 } 700 701 /* Check controller not ready */ 702 for (i = 0; i < XHCI_WAIT_CNR; i++) { 703 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 704 if ((usbsts & XHCI_STS_CNR) == 0) 705 break; 706 usb_delay_ms(&sc->sc_bus, 1); 707 } 708 if (i >= XHCI_WAIT_CNR) { 709 aprint_error_dev(sc->sc_dev, 710 "controller not ready timeout after reset\n"); 711 return EIO; 712 } 713 714 return 0; 715 } 716 717 718 static void 719 hexdump(const char *msg, const void *base, size_t len) 720 { 721 #if 0 722 size_t cnt; 723 const uint32_t *p; 724 extern paddr_t vtophys(vaddr_t); 725 726 p = base; 727 cnt = 0; 728 729 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 730 (void *)vtophys((vaddr_t)base)); 731 732 while (cnt < len) { 733 if (cnt % 16 == 0) 734 printf("%p: ", p); 735 else if (cnt % 8 == 0) 736 printf(" |"); 737 printf(" %08x", *p++); 738 cnt += 4; 739 if (cnt % 16 == 0) 740 printf("\n"); 741 } 742 if (cnt % 16 != 0) 743 printf("\n"); 744 #endif 745 } 746 747 /* 7.2 xHCI Support Protocol Capability */ 748 static void 749 xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp) 750 { 751 /* XXX Cache this lot */ 752 753 const uint32_t w0 = xhci_read_4(sc, ecp); 754 const uint32_t w4 = xhci_read_4(sc, ecp + 4); 755 const uint32_t w8 = xhci_read_4(sc, ecp + 8); 756 const uint32_t wc = xhci_read_4(sc, ecp + 0xc); 757 758 aprint_debug_dev(sc->sc_dev, 759 " SP: %08x %08x %08x %08x\n", w0, w4, w8, wc); 760 761 if (w4 != XHCI_XECP_USBID) 762 return; 763 764 const int major = XHCI_XECP_SP_W0_MAJOR(w0); 765 const int minor = XHCI_XECP_SP_W0_MINOR(w0); 766 const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8); 767 const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8); 768 769 const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16)); 770 switch (mm) { 771 case 0x0200: 772 case 0x0300: 773 case 0x0301: 774 aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n", 775 major == 3 ? "ss" : "hs", cpo, cpo + cpc -1); 776 break; 777 default: 778 aprint_debug_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n", 779 major, minor); 780 return; 781 } 782 783 const size_t bus = (major == 3) ? 0 : 1; 784 785 /* Index arrays with 0..n-1 where ports are numbered 1..n */ 786 for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) { 787 if (sc->sc_ctlrportmap[cp] != 0) { 788 aprint_error_dev(sc->sc_dev, "contoller port %zu " 789 "already assigned", cp); 790 continue; 791 } 792 793 sc->sc_ctlrportbus[cp / NBBY] |= 794 bus == 0 ? 0 : __BIT(cp % NBBY); 795 796 const size_t rhp = sc->sc_rhportcount[bus]++; 797 798 KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0, 799 "bus %zu rhp %zu is %d", bus, rhp, 800 sc->sc_rhportmap[bus][rhp]); 801 802 sc->sc_rhportmap[bus][rhp] = cp + 1; 803 sc->sc_ctlrportmap[cp] = rhp + 1; 804 } 805 } 806 807 /* Process extended capabilities */ 808 static void 809 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 810 { 811 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 812 813 bus_size_t ecp = XHCI_HCC_XECP(hcc) * 4; 814 while (ecp != 0) { 815 uint32_t ecr = xhci_read_4(sc, ecp); 816 aprint_debug_dev(sc->sc_dev, "ECR %lx: %08x\n", ecp, ecr); 817 switch (XHCI_XECP_ID(ecr)) { 818 case XHCI_ID_PROTOCOLS: { 819 xhci_id_protocols(sc, ecp); 820 break; 821 } 822 case XHCI_ID_USB_LEGACY: { 823 uint8_t bios_sem; 824 825 /* Take host controller ownership from BIOS */ 826 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 827 if (bios_sem) { 828 /* sets xHCI to be owned by OS */ 829 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 830 aprint_debug_dev(sc->sc_dev, 831 "waiting for BIOS to give up control\n"); 832 for (int i = 0; i < 5000; i++) { 833 bios_sem = xhci_read_1(sc, ecp + 834 XHCI_XECP_BIOS_SEM); 835 if (bios_sem == 0) 836 break; 837 DELAY(1000); 838 } 839 if (bios_sem) { 840 aprint_error_dev(sc->sc_dev, 841 "timed out waiting for BIOS\n"); 842 } 843 } 844 break; 845 } 846 default: 847 break; 848 } 849 ecr = xhci_read_4(sc, ecp); 850 if (XHCI_XECP_NEXT(ecr) == 0) { 851 ecp = 0; 852 } else { 853 ecp += XHCI_XECP_NEXT(ecr) * 4; 854 } 855 } 856 } 857 858 #define XHCI_HCCPREV1_BITS \ 859 "\177\020" /* New bitmask */ \ 860 "f\020\020XECP\0" \ 861 "f\014\4MAXPSA\0" \ 862 "b\013CFC\0" \ 863 "b\012SEC\0" \ 864 "b\011SBD\0" \ 865 "b\010FSE\0" \ 866 "b\7NSS\0" \ 867 "b\6LTC\0" \ 868 "b\5LHRC\0" \ 869 "b\4PIND\0" \ 870 "b\3PPC\0" \ 871 "b\2CZC\0" \ 872 "b\1BNC\0" \ 873 "b\0AC64\0" \ 874 "\0" 875 #define XHCI_HCCV1_x_BITS \ 876 "\177\020" /* New bitmask */ \ 877 "f\020\020XECP\0" \ 878 "f\014\4MAXPSA\0" \ 879 "b\013CFC\0" \ 880 "b\012SEC\0" \ 881 "b\011SPC\0" \ 882 "b\010PAE\0" \ 883 "b\7NSS\0" \ 884 "b\6LTC\0" \ 885 "b\5LHRC\0" \ 886 "b\4PIND\0" \ 887 "b\3PPC\0" \ 888 "b\2CSZ\0" \ 889 "b\1BNC\0" \ 890 "b\0AC64\0" \ 891 "\0" 892 893 int 894 xhci_init(struct xhci_softc *sc) 895 { 896 bus_size_t bsz; 897 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 898 uint32_t pagesize, config; 899 int i = 0; 900 uint16_t hciversion; 901 uint8_t caplength; 902 903 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 904 905 /* Set up the bus struct for the usb 3 and usb 2 buses */ 906 sc->sc_bus.ub_methods = &xhci_bus_methods; 907 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 908 sc->sc_bus.ub_revision = USBREV_3_0; 909 sc->sc_bus.ub_usedma = true; 910 sc->sc_bus.ub_hcpriv = sc; 911 912 sc->sc_bus2.ub_methods = &xhci_bus_methods; 913 sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe); 914 sc->sc_bus2.ub_revision = USBREV_2_0; 915 sc->sc_bus2.ub_usedma = true; 916 sc->sc_bus2.ub_hcpriv = sc; 917 sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag; 918 919 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 920 caplength = XHCI_CAP_CAPLENGTH(cap); 921 hciversion = XHCI_CAP_HCIVERSION(cap); 922 923 if (hciversion < XHCI_HCIVERSION_0_96 || 924 hciversion > XHCI_HCIVERSION_1_0) { 925 aprint_normal_dev(sc->sc_dev, 926 "xHCI version %x.%x not known to be supported\n", 927 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 928 } else { 929 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 930 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 931 } 932 933 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 934 &sc->sc_cbh) != 0) { 935 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 936 return ENOMEM; 937 } 938 939 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 940 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 941 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 942 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 943 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 944 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 945 aprint_debug_dev(sc->sc_dev, 946 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 947 948 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 949 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 950 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 951 952 char sbuf[128]; 953 if (hciversion < XHCI_HCIVERSION_1_0) 954 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 955 else 956 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 957 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 958 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 959 960 /* default all ports to bus 0, i.e. usb 3 */ 961 sc->sc_ctlrportbus = kmem_zalloc(sc->sc_maxports * sizeof(uint8_t) / NBBY, KM_SLEEP); 962 sc->sc_ctlrportmap = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 963 964 /* controller port to bus roothub port map */ 965 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 966 sc->sc_rhportmap[j] = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 967 } 968 969 /* 970 * Process all Extended Capabilities 971 */ 972 xhci_ecp(sc, hcc); 973 974 bsz = XHCI_PORTSC(sc->sc_maxports); 975 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 976 &sc->sc_obh) != 0) { 977 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 978 return ENOMEM; 979 } 980 981 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 982 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 983 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 984 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 985 return ENOMEM; 986 } 987 988 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 989 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 990 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 991 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 992 return ENOMEM; 993 } 994 995 int rv; 996 rv = xhci_hc_reset(sc); 997 if (rv != 0) { 998 return rv; 999 } 1000 1001 if (sc->sc_vendor_init) 1002 sc->sc_vendor_init(sc); 1003 1004 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 1005 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 1006 pagesize = ffs(pagesize); 1007 if (pagesize == 0) { 1008 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 1009 return EIO; 1010 } 1011 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 1012 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 1013 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 1014 (uint32_t)sc->sc_maxslots); 1015 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 1016 1017 usbd_status err; 1018 1019 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 1020 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 1021 if (sc->sc_maxspbuf != 0) { 1022 err = usb_allocmem(&sc->sc_bus, 1023 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 1024 &sc->sc_spbufarray_dma); 1025 if (err) { 1026 aprint_error_dev(sc->sc_dev, 1027 "spbufarray init fail, err %d\n", err); 1028 return ENOMEM; 1029 } 1030 1031 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 1032 sc->sc_maxspbuf, KM_SLEEP); 1033 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 1034 for (i = 0; i < sc->sc_maxspbuf; i++) { 1035 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 1036 /* allocate contexts */ 1037 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 1038 sc->sc_pgsz, dma); 1039 if (err) { 1040 aprint_error_dev(sc->sc_dev, 1041 "spbufarray_dma init fail, err %d\n", err); 1042 rv = ENOMEM; 1043 goto bad1; 1044 } 1045 spbufarray[i] = htole64(DMAADDR(dma, 0)); 1046 usb_syncmem(dma, 0, sc->sc_pgsz, 1047 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1048 } 1049 1050 usb_syncmem(&sc->sc_spbufarray_dma, 0, 1051 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 1052 } 1053 1054 config = xhci_op_read_4(sc, XHCI_CONFIG); 1055 config &= ~0xFF; 1056 config |= sc->sc_maxslots & 0xFF; 1057 xhci_op_write_4(sc, XHCI_CONFIG, config); 1058 1059 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 1060 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 1061 if (err) { 1062 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 1063 err); 1064 rv = ENOMEM; 1065 goto bad1; 1066 } 1067 1068 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 1069 XHCI_EVENT_RING_SEGMENTS_ALIGN); 1070 if (err) { 1071 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 1072 err); 1073 rv = ENOMEM; 1074 goto bad2; 1075 } 1076 1077 usb_dma_t *dma; 1078 size_t size; 1079 size_t align; 1080 1081 dma = &sc->sc_eventst_dma; 1082 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 1083 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 1084 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 1085 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 1086 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1087 if (err) { 1088 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 1089 err); 1090 rv = ENOMEM; 1091 goto bad3; 1092 } 1093 1094 memset(KERNADDR(dma, 0), 0, size); 1095 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1096 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 1097 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 1098 KERNADDR(&sc->sc_eventst_dma, 0), 1099 sc->sc_eventst_dma.udma_block->size); 1100 1101 dma = &sc->sc_dcbaa_dma; 1102 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 1103 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 1104 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 1105 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1106 if (err) { 1107 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1108 rv = ENOMEM; 1109 goto bad4; 1110 } 1111 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 1112 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1113 KERNADDR(&sc->sc_dcbaa_dma, 0), 1114 sc->sc_dcbaa_dma.udma_block->size); 1115 1116 memset(KERNADDR(dma, 0), 0, size); 1117 if (sc->sc_maxspbuf != 0) { 1118 /* 1119 * DCBA entry 0 hold the scratchbuf array pointer. 1120 */ 1121 *(uint64_t *)KERNADDR(dma, 0) = 1122 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1123 } 1124 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1125 1126 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1127 KM_SLEEP); 1128 if (sc->sc_slots == NULL) { 1129 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1130 rv = ENOMEM; 1131 goto bad; 1132 } 1133 1134 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1135 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1136 if (sc->sc_xferpool == NULL) { 1137 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1138 err); 1139 rv = ENOMEM; 1140 goto bad; 1141 } 1142 1143 cv_init(&sc->sc_command_cv, "xhcicmd"); 1144 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1145 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1146 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1147 1148 struct xhci_erste *erst; 1149 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1150 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1151 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1152 erst[0].erste_3 = htole32(0); 1153 usb_syncmem(&sc->sc_eventst_dma, 0, 1154 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1155 1156 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1157 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1158 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1159 XHCI_ERDP_LO_BUSY); 1160 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1161 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1162 sc->sc_cr.xr_cs); 1163 1164 #if 0 1165 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1166 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1167 #endif 1168 1169 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1170 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1171 /* Intel xhci needs interrupt rate moderated. */ 1172 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1173 else 1174 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1175 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 1176 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1177 1178 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 1179 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1180 xhci_op_read_4(sc, XHCI_USBCMD)); 1181 1182 return 0; 1183 1184 bad: 1185 if (sc->sc_xferpool) { 1186 pool_cache_destroy(sc->sc_xferpool); 1187 sc->sc_xferpool = NULL; 1188 } 1189 1190 if (sc->sc_slots) { 1191 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1192 sc->sc_maxslots); 1193 sc->sc_slots = NULL; 1194 } 1195 1196 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1197 bad4: 1198 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1199 bad3: 1200 xhci_ring_free(sc, &sc->sc_er); 1201 bad2: 1202 xhci_ring_free(sc, &sc->sc_cr); 1203 i = sc->sc_maxspbuf; 1204 bad1: 1205 for (int j = 0; j < i; j++) 1206 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1207 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1208 1209 return rv; 1210 } 1211 1212 int 1213 xhci_intr(void *v) 1214 { 1215 struct xhci_softc * const sc = v; 1216 int ret = 0; 1217 1218 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1219 1220 if (sc == NULL) 1221 return 0; 1222 1223 mutex_spin_enter(&sc->sc_intr_lock); 1224 1225 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1226 goto done; 1227 1228 /* If we get an interrupt while polling, then just ignore it. */ 1229 if (sc->sc_bus.ub_usepolling) { 1230 #ifdef DIAGNOSTIC 1231 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1232 #endif 1233 goto done; 1234 } 1235 1236 ret = xhci_intr1(sc); 1237 done: 1238 mutex_spin_exit(&sc->sc_intr_lock); 1239 return ret; 1240 } 1241 1242 int 1243 xhci_intr1(struct xhci_softc * const sc) 1244 { 1245 uint32_t usbsts; 1246 uint32_t iman; 1247 1248 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1249 1250 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1251 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1252 #if 0 1253 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1254 return 0; 1255 } 1256 #endif 1257 xhci_op_write_4(sc, XHCI_USBSTS, 1258 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1259 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1260 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1261 1262 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1263 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1264 iman |= XHCI_IMAN_INTR_PEND; 1265 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1266 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1267 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1268 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1269 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1270 1271 usb_schedsoftintr(&sc->sc_bus); 1272 1273 return 1; 1274 } 1275 1276 /* 1277 * 3 port speed types used in USB stack 1278 * 1279 * usbdi speed 1280 * definition: USB_SPEED_* in usb.h 1281 * They are used in struct usbd_device in USB stack. 1282 * ioctl interface uses these values too. 1283 * port_status speed 1284 * definition: UPS_*_SPEED in usb.h 1285 * They are used in usb_port_status_t and valid only for USB 2.0. 1286 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1287 * of usb_port_status_ext_t indicates port speed. 1288 * Note that some 3.0 values overlap with 2.0 values. 1289 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1290 * means UPS_LOW_SPEED in HS.) 1291 * port status returned from hub also uses these values. 1292 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1293 * or more. 1294 * xspeed: 1295 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1296 * They are used in only slot context and PORTSC reg of xhci. 1297 * The difference between usbdi speed and xspeed is 1298 * that FS and LS values are swapped. 1299 */ 1300 1301 /* convert usbdi speed to xspeed */ 1302 static int 1303 xhci_speed2xspeed(int speed) 1304 { 1305 switch (speed) { 1306 case USB_SPEED_LOW: return 2; 1307 case USB_SPEED_FULL: return 1; 1308 default: return speed; 1309 } 1310 } 1311 1312 #if 0 1313 /* convert xspeed to usbdi speed */ 1314 static int 1315 xhci_xspeed2speed(int xspeed) 1316 { 1317 switch (xspeed) { 1318 case 1: return USB_SPEED_FULL; 1319 case 2: return USB_SPEED_LOW; 1320 default: return xspeed; 1321 } 1322 } 1323 #endif 1324 1325 /* convert xspeed to port status speed */ 1326 static int 1327 xhci_xspeed2psspeed(int xspeed) 1328 { 1329 switch (xspeed) { 1330 case 0: return 0; 1331 case 1: return UPS_FULL_SPEED; 1332 case 2: return UPS_LOW_SPEED; 1333 case 3: return UPS_HIGH_SPEED; 1334 default: return UPS_OTHER_SPEED; 1335 } 1336 } 1337 1338 /* 1339 * Construct input contexts and issue TRB to open pipe. 1340 */ 1341 static usbd_status 1342 xhci_configure_endpoint(struct usbd_pipe *pipe) 1343 { 1344 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1345 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1346 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1347 struct xhci_trb trb; 1348 usbd_status err; 1349 1350 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1351 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1352 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1353 pipe->up_endpoint->ue_edesc->bmAttributes); 1354 1355 /* XXX ensure input context is available? */ 1356 1357 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1358 1359 /* set up context */ 1360 xhci_setup_ctx(pipe); 1361 1362 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1363 sc->sc_ctxsz * 1); 1364 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1365 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1366 1367 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1368 trb.trb_2 = 0; 1369 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1370 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1371 1372 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1373 1374 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1375 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1376 sc->sc_ctxsz * 1); 1377 1378 return err; 1379 } 1380 1381 #if 0 1382 static usbd_status 1383 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1384 { 1385 #ifdef USB_DEBUG 1386 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1387 #endif 1388 1389 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1390 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1391 1392 return USBD_NORMAL_COMPLETION; 1393 } 1394 #endif 1395 1396 /* 4.6.8, 6.4.3.7 */ 1397 static usbd_status 1398 xhci_reset_endpoint_locked(struct usbd_pipe *pipe) 1399 { 1400 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1401 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1402 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1403 struct xhci_trb trb; 1404 usbd_status err; 1405 1406 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1407 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1408 1409 KASSERT(mutex_owned(&sc->sc_lock)); 1410 1411 trb.trb_0 = 0; 1412 trb.trb_2 = 0; 1413 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1414 XHCI_TRB_3_EP_SET(dci) | 1415 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1416 1417 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1418 1419 return err; 1420 } 1421 1422 static usbd_status 1423 xhci_reset_endpoint(struct usbd_pipe *pipe) 1424 { 1425 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1426 1427 mutex_enter(&sc->sc_lock); 1428 usbd_status ret = xhci_reset_endpoint_locked(pipe); 1429 mutex_exit(&sc->sc_lock); 1430 1431 return ret; 1432 } 1433 1434 /* 1435 * 4.6.9, 6.4.3.8 1436 * Stop execution of TDs on xfer ring. 1437 * Should be called with sc_lock held. 1438 */ 1439 static usbd_status 1440 xhci_stop_endpoint(struct usbd_pipe *pipe) 1441 { 1442 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1443 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1444 struct xhci_trb trb; 1445 usbd_status err; 1446 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1447 1448 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1449 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1450 1451 KASSERT(mutex_owned(&sc->sc_lock)); 1452 1453 trb.trb_0 = 0; 1454 trb.trb_2 = 0; 1455 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1456 XHCI_TRB_3_EP_SET(dci) | 1457 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1458 1459 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1460 1461 return err; 1462 } 1463 1464 /* 1465 * Set TR Dequeue Pointer. 1466 * xHCI 1.1 4.6.10 6.4.3.9 1467 * Purge all of the TRBs on ring and reinitialize ring. 1468 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1469 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1470 * error will be generated. 1471 */ 1472 static usbd_status 1473 xhci_set_dequeue_locked(struct usbd_pipe *pipe) 1474 { 1475 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1476 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1477 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1478 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1479 struct xhci_trb trb; 1480 usbd_status err; 1481 1482 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1483 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1484 1485 KASSERT(mutex_owned(&sc->sc_lock)); 1486 1487 xhci_host_dequeue(xr); 1488 1489 /* set DCS */ 1490 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1491 trb.trb_2 = 0; 1492 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1493 XHCI_TRB_3_EP_SET(dci) | 1494 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1495 1496 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1497 1498 return err; 1499 } 1500 1501 static usbd_status 1502 xhci_set_dequeue(struct usbd_pipe *pipe) 1503 { 1504 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1505 1506 mutex_enter(&sc->sc_lock); 1507 usbd_status ret = xhci_set_dequeue_locked(pipe); 1508 mutex_exit(&sc->sc_lock); 1509 1510 return ret; 1511 } 1512 1513 /* 1514 * Open new pipe: called from usbd_setup_pipe_flags. 1515 * Fills methods of pipe. 1516 * If pipe is not for ep0, calls configure_endpoint. 1517 */ 1518 static usbd_status 1519 xhci_open(struct usbd_pipe *pipe) 1520 { 1521 struct usbd_device * const dev = pipe->up_dev; 1522 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1523 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1524 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1525 1526 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1527 DPRINTFN(1, "addr %d depth %d port %d speed %d", dev->ud_addr, 1528 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1529 DPRINTFN(1, " dci %u type 0x%02x epaddr 0x%02x attr 0x%02x", 1530 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1531 ed->bmAttributes); 1532 DPRINTFN(1, " mps %u ival %u", UGETW(ed->wMaxPacketSize), ed->bInterval, 1533 0, 0); 1534 1535 if (sc->sc_dying) 1536 return USBD_IOERROR; 1537 1538 /* Root Hub */ 1539 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1540 switch (ed->bEndpointAddress) { 1541 case USB_CONTROL_ENDPOINT: 1542 pipe->up_methods = &roothub_ctrl_methods; 1543 break; 1544 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1545 pipe->up_methods = &xhci_root_intr_methods; 1546 break; 1547 default: 1548 pipe->up_methods = NULL; 1549 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1550 ed->bEndpointAddress, 0, 0, 0); 1551 return USBD_INVAL; 1552 } 1553 return USBD_NORMAL_COMPLETION; 1554 } 1555 1556 switch (xfertype) { 1557 case UE_CONTROL: 1558 pipe->up_methods = &xhci_device_ctrl_methods; 1559 break; 1560 case UE_ISOCHRONOUS: 1561 pipe->up_methods = &xhci_device_isoc_methods; 1562 return USBD_INVAL; 1563 break; 1564 case UE_BULK: 1565 pipe->up_methods = &xhci_device_bulk_methods; 1566 break; 1567 case UE_INTERRUPT: 1568 pipe->up_methods = &xhci_device_intr_methods; 1569 break; 1570 default: 1571 return USBD_IOERROR; 1572 break; 1573 } 1574 1575 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1576 return xhci_configure_endpoint(pipe); 1577 1578 return USBD_NORMAL_COMPLETION; 1579 } 1580 1581 /* 1582 * Closes pipe, called from usbd_kill_pipe via close methods. 1583 * If the endpoint to be closed is ep0, disable_slot. 1584 * Should be called with sc_lock held. 1585 */ 1586 static void 1587 xhci_close_pipe(struct usbd_pipe *pipe) 1588 { 1589 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1590 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1591 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1592 const u_int dci = xhci_ep_get_dci(ed); 1593 struct xhci_trb trb; 1594 uint32_t *cp; 1595 1596 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1597 1598 if (sc->sc_dying) 1599 return; 1600 1601 /* xs is uninitialized before xhci_init_slot */ 1602 if (xs == NULL || xs->xs_idx == 0) 1603 return; 1604 1605 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1606 1607 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1608 KASSERT(mutex_owned(&sc->sc_lock)); 1609 1610 if (pipe->up_dev->ud_depth == 0) 1611 return; 1612 1613 if (dci == XHCI_DCI_EP_CONTROL) { 1614 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1615 xhci_disable_slot(sc, xs->xs_idx); 1616 return; 1617 } 1618 1619 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED) 1620 (void)xhci_stop_endpoint(pipe); 1621 1622 /* 1623 * set appropriate bit to be dropped. 1624 * don't set DC bit to 1, otherwise all endpoints 1625 * would be deconfigured. 1626 */ 1627 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1628 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1629 cp[1] = htole32(0); 1630 1631 /* XXX should be most significant one, not dci? */ 1632 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1633 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1634 1635 /* configure ep context performs an implicit dequeue */ 1636 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 1637 1638 /* sync input contexts before they are read from memory */ 1639 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1640 1641 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1642 trb.trb_2 = 0; 1643 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1644 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1645 1646 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1647 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1648 } 1649 1650 /* 1651 * Abort transfer. 1652 * Should be called with sc_lock held. 1653 */ 1654 static void 1655 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1656 { 1657 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1658 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1659 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1660 1661 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1662 DPRINTFN(4, "xfer %p pipe %p status %d", 1663 xfer, xfer->ux_pipe, status, 0); 1664 1665 KASSERT(mutex_owned(&sc->sc_lock)); 1666 ASSERT_SLEEPABLE(); 1667 1668 if (sc->sc_dying) { 1669 /* If we're dying, just do the software part. */ 1670 DPRINTFN(4, "xfer %p dying %u", xfer, xfer->ux_status, 0, 0); 1671 xfer->ux_status = status; 1672 callout_halt(&xfer->ux_callout, &sc->sc_lock); 1673 usb_transfer_complete(xfer); 1674 return; 1675 } 1676 1677 /* 1678 * If an abort is already in progress then just wait for it to 1679 * complete and return. 1680 */ 1681 if (xfer->ux_hcflags & UXFER_ABORTING) { 1682 DPRINTFN(4, "already aborting", 0, 0, 0, 0); 1683 #ifdef DIAGNOSTIC 1684 if (status == USBD_TIMEOUT) 1685 DPRINTFN(4, "TIMEOUT while aborting", 0, 0, 0, 0); 1686 #endif 1687 /* Override the status which might be USBD_TIMEOUT. */ 1688 xfer->ux_status = status; 1689 DPRINTFN(4, "xfer %p waiting for abort to finish", xfer, 0, 0, 1690 0); 1691 xfer->ux_hcflags |= UXFER_ABORTWAIT; 1692 while (xfer->ux_hcflags & UXFER_ABORTING) 1693 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 1694 return; 1695 } 1696 xfer->ux_hcflags |= UXFER_ABORTING; 1697 1698 /* 1699 * Step 1: When cancelling a transfer make sure the timeout handler 1700 * didn't run or ran to the end and saw the USBD_CANCELLED status. 1701 * Otherwise we must have got here via a timeout. 1702 */ 1703 if (status == USBD_CANCELLED) { 1704 xfer->ux_status = status; 1705 callout_halt(&xfer->ux_callout, &sc->sc_lock); 1706 } else { 1707 KASSERT(xfer->ux_status == USBD_TIMEOUT); 1708 } 1709 1710 /* 1711 * Step 2: Stop execution of TD on the ring. 1712 */ 1713 switch (xhci_get_epstate(sc, xs, dci)) { 1714 case XHCI_EPSTATE_HALTED: 1715 (void)xhci_reset_endpoint_locked(xfer->ux_pipe); 1716 break; 1717 case XHCI_EPSTATE_STOPPED: 1718 break; 1719 default: 1720 (void)xhci_stop_endpoint(xfer->ux_pipe); 1721 break; 1722 } 1723 #ifdef DIAGNOSTIC 1724 uint32_t epst = xhci_get_epstate(sc, xs, dci); 1725 if (epst != XHCI_EPSTATE_STOPPED) 1726 DPRINTFN(4, "dci %u not stopped %u", dci, epst, 0, 0); 1727 #endif 1728 1729 /* 1730 * Step 3: Remove any vestiges of the xfer from the ring. 1731 */ 1732 xhci_set_dequeue_locked(xfer->ux_pipe); 1733 1734 /* 1735 * Step 4: Notify completion to waiting xfers. 1736 */ 1737 int wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 1738 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 1739 usb_transfer_complete(xfer); 1740 if (wake) { 1741 cv_broadcast(&xfer->ux_hccv); 1742 } 1743 DPRINTFN(14, "end", 0, 0, 0, 0); 1744 1745 KASSERT(mutex_owned(&sc->sc_lock)); 1746 } 1747 1748 static void 1749 xhci_host_dequeue(struct xhci_ring * const xr) 1750 { 1751 /* When dequeueing the controller, update our struct copy too */ 1752 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1753 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1754 BUS_DMASYNC_PREWRITE); 1755 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1756 1757 xr->xr_ep = 0; 1758 xr->xr_cs = 1; 1759 } 1760 1761 /* 1762 * Recover STALLed endpoint. 1763 * xHCI 1.1 sect 4.10.2.1 1764 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1765 * all transfers on transfer ring. 1766 * These are done in thread context asynchronously. 1767 */ 1768 static void 1769 xhci_clear_endpoint_stall_async_task(void *cookie) 1770 { 1771 struct usbd_xfer * const xfer = cookie; 1772 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1773 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1774 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1775 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1776 1777 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1778 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1779 1780 xhci_reset_endpoint(xfer->ux_pipe); 1781 xhci_set_dequeue(xfer->ux_pipe); 1782 1783 mutex_enter(&sc->sc_lock); 1784 tr->is_halted = false; 1785 usb_transfer_complete(xfer); 1786 mutex_exit(&sc->sc_lock); 1787 DPRINTFN(4, "ends", 0, 0, 0, 0); 1788 } 1789 1790 static usbd_status 1791 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1792 { 1793 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1794 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1795 1796 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1797 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1798 1799 if (sc->sc_dying) { 1800 return USBD_IOERROR; 1801 } 1802 1803 usb_init_task(&xp->xp_async_task, 1804 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1805 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1806 DPRINTFN(4, "ends", 0, 0, 0, 0); 1807 1808 return USBD_NORMAL_COMPLETION; 1809 } 1810 1811 /* Process roothub port status/change events and notify to uhub_intr. */ 1812 static void 1813 xhci_rhpsc(struct xhci_softc * const sc, u_int ctlrport) 1814 { 1815 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1816 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1817 ctlrport, 0, 0); 1818 1819 if (ctlrport > sc->sc_maxports) 1820 return; 1821 1822 const size_t bn = xhci_ctlrport2bus(sc, ctlrport); 1823 const size_t rhp = xhci_ctlrport2rhport(sc, ctlrport); 1824 struct usbd_xfer * const xfer = sc->sc_intrxfer[bn]; 1825 1826 DPRINTFN(4, "xhci%d: bus %d bp %u xfer %p status change", 1827 device_unit(sc->sc_dev), bn, rhp, xfer); 1828 1829 if (xfer == NULL) 1830 return; 1831 1832 uint8_t *p = xfer->ux_buf; 1833 memset(p, 0, xfer->ux_length); 1834 p[rhp / NBBY] |= 1 << (rhp % NBBY); 1835 xfer->ux_actlen = xfer->ux_length; 1836 xfer->ux_status = USBD_NORMAL_COMPLETION; 1837 usb_transfer_complete(xfer); 1838 } 1839 1840 /* Process Transfer Events */ 1841 static void 1842 xhci_event_transfer(struct xhci_softc * const sc, 1843 const struct xhci_trb * const trb) 1844 { 1845 uint64_t trb_0; 1846 uint32_t trb_2, trb_3; 1847 uint8_t trbcode; 1848 u_int slot, dci; 1849 struct xhci_slot *xs; 1850 struct xhci_ring *xr; 1851 struct xhci_xfer *xx; 1852 struct usbd_xfer *xfer; 1853 usbd_status err; 1854 1855 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1856 1857 trb_0 = le64toh(trb->trb_0); 1858 trb_2 = le32toh(trb->trb_2); 1859 trb_3 = le32toh(trb->trb_3); 1860 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1861 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1862 dci = XHCI_TRB_3_EP_GET(trb_3); 1863 xs = &sc->sc_slots[slot]; 1864 xr = &xs->xs_ep[dci].xe_tr; 1865 1866 /* sanity check */ 1867 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1868 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1869 1870 int idx = 0; 1871 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1872 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1873 DPRINTFN(0, "invalid trb_0 0x%"PRIx64, trb_0, 0, 0, 0); 1874 return; 1875 } 1876 xx = xr->xr_cookies[idx]; 1877 1878 /* clear cookie of consumed TRB */ 1879 xr->xr_cookies[idx] = NULL; 1880 1881 /* 1882 * xx is NULL if pipe is opened but xfer is not started. 1883 * It happens when stopping idle pipe. 1884 */ 1885 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1886 DPRINTFN(1, "Ignore #%u: cookie %p cc %u dci %u", 1887 idx, xx, trbcode, dci); 1888 DPRINTFN(1, " orig TRB %"PRIx64" type %u", trb_0, 1889 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1890 0, 0); 1891 return; 1892 } 1893 } else { 1894 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1895 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1896 } 1897 /* XXX this may not happen */ 1898 if (xx == NULL) { 1899 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1900 return; 1901 } 1902 xfer = &xx->xx_xfer; 1903 /* XXX this may happen when detaching */ 1904 if (xfer == NULL) { 1905 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1906 xx, trb_0, 0, 0); 1907 return; 1908 } 1909 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1910 /* XXX I dunno why this happens */ 1911 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1912 1913 if (!xfer->ux_pipe->up_repeat && 1914 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1915 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1916 return; 1917 } 1918 1919 /* 4.11.5.2 Event Data TRB */ 1920 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1921 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1922 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1923 if ((trb_0 & 0x3) == 0x3) { 1924 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1925 } 1926 } 1927 1928 switch (trbcode) { 1929 case XHCI_TRB_ERROR_SHORT_PKT: 1930 case XHCI_TRB_ERROR_SUCCESS: 1931 /* 1932 * A ctrl transfer can generate two events if it has a Data 1933 * stage. A short data stage can be OK and should not 1934 * complete the transfer as the status stage needs to be 1935 * performed. 1936 * 1937 * Note: Data and Status stage events point at same xfer. 1938 * ux_actlen and ux_dmabuf will be passed to 1939 * usb_transfer_complete after the Status stage event. 1940 * 1941 * It can be distingished which stage generates the event: 1942 * + by checking least 3 bits of trb_0 if ED==1. 1943 * (see xhci_device_ctrl_start). 1944 * + by checking the type of original TRB if ED==0. 1945 * 1946 * In addition, intr, bulk, and isoc transfer currently 1947 * consists of single TD, so the "skip" is not needed. 1948 * ctrl xfer uses EVENT_DATA, and others do not. 1949 * Thus driver can switch the flow by checking ED bit. 1950 */ 1951 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1952 if (xfer->ux_actlen == 0) 1953 xfer->ux_actlen = xfer->ux_length - 1954 XHCI_TRB_2_REM_GET(trb_2); 1955 if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)) 1956 == XHCI_TRB_TYPE_DATA_STAGE) { 1957 return; 1958 } 1959 } else if ((trb_0 & 0x3) == 0x3) { 1960 return; 1961 } 1962 err = USBD_NORMAL_COMPLETION; 1963 break; 1964 case XHCI_TRB_ERROR_STOPPED: 1965 case XHCI_TRB_ERROR_LENGTH: 1966 case XHCI_TRB_ERROR_STOPPED_SHORT: 1967 /* 1968 * don't complete the transfer being aborted 1969 * as abort_xfer does instead. 1970 */ 1971 if (xfer->ux_hcflags & UXFER_ABORTING) { 1972 DPRINTFN(14, "ignore aborting xfer %p", xfer, 0, 0, 0); 1973 return; 1974 } 1975 err = USBD_CANCELLED; 1976 break; 1977 case XHCI_TRB_ERROR_STALL: 1978 case XHCI_TRB_ERROR_BABBLE: 1979 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1980 xr->is_halted = true; 1981 err = USBD_STALLED; 1982 /* 1983 * Stalled endpoints can be recoverd by issuing 1984 * command TRB TYPE_RESET_EP on xHCI instead of 1985 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1986 * on the endpoint. However, this function may be 1987 * called from softint context (e.g. from umass), 1988 * in that case driver gets KASSERT in cv_timedwait 1989 * in xhci_do_command. 1990 * To avoid this, this runs reset_endpoint and 1991 * usb_transfer_complete in usb task thread 1992 * asynchronously (and then umass issues clear 1993 * UF_ENDPOINT_HALT). 1994 */ 1995 xfer->ux_status = err; 1996 callout_halt(&xfer->ux_callout, &sc->sc_lock); 1997 xhci_clear_endpoint_stall_async(xfer); 1998 return; 1999 default: 2000 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 2001 err = USBD_IOERROR; 2002 break; 2003 } 2004 xfer->ux_status = err; 2005 2006 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 2007 if ((trb_0 & 0x3) == 0x0) { 2008 callout_stop(&xfer->ux_callout); 2009 usb_transfer_complete(xfer); 2010 } 2011 } else { 2012 callout_stop(&xfer->ux_callout); 2013 usb_transfer_complete(xfer); 2014 } 2015 } 2016 2017 /* Process Command complete events */ 2018 static void 2019 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 2020 { 2021 uint64_t trb_0; 2022 uint32_t trb_2, trb_3; 2023 2024 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2025 2026 KASSERT(mutex_owned(&sc->sc_lock)); 2027 2028 trb_0 = le64toh(trb->trb_0); 2029 trb_2 = le32toh(trb->trb_2); 2030 trb_3 = le32toh(trb->trb_3); 2031 2032 if (trb_0 == sc->sc_command_addr) { 2033 sc->sc_resultpending = false; 2034 2035 sc->sc_result_trb.trb_0 = trb_0; 2036 sc->sc_result_trb.trb_2 = trb_2; 2037 sc->sc_result_trb.trb_3 = trb_3; 2038 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2039 XHCI_TRB_ERROR_SUCCESS) { 2040 DPRINTFN(1, "command completion " 2041 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 2042 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 2043 } 2044 cv_signal(&sc->sc_command_cv); 2045 } else { 2046 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 2047 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 2048 trb_2, trb_3); 2049 } 2050 } 2051 2052 /* 2053 * Process events. 2054 * called from xhci_softintr 2055 */ 2056 static void 2057 xhci_handle_event(struct xhci_softc * const sc, 2058 const struct xhci_trb * const trb) 2059 { 2060 uint64_t trb_0; 2061 uint32_t trb_2, trb_3; 2062 2063 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2064 2065 trb_0 = le64toh(trb->trb_0); 2066 trb_2 = le32toh(trb->trb_2); 2067 trb_3 = le32toh(trb->trb_3); 2068 2069 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2070 trb, trb_0, trb_2, trb_3); 2071 2072 /* 2073 * 4.11.3.1, 6.4.2.1 2074 * TRB Pointer is invalid for these completion codes. 2075 */ 2076 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2077 case XHCI_TRB_ERROR_RING_UNDERRUN: 2078 case XHCI_TRB_ERROR_RING_OVERRUN: 2079 case XHCI_TRB_ERROR_VF_RING_FULL: 2080 return; 2081 default: 2082 if (trb_0 == 0) { 2083 return; 2084 } 2085 break; 2086 } 2087 2088 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2089 case XHCI_TRB_EVENT_TRANSFER: 2090 xhci_event_transfer(sc, trb); 2091 break; 2092 case XHCI_TRB_EVENT_CMD_COMPLETE: 2093 xhci_event_cmd(sc, trb); 2094 break; 2095 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2096 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2097 break; 2098 default: 2099 break; 2100 } 2101 } 2102 2103 static void 2104 xhci_softintr(void *v) 2105 { 2106 struct usbd_bus * const bus = v; 2107 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2108 struct xhci_ring * const er = &sc->sc_er; 2109 struct xhci_trb *trb; 2110 int i, j, k; 2111 2112 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2113 2114 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2115 2116 i = er->xr_ep; 2117 j = er->xr_cs; 2118 2119 DPRINTFN(16, "er: xr_ep %d xr_cs %d", i, j, 0, 0); 2120 2121 while (1) { 2122 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2123 BUS_DMASYNC_POSTREAD); 2124 trb = &er->xr_trb[i]; 2125 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2126 2127 if (j != k) 2128 break; 2129 2130 xhci_handle_event(sc, trb); 2131 2132 i++; 2133 if (i == er->xr_ntrb) { 2134 i = 0; 2135 j ^= 1; 2136 } 2137 } 2138 2139 er->xr_ep = i; 2140 er->xr_cs = j; 2141 2142 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2143 XHCI_ERDP_LO_BUSY); 2144 2145 DPRINTFN(16, "ends", 0, 0, 0, 0); 2146 2147 return; 2148 } 2149 2150 static void 2151 xhci_poll(struct usbd_bus *bus) 2152 { 2153 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2154 2155 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2156 2157 mutex_spin_enter(&sc->sc_intr_lock); 2158 xhci_intr1(sc); 2159 mutex_spin_exit(&sc->sc_intr_lock); 2160 2161 return; 2162 } 2163 2164 static struct usbd_xfer * 2165 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2166 { 2167 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2168 struct usbd_xfer *xfer; 2169 2170 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2171 2172 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 2173 if (xfer != NULL) { 2174 memset(xfer, 0, sizeof(struct xhci_xfer)); 2175 #ifdef DIAGNOSTIC 2176 xfer->ux_state = XFER_BUSY; 2177 #endif 2178 } 2179 2180 return xfer; 2181 } 2182 2183 static void 2184 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2185 { 2186 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2187 2188 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2189 2190 #ifdef DIAGNOSTIC 2191 if (xfer->ux_state != XFER_BUSY) { 2192 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 2193 xfer, xfer->ux_state, 0, 0); 2194 } 2195 xfer->ux_state = XFER_FREE; 2196 #endif 2197 pool_cache_put(sc->sc_xferpool, xfer); 2198 } 2199 2200 static void 2201 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2202 { 2203 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2204 2205 *lock = &sc->sc_lock; 2206 } 2207 2208 extern uint32_t usb_cookie_no; 2209 2210 /* 2211 * xHCI 4.3 2212 * Called when uhub_explore finds a new device (via usbd_new_device). 2213 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2214 * This function does: 2215 * Allocate and construct dev structure of default endpoint (ep0). 2216 * Allocate and open pipe of ep0. 2217 * Enable slot and initialize slot context. 2218 * Set Address. 2219 * Read initial device descriptor. 2220 * Determine initial MaxPacketSize (mps) by speed. 2221 * Read full device descriptor. 2222 * Register this device. 2223 * Finally state of device transitions ADDRESSED. 2224 */ 2225 static usbd_status 2226 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2227 int speed, int port, struct usbd_port *up) 2228 { 2229 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2230 struct usbd_device *dev; 2231 usbd_status err; 2232 usb_device_descriptor_t *dd; 2233 struct xhci_slot *xs; 2234 uint32_t *cp; 2235 2236 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2237 DPRINTFN(4, "port %u depth %u speed %u up %p", port, depth, speed, up); 2238 2239 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2240 if (dev == NULL) 2241 return USBD_NOMEM; 2242 2243 dev->ud_bus = bus; 2244 dev->ud_quirks = &usbd_no_quirk; 2245 dev->ud_addr = 0; 2246 dev->ud_ddesc.bMaxPacketSize = 0; 2247 dev->ud_depth = depth; 2248 dev->ud_powersrc = up; 2249 dev->ud_myhub = up->up_parent; 2250 dev->ud_speed = speed; 2251 dev->ud_langid = USBD_NOLANG; 2252 dev->ud_cookie.cookie = ++usb_cookie_no; 2253 2254 /* Set up default endpoint handle. */ 2255 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2256 /* doesn't matter, just don't let it uninitialized */ 2257 dev->ud_ep0.ue_toggle = 0; 2258 2259 /* Set up default endpoint descriptor. */ 2260 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2261 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2262 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2263 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2264 dev->ud_ep0desc.bInterval = 0; 2265 2266 /* 4.3, 4.8.2.1 */ 2267 switch (speed) { 2268 case USB_SPEED_SUPER: 2269 case USB_SPEED_SUPER_PLUS: 2270 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2271 break; 2272 case USB_SPEED_FULL: 2273 /* XXX using 64 as initial mps of ep0 in FS */ 2274 case USB_SPEED_HIGH: 2275 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2276 break; 2277 case USB_SPEED_LOW: 2278 default: 2279 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2280 break; 2281 } 2282 2283 up->up_dev = dev; 2284 2285 /* Establish the default pipe. */ 2286 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2287 &dev->ud_pipe0); 2288 if (err) { 2289 goto bad; 2290 } 2291 2292 dd = &dev->ud_ddesc; 2293 2294 if (depth == 0 && port == 0) { 2295 #define XHCI_ROOTHUB_INDEX 128 2296 KASSERT(bus->ub_devices[XHCI_ROOTHUB_INDEX] == NULL); 2297 bus->ub_devices[XHCI_ROOTHUB_INDEX] = dev; 2298 err = usbd_get_initial_ddesc(dev, dd); 2299 if (err) { 2300 DPRINTFN(1, "get_initial_ddesc %u", err, 0, 0, 0); 2301 goto bad; 2302 } 2303 2304 err = usbd_reload_device_desc(dev); 2305 if (err) { 2306 DPRINTFN(1, "reload desc %u", err, 0, 0, 0); 2307 goto bad; 2308 } 2309 } else { 2310 uint8_t slot = 0; 2311 2312 /* 4.3.2 */ 2313 err = xhci_enable_slot(sc, &slot); 2314 if (err) { 2315 DPRINTFN(1, "enable slot %u", err, 0, 0, 0); 2316 goto bad; 2317 } 2318 2319 xs = &sc->sc_slots[slot]; 2320 dev->ud_hcpriv = xs; 2321 2322 /* 4.3.3 initialize slot structure */ 2323 err = xhci_init_slot(dev, slot); 2324 if (err) { 2325 DPRINTFN(1, "init slot %u", err, 0, 0, 0); 2326 dev->ud_hcpriv = NULL; 2327 /* 2328 * We have to disable_slot here because 2329 * xs->xs_idx == 0 when xhci_init_slot fails, 2330 * in that case usbd_remove_dev won't work. 2331 */ 2332 mutex_enter(&sc->sc_lock); 2333 xhci_disable_slot(sc, slot); 2334 mutex_exit(&sc->sc_lock); 2335 goto bad; 2336 } 2337 2338 /* 4.3.4 Address Assignment */ 2339 err = xhci_set_address(dev, slot, false); 2340 if (err) { 2341 DPRINTFN(1, "set address w/o bsr %u", err, 0, 0, 0); 2342 goto bad; 2343 } 2344 2345 /* Allow device time to set new address */ 2346 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2347 2348 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2349 //hexdump("slot context", cp, sc->sc_ctxsz); 2350 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3])); 2351 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2352 /* 2353 * XXX ensure we know when the hardware does something 2354 * we can't yet cope with 2355 */ 2356 KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr); 2357 dev->ud_addr = addr; 2358 2359 KASSERTMSG(bus->ub_devices[dev->ud_addr] == NULL, 2360 "addr %d already allocated", dev->ud_addr); 2361 /* 2362 * The root hub is given a slot 2363 */ 2364 bus->ub_devices[dev->ud_addr] = dev; 2365 2366 err = usbd_get_initial_ddesc(dev, dd); 2367 if (err) { 2368 DPRINTFN(1, "get_initial_ddesc %u", err, 0, 0, 0); 2369 goto bad; 2370 } 2371 2372 /* 4.8.2.1 */ 2373 if (USB_IS_SS(speed)) { 2374 if (dd->bMaxPacketSize != 9) { 2375 printf("%s: invalid mps 2^%u for SS ep0," 2376 " using 512\n", 2377 device_xname(sc->sc_dev), 2378 dd->bMaxPacketSize); 2379 dd->bMaxPacketSize = 9; 2380 } 2381 USETW(dev->ud_ep0desc.wMaxPacketSize, 2382 (1 << dd->bMaxPacketSize)); 2383 } else 2384 USETW(dev->ud_ep0desc.wMaxPacketSize, 2385 dd->bMaxPacketSize); 2386 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2387 err = xhci_update_ep0_mps(sc, xs, 2388 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2389 if (err) { 2390 DPRINTFN(1, "update mps of ep0 %u", err, 0, 0, 0); 2391 goto bad; 2392 } 2393 2394 err = usbd_reload_device_desc(dev); 2395 if (err) { 2396 DPRINTFN(1, "reload desc %u", err, 0, 0, 0); 2397 goto bad; 2398 } 2399 } 2400 2401 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2402 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2403 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2404 dd->bDeviceClass, dd->bDeviceSubClass, 2405 dd->bDeviceProtocol, 0); 2406 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2407 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2408 dev->ud_speed); 2409 2410 usbd_get_device_strings(dev); 2411 2412 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2413 2414 if (depth == 0 && port == 0) { 2415 usbd_attach_roothub(parent, dev); 2416 DPRINTFN(1, "root hub %p", dev, 0, 0, 0); 2417 return USBD_NORMAL_COMPLETION; 2418 } 2419 2420 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2421 bad: 2422 if (err != USBD_NORMAL_COMPLETION) { 2423 usbd_remove_device(dev, up); 2424 } 2425 2426 return err; 2427 } 2428 2429 static usbd_status 2430 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2431 size_t ntrb, size_t align) 2432 { 2433 usbd_status err; 2434 size_t size = ntrb * XHCI_TRB_SIZE; 2435 2436 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2437 2438 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2439 if (err) 2440 return err; 2441 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2442 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2443 xr->xr_trb = xhci_ring_trbv(xr, 0); 2444 xr->xr_ntrb = ntrb; 2445 xr->is_halted = false; 2446 xhci_host_dequeue(xr); 2447 2448 return USBD_NORMAL_COMPLETION; 2449 } 2450 2451 static void 2452 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2453 { 2454 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2455 mutex_destroy(&xr->xr_lock); 2456 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2457 } 2458 2459 static void 2460 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2461 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2462 { 2463 size_t i; 2464 u_int ri; 2465 u_int cs; 2466 uint64_t parameter; 2467 uint32_t status; 2468 uint32_t control; 2469 2470 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2471 2472 KASSERTMSG(ntrbs <= XHCI_XFER_NTRB, "ntrbs %zu", ntrbs); 2473 for (i = 0; i < ntrbs; i++) { 2474 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2475 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2476 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2477 KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2478 XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3); 2479 } 2480 2481 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2482 2483 ri = xr->xr_ep; 2484 cs = xr->xr_cs; 2485 2486 /* 2487 * Although the xhci hardware can do scatter/gather dma from 2488 * arbitrary sized buffers, there is a non-obvious restriction 2489 * that a LINK trb is only allowed at the end of a burst of 2490 * transfers - which might be 16kB. 2491 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2492 * The simple solution is not to allow a LINK trb in the middle 2493 * of anything - as here. 2494 * XXX: (dsl) There are xhci controllers out there (eg some made by 2495 * ASMedia) that seem to lock up if they process a LINK trb but 2496 * cannot process the linked-to trb yet. 2497 * The code should write the 'cycle' bit on the link trb AFTER 2498 * adding the other trb. 2499 */ 2500 u_int firstep = xr->xr_ep; 2501 u_int firstcs = xr->xr_cs; 2502 2503 for (i = 0; i < ntrbs; ) { 2504 u_int oldri = ri; 2505 u_int oldcs = cs; 2506 2507 if (ri >= (xr->xr_ntrb - 1)) { 2508 /* Put Link TD at the end of ring */ 2509 parameter = xhci_ring_trbp(xr, 0); 2510 status = 0; 2511 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2512 XHCI_TRB_3_TC_BIT; 2513 xr->xr_cookies[ri] = NULL; 2514 xr->xr_ep = 0; 2515 xr->xr_cs ^= 1; 2516 ri = xr->xr_ep; 2517 cs = xr->xr_cs; 2518 } else { 2519 parameter = trbs[i].trb_0; 2520 status = trbs[i].trb_2; 2521 control = trbs[i].trb_3; 2522 2523 xr->xr_cookies[ri] = cookie; 2524 ri++; 2525 i++; 2526 } 2527 /* 2528 * If this is a first TRB, mark it invalid to prevent 2529 * xHC from running it immediately. 2530 */ 2531 if (oldri == firstep) { 2532 if (oldcs) { 2533 control &= ~XHCI_TRB_3_CYCLE_BIT; 2534 } else { 2535 control |= XHCI_TRB_3_CYCLE_BIT; 2536 } 2537 } else { 2538 if (oldcs) { 2539 control |= XHCI_TRB_3_CYCLE_BIT; 2540 } else { 2541 control &= ~XHCI_TRB_3_CYCLE_BIT; 2542 } 2543 } 2544 xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control); 2545 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri, 2546 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2547 } 2548 2549 /* Now invert cycle bit of first TRB */ 2550 if (firstcs) { 2551 xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 2552 } else { 2553 xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 2554 } 2555 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep, 2556 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2557 2558 xr->xr_ep = ri; 2559 xr->xr_cs = cs; 2560 2561 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2562 } 2563 2564 /* 2565 * Stop execution commands, purge all commands on command ring, and 2566 * rewind dequeue pointer. 2567 */ 2568 static void 2569 xhci_abort_command(struct xhci_softc *sc) 2570 { 2571 struct xhci_ring * const cr = &sc->sc_cr; 2572 uint64_t crcr; 2573 int i; 2574 2575 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2576 DPRINTFN(14, "command %#"PRIx64" timeout, aborting", 2577 sc->sc_command_addr, 0, 0, 0); 2578 2579 mutex_enter(&cr->xr_lock); 2580 2581 /* 4.6.1.2 Aborting a Command */ 2582 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2583 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2584 2585 for (i = 0; i < 500; i++) { 2586 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2587 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2588 break; 2589 usb_delay_ms(&sc->sc_bus, 1); 2590 } 2591 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2592 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2593 /* reset HC here? */ 2594 } 2595 2596 /* reset command ring dequeue pointer */ 2597 cr->xr_ep = 0; 2598 cr->xr_cs = 1; 2599 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2600 2601 mutex_exit(&cr->xr_lock); 2602 } 2603 2604 /* 2605 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2606 * Command completion is notified by cv_signal from xhci_event_cmd() 2607 * (called from xhci_softint), or timed-out. 2608 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2609 * then do_command examines it. 2610 */ 2611 static usbd_status 2612 xhci_do_command_locked(struct xhci_softc * const sc, 2613 struct xhci_trb * const trb, int timeout) 2614 { 2615 struct xhci_ring * const cr = &sc->sc_cr; 2616 usbd_status err; 2617 2618 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2619 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2620 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2621 2622 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2623 KASSERT(mutex_owned(&sc->sc_lock)); 2624 2625 while (sc->sc_command_addr != 0) 2626 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 2627 2628 /* 2629 * If enqueue pointer points at last of ring, it's Link TRB, 2630 * command TRB will be stored in 0th TRB. 2631 */ 2632 if (cr->xr_ep == cr->xr_ntrb - 1) 2633 sc->sc_command_addr = xhci_ring_trbp(cr, 0); 2634 else 2635 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2636 2637 sc->sc_resultpending = true; 2638 2639 mutex_enter(&cr->xr_lock); 2640 xhci_ring_put(sc, cr, NULL, trb, 1); 2641 mutex_exit(&cr->xr_lock); 2642 2643 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2644 2645 while (sc->sc_resultpending) { 2646 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2647 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2648 xhci_abort_command(sc); 2649 err = USBD_TIMEOUT; 2650 goto timedout; 2651 } 2652 } 2653 2654 trb->trb_0 = sc->sc_result_trb.trb_0; 2655 trb->trb_2 = sc->sc_result_trb.trb_2; 2656 trb->trb_3 = sc->sc_result_trb.trb_3; 2657 2658 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2659 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2660 2661 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2662 case XHCI_TRB_ERROR_SUCCESS: 2663 err = USBD_NORMAL_COMPLETION; 2664 break; 2665 default: 2666 case 192 ... 223: 2667 err = USBD_IOERROR; 2668 break; 2669 case 224 ... 255: 2670 err = USBD_NORMAL_COMPLETION; 2671 break; 2672 } 2673 2674 timedout: 2675 sc->sc_resultpending = false; 2676 sc->sc_command_addr = 0; 2677 cv_broadcast(&sc->sc_cmdbusy_cv); 2678 2679 return err; 2680 } 2681 2682 static usbd_status 2683 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2684 int timeout) 2685 { 2686 2687 mutex_enter(&sc->sc_lock); 2688 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2689 mutex_exit(&sc->sc_lock); 2690 2691 return ret; 2692 } 2693 2694 static usbd_status 2695 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2696 { 2697 struct xhci_trb trb; 2698 usbd_status err; 2699 2700 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2701 2702 trb.trb_0 = 0; 2703 trb.trb_2 = 0; 2704 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2705 2706 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2707 if (err != USBD_NORMAL_COMPLETION) { 2708 return err; 2709 } 2710 2711 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2712 2713 return err; 2714 } 2715 2716 /* 2717 * xHCI 4.6.4 2718 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2719 * All endpoints in the slot should be stopped. 2720 * Should be called with sc_lock held. 2721 */ 2722 static usbd_status 2723 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2724 { 2725 struct xhci_trb trb; 2726 struct xhci_slot *xs; 2727 usbd_status err; 2728 2729 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2730 2731 if (sc->sc_dying) 2732 return USBD_IOERROR; 2733 2734 trb.trb_0 = 0; 2735 trb.trb_2 = 0; 2736 trb.trb_3 = htole32( 2737 XHCI_TRB_3_SLOT_SET(slot) | 2738 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2739 2740 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2741 2742 if (!err) { 2743 xs = &sc->sc_slots[slot]; 2744 if (xs->xs_idx != 0) { 2745 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2746 xhci_set_dcba(sc, 0, slot); 2747 memset(xs, 0, sizeof(*xs)); 2748 } 2749 } 2750 2751 return err; 2752 } 2753 2754 /* 2755 * Set address of device and transition slot state from ENABLED to ADDRESSED 2756 * if Block Setaddress Request (BSR) is false. 2757 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2758 * see xHCI 1.1 4.5.3, 3.3.4 2759 * Should be called without sc_lock held. 2760 */ 2761 static usbd_status 2762 xhci_address_device(struct xhci_softc * const sc, 2763 uint64_t icp, uint8_t slot_id, bool bsr) 2764 { 2765 struct xhci_trb trb; 2766 usbd_status err; 2767 2768 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2769 2770 trb.trb_0 = icp; 2771 trb.trb_2 = 0; 2772 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2773 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2774 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2775 2776 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2777 2778 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2779 err = USBD_NO_ADDR; 2780 2781 return err; 2782 } 2783 2784 static usbd_status 2785 xhci_update_ep0_mps(struct xhci_softc * const sc, 2786 struct xhci_slot * const xs, u_int mps) 2787 { 2788 struct xhci_trb trb; 2789 usbd_status err; 2790 uint32_t * cp; 2791 2792 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2793 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2794 2795 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2796 cp[0] = htole32(0); 2797 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2798 2799 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2800 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2801 2802 /* sync input contexts before they are read from memory */ 2803 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2804 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2805 sc->sc_ctxsz * 4); 2806 2807 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2808 trb.trb_2 = 0; 2809 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2810 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2811 2812 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2813 return err; 2814 } 2815 2816 static void 2817 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2818 { 2819 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2820 2821 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2822 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2823 &dcbaa[si], dcba, si, 0); 2824 2825 dcbaa[si] = htole64(dcba); 2826 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2827 BUS_DMASYNC_PREWRITE); 2828 } 2829 2830 /* 2831 * Allocate device and input context DMA buffer, and 2832 * TRB DMA buffer for each endpoint. 2833 */ 2834 static usbd_status 2835 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2836 { 2837 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2838 struct xhci_slot *xs; 2839 usbd_status err; 2840 u_int dci; 2841 2842 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2843 DPRINTFN(4, "slot %u", slot, 0, 0, 0); 2844 2845 xs = &sc->sc_slots[slot]; 2846 2847 /* allocate contexts */ 2848 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2849 &xs->xs_dc_dma); 2850 if (err) 2851 return err; 2852 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2853 2854 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2855 &xs->xs_ic_dma); 2856 if (err) 2857 goto bad1; 2858 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2859 2860 for (dci = 0; dci < 32; dci++) { 2861 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2862 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2863 if (dci == XHCI_DCI_SLOT) 2864 continue; 2865 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2866 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2867 if (err) { 2868 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2869 goto bad2; 2870 } 2871 } 2872 2873 bad2: 2874 if (err == USBD_NORMAL_COMPLETION) { 2875 xs->xs_idx = slot; 2876 } else { 2877 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2878 } 2879 2880 return err; 2881 2882 bad1: 2883 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2884 xs->xs_idx = 0; 2885 return err; 2886 } 2887 2888 static void 2889 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2890 int end_dci) 2891 { 2892 u_int dci; 2893 2894 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2895 DPRINTFN(4, "slot %u start %u end %u", xs->xs_idx, start_dci, end_dci, 2896 0); 2897 2898 for (dci = start_dci; dci < end_dci; dci++) { 2899 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2900 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2901 } 2902 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2903 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2904 xs->xs_idx = 0; 2905 } 2906 2907 /* 2908 * Setup slot context, set Device Context Base Address, and issue 2909 * Set Address Device command. 2910 */ 2911 static usbd_status 2912 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 2913 { 2914 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2915 struct xhci_slot *xs; 2916 usbd_status err; 2917 2918 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2919 DPRINTFN(4, "slot %u bsr %u", slot, bsr, 0, 0); 2920 2921 xs = &sc->sc_slots[slot]; 2922 2923 xhci_setup_ctx(dev->ud_pipe0); 2924 2925 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2926 sc->sc_ctxsz * 3); 2927 2928 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2929 2930 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 2931 2932 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2933 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2934 sc->sc_ctxsz * 2); 2935 2936 return err; 2937 } 2938 2939 /* 2940 * 4.8.2, 6.2.3.2 2941 * construct slot/endpoint context parameters and do syncmem 2942 */ 2943 static void 2944 xhci_setup_ctx(struct usbd_pipe *pipe) 2945 { 2946 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2947 struct usbd_device *dev = pipe->up_dev; 2948 struct xhci_slot * const xs = dev->ud_hcpriv; 2949 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2950 const u_int dci = xhci_ep_get_dci(ed); 2951 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2952 uint32_t *cp; 2953 uint16_t mps = UGETW(ed->wMaxPacketSize); 2954 uint8_t speed = dev->ud_speed; 2955 uint8_t ival = ed->bInterval; 2956 2957 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2958 DPRINTFN(4, "pipe %p: slot %u dci %u speed %u", pipe, xs->xs_idx, dci, 2959 speed); 2960 2961 /* set up initial input control context */ 2962 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2963 cp[0] = htole32(0); 2964 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 2965 if (dci == XHCI_DCI_EP_CONTROL) 2966 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2967 cp[7] = htole32(0); 2968 2969 /* set up input slot context */ 2970 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2971 cp[0] = 2972 XHCI_SCTX_0_CTX_NUM_SET(dci) | 2973 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 2974 cp[1] = 0; 2975 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2976 cp[3] = 0; 2977 xhci_setup_route(pipe, cp); 2978 xhci_setup_tthub(pipe, cp); 2979 2980 cp[0] = htole32(cp[0]); 2981 cp[1] = htole32(cp[1]); 2982 cp[2] = htole32(cp[2]); 2983 cp[3] = htole32(cp[3]); 2984 2985 /* set up input endpoint context */ 2986 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 2987 cp[0] = 2988 XHCI_EPCTX_0_EPSTATE_SET(0) | 2989 XHCI_EPCTX_0_MULT_SET(0) | 2990 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2991 XHCI_EPCTX_0_LSA_SET(0) | 2992 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 2993 cp[1] = 2994 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 2995 XHCI_EPCTX_1_HID_SET(0) | 2996 XHCI_EPCTX_1_MAXB_SET(0); 2997 2998 if (xfertype != UE_ISOCHRONOUS) 2999 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 3000 3001 if (xfertype == UE_CONTROL) 3002 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 3003 else if (USB_IS_SS(speed)) 3004 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 3005 else 3006 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 3007 3008 xhci_setup_maxburst(pipe, cp); 3009 3010 switch (xfertype) { 3011 case UE_CONTROL: 3012 break; 3013 case UE_BULK: 3014 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 3015 break; 3016 case UE_INTERRUPT: 3017 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3018 ival = pipe->up_interval; 3019 3020 ival = xhci_bival2ival(ival, speed); 3021 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3022 break; 3023 case UE_ISOCHRONOUS: 3024 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3025 ival = pipe->up_interval; 3026 3027 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 3028 if (speed == USB_SPEED_FULL) 3029 ival += 3; /* 1ms -> 125us */ 3030 ival--; 3031 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3032 break; 3033 default: 3034 break; 3035 } 3036 DPRINTFN(4, "setting ival %u MaxBurst %#x", 3037 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 3038 3039 /* rewind TR dequeue pointer in xHC */ 3040 /* can't use xhci_ep_get_dci() yet? */ 3041 *(uint64_t *)(&cp[2]) = htole64( 3042 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 3043 XHCI_EPCTX_2_DCS_SET(1)); 3044 3045 cp[0] = htole32(cp[0]); 3046 cp[1] = htole32(cp[1]); 3047 cp[4] = htole32(cp[4]); 3048 3049 /* rewind TR dequeue pointer in driver */ 3050 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 3051 mutex_enter(&xr->xr_lock); 3052 xhci_host_dequeue(xr); 3053 mutex_exit(&xr->xr_lock); 3054 3055 /* sync input contexts before they are read from memory */ 3056 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3057 } 3058 3059 /* 3060 * Setup route string and roothub port of given device for slot context 3061 */ 3062 static void 3063 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 3064 { 3065 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3066 struct usbd_device *dev = pipe->up_dev; 3067 struct usbd_port *up = dev->ud_powersrc; 3068 struct usbd_device *hub; 3069 struct usbd_device *adev; 3070 uint8_t rhport = 0; 3071 uint32_t route = 0; 3072 3073 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3074 3075 /* Locate root hub port and Determine route string */ 3076 /* 4.3.3 route string does not include roothub port */ 3077 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 3078 uint32_t dep; 3079 3080 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 3081 hub, hub->ud_depth, hub->ud_powersrc, 3082 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 3083 3084 if (hub->ud_powersrc == NULL) 3085 break; 3086 dep = hub->ud_depth; 3087 if (dep == 0) 3088 break; 3089 rhport = hub->ud_powersrc->up_portno; 3090 if (dep > USB_HUB_MAX_DEPTH) 3091 continue; 3092 3093 route |= 3094 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 3095 << ((dep - 1) * 4); 3096 } 3097 route = route >> 4; 3098 size_t bn = hub == sc->sc_bus.ub_roothub ? 0 : 1; 3099 3100 /* Locate port on upstream high speed hub */ 3101 for (adev = dev, hub = up->up_parent; 3102 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 3103 adev = hub, hub = hub->ud_myhub) 3104 ; 3105 if (hub) { 3106 int p; 3107 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 3108 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 3109 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 3110 goto found; 3111 } 3112 } 3113 panic("%s: cannot find HS port", __func__); 3114 found: 3115 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 3116 } else { 3117 dev->ud_myhsport = NULL; 3118 } 3119 3120 const size_t ctlrport = xhci_rhport2ctlrport(sc, bn, rhport); 3121 3122 DPRINTFN(4, "rhport %u ctlrport %u Route %05x hub %p", rhport, 3123 ctlrport, route, hub); 3124 3125 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 3126 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(ctlrport); 3127 } 3128 3129 /* 3130 * Setup whether device is hub, whether device uses MTT, and 3131 * TT informations if it uses MTT. 3132 */ 3133 static void 3134 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 3135 { 3136 struct usbd_device *dev = pipe->up_dev; 3137 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 3138 uint32_t speed = dev->ud_speed; 3139 uint8_t tthubslot, ttportnum; 3140 bool ishub; 3141 bool usemtt; 3142 3143 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3144 3145 /* 3146 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 3147 * tthubslot: 3148 * This is the slot ID of parent HS hub 3149 * if LS/FS device is connected && connected through HS hub. 3150 * This is 0 if device is not LS/FS device || 3151 * parent hub is not HS hub || 3152 * attached to root hub. 3153 * ttportnum: 3154 * This is the downstream facing port of parent HS hub 3155 * if LS/FS device is connected. 3156 * This is 0 if device is not LS/FS device || 3157 * parent hub is not HS hub || 3158 * attached to root hub. 3159 */ 3160 if (dev->ud_myhsport != NULL && 3161 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3162 (dev->ud_myhub != NULL && 3163 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3164 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 3165 ttportnum = dev->ud_myhsport->up_portno; 3166 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 3167 } else { 3168 ttportnum = 0; 3169 tthubslot = 0; 3170 } 3171 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 3172 dev->ud_myhsport, ttportnum, tthubslot, 0); 3173 3174 /* ishub is valid after reading UDESC_DEVICE */ 3175 ishub = (dd->bDeviceClass == UDCLASS_HUB); 3176 3177 /* dev->ud_hub is valid after reading UDESC_HUB */ 3178 if (ishub && dev->ud_hub) { 3179 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 3180 uint8_t ttt = 3181 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 3182 3183 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 3184 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 3185 DPRINTFN(4, "nports=%d ttt=%d", hd->bNbrPorts, ttt, 0, 0); 3186 } 3187 3188 #define IS_TTHUB(dd) \ 3189 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 3190 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 3191 3192 /* 3193 * MTT flag is set if 3194 * 1. this is HS hub && MTT is enabled 3195 * or 3196 * 2. this is not hub && this is LS or FS device && 3197 * MTT of parent HS hub (and its parent, too) is enabled 3198 */ 3199 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 3200 usemtt = true; 3201 else if (!ishub && 3202 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 3203 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3204 (dev->ud_myhub != NULL && 3205 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3206 dev->ud_myhsport != NULL && 3207 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 3208 usemtt = true; 3209 else 3210 usemtt = false; 3211 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 3212 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 3213 3214 #undef IS_TTHUB 3215 3216 cp[0] |= 3217 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 3218 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 3219 cp[2] |= 3220 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 3221 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 3222 } 3223 3224 /* set up params for periodic endpoint */ 3225 static void 3226 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 3227 { 3228 struct usbd_device *dev = pipe->up_dev; 3229 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3230 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3231 usbd_desc_iter_t iter; 3232 const usb_cdc_descriptor_t *cdcd; 3233 uint32_t maxb = 0; 3234 uint16_t mps = UGETW(ed->wMaxPacketSize); 3235 uint8_t speed = dev->ud_speed; 3236 uint8_t ep; 3237 3238 /* config desc is NULL when opening ep0 */ 3239 if (dev == NULL || dev->ud_cdesc == NULL) 3240 goto no_cdcd; 3241 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 3242 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 3243 if (cdcd == NULL) 3244 goto no_cdcd; 3245 usb_desc_iter_init(dev, &iter); 3246 iter.cur = (const void *)cdcd; 3247 3248 /* find endpoint_ss_comp desc for ep of this pipe */ 3249 for (ep = 0;;) { 3250 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 3251 if (cdcd == NULL) 3252 break; 3253 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 3254 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 3255 bEndpointAddress; 3256 if (UE_GET_ADDR(ep) == 3257 UE_GET_ADDR(ed->bEndpointAddress)) { 3258 cdcd = (const usb_cdc_descriptor_t *) 3259 usb_desc_iter_next(&iter); 3260 break; 3261 } 3262 ep = 0; 3263 } 3264 } 3265 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 3266 const usb_endpoint_ss_comp_descriptor_t * esscd = 3267 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3268 maxb = esscd->bMaxBurst; 3269 } 3270 3271 no_cdcd: 3272 /* 6.2.3.4, 4.8.2.4 */ 3273 if (USB_IS_SS(speed)) { 3274 /* USB 3.1 9.6.6 */ 3275 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3276 /* USB 3.1 9.6.7 */ 3277 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3278 #ifdef notyet 3279 if (xfertype == UE_ISOCHRONOUS) { 3280 } 3281 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3282 /* use ESIT */ 3283 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3284 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3285 3286 /* XXX if LEC = 1, set ESIT instead */ 3287 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3288 } else { 3289 /* use ival */ 3290 } 3291 #endif 3292 } else { 3293 /* USB 2.0 9.6.6 */ 3294 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3295 3296 /* 6.2.3.4 */ 3297 if (speed == USB_SPEED_HIGH && 3298 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3299 maxb = UE_GET_TRANS(mps); 3300 } else { 3301 /* LS/FS or HS CTRL or HS BULK */ 3302 maxb = 0; 3303 } 3304 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3305 } 3306 } 3307 3308 /* 3309 * Convert endpoint bInterval value to endpoint context interval value 3310 * for Interrupt pipe. 3311 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3312 */ 3313 static uint32_t 3314 xhci_bival2ival(uint32_t ival, uint32_t speed) 3315 { 3316 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3317 int i; 3318 3319 /* 3320 * round ival down to "the nearest base 2 multiple of 3321 * bInterval * 8". 3322 * bInterval is at most 255 as its type is uByte. 3323 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3324 */ 3325 for (i = 10; i > 0; i--) { 3326 if ((ival * 8) >= (1 << i)) 3327 break; 3328 } 3329 ival = i; 3330 } else { 3331 /* Interval = bInterval-1 for SS/HS */ 3332 ival--; 3333 } 3334 3335 return ival; 3336 } 3337 3338 /* ----- */ 3339 3340 static void 3341 xhci_noop(struct usbd_pipe *pipe) 3342 { 3343 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3344 } 3345 3346 /* 3347 * Process root hub request. 3348 */ 3349 static int 3350 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3351 void *buf, int buflen) 3352 { 3353 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3354 usb_port_status_t ps; 3355 int l, totlen = 0; 3356 uint16_t len, value, index; 3357 int port, i; 3358 uint32_t v; 3359 3360 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3361 3362 if (sc->sc_dying) 3363 return -1; 3364 3365 size_t bn = bus == &sc->sc_bus ? 0 : 1; 3366 3367 len = UGETW(req->wLength); 3368 value = UGETW(req->wValue); 3369 index = UGETW(req->wIndex); 3370 3371 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 3372 req->bmRequestType | (req->bRequest << 8), value, index, len); 3373 3374 #define C(x,y) ((x) | ((y) << 8)) 3375 switch (C(req->bRequest, req->bmRequestType)) { 3376 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3377 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 3378 if (len == 0) 3379 break; 3380 switch (value) { 3381 case C(0, UDESC_DEVICE): { 3382 usb_device_descriptor_t devd; 3383 totlen = min(buflen, sizeof(devd)); 3384 memcpy(&devd, buf, totlen); 3385 USETW(devd.idVendor, sc->sc_id_vendor); 3386 memcpy(buf, &devd, totlen); 3387 break; 3388 } 3389 #define sd ((usb_string_descriptor_t *)buf) 3390 case C(1, UDESC_STRING): 3391 /* Vendor */ 3392 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3393 break; 3394 case C(2, UDESC_STRING): 3395 /* Product */ 3396 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3397 break; 3398 #undef sd 3399 default: 3400 /* default from usbroothub */ 3401 return buflen; 3402 } 3403 break; 3404 3405 /* Hub requests */ 3406 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3407 break; 3408 /* Clear Port Feature request */ 3409 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): { 3410 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3411 3412 DPRINTFN(4, "UR_CLEAR_PORT_FEAT bp=%d feat=%d bus=%d cp=%d", 3413 index, value, bn, cp); 3414 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3415 return -1; 3416 } 3417 port = XHCI_PORTSC(cp); 3418 v = xhci_op_read_4(sc, port); 3419 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3420 v &= ~XHCI_PS_CLEAR; 3421 switch (value) { 3422 case UHF_PORT_ENABLE: 3423 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3424 break; 3425 case UHF_PORT_SUSPEND: 3426 return -1; 3427 case UHF_PORT_POWER: 3428 break; 3429 case UHF_PORT_TEST: 3430 case UHF_PORT_INDICATOR: 3431 return -1; 3432 case UHF_C_PORT_CONNECTION: 3433 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3434 break; 3435 case UHF_C_PORT_ENABLE: 3436 case UHF_C_PORT_SUSPEND: 3437 case UHF_C_PORT_OVER_CURRENT: 3438 return -1; 3439 case UHF_C_BH_PORT_RESET: 3440 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3441 break; 3442 case UHF_C_PORT_RESET: 3443 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3444 break; 3445 case UHF_C_PORT_LINK_STATE: 3446 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3447 break; 3448 case UHF_C_PORT_CONFIG_ERROR: 3449 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3450 break; 3451 default: 3452 return -1; 3453 } 3454 break; 3455 } 3456 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3457 if (len == 0) 3458 break; 3459 if ((value & 0xff) != 0) { 3460 return -1; 3461 } 3462 usb_hub_descriptor_t hubd; 3463 3464 totlen = min(buflen, sizeof(hubd)); 3465 memcpy(&hubd, buf, totlen); 3466 hubd.bNbrPorts = sc->sc_rhportcount[bn]; 3467 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3468 hubd.bPwrOn2PwrGood = 200; 3469 for (i = 0, l = sc->sc_rhportcount[bn]; l > 0; i++, l -= 8) { 3470 /* XXX can't find out? */ 3471 hubd.DeviceRemovable[i++] = 0; 3472 } 3473 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3474 totlen = min(totlen, hubd.bDescLength); 3475 memcpy(buf, &hubd, totlen); 3476 break; 3477 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3478 if (len != 4) { 3479 return -1; 3480 } 3481 memset(buf, 0, len); /* ? XXX */ 3482 totlen = len; 3483 break; 3484 /* Get Port Status request */ 3485 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): { 3486 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3487 3488 DPRINTFN(8, "get port status bn=%d i=%d cp=%zu", bn, index, cp, 3489 0); 3490 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3491 return -1; 3492 } 3493 if (len != 4) { 3494 return -1; 3495 } 3496 v = xhci_op_read_4(sc, XHCI_PORTSC(cp)); 3497 DPRINTFN(4, "getrhportsc %d %08x", cp, v, 0, 0); 3498 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3499 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3500 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3501 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3502 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3503 if (v & XHCI_PS_PR) i |= UPS_RESET; 3504 if (v & XHCI_PS_PP) { 3505 if (i & UPS_OTHER_SPEED) 3506 i |= UPS_PORT_POWER_SS; 3507 else 3508 i |= UPS_PORT_POWER; 3509 } 3510 if (i & UPS_OTHER_SPEED) 3511 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3512 if (sc->sc_vendor_port_status) 3513 i = sc->sc_vendor_port_status(sc, v, i); 3514 USETW(ps.wPortStatus, i); 3515 i = 0; 3516 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3517 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3518 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3519 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3520 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3521 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3522 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3523 USETW(ps.wPortChange, i); 3524 totlen = min(len, sizeof(ps)); 3525 memcpy(buf, &ps, totlen); 3526 break; 3527 } 3528 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3529 return -1; 3530 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3531 break; 3532 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3533 break; 3534 /* Set Port Feature request */ 3535 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3536 int optval = (index >> 8) & 0xff; 3537 index &= 0xff; 3538 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3539 return -1; 3540 } 3541 3542 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3543 3544 port = XHCI_PORTSC(cp); 3545 v = xhci_op_read_4(sc, port); 3546 DPRINTFN(4, "index %d cp %d portsc=0x%08x", index, cp, v, 0); 3547 v &= ~XHCI_PS_CLEAR; 3548 switch (value) { 3549 case UHF_PORT_ENABLE: 3550 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3551 break; 3552 case UHF_PORT_SUSPEND: 3553 /* XXX suspend */ 3554 break; 3555 case UHF_PORT_RESET: 3556 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3557 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3558 /* Wait for reset to complete. */ 3559 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3560 if (sc->sc_dying) { 3561 return -1; 3562 } 3563 v = xhci_op_read_4(sc, port); 3564 if (v & XHCI_PS_PR) { 3565 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3566 usb_delay_ms(&sc->sc_bus, 10); 3567 /* XXX */ 3568 } 3569 break; 3570 case UHF_PORT_POWER: 3571 /* XXX power control */ 3572 break; 3573 /* XXX more */ 3574 case UHF_C_PORT_RESET: 3575 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3576 break; 3577 case UHF_PORT_U1_TIMEOUT: 3578 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3579 return -1; 3580 } 3581 port = XHCI_PORTPMSC(cp); 3582 v = xhci_op_read_4(sc, port); 3583 DPRINTFN(4, "index %d cp %d portpmsc=0x%08x", index, cp, v, 0); 3584 v &= ~XHCI_PM3_U1TO_SET(0xff); 3585 v |= XHCI_PM3_U1TO_SET(optval); 3586 xhci_op_write_4(sc, port, v); 3587 break; 3588 case UHF_PORT_U2_TIMEOUT: 3589 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3590 return -1; 3591 } 3592 port = XHCI_PORTPMSC(cp); 3593 v = xhci_op_read_4(sc, port); 3594 DPRINTFN(4, "index %d cp %d portpmsc=0x%08x", index, cp, v, 0); 3595 v &= ~XHCI_PM3_U2TO_SET(0xff); 3596 v |= XHCI_PM3_U2TO_SET(optval); 3597 xhci_op_write_4(sc, port, v); 3598 break; 3599 default: 3600 return -1; 3601 } 3602 } 3603 break; 3604 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3605 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3606 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3607 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3608 break; 3609 default: 3610 /* default from usbroothub */ 3611 return buflen; 3612 } 3613 3614 return totlen; 3615 } 3616 3617 /* root hub interrupt */ 3618 3619 static usbd_status 3620 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3621 { 3622 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3623 usbd_status err; 3624 3625 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3626 3627 /* Insert last in queue. */ 3628 mutex_enter(&sc->sc_lock); 3629 err = usb_insert_transfer(xfer); 3630 mutex_exit(&sc->sc_lock); 3631 if (err) 3632 return err; 3633 3634 /* Pipe isn't running, start first */ 3635 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3636 } 3637 3638 /* Wait for roothub port status/change */ 3639 static usbd_status 3640 xhci_root_intr_start(struct usbd_xfer *xfer) 3641 { 3642 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3643 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3644 3645 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3646 3647 if (sc->sc_dying) 3648 return USBD_IOERROR; 3649 3650 mutex_enter(&sc->sc_lock); 3651 sc->sc_intrxfer[bn] = xfer; 3652 mutex_exit(&sc->sc_lock); 3653 3654 return USBD_IN_PROGRESS; 3655 } 3656 3657 static void 3658 xhci_root_intr_abort(struct usbd_xfer *xfer) 3659 { 3660 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3661 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3662 3663 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3664 3665 KASSERT(mutex_owned(&sc->sc_lock)); 3666 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3667 3668 sc->sc_intrxfer[bn] = NULL; 3669 3670 xfer->ux_status = USBD_CANCELLED; 3671 usb_transfer_complete(xfer); 3672 } 3673 3674 static void 3675 xhci_root_intr_close(struct usbd_pipe *pipe) 3676 { 3677 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3678 const struct usbd_xfer *xfer = pipe->up_intrxfer; 3679 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3680 3681 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3682 3683 KASSERT(mutex_owned(&sc->sc_lock)); 3684 3685 sc->sc_intrxfer[bn] = NULL; 3686 } 3687 3688 static void 3689 xhci_root_intr_done(struct usbd_xfer *xfer) 3690 { 3691 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3692 3693 } 3694 3695 /* -------------- */ 3696 /* device control */ 3697 3698 static usbd_status 3699 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3700 { 3701 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3702 usbd_status err; 3703 3704 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3705 3706 /* Insert last in queue. */ 3707 mutex_enter(&sc->sc_lock); 3708 err = usb_insert_transfer(xfer); 3709 mutex_exit(&sc->sc_lock); 3710 if (err) 3711 return err; 3712 3713 /* Pipe isn't running, start first */ 3714 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3715 } 3716 3717 static usbd_status 3718 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3719 { 3720 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3721 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3722 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3723 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3724 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3725 usb_device_request_t * const req = &xfer->ux_request; 3726 const int isread = usbd_xfer_isread(xfer); 3727 const uint32_t len = UGETW(req->wLength); 3728 usb_dma_t * const dma = &xfer->ux_dmabuf; 3729 uint64_t parameter; 3730 uint32_t status; 3731 uint32_t control; 3732 u_int i; 3733 3734 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3735 DPRINTFN(12, "req: %04x %04x %04x %04x", 3736 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3737 UGETW(req->wIndex), UGETW(req->wLength)); 3738 3739 /* we rely on the bottom bits for extra info */ 3740 KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx", 3741 (uintptr_t) xfer); 3742 3743 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3744 3745 i = 0; 3746 3747 /* setup phase */ 3748 memcpy(¶meter, req, sizeof(parameter)); 3749 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3750 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3751 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3752 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3753 XHCI_TRB_3_IDT_BIT; 3754 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3755 3756 if (len != 0) { 3757 /* data phase */ 3758 parameter = DMAADDR(dma, 0); 3759 KASSERTMSG(len <= 0x10000, "len %d", len); 3760 status = XHCI_TRB_2_IRQ_SET(0) | 3761 XHCI_TRB_2_TDSZ_SET(1) | 3762 XHCI_TRB_2_BYTES_SET(len); 3763 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3764 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3765 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3766 XHCI_TRB_3_IOC_BIT; 3767 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3768 } 3769 3770 parameter = 0; 3771 status = XHCI_TRB_2_IRQ_SET(0); 3772 /* the status stage has inverted direction */ 3773 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3774 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3775 XHCI_TRB_3_IOC_BIT; 3776 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3777 3778 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3779 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3780 xhci_timeout, xfer); 3781 } 3782 xfer->ux_status = USBD_IN_PROGRESS; 3783 3784 mutex_enter(&tr->xr_lock); 3785 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3786 mutex_exit(&tr->xr_lock); 3787 3788 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3789 3790 return USBD_IN_PROGRESS; 3791 } 3792 3793 static void 3794 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3795 { 3796 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3797 usb_device_request_t *req = &xfer->ux_request; 3798 int len = UGETW(req->wLength); 3799 int rd = req->bmRequestType & UT_READ; 3800 3801 if (len) 3802 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3803 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3804 } 3805 3806 static void 3807 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3808 { 3809 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3810 3811 xhci_abort_xfer(xfer, USBD_CANCELLED); 3812 } 3813 3814 static void 3815 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3816 { 3817 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3818 3819 xhci_close_pipe(pipe); 3820 } 3821 3822 /* ------------------ */ 3823 /* device isochronous */ 3824 3825 /* ----------- */ 3826 /* device bulk */ 3827 3828 static usbd_status 3829 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3830 { 3831 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3832 usbd_status err; 3833 3834 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3835 3836 /* Insert last in queue. */ 3837 mutex_enter(&sc->sc_lock); 3838 err = usb_insert_transfer(xfer); 3839 mutex_exit(&sc->sc_lock); 3840 if (err) 3841 return err; 3842 3843 /* 3844 * Pipe isn't running (otherwise err would be USBD_INPROG), 3845 * so start it first. 3846 */ 3847 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3848 } 3849 3850 static usbd_status 3851 xhci_device_bulk_start(struct usbd_xfer *xfer) 3852 { 3853 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3854 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3855 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3856 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3857 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3858 const uint32_t len = xfer->ux_length; 3859 usb_dma_t * const dma = &xfer->ux_dmabuf; 3860 uint64_t parameter; 3861 uint32_t status; 3862 uint32_t control; 3863 u_int i = 0; 3864 3865 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3866 3867 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3868 3869 if (sc->sc_dying) 3870 return USBD_IOERROR; 3871 3872 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3873 3874 parameter = DMAADDR(dma, 0); 3875 /* 3876 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3877 * If the user supplied buffer crosses such a boundary then 2 3878 * (or more) TRB should be used. 3879 * If multiple TRB are used the td_size field must be set correctly. 3880 * For v1.0 devices (like ivy bridge) this is the number of usb data 3881 * blocks needed to complete the transfer. 3882 * Setting it to 1 in the last TRB causes an extra zero-length 3883 * data block be sent. 3884 * The earlier documentation differs, I don't know how it behaves. 3885 */ 3886 KASSERTMSG(len <= 0x10000, "len %d", len); 3887 status = XHCI_TRB_2_IRQ_SET(0) | 3888 XHCI_TRB_2_TDSZ_SET(1) | 3889 XHCI_TRB_2_BYTES_SET(len); 3890 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3891 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3892 XHCI_TRB_3_IOC_BIT; 3893 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3894 3895 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3896 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3897 xhci_timeout, xfer); 3898 } 3899 xfer->ux_status = USBD_IN_PROGRESS; 3900 3901 mutex_enter(&tr->xr_lock); 3902 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3903 mutex_exit(&tr->xr_lock); 3904 3905 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3906 3907 return USBD_IN_PROGRESS; 3908 } 3909 3910 static void 3911 xhci_device_bulk_done(struct usbd_xfer *xfer) 3912 { 3913 #ifdef USB_DEBUG 3914 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3915 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3916 #endif 3917 const int isread = usbd_xfer_isread(xfer); 3918 3919 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3920 3921 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3922 3923 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3924 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3925 } 3926 3927 static void 3928 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3929 { 3930 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3931 3932 xhci_abort_xfer(xfer, USBD_CANCELLED); 3933 } 3934 3935 static void 3936 xhci_device_bulk_close(struct usbd_pipe *pipe) 3937 { 3938 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3939 3940 xhci_close_pipe(pipe); 3941 } 3942 3943 /* ---------------- */ 3944 /* device interrupt */ 3945 3946 static usbd_status 3947 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3948 { 3949 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3950 usbd_status err; 3951 3952 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3953 3954 /* Insert last in queue. */ 3955 mutex_enter(&sc->sc_lock); 3956 err = usb_insert_transfer(xfer); 3957 mutex_exit(&sc->sc_lock); 3958 if (err) 3959 return err; 3960 3961 /* 3962 * Pipe isn't running (otherwise err would be USBD_INPROG), 3963 * so start it first. 3964 */ 3965 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3966 } 3967 3968 static usbd_status 3969 xhci_device_intr_start(struct usbd_xfer *xfer) 3970 { 3971 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3972 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3973 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3974 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3975 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3976 const uint32_t len = xfer->ux_length; 3977 usb_dma_t * const dma = &xfer->ux_dmabuf; 3978 uint64_t parameter; 3979 uint32_t status; 3980 uint32_t control; 3981 u_int i = 0; 3982 3983 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3984 3985 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3986 3987 if (sc->sc_dying) 3988 return USBD_IOERROR; 3989 3990 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3991 3992 parameter = DMAADDR(dma, 0); 3993 KASSERTMSG(len <= 0x10000, "len %d", len); 3994 status = XHCI_TRB_2_IRQ_SET(0) | 3995 XHCI_TRB_2_TDSZ_SET(1) | 3996 XHCI_TRB_2_BYTES_SET(len); 3997 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3998 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3999 XHCI_TRB_3_IOC_BIT; 4000 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 4001 4002 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4003 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4004 xhci_timeout, xfer); 4005 } 4006 xfer->ux_status = USBD_IN_PROGRESS; 4007 4008 mutex_enter(&tr->xr_lock); 4009 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 4010 mutex_exit(&tr->xr_lock); 4011 4012 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4013 4014 return USBD_IN_PROGRESS; 4015 } 4016 4017 static void 4018 xhci_device_intr_done(struct usbd_xfer *xfer) 4019 { 4020 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4021 #ifdef USB_DEBUG 4022 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4023 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4024 #endif 4025 const int isread = usbd_xfer_isread(xfer); 4026 4027 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4028 4029 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 4030 4031 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4032 4033 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4034 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4035 } 4036 4037 static void 4038 xhci_device_intr_abort(struct usbd_xfer *xfer) 4039 { 4040 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4041 4042 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4043 4044 KASSERT(mutex_owned(&sc->sc_lock)); 4045 DPRINTFN(15, "%p", xfer, 0, 0, 0); 4046 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4047 xhci_abort_xfer(xfer, USBD_CANCELLED); 4048 } 4049 4050 static void 4051 xhci_device_intr_close(struct usbd_pipe *pipe) 4052 { 4053 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 4054 4055 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4056 DPRINTFN(15, "%p", pipe, 0, 0, 0); 4057 4058 xhci_close_pipe(pipe); 4059 } 4060 4061 /* ------------ */ 4062 4063 static void 4064 xhci_timeout(void *addr) 4065 { 4066 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4067 struct xhci_xfer * const xx = addr; 4068 struct usbd_xfer * const xfer = &xx->xx_xfer; 4069 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4070 bool timeout = false; 4071 4072 mutex_enter(&sc->sc_lock); 4073 if (sc->sc_dying) { 4074 mutex_exit(&sc->sc_lock); 4075 return; 4076 } 4077 if (xfer->ux_status != USBD_CANCELLED) { 4078 xfer->ux_status = USBD_TIMEOUT; 4079 timeout = true; 4080 } 4081 mutex_exit(&sc->sc_lock); 4082 4083 if (timeout) { 4084 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4085 4086 /* Execute the abort in a process context. */ 4087 usb_init_task(&xfer->ux_aborttask, xhci_timeout_task, xfer, 4088 USB_TASKQ_MPSAFE); 4089 usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC); 4090 } 4091 } 4092 4093 static void 4094 xhci_timeout_task(void *addr) 4095 { 4096 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4097 struct usbd_xfer * const xfer = addr; 4098 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4099 4100 mutex_enter(&sc->sc_lock); 4101 KASSERT(xfer->ux_status == USBD_TIMEOUT); 4102 xhci_abort_xfer(xfer, USBD_TIMEOUT); 4103 mutex_exit(&sc->sc_lock); 4104 } 4105
Indexes created Wed Oct 01 15:09:59 GMT 2025