xhci.c revision 1.28.2.85
1 /* $NetBSD: xhci.c,v 1.28.2.85 2017/02/05 13:40:48 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.28.2.85 2017/02/05 13:40:48 skrll Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static void xhci_host_dequeue(struct xhci_ring * const); 146 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 147 148 static usbd_status xhci_do_command(struct xhci_softc * const, 149 struct xhci_trb * const, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 153 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 154 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 155 static usbd_status xhci_enable_slot(struct xhci_softc * const, 156 uint8_t * const); 157 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 158 static usbd_status xhci_address_device(struct xhci_softc * const, 159 uint64_t, uint8_t, bool); 160 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 161 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 162 struct xhci_slot * const, u_int); 163 static usbd_status xhci_ring_init(struct xhci_softc * const, 164 struct xhci_ring * const, size_t, size_t); 165 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 166 167 static void xhci_setup_ctx(struct usbd_pipe *); 168 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 169 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 170 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 171 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 172 173 static void xhci_noop(struct usbd_pipe *); 174 175 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 176 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 177 static void xhci_root_intr_abort(struct usbd_xfer *); 178 static void xhci_root_intr_close(struct usbd_pipe *); 179 static void xhci_root_intr_done(struct usbd_xfer *); 180 181 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 182 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 183 static void xhci_device_ctrl_abort(struct usbd_xfer *); 184 static void xhci_device_ctrl_close(struct usbd_pipe *); 185 static void xhci_device_ctrl_done(struct usbd_xfer *); 186 187 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 188 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 189 static void xhci_device_intr_abort(struct usbd_xfer *); 190 static void xhci_device_intr_close(struct usbd_pipe *); 191 static void xhci_device_intr_done(struct usbd_xfer *); 192 193 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 194 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 195 static void xhci_device_bulk_abort(struct usbd_xfer *); 196 static void xhci_device_bulk_close(struct usbd_pipe *); 197 static void xhci_device_bulk_done(struct usbd_xfer *); 198 199 static void xhci_timeout(void *); 200 static void xhci_timeout_task(void *); 201 202 static const struct usbd_bus_methods xhci_bus_methods = { 203 .ubm_open = xhci_open, 204 .ubm_softint = xhci_softintr, 205 .ubm_dopoll = xhci_poll, 206 .ubm_allocx = xhci_allocx, 207 .ubm_freex = xhci_freex, 208 .ubm_getlock = xhci_get_lock, 209 .ubm_newdev = xhci_new_device, 210 .ubm_rhctrl = xhci_roothub_ctrl, 211 }; 212 213 static const struct usbd_pipe_methods xhci_root_intr_methods = { 214 .upm_transfer = xhci_root_intr_transfer, 215 .upm_start = xhci_root_intr_start, 216 .upm_abort = xhci_root_intr_abort, 217 .upm_close = xhci_root_intr_close, 218 .upm_cleartoggle = xhci_noop, 219 .upm_done = xhci_root_intr_done, 220 }; 221 222 223 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 224 .upm_transfer = xhci_device_ctrl_transfer, 225 .upm_start = xhci_device_ctrl_start, 226 .upm_abort = xhci_device_ctrl_abort, 227 .upm_close = xhci_device_ctrl_close, 228 .upm_cleartoggle = xhci_noop, 229 .upm_done = xhci_device_ctrl_done, 230 }; 231 232 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 233 .upm_cleartoggle = xhci_noop, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 237 .upm_transfer = xhci_device_bulk_transfer, 238 .upm_start = xhci_device_bulk_start, 239 .upm_abort = xhci_device_bulk_abort, 240 .upm_close = xhci_device_bulk_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_bulk_done, 243 }; 244 245 static const struct usbd_pipe_methods xhci_device_intr_methods = { 246 .upm_transfer = xhci_device_intr_transfer, 247 .upm_start = xhci_device_intr_start, 248 .upm_abort = xhci_device_intr_abort, 249 .upm_close = xhci_device_intr_close, 250 .upm_cleartoggle = xhci_noop, 251 .upm_done = xhci_device_intr_done, 252 }; 253 254 static inline uint32_t 255 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 256 { 257 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 258 } 259 260 static inline uint32_t 261 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 262 { 263 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 264 } 265 266 static inline void 267 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 268 uint32_t value) 269 { 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 271 } 272 273 #if 0 /* unused */ 274 static inline void 275 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 276 uint32_t value) 277 { 278 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 279 } 280 #endif /* unused */ 281 282 static inline uint32_t 283 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 284 { 285 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 286 } 287 288 static inline uint32_t 289 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 290 { 291 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 292 } 293 294 static inline void 295 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 296 uint32_t value) 297 { 298 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 299 } 300 301 static inline uint64_t 302 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 303 { 304 uint64_t value; 305 306 if (sc->sc_ac64) { 307 #ifdef XHCI_USE_BUS_SPACE_8 308 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 309 #else 310 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 311 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 312 offset + 4) << 32; 313 #endif 314 } else { 315 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 316 } 317 318 return value; 319 } 320 321 static inline void 322 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 336 } 337 } 338 339 static inline uint32_t 340 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 341 { 342 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 343 } 344 345 static inline void 346 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 347 uint32_t value) 348 { 349 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 350 } 351 352 #if 0 /* unused */ 353 static inline uint64_t 354 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 355 { 356 uint64_t value; 357 358 if (sc->sc_ac64) { 359 #ifdef XHCI_USE_BUS_SPACE_8 360 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 361 #else 362 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 363 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 364 offset + 4) << 32; 365 #endif 366 } else { 367 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 368 } 369 370 return value; 371 } 372 #endif /* unused */ 373 374 static inline void 375 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 376 uint64_t value) 377 { 378 if (sc->sc_ac64) { 379 #ifdef XHCI_USE_BUS_SPACE_8 380 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 381 #else 382 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 383 (value >> 0) & 0xffffffff); 384 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 385 (value >> 32) & 0xffffffff); 386 #endif 387 } else { 388 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 389 } 390 } 391 392 #if 0 /* unused */ 393 static inline uint32_t 394 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 395 { 396 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 397 } 398 #endif /* unused */ 399 400 static inline void 401 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 402 uint32_t value) 403 { 404 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 405 } 406 407 /* --- */ 408 409 static inline uint8_t 410 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 411 { 412 u_int eptype = 0; 413 414 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 415 case UE_CONTROL: 416 eptype = 0x0; 417 break; 418 case UE_ISOCHRONOUS: 419 eptype = 0x1; 420 break; 421 case UE_BULK: 422 eptype = 0x2; 423 break; 424 case UE_INTERRUPT: 425 eptype = 0x3; 426 break; 427 } 428 429 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 430 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 431 return eptype | 0x4; 432 else 433 return eptype; 434 } 435 436 static u_int 437 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 438 { 439 /* xHCI 1.0 section 4.5.1 */ 440 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 441 u_int in = 0; 442 443 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 444 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 445 in = 1; 446 447 return epaddr * 2 + in; 448 } 449 450 static inline u_int 451 xhci_dci_to_ici(const u_int i) 452 { 453 return i + 1; 454 } 455 456 static inline void * 457 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 458 const u_int dci) 459 { 460 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 461 } 462 463 #if 0 /* unused */ 464 static inline bus_addr_t 465 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 466 const u_int dci) 467 { 468 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 469 } 470 #endif /* unused */ 471 472 static inline void * 473 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline bus_addr_t 480 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 481 const u_int ici) 482 { 483 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 484 } 485 486 static inline struct xhci_trb * 487 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 488 { 489 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 490 } 491 492 static inline bus_addr_t 493 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 494 { 495 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 496 } 497 498 static inline void 499 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 500 uint32_t control) 501 { 502 trb->trb_0 = htole64(parameter); 503 trb->trb_2 = htole32(status); 504 trb->trb_3 = htole32(control); 505 } 506 507 static int 508 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 509 { 510 /* base address of TRBs */ 511 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 512 513 /* trb_0 range sanity check */ 514 if (trb_0 == 0 || trb_0 < trbp || 515 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 516 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 517 return 1; 518 } 519 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 520 return 0; 521 } 522 523 static unsigned int 524 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 525 u_int dci) 526 { 527 uint32_t *cp; 528 529 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 530 cp = xhci_slot_get_dcv(sc, xs, dci); 531 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 532 } 533 534 static inline unsigned int 535 xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport) 536 { 537 const unsigned int port = ctlrport - 1; 538 const uint8_t bit = __BIT(port % NBBY); 539 540 return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit); 541 } 542 543 /* 544 * Return the roothub port for a controller port. Both are 1..n. 545 */ 546 static inline unsigned int 547 xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport) 548 { 549 550 return sc->sc_ctlrportmap[ctrlport - 1]; 551 } 552 553 /* 554 * Return the controller port for a bus roothub port. Both are 1..n. 555 */ 556 static inline unsigned int 557 xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn, 558 unsigned int rhport) 559 { 560 561 return sc->sc_rhportmap[bn][rhport - 1]; 562 } 563 564 /* --- */ 565 566 void 567 xhci_childdet(device_t self, device_t child) 568 { 569 struct xhci_softc * const sc = device_private(self); 570 571 KASSERT(sc->sc_child == child); 572 if (child == sc->sc_child) 573 sc->sc_child = NULL; 574 } 575 576 int 577 xhci_detach(struct xhci_softc *sc, int flags) 578 { 579 int rv = 0; 580 581 if (sc->sc_child2 != NULL) { 582 rv = config_detach(sc->sc_child2, flags); 583 if (rv != 0) 584 return rv; 585 } 586 587 if (sc->sc_child != NULL) { 588 rv = config_detach(sc->sc_child, flags); 589 if (rv != 0) 590 return rv; 591 } 592 593 /* XXX unconfigure/free slots */ 594 595 /* verify: */ 596 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 597 xhci_op_write_4(sc, XHCI_USBCMD, 0); 598 /* do we need to wait for stop? */ 599 600 xhci_op_write_8(sc, XHCI_CRCR, 0); 601 xhci_ring_free(sc, &sc->sc_cr); 602 cv_destroy(&sc->sc_command_cv); 603 cv_destroy(&sc->sc_cmdbusy_cv); 604 605 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 606 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 607 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 608 xhci_ring_free(sc, &sc->sc_er); 609 610 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 611 612 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 613 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 614 615 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 616 617 kmem_free(sc->sc_ctlrportbus, 618 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY)); 619 kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int)); 620 621 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 622 kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int)); 623 } 624 625 mutex_destroy(&sc->sc_lock); 626 mutex_destroy(&sc->sc_intr_lock); 627 628 pool_cache_destroy(sc->sc_xferpool); 629 630 return rv; 631 } 632 633 int 634 xhci_activate(device_t self, enum devact act) 635 { 636 struct xhci_softc * const sc = device_private(self); 637 638 switch (act) { 639 case DVACT_DEACTIVATE: 640 sc->sc_dying = true; 641 return 0; 642 default: 643 return EOPNOTSUPP; 644 } 645 } 646 647 bool 648 xhci_suspend(device_t dv, const pmf_qual_t *qual) 649 { 650 return false; 651 } 652 653 bool 654 xhci_resume(device_t dv, const pmf_qual_t *qual) 655 { 656 return false; 657 } 658 659 bool 660 xhci_shutdown(device_t self, int flags) 661 { 662 return false; 663 } 664 665 static int 666 xhci_hc_reset(struct xhci_softc * const sc) 667 { 668 uint32_t usbcmd, usbsts; 669 int i; 670 671 /* Check controller not ready */ 672 for (i = 0; i < XHCI_WAIT_CNR; i++) { 673 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 674 if ((usbsts & XHCI_STS_CNR) == 0) 675 break; 676 usb_delay_ms(&sc->sc_bus, 1); 677 } 678 if (i >= XHCI_WAIT_CNR) { 679 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 680 return EIO; 681 } 682 683 /* Halt controller */ 684 usbcmd = 0; 685 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 686 usb_delay_ms(&sc->sc_bus, 1); 687 688 /* Reset controller */ 689 usbcmd = XHCI_CMD_HCRST; 690 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 691 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 692 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 693 if ((usbcmd & XHCI_CMD_HCRST) == 0) 694 break; 695 usb_delay_ms(&sc->sc_bus, 1); 696 } 697 if (i >= XHCI_WAIT_HCRST) { 698 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 699 return EIO; 700 } 701 702 /* Check controller not ready */ 703 for (i = 0; i < XHCI_WAIT_CNR; i++) { 704 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 705 if ((usbsts & XHCI_STS_CNR) == 0) 706 break; 707 usb_delay_ms(&sc->sc_bus, 1); 708 } 709 if (i >= XHCI_WAIT_CNR) { 710 aprint_error_dev(sc->sc_dev, 711 "controller not ready timeout after reset\n"); 712 return EIO; 713 } 714 715 return 0; 716 } 717 718 719 static void 720 hexdump(const char *msg, const void *base, size_t len) 721 { 722 #if 0 723 size_t cnt; 724 const uint32_t *p; 725 extern paddr_t vtophys(vaddr_t); 726 727 p = base; 728 cnt = 0; 729 730 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 731 (void *)vtophys((vaddr_t)base)); 732 733 while (cnt < len) { 734 if (cnt % 16 == 0) 735 printf("%p: ", p); 736 else if (cnt % 8 == 0) 737 printf(" |"); 738 printf(" %08x", *p++); 739 cnt += 4; 740 if (cnt % 16 == 0) 741 printf("\n"); 742 } 743 if (cnt % 16 != 0) 744 printf("\n"); 745 #endif 746 } 747 748 /* 7.2 xHCI Support Protocol Capability */ 749 static void 750 xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp) 751 { 752 /* XXX Cache this lot */ 753 754 const uint32_t w0 = xhci_read_4(sc, ecp); 755 const uint32_t w4 = xhci_read_4(sc, ecp + 4); 756 const uint32_t w8 = xhci_read_4(sc, ecp + 8); 757 const uint32_t wc = xhci_read_4(sc, ecp + 0xc); 758 759 aprint_debug_dev(sc->sc_dev, 760 " SP: %08x %08x %08x %08x\n", w0, w4, w8, wc); 761 762 if (w4 != XHCI_XECP_USBID) 763 return; 764 765 const int major = XHCI_XECP_SP_W0_MAJOR(w0); 766 const int minor = XHCI_XECP_SP_W0_MINOR(w0); 767 const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8); 768 const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8); 769 770 const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16)); 771 switch (mm) { 772 case 0x0200: 773 case 0x0300: 774 case 0x0301: 775 aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n", 776 major == 3 ? "ss" : "hs", cpo, cpo + cpc -1); 777 break; 778 default: 779 aprint_debug_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n", 780 major, minor); 781 return; 782 } 783 784 const size_t bus = (major == 3) ? 0 : 1; 785 786 /* Index arrays with 0..n-1 where ports are numbered 1..n */ 787 for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) { 788 if (sc->sc_ctlrportmap[cp] != 0) { 789 aprint_error_dev(sc->sc_dev, "contoller port %zu " 790 "already assigned", cp); 791 continue; 792 } 793 794 sc->sc_ctlrportbus[cp / NBBY] |= 795 bus == 0 ? 0 : __BIT(cp % NBBY); 796 797 const size_t rhp = sc->sc_rhportcount[bus]++; 798 799 KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0, 800 "bus %zu rhp %zu is %d", bus, rhp, 801 sc->sc_rhportmap[bus][rhp]); 802 803 sc->sc_rhportmap[bus][rhp] = cp + 1; 804 sc->sc_ctlrportmap[cp] = rhp + 1; 805 } 806 } 807 808 /* Process extended capabilities */ 809 static void 810 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 811 { 812 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 813 814 bus_size_t ecp = XHCI_HCC_XECP(hcc) * 4; 815 while (ecp != 0) { 816 uint32_t ecr = xhci_read_4(sc, ecp); 817 aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr); 818 switch (XHCI_XECP_ID(ecr)) { 819 case XHCI_ID_PROTOCOLS: { 820 xhci_id_protocols(sc, ecp); 821 break; 822 } 823 case XHCI_ID_USB_LEGACY: { 824 uint8_t bios_sem; 825 826 /* Take host controller ownership from BIOS */ 827 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 828 if (bios_sem) { 829 /* sets xHCI to be owned by OS */ 830 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 831 aprint_debug_dev(sc->sc_dev, 832 "waiting for BIOS to give up control\n"); 833 for (int i = 0; i < 5000; i++) { 834 bios_sem = xhci_read_1(sc, ecp + 835 XHCI_XECP_BIOS_SEM); 836 if (bios_sem == 0) 837 break; 838 DELAY(1000); 839 } 840 if (bios_sem) { 841 aprint_error_dev(sc->sc_dev, 842 "timed out waiting for BIOS\n"); 843 } 844 } 845 break; 846 } 847 default: 848 break; 849 } 850 ecr = xhci_read_4(sc, ecp); 851 if (XHCI_XECP_NEXT(ecr) == 0) { 852 ecp = 0; 853 } else { 854 ecp += XHCI_XECP_NEXT(ecr) * 4; 855 } 856 } 857 } 858 859 #define XHCI_HCCPREV1_BITS \ 860 "\177\020" /* New bitmask */ \ 861 "f\020\020XECP\0" \ 862 "f\014\4MAXPSA\0" \ 863 "b\013CFC\0" \ 864 "b\012SEC\0" \ 865 "b\011SBD\0" \ 866 "b\010FSE\0" \ 867 "b\7NSS\0" \ 868 "b\6LTC\0" \ 869 "b\5LHRC\0" \ 870 "b\4PIND\0" \ 871 "b\3PPC\0" \ 872 "b\2CZC\0" \ 873 "b\1BNC\0" \ 874 "b\0AC64\0" \ 875 "\0" 876 #define XHCI_HCCV1_x_BITS \ 877 "\177\020" /* New bitmask */ \ 878 "f\020\020XECP\0" \ 879 "f\014\4MAXPSA\0" \ 880 "b\013CFC\0" \ 881 "b\012SEC\0" \ 882 "b\011SPC\0" \ 883 "b\010PAE\0" \ 884 "b\7NSS\0" \ 885 "b\6LTC\0" \ 886 "b\5LHRC\0" \ 887 "b\4PIND\0" \ 888 "b\3PPC\0" \ 889 "b\2CSZ\0" \ 890 "b\1BNC\0" \ 891 "b\0AC64\0" \ 892 "\0" 893 894 int 895 xhci_init(struct xhci_softc *sc) 896 { 897 bus_size_t bsz; 898 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 899 uint32_t pagesize, config; 900 int i = 0; 901 uint16_t hciversion; 902 uint8_t caplength; 903 904 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 905 906 /* Set up the bus struct for the usb 3 and usb 2 buses */ 907 sc->sc_bus.ub_methods = &xhci_bus_methods; 908 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 909 sc->sc_bus.ub_revision = USBREV_3_0; 910 sc->sc_bus.ub_usedma = true; 911 sc->sc_bus.ub_hcpriv = sc; 912 913 sc->sc_bus2.ub_methods = &xhci_bus_methods; 914 sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe); 915 sc->sc_bus2.ub_revision = USBREV_2_0; 916 sc->sc_bus2.ub_usedma = true; 917 sc->sc_bus2.ub_hcpriv = sc; 918 sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag; 919 920 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 921 caplength = XHCI_CAP_CAPLENGTH(cap); 922 hciversion = XHCI_CAP_HCIVERSION(cap); 923 924 if (hciversion < XHCI_HCIVERSION_0_96 || 925 hciversion > XHCI_HCIVERSION_1_0) { 926 aprint_normal_dev(sc->sc_dev, 927 "xHCI version %x.%x not known to be supported\n", 928 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 929 } else { 930 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 931 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 932 } 933 934 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 935 &sc->sc_cbh) != 0) { 936 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 937 return ENOMEM; 938 } 939 940 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 941 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 942 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 943 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 944 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 945 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 946 aprint_debug_dev(sc->sc_dev, 947 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 948 949 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 950 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 951 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 952 953 char sbuf[128]; 954 if (hciversion < XHCI_HCIVERSION_1_0) 955 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 956 else 957 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 958 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 959 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 960 961 /* default all ports to bus 0, i.e. usb 3 */ 962 sc->sc_ctlrportbus = kmem_zalloc( 963 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP); 964 sc->sc_ctlrportmap = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 965 966 /* controller port to bus roothub port map */ 967 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 968 sc->sc_rhportmap[j] = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 969 } 970 971 /* 972 * Process all Extended Capabilities 973 */ 974 xhci_ecp(sc, hcc); 975 976 bsz = XHCI_PORTSC(sc->sc_maxports); 977 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 978 &sc->sc_obh) != 0) { 979 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 980 return ENOMEM; 981 } 982 983 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 984 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 985 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 986 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 987 return ENOMEM; 988 } 989 990 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 991 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 992 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 993 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 994 return ENOMEM; 995 } 996 997 int rv; 998 rv = xhci_hc_reset(sc); 999 if (rv != 0) { 1000 return rv; 1001 } 1002 1003 if (sc->sc_vendor_init) 1004 sc->sc_vendor_init(sc); 1005 1006 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 1007 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 1008 pagesize = ffs(pagesize); 1009 if (pagesize == 0) { 1010 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 1011 return EIO; 1012 } 1013 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 1014 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 1015 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 1016 (uint32_t)sc->sc_maxslots); 1017 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 1018 1019 usbd_status err; 1020 1021 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 1022 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 1023 if (sc->sc_maxspbuf != 0) { 1024 err = usb_allocmem(&sc->sc_bus, 1025 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 1026 &sc->sc_spbufarray_dma); 1027 if (err) { 1028 aprint_error_dev(sc->sc_dev, 1029 "spbufarray init fail, err %d\n", err); 1030 return ENOMEM; 1031 } 1032 1033 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 1034 sc->sc_maxspbuf, KM_SLEEP); 1035 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 1036 for (i = 0; i < sc->sc_maxspbuf; i++) { 1037 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 1038 /* allocate contexts */ 1039 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 1040 sc->sc_pgsz, dma); 1041 if (err) { 1042 aprint_error_dev(sc->sc_dev, 1043 "spbufarray_dma init fail, err %d\n", err); 1044 rv = ENOMEM; 1045 goto bad1; 1046 } 1047 spbufarray[i] = htole64(DMAADDR(dma, 0)); 1048 usb_syncmem(dma, 0, sc->sc_pgsz, 1049 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1050 } 1051 1052 usb_syncmem(&sc->sc_spbufarray_dma, 0, 1053 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 1054 } 1055 1056 config = xhci_op_read_4(sc, XHCI_CONFIG); 1057 config &= ~0xFF; 1058 config |= sc->sc_maxslots & 0xFF; 1059 xhci_op_write_4(sc, XHCI_CONFIG, config); 1060 1061 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 1062 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 1063 if (err) { 1064 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 1065 err); 1066 rv = ENOMEM; 1067 goto bad1; 1068 } 1069 1070 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 1071 XHCI_EVENT_RING_SEGMENTS_ALIGN); 1072 if (err) { 1073 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 1074 err); 1075 rv = ENOMEM; 1076 goto bad2; 1077 } 1078 1079 usb_dma_t *dma; 1080 size_t size; 1081 size_t align; 1082 1083 dma = &sc->sc_eventst_dma; 1084 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 1085 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 1086 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 1087 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 1088 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1089 if (err) { 1090 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 1091 err); 1092 rv = ENOMEM; 1093 goto bad3; 1094 } 1095 1096 memset(KERNADDR(dma, 0), 0, size); 1097 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1098 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 1099 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 1100 KERNADDR(&sc->sc_eventst_dma, 0), 1101 sc->sc_eventst_dma.udma_block->size); 1102 1103 dma = &sc->sc_dcbaa_dma; 1104 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 1105 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 1106 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 1107 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1108 if (err) { 1109 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1110 rv = ENOMEM; 1111 goto bad4; 1112 } 1113 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 1114 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1115 KERNADDR(&sc->sc_dcbaa_dma, 0), 1116 sc->sc_dcbaa_dma.udma_block->size); 1117 1118 memset(KERNADDR(dma, 0), 0, size); 1119 if (sc->sc_maxspbuf != 0) { 1120 /* 1121 * DCBA entry 0 hold the scratchbuf array pointer. 1122 */ 1123 *(uint64_t *)KERNADDR(dma, 0) = 1124 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1125 } 1126 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1127 1128 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1129 KM_SLEEP); 1130 if (sc->sc_slots == NULL) { 1131 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1132 rv = ENOMEM; 1133 goto bad; 1134 } 1135 1136 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1137 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1138 if (sc->sc_xferpool == NULL) { 1139 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1140 err); 1141 rv = ENOMEM; 1142 goto bad; 1143 } 1144 1145 cv_init(&sc->sc_command_cv, "xhcicmd"); 1146 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1147 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1148 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1149 1150 struct xhci_erste *erst; 1151 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1152 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1153 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1154 erst[0].erste_3 = htole32(0); 1155 usb_syncmem(&sc->sc_eventst_dma, 0, 1156 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1157 1158 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1159 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1160 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1161 XHCI_ERDP_LO_BUSY); 1162 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1163 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1164 sc->sc_cr.xr_cs); 1165 1166 #if 0 1167 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1168 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1169 #endif 1170 1171 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1172 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1173 /* Intel xhci needs interrupt rate moderated. */ 1174 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1175 else 1176 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1177 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 1178 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1179 1180 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 1181 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1182 xhci_op_read_4(sc, XHCI_USBCMD)); 1183 1184 return 0; 1185 1186 bad: 1187 if (sc->sc_xferpool) { 1188 pool_cache_destroy(sc->sc_xferpool); 1189 sc->sc_xferpool = NULL; 1190 } 1191 1192 if (sc->sc_slots) { 1193 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1194 sc->sc_maxslots); 1195 sc->sc_slots = NULL; 1196 } 1197 1198 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1199 bad4: 1200 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1201 bad3: 1202 xhci_ring_free(sc, &sc->sc_er); 1203 bad2: 1204 xhci_ring_free(sc, &sc->sc_cr); 1205 i = sc->sc_maxspbuf; 1206 bad1: 1207 for (int j = 0; j < i; j++) 1208 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1209 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1210 1211 return rv; 1212 } 1213 1214 int 1215 xhci_intr(void *v) 1216 { 1217 struct xhci_softc * const sc = v; 1218 int ret = 0; 1219 1220 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1221 1222 if (sc == NULL) 1223 return 0; 1224 1225 mutex_spin_enter(&sc->sc_intr_lock); 1226 1227 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1228 goto done; 1229 1230 /* If we get an interrupt while polling, then just ignore it. */ 1231 if (sc->sc_bus.ub_usepolling) { 1232 #ifdef DIAGNOSTIC 1233 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1234 #endif 1235 goto done; 1236 } 1237 1238 ret = xhci_intr1(sc); 1239 done: 1240 mutex_spin_exit(&sc->sc_intr_lock); 1241 return ret; 1242 } 1243 1244 int 1245 xhci_intr1(struct xhci_softc * const sc) 1246 { 1247 uint32_t usbsts; 1248 uint32_t iman; 1249 1250 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1251 1252 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1253 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1254 #if 0 1255 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1256 return 0; 1257 } 1258 #endif 1259 xhci_op_write_4(sc, XHCI_USBSTS, 1260 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1261 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1262 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1263 1264 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1265 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1266 iman |= XHCI_IMAN_INTR_PEND; 1267 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1268 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1269 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1270 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1271 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1272 1273 usb_schedsoftintr(&sc->sc_bus); 1274 1275 return 1; 1276 } 1277 1278 /* 1279 * 3 port speed types used in USB stack 1280 * 1281 * usbdi speed 1282 * definition: USB_SPEED_* in usb.h 1283 * They are used in struct usbd_device in USB stack. 1284 * ioctl interface uses these values too. 1285 * port_status speed 1286 * definition: UPS_*_SPEED in usb.h 1287 * They are used in usb_port_status_t and valid only for USB 2.0. 1288 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1289 * of usb_port_status_ext_t indicates port speed. 1290 * Note that some 3.0 values overlap with 2.0 values. 1291 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1292 * means UPS_LOW_SPEED in HS.) 1293 * port status returned from hub also uses these values. 1294 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1295 * or more. 1296 * xspeed: 1297 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1298 * They are used in only slot context and PORTSC reg of xhci. 1299 * The difference between usbdi speed and xspeed is 1300 * that FS and LS values are swapped. 1301 */ 1302 1303 /* convert usbdi speed to xspeed */ 1304 static int 1305 xhci_speed2xspeed(int speed) 1306 { 1307 switch (speed) { 1308 case USB_SPEED_LOW: return 2; 1309 case USB_SPEED_FULL: return 1; 1310 default: return speed; 1311 } 1312 } 1313 1314 #if 0 1315 /* convert xspeed to usbdi speed */ 1316 static int 1317 xhci_xspeed2speed(int xspeed) 1318 { 1319 switch (xspeed) { 1320 case 1: return USB_SPEED_FULL; 1321 case 2: return USB_SPEED_LOW; 1322 default: return xspeed; 1323 } 1324 } 1325 #endif 1326 1327 /* convert xspeed to port status speed */ 1328 static int 1329 xhci_xspeed2psspeed(int xspeed) 1330 { 1331 switch (xspeed) { 1332 case 0: return 0; 1333 case 1: return UPS_FULL_SPEED; 1334 case 2: return UPS_LOW_SPEED; 1335 case 3: return UPS_HIGH_SPEED; 1336 default: return UPS_OTHER_SPEED; 1337 } 1338 } 1339 1340 /* 1341 * Construct input contexts and issue TRB to open pipe. 1342 */ 1343 static usbd_status 1344 xhci_configure_endpoint(struct usbd_pipe *pipe) 1345 { 1346 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1347 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1348 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1349 struct xhci_trb trb; 1350 usbd_status err; 1351 1352 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1353 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1354 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1355 pipe->up_endpoint->ue_edesc->bmAttributes); 1356 1357 /* XXX ensure input context is available? */ 1358 1359 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1360 1361 /* set up context */ 1362 xhci_setup_ctx(pipe); 1363 1364 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1365 sc->sc_ctxsz * 1); 1366 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1367 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1368 1369 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1370 trb.trb_2 = 0; 1371 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1372 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1373 1374 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1375 1376 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1377 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1378 sc->sc_ctxsz * 1); 1379 1380 return err; 1381 } 1382 1383 #if 0 1384 static usbd_status 1385 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1386 { 1387 #ifdef USB_DEBUG 1388 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1389 #endif 1390 1391 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1392 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1393 1394 return USBD_NORMAL_COMPLETION; 1395 } 1396 #endif 1397 1398 /* 4.6.8, 6.4.3.7 */ 1399 static usbd_status 1400 xhci_reset_endpoint_locked(struct usbd_pipe *pipe) 1401 { 1402 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1403 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1404 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1405 struct xhci_trb trb; 1406 usbd_status err; 1407 1408 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1409 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1410 1411 KASSERT(mutex_owned(&sc->sc_lock)); 1412 1413 trb.trb_0 = 0; 1414 trb.trb_2 = 0; 1415 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1416 XHCI_TRB_3_EP_SET(dci) | 1417 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1418 1419 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1420 1421 return err; 1422 } 1423 1424 static usbd_status 1425 xhci_reset_endpoint(struct usbd_pipe *pipe) 1426 { 1427 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1428 1429 mutex_enter(&sc->sc_lock); 1430 usbd_status ret = xhci_reset_endpoint_locked(pipe); 1431 mutex_exit(&sc->sc_lock); 1432 1433 return ret; 1434 } 1435 1436 /* 1437 * 4.6.9, 6.4.3.8 1438 * Stop execution of TDs on xfer ring. 1439 * Should be called with sc_lock held. 1440 */ 1441 static usbd_status 1442 xhci_stop_endpoint(struct usbd_pipe *pipe) 1443 { 1444 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1445 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1446 struct xhci_trb trb; 1447 usbd_status err; 1448 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1449 1450 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1451 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1452 1453 KASSERT(mutex_owned(&sc->sc_lock)); 1454 1455 trb.trb_0 = 0; 1456 trb.trb_2 = 0; 1457 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1458 XHCI_TRB_3_EP_SET(dci) | 1459 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1460 1461 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1462 1463 return err; 1464 } 1465 1466 /* 1467 * Set TR Dequeue Pointer. 1468 * xHCI 1.1 4.6.10 6.4.3.9 1469 * Purge all of the TRBs on ring and reinitialize ring. 1470 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1471 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1472 * error will be generated. 1473 */ 1474 static usbd_status 1475 xhci_set_dequeue_locked(struct usbd_pipe *pipe) 1476 { 1477 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1478 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1479 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1480 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1481 struct xhci_trb trb; 1482 usbd_status err; 1483 1484 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1485 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1486 1487 KASSERT(mutex_owned(&sc->sc_lock)); 1488 1489 xhci_host_dequeue(xr); 1490 1491 /* set DCS */ 1492 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1493 trb.trb_2 = 0; 1494 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1495 XHCI_TRB_3_EP_SET(dci) | 1496 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1497 1498 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1499 1500 return err; 1501 } 1502 1503 static usbd_status 1504 xhci_set_dequeue(struct usbd_pipe *pipe) 1505 { 1506 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1507 1508 mutex_enter(&sc->sc_lock); 1509 usbd_status ret = xhci_set_dequeue_locked(pipe); 1510 mutex_exit(&sc->sc_lock); 1511 1512 return ret; 1513 } 1514 1515 /* 1516 * Open new pipe: called from usbd_setup_pipe_flags. 1517 * Fills methods of pipe. 1518 * If pipe is not for ep0, calls configure_endpoint. 1519 */ 1520 static usbd_status 1521 xhci_open(struct usbd_pipe *pipe) 1522 { 1523 struct usbd_device * const dev = pipe->up_dev; 1524 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1525 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1526 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1527 1528 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1529 DPRINTFN(1, "addr %d depth %d port %d speed %d", dev->ud_addr, 1530 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1531 DPRINTFN(1, " dci %u type 0x%02x epaddr 0x%02x attr 0x%02x", 1532 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1533 ed->bmAttributes); 1534 DPRINTFN(1, " mps %u ival %u", UGETW(ed->wMaxPacketSize), ed->bInterval, 1535 0, 0); 1536 1537 if (sc->sc_dying) 1538 return USBD_IOERROR; 1539 1540 /* Root Hub */ 1541 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1542 switch (ed->bEndpointAddress) { 1543 case USB_CONTROL_ENDPOINT: 1544 pipe->up_methods = &roothub_ctrl_methods; 1545 break; 1546 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1547 pipe->up_methods = &xhci_root_intr_methods; 1548 break; 1549 default: 1550 pipe->up_methods = NULL; 1551 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1552 ed->bEndpointAddress, 0, 0, 0); 1553 return USBD_INVAL; 1554 } 1555 return USBD_NORMAL_COMPLETION; 1556 } 1557 1558 switch (xfertype) { 1559 case UE_CONTROL: 1560 pipe->up_methods = &xhci_device_ctrl_methods; 1561 break; 1562 case UE_ISOCHRONOUS: 1563 pipe->up_methods = &xhci_device_isoc_methods; 1564 return USBD_INVAL; 1565 break; 1566 case UE_BULK: 1567 pipe->up_methods = &xhci_device_bulk_methods; 1568 break; 1569 case UE_INTERRUPT: 1570 pipe->up_methods = &xhci_device_intr_methods; 1571 break; 1572 default: 1573 return USBD_IOERROR; 1574 break; 1575 } 1576 1577 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1578 return xhci_configure_endpoint(pipe); 1579 1580 return USBD_NORMAL_COMPLETION; 1581 } 1582 1583 /* 1584 * Closes pipe, called from usbd_kill_pipe via close methods. 1585 * If the endpoint to be closed is ep0, disable_slot. 1586 * Should be called with sc_lock held. 1587 */ 1588 static void 1589 xhci_close_pipe(struct usbd_pipe *pipe) 1590 { 1591 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1592 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1593 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1594 const u_int dci = xhci_ep_get_dci(ed); 1595 struct xhci_trb trb; 1596 uint32_t *cp; 1597 1598 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1599 1600 if (sc->sc_dying) 1601 return; 1602 1603 /* xs is uninitialized before xhci_init_slot */ 1604 if (xs == NULL || xs->xs_idx == 0) 1605 return; 1606 1607 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1608 1609 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1610 KASSERT(mutex_owned(&sc->sc_lock)); 1611 1612 if (pipe->up_dev->ud_depth == 0) 1613 return; 1614 1615 if (dci == XHCI_DCI_EP_CONTROL) { 1616 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1617 xhci_disable_slot(sc, xs->xs_idx); 1618 return; 1619 } 1620 1621 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED) 1622 (void)xhci_stop_endpoint(pipe); 1623 1624 /* 1625 * set appropriate bit to be dropped. 1626 * don't set DC bit to 1, otherwise all endpoints 1627 * would be deconfigured. 1628 */ 1629 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1630 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1631 cp[1] = htole32(0); 1632 1633 /* XXX should be most significant one, not dci? */ 1634 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1635 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1636 1637 /* configure ep context performs an implicit dequeue */ 1638 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 1639 1640 /* sync input contexts before they are read from memory */ 1641 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1642 1643 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1644 trb.trb_2 = 0; 1645 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1646 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1647 1648 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1649 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1650 } 1651 1652 /* 1653 * Abort transfer. 1654 * Should be called with sc_lock held. 1655 */ 1656 static void 1657 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1658 { 1659 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1660 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1661 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1662 1663 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1664 DPRINTFN(4, "xfer %p pipe %p status %d", 1665 xfer, xfer->ux_pipe, status, 0); 1666 1667 KASSERT(mutex_owned(&sc->sc_lock)); 1668 ASSERT_SLEEPABLE(); 1669 1670 if (sc->sc_dying) { 1671 /* If we're dying, just do the software part. */ 1672 DPRINTFN(4, "xfer %p dying %u", xfer, xfer->ux_status, 0, 0); 1673 xfer->ux_status = status; 1674 callout_halt(&xfer->ux_callout, &sc->sc_lock); 1675 usb_transfer_complete(xfer); 1676 return; 1677 } 1678 1679 /* 1680 * If an abort is already in progress then just wait for it to 1681 * complete and return. 1682 */ 1683 if (xfer->ux_hcflags & UXFER_ABORTING) { 1684 DPRINTFN(4, "already aborting", 0, 0, 0, 0); 1685 #ifdef DIAGNOSTIC 1686 if (status == USBD_TIMEOUT) 1687 DPRINTFN(4, "TIMEOUT while aborting", 0, 0, 0, 0); 1688 #endif 1689 /* Override the status which might be USBD_TIMEOUT. */ 1690 xfer->ux_status = status; 1691 DPRINTFN(4, "xfer %p waiting for abort to finish", xfer, 0, 0, 1692 0); 1693 xfer->ux_hcflags |= UXFER_ABORTWAIT; 1694 while (xfer->ux_hcflags & UXFER_ABORTING) 1695 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 1696 return; 1697 } 1698 xfer->ux_hcflags |= UXFER_ABORTING; 1699 1700 /* 1701 * Step 1: When cancelling a transfer make sure the timeout handler 1702 * didn't run or ran to the end and saw the USBD_CANCELLED status. 1703 * Otherwise we must have got here via a timeout. 1704 */ 1705 if (status == USBD_CANCELLED) { 1706 xfer->ux_status = status; 1707 callout_halt(&xfer->ux_callout, &sc->sc_lock); 1708 } else { 1709 KASSERT(xfer->ux_status == USBD_TIMEOUT); 1710 } 1711 1712 /* 1713 * Step 2: Stop execution of TD on the ring. 1714 */ 1715 switch (xhci_get_epstate(sc, xs, dci)) { 1716 case XHCI_EPSTATE_HALTED: 1717 (void)xhci_reset_endpoint_locked(xfer->ux_pipe); 1718 break; 1719 case XHCI_EPSTATE_STOPPED: 1720 break; 1721 default: 1722 (void)xhci_stop_endpoint(xfer->ux_pipe); 1723 break; 1724 } 1725 #ifdef DIAGNOSTIC 1726 uint32_t epst = xhci_get_epstate(sc, xs, dci); 1727 if (epst != XHCI_EPSTATE_STOPPED) 1728 DPRINTFN(4, "dci %u not stopped %u", dci, epst, 0, 0); 1729 #endif 1730 1731 /* 1732 * Step 3: Remove any vestiges of the xfer from the ring. 1733 */ 1734 xhci_set_dequeue_locked(xfer->ux_pipe); 1735 1736 /* 1737 * Step 4: Notify completion to waiting xfers. 1738 */ 1739 int wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 1740 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 1741 usb_transfer_complete(xfer); 1742 if (wake) { 1743 cv_broadcast(&xfer->ux_hccv); 1744 } 1745 DPRINTFN(14, "end", 0, 0, 0, 0); 1746 1747 KASSERT(mutex_owned(&sc->sc_lock)); 1748 } 1749 1750 static void 1751 xhci_host_dequeue(struct xhci_ring * const xr) 1752 { 1753 /* When dequeueing the controller, update our struct copy too */ 1754 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1755 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1756 BUS_DMASYNC_PREWRITE); 1757 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1758 1759 xr->xr_ep = 0; 1760 xr->xr_cs = 1; 1761 } 1762 1763 /* 1764 * Recover STALLed endpoint. 1765 * xHCI 1.1 sect 4.10.2.1 1766 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1767 * all transfers on transfer ring. 1768 * These are done in thread context asynchronously. 1769 */ 1770 static void 1771 xhci_clear_endpoint_stall_async_task(void *cookie) 1772 { 1773 struct usbd_xfer * const xfer = cookie; 1774 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1775 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1776 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1777 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1778 1779 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1780 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1781 1782 xhci_reset_endpoint(xfer->ux_pipe); 1783 xhci_set_dequeue(xfer->ux_pipe); 1784 1785 mutex_enter(&sc->sc_lock); 1786 tr->is_halted = false; 1787 usb_transfer_complete(xfer); 1788 mutex_exit(&sc->sc_lock); 1789 DPRINTFN(4, "ends", 0, 0, 0, 0); 1790 } 1791 1792 static usbd_status 1793 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1794 { 1795 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1796 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1797 1798 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1799 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1800 1801 if (sc->sc_dying) { 1802 return USBD_IOERROR; 1803 } 1804 1805 usb_init_task(&xp->xp_async_task, 1806 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1807 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1808 DPRINTFN(4, "ends", 0, 0, 0, 0); 1809 1810 return USBD_NORMAL_COMPLETION; 1811 } 1812 1813 /* Process roothub port status/change events and notify to uhub_intr. */ 1814 static void 1815 xhci_rhpsc(struct xhci_softc * const sc, u_int ctlrport) 1816 { 1817 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1818 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1819 ctlrport, 0, 0); 1820 1821 if (ctlrport > sc->sc_maxports) 1822 return; 1823 1824 const size_t bn = xhci_ctlrport2bus(sc, ctlrport); 1825 const size_t rhp = xhci_ctlrport2rhport(sc, ctlrport); 1826 struct usbd_xfer * const xfer = sc->sc_intrxfer[bn]; 1827 1828 DPRINTFN(4, "xhci%d: bus %d bp %u xfer %p status change", 1829 device_unit(sc->sc_dev), bn, rhp, xfer); 1830 1831 if (xfer == NULL) 1832 return; 1833 1834 uint8_t *p = xfer->ux_buf; 1835 memset(p, 0, xfer->ux_length); 1836 p[rhp / NBBY] |= 1 << (rhp % NBBY); 1837 xfer->ux_actlen = xfer->ux_length; 1838 xfer->ux_status = USBD_NORMAL_COMPLETION; 1839 usb_transfer_complete(xfer); 1840 } 1841 1842 /* Process Transfer Events */ 1843 static void 1844 xhci_event_transfer(struct xhci_softc * const sc, 1845 const struct xhci_trb * const trb) 1846 { 1847 uint64_t trb_0; 1848 uint32_t trb_2, trb_3; 1849 uint8_t trbcode; 1850 u_int slot, dci; 1851 struct xhci_slot *xs; 1852 struct xhci_ring *xr; 1853 struct xhci_xfer *xx; 1854 struct usbd_xfer *xfer; 1855 usbd_status err; 1856 1857 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1858 1859 trb_0 = le64toh(trb->trb_0); 1860 trb_2 = le32toh(trb->trb_2); 1861 trb_3 = le32toh(trb->trb_3); 1862 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1863 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1864 dci = XHCI_TRB_3_EP_GET(trb_3); 1865 xs = &sc->sc_slots[slot]; 1866 xr = &xs->xs_ep[dci].xe_tr; 1867 1868 /* sanity check */ 1869 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1870 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1871 1872 int idx = 0; 1873 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1874 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1875 DPRINTFN(0, "invalid trb_0 0x%"PRIx64, trb_0, 0, 0, 0); 1876 return; 1877 } 1878 xx = xr->xr_cookies[idx]; 1879 1880 /* clear cookie of consumed TRB */ 1881 xr->xr_cookies[idx] = NULL; 1882 1883 /* 1884 * xx is NULL if pipe is opened but xfer is not started. 1885 * It happens when stopping idle pipe. 1886 */ 1887 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1888 DPRINTFN(1, "Ignore #%u: cookie %p cc %u dci %u", 1889 idx, xx, trbcode, dci); 1890 DPRINTFN(1, " orig TRB %"PRIx64" type %u", trb_0, 1891 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1892 0, 0); 1893 return; 1894 } 1895 } else { 1896 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1897 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1898 } 1899 /* XXX this may not happen */ 1900 if (xx == NULL) { 1901 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1902 return; 1903 } 1904 xfer = &xx->xx_xfer; 1905 /* XXX this may happen when detaching */ 1906 if (xfer == NULL) { 1907 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1908 xx, trb_0, 0, 0); 1909 return; 1910 } 1911 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1912 /* XXX I dunno why this happens */ 1913 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1914 1915 if (!xfer->ux_pipe->up_repeat && 1916 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1917 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1918 return; 1919 } 1920 1921 /* 4.11.5.2 Event Data TRB */ 1922 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1923 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1924 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1925 if ((trb_0 & 0x3) == 0x3) { 1926 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1927 } 1928 } 1929 1930 switch (trbcode) { 1931 case XHCI_TRB_ERROR_SHORT_PKT: 1932 case XHCI_TRB_ERROR_SUCCESS: 1933 /* 1934 * A ctrl transfer can generate two events if it has a Data 1935 * stage. A short data stage can be OK and should not 1936 * complete the transfer as the status stage needs to be 1937 * performed. 1938 * 1939 * Note: Data and Status stage events point at same xfer. 1940 * ux_actlen and ux_dmabuf will be passed to 1941 * usb_transfer_complete after the Status stage event. 1942 * 1943 * It can be distingished which stage generates the event: 1944 * + by checking least 3 bits of trb_0 if ED==1. 1945 * (see xhci_device_ctrl_start). 1946 * + by checking the type of original TRB if ED==0. 1947 * 1948 * In addition, intr, bulk, and isoc transfer currently 1949 * consists of single TD, so the "skip" is not needed. 1950 * ctrl xfer uses EVENT_DATA, and others do not. 1951 * Thus driver can switch the flow by checking ED bit. 1952 */ 1953 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1954 if (xfer->ux_actlen == 0) 1955 xfer->ux_actlen = xfer->ux_length - 1956 XHCI_TRB_2_REM_GET(trb_2); 1957 if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)) 1958 == XHCI_TRB_TYPE_DATA_STAGE) { 1959 return; 1960 } 1961 } else if ((trb_0 & 0x3) == 0x3) { 1962 return; 1963 } 1964 err = USBD_NORMAL_COMPLETION; 1965 break; 1966 case XHCI_TRB_ERROR_STOPPED: 1967 case XHCI_TRB_ERROR_LENGTH: 1968 case XHCI_TRB_ERROR_STOPPED_SHORT: 1969 /* 1970 * don't complete the transfer being aborted 1971 * as abort_xfer does instead. 1972 */ 1973 if (xfer->ux_hcflags & UXFER_ABORTING) { 1974 DPRINTFN(14, "ignore aborting xfer %p", xfer, 0, 0, 0); 1975 return; 1976 } 1977 err = USBD_CANCELLED; 1978 break; 1979 case XHCI_TRB_ERROR_STALL: 1980 case XHCI_TRB_ERROR_BABBLE: 1981 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1982 xr->is_halted = true; 1983 err = USBD_STALLED; 1984 /* 1985 * Stalled endpoints can be recoverd by issuing 1986 * command TRB TYPE_RESET_EP on xHCI instead of 1987 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1988 * on the endpoint. However, this function may be 1989 * called from softint context (e.g. from umass), 1990 * in that case driver gets KASSERT in cv_timedwait 1991 * in xhci_do_command. 1992 * To avoid this, this runs reset_endpoint and 1993 * usb_transfer_complete in usb task thread 1994 * asynchronously (and then umass issues clear 1995 * UF_ENDPOINT_HALT). 1996 */ 1997 xfer->ux_status = err; 1998 callout_halt(&xfer->ux_callout, &sc->sc_lock); 1999 xhci_clear_endpoint_stall_async(xfer); 2000 return; 2001 default: 2002 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 2003 err = USBD_IOERROR; 2004 break; 2005 } 2006 xfer->ux_status = err; 2007 2008 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 2009 if ((trb_0 & 0x3) == 0x0) { 2010 callout_stop(&xfer->ux_callout); 2011 usb_transfer_complete(xfer); 2012 } 2013 } else { 2014 callout_stop(&xfer->ux_callout); 2015 usb_transfer_complete(xfer); 2016 } 2017 } 2018 2019 /* Process Command complete events */ 2020 static void 2021 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 2022 { 2023 uint64_t trb_0; 2024 uint32_t trb_2, trb_3; 2025 2026 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2027 2028 KASSERT(mutex_owned(&sc->sc_lock)); 2029 2030 trb_0 = le64toh(trb->trb_0); 2031 trb_2 = le32toh(trb->trb_2); 2032 trb_3 = le32toh(trb->trb_3); 2033 2034 if (trb_0 == sc->sc_command_addr) { 2035 sc->sc_resultpending = false; 2036 2037 sc->sc_result_trb.trb_0 = trb_0; 2038 sc->sc_result_trb.trb_2 = trb_2; 2039 sc->sc_result_trb.trb_3 = trb_3; 2040 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2041 XHCI_TRB_ERROR_SUCCESS) { 2042 DPRINTFN(1, "command completion " 2043 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 2044 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 2045 } 2046 cv_signal(&sc->sc_command_cv); 2047 } else { 2048 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 2049 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 2050 trb_2, trb_3); 2051 } 2052 } 2053 2054 /* 2055 * Process events. 2056 * called from xhci_softintr 2057 */ 2058 static void 2059 xhci_handle_event(struct xhci_softc * const sc, 2060 const struct xhci_trb * const trb) 2061 { 2062 uint64_t trb_0; 2063 uint32_t trb_2, trb_3; 2064 2065 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2066 2067 trb_0 = le64toh(trb->trb_0); 2068 trb_2 = le32toh(trb->trb_2); 2069 trb_3 = le32toh(trb->trb_3); 2070 2071 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2072 trb, trb_0, trb_2, trb_3); 2073 2074 /* 2075 * 4.11.3.1, 6.4.2.1 2076 * TRB Pointer is invalid for these completion codes. 2077 */ 2078 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2079 case XHCI_TRB_ERROR_RING_UNDERRUN: 2080 case XHCI_TRB_ERROR_RING_OVERRUN: 2081 case XHCI_TRB_ERROR_VF_RING_FULL: 2082 return; 2083 default: 2084 if (trb_0 == 0) { 2085 return; 2086 } 2087 break; 2088 } 2089 2090 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2091 case XHCI_TRB_EVENT_TRANSFER: 2092 xhci_event_transfer(sc, trb); 2093 break; 2094 case XHCI_TRB_EVENT_CMD_COMPLETE: 2095 xhci_event_cmd(sc, trb); 2096 break; 2097 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2098 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2099 break; 2100 default: 2101 break; 2102 } 2103 } 2104 2105 static void 2106 xhci_softintr(void *v) 2107 { 2108 struct usbd_bus * const bus = v; 2109 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2110 struct xhci_ring * const er = &sc->sc_er; 2111 struct xhci_trb *trb; 2112 int i, j, k; 2113 2114 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2115 2116 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2117 2118 i = er->xr_ep; 2119 j = er->xr_cs; 2120 2121 DPRINTFN(16, "er: xr_ep %d xr_cs %d", i, j, 0, 0); 2122 2123 while (1) { 2124 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2125 BUS_DMASYNC_POSTREAD); 2126 trb = &er->xr_trb[i]; 2127 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2128 2129 if (j != k) 2130 break; 2131 2132 xhci_handle_event(sc, trb); 2133 2134 i++; 2135 if (i == er->xr_ntrb) { 2136 i = 0; 2137 j ^= 1; 2138 } 2139 } 2140 2141 er->xr_ep = i; 2142 er->xr_cs = j; 2143 2144 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2145 XHCI_ERDP_LO_BUSY); 2146 2147 DPRINTFN(16, "ends", 0, 0, 0, 0); 2148 2149 return; 2150 } 2151 2152 static void 2153 xhci_poll(struct usbd_bus *bus) 2154 { 2155 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2156 2157 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2158 2159 mutex_spin_enter(&sc->sc_intr_lock); 2160 xhci_intr1(sc); 2161 mutex_spin_exit(&sc->sc_intr_lock); 2162 2163 return; 2164 } 2165 2166 static struct usbd_xfer * 2167 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2168 { 2169 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2170 struct usbd_xfer *xfer; 2171 2172 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2173 2174 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 2175 if (xfer != NULL) { 2176 memset(xfer, 0, sizeof(struct xhci_xfer)); 2177 #ifdef DIAGNOSTIC 2178 xfer->ux_state = XFER_BUSY; 2179 #endif 2180 } 2181 2182 return xfer; 2183 } 2184 2185 static void 2186 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2187 { 2188 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2189 2190 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2191 2192 #ifdef DIAGNOSTIC 2193 if (xfer->ux_state != XFER_BUSY) { 2194 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 2195 xfer, xfer->ux_state, 0, 0); 2196 } 2197 xfer->ux_state = XFER_FREE; 2198 #endif 2199 pool_cache_put(sc->sc_xferpool, xfer); 2200 } 2201 2202 static void 2203 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2204 { 2205 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2206 2207 *lock = &sc->sc_lock; 2208 } 2209 2210 extern uint32_t usb_cookie_no; 2211 2212 /* 2213 * xHCI 4.3 2214 * Called when uhub_explore finds a new device (via usbd_new_device). 2215 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2216 * This function does: 2217 * Allocate and construct dev structure of default endpoint (ep0). 2218 * Allocate and open pipe of ep0. 2219 * Enable slot and initialize slot context. 2220 * Set Address. 2221 * Read initial device descriptor. 2222 * Determine initial MaxPacketSize (mps) by speed. 2223 * Read full device descriptor. 2224 * Register this device. 2225 * Finally state of device transitions ADDRESSED. 2226 */ 2227 static usbd_status 2228 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2229 int speed, int port, struct usbd_port *up) 2230 { 2231 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2232 struct usbd_device *dev; 2233 usbd_status err; 2234 usb_device_descriptor_t *dd; 2235 struct xhci_slot *xs; 2236 uint32_t *cp; 2237 2238 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2239 DPRINTFN(4, "port %u depth %u speed %u up %p", port, depth, speed, up); 2240 2241 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2242 if (dev == NULL) 2243 return USBD_NOMEM; 2244 2245 dev->ud_bus = bus; 2246 dev->ud_quirks = &usbd_no_quirk; 2247 dev->ud_addr = 0; 2248 dev->ud_ddesc.bMaxPacketSize = 0; 2249 dev->ud_depth = depth; 2250 dev->ud_powersrc = up; 2251 dev->ud_myhub = up->up_parent; 2252 dev->ud_speed = speed; 2253 dev->ud_langid = USBD_NOLANG; 2254 dev->ud_cookie.cookie = ++usb_cookie_no; 2255 2256 /* Set up default endpoint handle. */ 2257 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2258 /* doesn't matter, just don't let it uninitialized */ 2259 dev->ud_ep0.ue_toggle = 0; 2260 2261 /* Set up default endpoint descriptor. */ 2262 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2263 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2264 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2265 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2266 dev->ud_ep0desc.bInterval = 0; 2267 2268 /* 4.3, 4.8.2.1 */ 2269 switch (speed) { 2270 case USB_SPEED_SUPER: 2271 case USB_SPEED_SUPER_PLUS: 2272 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2273 break; 2274 case USB_SPEED_FULL: 2275 /* XXX using 64 as initial mps of ep0 in FS */ 2276 case USB_SPEED_HIGH: 2277 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2278 break; 2279 case USB_SPEED_LOW: 2280 default: 2281 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2282 break; 2283 } 2284 2285 up->up_dev = dev; 2286 2287 /* Establish the default pipe. */ 2288 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2289 &dev->ud_pipe0); 2290 if (err) { 2291 goto bad; 2292 } 2293 2294 dd = &dev->ud_ddesc; 2295 2296 if (depth == 0 && port == 0) { 2297 KASSERT(bus->ub_devices[USB_ROOTHUB_INDEX] == NULL); 2298 bus->ub_devices[USB_ROOTHUB_INDEX] = dev; 2299 err = usbd_get_initial_ddesc(dev, dd); 2300 if (err) { 2301 DPRINTFN(1, "get_initial_ddesc %u", err, 0, 0, 0); 2302 goto bad; 2303 } 2304 2305 err = usbd_reload_device_desc(dev); 2306 if (err) { 2307 DPRINTFN(1, "reload desc %u", err, 0, 0, 0); 2308 goto bad; 2309 } 2310 } else { 2311 uint8_t slot = 0; 2312 2313 /* 4.3.2 */ 2314 err = xhci_enable_slot(sc, &slot); 2315 if (err) { 2316 DPRINTFN(1, "enable slot %u", err, 0, 0, 0); 2317 goto bad; 2318 } 2319 2320 xs = &sc->sc_slots[slot]; 2321 dev->ud_hcpriv = xs; 2322 2323 /* 4.3.3 initialize slot structure */ 2324 err = xhci_init_slot(dev, slot); 2325 if (err) { 2326 DPRINTFN(1, "init slot %u", err, 0, 0, 0); 2327 dev->ud_hcpriv = NULL; 2328 /* 2329 * We have to disable_slot here because 2330 * xs->xs_idx == 0 when xhci_init_slot fails, 2331 * in that case usbd_remove_dev won't work. 2332 */ 2333 mutex_enter(&sc->sc_lock); 2334 xhci_disable_slot(sc, slot); 2335 mutex_exit(&sc->sc_lock); 2336 goto bad; 2337 } 2338 2339 /* 4.3.4 Address Assignment */ 2340 err = xhci_set_address(dev, slot, false); 2341 if (err) { 2342 DPRINTFN(1, "set address w/o bsr %u", err, 0, 0, 0); 2343 goto bad; 2344 } 2345 2346 /* Allow device time to set new address */ 2347 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2348 2349 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2350 //hexdump("slot context", cp, sc->sc_ctxsz); 2351 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3])); 2352 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2353 /* 2354 * XXX ensure we know when the hardware does something 2355 * we can't yet cope with 2356 */ 2357 KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr); 2358 dev->ud_addr = addr; 2359 2360 KASSERTMSG(bus->ub_devices[usb_addr2dindex(dev->ud_addr)] == NULL, 2361 "addr %d already allocated", dev->ud_addr); 2362 /* 2363 * The root hub is given its own slot 2364 */ 2365 bus->ub_devices[usb_addr2dindex(dev->ud_addr)] = dev; 2366 2367 err = usbd_get_initial_ddesc(dev, dd); 2368 if (err) { 2369 DPRINTFN(1, "get_initial_ddesc %u", err, 0, 0, 0); 2370 goto bad; 2371 } 2372 2373 /* 4.8.2.1 */ 2374 if (USB_IS_SS(speed)) { 2375 if (dd->bMaxPacketSize != 9) { 2376 printf("%s: invalid mps 2^%u for SS ep0," 2377 " using 512\n", 2378 device_xname(sc->sc_dev), 2379 dd->bMaxPacketSize); 2380 dd->bMaxPacketSize = 9; 2381 } 2382 USETW(dev->ud_ep0desc.wMaxPacketSize, 2383 (1 << dd->bMaxPacketSize)); 2384 } else 2385 USETW(dev->ud_ep0desc.wMaxPacketSize, 2386 dd->bMaxPacketSize); 2387 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2388 err = xhci_update_ep0_mps(sc, xs, 2389 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2390 if (err) { 2391 DPRINTFN(1, "update mps of ep0 %u", err, 0, 0, 0); 2392 goto bad; 2393 } 2394 2395 err = usbd_reload_device_desc(dev); 2396 if (err) { 2397 DPRINTFN(1, "reload desc %u", err, 0, 0, 0); 2398 goto bad; 2399 } 2400 } 2401 2402 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2403 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2404 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2405 dd->bDeviceClass, dd->bDeviceSubClass, 2406 dd->bDeviceProtocol, 0); 2407 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2408 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2409 dev->ud_speed); 2410 2411 usbd_get_device_strings(dev); 2412 2413 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2414 2415 if (depth == 0 && port == 0) { 2416 usbd_attach_roothub(parent, dev); 2417 DPRINTFN(1, "root hub %p", dev, 0, 0, 0); 2418 return USBD_NORMAL_COMPLETION; 2419 } 2420 2421 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2422 bad: 2423 if (err != USBD_NORMAL_COMPLETION) { 2424 usbd_remove_device(dev, up); 2425 } 2426 2427 return err; 2428 } 2429 2430 static usbd_status 2431 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2432 size_t ntrb, size_t align) 2433 { 2434 usbd_status err; 2435 size_t size = ntrb * XHCI_TRB_SIZE; 2436 2437 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2438 2439 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2440 if (err) 2441 return err; 2442 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2443 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2444 xr->xr_trb = xhci_ring_trbv(xr, 0); 2445 xr->xr_ntrb = ntrb; 2446 xr->is_halted = false; 2447 xhci_host_dequeue(xr); 2448 2449 return USBD_NORMAL_COMPLETION; 2450 } 2451 2452 static void 2453 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2454 { 2455 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2456 mutex_destroy(&xr->xr_lock); 2457 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2458 } 2459 2460 static void 2461 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2462 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2463 { 2464 size_t i; 2465 u_int ri; 2466 u_int cs; 2467 uint64_t parameter; 2468 uint32_t status; 2469 uint32_t control; 2470 2471 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2472 2473 KASSERTMSG(ntrbs <= XHCI_XFER_NTRB, "ntrbs %zu", ntrbs); 2474 for (i = 0; i < ntrbs; i++) { 2475 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2476 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2477 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2478 KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2479 XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3); 2480 } 2481 2482 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2483 2484 ri = xr->xr_ep; 2485 cs = xr->xr_cs; 2486 2487 /* 2488 * Although the xhci hardware can do scatter/gather dma from 2489 * arbitrary sized buffers, there is a non-obvious restriction 2490 * that a LINK trb is only allowed at the end of a burst of 2491 * transfers - which might be 16kB. 2492 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2493 * The simple solution is not to allow a LINK trb in the middle 2494 * of anything - as here. 2495 * XXX: (dsl) There are xhci controllers out there (eg some made by 2496 * ASMedia) that seem to lock up if they process a LINK trb but 2497 * cannot process the linked-to trb yet. 2498 * The code should write the 'cycle' bit on the link trb AFTER 2499 * adding the other trb. 2500 */ 2501 u_int firstep = xr->xr_ep; 2502 u_int firstcs = xr->xr_cs; 2503 2504 for (i = 0; i < ntrbs; ) { 2505 u_int oldri = ri; 2506 u_int oldcs = cs; 2507 2508 if (ri >= (xr->xr_ntrb - 1)) { 2509 /* Put Link TD at the end of ring */ 2510 parameter = xhci_ring_trbp(xr, 0); 2511 status = 0; 2512 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2513 XHCI_TRB_3_TC_BIT; 2514 xr->xr_cookies[ri] = NULL; 2515 xr->xr_ep = 0; 2516 xr->xr_cs ^= 1; 2517 ri = xr->xr_ep; 2518 cs = xr->xr_cs; 2519 } else { 2520 parameter = trbs[i].trb_0; 2521 status = trbs[i].trb_2; 2522 control = trbs[i].trb_3; 2523 2524 xr->xr_cookies[ri] = cookie; 2525 ri++; 2526 i++; 2527 } 2528 /* 2529 * If this is a first TRB, mark it invalid to prevent 2530 * xHC from running it immediately. 2531 */ 2532 if (oldri == firstep) { 2533 if (oldcs) { 2534 control &= ~XHCI_TRB_3_CYCLE_BIT; 2535 } else { 2536 control |= XHCI_TRB_3_CYCLE_BIT; 2537 } 2538 } else { 2539 if (oldcs) { 2540 control |= XHCI_TRB_3_CYCLE_BIT; 2541 } else { 2542 control &= ~XHCI_TRB_3_CYCLE_BIT; 2543 } 2544 } 2545 xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control); 2546 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri, 2547 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2548 } 2549 2550 /* Now invert cycle bit of first TRB */ 2551 if (firstcs) { 2552 xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 2553 } else { 2554 xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 2555 } 2556 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep, 2557 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2558 2559 xr->xr_ep = ri; 2560 xr->xr_cs = cs; 2561 2562 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2563 } 2564 2565 /* 2566 * Stop execution commands, purge all commands on command ring, and 2567 * rewind dequeue pointer. 2568 */ 2569 static void 2570 xhci_abort_command(struct xhci_softc *sc) 2571 { 2572 struct xhci_ring * const cr = &sc->sc_cr; 2573 uint64_t crcr; 2574 int i; 2575 2576 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2577 DPRINTFN(14, "command %#"PRIx64" timeout, aborting", 2578 sc->sc_command_addr, 0, 0, 0); 2579 2580 mutex_enter(&cr->xr_lock); 2581 2582 /* 4.6.1.2 Aborting a Command */ 2583 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2584 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2585 2586 for (i = 0; i < 500; i++) { 2587 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2588 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2589 break; 2590 usb_delay_ms(&sc->sc_bus, 1); 2591 } 2592 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2593 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2594 /* reset HC here? */ 2595 } 2596 2597 /* reset command ring dequeue pointer */ 2598 cr->xr_ep = 0; 2599 cr->xr_cs = 1; 2600 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2601 2602 mutex_exit(&cr->xr_lock); 2603 } 2604 2605 /* 2606 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2607 * Command completion is notified by cv_signal from xhci_event_cmd() 2608 * (called from xhci_softint), or timed-out. 2609 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2610 * then do_command examines it. 2611 */ 2612 static usbd_status 2613 xhci_do_command_locked(struct xhci_softc * const sc, 2614 struct xhci_trb * const trb, int timeout) 2615 { 2616 struct xhci_ring * const cr = &sc->sc_cr; 2617 usbd_status err; 2618 2619 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2620 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2621 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2622 2623 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2624 KASSERT(mutex_owned(&sc->sc_lock)); 2625 2626 while (sc->sc_command_addr != 0) 2627 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 2628 2629 /* 2630 * If enqueue pointer points at last of ring, it's Link TRB, 2631 * command TRB will be stored in 0th TRB. 2632 */ 2633 if (cr->xr_ep == cr->xr_ntrb - 1) 2634 sc->sc_command_addr = xhci_ring_trbp(cr, 0); 2635 else 2636 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2637 2638 sc->sc_resultpending = true; 2639 2640 mutex_enter(&cr->xr_lock); 2641 xhci_ring_put(sc, cr, NULL, trb, 1); 2642 mutex_exit(&cr->xr_lock); 2643 2644 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2645 2646 while (sc->sc_resultpending) { 2647 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2648 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2649 xhci_abort_command(sc); 2650 err = USBD_TIMEOUT; 2651 goto timedout; 2652 } 2653 } 2654 2655 trb->trb_0 = sc->sc_result_trb.trb_0; 2656 trb->trb_2 = sc->sc_result_trb.trb_2; 2657 trb->trb_3 = sc->sc_result_trb.trb_3; 2658 2659 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2660 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2661 2662 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2663 case XHCI_TRB_ERROR_SUCCESS: 2664 err = USBD_NORMAL_COMPLETION; 2665 break; 2666 default: 2667 case 192 ... 223: 2668 err = USBD_IOERROR; 2669 break; 2670 case 224 ... 255: 2671 err = USBD_NORMAL_COMPLETION; 2672 break; 2673 } 2674 2675 timedout: 2676 sc->sc_resultpending = false; 2677 sc->sc_command_addr = 0; 2678 cv_broadcast(&sc->sc_cmdbusy_cv); 2679 2680 return err; 2681 } 2682 2683 static usbd_status 2684 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2685 int timeout) 2686 { 2687 2688 mutex_enter(&sc->sc_lock); 2689 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2690 mutex_exit(&sc->sc_lock); 2691 2692 return ret; 2693 } 2694 2695 static usbd_status 2696 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2697 { 2698 struct xhci_trb trb; 2699 usbd_status err; 2700 2701 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2702 2703 trb.trb_0 = 0; 2704 trb.trb_2 = 0; 2705 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2706 2707 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2708 if (err != USBD_NORMAL_COMPLETION) { 2709 return err; 2710 } 2711 2712 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2713 2714 return err; 2715 } 2716 2717 /* 2718 * xHCI 4.6.4 2719 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2720 * All endpoints in the slot should be stopped. 2721 * Should be called with sc_lock held. 2722 */ 2723 static usbd_status 2724 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2725 { 2726 struct xhci_trb trb; 2727 struct xhci_slot *xs; 2728 usbd_status err; 2729 2730 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2731 2732 if (sc->sc_dying) 2733 return USBD_IOERROR; 2734 2735 trb.trb_0 = 0; 2736 trb.trb_2 = 0; 2737 trb.trb_3 = htole32( 2738 XHCI_TRB_3_SLOT_SET(slot) | 2739 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2740 2741 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2742 2743 if (!err) { 2744 xs = &sc->sc_slots[slot]; 2745 if (xs->xs_idx != 0) { 2746 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2747 xhci_set_dcba(sc, 0, slot); 2748 memset(xs, 0, sizeof(*xs)); 2749 } 2750 } 2751 2752 return err; 2753 } 2754 2755 /* 2756 * Set address of device and transition slot state from ENABLED to ADDRESSED 2757 * if Block Setaddress Request (BSR) is false. 2758 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2759 * see xHCI 1.1 4.5.3, 3.3.4 2760 * Should be called without sc_lock held. 2761 */ 2762 static usbd_status 2763 xhci_address_device(struct xhci_softc * const sc, 2764 uint64_t icp, uint8_t slot_id, bool bsr) 2765 { 2766 struct xhci_trb trb; 2767 usbd_status err; 2768 2769 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2770 2771 trb.trb_0 = icp; 2772 trb.trb_2 = 0; 2773 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2774 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2775 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2776 2777 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2778 2779 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2780 err = USBD_NO_ADDR; 2781 2782 return err; 2783 } 2784 2785 static usbd_status 2786 xhci_update_ep0_mps(struct xhci_softc * const sc, 2787 struct xhci_slot * const xs, u_int mps) 2788 { 2789 struct xhci_trb trb; 2790 usbd_status err; 2791 uint32_t * cp; 2792 2793 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2794 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2795 2796 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2797 cp[0] = htole32(0); 2798 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2799 2800 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2801 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2802 2803 /* sync input contexts before they are read from memory */ 2804 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2805 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2806 sc->sc_ctxsz * 4); 2807 2808 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2809 trb.trb_2 = 0; 2810 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2811 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2812 2813 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2814 return err; 2815 } 2816 2817 static void 2818 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2819 { 2820 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2821 2822 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2823 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2824 &dcbaa[si], dcba, si, 0); 2825 2826 dcbaa[si] = htole64(dcba); 2827 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2828 BUS_DMASYNC_PREWRITE); 2829 } 2830 2831 /* 2832 * Allocate device and input context DMA buffer, and 2833 * TRB DMA buffer for each endpoint. 2834 */ 2835 static usbd_status 2836 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2837 { 2838 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2839 struct xhci_slot *xs; 2840 usbd_status err; 2841 u_int dci; 2842 2843 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2844 DPRINTFN(4, "slot %u", slot, 0, 0, 0); 2845 2846 xs = &sc->sc_slots[slot]; 2847 2848 /* allocate contexts */ 2849 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2850 &xs->xs_dc_dma); 2851 if (err) 2852 return err; 2853 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2854 2855 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2856 &xs->xs_ic_dma); 2857 if (err) 2858 goto bad1; 2859 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2860 2861 for (dci = 0; dci < 32; dci++) { 2862 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2863 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2864 if (dci == XHCI_DCI_SLOT) 2865 continue; 2866 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2867 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2868 if (err) { 2869 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2870 goto bad2; 2871 } 2872 } 2873 2874 bad2: 2875 if (err == USBD_NORMAL_COMPLETION) { 2876 xs->xs_idx = slot; 2877 } else { 2878 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2879 } 2880 2881 return err; 2882 2883 bad1: 2884 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2885 xs->xs_idx = 0; 2886 return err; 2887 } 2888 2889 static void 2890 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2891 int end_dci) 2892 { 2893 u_int dci; 2894 2895 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2896 DPRINTFN(4, "slot %u start %u end %u", xs->xs_idx, start_dci, end_dci, 2897 0); 2898 2899 for (dci = start_dci; dci < end_dci; dci++) { 2900 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2901 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2902 } 2903 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2904 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2905 xs->xs_idx = 0; 2906 } 2907 2908 /* 2909 * Setup slot context, set Device Context Base Address, and issue 2910 * Set Address Device command. 2911 */ 2912 static usbd_status 2913 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 2914 { 2915 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2916 struct xhci_slot *xs; 2917 usbd_status err; 2918 2919 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2920 DPRINTFN(4, "slot %u bsr %u", slot, bsr, 0, 0); 2921 2922 xs = &sc->sc_slots[slot]; 2923 2924 xhci_setup_ctx(dev->ud_pipe0); 2925 2926 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2927 sc->sc_ctxsz * 3); 2928 2929 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2930 2931 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 2932 2933 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2934 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2935 sc->sc_ctxsz * 2); 2936 2937 return err; 2938 } 2939 2940 /* 2941 * 4.8.2, 6.2.3.2 2942 * construct slot/endpoint context parameters and do syncmem 2943 */ 2944 static void 2945 xhci_setup_ctx(struct usbd_pipe *pipe) 2946 { 2947 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2948 struct usbd_device *dev = pipe->up_dev; 2949 struct xhci_slot * const xs = dev->ud_hcpriv; 2950 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2951 const u_int dci = xhci_ep_get_dci(ed); 2952 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2953 uint32_t *cp; 2954 uint16_t mps = UGETW(ed->wMaxPacketSize); 2955 uint8_t speed = dev->ud_speed; 2956 uint8_t ival = ed->bInterval; 2957 2958 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2959 DPRINTFN(4, "pipe %p: slot %u dci %u speed %u", pipe, xs->xs_idx, dci, 2960 speed); 2961 2962 /* set up initial input control context */ 2963 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2964 cp[0] = htole32(0); 2965 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 2966 if (dci == XHCI_DCI_EP_CONTROL) 2967 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2968 cp[7] = htole32(0); 2969 2970 /* set up input slot context */ 2971 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2972 cp[0] = 2973 XHCI_SCTX_0_CTX_NUM_SET(dci) | 2974 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 2975 cp[1] = 0; 2976 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2977 cp[3] = 0; 2978 xhci_setup_route(pipe, cp); 2979 xhci_setup_tthub(pipe, cp); 2980 2981 cp[0] = htole32(cp[0]); 2982 cp[1] = htole32(cp[1]); 2983 cp[2] = htole32(cp[2]); 2984 cp[3] = htole32(cp[3]); 2985 2986 /* set up input endpoint context */ 2987 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 2988 cp[0] = 2989 XHCI_EPCTX_0_EPSTATE_SET(0) | 2990 XHCI_EPCTX_0_MULT_SET(0) | 2991 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2992 XHCI_EPCTX_0_LSA_SET(0) | 2993 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 2994 cp[1] = 2995 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 2996 XHCI_EPCTX_1_HID_SET(0) | 2997 XHCI_EPCTX_1_MAXB_SET(0); 2998 2999 if (xfertype != UE_ISOCHRONOUS) 3000 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 3001 3002 if (xfertype == UE_CONTROL) 3003 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 3004 else if (USB_IS_SS(speed)) 3005 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 3006 else 3007 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 3008 3009 xhci_setup_maxburst(pipe, cp); 3010 3011 switch (xfertype) { 3012 case UE_CONTROL: 3013 break; 3014 case UE_BULK: 3015 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 3016 break; 3017 case UE_INTERRUPT: 3018 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3019 ival = pipe->up_interval; 3020 3021 ival = xhci_bival2ival(ival, speed); 3022 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3023 break; 3024 case UE_ISOCHRONOUS: 3025 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3026 ival = pipe->up_interval; 3027 3028 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 3029 if (speed == USB_SPEED_FULL) 3030 ival += 3; /* 1ms -> 125us */ 3031 ival--; 3032 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3033 break; 3034 default: 3035 break; 3036 } 3037 DPRINTFN(4, "setting ival %u MaxBurst %#x", 3038 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 3039 3040 /* rewind TR dequeue pointer in xHC */ 3041 /* can't use xhci_ep_get_dci() yet? */ 3042 *(uint64_t *)(&cp[2]) = htole64( 3043 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 3044 XHCI_EPCTX_2_DCS_SET(1)); 3045 3046 cp[0] = htole32(cp[0]); 3047 cp[1] = htole32(cp[1]); 3048 cp[4] = htole32(cp[4]); 3049 3050 /* rewind TR dequeue pointer in driver */ 3051 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 3052 mutex_enter(&xr->xr_lock); 3053 xhci_host_dequeue(xr); 3054 mutex_exit(&xr->xr_lock); 3055 3056 /* sync input contexts before they are read from memory */ 3057 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3058 } 3059 3060 /* 3061 * Setup route string and roothub port of given device for slot context 3062 */ 3063 static void 3064 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 3065 { 3066 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3067 struct usbd_device *dev = pipe->up_dev; 3068 struct usbd_port *up = dev->ud_powersrc; 3069 struct usbd_device *hub; 3070 struct usbd_device *adev; 3071 uint8_t rhport = 0; 3072 uint32_t route = 0; 3073 3074 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3075 3076 /* Locate root hub port and Determine route string */ 3077 /* 4.3.3 route string does not include roothub port */ 3078 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 3079 uint32_t dep; 3080 3081 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 3082 hub, hub->ud_depth, hub->ud_powersrc, 3083 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 3084 3085 if (hub->ud_powersrc == NULL) 3086 break; 3087 dep = hub->ud_depth; 3088 if (dep == 0) 3089 break; 3090 rhport = hub->ud_powersrc->up_portno; 3091 if (dep > USB_HUB_MAX_DEPTH) 3092 continue; 3093 3094 route |= 3095 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 3096 << ((dep - 1) * 4); 3097 } 3098 route = route >> 4; 3099 size_t bn = hub == sc->sc_bus.ub_roothub ? 0 : 1; 3100 3101 /* Locate port on upstream high speed hub */ 3102 for (adev = dev, hub = up->up_parent; 3103 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 3104 adev = hub, hub = hub->ud_myhub) 3105 ; 3106 if (hub) { 3107 int p; 3108 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 3109 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 3110 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 3111 goto found; 3112 } 3113 } 3114 panic("%s: cannot find HS port", __func__); 3115 found: 3116 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 3117 } else { 3118 dev->ud_myhsport = NULL; 3119 } 3120 3121 const size_t ctlrport = xhci_rhport2ctlrport(sc, bn, rhport); 3122 3123 DPRINTFN(4, "rhport %u ctlrport %u Route %05x hub %p", rhport, 3124 ctlrport, route, hub); 3125 3126 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 3127 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(ctlrport); 3128 } 3129 3130 /* 3131 * Setup whether device is hub, whether device uses MTT, and 3132 * TT informations if it uses MTT. 3133 */ 3134 static void 3135 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 3136 { 3137 struct usbd_device *dev = pipe->up_dev; 3138 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 3139 uint32_t speed = dev->ud_speed; 3140 uint8_t tthubslot, ttportnum; 3141 bool ishub; 3142 bool usemtt; 3143 3144 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3145 3146 /* 3147 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 3148 * tthubslot: 3149 * This is the slot ID of parent HS hub 3150 * if LS/FS device is connected && connected through HS hub. 3151 * This is 0 if device is not LS/FS device || 3152 * parent hub is not HS hub || 3153 * attached to root hub. 3154 * ttportnum: 3155 * This is the downstream facing port of parent HS hub 3156 * if LS/FS device is connected. 3157 * This is 0 if device is not LS/FS device || 3158 * parent hub is not HS hub || 3159 * attached to root hub. 3160 */ 3161 if (dev->ud_myhsport != NULL && 3162 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3163 (dev->ud_myhub != NULL && 3164 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3165 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 3166 ttportnum = dev->ud_myhsport->up_portno; 3167 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 3168 } else { 3169 ttportnum = 0; 3170 tthubslot = 0; 3171 } 3172 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 3173 dev->ud_myhsport, ttportnum, tthubslot, 0); 3174 3175 /* ishub is valid after reading UDESC_DEVICE */ 3176 ishub = (dd->bDeviceClass == UDCLASS_HUB); 3177 3178 /* dev->ud_hub is valid after reading UDESC_HUB */ 3179 if (ishub && dev->ud_hub) { 3180 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 3181 uint8_t ttt = 3182 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 3183 3184 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 3185 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 3186 DPRINTFN(4, "nports=%d ttt=%d", hd->bNbrPorts, ttt, 0, 0); 3187 } 3188 3189 #define IS_TTHUB(dd) \ 3190 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 3191 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 3192 3193 /* 3194 * MTT flag is set if 3195 * 1. this is HS hub && MTT is enabled 3196 * or 3197 * 2. this is not hub && this is LS or FS device && 3198 * MTT of parent HS hub (and its parent, too) is enabled 3199 */ 3200 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 3201 usemtt = true; 3202 else if (!ishub && 3203 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 3204 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3205 (dev->ud_myhub != NULL && 3206 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3207 dev->ud_myhsport != NULL && 3208 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 3209 usemtt = true; 3210 else 3211 usemtt = false; 3212 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 3213 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 3214 3215 #undef IS_TTHUB 3216 3217 cp[0] |= 3218 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 3219 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 3220 cp[2] |= 3221 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 3222 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 3223 } 3224 3225 /* set up params for periodic endpoint */ 3226 static void 3227 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 3228 { 3229 struct usbd_device *dev = pipe->up_dev; 3230 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3231 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3232 usbd_desc_iter_t iter; 3233 const usb_cdc_descriptor_t *cdcd; 3234 uint32_t maxb = 0; 3235 uint16_t mps = UGETW(ed->wMaxPacketSize); 3236 uint8_t speed = dev->ud_speed; 3237 uint8_t ep; 3238 3239 /* config desc is NULL when opening ep0 */ 3240 if (dev == NULL || dev->ud_cdesc == NULL) 3241 goto no_cdcd; 3242 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 3243 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 3244 if (cdcd == NULL) 3245 goto no_cdcd; 3246 usb_desc_iter_init(dev, &iter); 3247 iter.cur = (const void *)cdcd; 3248 3249 /* find endpoint_ss_comp desc for ep of this pipe */ 3250 for (ep = 0;;) { 3251 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 3252 if (cdcd == NULL) 3253 break; 3254 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 3255 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 3256 bEndpointAddress; 3257 if (UE_GET_ADDR(ep) == 3258 UE_GET_ADDR(ed->bEndpointAddress)) { 3259 cdcd = (const usb_cdc_descriptor_t *) 3260 usb_desc_iter_next(&iter); 3261 break; 3262 } 3263 ep = 0; 3264 } 3265 } 3266 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 3267 const usb_endpoint_ss_comp_descriptor_t * esscd = 3268 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3269 maxb = esscd->bMaxBurst; 3270 } 3271 3272 no_cdcd: 3273 /* 6.2.3.4, 4.8.2.4 */ 3274 if (USB_IS_SS(speed)) { 3275 /* USB 3.1 9.6.6 */ 3276 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3277 /* USB 3.1 9.6.7 */ 3278 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3279 #ifdef notyet 3280 if (xfertype == UE_ISOCHRONOUS) { 3281 } 3282 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3283 /* use ESIT */ 3284 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3285 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3286 3287 /* XXX if LEC = 1, set ESIT instead */ 3288 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3289 } else { 3290 /* use ival */ 3291 } 3292 #endif 3293 } else { 3294 /* USB 2.0 9.6.6 */ 3295 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3296 3297 /* 6.2.3.4 */ 3298 if (speed == USB_SPEED_HIGH && 3299 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3300 maxb = UE_GET_TRANS(mps); 3301 } else { 3302 /* LS/FS or HS CTRL or HS BULK */ 3303 maxb = 0; 3304 } 3305 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3306 } 3307 } 3308 3309 /* 3310 * Convert endpoint bInterval value to endpoint context interval value 3311 * for Interrupt pipe. 3312 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3313 */ 3314 static uint32_t 3315 xhci_bival2ival(uint32_t ival, uint32_t speed) 3316 { 3317 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3318 int i; 3319 3320 /* 3321 * round ival down to "the nearest base 2 multiple of 3322 * bInterval * 8". 3323 * bInterval is at most 255 as its type is uByte. 3324 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3325 */ 3326 for (i = 10; i > 0; i--) { 3327 if ((ival * 8) >= (1 << i)) 3328 break; 3329 } 3330 ival = i; 3331 } else { 3332 /* Interval = bInterval-1 for SS/HS */ 3333 ival--; 3334 } 3335 3336 return ival; 3337 } 3338 3339 /* ----- */ 3340 3341 static void 3342 xhci_noop(struct usbd_pipe *pipe) 3343 { 3344 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3345 } 3346 3347 /* 3348 * Process root hub request. 3349 */ 3350 static int 3351 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3352 void *buf, int buflen) 3353 { 3354 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3355 usb_port_status_t ps; 3356 int l, totlen = 0; 3357 uint16_t len, value, index; 3358 int port, i; 3359 uint32_t v; 3360 3361 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3362 3363 if (sc->sc_dying) 3364 return -1; 3365 3366 size_t bn = bus == &sc->sc_bus ? 0 : 1; 3367 3368 len = UGETW(req->wLength); 3369 value = UGETW(req->wValue); 3370 index = UGETW(req->wIndex); 3371 3372 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 3373 req->bmRequestType | (req->bRequest << 8), value, index, len); 3374 3375 #define C(x,y) ((x) | ((y) << 8)) 3376 switch (C(req->bRequest, req->bmRequestType)) { 3377 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3378 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 3379 if (len == 0) 3380 break; 3381 switch (value) { 3382 case C(0, UDESC_DEVICE): { 3383 usb_device_descriptor_t devd; 3384 totlen = min(buflen, sizeof(devd)); 3385 memcpy(&devd, buf, totlen); 3386 USETW(devd.idVendor, sc->sc_id_vendor); 3387 memcpy(buf, &devd, totlen); 3388 break; 3389 } 3390 #define sd ((usb_string_descriptor_t *)buf) 3391 case C(1, UDESC_STRING): 3392 /* Vendor */ 3393 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3394 break; 3395 case C(2, UDESC_STRING): 3396 /* Product */ 3397 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3398 break; 3399 #undef sd 3400 default: 3401 /* default from usbroothub */ 3402 return buflen; 3403 } 3404 break; 3405 3406 /* Hub requests */ 3407 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3408 break; 3409 /* Clear Port Feature request */ 3410 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): { 3411 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3412 3413 DPRINTFN(4, "UR_CLEAR_PORT_FEAT bp=%d feat=%d bus=%d cp=%d", 3414 index, value, bn, cp); 3415 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3416 return -1; 3417 } 3418 port = XHCI_PORTSC(cp); 3419 v = xhci_op_read_4(sc, port); 3420 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3421 v &= ~XHCI_PS_CLEAR; 3422 switch (value) { 3423 case UHF_PORT_ENABLE: 3424 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3425 break; 3426 case UHF_PORT_SUSPEND: 3427 return -1; 3428 case UHF_PORT_POWER: 3429 break; 3430 case UHF_PORT_TEST: 3431 case UHF_PORT_INDICATOR: 3432 return -1; 3433 case UHF_C_PORT_CONNECTION: 3434 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3435 break; 3436 case UHF_C_PORT_ENABLE: 3437 case UHF_C_PORT_SUSPEND: 3438 case UHF_C_PORT_OVER_CURRENT: 3439 return -1; 3440 case UHF_C_BH_PORT_RESET: 3441 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3442 break; 3443 case UHF_C_PORT_RESET: 3444 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3445 break; 3446 case UHF_C_PORT_LINK_STATE: 3447 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3448 break; 3449 case UHF_C_PORT_CONFIG_ERROR: 3450 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3451 break; 3452 default: 3453 return -1; 3454 } 3455 break; 3456 } 3457 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3458 if (len == 0) 3459 break; 3460 if ((value & 0xff) != 0) { 3461 return -1; 3462 } 3463 usb_hub_descriptor_t hubd; 3464 3465 totlen = min(buflen, sizeof(hubd)); 3466 memcpy(&hubd, buf, totlen); 3467 hubd.bNbrPorts = sc->sc_rhportcount[bn]; 3468 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3469 hubd.bPwrOn2PwrGood = 200; 3470 for (i = 0, l = sc->sc_rhportcount[bn]; l > 0; i++, l -= 8) { 3471 /* XXX can't find out? */ 3472 hubd.DeviceRemovable[i++] = 0; 3473 } 3474 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3475 totlen = min(totlen, hubd.bDescLength); 3476 memcpy(buf, &hubd, totlen); 3477 break; 3478 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3479 if (len != 4) { 3480 return -1; 3481 } 3482 memset(buf, 0, len); /* ? XXX */ 3483 totlen = len; 3484 break; 3485 /* Get Port Status request */ 3486 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): { 3487 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3488 3489 DPRINTFN(8, "get port status bn=%d i=%d cp=%zu", bn, index, cp, 3490 0); 3491 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3492 return -1; 3493 } 3494 if (len != 4) { 3495 return -1; 3496 } 3497 v = xhci_op_read_4(sc, XHCI_PORTSC(cp)); 3498 DPRINTFN(4, "getrhportsc %d %08x", cp, v, 0, 0); 3499 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3500 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3501 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3502 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3503 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3504 if (v & XHCI_PS_PR) i |= UPS_RESET; 3505 if (v & XHCI_PS_PP) { 3506 if (i & UPS_OTHER_SPEED) 3507 i |= UPS_PORT_POWER_SS; 3508 else 3509 i |= UPS_PORT_POWER; 3510 } 3511 if (i & UPS_OTHER_SPEED) 3512 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3513 if (sc->sc_vendor_port_status) 3514 i = sc->sc_vendor_port_status(sc, v, i); 3515 USETW(ps.wPortStatus, i); 3516 i = 0; 3517 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3518 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3519 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3520 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3521 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3522 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3523 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3524 USETW(ps.wPortChange, i); 3525 totlen = min(len, sizeof(ps)); 3526 memcpy(buf, &ps, totlen); 3527 break; 3528 } 3529 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3530 return -1; 3531 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3532 break; 3533 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3534 break; 3535 /* Set Port Feature request */ 3536 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3537 int optval = (index >> 8) & 0xff; 3538 index &= 0xff; 3539 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3540 return -1; 3541 } 3542 3543 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3544 3545 port = XHCI_PORTSC(cp); 3546 v = xhci_op_read_4(sc, port); 3547 DPRINTFN(4, "index %d cp %d portsc=0x%08x", index, cp, v, 0); 3548 v &= ~XHCI_PS_CLEAR; 3549 switch (value) { 3550 case UHF_PORT_ENABLE: 3551 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3552 break; 3553 case UHF_PORT_SUSPEND: 3554 /* XXX suspend */ 3555 break; 3556 case UHF_PORT_RESET: 3557 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3558 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3559 /* Wait for reset to complete. */ 3560 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3561 if (sc->sc_dying) { 3562 return -1; 3563 } 3564 v = xhci_op_read_4(sc, port); 3565 if (v & XHCI_PS_PR) { 3566 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3567 usb_delay_ms(&sc->sc_bus, 10); 3568 /* XXX */ 3569 } 3570 break; 3571 case UHF_PORT_POWER: 3572 /* XXX power control */ 3573 break; 3574 /* XXX more */ 3575 case UHF_C_PORT_RESET: 3576 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3577 break; 3578 case UHF_PORT_U1_TIMEOUT: 3579 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3580 return -1; 3581 } 3582 port = XHCI_PORTPMSC(cp); 3583 v = xhci_op_read_4(sc, port); 3584 DPRINTFN(4, "index %d cp %d portpmsc=0x%08x", index, cp, v, 0); 3585 v &= ~XHCI_PM3_U1TO_SET(0xff); 3586 v |= XHCI_PM3_U1TO_SET(optval); 3587 xhci_op_write_4(sc, port, v); 3588 break; 3589 case UHF_PORT_U2_TIMEOUT: 3590 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3591 return -1; 3592 } 3593 port = XHCI_PORTPMSC(cp); 3594 v = xhci_op_read_4(sc, port); 3595 DPRINTFN(4, "index %d cp %d portpmsc=0x%08x", index, cp, v, 0); 3596 v &= ~XHCI_PM3_U2TO_SET(0xff); 3597 v |= XHCI_PM3_U2TO_SET(optval); 3598 xhci_op_write_4(sc, port, v); 3599 break; 3600 default: 3601 return -1; 3602 } 3603 } 3604 break; 3605 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3606 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3607 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3608 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3609 break; 3610 default: 3611 /* default from usbroothub */ 3612 return buflen; 3613 } 3614 3615 return totlen; 3616 } 3617 3618 /* root hub interrupt */ 3619 3620 static usbd_status 3621 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3622 { 3623 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3624 usbd_status err; 3625 3626 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3627 3628 /* Insert last in queue. */ 3629 mutex_enter(&sc->sc_lock); 3630 err = usb_insert_transfer(xfer); 3631 mutex_exit(&sc->sc_lock); 3632 if (err) 3633 return err; 3634 3635 /* Pipe isn't running, start first */ 3636 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3637 } 3638 3639 /* Wait for roothub port status/change */ 3640 static usbd_status 3641 xhci_root_intr_start(struct usbd_xfer *xfer) 3642 { 3643 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3644 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3645 3646 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3647 3648 if (sc->sc_dying) 3649 return USBD_IOERROR; 3650 3651 mutex_enter(&sc->sc_lock); 3652 sc->sc_intrxfer[bn] = xfer; 3653 mutex_exit(&sc->sc_lock); 3654 3655 return USBD_IN_PROGRESS; 3656 } 3657 3658 static void 3659 xhci_root_intr_abort(struct usbd_xfer *xfer) 3660 { 3661 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3662 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3663 3664 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3665 3666 KASSERT(mutex_owned(&sc->sc_lock)); 3667 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3668 3669 sc->sc_intrxfer[bn] = NULL; 3670 3671 xfer->ux_status = USBD_CANCELLED; 3672 usb_transfer_complete(xfer); 3673 } 3674 3675 static void 3676 xhci_root_intr_close(struct usbd_pipe *pipe) 3677 { 3678 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3679 const struct usbd_xfer *xfer = pipe->up_intrxfer; 3680 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3681 3682 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3683 3684 KASSERT(mutex_owned(&sc->sc_lock)); 3685 3686 sc->sc_intrxfer[bn] = NULL; 3687 } 3688 3689 static void 3690 xhci_root_intr_done(struct usbd_xfer *xfer) 3691 { 3692 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3693 3694 } 3695 3696 /* -------------- */ 3697 /* device control */ 3698 3699 static usbd_status 3700 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3701 { 3702 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3703 usbd_status err; 3704 3705 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3706 3707 /* Insert last in queue. */ 3708 mutex_enter(&sc->sc_lock); 3709 err = usb_insert_transfer(xfer); 3710 mutex_exit(&sc->sc_lock); 3711 if (err) 3712 return err; 3713 3714 /* Pipe isn't running, start first */ 3715 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3716 } 3717 3718 static usbd_status 3719 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3720 { 3721 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3722 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3723 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3724 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3725 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3726 usb_device_request_t * const req = &xfer->ux_request; 3727 const int isread = usbd_xfer_isread(xfer); 3728 const uint32_t len = UGETW(req->wLength); 3729 usb_dma_t * const dma = &xfer->ux_dmabuf; 3730 uint64_t parameter; 3731 uint32_t status; 3732 uint32_t control; 3733 u_int i; 3734 3735 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3736 DPRINTFN(12, "req: %04x %04x %04x %04x", 3737 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3738 UGETW(req->wIndex), UGETW(req->wLength)); 3739 3740 /* we rely on the bottom bits for extra info */ 3741 KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx", 3742 (uintptr_t) xfer); 3743 3744 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3745 3746 i = 0; 3747 3748 /* setup phase */ 3749 memcpy(¶meter, req, sizeof(parameter)); 3750 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3751 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3752 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3753 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3754 XHCI_TRB_3_IDT_BIT; 3755 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3756 3757 if (len != 0) { 3758 /* data phase */ 3759 parameter = DMAADDR(dma, 0); 3760 KASSERTMSG(len <= 0x10000, "len %d", len); 3761 status = XHCI_TRB_2_IRQ_SET(0) | 3762 XHCI_TRB_2_TDSZ_SET(1) | 3763 XHCI_TRB_2_BYTES_SET(len); 3764 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3765 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3766 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3767 XHCI_TRB_3_IOC_BIT; 3768 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3769 } 3770 3771 parameter = 0; 3772 status = XHCI_TRB_2_IRQ_SET(0); 3773 /* the status stage has inverted direction */ 3774 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3775 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3776 XHCI_TRB_3_IOC_BIT; 3777 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3778 3779 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3780 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3781 xhci_timeout, xfer); 3782 } 3783 xfer->ux_status = USBD_IN_PROGRESS; 3784 3785 mutex_enter(&tr->xr_lock); 3786 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3787 mutex_exit(&tr->xr_lock); 3788 3789 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3790 3791 return USBD_IN_PROGRESS; 3792 } 3793 3794 static void 3795 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3796 { 3797 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3798 usb_device_request_t *req = &xfer->ux_request; 3799 int len = UGETW(req->wLength); 3800 int rd = req->bmRequestType & UT_READ; 3801 3802 if (len) 3803 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3804 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3805 } 3806 3807 static void 3808 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3809 { 3810 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3811 3812 xhci_abort_xfer(xfer, USBD_CANCELLED); 3813 } 3814 3815 static void 3816 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3817 { 3818 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3819 3820 xhci_close_pipe(pipe); 3821 } 3822 3823 /* ------------------ */ 3824 /* device isochronous */ 3825 3826 /* ----------- */ 3827 /* device bulk */ 3828 3829 static usbd_status 3830 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3831 { 3832 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3833 usbd_status err; 3834 3835 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3836 3837 /* Insert last in queue. */ 3838 mutex_enter(&sc->sc_lock); 3839 err = usb_insert_transfer(xfer); 3840 mutex_exit(&sc->sc_lock); 3841 if (err) 3842 return err; 3843 3844 /* 3845 * Pipe isn't running (otherwise err would be USBD_INPROG), 3846 * so start it first. 3847 */ 3848 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3849 } 3850 3851 static usbd_status 3852 xhci_device_bulk_start(struct usbd_xfer *xfer) 3853 { 3854 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3855 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3856 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3857 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3858 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3859 const uint32_t len = xfer->ux_length; 3860 usb_dma_t * const dma = &xfer->ux_dmabuf; 3861 uint64_t parameter; 3862 uint32_t status; 3863 uint32_t control; 3864 u_int i = 0; 3865 3866 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3867 3868 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3869 3870 if (sc->sc_dying) 3871 return USBD_IOERROR; 3872 3873 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3874 3875 parameter = DMAADDR(dma, 0); 3876 /* 3877 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3878 * If the user supplied buffer crosses such a boundary then 2 3879 * (or more) TRB should be used. 3880 * If multiple TRB are used the td_size field must be set correctly. 3881 * For v1.0 devices (like ivy bridge) this is the number of usb data 3882 * blocks needed to complete the transfer. 3883 * Setting it to 1 in the last TRB causes an extra zero-length 3884 * data block be sent. 3885 * The earlier documentation differs, I don't know how it behaves. 3886 */ 3887 KASSERTMSG(len <= 0x10000, "len %d", len); 3888 status = XHCI_TRB_2_IRQ_SET(0) | 3889 XHCI_TRB_2_TDSZ_SET(1) | 3890 XHCI_TRB_2_BYTES_SET(len); 3891 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3892 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3893 XHCI_TRB_3_IOC_BIT; 3894 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3895 3896 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3897 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3898 xhci_timeout, xfer); 3899 } 3900 xfer->ux_status = USBD_IN_PROGRESS; 3901 3902 mutex_enter(&tr->xr_lock); 3903 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3904 mutex_exit(&tr->xr_lock); 3905 3906 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3907 3908 return USBD_IN_PROGRESS; 3909 } 3910 3911 static void 3912 xhci_device_bulk_done(struct usbd_xfer *xfer) 3913 { 3914 #ifdef USB_DEBUG 3915 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3916 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3917 #endif 3918 const int isread = usbd_xfer_isread(xfer); 3919 3920 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3921 3922 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3923 3924 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3925 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3926 } 3927 3928 static void 3929 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3930 { 3931 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3932 3933 xhci_abort_xfer(xfer, USBD_CANCELLED); 3934 } 3935 3936 static void 3937 xhci_device_bulk_close(struct usbd_pipe *pipe) 3938 { 3939 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3940 3941 xhci_close_pipe(pipe); 3942 } 3943 3944 /* ---------------- */ 3945 /* device interrupt */ 3946 3947 static usbd_status 3948 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3949 { 3950 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3951 usbd_status err; 3952 3953 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3954 3955 /* Insert last in queue. */ 3956 mutex_enter(&sc->sc_lock); 3957 err = usb_insert_transfer(xfer); 3958 mutex_exit(&sc->sc_lock); 3959 if (err) 3960 return err; 3961 3962 /* 3963 * Pipe isn't running (otherwise err would be USBD_INPROG), 3964 * so start it first. 3965 */ 3966 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3967 } 3968 3969 static usbd_status 3970 xhci_device_intr_start(struct usbd_xfer *xfer) 3971 { 3972 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3973 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3974 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3975 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3976 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3977 const uint32_t len = xfer->ux_length; 3978 usb_dma_t * const dma = &xfer->ux_dmabuf; 3979 uint64_t parameter; 3980 uint32_t status; 3981 uint32_t control; 3982 u_int i = 0; 3983 3984 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3985 3986 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3987 3988 if (sc->sc_dying) 3989 return USBD_IOERROR; 3990 3991 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3992 3993 parameter = DMAADDR(dma, 0); 3994 KASSERTMSG(len <= 0x10000, "len %d", len); 3995 status = XHCI_TRB_2_IRQ_SET(0) | 3996 XHCI_TRB_2_TDSZ_SET(1) | 3997 XHCI_TRB_2_BYTES_SET(len); 3998 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3999 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 4000 XHCI_TRB_3_IOC_BIT; 4001 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 4002 4003 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4004 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4005 xhci_timeout, xfer); 4006 } 4007 xfer->ux_status = USBD_IN_PROGRESS; 4008 4009 mutex_enter(&tr->xr_lock); 4010 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 4011 mutex_exit(&tr->xr_lock); 4012 4013 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4014 4015 return USBD_IN_PROGRESS; 4016 } 4017 4018 static void 4019 xhci_device_intr_done(struct usbd_xfer *xfer) 4020 { 4021 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4022 #ifdef USB_DEBUG 4023 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4024 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4025 #endif 4026 const int isread = usbd_xfer_isread(xfer); 4027 4028 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4029 4030 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 4031 4032 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4033 4034 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4035 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4036 } 4037 4038 static void 4039 xhci_device_intr_abort(struct usbd_xfer *xfer) 4040 { 4041 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4042 4043 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4044 4045 KASSERT(mutex_owned(&sc->sc_lock)); 4046 DPRINTFN(15, "%p", xfer, 0, 0, 0); 4047 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4048 xhci_abort_xfer(xfer, USBD_CANCELLED); 4049 } 4050 4051 static void 4052 xhci_device_intr_close(struct usbd_pipe *pipe) 4053 { 4054 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 4055 4056 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4057 DPRINTFN(15, "%p", pipe, 0, 0, 0); 4058 4059 xhci_close_pipe(pipe); 4060 } 4061 4062 /* ------------ */ 4063 4064 static void 4065 xhci_timeout(void *addr) 4066 { 4067 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4068 struct xhci_xfer * const xx = addr; 4069 struct usbd_xfer * const xfer = &xx->xx_xfer; 4070 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4071 bool timeout = false; 4072 4073 mutex_enter(&sc->sc_lock); 4074 if (sc->sc_dying) { 4075 mutex_exit(&sc->sc_lock); 4076 return; 4077 } 4078 if (xfer->ux_status != USBD_CANCELLED) { 4079 xfer->ux_status = USBD_TIMEOUT; 4080 timeout = true; 4081 } 4082 mutex_exit(&sc->sc_lock); 4083 4084 if (timeout) { 4085 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4086 4087 /* Execute the abort in a process context. */ 4088 usb_init_task(&xfer->ux_aborttask, xhci_timeout_task, xfer, 4089 USB_TASKQ_MPSAFE); 4090 usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC); 4091 } 4092 } 4093 4094 static void 4095 xhci_timeout_task(void *addr) 4096 { 4097 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4098 struct usbd_xfer * const xfer = addr; 4099 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4100 4101 mutex_enter(&sc->sc_lock); 4102 KASSERT(xfer->ux_status == USBD_TIMEOUT); 4103 xhci_abort_xfer(xfer, USBD_TIMEOUT); 4104 mutex_exit(&sc->sc_lock); 4105 } 4106
Indexes created Wed Oct 01 15:09:59 GMT 2025