xhci.c revision 1.34
1 /* $NetBSD: xhci.c,v 1.34 2016/04/23 10:15:32 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 3.1 specification 31 * http://www.usb.org/developers/docs/usb_31_040315.zip 32 * USB rev 2.0 specification 33 * http://www.usb.org/developers/docs/usb20_docs/usb_20_031815.zip 34 * xHCI rev 1.1 specification 35 * http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.34 2016/04/23 10:15:32 skrll Exp $"); 40 41 #include "opt_usb.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 146 147 static usbd_status xhci_do_command(struct xhci_softc * const, 148 struct xhci_trb * const, int); 149 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 150 struct xhci_trb * const, int); 151 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t, uint32_t, int); 152 static usbd_status xhci_enable_slot(struct xhci_softc * const, 153 uint8_t * const); 154 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 155 static usbd_status xhci_address_device(struct xhci_softc * const, 156 uint64_t, uint8_t, bool); 157 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 158 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 159 struct xhci_slot * const, u_int); 160 static usbd_status xhci_ring_init(struct xhci_softc * const, 161 struct xhci_ring * const, size_t, size_t); 162 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 163 164 static void xhci_noop(struct usbd_pipe *); 165 166 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 167 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 168 static void xhci_root_intr_abort(struct usbd_xfer *); 169 static void xhci_root_intr_close(struct usbd_pipe *); 170 static void xhci_root_intr_done(struct usbd_xfer *); 171 172 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 173 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 174 static void xhci_device_ctrl_abort(struct usbd_xfer *); 175 static void xhci_device_ctrl_close(struct usbd_pipe *); 176 static void xhci_device_ctrl_done(struct usbd_xfer *); 177 178 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 179 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 180 static void xhci_device_intr_abort(struct usbd_xfer *); 181 static void xhci_device_intr_close(struct usbd_pipe *); 182 static void xhci_device_intr_done(struct usbd_xfer *); 183 184 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 185 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 186 static void xhci_device_bulk_abort(struct usbd_xfer *); 187 static void xhci_device_bulk_close(struct usbd_pipe *); 188 static void xhci_device_bulk_done(struct usbd_xfer *); 189 190 static void xhci_timeout(void *); 191 static void xhci_timeout_task(void *); 192 193 static const struct usbd_bus_methods xhci_bus_methods = { 194 .ubm_open = xhci_open, 195 .ubm_softint = xhci_softintr, 196 .ubm_dopoll = xhci_poll, 197 .ubm_allocx = xhci_allocx, 198 .ubm_freex = xhci_freex, 199 .ubm_getlock = xhci_get_lock, 200 .ubm_newdev = xhci_new_device, 201 .ubm_rhctrl = xhci_roothub_ctrl, 202 }; 203 204 static const struct usbd_pipe_methods xhci_root_intr_methods = { 205 .upm_transfer = xhci_root_intr_transfer, 206 .upm_start = xhci_root_intr_start, 207 .upm_abort = xhci_root_intr_abort, 208 .upm_close = xhci_root_intr_close, 209 .upm_cleartoggle = xhci_noop, 210 .upm_done = xhci_root_intr_done, 211 }; 212 213 214 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 215 .upm_transfer = xhci_device_ctrl_transfer, 216 .upm_start = xhci_device_ctrl_start, 217 .upm_abort = xhci_device_ctrl_abort, 218 .upm_close = xhci_device_ctrl_close, 219 .upm_cleartoggle = xhci_noop, 220 .upm_done = xhci_device_ctrl_done, 221 }; 222 223 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 224 .upm_cleartoggle = xhci_noop, 225 }; 226 227 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 228 .upm_transfer = xhci_device_bulk_transfer, 229 .upm_start = xhci_device_bulk_start, 230 .upm_abort = xhci_device_bulk_abort, 231 .upm_close = xhci_device_bulk_close, 232 .upm_cleartoggle = xhci_noop, 233 .upm_done = xhci_device_bulk_done, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_intr_methods = { 237 .upm_transfer = xhci_device_intr_transfer, 238 .upm_start = xhci_device_intr_start, 239 .upm_abort = xhci_device_intr_abort, 240 .upm_close = xhci_device_intr_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_intr_done, 243 }; 244 245 static inline uint32_t 246 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 247 { 248 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 249 } 250 251 static inline uint32_t 252 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 253 { 254 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 255 } 256 257 static inline void 258 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 259 uint32_t value) 260 { 261 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 262 } 263 264 #if 0 /* unused */ 265 static inline void 266 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 267 uint32_t value) 268 { 269 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 270 } 271 #endif /* unused */ 272 273 static inline uint32_t 274 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 275 { 276 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 277 } 278 279 static inline uint32_t 280 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 281 { 282 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 283 } 284 285 static inline void 286 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 287 uint32_t value) 288 { 289 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 290 } 291 292 #if 0 /* unused */ 293 static inline uint64_t 294 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 295 { 296 uint64_t value; 297 298 if (sc->sc_ac64) { 299 #ifdef XHCI_USE_BUS_SPACE_8 300 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 301 #else 302 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 303 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 304 offset + 4) << 32; 305 #endif 306 } else { 307 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 308 } 309 310 return value; 311 } 312 #endif /* unused */ 313 314 static inline void 315 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 316 uint64_t value) 317 { 318 if (sc->sc_ac64) { 319 #ifdef XHCI_USE_BUS_SPACE_8 320 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 321 #else 322 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 323 (value >> 0) & 0xffffffff); 324 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 325 (value >> 32) & 0xffffffff); 326 #endif 327 } else { 328 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 329 } 330 } 331 332 static inline uint32_t 333 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 334 { 335 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 336 } 337 338 static inline void 339 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 340 uint32_t value) 341 { 342 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 343 } 344 345 #if 0 /* unused */ 346 static inline uint64_t 347 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 348 { 349 uint64_t value; 350 351 if (sc->sc_ac64) { 352 #ifdef XHCI_USE_BUS_SPACE_8 353 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 354 #else 355 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 356 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 357 offset + 4) << 32; 358 #endif 359 } else { 360 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 361 } 362 363 return value; 364 } 365 #endif /* unused */ 366 367 static inline void 368 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 369 uint64_t value) 370 { 371 if (sc->sc_ac64) { 372 #ifdef XHCI_USE_BUS_SPACE_8 373 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 374 #else 375 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 376 (value >> 0) & 0xffffffff); 377 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 378 (value >> 32) & 0xffffffff); 379 #endif 380 } else { 381 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 382 } 383 } 384 385 #if 0 /* unused */ 386 static inline uint32_t 387 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 388 { 389 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 390 } 391 #endif /* unused */ 392 393 static inline void 394 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 395 uint32_t value) 396 { 397 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 398 } 399 400 /* --- */ 401 402 static inline uint8_t 403 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 404 { 405 u_int eptype = 0; 406 407 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 408 case UE_CONTROL: 409 eptype = 0x0; 410 break; 411 case UE_ISOCHRONOUS: 412 eptype = 0x1; 413 break; 414 case UE_BULK: 415 eptype = 0x2; 416 break; 417 case UE_INTERRUPT: 418 eptype = 0x3; 419 break; 420 } 421 422 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 423 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 424 return eptype | 0x4; 425 else 426 return eptype; 427 } 428 429 static u_int 430 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 431 { 432 /* xHCI 1.0 section 4.5.1 */ 433 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 434 u_int in = 0; 435 436 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 437 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 438 in = 1; 439 440 return epaddr * 2 + in; 441 } 442 443 static inline u_int 444 xhci_dci_to_ici(const u_int i) 445 { 446 return i + 1; 447 } 448 449 static inline void * 450 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 451 const u_int dci) 452 { 453 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 454 } 455 456 #if 0 /* unused */ 457 static inline bus_addr_t 458 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 459 const u_int dci) 460 { 461 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 462 } 463 #endif /* unused */ 464 465 static inline void * 466 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 467 const u_int ici) 468 { 469 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 470 } 471 472 static inline bus_addr_t 473 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline struct xhci_trb * 480 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 481 { 482 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 483 } 484 485 static inline bus_addr_t 486 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 487 { 488 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 489 } 490 491 static inline void 492 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 493 uint32_t control) 494 { 495 trb->trb_0 = htole64(parameter); 496 trb->trb_2 = htole32(status); 497 trb->trb_3 = htole32(control); 498 } 499 500 /* --- */ 501 502 void 503 xhci_childdet(device_t self, device_t child) 504 { 505 struct xhci_softc * const sc = device_private(self); 506 507 KASSERT(sc->sc_child == child); 508 if (child == sc->sc_child) 509 sc->sc_child = NULL; 510 } 511 512 int 513 xhci_detach(struct xhci_softc *sc, int flags) 514 { 515 int rv = 0; 516 517 if (sc->sc_child != NULL) 518 rv = config_detach(sc->sc_child, flags); 519 520 if (rv != 0) 521 return rv; 522 523 /* XXX unconfigure/free slots */ 524 525 /* verify: */ 526 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 527 xhci_op_write_4(sc, XHCI_USBCMD, 0); 528 /* do we need to wait for stop? */ 529 530 xhci_op_write_8(sc, XHCI_CRCR, 0); 531 xhci_ring_free(sc, &sc->sc_cr); 532 cv_destroy(&sc->sc_command_cv); 533 534 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 535 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 536 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 537 xhci_ring_free(sc, &sc->sc_er); 538 539 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 540 541 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 542 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 543 544 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 545 546 mutex_destroy(&sc->sc_lock); 547 mutex_destroy(&sc->sc_intr_lock); 548 cv_destroy(&sc->sc_softwake_cv); 549 550 pool_cache_destroy(sc->sc_xferpool); 551 552 return rv; 553 } 554 555 int 556 xhci_activate(device_t self, enum devact act) 557 { 558 struct xhci_softc * const sc = device_private(self); 559 560 switch (act) { 561 case DVACT_DEACTIVATE: 562 sc->sc_dying = true; 563 return 0; 564 default: 565 return EOPNOTSUPP; 566 } 567 } 568 569 bool 570 xhci_suspend(device_t dv, const pmf_qual_t *qual) 571 { 572 return false; 573 } 574 575 bool 576 xhci_resume(device_t dv, const pmf_qual_t *qual) 577 { 578 return false; 579 } 580 581 bool 582 xhci_shutdown(device_t self, int flags) 583 { 584 return false; 585 } 586 587 588 static void 589 hexdump(const char *msg, const void *base, size_t len) 590 { 591 #if 0 592 size_t cnt; 593 const uint32_t *p; 594 extern paddr_t vtophys(vaddr_t); 595 596 p = base; 597 cnt = 0; 598 599 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 600 (void *)vtophys((vaddr_t)base)); 601 602 while (cnt < len) { 603 if (cnt % 16 == 0) 604 printf("%p: ", p); 605 else if (cnt % 8 == 0) 606 printf(" |"); 607 printf(" %08x", *p++); 608 cnt += 4; 609 if (cnt % 16 == 0) 610 printf("\n"); 611 } 612 #endif 613 } 614 615 #define XHCI_HCCPREV1_BITS \ 616 "\177\020" /* New bitmask */ \ 617 "f\020\020XECP\0" \ 618 "f\014\4MAXPSA\0" \ 619 "b\013CFC\0" \ 620 "b\012SEC\0" \ 621 "b\011SBD\0" \ 622 "b\010FSE\0" \ 623 "b\7NSS\0" \ 624 "b\6LTC\0" \ 625 "b\5LHRC\0" \ 626 "b\4PIND\0" \ 627 "b\3PPC\0" \ 628 "b\2CZC\0" \ 629 "b\1BNC\0" \ 630 "b\0AC64\0" \ 631 "\0" 632 #define XHCI_HCCV1_x_BITS \ 633 "\177\020" /* New bitmask */ \ 634 "f\020\020XECP\0" \ 635 "f\014\4MAXPSA\0" \ 636 "b\013CFC\0" \ 637 "b\012SEC\0" \ 638 "b\011SPC\0" \ 639 "b\010PAE\0" \ 640 "b\7NSS\0" \ 641 "b\6LTC\0" \ 642 "b\5LHRC\0" \ 643 "b\4PIND\0" \ 644 "b\3PPC\0" \ 645 "b\2CSZ\0" \ 646 "b\1BNC\0" \ 647 "b\0AC64\0" \ 648 "\0" 649 650 int 651 xhci_init(struct xhci_softc *sc) 652 { 653 bus_size_t bsz; 654 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 655 uint32_t ecp, ecr; 656 uint32_t usbcmd, usbsts, pagesize, config; 657 int i; 658 uint16_t hciversion; 659 uint8_t caplength; 660 661 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 662 663 sc->sc_bus.ub_revision = USBREV_3_0; 664 sc->sc_bus.ub_usedma = true; 665 666 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 667 caplength = XHCI_CAP_CAPLENGTH(cap); 668 hciversion = XHCI_CAP_HCIVERSION(cap); 669 670 if (hciversion < XHCI_HCIVERSION_0_96 || 671 hciversion > XHCI_HCIVERSION_1_0) { 672 aprint_normal_dev(sc->sc_dev, 673 "xHCI version %x.%x not known to be supported\n", 674 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 675 } else { 676 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 677 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 678 } 679 680 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 681 &sc->sc_cbh) != 0) { 682 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 683 return ENOMEM; 684 } 685 686 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 687 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 688 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 689 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 690 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 691 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 692 aprint_debug_dev(sc->sc_dev, 693 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 694 695 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 696 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 697 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 698 699 char sbuf[128]; 700 if (hciversion < XHCI_HCIVERSION_1_0) 701 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 702 else 703 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 704 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 705 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 706 707 ecp = XHCI_HCC_XECP(hcc) * 4; 708 while (ecp != 0) { 709 ecr = xhci_read_4(sc, ecp); 710 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 711 switch (XHCI_XECP_ID(ecr)) { 712 case XHCI_ID_PROTOCOLS: { 713 uint32_t w0, w4, w8; 714 uint16_t w2; 715 w0 = xhci_read_4(sc, ecp + 0); 716 w2 = (w0 >> 16) & 0xffff; 717 w4 = xhci_read_4(sc, ecp + 4); 718 w8 = xhci_read_4(sc, ecp + 8); 719 aprint_debug_dev(sc->sc_dev, "SP: %08x %08x %08x\n", 720 w0, w4, w8); 721 if (w4 == 0x20425355 && w2 == 0x0300) { 722 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 723 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 724 } 725 if (w4 == 0x20425355 && w2 == 0x0200) { 726 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 727 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 728 } 729 break; 730 } 731 case XHCI_ID_USB_LEGACY: { 732 uint8_t bios_sem; 733 734 /* Take host controller from BIOS */ 735 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 736 if (bios_sem) { 737 /* sets xHCI to be owned by OS */ 738 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 739 aprint_debug( 740 "waiting for BIOS to give up control\n"); 741 for (i = 0; i < 5000; i++) { 742 bios_sem = xhci_read_1(sc, ecp + 743 XHCI_XECP_BIOS_SEM); 744 if (bios_sem == 0) 745 break; 746 DELAY(1000); 747 } 748 if (bios_sem) 749 printf("timed out waiting for BIOS\n"); 750 } 751 break; 752 } 753 default: 754 break; 755 } 756 ecr = xhci_read_4(sc, ecp); 757 if (XHCI_XECP_NEXT(ecr) == 0) { 758 ecp = 0; 759 } else { 760 ecp += XHCI_XECP_NEXT(ecr) * 4; 761 } 762 } 763 764 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 765 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 766 &sc->sc_obh) != 0) { 767 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 768 return ENOMEM; 769 } 770 771 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 772 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 773 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 774 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 775 return ENOMEM; 776 } 777 778 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 779 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 780 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 781 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 782 return ENOMEM; 783 } 784 785 for (i = 0; i < 100; i++) { 786 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 787 if ((usbsts & XHCI_STS_CNR) == 0) 788 break; 789 usb_delay_ms(&sc->sc_bus, 1); 790 } 791 if (i >= 100) 792 return EIO; 793 794 usbcmd = 0; 795 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 796 usb_delay_ms(&sc->sc_bus, 1); 797 798 usbcmd = XHCI_CMD_HCRST; 799 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 800 for (i = 0; i < 100; i++) { 801 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 802 if ((usbcmd & XHCI_CMD_HCRST) == 0) 803 break; 804 usb_delay_ms(&sc->sc_bus, 1); 805 } 806 if (i >= 100) 807 return EIO; 808 809 for (i = 0; i < 100; i++) { 810 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 811 if ((usbsts & XHCI_STS_CNR) == 0) 812 break; 813 usb_delay_ms(&sc->sc_bus, 1); 814 } 815 if (i >= 100) 816 return EIO; 817 818 if (sc->sc_vendor_init) 819 sc->sc_vendor_init(sc); 820 821 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 822 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 823 pagesize = ffs(pagesize); 824 if (pagesize == 0) 825 return EIO; 826 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 827 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 828 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 829 (uint32_t)sc->sc_maxslots); 830 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 831 832 usbd_status err; 833 834 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 835 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 836 if (sc->sc_maxspbuf != 0) { 837 err = usb_allocmem(&sc->sc_bus, 838 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 839 &sc->sc_spbufarray_dma); 840 if (err) 841 return err; 842 843 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * sc->sc_maxspbuf, KM_SLEEP); 844 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 845 for (i = 0; i < sc->sc_maxspbuf; i++) { 846 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 847 /* allocate contexts */ 848 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 849 sc->sc_pgsz, dma); 850 if (err) 851 return err; 852 spbufarray[i] = htole64(DMAADDR(dma, 0)); 853 usb_syncmem(dma, 0, sc->sc_pgsz, 854 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 855 } 856 857 usb_syncmem(&sc->sc_spbufarray_dma, 0, 858 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 859 } 860 861 config = xhci_op_read_4(sc, XHCI_CONFIG); 862 config &= ~0xFF; 863 config |= sc->sc_maxslots & 0xFF; 864 xhci_op_write_4(sc, XHCI_CONFIG, config); 865 866 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 867 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 868 if (err) { 869 aprint_error_dev(sc->sc_dev, "command ring init fail\n"); 870 return err; 871 } 872 873 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 874 XHCI_EVENT_RING_SEGMENTS_ALIGN); 875 if (err) { 876 aprint_error_dev(sc->sc_dev, "event ring init fail\n"); 877 return err; 878 } 879 880 usb_dma_t *dma; 881 size_t size; 882 size_t align; 883 884 dma = &sc->sc_eventst_dma; 885 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 886 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 887 KASSERT(size <= (512 * 1024)); 888 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 889 err = usb_allocmem(&sc->sc_bus, size, align, dma); 890 891 memset(KERNADDR(dma, 0), 0, size); 892 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 893 aprint_debug_dev(sc->sc_dev, "eventst: %s %016jx %p %zx\n", 894 usbd_errstr(err), 895 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 896 KERNADDR(&sc->sc_eventst_dma, 0), 897 sc->sc_eventst_dma.udma_block->size); 898 899 dma = &sc->sc_dcbaa_dma; 900 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 901 KASSERT(size <= 2048); 902 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 903 err = usb_allocmem(&sc->sc_bus, size, align, dma); 904 905 memset(KERNADDR(dma, 0), 0, size); 906 if (sc->sc_maxspbuf != 0) { 907 /* 908 * DCBA entry 0 hold the scratchbuf array pointer. 909 */ 910 *(uint64_t *)KERNADDR(dma, 0) = 911 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 912 } 913 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 914 aprint_debug_dev(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n", 915 usbd_errstr(err), 916 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 917 KERNADDR(&sc->sc_dcbaa_dma, 0), 918 sc->sc_dcbaa_dma.udma_block->size); 919 920 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 921 KM_SLEEP); 922 923 cv_init(&sc->sc_command_cv, "xhcicmd"); 924 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 925 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 926 cv_init(&sc->sc_softwake_cv, "xhciab"); 927 928 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 929 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 930 931 /* Set up the bus struct. */ 932 sc->sc_bus.ub_methods = &xhci_bus_methods; 933 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 934 935 struct xhci_erste *erst; 936 erst = KERNADDR(&sc->sc_eventst_dma, 0); 937 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 938 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 939 erst[0].erste_3 = htole32(0); 940 usb_syncmem(&sc->sc_eventst_dma, 0, 941 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 942 943 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 944 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 945 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 946 XHCI_ERDP_LO_BUSY); 947 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 948 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 949 sc->sc_cr.xr_cs); 950 951 #if 0 952 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 953 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 954 #endif 955 956 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 957 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 958 /* Intel xhci needs interrupt rate moderated. */ 959 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 960 else 961 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 962 aprint_debug_dev(sc->sc_dev, "setting IMOD %u\n", 963 xhci_rt_read_4(sc, XHCI_IMOD(0))); 964 965 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 966 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 967 xhci_op_read_4(sc, XHCI_USBCMD)); 968 969 return USBD_NORMAL_COMPLETION; 970 } 971 972 int 973 xhci_intr(void *v) 974 { 975 struct xhci_softc * const sc = v; 976 int ret = 0; 977 978 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 979 980 if (sc == NULL) 981 return 0; 982 983 mutex_spin_enter(&sc->sc_intr_lock); 984 985 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 986 goto done; 987 988 /* If we get an interrupt while polling, then just ignore it. */ 989 if (sc->sc_bus.ub_usepolling) { 990 #ifdef DIAGNOSTIC 991 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 992 #endif 993 goto done; 994 } 995 996 ret = xhci_intr1(sc); 997 done: 998 mutex_spin_exit(&sc->sc_intr_lock); 999 return ret; 1000 } 1001 1002 int 1003 xhci_intr1(struct xhci_softc * const sc) 1004 { 1005 uint32_t usbsts; 1006 uint32_t iman; 1007 1008 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1009 1010 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1011 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1012 #if 0 1013 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1014 return 0; 1015 } 1016 #endif 1017 xhci_op_write_4(sc, XHCI_USBSTS, 1018 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1019 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1020 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1021 1022 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1023 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1024 iman |= XHCI_IMAN_INTR_PEND; 1025 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1026 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1027 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1028 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1029 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1030 1031 usb_schedsoftintr(&sc->sc_bus); 1032 1033 return 1; 1034 } 1035 1036 /* 1037 * 3 port speed types used in USB stack 1038 * 1039 * usbdi speed 1040 * definition: USB_SPEED_* in usb.h 1041 * They are used in struct usbd_device in USB stack. 1042 * ioctl interface uses these values too. 1043 * port_status speed 1044 * definition: UPS_*_SPEED in usb.h 1045 * They are used in usb_port_status_t and valid only for USB 2.0. 1046 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1047 * of usb_port_status_ext_t indicates port speed. 1048 * Note that some 3.0 values overlap with 2.0 values. 1049 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1050 * means UPS_LOW_SPEED in HS.) 1051 * port status returned from hub also uses these values. 1052 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1053 * or more. 1054 * xspeed: 1055 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1056 * They are used in only slot context and PORTSC reg of xhci. 1057 * The difference between usbdi speed and xspeed is 1058 * that FS and LS values are swapped. 1059 */ 1060 1061 /* convert usbdi speed to xspeed */ 1062 static int 1063 xhci_speed2xspeed(int speed) 1064 { 1065 switch (speed) { 1066 case USB_SPEED_LOW: return 2; 1067 case USB_SPEED_FULL: return 1; 1068 default: return speed; 1069 } 1070 } 1071 1072 #if 0 1073 /* convert xspeed to usbdi speed */ 1074 static int 1075 xhci_xspeed2speed(int xspeed) 1076 { 1077 switch (xspeed) { 1078 case 1: return USB_SPEED_FULL; 1079 case 2: return USB_SPEED_LOW; 1080 default: return xspeed; 1081 } 1082 } 1083 #endif 1084 1085 /* convert xspeed to port status speed */ 1086 static int 1087 xhci_xspeed2psspeed(int xspeed) 1088 { 1089 switch (xspeed) { 1090 case 0: return 0; 1091 case 1: return UPS_FULL_SPEED; 1092 case 2: return UPS_LOW_SPEED; 1093 case 3: return UPS_HIGH_SPEED; 1094 default: return UPS_OTHER_SPEED; 1095 } 1096 } 1097 1098 /* construct slot context */ 1099 static void 1100 xhci_setup_sctx(struct usbd_device *dev, uint32_t *cp) 1101 { 1102 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 1103 int speed = dev->ud_speed; 1104 int tthubslot, ttportnum; 1105 bool ishub; 1106 bool usemtt; 1107 1108 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1109 1110 /* 1111 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 1112 * tthubslot: 1113 * This is the slot ID of parent HS hub 1114 * if LS/FS device is connected && connected through HS hub. 1115 * This is 0 if device is not LS/FS device || 1116 * parent hub is not HS hub || 1117 * attached to root hub. 1118 * ttportnum: 1119 * This is the downstream facing port of parent HS hub 1120 * if LS/FS device is connected. 1121 * This is 0 if device is not LS/FS device || 1122 * parent hub is not HS hub || 1123 * attached to root hub. 1124 */ 1125 if (dev->ud_myhsport != NULL && 1126 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1127 (dev->ud_myhub != NULL && 1128 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1129 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 1130 ttportnum = dev->ud_myhsport->up_portno; 1131 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 1132 } else { 1133 ttportnum = 0; 1134 tthubslot = 0; 1135 } 1136 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 1137 dev->ud_myhsport, ttportnum, tthubslot, 0); 1138 1139 /* ishub is valid after reading UDESC_DEVICE */ 1140 ishub = (dd->bDeviceClass == UDCLASS_HUB); 1141 1142 /* dev->ud_hub is valid after reading UDESC_HUB */ 1143 if (ishub && dev->ud_hub) { 1144 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 1145 1146 cp[1] |= htole32(XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts)); 1147 cp[2] |= htole32(XHCI_SCTX_2_TT_THINK_TIME_SET( 1148 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK))); 1149 DPRINTFN(4, "nports=%d ttt=%d", 1150 hd->bNbrPorts, XHCI_SCTX_2_TT_THINK_TIME_GET(cp[2]), 0, 0); 1151 } 1152 1153 #define IS_TTHUB(dd) \ 1154 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 1155 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 1156 1157 /* 1158 * MTT flag is set if 1159 * 1. this is HS hub && MTT is enabled 1160 * or 1161 * 2. this is not hub && this is LS or FS device && 1162 * MTT of parent HS hub (and its parent, too) is enabled 1163 */ 1164 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 1165 usemtt = true; 1166 else if (!ishub && 1167 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 1168 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1169 (dev->ud_myhub != NULL && 1170 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1171 dev->ud_myhsport != NULL && 1172 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 1173 usemtt = true; 1174 else 1175 usemtt = false; 1176 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 1177 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 1178 1179 cp[0] |= htole32( 1180 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)) | 1181 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 1182 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0) 1183 ); 1184 cp[1] |= htole32(0); 1185 cp[2] |= htole32( 1186 XHCI_SCTX_2_IRQ_TARGET_SET(0) | 1187 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 1188 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum) 1189 ); 1190 cp[3] |= htole32(0); 1191 } 1192 1193 static uint32_t 1194 xhci_get_maxburst(struct usbd_pipe *pipe) 1195 { 1196 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1197 usbd_desc_iter_t iter; 1198 const usb_cdc_descriptor_t *cdcd; 1199 const usb_endpoint_ss_comp_descriptor_t * esscd = NULL; 1200 uint32_t maxb = 0; 1201 uint8_t ep; 1202 1203 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc( 1204 pipe->up_dev, UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 1205 usb_desc_iter_init(pipe->up_dev, &iter); 1206 iter.cur = (const void *)cdcd; 1207 1208 /* find endpoint_ss_comp desc for ep of this pipe */ 1209 for (ep = 0;;) { 1210 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 1211 if (cdcd == NULL) 1212 break; 1213 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 1214 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 1215 bEndpointAddress; 1216 if (UE_GET_ADDR(ep) == 1217 UE_GET_ADDR(ed->bEndpointAddress)) { 1218 cdcd = (const usb_cdc_descriptor_t *) 1219 usb_desc_iter_next(&iter); 1220 break; 1221 } 1222 ep = 0; 1223 } 1224 } 1225 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 1226 esscd = (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 1227 maxb = esscd->bMaxBurst; 1228 } 1229 1230 return maxb; 1231 } 1232 1233 /* 1234 * Convert endpoint bInterval value to endpoint context interval value 1235 * for Interrupt pipe. 1236 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 1237 */ 1238 static uint32_t 1239 xhci_bival2ival(uint32_t ival, int speed) 1240 { 1241 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 1242 int i; 1243 1244 /* 1245 * round ival down to "the nearest base 2 multiple of 1246 * bInterval * 8". 1247 * bInterval is at most 255 as its type is uByte. 1248 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 1249 */ 1250 for (i = 10; i > 0; i--) { 1251 if ((ival * 8) >= (1 << i)) 1252 break; 1253 } 1254 ival = i; 1255 } else { 1256 /* Interval = bInterval-1 for SS/HS */ 1257 ival--; 1258 } 1259 1260 return ival; 1261 } 1262 1263 /* 1264 * 4.8.2, 6.2.3.2 1265 * construct common endpoint parameters 1266 */ 1267 static void 1268 xhci_setup_endp_ctx(struct usbd_pipe *pipe, uint32_t *cp) 1269 { 1270 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1271 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1272 const u_int dci = xhci_ep_get_dci(ed); 1273 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1274 uint32_t mps = UGETW(ed->wMaxPacketSize); 1275 uint32_t maxb = 0; 1276 int speed = pipe->up_dev->ud_speed; 1277 uint32_t ival = ed->bInterval; 1278 1279 cp[0] = htole32( 1280 XHCI_EPCTX_0_EPSTATE_SET(0) | 1281 XHCI_EPCTX_0_MULT_SET(0) | /* always 0 except SS iscoh */ 1282 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 1283 XHCI_EPCTX_0_LSA_SET(0) | 1284 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0) 1285 ); 1286 cp[1] = htole32( 1287 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 1288 XHCI_EPCTX_1_HID_SET(0) | 1289 XHCI_EPCTX_1_MAXB_SET(0) 1290 ); 1291 if (xfertype != UE_ISOCHRONOUS) 1292 cp[1] |= htole32(XHCI_EPCTX_1_CERR_SET(3)); 1293 1294 /* 6.2.3.4, 4.8.2.4 */ 1295 if (USB_IS_SS(speed)) { 1296 /* UBS 3.1 9.6.6 */ 1297 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1298 /* UBS 3.1 9.6.7 */ 1299 maxb = xhci_get_maxburst(pipe); 1300 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1301 } else { 1302 /* UBS 2.0 9.6.6 */ 1303 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps))); 1304 1305 /* 6.2.3.4 */ 1306 if (speed == USB_SPEED_HIGH && 1307 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 1308 maxb = UE_GET_TRANS(mps); 1309 } else { 1310 /* LS/FS or HS CTRL or HS BULK */ 1311 maxb = 0; 1312 } 1313 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1314 } 1315 1316 if (xfertype == UE_CONTROL) 1317 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(8)); /* 6.2.3 */ 1318 else if (USB_IS_SS(speed)) 1319 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps)); 1320 else 1321 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps))); 1322 1323 switch (xfertype) { 1324 case UE_CONTROL: 1325 break; 1326 case UE_BULK: 1327 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 1328 break; 1329 case UE_INTERRUPT: 1330 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1331 ival = pipe->up_interval; 1332 1333 ival = xhci_bival2ival(ival, speed); 1334 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1335 break; 1336 case UE_ISOCHRONOUS: 1337 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1338 ival = pipe->up_interval; 1339 1340 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 1341 if (speed == USB_SPEED_FULL) 1342 ival += 3; /* 1ms -> 125us */ 1343 ival--; 1344 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1345 1346 if (USB_IS_SS(speed)) { 1347 /* XXX if LEC = 1, set ESIT instead */ 1348 cp[0] |= htole32(XHCI_EPCTX_0_MULT_SET(0)); 1349 } 1350 break; 1351 default: 1352 break; 1353 } 1354 *(uint64_t *)(&cp[2]) = htole64( 1355 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 1356 XHCI_EPCTX_2_DCS_SET(1)); 1357 } 1358 1359 /* 1360 * Construct input contexts and issue TRB 1361 */ 1362 static usbd_status 1363 xhci_configure_endpoint(struct usbd_pipe *pipe) 1364 { 1365 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1366 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1367 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1368 struct xhci_trb trb; 1369 usbd_status err; 1370 uint32_t *cp; 1371 1372 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1373 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1374 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1375 pipe->up_endpoint->ue_edesc->bmAttributes); 1376 1377 /* XXX ensure input context is available? */ 1378 1379 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1380 1381 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1382 cp[0] = htole32(0); 1383 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 1384 1385 /* set up input slot context */ 1386 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1387 xhci_setup_sctx(pipe->up_dev, cp); 1388 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1389 1390 /* set up input endpoint context */ 1391 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 1392 xhci_setup_endp_ctx(pipe, cp); 1393 1394 /* sync input contexts before they are read from memory */ 1395 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1396 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1397 sc->sc_ctxsz * 1); 1398 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1399 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1400 1401 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1402 trb.trb_2 = 0; 1403 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1404 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1405 1406 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1407 1408 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1409 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1410 sc->sc_ctxsz * 1); 1411 1412 return err; 1413 } 1414 1415 #if 0 1416 static usbd_status 1417 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1418 { 1419 #ifdef USB_DEBUG 1420 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1421 #endif 1422 1423 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1424 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1425 1426 return USBD_NORMAL_COMPLETION; 1427 } 1428 #endif 1429 1430 /* 4.6.8, 6.4.3.7 */ 1431 static usbd_status 1432 xhci_reset_endpoint(struct usbd_pipe *pipe) 1433 { 1434 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1435 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1436 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1437 struct xhci_trb trb; 1438 usbd_status err; 1439 1440 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1441 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1442 1443 KASSERT(!mutex_owned(&sc->sc_lock)); 1444 1445 trb.trb_0 = 0; 1446 trb.trb_2 = 0; 1447 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1448 XHCI_TRB_3_EP_SET(dci) | 1449 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1450 1451 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1452 1453 return err; 1454 } 1455 1456 /* 1457 * 4.6.9, 6.4.3.8 1458 * Stop execution of TDs on xfer ring. 1459 * Should be called with sc_lock held. 1460 */ 1461 static usbd_status 1462 xhci_stop_endpoint(struct usbd_pipe *pipe) 1463 { 1464 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1465 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1466 struct xhci_trb trb; 1467 usbd_status err; 1468 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1469 1470 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1471 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1472 1473 KASSERT(mutex_owned(&sc->sc_lock)); 1474 1475 trb.trb_0 = 0; 1476 trb.trb_2 = 0; 1477 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1478 XHCI_TRB_3_EP_SET(dci) | 1479 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1480 1481 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1482 1483 return err; 1484 } 1485 1486 /* 1487 * Set TR Dequeue Pointer. 1488 * xCHI 1.1 4.6.10 6.4.3.9 1489 * Purge all of the transfer requests on ring. 1490 * EPSTATE of endpoint must be ERROR or STOPPED, or CONTEXT_STATE error. 1491 */ 1492 static usbd_status 1493 xhci_set_dequeue(struct usbd_pipe *pipe) 1494 { 1495 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1496 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1497 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1498 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1499 struct xhci_trb trb; 1500 usbd_status err; 1501 1502 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1503 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1504 1505 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1506 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1507 BUS_DMASYNC_PREWRITE); 1508 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1509 1510 xr->xr_ep = 0; 1511 xr->xr_cs = 1; 1512 1513 /* set DCS */ 1514 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1515 trb.trb_2 = 0; 1516 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1517 XHCI_TRB_3_EP_SET(dci) | 1518 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1519 1520 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1521 1522 return err; 1523 } 1524 1525 /* 1526 * Open new pipe: called from usbd_setup_pipe_flags. 1527 * Fills methods of pipe. 1528 * If pipe is not for ep0, calls configure_endpoint. 1529 */ 1530 static usbd_status 1531 xhci_open(struct usbd_pipe *pipe) 1532 { 1533 struct usbd_device * const dev = pipe->up_dev; 1534 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1535 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1536 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1537 1538 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1539 DPRINTFN(1, "addr %d depth %d port %d speed %d", 1540 dev->ud_addr, dev->ud_depth, dev->ud_powersrc->up_portno, 1541 dev->ud_speed); 1542 1543 if (sc->sc_dying) 1544 return USBD_IOERROR; 1545 1546 /* Root Hub */ 1547 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1548 switch (ed->bEndpointAddress) { 1549 case USB_CONTROL_ENDPOINT: 1550 pipe->up_methods = &roothub_ctrl_methods; 1551 break; 1552 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1553 pipe->up_methods = &xhci_root_intr_methods; 1554 break; 1555 default: 1556 pipe->up_methods = NULL; 1557 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1558 ed->bEndpointAddress, 0, 0, 0); 1559 return USBD_INVAL; 1560 } 1561 return USBD_NORMAL_COMPLETION; 1562 } 1563 1564 switch (xfertype) { 1565 case UE_CONTROL: 1566 pipe->up_methods = &xhci_device_ctrl_methods; 1567 break; 1568 case UE_ISOCHRONOUS: 1569 pipe->up_methods = &xhci_device_isoc_methods; 1570 return USBD_INVAL; 1571 break; 1572 case UE_BULK: 1573 pipe->up_methods = &xhci_device_bulk_methods; 1574 break; 1575 case UE_INTERRUPT: 1576 pipe->up_methods = &xhci_device_intr_methods; 1577 break; 1578 default: 1579 return USBD_IOERROR; 1580 break; 1581 } 1582 1583 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1584 return xhci_configure_endpoint(pipe); 1585 1586 return USBD_NORMAL_COMPLETION; 1587 } 1588 1589 /* 1590 * Closes pipe, called from usbd_kill_pipe via close methods. 1591 * If the endpoint to be closed is ep0, disable_slot. 1592 * Should be called with sc_lock held. 1593 */ 1594 static void 1595 xhci_close_pipe(struct usbd_pipe *pipe) 1596 { 1597 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1598 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1599 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1600 const u_int dci = xhci_ep_get_dci(ed); 1601 struct xhci_trb trb; 1602 uint32_t *cp; 1603 1604 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1605 1606 if (sc->sc_dying) 1607 return; 1608 1609 if (xs == NULL || xs->xs_idx == 0) 1610 /* xs is uninitialized before xhci_init_slot */ 1611 return; 1612 1613 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1614 1615 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1616 KASSERT(mutex_owned(&sc->sc_lock)); 1617 1618 if (pipe->up_dev->ud_depth == 0) 1619 return; 1620 1621 if (dci == XHCI_DCI_EP_CONTROL) { 1622 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1623 xhci_disable_slot(sc, xs->xs_idx); 1624 return; 1625 } 1626 1627 /* 1628 * This may fail in the case that xhci_close_pipe is called after 1629 * xhci_abort_xfer e.g. usbd_kill_pipe. 1630 */ 1631 (void)xhci_stop_endpoint(pipe); 1632 1633 /* 1634 * set appropriate bit to be dropped. 1635 * don't set DC bit to 1, otherwise all endpoints 1636 * would be deconfigured. 1637 */ 1638 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1639 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1640 cp[1] = htole32(0); 1641 1642 /* XXX should be most significant one, not dci? */ 1643 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1644 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1645 1646 /* sync input contexts before they are read from memory */ 1647 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1648 1649 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1650 trb.trb_2 = 0; 1651 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1652 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1653 1654 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1655 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1656 } 1657 1658 /* 1659 * Abort transfer. 1660 * Called with sc_lock held. 1661 * May be called from softintr context. 1662 */ 1663 static void 1664 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1665 { 1666 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1667 1668 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1669 DPRINTFN(4, "xfer %p pipe %p status %d", 1670 xfer, xfer->ux_pipe, status, 0); 1671 1672 KASSERT(mutex_owned(&sc->sc_lock)); 1673 1674 if (sc->sc_dying) { 1675 /* If we're dying, just do the software part. */ 1676 DPRINTFN(4, "dying", 0, 0, 0, 0); 1677 xfer->ux_status = status; /* make software ignore it */ 1678 callout_stop(&xfer->ux_callout); 1679 usb_transfer_complete(xfer); 1680 return; 1681 } 1682 1683 /* XXX need more stuff */ 1684 xfer->ux_status = status; 1685 callout_stop(&xfer->ux_callout); 1686 usb_transfer_complete(xfer); 1687 DPRINTFN(14, "end", 0, 0, 0, 0); 1688 1689 KASSERT(mutex_owned(&sc->sc_lock)); 1690 } 1691 1692 /* 1693 * Recover STALLed endpoint. 1694 * xHCI 1.1 sect 4.10.2.1 1695 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1696 * all transfers on transfer ring. 1697 * These are done in thread context asynchronously. 1698 */ 1699 static void 1700 xhci_clear_endpoint_stall_async_task(void *cookie) 1701 { 1702 struct usbd_xfer * const xfer = cookie; 1703 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1704 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1705 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1706 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1707 1708 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1709 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1710 1711 xhci_reset_endpoint(xfer->ux_pipe); 1712 xhci_set_dequeue(xfer->ux_pipe); 1713 1714 mutex_enter(&sc->sc_lock); 1715 tr->is_halted = false; 1716 usb_transfer_complete(xfer); 1717 mutex_exit(&sc->sc_lock); 1718 DPRINTFN(4, "ends", 0, 0, 0, 0); 1719 } 1720 1721 static usbd_status 1722 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1723 { 1724 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1725 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1726 1727 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1728 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1729 1730 if (sc->sc_dying) { 1731 return USBD_IOERROR; 1732 } 1733 1734 usb_init_task(&xp->xp_async_task, 1735 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1736 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1737 DPRINTFN(4, "ends", 0, 0, 0, 0); 1738 1739 return USBD_NORMAL_COMPLETION; 1740 } 1741 1742 /* Process roothub port status/change events and notify to uhub_intr. */ 1743 static void 1744 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1745 { 1746 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1747 uint8_t *p; 1748 1749 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1750 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1751 port, 0, 0); 1752 1753 if (xfer == NULL) 1754 return; 1755 1756 if (port > sc->sc_maxports) 1757 return; 1758 1759 p = xfer->ux_buf; 1760 memset(p, 0, xfer->ux_length); 1761 p[port/NBBY] |= 1 << (port%NBBY); 1762 xfer->ux_actlen = xfer->ux_length; 1763 xfer->ux_status = USBD_NORMAL_COMPLETION; 1764 usb_transfer_complete(xfer); 1765 } 1766 1767 /* Process Transfer Events */ 1768 static void 1769 xhci_event_transfer(struct xhci_softc * const sc, 1770 const struct xhci_trb * const trb) 1771 { 1772 uint64_t trb_0; 1773 uint32_t trb_2, trb_3; 1774 uint8_t trbcode; 1775 u_int slot, dci; 1776 struct xhci_slot *xs; 1777 struct xhci_ring *xr; 1778 struct xhci_xfer *xx; 1779 struct usbd_xfer *xfer; 1780 usbd_status err; 1781 1782 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1783 1784 trb_0 = le64toh(trb->trb_0); 1785 trb_2 = le32toh(trb->trb_2); 1786 trb_3 = le32toh(trb->trb_3); 1787 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1788 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1789 dci = XHCI_TRB_3_EP_GET(trb_3); 1790 xs = &sc->sc_slots[slot]; 1791 xr = &xs->xs_ep[dci].xe_tr; 1792 1793 /* sanity check */ 1794 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1795 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1796 1797 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1798 /* 1799 * When ED == 0, trb_0 is physical address of the TRB 1800 * that caused this event. (6.4.2.1) 1801 */ 1802 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 1803 1804 /* trb_0 range sanity check */ 1805 if (trb_0 < trbp || 1806 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 1807 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 1808 DPRINTFN(1, "invalid trb_0 0x%"PRIx64" trbp 0x%"PRIx64, 1809 trb_0, trbp, 0, 0); 1810 return; 1811 } 1812 int idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 1813 xx = xr->xr_cookies[idx]; 1814 1815 /* 1816 * If endpoint is stopped between TDs, TRB pointer points at 1817 * next TRB, however, it is not put yet or is a garbage TRB. 1818 * That's why xr_cookies may be NULL or look like broken. 1819 * Note: this ev happens only when hciversion >= 1.0 or 1820 * hciversion == 0.96 and FSE of hcc1 is set. 1821 */ 1822 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1823 DPRINTFN(1, "xx NULL: #%u: cookie %p: code %u trb_0 %" 1824 PRIx64, idx, xx, trbcode, trb_0); 1825 } 1826 } else { 1827 /* When ED != 0, trb_0 is kaddr of struct xhci_xfer. */ 1828 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1829 } 1830 /* XXX this may not happen */ 1831 if (xx == NULL) { 1832 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1833 return; 1834 } 1835 xfer = &xx->xx_xfer; 1836 /* XXX this may happen when detaching */ 1837 if (xfer == NULL) { 1838 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1839 xx, trb_0, 0, 0); 1840 return; 1841 } 1842 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1843 /* XXX I dunno why this happens */ 1844 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1845 1846 if (!xfer->ux_pipe->up_repeat && 1847 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1848 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1849 return; 1850 } 1851 1852 /* 4.11.5.2 Event Data TRB */ 1853 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1854 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1855 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1856 if ((trb_0 & 0x3) == 0x3) { 1857 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1858 } 1859 } 1860 1861 switch (trbcode) { 1862 case XHCI_TRB_ERROR_SHORT_PKT: 1863 case XHCI_TRB_ERROR_SUCCESS: 1864 xfer->ux_actlen = 1865 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1866 err = USBD_NORMAL_COMPLETION; 1867 break; 1868 case XHCI_TRB_ERROR_STALL: 1869 case XHCI_TRB_ERROR_BABBLE: 1870 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1871 xr->is_halted = true; 1872 err = USBD_STALLED; 1873 /* 1874 * Stalled endpoints can be recoverd by issuing 1875 * command TRB TYPE_RESET_EP on xHCI instead of 1876 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1877 * on the endpoint. However, this function may be 1878 * called from softint context (e.g. from umass), 1879 * in that case driver gets KASSERT in cv_timedwait 1880 * in xhci_do_command. 1881 * To avoid this, this runs reset_endpoint and 1882 * usb_transfer_complete in usb task thread 1883 * asynchronously (and then umass issues clear 1884 * UF_ENDPOINT_HALT). 1885 */ 1886 xfer->ux_status = err; 1887 xhci_clear_endpoint_stall_async(xfer); 1888 return; 1889 default: 1890 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1891 err = USBD_IOERROR; 1892 break; 1893 } 1894 xfer->ux_status = err; 1895 1896 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1897 if ((trb_0 & 0x3) == 0x0) { 1898 callout_stop(&xfer->ux_callout); 1899 usb_transfer_complete(xfer); 1900 } 1901 } else { 1902 callout_stop(&xfer->ux_callout); 1903 usb_transfer_complete(xfer); 1904 } 1905 } 1906 1907 /* Process Command complete events */ 1908 static void 1909 xhci_event_cmd(struct xhci_softc * const sc, 1910 const struct xhci_trb * const trb) 1911 { 1912 uint64_t trb_0; 1913 uint32_t trb_2, trb_3; 1914 1915 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1916 1917 trb_0 = le64toh(trb->trb_0); 1918 trb_2 = le32toh(trb->trb_2); 1919 trb_3 = le32toh(trb->trb_3); 1920 1921 if (trb_0 == sc->sc_command_addr) { 1922 sc->sc_result_trb.trb_0 = trb_0; 1923 sc->sc_result_trb.trb_2 = trb_2; 1924 sc->sc_result_trb.trb_3 = trb_3; 1925 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1926 XHCI_TRB_ERROR_SUCCESS) { 1927 DPRINTFN(1, "command completion " 1928 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1929 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1930 } 1931 cv_signal(&sc->sc_command_cv); 1932 } else { 1933 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 1934 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1935 trb_2, trb_3); 1936 } 1937 } 1938 1939 /* 1940 * Process events. 1941 * called from xhci_softintr 1942 */ 1943 static void 1944 xhci_handle_event(struct xhci_softc * const sc, 1945 const struct xhci_trb * const trb) 1946 { 1947 uint64_t trb_0; 1948 uint32_t trb_2, trb_3; 1949 1950 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1951 1952 trb_0 = le64toh(trb->trb_0); 1953 trb_2 = le32toh(trb->trb_2); 1954 trb_3 = le32toh(trb->trb_3); 1955 1956 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1957 trb, trb_0, trb_2, trb_3); 1958 1959 /* 1960 * 4.11.3.1, 6.4.2.1 1961 * TRB Pointer is invalid for these completion codes. 1962 */ 1963 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 1964 case XHCI_TRB_ERROR_RING_UNDERRUN: 1965 case XHCI_TRB_ERROR_RING_OVERRUN: 1966 case XHCI_TRB_ERROR_VF_RING_FULL: 1967 return; 1968 default: 1969 if (trb_0 == 0) { 1970 return; 1971 } 1972 break; 1973 } 1974 1975 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 1976 case XHCI_TRB_EVENT_TRANSFER: 1977 xhci_event_transfer(sc, trb); 1978 break; 1979 case XHCI_TRB_EVENT_CMD_COMPLETE: 1980 xhci_event_cmd(sc, trb); 1981 break; 1982 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1983 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1984 break; 1985 default: 1986 break; 1987 } 1988 } 1989 1990 static void 1991 xhci_softintr(void *v) 1992 { 1993 struct usbd_bus * const bus = v; 1994 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1995 struct xhci_ring * const er = &sc->sc_er; 1996 struct xhci_trb *trb; 1997 int i, j, k; 1998 1999 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2000 2001 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2002 2003 i = er->xr_ep; 2004 j = er->xr_cs; 2005 2006 DPRINTFN(16, "xr_ep %d xr_cs %d", i, j, 0, 0); 2007 2008 while (1) { 2009 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2010 BUS_DMASYNC_POSTREAD); 2011 trb = &er->xr_trb[i]; 2012 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2013 2014 if (j != k) 2015 break; 2016 2017 xhci_handle_event(sc, trb); 2018 2019 i++; 2020 if (i == XHCI_EVENT_RING_TRBS) { 2021 i = 0; 2022 j ^= 1; 2023 } 2024 } 2025 2026 er->xr_ep = i; 2027 er->xr_cs = j; 2028 2029 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2030 XHCI_ERDP_LO_BUSY); 2031 2032 DPRINTFN(16, "ends", 0, 0, 0, 0); 2033 2034 return; 2035 } 2036 2037 static void 2038 xhci_poll(struct usbd_bus *bus) 2039 { 2040 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2041 2042 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2043 2044 mutex_spin_enter(&sc->sc_intr_lock); 2045 xhci_intr1(sc); 2046 mutex_spin_exit(&sc->sc_intr_lock); 2047 2048 return; 2049 } 2050 2051 static struct usbd_xfer * 2052 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2053 { 2054 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2055 struct usbd_xfer *xfer; 2056 2057 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2058 2059 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 2060 if (xfer != NULL) { 2061 memset(xfer, 0, sizeof(struct xhci_xfer)); 2062 #ifdef DIAGNOSTIC 2063 xfer->ux_state = XFER_BUSY; 2064 #endif 2065 } 2066 2067 return xfer; 2068 } 2069 2070 static void 2071 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2072 { 2073 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2074 2075 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2076 2077 #ifdef DIAGNOSTIC 2078 if (xfer->ux_state != XFER_BUSY) { 2079 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 2080 xfer, xfer->ux_state, 0, 0); 2081 } 2082 xfer->ux_state = XFER_FREE; 2083 #endif 2084 pool_cache_put(sc->sc_xferpool, xfer); 2085 } 2086 2087 static void 2088 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2089 { 2090 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2091 2092 *lock = &sc->sc_lock; 2093 } 2094 2095 extern uint32_t usb_cookie_no; 2096 2097 /* 2098 * Called if uhub_explore finds a new device (via usbd_new_device). 2099 * Allocate and construct dev structure of default endpoint (ep0). 2100 * Determine initial MaxPacketSize (mps) by speed. 2101 * Determine route string and roothub port for slot of dev. 2102 * Allocate pipe of ep0. 2103 * Enable and initialize slot and Set Address. 2104 * Read device descriptor. 2105 * Register this device. 2106 */ 2107 static usbd_status 2108 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2109 int speed, int port, struct usbd_port *up) 2110 { 2111 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2112 struct usbd_device *dev; 2113 usbd_status err; 2114 usb_device_descriptor_t *dd; 2115 struct usbd_device *hub; 2116 struct usbd_device *adev; 2117 int rhport = 0; 2118 struct xhci_slot *xs; 2119 uint32_t *cp; 2120 uint32_t route = 0; 2121 uint8_t slot = 0; 2122 uint8_t addr; 2123 2124 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2125 DPRINTFN(4, "port=%d depth=%d speed=%d upport %d", 2126 port, depth, speed, up->up_portno); 2127 2128 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2129 if (dev == NULL) 2130 return USBD_NOMEM; 2131 2132 dev->ud_bus = bus; 2133 2134 /* Set up default endpoint handle. */ 2135 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2136 2137 /* Set up default endpoint descriptor. */ 2138 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2139 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2140 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2141 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2142 /* 4.3, 4.8.2.1 */ 2143 switch (speed) { 2144 case USB_SPEED_SUPER: 2145 case USB_SPEED_SUPER_PLUS: 2146 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2147 break; 2148 case USB_SPEED_FULL: 2149 /* XXX using 64 as initial mps of ep0 in FS */ 2150 case USB_SPEED_HIGH: 2151 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2152 break; 2153 case USB_SPEED_LOW: 2154 default: 2155 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2156 break; 2157 } 2158 dev->ud_ep0desc.bInterval = 0; 2159 2160 /* doesn't matter, just don't let it uninitialized */ 2161 dev->ud_ep0.ue_toggle = 0; 2162 2163 DPRINTFN(4, "up %p portno %d", up, up->up_portno, 0, 0); 2164 2165 dev->ud_quirks = &usbd_no_quirk; 2166 dev->ud_addr = 0; 2167 dev->ud_ddesc.bMaxPacketSize = 0; 2168 dev->ud_depth = depth; 2169 dev->ud_powersrc = up; 2170 dev->ud_myhub = up->up_parent; 2171 2172 up->up_dev = dev; 2173 2174 /* Locate root hub port */ 2175 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2176 uint32_t dep; 2177 2178 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2179 hub, hub->ud_depth, hub->ud_powersrc, 2180 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2181 2182 if (hub->ud_powersrc == NULL) 2183 break; 2184 dep = hub->ud_depth; 2185 if (dep == 0) 2186 break; 2187 rhport = hub->ud_powersrc->up_portno; 2188 if (dep > USB_HUB_MAX_DEPTH) 2189 continue; 2190 2191 route |= 2192 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2193 << ((dep - 1) * 4); 2194 } 2195 route = route >> 4; 2196 DPRINTFN(4, "rhport %d Route %05x hub %p", rhport, route, hub, 0); 2197 2198 /* Locate port on upstream high speed hub */ 2199 for (adev = dev, hub = up->up_parent; 2200 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2201 adev = hub, hub = hub->ud_myhub) 2202 ; 2203 if (hub) { 2204 int p; 2205 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2206 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2207 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2208 goto found; 2209 } 2210 } 2211 panic("xhci_new_device: cannot find HS port"); 2212 found: 2213 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2214 } else { 2215 dev->ud_myhsport = NULL; 2216 } 2217 2218 dev->ud_speed = speed; 2219 dev->ud_langid = USBD_NOLANG; 2220 dev->ud_cookie.cookie = ++usb_cookie_no; 2221 2222 /* Establish the default pipe. */ 2223 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2224 &dev->ud_pipe0); 2225 if (err) { 2226 goto bad; 2227 } 2228 2229 dd = &dev->ud_ddesc; 2230 2231 if ((depth == 0) && (port == 0)) { 2232 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2233 bus->ub_devices[dev->ud_addr] = dev; 2234 err = usbd_get_initial_ddesc(dev, dd); 2235 if (err) 2236 goto bad; 2237 err = usbd_reload_device_desc(dev); 2238 if (err) 2239 goto bad; 2240 } else { 2241 err = xhci_enable_slot(sc, &slot); 2242 if (err) 2243 goto bad; 2244 xs = &sc->sc_slots[slot]; 2245 dev->ud_hcpriv = xs; 2246 err = xhci_init_slot(dev, slot, route, rhport); 2247 if (err) { 2248 dev->ud_hcpriv = NULL; 2249 /* 2250 * We have to disable_slot here because 2251 * xs->xs_idx == 0 when xhci_init_slot fails, 2252 * in that case usbd_remove_dev won't work. 2253 */ 2254 mutex_enter(&sc->sc_lock); 2255 xhci_disable_slot(sc, slot); 2256 mutex_exit(&sc->sc_lock); 2257 goto bad; 2258 } 2259 2260 /* Allow device time to set new address */ 2261 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2262 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2263 //hexdump("slot context", cp, sc->sc_ctxsz); 2264 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2265 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2266 /* XXX ensure we know when the hardware does something 2267 we can't yet cope with */ 2268 KASSERT(addr >= 1 && addr <= 127); 2269 dev->ud_addr = addr; 2270 /* XXX dev->ud_addr not necessarily unique on bus */ 2271 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2272 bus->ub_devices[dev->ud_addr] = dev; 2273 2274 err = usbd_get_initial_ddesc(dev, dd); 2275 if (err) 2276 goto bad; 2277 /* 4.8.2.1 */ 2278 if (USB_IS_SS(speed)) { 2279 if (dd->bMaxPacketSize != 9) { 2280 printf("%s: invalid mps 2^%u for SS ep0," 2281 " using 512\n", 2282 device_xname(sc->sc_dev), 2283 dd->bMaxPacketSize); 2284 dd->bMaxPacketSize = 9; 2285 } 2286 USETW(dev->ud_ep0desc.wMaxPacketSize, 2287 (1 << dd->bMaxPacketSize)); 2288 } else 2289 USETW(dev->ud_ep0desc.wMaxPacketSize, 2290 dd->bMaxPacketSize); 2291 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2292 xhci_update_ep0_mps(sc, xs, 2293 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2294 err = usbd_reload_device_desc(dev); 2295 if (err) 2296 goto bad; 2297 2298 #if 0 2299 /* Re-establish the default pipe with the new MPS. */ 2300 /* In xhci this is done by xhci_update_ep0_mps. */ 2301 usbd_kill_pipe(dev->ud_pipe0); 2302 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2303 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2304 #endif 2305 } 2306 2307 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2308 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2309 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2310 dd->bDeviceClass, dd->bDeviceSubClass, 2311 dd->bDeviceProtocol, 0); 2312 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2313 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2314 dev->ud_speed); 2315 2316 usbd_get_device_strings(dev); 2317 2318 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2319 2320 if ((depth == 0) && (port == 0)) { 2321 usbd_attach_roothub(parent, dev); 2322 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2323 return USBD_NORMAL_COMPLETION; 2324 } 2325 2326 2327 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2328 bad: 2329 if (err != USBD_NORMAL_COMPLETION) { 2330 usbd_remove_device(dev, up); 2331 } 2332 2333 return err; 2334 } 2335 2336 static usbd_status 2337 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2338 size_t ntrb, size_t align) 2339 { 2340 usbd_status err; 2341 size_t size = ntrb * XHCI_TRB_SIZE; 2342 2343 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2344 2345 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2346 if (err) 2347 return err; 2348 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2349 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2350 xr->xr_trb = xhci_ring_trbv(xr, 0); 2351 xr->xr_ntrb = ntrb; 2352 xr->xr_ep = 0; 2353 xr->xr_cs = 1; 2354 memset(xr->xr_trb, 0, size); 2355 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 2356 xr->is_halted = false; 2357 2358 return USBD_NORMAL_COMPLETION; 2359 } 2360 2361 static void 2362 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2363 { 2364 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2365 mutex_destroy(&xr->xr_lock); 2366 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2367 } 2368 2369 static void 2370 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2371 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2372 { 2373 size_t i; 2374 u_int ri; 2375 u_int cs; 2376 uint64_t parameter; 2377 uint32_t status; 2378 uint32_t control; 2379 2380 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2381 2382 KASSERT(ntrbs <= XHCI_XFER_NTRB); 2383 for (i = 0; i < ntrbs; i++) { 2384 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2385 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2386 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2387 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2388 XHCI_TRB_TYPE_LINK); 2389 } 2390 2391 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2392 2393 ri = xr->xr_ep; 2394 cs = xr->xr_cs; 2395 2396 /* 2397 * Although the xhci hardware can do scatter/gather dma from 2398 * arbitrary sized buffers, there is a non-obvious restriction 2399 * that a LINK trb is only allowed at the end of a burst of 2400 * transfers - which might be 16kB. 2401 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2402 * The simple solution is not to allow a LINK trb in the middle 2403 * of anything - as here. 2404 * XXX: (dsl) There are xhci controllers out there (eg some made by 2405 * ASMedia) that seem to lock up if they process a LINK trb but 2406 * cannot process the linked-to trb yet. 2407 * The code should write the 'cycle' bit on the link trb AFTER 2408 * adding the other trb. 2409 */ 2410 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2411 parameter = xhci_ring_trbp(xr, 0); 2412 status = 0; 2413 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2414 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2415 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2416 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2417 BUS_DMASYNC_PREWRITE); 2418 xr->xr_cookies[ri] = NULL; 2419 xr->xr_ep = 0; 2420 xr->xr_cs ^= 1; 2421 ri = xr->xr_ep; 2422 cs = xr->xr_cs; 2423 } 2424 2425 ri++; 2426 2427 /* Write any subsequent TRB first */ 2428 for (i = 1; i < ntrbs; i++) { 2429 parameter = trbs[i].trb_0; 2430 status = trbs[i].trb_2; 2431 control = trbs[i].trb_3; 2432 2433 if (cs) { 2434 control |= XHCI_TRB_3_CYCLE_BIT; 2435 } else { 2436 control &= ~XHCI_TRB_3_CYCLE_BIT; 2437 } 2438 2439 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2440 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2441 BUS_DMASYNC_PREWRITE); 2442 xr->xr_cookies[ri] = cookie; 2443 ri++; 2444 } 2445 2446 /* Write the first TRB last */ 2447 i = 0; 2448 parameter = trbs[i].trb_0; 2449 status = trbs[i].trb_2; 2450 control = trbs[i].trb_3; 2451 2452 if (xr->xr_cs) { 2453 control |= XHCI_TRB_3_CYCLE_BIT; 2454 } else { 2455 control &= ~XHCI_TRB_3_CYCLE_BIT; 2456 } 2457 2458 xhci_trb_put(&xr->xr_trb[xr->xr_ep], parameter, status, control); 2459 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2460 BUS_DMASYNC_PREWRITE); 2461 xr->xr_cookies[xr->xr_ep] = cookie; 2462 2463 xr->xr_ep = ri; 2464 xr->xr_cs = cs; 2465 2466 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2467 } 2468 2469 /* 2470 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2471 * Command completion is notified by cv_signal from xhci_handle_event 2472 * (called from interrupt from xHCI), or timed-out. 2473 * Command validation is performed in xhci_handle_event by checking if 2474 * trb_0 in CMD_COMPLETE TRB and sc->sc_command_addr are identical. 2475 */ 2476 static usbd_status 2477 xhci_do_command_locked(struct xhci_softc * const sc, struct xhci_trb * const trb, 2478 int timeout) 2479 { 2480 struct xhci_ring * const cr = &sc->sc_cr; 2481 usbd_status err; 2482 2483 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2484 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2485 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2486 2487 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2488 KASSERT(mutex_owned(&sc->sc_lock)); 2489 2490 /* XXX KASSERT may fire when cv_timedwait unlocks sc_lock */ 2491 KASSERT(sc->sc_command_addr == 0); 2492 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2493 2494 mutex_enter(&cr->xr_lock); 2495 xhci_ring_put(sc, cr, NULL, trb, 1); 2496 mutex_exit(&cr->xr_lock); 2497 2498 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2499 2500 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2501 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2502 err = USBD_TIMEOUT; 2503 goto timedout; 2504 } 2505 2506 trb->trb_0 = sc->sc_result_trb.trb_0; 2507 trb->trb_2 = sc->sc_result_trb.trb_2; 2508 trb->trb_3 = sc->sc_result_trb.trb_3; 2509 2510 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2511 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2512 2513 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2514 case XHCI_TRB_ERROR_SUCCESS: 2515 err = USBD_NORMAL_COMPLETION; 2516 break; 2517 default: 2518 case 192 ... 223: 2519 err = USBD_IOERROR; 2520 break; 2521 case 224 ... 255: 2522 err = USBD_NORMAL_COMPLETION; 2523 break; 2524 } 2525 2526 timedout: 2527 sc->sc_command_addr = 0; 2528 return err; 2529 } 2530 2531 static usbd_status 2532 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2533 int timeout) 2534 { 2535 2536 mutex_enter(&sc->sc_lock); 2537 int ret = xhci_do_command_locked(sc, trb, timeout); 2538 mutex_exit(&sc->sc_lock); 2539 2540 return ret; 2541 } 2542 2543 static usbd_status 2544 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2545 { 2546 struct xhci_trb trb; 2547 usbd_status err; 2548 2549 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2550 2551 trb.trb_0 = 0; 2552 trb.trb_2 = 0; 2553 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2554 2555 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2556 if (err != USBD_NORMAL_COMPLETION) { 2557 return err; 2558 } 2559 2560 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2561 2562 return err; 2563 } 2564 2565 /* 2566 * Deallocate DMA buffer and ring buffer, and disable_slot. 2567 * Should be called with sc_lock held. 2568 */ 2569 static usbd_status 2570 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2571 { 2572 struct xhci_trb trb; 2573 struct xhci_slot *xs; 2574 usbd_status err; 2575 2576 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2577 2578 if (sc->sc_dying) 2579 return USBD_IOERROR; 2580 2581 trb.trb_0 = 0; 2582 trb.trb_2 = 0; 2583 trb.trb_3 = htole32( 2584 XHCI_TRB_3_SLOT_SET(slot) | 2585 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2586 2587 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2588 2589 if (!err) { 2590 xs = &sc->sc_slots[slot]; 2591 if (xs->xs_idx != 0) { 2592 for (int i = XHCI_DCI_SLOT + 1; i < 32; i++) { 2593 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2594 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2595 } 2596 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2597 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2598 xhci_set_dcba(sc, 0, slot); 2599 memset(xs, 0, sizeof(*xs)); 2600 } 2601 } 2602 2603 return err; 2604 } 2605 2606 /* 2607 * Change slot state. 2608 * bsr=0: ENABLED -> ADDRESSED 2609 * bsr=1: ENABLED -> DEFAULT 2610 * see xHCI 1.1 4.5.3, 3.3.4 2611 */ 2612 static usbd_status 2613 xhci_address_device(struct xhci_softc * const sc, 2614 uint64_t icp, uint8_t slot_id, bool bsr) 2615 { 2616 struct xhci_trb trb; 2617 usbd_status err; 2618 2619 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2620 2621 trb.trb_0 = icp; 2622 trb.trb_2 = 0; 2623 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2624 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2625 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2626 2627 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2628 2629 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2630 err = USBD_NO_ADDR; 2631 2632 return err; 2633 } 2634 2635 static usbd_status 2636 xhci_update_ep0_mps(struct xhci_softc * const sc, 2637 struct xhci_slot * const xs, u_int mps) 2638 { 2639 struct xhci_trb trb; 2640 usbd_status err; 2641 uint32_t * cp; 2642 2643 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2644 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2645 2646 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2647 cp[0] = htole32(0); 2648 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2649 2650 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2651 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2652 2653 /* sync input contexts before they are read from memory */ 2654 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2655 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2656 sc->sc_ctxsz * 4); 2657 2658 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2659 trb.trb_2 = 0; 2660 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2661 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2662 2663 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2664 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2665 return err; 2666 } 2667 2668 static void 2669 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2670 { 2671 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2672 2673 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2674 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2675 &dcbaa[si], dcba, si, 0); 2676 2677 dcbaa[si] = htole64(dcba); 2678 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2679 BUS_DMASYNC_PREWRITE); 2680 } 2681 2682 /* 2683 * Allocate DMA buffer and ring buffer for specified slot 2684 * and set Device Context Base Address 2685 * and issue Set Address device command. 2686 */ 2687 static usbd_status 2688 xhci_init_slot(struct usbd_device *dev, uint32_t slot, uint32_t route, int rhport) 2689 { 2690 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2691 struct xhci_slot *xs; 2692 usbd_status err; 2693 u_int dci; 2694 uint32_t *cp; 2695 uint32_t mps = UGETW(dev->ud_ep0desc.wMaxPacketSize); 2696 2697 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2698 DPRINTFN(4, "slot %u speed %d route %05x rhport %d", 2699 slot, dev->ud_speed, route, rhport); 2700 2701 xs = &sc->sc_slots[slot]; 2702 2703 /* allocate contexts */ 2704 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2705 &xs->xs_dc_dma); 2706 if (err) 2707 return err; 2708 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2709 2710 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2711 &xs->xs_ic_dma); 2712 if (err) 2713 goto bad1; 2714 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2715 2716 for (dci = 0; dci < 32; dci++) { 2717 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2718 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2719 if (dci == XHCI_DCI_SLOT) 2720 continue; 2721 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2722 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2723 if (err) { 2724 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2725 goto bad2; 2726 } 2727 } 2728 2729 /* set up initial input control context */ 2730 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2731 cp[0] = htole32(0); 2732 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 2733 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2734 2735 /* set up input slot context */ 2736 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2737 xhci_setup_sctx(dev, cp); 2738 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(1)); 2739 cp[0] |= htole32(XHCI_SCTX_0_ROUTE_SET(route)); 2740 cp[1] |= htole32(XHCI_SCTX_1_RH_PORT_SET(rhport)); 2741 2742 /* set up input EP0 context */ 2743 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2744 cp[0] = htole32(0); 2745 cp[1] = htole32( 2746 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 2747 XHCI_EPCTX_1_EPTYPE_SET(4) | 2748 XHCI_EPCTX_1_CERR_SET(3) 2749 ); 2750 /* can't use xhci_ep_get_dci() yet? */ 2751 *(uint64_t *)(&cp[2]) = htole64( 2752 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 2753 XHCI_EPCTX_2_DCS_SET(1)); 2754 cp[4] = htole32( 2755 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 2756 ); 2757 2758 /* sync input contexts before they are read from memory */ 2759 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2760 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2761 sc->sc_ctxsz * 3); 2762 2763 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2764 2765 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 2766 false); 2767 2768 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2769 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2770 sc->sc_ctxsz * 2); 2771 2772 bad2: 2773 if (err == USBD_NORMAL_COMPLETION) { 2774 xs->xs_idx = slot; 2775 } else { 2776 for (int i = 1; i < dci; i++) { 2777 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2778 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2779 } 2780 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2781 bad1: 2782 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2783 xs->xs_idx = 0; 2784 } 2785 2786 return err; 2787 } 2788 2789 /* ----- */ 2790 2791 static void 2792 xhci_noop(struct usbd_pipe *pipe) 2793 { 2794 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2795 } 2796 2797 /* 2798 * Process root hub request. 2799 */ 2800 static int 2801 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2802 void *buf, int buflen) 2803 { 2804 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2805 usb_port_status_t ps; 2806 int l, totlen = 0; 2807 uint16_t len, value, index; 2808 int port, i; 2809 uint32_t v; 2810 2811 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2812 2813 if (sc->sc_dying) 2814 return -1; 2815 2816 len = UGETW(req->wLength); 2817 value = UGETW(req->wValue); 2818 index = UGETW(req->wIndex); 2819 2820 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 2821 req->bmRequestType | (req->bRequest << 8), value, index, len); 2822 2823 #define C(x,y) ((x) | ((y) << 8)) 2824 switch (C(req->bRequest, req->bmRequestType)) { 2825 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2826 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 2827 if (len == 0) 2828 break; 2829 switch (value) { 2830 case C(0, UDESC_DEVICE): { 2831 usb_device_descriptor_t devd; 2832 totlen = min(buflen, sizeof(devd)); 2833 memcpy(&devd, buf, totlen); 2834 USETW(devd.idVendor, sc->sc_id_vendor); 2835 memcpy(buf, &devd, totlen); 2836 break; 2837 } 2838 #define sd ((usb_string_descriptor_t *)buf) 2839 case C(1, UDESC_STRING): 2840 /* Vendor */ 2841 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2842 break; 2843 case C(2, UDESC_STRING): 2844 /* Product */ 2845 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 2846 break; 2847 #undef sd 2848 default: 2849 /* default from usbroothub */ 2850 return buflen; 2851 } 2852 break; 2853 2854 /* Hub requests */ 2855 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2856 break; 2857 /* Clear Port Feature request */ 2858 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2859 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2860 index, value, 0, 0); 2861 if (index < 1 || index > sc->sc_maxports) { 2862 return -1; 2863 } 2864 port = XHCI_PORTSC(index); 2865 v = xhci_op_read_4(sc, port); 2866 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2867 v &= ~XHCI_PS_CLEAR; 2868 switch (value) { 2869 case UHF_PORT_ENABLE: 2870 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 2871 break; 2872 case UHF_PORT_SUSPEND: 2873 return -1; 2874 case UHF_PORT_POWER: 2875 break; 2876 case UHF_PORT_TEST: 2877 case UHF_PORT_INDICATOR: 2878 return -1; 2879 case UHF_C_PORT_CONNECTION: 2880 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2881 break; 2882 case UHF_C_PORT_ENABLE: 2883 case UHF_C_PORT_SUSPEND: 2884 case UHF_C_PORT_OVER_CURRENT: 2885 return -1; 2886 case UHF_C_BH_PORT_RESET: 2887 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 2888 break; 2889 case UHF_C_PORT_RESET: 2890 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2891 break; 2892 case UHF_C_PORT_LINK_STATE: 2893 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 2894 break; 2895 case UHF_C_PORT_CONFIG_ERROR: 2896 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 2897 break; 2898 default: 2899 return -1; 2900 } 2901 break; 2902 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2903 if (len == 0) 2904 break; 2905 if ((value & 0xff) != 0) { 2906 return -1; 2907 } 2908 usb_hub_descriptor_t hubd; 2909 2910 totlen = min(buflen, sizeof(hubd)); 2911 memcpy(&hubd, buf, totlen); 2912 hubd.bNbrPorts = sc->sc_maxports; 2913 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2914 hubd.bPwrOn2PwrGood = 200; 2915 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 2916 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2917 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2918 totlen = min(totlen, hubd.bDescLength); 2919 memcpy(buf, &hubd, totlen); 2920 break; 2921 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2922 if (len != 4) { 2923 return -1; 2924 } 2925 memset(buf, 0, len); /* ? XXX */ 2926 totlen = len; 2927 break; 2928 /* Get Port Status request */ 2929 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2930 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2931 if (index < 1 || index > sc->sc_maxports) { 2932 return -1; 2933 } 2934 if (len != 4) { 2935 return -1; 2936 } 2937 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 2938 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 2939 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 2940 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2941 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2942 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2943 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 2944 if (v & XHCI_PS_PR) i |= UPS_RESET; 2945 if (v & XHCI_PS_PP) { 2946 if (i & UPS_OTHER_SPEED) 2947 i |= UPS_PORT_POWER_SS; 2948 else 2949 i |= UPS_PORT_POWER; 2950 } 2951 if (i & UPS_OTHER_SPEED) 2952 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 2953 if (sc->sc_vendor_port_status) 2954 i = sc->sc_vendor_port_status(sc, v, i); 2955 USETW(ps.wPortStatus, i); 2956 i = 0; 2957 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2958 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2959 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2960 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2961 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 2962 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 2963 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 2964 USETW(ps.wPortChange, i); 2965 totlen = min(len, sizeof(ps)); 2966 memcpy(buf, &ps, totlen); 2967 break; 2968 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2969 return -1; 2970 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 2971 break; 2972 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2973 break; 2974 /* Set Port Feature request */ 2975 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 2976 int optval = (index >> 8) & 0xff; 2977 index &= 0xff; 2978 if (index < 1 || index > sc->sc_maxports) { 2979 return -1; 2980 } 2981 port = XHCI_PORTSC(index); 2982 v = xhci_op_read_4(sc, port); 2983 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2984 v &= ~XHCI_PS_CLEAR; 2985 switch (value) { 2986 case UHF_PORT_ENABLE: 2987 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 2988 break; 2989 case UHF_PORT_SUSPEND: 2990 /* XXX suspend */ 2991 break; 2992 case UHF_PORT_RESET: 2993 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 2994 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 2995 /* Wait for reset to complete. */ 2996 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2997 if (sc->sc_dying) { 2998 return -1; 2999 } 3000 v = xhci_op_read_4(sc, port); 3001 if (v & XHCI_PS_PR) { 3002 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3003 usb_delay_ms(&sc->sc_bus, 10); 3004 /* XXX */ 3005 } 3006 break; 3007 case UHF_PORT_POWER: 3008 /* XXX power control */ 3009 break; 3010 /* XXX more */ 3011 case UHF_C_PORT_RESET: 3012 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3013 break; 3014 case UHF_PORT_U1_TIMEOUT: 3015 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3016 return -1; 3017 } 3018 port = XHCI_PORTPMSC(index); 3019 v = xhci_op_read_4(sc, port); 3020 v &= ~XHCI_PM3_U1TO_SET(0xff); 3021 v |= XHCI_PM3_U1TO_SET(optval); 3022 xhci_op_write_4(sc, port, v); 3023 break; 3024 case UHF_PORT_U2_TIMEOUT: 3025 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3026 return -1; 3027 } 3028 port = XHCI_PORTPMSC(index); 3029 v = xhci_op_read_4(sc, port); 3030 v &= ~XHCI_PM3_U2TO_SET(0xff); 3031 v |= XHCI_PM3_U2TO_SET(optval); 3032 xhci_op_write_4(sc, port, v); 3033 break; 3034 default: 3035 return -1; 3036 } 3037 } 3038 break; 3039 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3040 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3041 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3042 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3043 break; 3044 default: 3045 /* default from usbroothub */ 3046 return buflen; 3047 } 3048 3049 return totlen; 3050 } 3051 3052 /* root hub interrupt */ 3053 3054 static usbd_status 3055 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3056 { 3057 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3058 usbd_status err; 3059 3060 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3061 3062 /* Insert last in queue. */ 3063 mutex_enter(&sc->sc_lock); 3064 err = usb_insert_transfer(xfer); 3065 mutex_exit(&sc->sc_lock); 3066 if (err) 3067 return err; 3068 3069 /* Pipe isn't running, start first */ 3070 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3071 } 3072 3073 /* Wait for roothub port status/change */ 3074 static usbd_status 3075 xhci_root_intr_start(struct usbd_xfer *xfer) 3076 { 3077 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3078 3079 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3080 3081 if (sc->sc_dying) 3082 return USBD_IOERROR; 3083 3084 mutex_enter(&sc->sc_lock); 3085 sc->sc_intrxfer = xfer; 3086 mutex_exit(&sc->sc_lock); 3087 3088 return USBD_IN_PROGRESS; 3089 } 3090 3091 static void 3092 xhci_root_intr_abort(struct usbd_xfer *xfer) 3093 { 3094 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3095 3096 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3097 3098 KASSERT(mutex_owned(&sc->sc_lock)); 3099 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3100 3101 sc->sc_intrxfer = NULL; 3102 3103 xfer->ux_status = USBD_CANCELLED; 3104 usb_transfer_complete(xfer); 3105 } 3106 3107 static void 3108 xhci_root_intr_close(struct usbd_pipe *pipe) 3109 { 3110 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3111 3112 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3113 3114 KASSERT(mutex_owned(&sc->sc_lock)); 3115 3116 sc->sc_intrxfer = NULL; 3117 } 3118 3119 static void 3120 xhci_root_intr_done(struct usbd_xfer *xfer) 3121 { 3122 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3123 3124 } 3125 3126 /* -------------- */ 3127 /* device control */ 3128 3129 static usbd_status 3130 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3131 { 3132 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3133 usbd_status err; 3134 3135 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3136 3137 /* Insert last in queue. */ 3138 mutex_enter(&sc->sc_lock); 3139 err = usb_insert_transfer(xfer); 3140 mutex_exit(&sc->sc_lock); 3141 if (err) 3142 return err; 3143 3144 /* Pipe isn't running, start first */ 3145 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3146 } 3147 3148 static usbd_status 3149 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3150 { 3151 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3152 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3153 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3154 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3155 struct xhci_xfer * const xx = (void *)xfer; 3156 usb_device_request_t * const req = &xfer->ux_request; 3157 const int isread = usbd_xfer_isread(xfer); 3158 const uint32_t len = UGETW(req->wLength); 3159 usb_dma_t * const dma = &xfer->ux_dmabuf; 3160 uint64_t parameter; 3161 uint32_t status; 3162 uint32_t control; 3163 u_int i; 3164 3165 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3166 DPRINTFN(12, "req: %04x %04x %04x %04x", 3167 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3168 UGETW(req->wIndex), UGETW(req->wLength)); 3169 3170 #if 0 /* event handler does this */ 3171 /* XXX */ 3172 if (tr->is_halted) { 3173 DPRINTFN(1, "ctrl xfer %p halted: slot %u dci %u", 3174 xfer, xs->xs_idx, dci, 0); 3175 xhci_reset_endpoint(xfer->ux_pipe); 3176 tr->is_halted = false; 3177 xhci_set_dequeue(xfer->ux_pipe); 3178 } 3179 #endif 3180 3181 /* we rely on the bottom bits for extra info */ 3182 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 3183 3184 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3185 3186 i = 0; 3187 3188 /* setup phase */ 3189 memcpy(¶meter, req, sizeof(*req)); 3190 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3191 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3192 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3193 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3194 XHCI_TRB_3_IDT_BIT; 3195 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3196 3197 if (len != 0) { 3198 /* data phase */ 3199 parameter = DMAADDR(dma, 0); 3200 KASSERT(len <= 0x10000); 3201 status = XHCI_TRB_2_IRQ_SET(0) | 3202 XHCI_TRB_2_TDSZ_SET(1) | 3203 XHCI_TRB_2_BYTES_SET(len); 3204 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3205 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3206 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3207 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3208 3209 parameter = (uintptr_t)xfer | 0x3; 3210 status = XHCI_TRB_2_IRQ_SET(0); 3211 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3212 XHCI_TRB_3_IOC_BIT; 3213 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3214 } 3215 3216 parameter = 0; 3217 status = XHCI_TRB_2_IRQ_SET(0); 3218 /* the status stage has inverted direction */ 3219 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3220 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3221 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3222 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3223 3224 parameter = (uintptr_t)xfer | 0x0; 3225 status = XHCI_TRB_2_IRQ_SET(0); 3226 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3227 XHCI_TRB_3_IOC_BIT; 3228 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3229 3230 mutex_enter(&tr->xr_lock); 3231 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3232 mutex_exit(&tr->xr_lock); 3233 3234 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3235 3236 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3237 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3238 xhci_timeout, xfer); 3239 } 3240 3241 if (sc->sc_bus.ub_usepolling) { 3242 DPRINTFN(1, "polling", 0, 0, 0, 0); 3243 //xhci_waitintr(sc, xfer); 3244 } 3245 3246 return USBD_IN_PROGRESS; 3247 } 3248 3249 static void 3250 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3251 { 3252 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3253 usb_device_request_t *req = &xfer->ux_request; 3254 int len = UGETW(req->wLength); 3255 int rd = req->bmRequestType & UT_READ; 3256 3257 if (len) 3258 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3259 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3260 } 3261 3262 static void 3263 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3264 { 3265 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3266 3267 xhci_abort_xfer(xfer, USBD_CANCELLED); 3268 } 3269 3270 static void 3271 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3272 { 3273 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3274 3275 xhci_close_pipe(pipe); 3276 } 3277 3278 /* ------------------ */ 3279 /* device isochronous */ 3280 3281 /* ----------- */ 3282 /* device bulk */ 3283 3284 static usbd_status 3285 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3286 { 3287 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3288 usbd_status err; 3289 3290 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3291 3292 /* Insert last in queue. */ 3293 mutex_enter(&sc->sc_lock); 3294 err = usb_insert_transfer(xfer); 3295 mutex_exit(&sc->sc_lock); 3296 if (err) 3297 return err; 3298 3299 /* 3300 * Pipe isn't running (otherwise err would be USBD_INPROG), 3301 * so start it first. 3302 */ 3303 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3304 } 3305 3306 static usbd_status 3307 xhci_device_bulk_start(struct usbd_xfer *xfer) 3308 { 3309 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3310 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3311 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3312 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3313 struct xhci_xfer * const xx = (void *)xfer; 3314 const uint32_t len = xfer->ux_length; 3315 usb_dma_t * const dma = &xfer->ux_dmabuf; 3316 uint64_t parameter; 3317 uint32_t status; 3318 uint32_t control; 3319 u_int i = 0; 3320 3321 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3322 3323 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3324 3325 if (sc->sc_dying) 3326 return USBD_IOERROR; 3327 3328 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3329 3330 parameter = DMAADDR(dma, 0); 3331 /* 3332 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3333 * If the user supplied buffer crosses such a boundary then 2 3334 * (or more) TRB should be used. 3335 * If multiple TRB are used the td_size field must be set correctly. 3336 * For v1.0 devices (like ivy bridge) this is the number of usb data 3337 * blocks needed to complete the transfer. 3338 * Setting it to 1 in the last TRB causes an extra zero-length 3339 * data block be sent. 3340 * The earlier documentation differs, I don't know how it behaves. 3341 */ 3342 KASSERT(len <= 0x10000); 3343 status = XHCI_TRB_2_IRQ_SET(0) | 3344 XHCI_TRB_2_TDSZ_SET(1) | 3345 XHCI_TRB_2_BYTES_SET(len); 3346 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3347 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3348 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3349 3350 mutex_enter(&tr->xr_lock); 3351 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3352 mutex_exit(&tr->xr_lock); 3353 3354 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3355 3356 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3357 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3358 xhci_timeout, xfer); 3359 } 3360 3361 if (sc->sc_bus.ub_usepolling) { 3362 DPRINTFN(1, "polling", 0, 0, 0, 0); 3363 //xhci_waitintr(sc, xfer); 3364 } 3365 3366 return USBD_IN_PROGRESS; 3367 } 3368 3369 static void 3370 xhci_device_bulk_done(struct usbd_xfer *xfer) 3371 { 3372 #ifdef USB_DEBUG 3373 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3374 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3375 #endif 3376 const int isread = usbd_xfer_isread(xfer); 3377 3378 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3379 3380 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3381 3382 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3383 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3384 } 3385 3386 static void 3387 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3388 { 3389 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3390 3391 xhci_abort_xfer(xfer, USBD_CANCELLED); 3392 } 3393 3394 static void 3395 xhci_device_bulk_close(struct usbd_pipe *pipe) 3396 { 3397 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3398 3399 xhci_close_pipe(pipe); 3400 } 3401 3402 /* ---------------- */ 3403 /* device interrupt */ 3404 3405 static usbd_status 3406 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3407 { 3408 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3409 usbd_status err; 3410 3411 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3412 3413 /* Insert last in queue. */ 3414 mutex_enter(&sc->sc_lock); 3415 err = usb_insert_transfer(xfer); 3416 mutex_exit(&sc->sc_lock); 3417 if (err) 3418 return err; 3419 3420 /* 3421 * Pipe isn't running (otherwise err would be USBD_INPROG), 3422 * so start it first. 3423 */ 3424 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3425 } 3426 3427 static usbd_status 3428 xhci_device_intr_start(struct usbd_xfer *xfer) 3429 { 3430 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3431 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3432 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3433 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3434 struct xhci_xfer * const xx = (void *)xfer; 3435 const uint32_t len = xfer->ux_length; 3436 usb_dma_t * const dma = &xfer->ux_dmabuf; 3437 uint64_t parameter; 3438 uint32_t status; 3439 uint32_t control; 3440 u_int i = 0; 3441 3442 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3443 3444 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3445 3446 if (sc->sc_dying) 3447 return USBD_IOERROR; 3448 3449 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3450 3451 parameter = DMAADDR(dma, 0); 3452 KASSERT(len <= 0x10000); 3453 status = XHCI_TRB_2_IRQ_SET(0) | 3454 XHCI_TRB_2_TDSZ_SET(1) | 3455 XHCI_TRB_2_BYTES_SET(len); 3456 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3457 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3458 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3459 3460 mutex_enter(&tr->xr_lock); 3461 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3462 mutex_exit(&tr->xr_lock); 3463 3464 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3465 3466 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3467 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3468 xhci_timeout, xfer); 3469 } 3470 3471 if (sc->sc_bus.ub_usepolling) { 3472 DPRINTFN(1, "polling", 0, 0, 0, 0); 3473 //xhci_waitintr(sc, xfer); 3474 } 3475 3476 return USBD_IN_PROGRESS; 3477 } 3478 3479 static void 3480 xhci_device_intr_done(struct usbd_xfer *xfer) 3481 { 3482 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3483 #ifdef USB_DEBUG 3484 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3485 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3486 #endif 3487 const int isread = usbd_xfer_isread(xfer); 3488 3489 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3490 3491 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3492 3493 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3494 3495 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3496 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3497 3498 #if 0 3499 device_printf(sc->sc_dev, ""); 3500 for (size_t i = 0; i < xfer->ux_length; i++) { 3501 printf(" %02x", ((uint8_t const *)xfer->ux_buffer)[i]); 3502 } 3503 printf("\n"); 3504 #endif 3505 3506 } 3507 3508 static void 3509 xhci_device_intr_abort(struct usbd_xfer *xfer) 3510 { 3511 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3512 3513 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3514 3515 KASSERT(mutex_owned(&sc->sc_lock)); 3516 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3517 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3518 xhci_abort_xfer(xfer, USBD_CANCELLED); 3519 } 3520 3521 static void 3522 xhci_device_intr_close(struct usbd_pipe *pipe) 3523 { 3524 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3525 3526 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3527 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3528 3529 xhci_close_pipe(pipe); 3530 } 3531 3532 /* ------------ */ 3533 3534 static void 3535 xhci_timeout(void *addr) 3536 { 3537 struct xhci_xfer * const xx = addr; 3538 struct usbd_xfer * const xfer = &xx->xx_xfer; 3539 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3540 3541 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3542 3543 if (sc->sc_dying) { 3544 return; 3545 } 3546 3547 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 3548 USB_TASKQ_MPSAFE); 3549 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 3550 USB_TASKQ_HC); 3551 } 3552 3553 static void 3554 xhci_timeout_task(void *addr) 3555 { 3556 struct usbd_xfer * const xfer = addr; 3557 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3558 3559 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3560 3561 mutex_enter(&sc->sc_lock); 3562 #if 0 3563 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3564 #else 3565 xfer->ux_status = USBD_TIMEOUT; 3566 usb_transfer_complete(xfer); 3567 #endif 3568 mutex_exit(&sc->sc_lock); 3569 } 3570
Indexes created Fri Sep 26 20:09:58 GMT 2025