xhci.c revision 1.36
1 /* $NetBSD: xhci.c,v 1.36 2016/04/30 14:51:04 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 3.1 specification 31 * http://www.usb.org/developers/docs/usb_31_040315.zip 32 * USB rev 2.0 specification 33 * http://www.usb.org/developers/docs/usb20_docs/usb_20_031815.zip 34 * xHCI rev 1.1 specification 35 * http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.36 2016/04/30 14:51:04 skrll Exp $"); 40 41 #include "opt_usb.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 146 147 static usbd_status xhci_do_command(struct xhci_softc * const, 148 struct xhci_trb * const, int); 149 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 150 struct xhci_trb * const, int); 151 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t, uint32_t, int); 152 static usbd_status xhci_enable_slot(struct xhci_softc * const, 153 uint8_t * const); 154 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 155 static usbd_status xhci_address_device(struct xhci_softc * const, 156 uint64_t, uint8_t, bool); 157 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 158 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 159 struct xhci_slot * const, u_int); 160 static usbd_status xhci_ring_init(struct xhci_softc * const, 161 struct xhci_ring * const, size_t, size_t); 162 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 163 164 static void xhci_noop(struct usbd_pipe *); 165 166 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 167 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 168 static void xhci_root_intr_abort(struct usbd_xfer *); 169 static void xhci_root_intr_close(struct usbd_pipe *); 170 static void xhci_root_intr_done(struct usbd_xfer *); 171 172 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 173 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 174 static void xhci_device_ctrl_abort(struct usbd_xfer *); 175 static void xhci_device_ctrl_close(struct usbd_pipe *); 176 static void xhci_device_ctrl_done(struct usbd_xfer *); 177 178 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 179 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 180 static void xhci_device_intr_abort(struct usbd_xfer *); 181 static void xhci_device_intr_close(struct usbd_pipe *); 182 static void xhci_device_intr_done(struct usbd_xfer *); 183 184 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 185 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 186 static void xhci_device_bulk_abort(struct usbd_xfer *); 187 static void xhci_device_bulk_close(struct usbd_pipe *); 188 static void xhci_device_bulk_done(struct usbd_xfer *); 189 190 static void xhci_timeout(void *); 191 static void xhci_timeout_task(void *); 192 193 static const struct usbd_bus_methods xhci_bus_methods = { 194 .ubm_open = xhci_open, 195 .ubm_softint = xhci_softintr, 196 .ubm_dopoll = xhci_poll, 197 .ubm_allocx = xhci_allocx, 198 .ubm_freex = xhci_freex, 199 .ubm_getlock = xhci_get_lock, 200 .ubm_newdev = xhci_new_device, 201 .ubm_rhctrl = xhci_roothub_ctrl, 202 }; 203 204 static const struct usbd_pipe_methods xhci_root_intr_methods = { 205 .upm_transfer = xhci_root_intr_transfer, 206 .upm_start = xhci_root_intr_start, 207 .upm_abort = xhci_root_intr_abort, 208 .upm_close = xhci_root_intr_close, 209 .upm_cleartoggle = xhci_noop, 210 .upm_done = xhci_root_intr_done, 211 }; 212 213 214 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 215 .upm_transfer = xhci_device_ctrl_transfer, 216 .upm_start = xhci_device_ctrl_start, 217 .upm_abort = xhci_device_ctrl_abort, 218 .upm_close = xhci_device_ctrl_close, 219 .upm_cleartoggle = xhci_noop, 220 .upm_done = xhci_device_ctrl_done, 221 }; 222 223 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 224 .upm_cleartoggle = xhci_noop, 225 }; 226 227 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 228 .upm_transfer = xhci_device_bulk_transfer, 229 .upm_start = xhci_device_bulk_start, 230 .upm_abort = xhci_device_bulk_abort, 231 .upm_close = xhci_device_bulk_close, 232 .upm_cleartoggle = xhci_noop, 233 .upm_done = xhci_device_bulk_done, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_intr_methods = { 237 .upm_transfer = xhci_device_intr_transfer, 238 .upm_start = xhci_device_intr_start, 239 .upm_abort = xhci_device_intr_abort, 240 .upm_close = xhci_device_intr_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_intr_done, 243 }; 244 245 static inline uint32_t 246 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 247 { 248 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 249 } 250 251 static inline uint32_t 252 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 253 { 254 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 255 } 256 257 static inline void 258 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 259 uint32_t value) 260 { 261 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 262 } 263 264 #if 0 /* unused */ 265 static inline void 266 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 267 uint32_t value) 268 { 269 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 270 } 271 #endif /* unused */ 272 273 static inline uint32_t 274 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 275 { 276 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 277 } 278 279 static inline uint32_t 280 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 281 { 282 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 283 } 284 285 static inline void 286 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 287 uint32_t value) 288 { 289 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 290 } 291 292 #if 0 /* unused */ 293 static inline uint64_t 294 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 295 { 296 uint64_t value; 297 298 if (sc->sc_ac64) { 299 #ifdef XHCI_USE_BUS_SPACE_8 300 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 301 #else 302 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 303 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 304 offset + 4) << 32; 305 #endif 306 } else { 307 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 308 } 309 310 return value; 311 } 312 #endif /* unused */ 313 314 static inline void 315 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 316 uint64_t value) 317 { 318 if (sc->sc_ac64) { 319 #ifdef XHCI_USE_BUS_SPACE_8 320 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 321 #else 322 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 323 (value >> 0) & 0xffffffff); 324 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 325 (value >> 32) & 0xffffffff); 326 #endif 327 } else { 328 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 329 } 330 } 331 332 static inline uint32_t 333 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 334 { 335 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 336 } 337 338 static inline void 339 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 340 uint32_t value) 341 { 342 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 343 } 344 345 #if 0 /* unused */ 346 static inline uint64_t 347 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 348 { 349 uint64_t value; 350 351 if (sc->sc_ac64) { 352 #ifdef XHCI_USE_BUS_SPACE_8 353 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 354 #else 355 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 356 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 357 offset + 4) << 32; 358 #endif 359 } else { 360 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 361 } 362 363 return value; 364 } 365 #endif /* unused */ 366 367 static inline void 368 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 369 uint64_t value) 370 { 371 if (sc->sc_ac64) { 372 #ifdef XHCI_USE_BUS_SPACE_8 373 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 374 #else 375 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 376 (value >> 0) & 0xffffffff); 377 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 378 (value >> 32) & 0xffffffff); 379 #endif 380 } else { 381 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 382 } 383 } 384 385 #if 0 /* unused */ 386 static inline uint32_t 387 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 388 { 389 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 390 } 391 #endif /* unused */ 392 393 static inline void 394 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 395 uint32_t value) 396 { 397 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 398 } 399 400 /* --- */ 401 402 static inline uint8_t 403 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 404 { 405 u_int eptype = 0; 406 407 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 408 case UE_CONTROL: 409 eptype = 0x0; 410 break; 411 case UE_ISOCHRONOUS: 412 eptype = 0x1; 413 break; 414 case UE_BULK: 415 eptype = 0x2; 416 break; 417 case UE_INTERRUPT: 418 eptype = 0x3; 419 break; 420 } 421 422 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 423 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 424 return eptype | 0x4; 425 else 426 return eptype; 427 } 428 429 static u_int 430 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 431 { 432 /* xHCI 1.0 section 4.5.1 */ 433 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 434 u_int in = 0; 435 436 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 437 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 438 in = 1; 439 440 return epaddr * 2 + in; 441 } 442 443 static inline u_int 444 xhci_dci_to_ici(const u_int i) 445 { 446 return i + 1; 447 } 448 449 static inline void * 450 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 451 const u_int dci) 452 { 453 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 454 } 455 456 #if 0 /* unused */ 457 static inline bus_addr_t 458 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 459 const u_int dci) 460 { 461 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 462 } 463 #endif /* unused */ 464 465 static inline void * 466 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 467 const u_int ici) 468 { 469 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 470 } 471 472 static inline bus_addr_t 473 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline struct xhci_trb * 480 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 481 { 482 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 483 } 484 485 static inline bus_addr_t 486 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 487 { 488 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 489 } 490 491 static inline void 492 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 493 uint32_t control) 494 { 495 trb->trb_0 = htole64(parameter); 496 trb->trb_2 = htole32(status); 497 trb->trb_3 = htole32(control); 498 } 499 500 /* --- */ 501 502 void 503 xhci_childdet(device_t self, device_t child) 504 { 505 struct xhci_softc * const sc = device_private(self); 506 507 KASSERT(sc->sc_child == child); 508 if (child == sc->sc_child) 509 sc->sc_child = NULL; 510 } 511 512 int 513 xhci_detach(struct xhci_softc *sc, int flags) 514 { 515 int rv = 0; 516 517 if (sc->sc_child != NULL) 518 rv = config_detach(sc->sc_child, flags); 519 520 if (rv != 0) 521 return rv; 522 523 /* XXX unconfigure/free slots */ 524 525 /* verify: */ 526 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 527 xhci_op_write_4(sc, XHCI_USBCMD, 0); 528 /* do we need to wait for stop? */ 529 530 xhci_op_write_8(sc, XHCI_CRCR, 0); 531 xhci_ring_free(sc, &sc->sc_cr); 532 cv_destroy(&sc->sc_command_cv); 533 534 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 535 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 536 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 537 xhci_ring_free(sc, &sc->sc_er); 538 539 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 540 541 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 542 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 543 544 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 545 546 mutex_destroy(&sc->sc_lock); 547 mutex_destroy(&sc->sc_intr_lock); 548 cv_destroy(&sc->sc_softwake_cv); 549 550 pool_cache_destroy(sc->sc_xferpool); 551 552 return rv; 553 } 554 555 int 556 xhci_activate(device_t self, enum devact act) 557 { 558 struct xhci_softc * const sc = device_private(self); 559 560 switch (act) { 561 case DVACT_DEACTIVATE: 562 sc->sc_dying = true; 563 return 0; 564 default: 565 return EOPNOTSUPP; 566 } 567 } 568 569 bool 570 xhci_suspend(device_t dv, const pmf_qual_t *qual) 571 { 572 return false; 573 } 574 575 bool 576 xhci_resume(device_t dv, const pmf_qual_t *qual) 577 { 578 return false; 579 } 580 581 bool 582 xhci_shutdown(device_t self, int flags) 583 { 584 return false; 585 } 586 587 588 static void 589 hexdump(const char *msg, const void *base, size_t len) 590 { 591 #if 0 592 size_t cnt; 593 const uint32_t *p; 594 extern paddr_t vtophys(vaddr_t); 595 596 p = base; 597 cnt = 0; 598 599 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 600 (void *)vtophys((vaddr_t)base)); 601 602 while (cnt < len) { 603 if (cnt % 16 == 0) 604 printf("%p: ", p); 605 else if (cnt % 8 == 0) 606 printf(" |"); 607 printf(" %08x", *p++); 608 cnt += 4; 609 if (cnt % 16 == 0) 610 printf("\n"); 611 } 612 #endif 613 } 614 615 #define XHCI_HCCPREV1_BITS \ 616 "\177\020" /* New bitmask */ \ 617 "f\020\020XECP\0" \ 618 "f\014\4MAXPSA\0" \ 619 "b\013CFC\0" \ 620 "b\012SEC\0" \ 621 "b\011SBD\0" \ 622 "b\010FSE\0" \ 623 "b\7NSS\0" \ 624 "b\6LTC\0" \ 625 "b\5LHRC\0" \ 626 "b\4PIND\0" \ 627 "b\3PPC\0" \ 628 "b\2CZC\0" \ 629 "b\1BNC\0" \ 630 "b\0AC64\0" \ 631 "\0" 632 #define XHCI_HCCV1_x_BITS \ 633 "\177\020" /* New bitmask */ \ 634 "f\020\020XECP\0" \ 635 "f\014\4MAXPSA\0" \ 636 "b\013CFC\0" \ 637 "b\012SEC\0" \ 638 "b\011SPC\0" \ 639 "b\010PAE\0" \ 640 "b\7NSS\0" \ 641 "b\6LTC\0" \ 642 "b\5LHRC\0" \ 643 "b\4PIND\0" \ 644 "b\3PPC\0" \ 645 "b\2CSZ\0" \ 646 "b\1BNC\0" \ 647 "b\0AC64\0" \ 648 "\0" 649 650 int 651 xhci_init(struct xhci_softc *sc) 652 { 653 bus_size_t bsz; 654 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 655 uint32_t ecp, ecr; 656 uint32_t usbcmd, usbsts, pagesize, config; 657 int i; 658 uint16_t hciversion; 659 uint8_t caplength; 660 661 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 662 663 sc->sc_bus.ub_revision = USBREV_3_0; 664 sc->sc_bus.ub_usedma = true; 665 666 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 667 caplength = XHCI_CAP_CAPLENGTH(cap); 668 hciversion = XHCI_CAP_HCIVERSION(cap); 669 670 if (hciversion < XHCI_HCIVERSION_0_96 || 671 hciversion > XHCI_HCIVERSION_1_0) { 672 aprint_normal_dev(sc->sc_dev, 673 "xHCI version %x.%x not known to be supported\n", 674 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 675 } else { 676 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 677 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 678 } 679 680 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 681 &sc->sc_cbh) != 0) { 682 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 683 return ENOMEM; 684 } 685 686 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 687 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 688 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 689 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 690 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 691 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 692 aprint_debug_dev(sc->sc_dev, 693 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 694 695 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 696 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 697 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 698 699 char sbuf[128]; 700 if (hciversion < XHCI_HCIVERSION_1_0) 701 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 702 else 703 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 704 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 705 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 706 707 ecp = XHCI_HCC_XECP(hcc) * 4; 708 while (ecp != 0) { 709 ecr = xhci_read_4(sc, ecp); 710 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 711 switch (XHCI_XECP_ID(ecr)) { 712 case XHCI_ID_PROTOCOLS: { 713 uint32_t w0, w4, w8; 714 uint16_t w2; 715 w0 = xhci_read_4(sc, ecp + 0); 716 w2 = (w0 >> 16) & 0xffff; 717 w4 = xhci_read_4(sc, ecp + 4); 718 w8 = xhci_read_4(sc, ecp + 8); 719 aprint_debug_dev(sc->sc_dev, "SP: %08x %08x %08x\n", 720 w0, w4, w8); 721 if (w4 == 0x20425355 && w2 == 0x0300) { 722 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 723 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 724 } 725 if (w4 == 0x20425355 && w2 == 0x0200) { 726 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 727 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 728 } 729 break; 730 } 731 case XHCI_ID_USB_LEGACY: { 732 uint8_t bios_sem; 733 734 /* Take host controller from BIOS */ 735 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 736 if (bios_sem) { 737 /* sets xHCI to be owned by OS */ 738 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 739 aprint_debug( 740 "waiting for BIOS to give up control\n"); 741 for (i = 0; i < 5000; i++) { 742 bios_sem = xhci_read_1(sc, ecp + 743 XHCI_XECP_BIOS_SEM); 744 if (bios_sem == 0) 745 break; 746 DELAY(1000); 747 } 748 if (bios_sem) 749 printf("timed out waiting for BIOS\n"); 750 } 751 break; 752 } 753 default: 754 break; 755 } 756 ecr = xhci_read_4(sc, ecp); 757 if (XHCI_XECP_NEXT(ecr) == 0) { 758 ecp = 0; 759 } else { 760 ecp += XHCI_XECP_NEXT(ecr) * 4; 761 } 762 } 763 764 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 765 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 766 &sc->sc_obh) != 0) { 767 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 768 return ENOMEM; 769 } 770 771 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 772 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 773 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 774 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 775 return ENOMEM; 776 } 777 778 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 779 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 780 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 781 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 782 return ENOMEM; 783 } 784 785 for (i = 0; i < 100; i++) { 786 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 787 if ((usbsts & XHCI_STS_CNR) == 0) 788 break; 789 usb_delay_ms(&sc->sc_bus, 1); 790 } 791 if (i >= 100) 792 return EIO; 793 794 usbcmd = 0; 795 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 796 usb_delay_ms(&sc->sc_bus, 1); 797 798 usbcmd = XHCI_CMD_HCRST; 799 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 800 for (i = 0; i < 100; i++) { 801 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 802 if ((usbcmd & XHCI_CMD_HCRST) == 0) 803 break; 804 usb_delay_ms(&sc->sc_bus, 1); 805 } 806 if (i >= 100) 807 return EIO; 808 809 for (i = 0; i < 100; i++) { 810 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 811 if ((usbsts & XHCI_STS_CNR) == 0) 812 break; 813 usb_delay_ms(&sc->sc_bus, 1); 814 } 815 if (i >= 100) 816 return EIO; 817 818 if (sc->sc_vendor_init) 819 sc->sc_vendor_init(sc); 820 821 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 822 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 823 pagesize = ffs(pagesize); 824 if (pagesize == 0) 825 return EIO; 826 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 827 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 828 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 829 (uint32_t)sc->sc_maxslots); 830 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 831 832 usbd_status err; 833 834 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 835 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 836 if (sc->sc_maxspbuf != 0) { 837 err = usb_allocmem(&sc->sc_bus, 838 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 839 &sc->sc_spbufarray_dma); 840 if (err) 841 return err; 842 843 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 844 sc->sc_maxspbuf, KM_SLEEP); 845 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 846 for (i = 0; i < sc->sc_maxspbuf; i++) { 847 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 848 /* allocate contexts */ 849 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 850 sc->sc_pgsz, dma); 851 if (err) 852 return err; 853 spbufarray[i] = htole64(DMAADDR(dma, 0)); 854 usb_syncmem(dma, 0, sc->sc_pgsz, 855 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 856 } 857 858 usb_syncmem(&sc->sc_spbufarray_dma, 0, 859 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 860 } 861 862 config = xhci_op_read_4(sc, XHCI_CONFIG); 863 config &= ~0xFF; 864 config |= sc->sc_maxslots & 0xFF; 865 xhci_op_write_4(sc, XHCI_CONFIG, config); 866 867 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 868 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 869 if (err) { 870 aprint_error_dev(sc->sc_dev, "command ring init fail\n"); 871 return err; 872 } 873 874 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 875 XHCI_EVENT_RING_SEGMENTS_ALIGN); 876 if (err) { 877 aprint_error_dev(sc->sc_dev, "event ring init fail\n"); 878 return err; 879 } 880 881 usb_dma_t *dma; 882 size_t size; 883 size_t align; 884 885 dma = &sc->sc_eventst_dma; 886 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 887 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 888 KASSERT(size <= (512 * 1024)); 889 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 890 err = usb_allocmem(&sc->sc_bus, size, align, dma); 891 892 memset(KERNADDR(dma, 0), 0, size); 893 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 894 aprint_debug_dev(sc->sc_dev, "eventst: %s %016jx %p %zx\n", 895 usbd_errstr(err), 896 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 897 KERNADDR(&sc->sc_eventst_dma, 0), 898 sc->sc_eventst_dma.udma_block->size); 899 900 dma = &sc->sc_dcbaa_dma; 901 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 902 KASSERT(size <= 2048); 903 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 904 err = usb_allocmem(&sc->sc_bus, size, align, dma); 905 906 memset(KERNADDR(dma, 0), 0, size); 907 if (sc->sc_maxspbuf != 0) { 908 /* 909 * DCBA entry 0 hold the scratchbuf array pointer. 910 */ 911 *(uint64_t *)KERNADDR(dma, 0) = 912 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 913 } 914 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 915 aprint_debug_dev(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n", 916 usbd_errstr(err), 917 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 918 KERNADDR(&sc->sc_dcbaa_dma, 0), 919 sc->sc_dcbaa_dma.udma_block->size); 920 921 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 922 KM_SLEEP); 923 924 cv_init(&sc->sc_command_cv, "xhcicmd"); 925 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 926 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 927 cv_init(&sc->sc_softwake_cv, "xhciab"); 928 929 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 930 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 931 932 /* Set up the bus struct. */ 933 sc->sc_bus.ub_methods = &xhci_bus_methods; 934 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 935 936 struct xhci_erste *erst; 937 erst = KERNADDR(&sc->sc_eventst_dma, 0); 938 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 939 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 940 erst[0].erste_3 = htole32(0); 941 usb_syncmem(&sc->sc_eventst_dma, 0, 942 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 943 944 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 945 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 946 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 947 XHCI_ERDP_LO_BUSY); 948 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 949 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 950 sc->sc_cr.xr_cs); 951 952 #if 0 953 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 954 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 955 #endif 956 957 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 958 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 959 /* Intel xhci needs interrupt rate moderated. */ 960 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 961 else 962 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 963 aprint_debug_dev(sc->sc_dev, "setting IMOD %u\n", 964 xhci_rt_read_4(sc, XHCI_IMOD(0))); 965 966 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 967 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 968 xhci_op_read_4(sc, XHCI_USBCMD)); 969 970 return USBD_NORMAL_COMPLETION; 971 } 972 973 int 974 xhci_intr(void *v) 975 { 976 struct xhci_softc * const sc = v; 977 int ret = 0; 978 979 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 980 981 if (sc == NULL) 982 return 0; 983 984 mutex_spin_enter(&sc->sc_intr_lock); 985 986 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 987 goto done; 988 989 /* If we get an interrupt while polling, then just ignore it. */ 990 if (sc->sc_bus.ub_usepolling) { 991 #ifdef DIAGNOSTIC 992 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 993 #endif 994 goto done; 995 } 996 997 ret = xhci_intr1(sc); 998 done: 999 mutex_spin_exit(&sc->sc_intr_lock); 1000 return ret; 1001 } 1002 1003 int 1004 xhci_intr1(struct xhci_softc * const sc) 1005 { 1006 uint32_t usbsts; 1007 uint32_t iman; 1008 1009 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1010 1011 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1012 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1013 #if 0 1014 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1015 return 0; 1016 } 1017 #endif 1018 xhci_op_write_4(sc, XHCI_USBSTS, 1019 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1020 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1021 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1022 1023 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1024 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1025 iman |= XHCI_IMAN_INTR_PEND; 1026 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1027 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1028 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1029 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1030 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1031 1032 usb_schedsoftintr(&sc->sc_bus); 1033 1034 return 1; 1035 } 1036 1037 /* 1038 * 3 port speed types used in USB stack 1039 * 1040 * usbdi speed 1041 * definition: USB_SPEED_* in usb.h 1042 * They are used in struct usbd_device in USB stack. 1043 * ioctl interface uses these values too. 1044 * port_status speed 1045 * definition: UPS_*_SPEED in usb.h 1046 * They are used in usb_port_status_t and valid only for USB 2.0. 1047 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1048 * of usb_port_status_ext_t indicates port speed. 1049 * Note that some 3.0 values overlap with 2.0 values. 1050 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1051 * means UPS_LOW_SPEED in HS.) 1052 * port status returned from hub also uses these values. 1053 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1054 * or more. 1055 * xspeed: 1056 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1057 * They are used in only slot context and PORTSC reg of xhci. 1058 * The difference between usbdi speed and xspeed is 1059 * that FS and LS values are swapped. 1060 */ 1061 1062 /* convert usbdi speed to xspeed */ 1063 static int 1064 xhci_speed2xspeed(int speed) 1065 { 1066 switch (speed) { 1067 case USB_SPEED_LOW: return 2; 1068 case USB_SPEED_FULL: return 1; 1069 default: return speed; 1070 } 1071 } 1072 1073 #if 0 1074 /* convert xspeed to usbdi speed */ 1075 static int 1076 xhci_xspeed2speed(int xspeed) 1077 { 1078 switch (xspeed) { 1079 case 1: return USB_SPEED_FULL; 1080 case 2: return USB_SPEED_LOW; 1081 default: return xspeed; 1082 } 1083 } 1084 #endif 1085 1086 /* convert xspeed to port status speed */ 1087 static int 1088 xhci_xspeed2psspeed(int xspeed) 1089 { 1090 switch (xspeed) { 1091 case 0: return 0; 1092 case 1: return UPS_FULL_SPEED; 1093 case 2: return UPS_LOW_SPEED; 1094 case 3: return UPS_HIGH_SPEED; 1095 default: return UPS_OTHER_SPEED; 1096 } 1097 } 1098 1099 /* construct slot context */ 1100 static void 1101 xhci_setup_sctx(struct usbd_device *dev, uint32_t *cp) 1102 { 1103 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 1104 int speed = dev->ud_speed; 1105 int tthubslot, ttportnum; 1106 bool ishub; 1107 bool usemtt; 1108 1109 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1110 1111 /* 1112 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 1113 * tthubslot: 1114 * This is the slot ID of parent HS hub 1115 * if LS/FS device is connected && connected through HS hub. 1116 * This is 0 if device is not LS/FS device || 1117 * parent hub is not HS hub || 1118 * attached to root hub. 1119 * ttportnum: 1120 * This is the downstream facing port of parent HS hub 1121 * if LS/FS device is connected. 1122 * This is 0 if device is not LS/FS device || 1123 * parent hub is not HS hub || 1124 * attached to root hub. 1125 */ 1126 if (dev->ud_myhsport != NULL && 1127 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1128 (dev->ud_myhub != NULL && 1129 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1130 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 1131 ttportnum = dev->ud_myhsport->up_portno; 1132 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 1133 } else { 1134 ttportnum = 0; 1135 tthubslot = 0; 1136 } 1137 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 1138 dev->ud_myhsport, ttportnum, tthubslot, 0); 1139 1140 /* ishub is valid after reading UDESC_DEVICE */ 1141 ishub = (dd->bDeviceClass == UDCLASS_HUB); 1142 1143 /* dev->ud_hub is valid after reading UDESC_HUB */ 1144 if (ishub && dev->ud_hub) { 1145 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 1146 1147 cp[1] |= htole32(XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts)); 1148 cp[2] |= htole32(XHCI_SCTX_2_TT_THINK_TIME_SET( 1149 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK))); 1150 DPRINTFN(4, "nports=%d ttt=%d", 1151 hd->bNbrPorts, XHCI_SCTX_2_TT_THINK_TIME_GET(cp[2]), 0, 0); 1152 } 1153 1154 #define IS_TTHUB(dd) \ 1155 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 1156 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 1157 1158 /* 1159 * MTT flag is set if 1160 * 1. this is HS hub && MTT is enabled 1161 * or 1162 * 2. this is not hub && this is LS or FS device && 1163 * MTT of parent HS hub (and its parent, too) is enabled 1164 */ 1165 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 1166 usemtt = true; 1167 else if (!ishub && 1168 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 1169 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1170 (dev->ud_myhub != NULL && 1171 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1172 dev->ud_myhsport != NULL && 1173 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 1174 usemtt = true; 1175 else 1176 usemtt = false; 1177 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 1178 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 1179 1180 cp[0] |= htole32( 1181 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)) | 1182 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 1183 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0) 1184 ); 1185 cp[1] |= htole32(0); 1186 cp[2] |= htole32( 1187 XHCI_SCTX_2_IRQ_TARGET_SET(0) | 1188 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 1189 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum) 1190 ); 1191 cp[3] |= htole32(0); 1192 } 1193 1194 static uint32_t 1195 xhci_get_maxburst(struct usbd_pipe *pipe) 1196 { 1197 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1198 usbd_desc_iter_t iter; 1199 const usb_cdc_descriptor_t *cdcd; 1200 const usb_endpoint_ss_comp_descriptor_t * esscd = NULL; 1201 uint32_t maxb = 0; 1202 uint8_t ep; 1203 1204 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc( 1205 pipe->up_dev, UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 1206 usb_desc_iter_init(pipe->up_dev, &iter); 1207 iter.cur = (const void *)cdcd; 1208 1209 /* find endpoint_ss_comp desc for ep of this pipe */ 1210 for (ep = 0;;) { 1211 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 1212 if (cdcd == NULL) 1213 break; 1214 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 1215 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 1216 bEndpointAddress; 1217 if (UE_GET_ADDR(ep) == 1218 UE_GET_ADDR(ed->bEndpointAddress)) { 1219 cdcd = (const usb_cdc_descriptor_t *) 1220 usb_desc_iter_next(&iter); 1221 break; 1222 } 1223 ep = 0; 1224 } 1225 } 1226 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 1227 esscd = (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 1228 maxb = esscd->bMaxBurst; 1229 } 1230 1231 return maxb; 1232 } 1233 1234 /* 1235 * Convert endpoint bInterval value to endpoint context interval value 1236 * for Interrupt pipe. 1237 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 1238 */ 1239 static uint32_t 1240 xhci_bival2ival(uint32_t ival, int speed) 1241 { 1242 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 1243 int i; 1244 1245 /* 1246 * round ival down to "the nearest base 2 multiple of 1247 * bInterval * 8". 1248 * bInterval is at most 255 as its type is uByte. 1249 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 1250 */ 1251 for (i = 10; i > 0; i--) { 1252 if ((ival * 8) >= (1 << i)) 1253 break; 1254 } 1255 ival = i; 1256 } else { 1257 /* Interval = bInterval-1 for SS/HS */ 1258 ival--; 1259 } 1260 1261 return ival; 1262 } 1263 1264 /* 1265 * 4.8.2, 6.2.3.2 1266 * construct common endpoint parameters 1267 */ 1268 static void 1269 xhci_setup_endp_ctx(struct usbd_pipe *pipe, uint32_t *cp) 1270 { 1271 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1272 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1273 const u_int dci = xhci_ep_get_dci(ed); 1274 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1275 uint32_t mps = UGETW(ed->wMaxPacketSize); 1276 uint32_t maxb = 0; 1277 int speed = pipe->up_dev->ud_speed; 1278 uint32_t ival = ed->bInterval; 1279 1280 cp[0] = htole32( 1281 XHCI_EPCTX_0_EPSTATE_SET(0) | 1282 XHCI_EPCTX_0_MULT_SET(0) | /* always 0 except SS iscoh */ 1283 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 1284 XHCI_EPCTX_0_LSA_SET(0) | 1285 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0) 1286 ); 1287 cp[1] = htole32( 1288 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 1289 XHCI_EPCTX_1_HID_SET(0) | 1290 XHCI_EPCTX_1_MAXB_SET(0) 1291 ); 1292 if (xfertype != UE_ISOCHRONOUS) 1293 cp[1] |= htole32(XHCI_EPCTX_1_CERR_SET(3)); 1294 1295 /* 6.2.3.4, 4.8.2.4 */ 1296 if (USB_IS_SS(speed)) { 1297 /* UBS 3.1 9.6.6 */ 1298 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1299 /* UBS 3.1 9.6.7 */ 1300 maxb = xhci_get_maxburst(pipe); 1301 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1302 } else { 1303 /* UBS 2.0 9.6.6 */ 1304 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps))); 1305 1306 /* 6.2.3.4 */ 1307 if (speed == USB_SPEED_HIGH && 1308 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 1309 maxb = UE_GET_TRANS(mps); 1310 } else { 1311 /* LS/FS or HS CTRL or HS BULK */ 1312 maxb = 0; 1313 } 1314 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1315 } 1316 1317 if (xfertype == UE_CONTROL) 1318 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(8)); /* 6.2.3 */ 1319 else if (USB_IS_SS(speed)) 1320 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps)); 1321 else 1322 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps))); 1323 1324 switch (xfertype) { 1325 case UE_CONTROL: 1326 break; 1327 case UE_BULK: 1328 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 1329 break; 1330 case UE_INTERRUPT: 1331 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1332 ival = pipe->up_interval; 1333 1334 ival = xhci_bival2ival(ival, speed); 1335 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1336 break; 1337 case UE_ISOCHRONOUS: 1338 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1339 ival = pipe->up_interval; 1340 1341 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 1342 if (speed == USB_SPEED_FULL) 1343 ival += 3; /* 1ms -> 125us */ 1344 ival--; 1345 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1346 1347 if (USB_IS_SS(speed)) { 1348 /* XXX if LEC = 1, set ESIT instead */ 1349 cp[0] |= htole32(XHCI_EPCTX_0_MULT_SET(0)); 1350 } 1351 break; 1352 default: 1353 break; 1354 } 1355 *(uint64_t *)(&cp[2]) = htole64( 1356 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 1357 XHCI_EPCTX_2_DCS_SET(1)); 1358 } 1359 1360 /* 1361 * Construct input contexts and issue TRB 1362 */ 1363 static usbd_status 1364 xhci_configure_endpoint(struct usbd_pipe *pipe) 1365 { 1366 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1367 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1368 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1369 struct xhci_trb trb; 1370 usbd_status err; 1371 uint32_t *cp; 1372 1373 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1374 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1375 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1376 pipe->up_endpoint->ue_edesc->bmAttributes); 1377 1378 /* XXX ensure input context is available? */ 1379 1380 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1381 1382 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1383 cp[0] = htole32(0); 1384 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 1385 1386 /* set up input slot context */ 1387 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1388 xhci_setup_sctx(pipe->up_dev, cp); 1389 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1390 1391 /* set up input endpoint context */ 1392 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 1393 xhci_setup_endp_ctx(pipe, cp); 1394 1395 /* sync input contexts before they are read from memory */ 1396 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1397 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1398 sc->sc_ctxsz * 1); 1399 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1400 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1401 1402 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1403 trb.trb_2 = 0; 1404 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1405 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1406 1407 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1408 1409 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1410 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1411 sc->sc_ctxsz * 1); 1412 1413 return err; 1414 } 1415 1416 #if 0 1417 static usbd_status 1418 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1419 { 1420 #ifdef USB_DEBUG 1421 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1422 #endif 1423 1424 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1425 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1426 1427 return USBD_NORMAL_COMPLETION; 1428 } 1429 #endif 1430 1431 /* 4.6.8, 6.4.3.7 */ 1432 static usbd_status 1433 xhci_reset_endpoint(struct usbd_pipe *pipe) 1434 { 1435 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1436 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1437 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1438 struct xhci_trb trb; 1439 usbd_status err; 1440 1441 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1442 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1443 1444 KASSERT(!mutex_owned(&sc->sc_lock)); 1445 1446 trb.trb_0 = 0; 1447 trb.trb_2 = 0; 1448 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1449 XHCI_TRB_3_EP_SET(dci) | 1450 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1451 1452 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1453 1454 return err; 1455 } 1456 1457 /* 1458 * 4.6.9, 6.4.3.8 1459 * Stop execution of TDs on xfer ring. 1460 * Should be called with sc_lock held. 1461 */ 1462 static usbd_status 1463 xhci_stop_endpoint(struct usbd_pipe *pipe) 1464 { 1465 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1466 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1467 struct xhci_trb trb; 1468 usbd_status err; 1469 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1470 1471 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1472 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1473 1474 KASSERT(mutex_owned(&sc->sc_lock)); 1475 1476 trb.trb_0 = 0; 1477 trb.trb_2 = 0; 1478 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1479 XHCI_TRB_3_EP_SET(dci) | 1480 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1481 1482 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1483 1484 return err; 1485 } 1486 1487 /* 1488 * Set TR Dequeue Pointer. 1489 * xCHI 1.1 4.6.10 6.4.3.9 1490 * Purge all of the transfer requests on ring. 1491 * EPSTATE of endpoint must be ERROR or STOPPED, or CONTEXT_STATE error. 1492 */ 1493 static usbd_status 1494 xhci_set_dequeue(struct usbd_pipe *pipe) 1495 { 1496 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1497 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1498 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1499 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1500 struct xhci_trb trb; 1501 usbd_status err; 1502 1503 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1504 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1505 1506 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1507 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1508 BUS_DMASYNC_PREWRITE); 1509 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1510 1511 xr->xr_ep = 0; 1512 xr->xr_cs = 1; 1513 1514 /* set DCS */ 1515 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1516 trb.trb_2 = 0; 1517 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1518 XHCI_TRB_3_EP_SET(dci) | 1519 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1520 1521 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1522 1523 return err; 1524 } 1525 1526 /* 1527 * Open new pipe: called from usbd_setup_pipe_flags. 1528 * Fills methods of pipe. 1529 * If pipe is not for ep0, calls configure_endpoint. 1530 */ 1531 static usbd_status 1532 xhci_open(struct usbd_pipe *pipe) 1533 { 1534 struct usbd_device * const dev = pipe->up_dev; 1535 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1536 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1537 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1538 1539 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1540 DPRINTFN(1, "addr %d depth %d port %d speed %d", 1541 dev->ud_addr, dev->ud_depth, dev->ud_powersrc->up_portno, 1542 dev->ud_speed); 1543 1544 if (sc->sc_dying) 1545 return USBD_IOERROR; 1546 1547 /* Root Hub */ 1548 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1549 switch (ed->bEndpointAddress) { 1550 case USB_CONTROL_ENDPOINT: 1551 pipe->up_methods = &roothub_ctrl_methods; 1552 break; 1553 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1554 pipe->up_methods = &xhci_root_intr_methods; 1555 break; 1556 default: 1557 pipe->up_methods = NULL; 1558 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1559 ed->bEndpointAddress, 0, 0, 0); 1560 return USBD_INVAL; 1561 } 1562 return USBD_NORMAL_COMPLETION; 1563 } 1564 1565 switch (xfertype) { 1566 case UE_CONTROL: 1567 pipe->up_methods = &xhci_device_ctrl_methods; 1568 break; 1569 case UE_ISOCHRONOUS: 1570 pipe->up_methods = &xhci_device_isoc_methods; 1571 return USBD_INVAL; 1572 break; 1573 case UE_BULK: 1574 pipe->up_methods = &xhci_device_bulk_methods; 1575 break; 1576 case UE_INTERRUPT: 1577 pipe->up_methods = &xhci_device_intr_methods; 1578 break; 1579 default: 1580 return USBD_IOERROR; 1581 break; 1582 } 1583 1584 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1585 return xhci_configure_endpoint(pipe); 1586 1587 return USBD_NORMAL_COMPLETION; 1588 } 1589 1590 /* 1591 * Closes pipe, called from usbd_kill_pipe via close methods. 1592 * If the endpoint to be closed is ep0, disable_slot. 1593 * Should be called with sc_lock held. 1594 */ 1595 static void 1596 xhci_close_pipe(struct usbd_pipe *pipe) 1597 { 1598 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1599 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1600 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1601 const u_int dci = xhci_ep_get_dci(ed); 1602 struct xhci_trb trb; 1603 uint32_t *cp; 1604 1605 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1606 1607 if (sc->sc_dying) 1608 return; 1609 1610 if (xs == NULL || xs->xs_idx == 0) 1611 /* xs is uninitialized before xhci_init_slot */ 1612 return; 1613 1614 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1615 1616 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1617 KASSERT(mutex_owned(&sc->sc_lock)); 1618 1619 if (pipe->up_dev->ud_depth == 0) 1620 return; 1621 1622 if (dci == XHCI_DCI_EP_CONTROL) { 1623 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1624 xhci_disable_slot(sc, xs->xs_idx); 1625 return; 1626 } 1627 1628 /* 1629 * This may fail in the case that xhci_close_pipe is called after 1630 * xhci_abort_xfer e.g. usbd_kill_pipe. 1631 */ 1632 (void)xhci_stop_endpoint(pipe); 1633 1634 /* 1635 * set appropriate bit to be dropped. 1636 * don't set DC bit to 1, otherwise all endpoints 1637 * would be deconfigured. 1638 */ 1639 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1640 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1641 cp[1] = htole32(0); 1642 1643 /* XXX should be most significant one, not dci? */ 1644 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1645 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1646 1647 /* sync input contexts before they are read from memory */ 1648 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1649 1650 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1651 trb.trb_2 = 0; 1652 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1653 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1654 1655 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1656 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1657 } 1658 1659 /* 1660 * Abort transfer. 1661 * Called with sc_lock held. 1662 * May be called from softintr context. 1663 */ 1664 static void 1665 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1666 { 1667 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1668 1669 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1670 DPRINTFN(4, "xfer %p pipe %p status %d", 1671 xfer, xfer->ux_pipe, status, 0); 1672 1673 KASSERT(mutex_owned(&sc->sc_lock)); 1674 1675 if (sc->sc_dying) { 1676 /* If we're dying, just do the software part. */ 1677 DPRINTFN(4, "dying", 0, 0, 0, 0); 1678 xfer->ux_status = status; /* make software ignore it */ 1679 callout_stop(&xfer->ux_callout); 1680 usb_transfer_complete(xfer); 1681 return; 1682 } 1683 1684 /* XXX need more stuff */ 1685 xfer->ux_status = status; 1686 callout_stop(&xfer->ux_callout); 1687 usb_transfer_complete(xfer); 1688 DPRINTFN(14, "end", 0, 0, 0, 0); 1689 1690 KASSERT(mutex_owned(&sc->sc_lock)); 1691 } 1692 1693 /* 1694 * Recover STALLed endpoint. 1695 * xHCI 1.1 sect 4.10.2.1 1696 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1697 * all transfers on transfer ring. 1698 * These are done in thread context asynchronously. 1699 */ 1700 static void 1701 xhci_clear_endpoint_stall_async_task(void *cookie) 1702 { 1703 struct usbd_xfer * const xfer = cookie; 1704 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1705 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1706 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1707 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1708 1709 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1710 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1711 1712 xhci_reset_endpoint(xfer->ux_pipe); 1713 xhci_set_dequeue(xfer->ux_pipe); 1714 1715 mutex_enter(&sc->sc_lock); 1716 tr->is_halted = false; 1717 usb_transfer_complete(xfer); 1718 mutex_exit(&sc->sc_lock); 1719 DPRINTFN(4, "ends", 0, 0, 0, 0); 1720 } 1721 1722 static usbd_status 1723 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1724 { 1725 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1726 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1727 1728 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1729 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1730 1731 if (sc->sc_dying) { 1732 return USBD_IOERROR; 1733 } 1734 1735 usb_init_task(&xp->xp_async_task, 1736 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1737 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1738 DPRINTFN(4, "ends", 0, 0, 0, 0); 1739 1740 return USBD_NORMAL_COMPLETION; 1741 } 1742 1743 /* Process roothub port status/change events and notify to uhub_intr. */ 1744 static void 1745 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1746 { 1747 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1748 uint8_t *p; 1749 1750 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1751 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1752 port, 0, 0); 1753 1754 if (xfer == NULL) 1755 return; 1756 1757 if (port > sc->sc_maxports) 1758 return; 1759 1760 p = xfer->ux_buf; 1761 memset(p, 0, xfer->ux_length); 1762 p[port/NBBY] |= 1 << (port%NBBY); 1763 xfer->ux_actlen = xfer->ux_length; 1764 xfer->ux_status = USBD_NORMAL_COMPLETION; 1765 usb_transfer_complete(xfer); 1766 } 1767 1768 /* Process Transfer Events */ 1769 static void 1770 xhci_event_transfer(struct xhci_softc * const sc, 1771 const struct xhci_trb * const trb) 1772 { 1773 uint64_t trb_0; 1774 uint32_t trb_2, trb_3; 1775 uint8_t trbcode; 1776 u_int slot, dci; 1777 struct xhci_slot *xs; 1778 struct xhci_ring *xr; 1779 struct xhci_xfer *xx; 1780 struct usbd_xfer *xfer; 1781 usbd_status err; 1782 1783 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1784 1785 trb_0 = le64toh(trb->trb_0); 1786 trb_2 = le32toh(trb->trb_2); 1787 trb_3 = le32toh(trb->trb_3); 1788 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1789 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1790 dci = XHCI_TRB_3_EP_GET(trb_3); 1791 xs = &sc->sc_slots[slot]; 1792 xr = &xs->xs_ep[dci].xe_tr; 1793 1794 /* sanity check */ 1795 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1796 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1797 1798 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1799 /* 1800 * When ED == 0, trb_0 is physical address of the TRB 1801 * that caused this event. (6.4.2.1) 1802 */ 1803 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 1804 1805 /* trb_0 range sanity check */ 1806 if (trb_0 < trbp || 1807 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 1808 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 1809 DPRINTFN(1, "invalid trb_0 0x%"PRIx64" trbp 0x%"PRIx64, 1810 trb_0, trbp, 0, 0); 1811 return; 1812 } 1813 int idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 1814 xx = xr->xr_cookies[idx]; 1815 1816 /* 1817 * If endpoint is stopped between TDs, TRB pointer points at 1818 * next TRB, however, it is not put yet or is a garbage TRB. 1819 * That's why xr_cookies may be NULL or look like broken. 1820 * Note: this ev happens only when hciversion >= 1.0 or 1821 * hciversion == 0.96 and FSE of hcc1 is set. 1822 */ 1823 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1824 DPRINTFN(1, "xx NULL: #%u: cookie %p: code %u trb_0 %" 1825 PRIx64, idx, xx, trbcode, trb_0); 1826 } 1827 } else { 1828 /* When ED != 0, trb_0 is kaddr of struct xhci_xfer. */ 1829 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1830 } 1831 /* XXX this may not happen */ 1832 if (xx == NULL) { 1833 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1834 return; 1835 } 1836 xfer = &xx->xx_xfer; 1837 /* XXX this may happen when detaching */ 1838 if (xfer == NULL) { 1839 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1840 xx, trb_0, 0, 0); 1841 return; 1842 } 1843 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1844 /* XXX I dunno why this happens */ 1845 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1846 1847 if (!xfer->ux_pipe->up_repeat && 1848 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1849 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1850 return; 1851 } 1852 1853 /* 4.11.5.2 Event Data TRB */ 1854 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1855 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1856 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1857 if ((trb_0 & 0x3) == 0x3) { 1858 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1859 } 1860 } 1861 1862 switch (trbcode) { 1863 case XHCI_TRB_ERROR_SHORT_PKT: 1864 case XHCI_TRB_ERROR_SUCCESS: 1865 xfer->ux_actlen = 1866 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1867 err = USBD_NORMAL_COMPLETION; 1868 break; 1869 case XHCI_TRB_ERROR_STALL: 1870 case XHCI_TRB_ERROR_BABBLE: 1871 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1872 xr->is_halted = true; 1873 err = USBD_STALLED; 1874 /* 1875 * Stalled endpoints can be recoverd by issuing 1876 * command TRB TYPE_RESET_EP on xHCI instead of 1877 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1878 * on the endpoint. However, this function may be 1879 * called from softint context (e.g. from umass), 1880 * in that case driver gets KASSERT in cv_timedwait 1881 * in xhci_do_command. 1882 * To avoid this, this runs reset_endpoint and 1883 * usb_transfer_complete in usb task thread 1884 * asynchronously (and then umass issues clear 1885 * UF_ENDPOINT_HALT). 1886 */ 1887 xfer->ux_status = err; 1888 xhci_clear_endpoint_stall_async(xfer); 1889 return; 1890 default: 1891 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1892 err = USBD_IOERROR; 1893 break; 1894 } 1895 xfer->ux_status = err; 1896 1897 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1898 if ((trb_0 & 0x3) == 0x0) { 1899 callout_stop(&xfer->ux_callout); 1900 usb_transfer_complete(xfer); 1901 } 1902 } else { 1903 callout_stop(&xfer->ux_callout); 1904 usb_transfer_complete(xfer); 1905 } 1906 } 1907 1908 /* Process Command complete events */ 1909 static void 1910 xhci_event_cmd(struct xhci_softc * const sc, 1911 const struct xhci_trb * const trb) 1912 { 1913 uint64_t trb_0; 1914 uint32_t trb_2, trb_3; 1915 1916 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1917 1918 trb_0 = le64toh(trb->trb_0); 1919 trb_2 = le32toh(trb->trb_2); 1920 trb_3 = le32toh(trb->trb_3); 1921 1922 if (trb_0 == sc->sc_command_addr) { 1923 sc->sc_result_trb.trb_0 = trb_0; 1924 sc->sc_result_trb.trb_2 = trb_2; 1925 sc->sc_result_trb.trb_3 = trb_3; 1926 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1927 XHCI_TRB_ERROR_SUCCESS) { 1928 DPRINTFN(1, "command completion " 1929 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1930 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1931 } 1932 cv_signal(&sc->sc_command_cv); 1933 } else { 1934 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 1935 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1936 trb_2, trb_3); 1937 } 1938 } 1939 1940 /* 1941 * Process events. 1942 * called from xhci_softintr 1943 */ 1944 static void 1945 xhci_handle_event(struct xhci_softc * const sc, 1946 const struct xhci_trb * const trb) 1947 { 1948 uint64_t trb_0; 1949 uint32_t trb_2, trb_3; 1950 1951 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1952 1953 trb_0 = le64toh(trb->trb_0); 1954 trb_2 = le32toh(trb->trb_2); 1955 trb_3 = le32toh(trb->trb_3); 1956 1957 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1958 trb, trb_0, trb_2, trb_3); 1959 1960 /* 1961 * 4.11.3.1, 6.4.2.1 1962 * TRB Pointer is invalid for these completion codes. 1963 */ 1964 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 1965 case XHCI_TRB_ERROR_RING_UNDERRUN: 1966 case XHCI_TRB_ERROR_RING_OVERRUN: 1967 case XHCI_TRB_ERROR_VF_RING_FULL: 1968 return; 1969 default: 1970 if (trb_0 == 0) { 1971 return; 1972 } 1973 break; 1974 } 1975 1976 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 1977 case XHCI_TRB_EVENT_TRANSFER: 1978 xhci_event_transfer(sc, trb); 1979 break; 1980 case XHCI_TRB_EVENT_CMD_COMPLETE: 1981 xhci_event_cmd(sc, trb); 1982 break; 1983 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1984 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1985 break; 1986 default: 1987 break; 1988 } 1989 } 1990 1991 static void 1992 xhci_softintr(void *v) 1993 { 1994 struct usbd_bus * const bus = v; 1995 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1996 struct xhci_ring * const er = &sc->sc_er; 1997 struct xhci_trb *trb; 1998 int i, j, k; 1999 2000 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2001 2002 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2003 2004 i = er->xr_ep; 2005 j = er->xr_cs; 2006 2007 DPRINTFN(16, "xr_ep %d xr_cs %d", i, j, 0, 0); 2008 2009 while (1) { 2010 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2011 BUS_DMASYNC_POSTREAD); 2012 trb = &er->xr_trb[i]; 2013 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2014 2015 if (j != k) 2016 break; 2017 2018 xhci_handle_event(sc, trb); 2019 2020 i++; 2021 if (i == XHCI_EVENT_RING_TRBS) { 2022 i = 0; 2023 j ^= 1; 2024 } 2025 } 2026 2027 er->xr_ep = i; 2028 er->xr_cs = j; 2029 2030 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2031 XHCI_ERDP_LO_BUSY); 2032 2033 DPRINTFN(16, "ends", 0, 0, 0, 0); 2034 2035 return; 2036 } 2037 2038 static void 2039 xhci_poll(struct usbd_bus *bus) 2040 { 2041 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2042 2043 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2044 2045 mutex_spin_enter(&sc->sc_intr_lock); 2046 xhci_intr1(sc); 2047 mutex_spin_exit(&sc->sc_intr_lock); 2048 2049 return; 2050 } 2051 2052 static struct usbd_xfer * 2053 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2054 { 2055 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2056 struct usbd_xfer *xfer; 2057 2058 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2059 2060 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 2061 if (xfer != NULL) { 2062 memset(xfer, 0, sizeof(struct xhci_xfer)); 2063 #ifdef DIAGNOSTIC 2064 xfer->ux_state = XFER_BUSY; 2065 #endif 2066 } 2067 2068 return xfer; 2069 } 2070 2071 static void 2072 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2073 { 2074 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2075 2076 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2077 2078 #ifdef DIAGNOSTIC 2079 if (xfer->ux_state != XFER_BUSY) { 2080 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 2081 xfer, xfer->ux_state, 0, 0); 2082 } 2083 xfer->ux_state = XFER_FREE; 2084 #endif 2085 pool_cache_put(sc->sc_xferpool, xfer); 2086 } 2087 2088 static void 2089 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2090 { 2091 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2092 2093 *lock = &sc->sc_lock; 2094 } 2095 2096 extern uint32_t usb_cookie_no; 2097 2098 /* 2099 * Called if uhub_explore finds a new device (via usbd_new_device). 2100 * Allocate and construct dev structure of default endpoint (ep0). 2101 * Determine initial MaxPacketSize (mps) by speed. 2102 * Determine route string and roothub port for slot of dev. 2103 * Allocate pipe of ep0. 2104 * Enable and initialize slot and Set Address. 2105 * Read device descriptor. 2106 * Register this device. 2107 */ 2108 static usbd_status 2109 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2110 int speed, int port, struct usbd_port *up) 2111 { 2112 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2113 struct usbd_device *dev; 2114 usbd_status err; 2115 usb_device_descriptor_t *dd; 2116 struct usbd_device *hub; 2117 struct usbd_device *adev; 2118 int rhport = 0; 2119 struct xhci_slot *xs; 2120 uint32_t *cp; 2121 uint32_t route = 0; 2122 uint8_t slot = 0; 2123 uint8_t addr; 2124 2125 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2126 DPRINTFN(4, "port=%d depth=%d speed=%d upport %d", 2127 port, depth, speed, up->up_portno); 2128 2129 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2130 if (dev == NULL) 2131 return USBD_NOMEM; 2132 2133 dev->ud_bus = bus; 2134 2135 /* Set up default endpoint handle. */ 2136 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2137 2138 /* Set up default endpoint descriptor. */ 2139 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2140 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2141 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2142 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2143 /* 4.3, 4.8.2.1 */ 2144 switch (speed) { 2145 case USB_SPEED_SUPER: 2146 case USB_SPEED_SUPER_PLUS: 2147 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2148 break; 2149 case USB_SPEED_FULL: 2150 /* XXX using 64 as initial mps of ep0 in FS */ 2151 case USB_SPEED_HIGH: 2152 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2153 break; 2154 case USB_SPEED_LOW: 2155 default: 2156 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2157 break; 2158 } 2159 dev->ud_ep0desc.bInterval = 0; 2160 2161 /* doesn't matter, just don't let it uninitialized */ 2162 dev->ud_ep0.ue_toggle = 0; 2163 2164 DPRINTFN(4, "up %p portno %d", up, up->up_portno, 0, 0); 2165 2166 dev->ud_quirks = &usbd_no_quirk; 2167 dev->ud_addr = 0; 2168 dev->ud_ddesc.bMaxPacketSize = 0; 2169 dev->ud_depth = depth; 2170 dev->ud_powersrc = up; 2171 dev->ud_myhub = up->up_parent; 2172 2173 up->up_dev = dev; 2174 2175 /* Locate root hub port */ 2176 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2177 uint32_t dep; 2178 2179 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2180 hub, hub->ud_depth, hub->ud_powersrc, 2181 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2182 2183 if (hub->ud_powersrc == NULL) 2184 break; 2185 dep = hub->ud_depth; 2186 if (dep == 0) 2187 break; 2188 rhport = hub->ud_powersrc->up_portno; 2189 if (dep > USB_HUB_MAX_DEPTH) 2190 continue; 2191 2192 route |= 2193 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2194 << ((dep - 1) * 4); 2195 } 2196 route = route >> 4; 2197 DPRINTFN(4, "rhport %d Route %05x hub %p", rhport, route, hub, 0); 2198 2199 /* Locate port on upstream high speed hub */ 2200 for (adev = dev, hub = up->up_parent; 2201 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2202 adev = hub, hub = hub->ud_myhub) 2203 ; 2204 if (hub) { 2205 int p; 2206 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2207 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2208 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2209 goto found; 2210 } 2211 } 2212 panic("xhci_new_device: cannot find HS port"); 2213 found: 2214 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2215 } else { 2216 dev->ud_myhsport = NULL; 2217 } 2218 2219 dev->ud_speed = speed; 2220 dev->ud_langid = USBD_NOLANG; 2221 dev->ud_cookie.cookie = ++usb_cookie_no; 2222 2223 /* Establish the default pipe. */ 2224 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2225 &dev->ud_pipe0); 2226 if (err) { 2227 goto bad; 2228 } 2229 2230 dd = &dev->ud_ddesc; 2231 2232 if ((depth == 0) && (port == 0)) { 2233 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2234 bus->ub_devices[dev->ud_addr] = dev; 2235 err = usbd_get_initial_ddesc(dev, dd); 2236 if (err) 2237 goto bad; 2238 err = usbd_reload_device_desc(dev); 2239 if (err) 2240 goto bad; 2241 } else { 2242 err = xhci_enable_slot(sc, &slot); 2243 if (err) 2244 goto bad; 2245 xs = &sc->sc_slots[slot]; 2246 dev->ud_hcpriv = xs; 2247 err = xhci_init_slot(dev, slot, route, rhport); 2248 if (err) { 2249 dev->ud_hcpriv = NULL; 2250 /* 2251 * We have to disable_slot here because 2252 * xs->xs_idx == 0 when xhci_init_slot fails, 2253 * in that case usbd_remove_dev won't work. 2254 */ 2255 mutex_enter(&sc->sc_lock); 2256 xhci_disable_slot(sc, slot); 2257 mutex_exit(&sc->sc_lock); 2258 goto bad; 2259 } 2260 2261 /* Allow device time to set new address */ 2262 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2263 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2264 //hexdump("slot context", cp, sc->sc_ctxsz); 2265 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2266 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2267 /* XXX ensure we know when the hardware does something 2268 we can't yet cope with */ 2269 KASSERT(addr >= 1 && addr <= 127); 2270 dev->ud_addr = addr; 2271 /* XXX dev->ud_addr not necessarily unique on bus */ 2272 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2273 bus->ub_devices[dev->ud_addr] = dev; 2274 2275 err = usbd_get_initial_ddesc(dev, dd); 2276 if (err) 2277 goto bad; 2278 /* 4.8.2.1 */ 2279 if (USB_IS_SS(speed)) { 2280 if (dd->bMaxPacketSize != 9) { 2281 printf("%s: invalid mps 2^%u for SS ep0," 2282 " using 512\n", 2283 device_xname(sc->sc_dev), 2284 dd->bMaxPacketSize); 2285 dd->bMaxPacketSize = 9; 2286 } 2287 USETW(dev->ud_ep0desc.wMaxPacketSize, 2288 (1 << dd->bMaxPacketSize)); 2289 } else 2290 USETW(dev->ud_ep0desc.wMaxPacketSize, 2291 dd->bMaxPacketSize); 2292 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2293 xhci_update_ep0_mps(sc, xs, 2294 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2295 err = usbd_reload_device_desc(dev); 2296 if (err) 2297 goto bad; 2298 2299 #if 0 2300 /* Re-establish the default pipe with the new MPS. */ 2301 /* In xhci this is done by xhci_update_ep0_mps. */ 2302 usbd_kill_pipe(dev->ud_pipe0); 2303 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2304 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2305 #endif 2306 } 2307 2308 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2309 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2310 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2311 dd->bDeviceClass, dd->bDeviceSubClass, 2312 dd->bDeviceProtocol, 0); 2313 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2314 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2315 dev->ud_speed); 2316 2317 usbd_get_device_strings(dev); 2318 2319 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2320 2321 if ((depth == 0) && (port == 0)) { 2322 usbd_attach_roothub(parent, dev); 2323 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2324 return USBD_NORMAL_COMPLETION; 2325 } 2326 2327 2328 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2329 bad: 2330 if (err != USBD_NORMAL_COMPLETION) { 2331 usbd_remove_device(dev, up); 2332 } 2333 2334 return err; 2335 } 2336 2337 static usbd_status 2338 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2339 size_t ntrb, size_t align) 2340 { 2341 usbd_status err; 2342 size_t size = ntrb * XHCI_TRB_SIZE; 2343 2344 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2345 2346 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2347 if (err) 2348 return err; 2349 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2350 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2351 xr->xr_trb = xhci_ring_trbv(xr, 0); 2352 xr->xr_ntrb = ntrb; 2353 xr->xr_ep = 0; 2354 xr->xr_cs = 1; 2355 memset(xr->xr_trb, 0, size); 2356 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 2357 xr->is_halted = false; 2358 2359 return USBD_NORMAL_COMPLETION; 2360 } 2361 2362 static void 2363 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2364 { 2365 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2366 mutex_destroy(&xr->xr_lock); 2367 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2368 } 2369 2370 static void 2371 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2372 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2373 { 2374 size_t i; 2375 u_int ri; 2376 u_int cs; 2377 uint64_t parameter; 2378 uint32_t status; 2379 uint32_t control; 2380 2381 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2382 2383 KASSERT(ntrbs <= XHCI_XFER_NTRB); 2384 for (i = 0; i < ntrbs; i++) { 2385 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2386 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2387 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2388 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2389 XHCI_TRB_TYPE_LINK); 2390 } 2391 2392 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2393 2394 ri = xr->xr_ep; 2395 cs = xr->xr_cs; 2396 2397 /* 2398 * Although the xhci hardware can do scatter/gather dma from 2399 * arbitrary sized buffers, there is a non-obvious restriction 2400 * that a LINK trb is only allowed at the end of a burst of 2401 * transfers - which might be 16kB. 2402 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2403 * The simple solution is not to allow a LINK trb in the middle 2404 * of anything - as here. 2405 * XXX: (dsl) There are xhci controllers out there (eg some made by 2406 * ASMedia) that seem to lock up if they process a LINK trb but 2407 * cannot process the linked-to trb yet. 2408 * The code should write the 'cycle' bit on the link trb AFTER 2409 * adding the other trb. 2410 */ 2411 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2412 parameter = xhci_ring_trbp(xr, 0); 2413 status = 0; 2414 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2415 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2416 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2417 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2418 BUS_DMASYNC_PREWRITE); 2419 xr->xr_cookies[ri] = NULL; 2420 xr->xr_ep = 0; 2421 xr->xr_cs ^= 1; 2422 ri = xr->xr_ep; 2423 cs = xr->xr_cs; 2424 } 2425 2426 ri++; 2427 2428 /* Write any subsequent TRB first */ 2429 for (i = 1; i < ntrbs; i++) { 2430 parameter = trbs[i].trb_0; 2431 status = trbs[i].trb_2; 2432 control = trbs[i].trb_3; 2433 2434 if (cs) { 2435 control |= XHCI_TRB_3_CYCLE_BIT; 2436 } else { 2437 control &= ~XHCI_TRB_3_CYCLE_BIT; 2438 } 2439 2440 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2441 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2442 BUS_DMASYNC_PREWRITE); 2443 xr->xr_cookies[ri] = cookie; 2444 ri++; 2445 } 2446 2447 /* Write the first TRB last */ 2448 i = 0; 2449 parameter = trbs[i].trb_0; 2450 status = trbs[i].trb_2; 2451 control = trbs[i].trb_3; 2452 2453 if (xr->xr_cs) { 2454 control |= XHCI_TRB_3_CYCLE_BIT; 2455 } else { 2456 control &= ~XHCI_TRB_3_CYCLE_BIT; 2457 } 2458 2459 xhci_trb_put(&xr->xr_trb[xr->xr_ep], parameter, status, control); 2460 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2461 BUS_DMASYNC_PREWRITE); 2462 xr->xr_cookies[xr->xr_ep] = cookie; 2463 2464 xr->xr_ep = ri; 2465 xr->xr_cs = cs; 2466 2467 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2468 } 2469 2470 /* 2471 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2472 * Command completion is notified by cv_signal from xhci_handle_event 2473 * (called from interrupt from xHCI), or timed-out. 2474 * Command validation is performed in xhci_handle_event by checking if 2475 * trb_0 in CMD_COMPLETE TRB and sc->sc_command_addr are identical. 2476 */ 2477 static usbd_status 2478 xhci_do_command_locked(struct xhci_softc * const sc, struct xhci_trb * const trb, 2479 int timeout) 2480 { 2481 struct xhci_ring * const cr = &sc->sc_cr; 2482 usbd_status err; 2483 2484 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2485 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2486 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2487 2488 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2489 KASSERT(mutex_owned(&sc->sc_lock)); 2490 2491 /* XXX KASSERT may fire when cv_timedwait unlocks sc_lock */ 2492 KASSERT(sc->sc_command_addr == 0); 2493 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2494 2495 mutex_enter(&cr->xr_lock); 2496 xhci_ring_put(sc, cr, NULL, trb, 1); 2497 mutex_exit(&cr->xr_lock); 2498 2499 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2500 2501 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2502 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2503 err = USBD_TIMEOUT; 2504 goto timedout; 2505 } 2506 2507 trb->trb_0 = sc->sc_result_trb.trb_0; 2508 trb->trb_2 = sc->sc_result_trb.trb_2; 2509 trb->trb_3 = sc->sc_result_trb.trb_3; 2510 2511 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2512 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2513 2514 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2515 case XHCI_TRB_ERROR_SUCCESS: 2516 err = USBD_NORMAL_COMPLETION; 2517 break; 2518 default: 2519 case 192 ... 223: 2520 err = USBD_IOERROR; 2521 break; 2522 case 224 ... 255: 2523 err = USBD_NORMAL_COMPLETION; 2524 break; 2525 } 2526 2527 timedout: 2528 sc->sc_command_addr = 0; 2529 return err; 2530 } 2531 2532 static usbd_status 2533 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2534 int timeout) 2535 { 2536 2537 mutex_enter(&sc->sc_lock); 2538 int ret = xhci_do_command_locked(sc, trb, timeout); 2539 mutex_exit(&sc->sc_lock); 2540 2541 return ret; 2542 } 2543 2544 static usbd_status 2545 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2546 { 2547 struct xhci_trb trb; 2548 usbd_status err; 2549 2550 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2551 2552 trb.trb_0 = 0; 2553 trb.trb_2 = 0; 2554 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2555 2556 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2557 if (err != USBD_NORMAL_COMPLETION) { 2558 return err; 2559 } 2560 2561 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2562 2563 return err; 2564 } 2565 2566 /* 2567 * Deallocate DMA buffer and ring buffer, and disable_slot. 2568 * Should be called with sc_lock held. 2569 */ 2570 static usbd_status 2571 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2572 { 2573 struct xhci_trb trb; 2574 struct xhci_slot *xs; 2575 usbd_status err; 2576 2577 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2578 2579 if (sc->sc_dying) 2580 return USBD_IOERROR; 2581 2582 trb.trb_0 = 0; 2583 trb.trb_2 = 0; 2584 trb.trb_3 = htole32( 2585 XHCI_TRB_3_SLOT_SET(slot) | 2586 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2587 2588 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2589 2590 if (!err) { 2591 xs = &sc->sc_slots[slot]; 2592 if (xs->xs_idx != 0) { 2593 for (int i = XHCI_DCI_SLOT + 1; i < 32; i++) { 2594 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2595 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2596 } 2597 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2598 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2599 xhci_set_dcba(sc, 0, slot); 2600 memset(xs, 0, sizeof(*xs)); 2601 } 2602 } 2603 2604 return err; 2605 } 2606 2607 /* 2608 * Change slot state. 2609 * bsr=0: ENABLED -> ADDRESSED 2610 * bsr=1: ENABLED -> DEFAULT 2611 * see xHCI 1.1 4.5.3, 3.3.4 2612 */ 2613 static usbd_status 2614 xhci_address_device(struct xhci_softc * const sc, 2615 uint64_t icp, uint8_t slot_id, bool bsr) 2616 { 2617 struct xhci_trb trb; 2618 usbd_status err; 2619 2620 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2621 2622 trb.trb_0 = icp; 2623 trb.trb_2 = 0; 2624 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2625 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2626 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2627 2628 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2629 2630 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2631 err = USBD_NO_ADDR; 2632 2633 return err; 2634 } 2635 2636 static usbd_status 2637 xhci_update_ep0_mps(struct xhci_softc * const sc, 2638 struct xhci_slot * const xs, u_int mps) 2639 { 2640 struct xhci_trb trb; 2641 usbd_status err; 2642 uint32_t * cp; 2643 2644 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2645 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2646 2647 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2648 cp[0] = htole32(0); 2649 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2650 2651 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2652 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2653 2654 /* sync input contexts before they are read from memory */ 2655 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2656 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2657 sc->sc_ctxsz * 4); 2658 2659 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2660 trb.trb_2 = 0; 2661 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2662 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2663 2664 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2665 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2666 return err; 2667 } 2668 2669 static void 2670 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2671 { 2672 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2673 2674 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2675 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2676 &dcbaa[si], dcba, si, 0); 2677 2678 dcbaa[si] = htole64(dcba); 2679 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2680 BUS_DMASYNC_PREWRITE); 2681 } 2682 2683 /* 2684 * Allocate DMA buffer and ring buffer for specified slot 2685 * and set Device Context Base Address 2686 * and issue Set Address device command. 2687 */ 2688 static usbd_status 2689 xhci_init_slot(struct usbd_device *dev, uint32_t slot, uint32_t route, int rhport) 2690 { 2691 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2692 struct xhci_slot *xs; 2693 usbd_status err; 2694 u_int dci; 2695 uint32_t *cp; 2696 uint32_t mps = UGETW(dev->ud_ep0desc.wMaxPacketSize); 2697 2698 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2699 DPRINTFN(4, "slot %u speed %d route %05x rhport %d", 2700 slot, dev->ud_speed, route, rhport); 2701 2702 xs = &sc->sc_slots[slot]; 2703 2704 /* allocate contexts */ 2705 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2706 &xs->xs_dc_dma); 2707 if (err) 2708 return err; 2709 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2710 2711 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2712 &xs->xs_ic_dma); 2713 if (err) 2714 goto bad1; 2715 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2716 2717 for (dci = 0; dci < 32; dci++) { 2718 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2719 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2720 if (dci == XHCI_DCI_SLOT) 2721 continue; 2722 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2723 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2724 if (err) { 2725 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2726 goto bad2; 2727 } 2728 } 2729 2730 /* set up initial input control context */ 2731 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2732 cp[0] = htole32(0); 2733 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 2734 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2735 2736 /* set up input slot context */ 2737 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2738 xhci_setup_sctx(dev, cp); 2739 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(1)); 2740 cp[0] |= htole32(XHCI_SCTX_0_ROUTE_SET(route)); 2741 cp[1] |= htole32(XHCI_SCTX_1_RH_PORT_SET(rhport)); 2742 2743 /* set up input EP0 context */ 2744 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2745 cp[0] = htole32(0); 2746 cp[1] = htole32( 2747 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 2748 XHCI_EPCTX_1_EPTYPE_SET(4) | 2749 XHCI_EPCTX_1_CERR_SET(3) 2750 ); 2751 /* can't use xhci_ep_get_dci() yet? */ 2752 *(uint64_t *)(&cp[2]) = htole64( 2753 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 2754 XHCI_EPCTX_2_DCS_SET(1)); 2755 cp[4] = htole32( 2756 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 2757 ); 2758 2759 /* sync input contexts before they are read from memory */ 2760 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2761 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2762 sc->sc_ctxsz * 3); 2763 2764 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2765 2766 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 2767 false); 2768 2769 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2770 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2771 sc->sc_ctxsz * 2); 2772 2773 bad2: 2774 if (err == USBD_NORMAL_COMPLETION) { 2775 xs->xs_idx = slot; 2776 } else { 2777 for (int i = 1; i < dci; i++) { 2778 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2779 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2780 } 2781 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2782 bad1: 2783 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2784 xs->xs_idx = 0; 2785 } 2786 2787 return err; 2788 } 2789 2790 /* ----- */ 2791 2792 static void 2793 xhci_noop(struct usbd_pipe *pipe) 2794 { 2795 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2796 } 2797 2798 /* 2799 * Process root hub request. 2800 */ 2801 static int 2802 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2803 void *buf, int buflen) 2804 { 2805 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2806 usb_port_status_t ps; 2807 int l, totlen = 0; 2808 uint16_t len, value, index; 2809 int port, i; 2810 uint32_t v; 2811 2812 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2813 2814 if (sc->sc_dying) 2815 return -1; 2816 2817 len = UGETW(req->wLength); 2818 value = UGETW(req->wValue); 2819 index = UGETW(req->wIndex); 2820 2821 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 2822 req->bmRequestType | (req->bRequest << 8), value, index, len); 2823 2824 #define C(x,y) ((x) | ((y) << 8)) 2825 switch (C(req->bRequest, req->bmRequestType)) { 2826 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2827 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 2828 if (len == 0) 2829 break; 2830 switch (value) { 2831 case C(0, UDESC_DEVICE): { 2832 usb_device_descriptor_t devd; 2833 totlen = min(buflen, sizeof(devd)); 2834 memcpy(&devd, buf, totlen); 2835 USETW(devd.idVendor, sc->sc_id_vendor); 2836 memcpy(buf, &devd, totlen); 2837 break; 2838 } 2839 #define sd ((usb_string_descriptor_t *)buf) 2840 case C(1, UDESC_STRING): 2841 /* Vendor */ 2842 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2843 break; 2844 case C(2, UDESC_STRING): 2845 /* Product */ 2846 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 2847 break; 2848 #undef sd 2849 default: 2850 /* default from usbroothub */ 2851 return buflen; 2852 } 2853 break; 2854 2855 /* Hub requests */ 2856 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2857 break; 2858 /* Clear Port Feature request */ 2859 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2860 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2861 index, value, 0, 0); 2862 if (index < 1 || index > sc->sc_maxports) { 2863 return -1; 2864 } 2865 port = XHCI_PORTSC(index); 2866 v = xhci_op_read_4(sc, port); 2867 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2868 v &= ~XHCI_PS_CLEAR; 2869 switch (value) { 2870 case UHF_PORT_ENABLE: 2871 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 2872 break; 2873 case UHF_PORT_SUSPEND: 2874 return -1; 2875 case UHF_PORT_POWER: 2876 break; 2877 case UHF_PORT_TEST: 2878 case UHF_PORT_INDICATOR: 2879 return -1; 2880 case UHF_C_PORT_CONNECTION: 2881 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2882 break; 2883 case UHF_C_PORT_ENABLE: 2884 case UHF_C_PORT_SUSPEND: 2885 case UHF_C_PORT_OVER_CURRENT: 2886 return -1; 2887 case UHF_C_BH_PORT_RESET: 2888 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 2889 break; 2890 case UHF_C_PORT_RESET: 2891 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2892 break; 2893 case UHF_C_PORT_LINK_STATE: 2894 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 2895 break; 2896 case UHF_C_PORT_CONFIG_ERROR: 2897 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 2898 break; 2899 default: 2900 return -1; 2901 } 2902 break; 2903 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2904 if (len == 0) 2905 break; 2906 if ((value & 0xff) != 0) { 2907 return -1; 2908 } 2909 usb_hub_descriptor_t hubd; 2910 2911 totlen = min(buflen, sizeof(hubd)); 2912 memcpy(&hubd, buf, totlen); 2913 hubd.bNbrPorts = sc->sc_maxports; 2914 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2915 hubd.bPwrOn2PwrGood = 200; 2916 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 2917 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2918 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2919 totlen = min(totlen, hubd.bDescLength); 2920 memcpy(buf, &hubd, totlen); 2921 break; 2922 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2923 if (len != 4) { 2924 return -1; 2925 } 2926 memset(buf, 0, len); /* ? XXX */ 2927 totlen = len; 2928 break; 2929 /* Get Port Status request */ 2930 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2931 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2932 if (index < 1 || index > sc->sc_maxports) { 2933 return -1; 2934 } 2935 if (len != 4) { 2936 return -1; 2937 } 2938 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 2939 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 2940 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 2941 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2942 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2943 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2944 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 2945 if (v & XHCI_PS_PR) i |= UPS_RESET; 2946 if (v & XHCI_PS_PP) { 2947 if (i & UPS_OTHER_SPEED) 2948 i |= UPS_PORT_POWER_SS; 2949 else 2950 i |= UPS_PORT_POWER; 2951 } 2952 if (i & UPS_OTHER_SPEED) 2953 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 2954 if (sc->sc_vendor_port_status) 2955 i = sc->sc_vendor_port_status(sc, v, i); 2956 USETW(ps.wPortStatus, i); 2957 i = 0; 2958 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2959 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2960 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2961 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2962 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 2963 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 2964 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 2965 USETW(ps.wPortChange, i); 2966 totlen = min(len, sizeof(ps)); 2967 memcpy(buf, &ps, totlen); 2968 break; 2969 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2970 return -1; 2971 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 2972 break; 2973 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2974 break; 2975 /* Set Port Feature request */ 2976 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 2977 int optval = (index >> 8) & 0xff; 2978 index &= 0xff; 2979 if (index < 1 || index > sc->sc_maxports) { 2980 return -1; 2981 } 2982 port = XHCI_PORTSC(index); 2983 v = xhci_op_read_4(sc, port); 2984 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2985 v &= ~XHCI_PS_CLEAR; 2986 switch (value) { 2987 case UHF_PORT_ENABLE: 2988 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 2989 break; 2990 case UHF_PORT_SUSPEND: 2991 /* XXX suspend */ 2992 break; 2993 case UHF_PORT_RESET: 2994 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 2995 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 2996 /* Wait for reset to complete. */ 2997 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2998 if (sc->sc_dying) { 2999 return -1; 3000 } 3001 v = xhci_op_read_4(sc, port); 3002 if (v & XHCI_PS_PR) { 3003 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3004 usb_delay_ms(&sc->sc_bus, 10); 3005 /* XXX */ 3006 } 3007 break; 3008 case UHF_PORT_POWER: 3009 /* XXX power control */ 3010 break; 3011 /* XXX more */ 3012 case UHF_C_PORT_RESET: 3013 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3014 break; 3015 case UHF_PORT_U1_TIMEOUT: 3016 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3017 return -1; 3018 } 3019 port = XHCI_PORTPMSC(index); 3020 v = xhci_op_read_4(sc, port); 3021 v &= ~XHCI_PM3_U1TO_SET(0xff); 3022 v |= XHCI_PM3_U1TO_SET(optval); 3023 xhci_op_write_4(sc, port, v); 3024 break; 3025 case UHF_PORT_U2_TIMEOUT: 3026 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3027 return -1; 3028 } 3029 port = XHCI_PORTPMSC(index); 3030 v = xhci_op_read_4(sc, port); 3031 v &= ~XHCI_PM3_U2TO_SET(0xff); 3032 v |= XHCI_PM3_U2TO_SET(optval); 3033 xhci_op_write_4(sc, port, v); 3034 break; 3035 default: 3036 return -1; 3037 } 3038 } 3039 break; 3040 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3041 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3042 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3043 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3044 break; 3045 default: 3046 /* default from usbroothub */ 3047 return buflen; 3048 } 3049 3050 return totlen; 3051 } 3052 3053 /* root hub interrupt */ 3054 3055 static usbd_status 3056 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3057 { 3058 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3059 usbd_status err; 3060 3061 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3062 3063 /* Insert last in queue. */ 3064 mutex_enter(&sc->sc_lock); 3065 err = usb_insert_transfer(xfer); 3066 mutex_exit(&sc->sc_lock); 3067 if (err) 3068 return err; 3069 3070 /* Pipe isn't running, start first */ 3071 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3072 } 3073 3074 /* Wait for roothub port status/change */ 3075 static usbd_status 3076 xhci_root_intr_start(struct usbd_xfer *xfer) 3077 { 3078 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3079 3080 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3081 3082 if (sc->sc_dying) 3083 return USBD_IOERROR; 3084 3085 mutex_enter(&sc->sc_lock); 3086 sc->sc_intrxfer = xfer; 3087 mutex_exit(&sc->sc_lock); 3088 3089 return USBD_IN_PROGRESS; 3090 } 3091 3092 static void 3093 xhci_root_intr_abort(struct usbd_xfer *xfer) 3094 { 3095 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3096 3097 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3098 3099 KASSERT(mutex_owned(&sc->sc_lock)); 3100 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3101 3102 sc->sc_intrxfer = NULL; 3103 3104 xfer->ux_status = USBD_CANCELLED; 3105 usb_transfer_complete(xfer); 3106 } 3107 3108 static void 3109 xhci_root_intr_close(struct usbd_pipe *pipe) 3110 { 3111 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3112 3113 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3114 3115 KASSERT(mutex_owned(&sc->sc_lock)); 3116 3117 sc->sc_intrxfer = NULL; 3118 } 3119 3120 static void 3121 xhci_root_intr_done(struct usbd_xfer *xfer) 3122 { 3123 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3124 3125 } 3126 3127 /* -------------- */ 3128 /* device control */ 3129 3130 static usbd_status 3131 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3132 { 3133 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3134 usbd_status err; 3135 3136 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3137 3138 /* Insert last in queue. */ 3139 mutex_enter(&sc->sc_lock); 3140 err = usb_insert_transfer(xfer); 3141 mutex_exit(&sc->sc_lock); 3142 if (err) 3143 return err; 3144 3145 /* Pipe isn't running, start first */ 3146 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3147 } 3148 3149 static usbd_status 3150 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3151 { 3152 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3153 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3154 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3155 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3156 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3157 usb_device_request_t * const req = &xfer->ux_request; 3158 const int isread = usbd_xfer_isread(xfer); 3159 const uint32_t len = UGETW(req->wLength); 3160 usb_dma_t * const dma = &xfer->ux_dmabuf; 3161 uint64_t parameter; 3162 uint32_t status; 3163 uint32_t control; 3164 u_int i; 3165 3166 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3167 DPRINTFN(12, "req: %04x %04x %04x %04x", 3168 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3169 UGETW(req->wIndex), UGETW(req->wLength)); 3170 3171 #if 0 /* event handler does this */ 3172 /* XXX */ 3173 if (tr->is_halted) { 3174 DPRINTFN(1, "ctrl xfer %p halted: slot %u dci %u", 3175 xfer, xs->xs_idx, dci, 0); 3176 xhci_reset_endpoint(xfer->ux_pipe); 3177 tr->is_halted = false; 3178 xhci_set_dequeue(xfer->ux_pipe); 3179 } 3180 #endif 3181 3182 /* we rely on the bottom bits for extra info */ 3183 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 3184 3185 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3186 3187 i = 0; 3188 3189 /* setup phase */ 3190 memcpy(¶meter, req, sizeof(*req)); 3191 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3192 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3193 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3194 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3195 XHCI_TRB_3_IDT_BIT; 3196 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3197 3198 if (len != 0) { 3199 /* data phase */ 3200 parameter = DMAADDR(dma, 0); 3201 KASSERT(len <= 0x10000); 3202 status = XHCI_TRB_2_IRQ_SET(0) | 3203 XHCI_TRB_2_TDSZ_SET(1) | 3204 XHCI_TRB_2_BYTES_SET(len); 3205 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3206 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3207 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3208 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3209 3210 parameter = (uintptr_t)xfer | 0x3; 3211 status = XHCI_TRB_2_IRQ_SET(0); 3212 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3213 XHCI_TRB_3_IOC_BIT; 3214 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3215 } 3216 3217 parameter = 0; 3218 status = XHCI_TRB_2_IRQ_SET(0); 3219 /* the status stage has inverted direction */ 3220 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3221 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3222 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3223 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3224 3225 parameter = (uintptr_t)xfer | 0x0; 3226 status = XHCI_TRB_2_IRQ_SET(0); 3227 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3228 XHCI_TRB_3_IOC_BIT; 3229 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3230 3231 mutex_enter(&tr->xr_lock); 3232 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3233 mutex_exit(&tr->xr_lock); 3234 3235 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3236 3237 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3238 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3239 xhci_timeout, xfer); 3240 } 3241 3242 if (sc->sc_bus.ub_usepolling) { 3243 DPRINTFN(1, "polling", 0, 0, 0, 0); 3244 //xhci_waitintr(sc, xfer); 3245 } 3246 3247 return USBD_IN_PROGRESS; 3248 } 3249 3250 static void 3251 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3252 { 3253 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3254 usb_device_request_t *req = &xfer->ux_request; 3255 int len = UGETW(req->wLength); 3256 int rd = req->bmRequestType & UT_READ; 3257 3258 if (len) 3259 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3260 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3261 } 3262 3263 static void 3264 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3265 { 3266 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3267 3268 xhci_abort_xfer(xfer, USBD_CANCELLED); 3269 } 3270 3271 static void 3272 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3273 { 3274 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3275 3276 xhci_close_pipe(pipe); 3277 } 3278 3279 /* ------------------ */ 3280 /* device isochronous */ 3281 3282 /* ----------- */ 3283 /* device bulk */ 3284 3285 static usbd_status 3286 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3287 { 3288 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3289 usbd_status err; 3290 3291 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3292 3293 /* Insert last in queue. */ 3294 mutex_enter(&sc->sc_lock); 3295 err = usb_insert_transfer(xfer); 3296 mutex_exit(&sc->sc_lock); 3297 if (err) 3298 return err; 3299 3300 /* 3301 * Pipe isn't running (otherwise err would be USBD_INPROG), 3302 * so start it first. 3303 */ 3304 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3305 } 3306 3307 static usbd_status 3308 xhci_device_bulk_start(struct usbd_xfer *xfer) 3309 { 3310 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3311 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3312 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3313 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3314 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3315 const uint32_t len = xfer->ux_length; 3316 usb_dma_t * const dma = &xfer->ux_dmabuf; 3317 uint64_t parameter; 3318 uint32_t status; 3319 uint32_t control; 3320 u_int i = 0; 3321 3322 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3323 3324 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3325 3326 if (sc->sc_dying) 3327 return USBD_IOERROR; 3328 3329 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3330 3331 parameter = DMAADDR(dma, 0); 3332 /* 3333 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3334 * If the user supplied buffer crosses such a boundary then 2 3335 * (or more) TRB should be used. 3336 * If multiple TRB are used the td_size field must be set correctly. 3337 * For v1.0 devices (like ivy bridge) this is the number of usb data 3338 * blocks needed to complete the transfer. 3339 * Setting it to 1 in the last TRB causes an extra zero-length 3340 * data block be sent. 3341 * The earlier documentation differs, I don't know how it behaves. 3342 */ 3343 KASSERT(len <= 0x10000); 3344 status = XHCI_TRB_2_IRQ_SET(0) | 3345 XHCI_TRB_2_TDSZ_SET(1) | 3346 XHCI_TRB_2_BYTES_SET(len); 3347 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3348 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3349 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3350 3351 mutex_enter(&tr->xr_lock); 3352 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3353 mutex_exit(&tr->xr_lock); 3354 3355 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3356 3357 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3358 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3359 xhci_timeout, xfer); 3360 } 3361 3362 if (sc->sc_bus.ub_usepolling) { 3363 DPRINTFN(1, "polling", 0, 0, 0, 0); 3364 //xhci_waitintr(sc, xfer); 3365 } 3366 3367 return USBD_IN_PROGRESS; 3368 } 3369 3370 static void 3371 xhci_device_bulk_done(struct usbd_xfer *xfer) 3372 { 3373 #ifdef USB_DEBUG 3374 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3375 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3376 #endif 3377 const int isread = usbd_xfer_isread(xfer); 3378 3379 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3380 3381 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3382 3383 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3384 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3385 } 3386 3387 static void 3388 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3389 { 3390 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3391 3392 xhci_abort_xfer(xfer, USBD_CANCELLED); 3393 } 3394 3395 static void 3396 xhci_device_bulk_close(struct usbd_pipe *pipe) 3397 { 3398 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3399 3400 xhci_close_pipe(pipe); 3401 } 3402 3403 /* ---------------- */ 3404 /* device interrupt */ 3405 3406 static usbd_status 3407 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3408 { 3409 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3410 usbd_status err; 3411 3412 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3413 3414 /* Insert last in queue. */ 3415 mutex_enter(&sc->sc_lock); 3416 err = usb_insert_transfer(xfer); 3417 mutex_exit(&sc->sc_lock); 3418 if (err) 3419 return err; 3420 3421 /* 3422 * Pipe isn't running (otherwise err would be USBD_INPROG), 3423 * so start it first. 3424 */ 3425 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3426 } 3427 3428 static usbd_status 3429 xhci_device_intr_start(struct usbd_xfer *xfer) 3430 { 3431 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3432 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3433 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3434 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3435 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3436 const uint32_t len = xfer->ux_length; 3437 usb_dma_t * const dma = &xfer->ux_dmabuf; 3438 uint64_t parameter; 3439 uint32_t status; 3440 uint32_t control; 3441 u_int i = 0; 3442 3443 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3444 3445 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3446 3447 if (sc->sc_dying) 3448 return USBD_IOERROR; 3449 3450 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3451 3452 parameter = DMAADDR(dma, 0); 3453 KASSERT(len <= 0x10000); 3454 status = XHCI_TRB_2_IRQ_SET(0) | 3455 XHCI_TRB_2_TDSZ_SET(1) | 3456 XHCI_TRB_2_BYTES_SET(len); 3457 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3458 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3459 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3460 3461 mutex_enter(&tr->xr_lock); 3462 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3463 mutex_exit(&tr->xr_lock); 3464 3465 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3466 3467 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3468 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3469 xhci_timeout, xfer); 3470 } 3471 3472 if (sc->sc_bus.ub_usepolling) { 3473 DPRINTFN(1, "polling", 0, 0, 0, 0); 3474 //xhci_waitintr(sc, xfer); 3475 } 3476 3477 return USBD_IN_PROGRESS; 3478 } 3479 3480 static void 3481 xhci_device_intr_done(struct usbd_xfer *xfer) 3482 { 3483 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3484 #ifdef USB_DEBUG 3485 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3486 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3487 #endif 3488 const int isread = usbd_xfer_isread(xfer); 3489 3490 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3491 3492 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3493 3494 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3495 3496 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3497 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3498 3499 #if 0 3500 device_printf(sc->sc_dev, ""); 3501 for (size_t i = 0; i < xfer->ux_length; i++) { 3502 printf(" %02x", ((uint8_t const *)xfer->ux_buffer)[i]); 3503 } 3504 printf("\n"); 3505 #endif 3506 3507 } 3508 3509 static void 3510 xhci_device_intr_abort(struct usbd_xfer *xfer) 3511 { 3512 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3513 3514 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3515 3516 KASSERT(mutex_owned(&sc->sc_lock)); 3517 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3518 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3519 xhci_abort_xfer(xfer, USBD_CANCELLED); 3520 } 3521 3522 static void 3523 xhci_device_intr_close(struct usbd_pipe *pipe) 3524 { 3525 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3526 3527 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3528 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3529 3530 xhci_close_pipe(pipe); 3531 } 3532 3533 /* ------------ */ 3534 3535 static void 3536 xhci_timeout(void *addr) 3537 { 3538 struct xhci_xfer * const xx = addr; 3539 struct usbd_xfer * const xfer = &xx->xx_xfer; 3540 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3541 3542 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3543 3544 if (sc->sc_dying) { 3545 return; 3546 } 3547 3548 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 3549 USB_TASKQ_MPSAFE); 3550 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 3551 USB_TASKQ_HC); 3552 } 3553 3554 static void 3555 xhci_timeout_task(void *addr) 3556 { 3557 struct usbd_xfer * const xfer = addr; 3558 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3559 3560 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3561 3562 mutex_enter(&sc->sc_lock); 3563 #if 0 3564 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3565 #else 3566 xfer->ux_status = USBD_TIMEOUT; 3567 usb_transfer_complete(xfer); 3568 #endif 3569 mutex_exit(&sc->sc_lock); 3570 } 3571
Indexes created Tue Sep 23 02:09:52 GMT 2025