xhci.c revision 1.38
1 /* $NetBSD: xhci.c,v 1.38 2016/04/30 14:56:20 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 3.1 specification 31 * http://www.usb.org/developers/docs/usb_31_040315.zip 32 * USB rev 2.0 specification 33 * http://www.usb.org/developers/docs/usb20_docs/usb_20_031815.zip 34 * xHCI rev 1.1 specification 35 * http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/extensible-host-controler-interface-usb-xhci.pdf 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.38 2016/04/30 14:56:20 skrll Exp $"); 40 41 #include "opt_usb.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 146 147 static usbd_status xhci_do_command(struct xhci_softc * const, 148 struct xhci_trb * const, int); 149 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 150 struct xhci_trb * const, int); 151 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t, uint32_t, int); 152 static usbd_status xhci_enable_slot(struct xhci_softc * const, 153 uint8_t * const); 154 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 155 static usbd_status xhci_address_device(struct xhci_softc * const, 156 uint64_t, uint8_t, bool); 157 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 158 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 159 struct xhci_slot * const, u_int); 160 static usbd_status xhci_ring_init(struct xhci_softc * const, 161 struct xhci_ring * const, size_t, size_t); 162 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 163 164 static void xhci_noop(struct usbd_pipe *); 165 166 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 167 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 168 static void xhci_root_intr_abort(struct usbd_xfer *); 169 static void xhci_root_intr_close(struct usbd_pipe *); 170 static void xhci_root_intr_done(struct usbd_xfer *); 171 172 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 173 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 174 static void xhci_device_ctrl_abort(struct usbd_xfer *); 175 static void xhci_device_ctrl_close(struct usbd_pipe *); 176 static void xhci_device_ctrl_done(struct usbd_xfer *); 177 178 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 179 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 180 static void xhci_device_intr_abort(struct usbd_xfer *); 181 static void xhci_device_intr_close(struct usbd_pipe *); 182 static void xhci_device_intr_done(struct usbd_xfer *); 183 184 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 185 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 186 static void xhci_device_bulk_abort(struct usbd_xfer *); 187 static void xhci_device_bulk_close(struct usbd_pipe *); 188 static void xhci_device_bulk_done(struct usbd_xfer *); 189 190 static void xhci_timeout(void *); 191 static void xhci_timeout_task(void *); 192 193 static const struct usbd_bus_methods xhci_bus_methods = { 194 .ubm_open = xhci_open, 195 .ubm_softint = xhci_softintr, 196 .ubm_dopoll = xhci_poll, 197 .ubm_allocx = xhci_allocx, 198 .ubm_freex = xhci_freex, 199 .ubm_getlock = xhci_get_lock, 200 .ubm_newdev = xhci_new_device, 201 .ubm_rhctrl = xhci_roothub_ctrl, 202 }; 203 204 static const struct usbd_pipe_methods xhci_root_intr_methods = { 205 .upm_transfer = xhci_root_intr_transfer, 206 .upm_start = xhci_root_intr_start, 207 .upm_abort = xhci_root_intr_abort, 208 .upm_close = xhci_root_intr_close, 209 .upm_cleartoggle = xhci_noop, 210 .upm_done = xhci_root_intr_done, 211 }; 212 213 214 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 215 .upm_transfer = xhci_device_ctrl_transfer, 216 .upm_start = xhci_device_ctrl_start, 217 .upm_abort = xhci_device_ctrl_abort, 218 .upm_close = xhci_device_ctrl_close, 219 .upm_cleartoggle = xhci_noop, 220 .upm_done = xhci_device_ctrl_done, 221 }; 222 223 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 224 .upm_cleartoggle = xhci_noop, 225 }; 226 227 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 228 .upm_transfer = xhci_device_bulk_transfer, 229 .upm_start = xhci_device_bulk_start, 230 .upm_abort = xhci_device_bulk_abort, 231 .upm_close = xhci_device_bulk_close, 232 .upm_cleartoggle = xhci_noop, 233 .upm_done = xhci_device_bulk_done, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_intr_methods = { 237 .upm_transfer = xhci_device_intr_transfer, 238 .upm_start = xhci_device_intr_start, 239 .upm_abort = xhci_device_intr_abort, 240 .upm_close = xhci_device_intr_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_intr_done, 243 }; 244 245 static inline uint32_t 246 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 247 { 248 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 249 } 250 251 static inline uint32_t 252 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 253 { 254 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 255 } 256 257 static inline void 258 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 259 uint32_t value) 260 { 261 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 262 } 263 264 #if 0 /* unused */ 265 static inline void 266 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 267 uint32_t value) 268 { 269 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 270 } 271 #endif /* unused */ 272 273 static inline uint32_t 274 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 275 { 276 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 277 } 278 279 static inline uint32_t 280 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 281 { 282 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 283 } 284 285 static inline void 286 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 287 uint32_t value) 288 { 289 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 290 } 291 292 #if 0 /* unused */ 293 static inline uint64_t 294 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 295 { 296 uint64_t value; 297 298 if (sc->sc_ac64) { 299 #ifdef XHCI_USE_BUS_SPACE_8 300 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 301 #else 302 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 303 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 304 offset + 4) << 32; 305 #endif 306 } else { 307 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 308 } 309 310 return value; 311 } 312 #endif /* unused */ 313 314 static inline void 315 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 316 uint64_t value) 317 { 318 if (sc->sc_ac64) { 319 #ifdef XHCI_USE_BUS_SPACE_8 320 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 321 #else 322 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 323 (value >> 0) & 0xffffffff); 324 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 325 (value >> 32) & 0xffffffff); 326 #endif 327 } else { 328 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 329 } 330 } 331 332 static inline uint32_t 333 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 334 { 335 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 336 } 337 338 static inline void 339 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 340 uint32_t value) 341 { 342 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 343 } 344 345 #if 0 /* unused */ 346 static inline uint64_t 347 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 348 { 349 uint64_t value; 350 351 if (sc->sc_ac64) { 352 #ifdef XHCI_USE_BUS_SPACE_8 353 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 354 #else 355 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 356 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 357 offset + 4) << 32; 358 #endif 359 } else { 360 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 361 } 362 363 return value; 364 } 365 #endif /* unused */ 366 367 static inline void 368 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 369 uint64_t value) 370 { 371 if (sc->sc_ac64) { 372 #ifdef XHCI_USE_BUS_SPACE_8 373 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 374 #else 375 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 376 (value >> 0) & 0xffffffff); 377 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 378 (value >> 32) & 0xffffffff); 379 #endif 380 } else { 381 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 382 } 383 } 384 385 #if 0 /* unused */ 386 static inline uint32_t 387 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 388 { 389 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 390 } 391 #endif /* unused */ 392 393 static inline void 394 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 395 uint32_t value) 396 { 397 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 398 } 399 400 /* --- */ 401 402 static inline uint8_t 403 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 404 { 405 u_int eptype = 0; 406 407 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 408 case UE_CONTROL: 409 eptype = 0x0; 410 break; 411 case UE_ISOCHRONOUS: 412 eptype = 0x1; 413 break; 414 case UE_BULK: 415 eptype = 0x2; 416 break; 417 case UE_INTERRUPT: 418 eptype = 0x3; 419 break; 420 } 421 422 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 423 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 424 return eptype | 0x4; 425 else 426 return eptype; 427 } 428 429 static u_int 430 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 431 { 432 /* xHCI 1.0 section 4.5.1 */ 433 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 434 u_int in = 0; 435 436 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 437 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 438 in = 1; 439 440 return epaddr * 2 + in; 441 } 442 443 static inline u_int 444 xhci_dci_to_ici(const u_int i) 445 { 446 return i + 1; 447 } 448 449 static inline void * 450 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 451 const u_int dci) 452 { 453 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 454 } 455 456 #if 0 /* unused */ 457 static inline bus_addr_t 458 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 459 const u_int dci) 460 { 461 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 462 } 463 #endif /* unused */ 464 465 static inline void * 466 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 467 const u_int ici) 468 { 469 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 470 } 471 472 static inline bus_addr_t 473 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline struct xhci_trb * 480 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 481 { 482 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 483 } 484 485 static inline bus_addr_t 486 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 487 { 488 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 489 } 490 491 static inline void 492 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 493 uint32_t control) 494 { 495 trb->trb_0 = htole64(parameter); 496 trb->trb_2 = htole32(status); 497 trb->trb_3 = htole32(control); 498 } 499 500 /* --- */ 501 502 void 503 xhci_childdet(device_t self, device_t child) 504 { 505 struct xhci_softc * const sc = device_private(self); 506 507 KASSERT(sc->sc_child == child); 508 if (child == sc->sc_child) 509 sc->sc_child = NULL; 510 } 511 512 int 513 xhci_detach(struct xhci_softc *sc, int flags) 514 { 515 int rv = 0; 516 517 if (sc->sc_child != NULL) 518 rv = config_detach(sc->sc_child, flags); 519 520 if (rv != 0) 521 return rv; 522 523 /* XXX unconfigure/free slots */ 524 525 /* verify: */ 526 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 527 xhci_op_write_4(sc, XHCI_USBCMD, 0); 528 /* do we need to wait for stop? */ 529 530 xhci_op_write_8(sc, XHCI_CRCR, 0); 531 xhci_ring_free(sc, &sc->sc_cr); 532 cv_destroy(&sc->sc_command_cv); 533 534 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 535 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 536 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 537 xhci_ring_free(sc, &sc->sc_er); 538 539 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 540 541 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 542 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 543 544 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 545 546 mutex_destroy(&sc->sc_lock); 547 mutex_destroy(&sc->sc_intr_lock); 548 cv_destroy(&sc->sc_softwake_cv); 549 550 pool_cache_destroy(sc->sc_xferpool); 551 552 return rv; 553 } 554 555 int 556 xhci_activate(device_t self, enum devact act) 557 { 558 struct xhci_softc * const sc = device_private(self); 559 560 switch (act) { 561 case DVACT_DEACTIVATE: 562 sc->sc_dying = true; 563 return 0; 564 default: 565 return EOPNOTSUPP; 566 } 567 } 568 569 bool 570 xhci_suspend(device_t dv, const pmf_qual_t *qual) 571 { 572 return false; 573 } 574 575 bool 576 xhci_resume(device_t dv, const pmf_qual_t *qual) 577 { 578 return false; 579 } 580 581 bool 582 xhci_shutdown(device_t self, int flags) 583 { 584 return false; 585 } 586 587 588 static void 589 hexdump(const char *msg, const void *base, size_t len) 590 { 591 #if 0 592 size_t cnt; 593 const uint32_t *p; 594 extern paddr_t vtophys(vaddr_t); 595 596 p = base; 597 cnt = 0; 598 599 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 600 (void *)vtophys((vaddr_t)base)); 601 602 while (cnt < len) { 603 if (cnt % 16 == 0) 604 printf("%p: ", p); 605 else if (cnt % 8 == 0) 606 printf(" |"); 607 printf(" %08x", *p++); 608 cnt += 4; 609 if (cnt % 16 == 0) 610 printf("\n"); 611 } 612 #endif 613 } 614 615 #define XHCI_HCCPREV1_BITS \ 616 "\177\020" /* New bitmask */ \ 617 "f\020\020XECP\0" \ 618 "f\014\4MAXPSA\0" \ 619 "b\013CFC\0" \ 620 "b\012SEC\0" \ 621 "b\011SBD\0" \ 622 "b\010FSE\0" \ 623 "b\7NSS\0" \ 624 "b\6LTC\0" \ 625 "b\5LHRC\0" \ 626 "b\4PIND\0" \ 627 "b\3PPC\0" \ 628 "b\2CZC\0" \ 629 "b\1BNC\0" \ 630 "b\0AC64\0" \ 631 "\0" 632 #define XHCI_HCCV1_x_BITS \ 633 "\177\020" /* New bitmask */ \ 634 "f\020\020XECP\0" \ 635 "f\014\4MAXPSA\0" \ 636 "b\013CFC\0" \ 637 "b\012SEC\0" \ 638 "b\011SPC\0" \ 639 "b\010PAE\0" \ 640 "b\7NSS\0" \ 641 "b\6LTC\0" \ 642 "b\5LHRC\0" \ 643 "b\4PIND\0" \ 644 "b\3PPC\0" \ 645 "b\2CSZ\0" \ 646 "b\1BNC\0" \ 647 "b\0AC64\0" \ 648 "\0" 649 650 int 651 xhci_init(struct xhci_softc *sc) 652 { 653 bus_size_t bsz; 654 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 655 uint32_t ecp, ecr; 656 uint32_t usbcmd, usbsts, pagesize, config; 657 int i; 658 uint16_t hciversion; 659 uint8_t caplength; 660 661 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 662 663 sc->sc_bus.ub_revision = USBREV_3_0; 664 sc->sc_bus.ub_usedma = true; 665 666 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 667 caplength = XHCI_CAP_CAPLENGTH(cap); 668 hciversion = XHCI_CAP_HCIVERSION(cap); 669 670 if (hciversion < XHCI_HCIVERSION_0_96 || 671 hciversion > XHCI_HCIVERSION_1_0) { 672 aprint_normal_dev(sc->sc_dev, 673 "xHCI version %x.%x not known to be supported\n", 674 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 675 } else { 676 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 677 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 678 } 679 680 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 681 &sc->sc_cbh) != 0) { 682 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 683 return ENOMEM; 684 } 685 686 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 687 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 688 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 689 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 690 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 691 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 692 aprint_debug_dev(sc->sc_dev, 693 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 694 695 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 696 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 697 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 698 699 char sbuf[128]; 700 if (hciversion < XHCI_HCIVERSION_1_0) 701 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 702 else 703 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 704 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 705 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 706 707 ecp = XHCI_HCC_XECP(hcc) * 4; 708 while (ecp != 0) { 709 ecr = xhci_read_4(sc, ecp); 710 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 711 switch (XHCI_XECP_ID(ecr)) { 712 case XHCI_ID_PROTOCOLS: { 713 uint32_t w0, w4, w8; 714 uint16_t w2; 715 w0 = xhci_read_4(sc, ecp + 0); 716 w2 = (w0 >> 16) & 0xffff; 717 w4 = xhci_read_4(sc, ecp + 4); 718 w8 = xhci_read_4(sc, ecp + 8); 719 aprint_debug_dev(sc->sc_dev, "SP: %08x %08x %08x\n", 720 w0, w4, w8); 721 if (w4 == 0x20425355 && w2 == 0x0300) { 722 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 723 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 724 } 725 if (w4 == 0x20425355 && w2 == 0x0200) { 726 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 727 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 728 } 729 break; 730 } 731 case XHCI_ID_USB_LEGACY: { 732 uint8_t bios_sem; 733 734 /* Take host controller from BIOS */ 735 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 736 if (bios_sem) { 737 /* sets xHCI to be owned by OS */ 738 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 739 aprint_debug( 740 "waiting for BIOS to give up control\n"); 741 for (i = 0; i < 5000; i++) { 742 bios_sem = xhci_read_1(sc, ecp + 743 XHCI_XECP_BIOS_SEM); 744 if (bios_sem == 0) 745 break; 746 DELAY(1000); 747 } 748 if (bios_sem) 749 printf("timed out waiting for BIOS\n"); 750 } 751 break; 752 } 753 default: 754 break; 755 } 756 ecr = xhci_read_4(sc, ecp); 757 if (XHCI_XECP_NEXT(ecr) == 0) { 758 ecp = 0; 759 } else { 760 ecp += XHCI_XECP_NEXT(ecr) * 4; 761 } 762 } 763 764 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 765 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 766 &sc->sc_obh) != 0) { 767 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 768 return ENOMEM; 769 } 770 771 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 772 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 773 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 774 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 775 return ENOMEM; 776 } 777 778 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 779 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 780 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 781 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 782 return ENOMEM; 783 } 784 785 for (i = 0; i < 100; i++) { 786 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 787 if ((usbsts & XHCI_STS_CNR) == 0) 788 break; 789 usb_delay_ms(&sc->sc_bus, 1); 790 } 791 if (i >= 100) { 792 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 793 return EIO; 794 } 795 796 usbcmd = 0; 797 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 798 usb_delay_ms(&sc->sc_bus, 1); 799 800 usbcmd = XHCI_CMD_HCRST; 801 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 802 for (i = 0; i < 100; i++) { 803 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 804 if ((usbcmd & XHCI_CMD_HCRST) == 0) 805 break; 806 usb_delay_ms(&sc->sc_bus, 1); 807 } 808 if (i >= 100) { 809 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 810 return EIO; 811 } 812 813 for (i = 0; i < 100; i++) { 814 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 815 if ((usbsts & XHCI_STS_CNR) == 0) 816 break; 817 usb_delay_ms(&sc->sc_bus, 1); 818 } 819 if (i >= 100) { 820 aprint_error_dev(sc->sc_dev, 821 "controller not ready timeout after reset\n"); 822 return EIO; 823 } 824 825 if (sc->sc_vendor_init) 826 sc->sc_vendor_init(sc); 827 828 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 829 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 830 pagesize = ffs(pagesize); 831 if (pagesize == 0) { 832 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 833 return EIO; 834 } 835 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 836 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 837 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 838 (uint32_t)sc->sc_maxslots); 839 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 840 841 usbd_status err; 842 int rv = 0; 843 844 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 845 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 846 if (sc->sc_maxspbuf != 0) { 847 err = usb_allocmem(&sc->sc_bus, 848 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 849 &sc->sc_spbufarray_dma); 850 if (err) { 851 aprint_error_dev(sc->sc_dev, 852 "spbufarray init fail, err %d\n", err); 853 return ENOMEM; 854 } 855 856 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 857 sc->sc_maxspbuf, KM_SLEEP); 858 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 859 for (i = 0; i < sc->sc_maxspbuf; i++) { 860 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 861 /* allocate contexts */ 862 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 863 sc->sc_pgsz, dma); 864 if (err) { 865 aprint_error_dev(sc->sc_dev, 866 "spbufarray_dma init fail, err %d\n", err); 867 rv = ENOMEM; 868 goto bad1; 869 } 870 spbufarray[i] = htole64(DMAADDR(dma, 0)); 871 usb_syncmem(dma, 0, sc->sc_pgsz, 872 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 873 } 874 875 usb_syncmem(&sc->sc_spbufarray_dma, 0, 876 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 877 } 878 879 config = xhci_op_read_4(sc, XHCI_CONFIG); 880 config &= ~0xFF; 881 config |= sc->sc_maxslots & 0xFF; 882 xhci_op_write_4(sc, XHCI_CONFIG, config); 883 884 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 885 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 886 if (err) { 887 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 888 err); 889 rv = ENOMEM; 890 goto bad1; 891 } 892 893 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 894 XHCI_EVENT_RING_SEGMENTS_ALIGN); 895 if (err) { 896 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 897 err); 898 rv = ENOMEM; 899 goto bad2; 900 } 901 902 usb_dma_t *dma; 903 size_t size; 904 size_t align; 905 906 dma = &sc->sc_eventst_dma; 907 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 908 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 909 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 910 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 911 err = usb_allocmem(&sc->sc_bus, size, align, dma); 912 if (err) { 913 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 914 err); 915 rv = ENOMEM; 916 goto bad3; 917 } 918 919 memset(KERNADDR(dma, 0), 0, size); 920 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 921 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 922 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 923 KERNADDR(&sc->sc_eventst_dma, 0), 924 sc->sc_eventst_dma.udma_block->size); 925 926 dma = &sc->sc_dcbaa_dma; 927 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 928 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 929 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 930 err = usb_allocmem(&sc->sc_bus, size, align, dma); 931 if (err) { 932 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 933 rv = ENOMEM; 934 goto bad4; 935 } 936 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 937 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 938 KERNADDR(&sc->sc_dcbaa_dma, 0), 939 sc->sc_dcbaa_dma.udma_block->size); 940 941 memset(KERNADDR(dma, 0), 0, size); 942 if (sc->sc_maxspbuf != 0) { 943 /* 944 * DCBA entry 0 hold the scratchbuf array pointer. 945 */ 946 *(uint64_t *)KERNADDR(dma, 0) = 947 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 948 } 949 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 950 951 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 952 KM_SLEEP); 953 if (sc->sc_slots == NULL) { 954 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 955 rv = ENOMEM; 956 goto bad; 957 } 958 959 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 960 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 961 if (sc->sc_xferpool == NULL) { 962 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 963 err); 964 rv = ENOMEM; 965 goto bad; 966 } 967 968 cv_init(&sc->sc_command_cv, "xhcicmd"); 969 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 970 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 971 cv_init(&sc->sc_softwake_cv, "xhciab"); 972 973 /* Set up the bus struct. */ 974 sc->sc_bus.ub_methods = &xhci_bus_methods; 975 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 976 977 struct xhci_erste *erst; 978 erst = KERNADDR(&sc->sc_eventst_dma, 0); 979 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 980 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 981 erst[0].erste_3 = htole32(0); 982 usb_syncmem(&sc->sc_eventst_dma, 0, 983 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 984 985 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 986 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 987 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 988 XHCI_ERDP_LO_BUSY); 989 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 990 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 991 sc->sc_cr.xr_cs); 992 993 #if 0 994 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 995 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 996 #endif 997 998 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 999 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1000 /* Intel xhci needs interrupt rate moderated. */ 1001 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1002 else 1003 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1004 aprint_debug_dev(sc->sc_dev, "setting IMOD %u\n", 1005 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1006 1007 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 1008 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1009 xhci_op_read_4(sc, XHCI_USBCMD)); 1010 1011 return 0; 1012 1013 bad: 1014 if (sc->sc_xferpool) { 1015 pool_cache_destroy(sc->sc_xferpool); 1016 sc->sc_xferpool = NULL; 1017 } 1018 1019 if (sc->sc_slots) { 1020 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1021 sc->sc_maxslots); 1022 sc->sc_slots = NULL; 1023 } 1024 1025 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1026 bad4: 1027 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1028 bad3: 1029 xhci_ring_free(sc, &sc->sc_er); 1030 bad2: 1031 xhci_ring_free(sc, &sc->sc_cr); 1032 i = sc->sc_maxspbuf; 1033 bad1: 1034 for (int j = 0; j < i; j++) 1035 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1036 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1037 1038 return rv; 1039 } 1040 1041 int 1042 xhci_intr(void *v) 1043 { 1044 struct xhci_softc * const sc = v; 1045 int ret = 0; 1046 1047 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1048 1049 if (sc == NULL) 1050 return 0; 1051 1052 mutex_spin_enter(&sc->sc_intr_lock); 1053 1054 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1055 goto done; 1056 1057 /* If we get an interrupt while polling, then just ignore it. */ 1058 if (sc->sc_bus.ub_usepolling) { 1059 #ifdef DIAGNOSTIC 1060 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1061 #endif 1062 goto done; 1063 } 1064 1065 ret = xhci_intr1(sc); 1066 done: 1067 mutex_spin_exit(&sc->sc_intr_lock); 1068 return ret; 1069 } 1070 1071 int 1072 xhci_intr1(struct xhci_softc * const sc) 1073 { 1074 uint32_t usbsts; 1075 uint32_t iman; 1076 1077 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1078 1079 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1080 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1081 #if 0 1082 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1083 return 0; 1084 } 1085 #endif 1086 xhci_op_write_4(sc, XHCI_USBSTS, 1087 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1088 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1089 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1090 1091 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1092 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1093 iman |= XHCI_IMAN_INTR_PEND; 1094 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1095 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1096 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1097 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1098 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1099 1100 usb_schedsoftintr(&sc->sc_bus); 1101 1102 return 1; 1103 } 1104 1105 /* 1106 * 3 port speed types used in USB stack 1107 * 1108 * usbdi speed 1109 * definition: USB_SPEED_* in usb.h 1110 * They are used in struct usbd_device in USB stack. 1111 * ioctl interface uses these values too. 1112 * port_status speed 1113 * definition: UPS_*_SPEED in usb.h 1114 * They are used in usb_port_status_t and valid only for USB 2.0. 1115 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1116 * of usb_port_status_ext_t indicates port speed. 1117 * Note that some 3.0 values overlap with 2.0 values. 1118 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1119 * means UPS_LOW_SPEED in HS.) 1120 * port status returned from hub also uses these values. 1121 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1122 * or more. 1123 * xspeed: 1124 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1125 * They are used in only slot context and PORTSC reg of xhci. 1126 * The difference between usbdi speed and xspeed is 1127 * that FS and LS values are swapped. 1128 */ 1129 1130 /* convert usbdi speed to xspeed */ 1131 static int 1132 xhci_speed2xspeed(int speed) 1133 { 1134 switch (speed) { 1135 case USB_SPEED_LOW: return 2; 1136 case USB_SPEED_FULL: return 1; 1137 default: return speed; 1138 } 1139 } 1140 1141 #if 0 1142 /* convert xspeed to usbdi speed */ 1143 static int 1144 xhci_xspeed2speed(int xspeed) 1145 { 1146 switch (xspeed) { 1147 case 1: return USB_SPEED_FULL; 1148 case 2: return USB_SPEED_LOW; 1149 default: return xspeed; 1150 } 1151 } 1152 #endif 1153 1154 /* convert xspeed to port status speed */ 1155 static int 1156 xhci_xspeed2psspeed(int xspeed) 1157 { 1158 switch (xspeed) { 1159 case 0: return 0; 1160 case 1: return UPS_FULL_SPEED; 1161 case 2: return UPS_LOW_SPEED; 1162 case 3: return UPS_HIGH_SPEED; 1163 default: return UPS_OTHER_SPEED; 1164 } 1165 } 1166 1167 /* construct slot context */ 1168 static void 1169 xhci_setup_sctx(struct usbd_device *dev, uint32_t *cp) 1170 { 1171 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 1172 int speed = dev->ud_speed; 1173 int tthubslot, ttportnum; 1174 bool ishub; 1175 bool usemtt; 1176 1177 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1178 1179 /* 1180 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 1181 * tthubslot: 1182 * This is the slot ID of parent HS hub 1183 * if LS/FS device is connected && connected through HS hub. 1184 * This is 0 if device is not LS/FS device || 1185 * parent hub is not HS hub || 1186 * attached to root hub. 1187 * ttportnum: 1188 * This is the downstream facing port of parent HS hub 1189 * if LS/FS device is connected. 1190 * This is 0 if device is not LS/FS device || 1191 * parent hub is not HS hub || 1192 * attached to root hub. 1193 */ 1194 if (dev->ud_myhsport != NULL && 1195 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1196 (dev->ud_myhub != NULL && 1197 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1198 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 1199 ttportnum = dev->ud_myhsport->up_portno; 1200 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 1201 } else { 1202 ttportnum = 0; 1203 tthubslot = 0; 1204 } 1205 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 1206 dev->ud_myhsport, ttportnum, tthubslot, 0); 1207 1208 /* ishub is valid after reading UDESC_DEVICE */ 1209 ishub = (dd->bDeviceClass == UDCLASS_HUB); 1210 1211 /* dev->ud_hub is valid after reading UDESC_HUB */ 1212 if (ishub && dev->ud_hub) { 1213 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 1214 1215 cp[1] |= htole32(XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts)); 1216 cp[2] |= htole32(XHCI_SCTX_2_TT_THINK_TIME_SET( 1217 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK))); 1218 DPRINTFN(4, "nports=%d ttt=%d", 1219 hd->bNbrPorts, XHCI_SCTX_2_TT_THINK_TIME_GET(cp[2]), 0, 0); 1220 } 1221 1222 #define IS_TTHUB(dd) \ 1223 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 1224 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 1225 1226 /* 1227 * MTT flag is set if 1228 * 1. this is HS hub && MTT is enabled 1229 * or 1230 * 2. this is not hub && this is LS or FS device && 1231 * MTT of parent HS hub (and its parent, too) is enabled 1232 */ 1233 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 1234 usemtt = true; 1235 else if (!ishub && 1236 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 1237 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1238 (dev->ud_myhub != NULL && 1239 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1240 dev->ud_myhsport != NULL && 1241 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 1242 usemtt = true; 1243 else 1244 usemtt = false; 1245 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 1246 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 1247 1248 cp[0] |= htole32( 1249 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)) | 1250 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 1251 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0) 1252 ); 1253 cp[1] |= htole32(0); 1254 cp[2] |= htole32( 1255 XHCI_SCTX_2_IRQ_TARGET_SET(0) | 1256 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 1257 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum) 1258 ); 1259 cp[3] |= htole32(0); 1260 } 1261 1262 static uint32_t 1263 xhci_get_maxburst(struct usbd_pipe *pipe) 1264 { 1265 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1266 usbd_desc_iter_t iter; 1267 const usb_cdc_descriptor_t *cdcd; 1268 const usb_endpoint_ss_comp_descriptor_t * esscd = NULL; 1269 uint32_t maxb = 0; 1270 uint8_t ep; 1271 1272 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc( 1273 pipe->up_dev, UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 1274 usb_desc_iter_init(pipe->up_dev, &iter); 1275 iter.cur = (const void *)cdcd; 1276 1277 /* find endpoint_ss_comp desc for ep of this pipe */ 1278 for (ep = 0;;) { 1279 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 1280 if (cdcd == NULL) 1281 break; 1282 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 1283 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 1284 bEndpointAddress; 1285 if (UE_GET_ADDR(ep) == 1286 UE_GET_ADDR(ed->bEndpointAddress)) { 1287 cdcd = (const usb_cdc_descriptor_t *) 1288 usb_desc_iter_next(&iter); 1289 break; 1290 } 1291 ep = 0; 1292 } 1293 } 1294 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 1295 esscd = (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 1296 maxb = esscd->bMaxBurst; 1297 } 1298 1299 return maxb; 1300 } 1301 1302 /* 1303 * Convert endpoint bInterval value to endpoint context interval value 1304 * for Interrupt pipe. 1305 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 1306 */ 1307 static uint32_t 1308 xhci_bival2ival(uint32_t ival, int speed) 1309 { 1310 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 1311 int i; 1312 1313 /* 1314 * round ival down to "the nearest base 2 multiple of 1315 * bInterval * 8". 1316 * bInterval is at most 255 as its type is uByte. 1317 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 1318 */ 1319 for (i = 10; i > 0; i--) { 1320 if ((ival * 8) >= (1 << i)) 1321 break; 1322 } 1323 ival = i; 1324 } else { 1325 /* Interval = bInterval-1 for SS/HS */ 1326 ival--; 1327 } 1328 1329 return ival; 1330 } 1331 1332 /* 1333 * 4.8.2, 6.2.3.2 1334 * construct common endpoint parameters 1335 */ 1336 static void 1337 xhci_setup_endp_ctx(struct usbd_pipe *pipe, uint32_t *cp) 1338 { 1339 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1340 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1341 const u_int dci = xhci_ep_get_dci(ed); 1342 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1343 uint32_t mps = UGETW(ed->wMaxPacketSize); 1344 uint32_t maxb = 0; 1345 int speed = pipe->up_dev->ud_speed; 1346 uint32_t ival = ed->bInterval; 1347 1348 cp[0] = htole32( 1349 XHCI_EPCTX_0_EPSTATE_SET(0) | 1350 XHCI_EPCTX_0_MULT_SET(0) | /* always 0 except SS iscoh */ 1351 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 1352 XHCI_EPCTX_0_LSA_SET(0) | 1353 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0) 1354 ); 1355 cp[1] = htole32( 1356 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 1357 XHCI_EPCTX_1_HID_SET(0) | 1358 XHCI_EPCTX_1_MAXB_SET(0) 1359 ); 1360 if (xfertype != UE_ISOCHRONOUS) 1361 cp[1] |= htole32(XHCI_EPCTX_1_CERR_SET(3)); 1362 1363 /* 6.2.3.4, 4.8.2.4 */ 1364 if (USB_IS_SS(speed)) { 1365 /* UBS 3.1 9.6.6 */ 1366 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1367 /* UBS 3.1 9.6.7 */ 1368 maxb = xhci_get_maxburst(pipe); 1369 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1370 } else { 1371 /* UBS 2.0 9.6.6 */ 1372 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps))); 1373 1374 /* 6.2.3.4 */ 1375 if (speed == USB_SPEED_HIGH && 1376 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 1377 maxb = UE_GET_TRANS(mps); 1378 } else { 1379 /* LS/FS or HS CTRL or HS BULK */ 1380 maxb = 0; 1381 } 1382 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1383 } 1384 1385 if (xfertype == UE_CONTROL) 1386 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(8)); /* 6.2.3 */ 1387 else if (USB_IS_SS(speed)) 1388 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps)); 1389 else 1390 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps))); 1391 1392 switch (xfertype) { 1393 case UE_CONTROL: 1394 break; 1395 case UE_BULK: 1396 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 1397 break; 1398 case UE_INTERRUPT: 1399 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1400 ival = pipe->up_interval; 1401 1402 ival = xhci_bival2ival(ival, speed); 1403 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1404 break; 1405 case UE_ISOCHRONOUS: 1406 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1407 ival = pipe->up_interval; 1408 1409 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 1410 if (speed == USB_SPEED_FULL) 1411 ival += 3; /* 1ms -> 125us */ 1412 ival--; 1413 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1414 1415 if (USB_IS_SS(speed)) { 1416 /* XXX if LEC = 1, set ESIT instead */ 1417 cp[0] |= htole32(XHCI_EPCTX_0_MULT_SET(0)); 1418 } 1419 break; 1420 default: 1421 break; 1422 } 1423 *(uint64_t *)(&cp[2]) = htole64( 1424 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 1425 XHCI_EPCTX_2_DCS_SET(1)); 1426 } 1427 1428 /* 1429 * Construct input contexts and issue TRB 1430 */ 1431 static usbd_status 1432 xhci_configure_endpoint(struct usbd_pipe *pipe) 1433 { 1434 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1435 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1436 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1437 struct xhci_trb trb; 1438 usbd_status err; 1439 uint32_t *cp; 1440 1441 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1442 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1443 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1444 pipe->up_endpoint->ue_edesc->bmAttributes); 1445 1446 /* XXX ensure input context is available? */ 1447 1448 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1449 1450 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1451 cp[0] = htole32(0); 1452 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 1453 1454 /* set up input slot context */ 1455 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1456 xhci_setup_sctx(pipe->up_dev, cp); 1457 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1458 1459 /* set up input endpoint context */ 1460 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 1461 xhci_setup_endp_ctx(pipe, cp); 1462 1463 /* sync input contexts before they are read from memory */ 1464 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1465 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1466 sc->sc_ctxsz * 1); 1467 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1468 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1469 1470 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1471 trb.trb_2 = 0; 1472 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1473 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1474 1475 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1476 1477 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1478 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1479 sc->sc_ctxsz * 1); 1480 1481 return err; 1482 } 1483 1484 #if 0 1485 static usbd_status 1486 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1487 { 1488 #ifdef USB_DEBUG 1489 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1490 #endif 1491 1492 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1493 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1494 1495 return USBD_NORMAL_COMPLETION; 1496 } 1497 #endif 1498 1499 /* 4.6.8, 6.4.3.7 */ 1500 static usbd_status 1501 xhci_reset_endpoint(struct usbd_pipe *pipe) 1502 { 1503 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1504 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1505 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1506 struct xhci_trb trb; 1507 usbd_status err; 1508 1509 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1510 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1511 1512 KASSERT(!mutex_owned(&sc->sc_lock)); 1513 1514 trb.trb_0 = 0; 1515 trb.trb_2 = 0; 1516 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1517 XHCI_TRB_3_EP_SET(dci) | 1518 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1519 1520 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1521 1522 return err; 1523 } 1524 1525 /* 1526 * 4.6.9, 6.4.3.8 1527 * Stop execution of TDs on xfer ring. 1528 * Should be called with sc_lock held. 1529 */ 1530 static usbd_status 1531 xhci_stop_endpoint(struct usbd_pipe *pipe) 1532 { 1533 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1534 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1535 struct xhci_trb trb; 1536 usbd_status err; 1537 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1538 1539 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1540 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1541 1542 KASSERT(mutex_owned(&sc->sc_lock)); 1543 1544 trb.trb_0 = 0; 1545 trb.trb_2 = 0; 1546 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1547 XHCI_TRB_3_EP_SET(dci) | 1548 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1549 1550 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1551 1552 return err; 1553 } 1554 1555 /* 1556 * Set TR Dequeue Pointer. 1557 * xCHI 1.1 4.6.10 6.4.3.9 1558 * Purge all of the transfer requests on ring. 1559 * EPSTATE of endpoint must be ERROR or STOPPED, or CONTEXT_STATE error. 1560 */ 1561 static usbd_status 1562 xhci_set_dequeue(struct usbd_pipe *pipe) 1563 { 1564 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1565 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1566 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1567 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1568 struct xhci_trb trb; 1569 usbd_status err; 1570 1571 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1572 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1573 1574 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1575 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1576 BUS_DMASYNC_PREWRITE); 1577 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1578 1579 xr->xr_ep = 0; 1580 xr->xr_cs = 1; 1581 1582 /* set DCS */ 1583 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1584 trb.trb_2 = 0; 1585 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1586 XHCI_TRB_3_EP_SET(dci) | 1587 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1588 1589 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1590 1591 return err; 1592 } 1593 1594 /* 1595 * Open new pipe: called from usbd_setup_pipe_flags. 1596 * Fills methods of pipe. 1597 * If pipe is not for ep0, calls configure_endpoint. 1598 */ 1599 static usbd_status 1600 xhci_open(struct usbd_pipe *pipe) 1601 { 1602 struct usbd_device * const dev = pipe->up_dev; 1603 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1604 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1605 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1606 1607 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1608 DPRINTFN(1, "addr %d depth %d port %d speed %d", 1609 dev->ud_addr, dev->ud_depth, dev->ud_powersrc->up_portno, 1610 dev->ud_speed); 1611 1612 if (sc->sc_dying) 1613 return USBD_IOERROR; 1614 1615 /* Root Hub */ 1616 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1617 switch (ed->bEndpointAddress) { 1618 case USB_CONTROL_ENDPOINT: 1619 pipe->up_methods = &roothub_ctrl_methods; 1620 break; 1621 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1622 pipe->up_methods = &xhci_root_intr_methods; 1623 break; 1624 default: 1625 pipe->up_methods = NULL; 1626 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1627 ed->bEndpointAddress, 0, 0, 0); 1628 return USBD_INVAL; 1629 } 1630 return USBD_NORMAL_COMPLETION; 1631 } 1632 1633 switch (xfertype) { 1634 case UE_CONTROL: 1635 pipe->up_methods = &xhci_device_ctrl_methods; 1636 break; 1637 case UE_ISOCHRONOUS: 1638 pipe->up_methods = &xhci_device_isoc_methods; 1639 return USBD_INVAL; 1640 break; 1641 case UE_BULK: 1642 pipe->up_methods = &xhci_device_bulk_methods; 1643 break; 1644 case UE_INTERRUPT: 1645 pipe->up_methods = &xhci_device_intr_methods; 1646 break; 1647 default: 1648 return USBD_IOERROR; 1649 break; 1650 } 1651 1652 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1653 return xhci_configure_endpoint(pipe); 1654 1655 return USBD_NORMAL_COMPLETION; 1656 } 1657 1658 /* 1659 * Closes pipe, called from usbd_kill_pipe via close methods. 1660 * If the endpoint to be closed is ep0, disable_slot. 1661 * Should be called with sc_lock held. 1662 */ 1663 static void 1664 xhci_close_pipe(struct usbd_pipe *pipe) 1665 { 1666 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1667 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1668 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1669 const u_int dci = xhci_ep_get_dci(ed); 1670 struct xhci_trb trb; 1671 uint32_t *cp; 1672 1673 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1674 1675 if (sc->sc_dying) 1676 return; 1677 1678 if (xs == NULL || xs->xs_idx == 0) 1679 /* xs is uninitialized before xhci_init_slot */ 1680 return; 1681 1682 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1683 1684 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1685 KASSERT(mutex_owned(&sc->sc_lock)); 1686 1687 if (pipe->up_dev->ud_depth == 0) 1688 return; 1689 1690 if (dci == XHCI_DCI_EP_CONTROL) { 1691 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1692 xhci_disable_slot(sc, xs->xs_idx); 1693 return; 1694 } 1695 1696 /* 1697 * This may fail in the case that xhci_close_pipe is called after 1698 * xhci_abort_xfer e.g. usbd_kill_pipe. 1699 */ 1700 (void)xhci_stop_endpoint(pipe); 1701 1702 /* 1703 * set appropriate bit to be dropped. 1704 * don't set DC bit to 1, otherwise all endpoints 1705 * would be deconfigured. 1706 */ 1707 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1708 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1709 cp[1] = htole32(0); 1710 1711 /* XXX should be most significant one, not dci? */ 1712 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1713 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1714 1715 /* sync input contexts before they are read from memory */ 1716 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1717 1718 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1719 trb.trb_2 = 0; 1720 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1721 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1722 1723 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1724 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1725 } 1726 1727 /* 1728 * Abort transfer. 1729 * Called with sc_lock held. 1730 * May be called from softintr context. 1731 */ 1732 static void 1733 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1734 { 1735 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1736 1737 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1738 DPRINTFN(4, "xfer %p pipe %p status %d", 1739 xfer, xfer->ux_pipe, status, 0); 1740 1741 KASSERT(mutex_owned(&sc->sc_lock)); 1742 1743 if (sc->sc_dying) { 1744 /* If we're dying, just do the software part. */ 1745 DPRINTFN(4, "dying", 0, 0, 0, 0); 1746 xfer->ux_status = status; /* make software ignore it */ 1747 callout_stop(&xfer->ux_callout); 1748 usb_transfer_complete(xfer); 1749 return; 1750 } 1751 1752 /* XXX need more stuff */ 1753 xfer->ux_status = status; 1754 callout_stop(&xfer->ux_callout); 1755 usb_transfer_complete(xfer); 1756 DPRINTFN(14, "end", 0, 0, 0, 0); 1757 1758 KASSERT(mutex_owned(&sc->sc_lock)); 1759 } 1760 1761 /* 1762 * Recover STALLed endpoint. 1763 * xHCI 1.1 sect 4.10.2.1 1764 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1765 * all transfers on transfer ring. 1766 * These are done in thread context asynchronously. 1767 */ 1768 static void 1769 xhci_clear_endpoint_stall_async_task(void *cookie) 1770 { 1771 struct usbd_xfer * const xfer = cookie; 1772 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1773 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1774 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1775 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1776 1777 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1778 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1779 1780 xhci_reset_endpoint(xfer->ux_pipe); 1781 xhci_set_dequeue(xfer->ux_pipe); 1782 1783 mutex_enter(&sc->sc_lock); 1784 tr->is_halted = false; 1785 usb_transfer_complete(xfer); 1786 mutex_exit(&sc->sc_lock); 1787 DPRINTFN(4, "ends", 0, 0, 0, 0); 1788 } 1789 1790 static usbd_status 1791 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1792 { 1793 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1794 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1795 1796 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1797 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1798 1799 if (sc->sc_dying) { 1800 return USBD_IOERROR; 1801 } 1802 1803 usb_init_task(&xp->xp_async_task, 1804 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1805 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1806 DPRINTFN(4, "ends", 0, 0, 0, 0); 1807 1808 return USBD_NORMAL_COMPLETION; 1809 } 1810 1811 /* Process roothub port status/change events and notify to uhub_intr. */ 1812 static void 1813 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1814 { 1815 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1816 uint8_t *p; 1817 1818 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1819 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1820 port, 0, 0); 1821 1822 if (xfer == NULL) 1823 return; 1824 1825 if (port > sc->sc_maxports) 1826 return; 1827 1828 p = xfer->ux_buf; 1829 memset(p, 0, xfer->ux_length); 1830 p[port/NBBY] |= 1 << (port%NBBY); 1831 xfer->ux_actlen = xfer->ux_length; 1832 xfer->ux_status = USBD_NORMAL_COMPLETION; 1833 usb_transfer_complete(xfer); 1834 } 1835 1836 /* Process Transfer Events */ 1837 static void 1838 xhci_event_transfer(struct xhci_softc * const sc, 1839 const struct xhci_trb * const trb) 1840 { 1841 uint64_t trb_0; 1842 uint32_t trb_2, trb_3; 1843 uint8_t trbcode; 1844 u_int slot, dci; 1845 struct xhci_slot *xs; 1846 struct xhci_ring *xr; 1847 struct xhci_xfer *xx; 1848 struct usbd_xfer *xfer; 1849 usbd_status err; 1850 1851 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1852 1853 trb_0 = le64toh(trb->trb_0); 1854 trb_2 = le32toh(trb->trb_2); 1855 trb_3 = le32toh(trb->trb_3); 1856 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1857 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1858 dci = XHCI_TRB_3_EP_GET(trb_3); 1859 xs = &sc->sc_slots[slot]; 1860 xr = &xs->xs_ep[dci].xe_tr; 1861 1862 /* sanity check */ 1863 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1864 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1865 1866 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1867 /* 1868 * When ED == 0, trb_0 is physical address of the TRB 1869 * that caused this event. (6.4.2.1) 1870 */ 1871 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 1872 1873 /* trb_0 range sanity check */ 1874 if (trb_0 < trbp || 1875 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 1876 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 1877 DPRINTFN(1, "invalid trb_0 0x%"PRIx64" trbp 0x%"PRIx64, 1878 trb_0, trbp, 0, 0); 1879 return; 1880 } 1881 int idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 1882 xx = xr->xr_cookies[idx]; 1883 1884 /* 1885 * If endpoint is stopped between TDs, TRB pointer points at 1886 * next TRB, however, it is not put yet or is a garbage TRB. 1887 * That's why xr_cookies may be NULL or look like broken. 1888 * Note: this ev happens only when hciversion >= 1.0 or 1889 * hciversion == 0.96 and FSE of hcc1 is set. 1890 */ 1891 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1892 DPRINTFN(1, "xx NULL: #%u: cookie %p: code %u trb_0 %" 1893 PRIx64, idx, xx, trbcode, trb_0); 1894 } 1895 } else { 1896 /* When ED != 0, trb_0 is kaddr of struct xhci_xfer. */ 1897 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1898 } 1899 /* XXX this may not happen */ 1900 if (xx == NULL) { 1901 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1902 return; 1903 } 1904 xfer = &xx->xx_xfer; 1905 /* XXX this may happen when detaching */ 1906 if (xfer == NULL) { 1907 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1908 xx, trb_0, 0, 0); 1909 return; 1910 } 1911 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1912 /* XXX I dunno why this happens */ 1913 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1914 1915 if (!xfer->ux_pipe->up_repeat && 1916 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1917 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1918 return; 1919 } 1920 1921 /* 4.11.5.2 Event Data TRB */ 1922 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1923 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1924 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1925 if ((trb_0 & 0x3) == 0x3) { 1926 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1927 } 1928 } 1929 1930 switch (trbcode) { 1931 case XHCI_TRB_ERROR_SHORT_PKT: 1932 case XHCI_TRB_ERROR_SUCCESS: 1933 xfer->ux_actlen = 1934 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1935 err = USBD_NORMAL_COMPLETION; 1936 break; 1937 case XHCI_TRB_ERROR_STALL: 1938 case XHCI_TRB_ERROR_BABBLE: 1939 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1940 xr->is_halted = true; 1941 err = USBD_STALLED; 1942 /* 1943 * Stalled endpoints can be recoverd by issuing 1944 * command TRB TYPE_RESET_EP on xHCI instead of 1945 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1946 * on the endpoint. However, this function may be 1947 * called from softint context (e.g. from umass), 1948 * in that case driver gets KASSERT in cv_timedwait 1949 * in xhci_do_command. 1950 * To avoid this, this runs reset_endpoint and 1951 * usb_transfer_complete in usb task thread 1952 * asynchronously (and then umass issues clear 1953 * UF_ENDPOINT_HALT). 1954 */ 1955 xfer->ux_status = err; 1956 xhci_clear_endpoint_stall_async(xfer); 1957 return; 1958 default: 1959 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1960 err = USBD_IOERROR; 1961 break; 1962 } 1963 xfer->ux_status = err; 1964 1965 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1966 if ((trb_0 & 0x3) == 0x0) { 1967 callout_stop(&xfer->ux_callout); 1968 usb_transfer_complete(xfer); 1969 } 1970 } else { 1971 callout_stop(&xfer->ux_callout); 1972 usb_transfer_complete(xfer); 1973 } 1974 } 1975 1976 /* Process Command complete events */ 1977 static void 1978 xhci_event_cmd(struct xhci_softc * const sc, 1979 const struct xhci_trb * const trb) 1980 { 1981 uint64_t trb_0; 1982 uint32_t trb_2, trb_3; 1983 1984 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1985 1986 trb_0 = le64toh(trb->trb_0); 1987 trb_2 = le32toh(trb->trb_2); 1988 trb_3 = le32toh(trb->trb_3); 1989 1990 if (trb_0 == sc->sc_command_addr) { 1991 sc->sc_result_trb.trb_0 = trb_0; 1992 sc->sc_result_trb.trb_2 = trb_2; 1993 sc->sc_result_trb.trb_3 = trb_3; 1994 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1995 XHCI_TRB_ERROR_SUCCESS) { 1996 DPRINTFN(1, "command completion " 1997 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1998 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1999 } 2000 cv_signal(&sc->sc_command_cv); 2001 } else { 2002 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 2003 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 2004 trb_2, trb_3); 2005 } 2006 } 2007 2008 /* 2009 * Process events. 2010 * called from xhci_softintr 2011 */ 2012 static void 2013 xhci_handle_event(struct xhci_softc * const sc, 2014 const struct xhci_trb * const trb) 2015 { 2016 uint64_t trb_0; 2017 uint32_t trb_2, trb_3; 2018 2019 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2020 2021 trb_0 = le64toh(trb->trb_0); 2022 trb_2 = le32toh(trb->trb_2); 2023 trb_3 = le32toh(trb->trb_3); 2024 2025 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2026 trb, trb_0, trb_2, trb_3); 2027 2028 /* 2029 * 4.11.3.1, 6.4.2.1 2030 * TRB Pointer is invalid for these completion codes. 2031 */ 2032 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2033 case XHCI_TRB_ERROR_RING_UNDERRUN: 2034 case XHCI_TRB_ERROR_RING_OVERRUN: 2035 case XHCI_TRB_ERROR_VF_RING_FULL: 2036 return; 2037 default: 2038 if (trb_0 == 0) { 2039 return; 2040 } 2041 break; 2042 } 2043 2044 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2045 case XHCI_TRB_EVENT_TRANSFER: 2046 xhci_event_transfer(sc, trb); 2047 break; 2048 case XHCI_TRB_EVENT_CMD_COMPLETE: 2049 xhci_event_cmd(sc, trb); 2050 break; 2051 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2052 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2053 break; 2054 default: 2055 break; 2056 } 2057 } 2058 2059 static void 2060 xhci_softintr(void *v) 2061 { 2062 struct usbd_bus * const bus = v; 2063 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2064 struct xhci_ring * const er = &sc->sc_er; 2065 struct xhci_trb *trb; 2066 int i, j, k; 2067 2068 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2069 2070 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2071 2072 i = er->xr_ep; 2073 j = er->xr_cs; 2074 2075 DPRINTFN(16, "xr_ep %d xr_cs %d", i, j, 0, 0); 2076 2077 while (1) { 2078 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2079 BUS_DMASYNC_POSTREAD); 2080 trb = &er->xr_trb[i]; 2081 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2082 2083 if (j != k) 2084 break; 2085 2086 xhci_handle_event(sc, trb); 2087 2088 i++; 2089 if (i == XHCI_EVENT_RING_TRBS) { 2090 i = 0; 2091 j ^= 1; 2092 } 2093 } 2094 2095 er->xr_ep = i; 2096 er->xr_cs = j; 2097 2098 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2099 XHCI_ERDP_LO_BUSY); 2100 2101 DPRINTFN(16, "ends", 0, 0, 0, 0); 2102 2103 return; 2104 } 2105 2106 static void 2107 xhci_poll(struct usbd_bus *bus) 2108 { 2109 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2110 2111 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2112 2113 mutex_spin_enter(&sc->sc_intr_lock); 2114 xhci_intr1(sc); 2115 mutex_spin_exit(&sc->sc_intr_lock); 2116 2117 return; 2118 } 2119 2120 static struct usbd_xfer * 2121 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2122 { 2123 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2124 struct usbd_xfer *xfer; 2125 2126 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2127 2128 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 2129 if (xfer != NULL) { 2130 memset(xfer, 0, sizeof(struct xhci_xfer)); 2131 #ifdef DIAGNOSTIC 2132 xfer->ux_state = XFER_BUSY; 2133 #endif 2134 } 2135 2136 return xfer; 2137 } 2138 2139 static void 2140 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2141 { 2142 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2143 2144 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2145 2146 #ifdef DIAGNOSTIC 2147 if (xfer->ux_state != XFER_BUSY) { 2148 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 2149 xfer, xfer->ux_state, 0, 0); 2150 } 2151 xfer->ux_state = XFER_FREE; 2152 #endif 2153 pool_cache_put(sc->sc_xferpool, xfer); 2154 } 2155 2156 static void 2157 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2158 { 2159 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2160 2161 *lock = &sc->sc_lock; 2162 } 2163 2164 extern uint32_t usb_cookie_no; 2165 2166 /* 2167 * Called if uhub_explore finds a new device (via usbd_new_device). 2168 * Allocate and construct dev structure of default endpoint (ep0). 2169 * Determine initial MaxPacketSize (mps) by speed. 2170 * Determine route string and roothub port for slot of dev. 2171 * Allocate pipe of ep0. 2172 * Enable and initialize slot and Set Address. 2173 * Read device descriptor. 2174 * Register this device. 2175 */ 2176 static usbd_status 2177 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2178 int speed, int port, struct usbd_port *up) 2179 { 2180 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2181 struct usbd_device *dev; 2182 usbd_status err; 2183 usb_device_descriptor_t *dd; 2184 struct usbd_device *hub; 2185 struct usbd_device *adev; 2186 int rhport = 0; 2187 struct xhci_slot *xs; 2188 uint32_t *cp; 2189 uint32_t route = 0; 2190 uint8_t slot = 0; 2191 uint8_t addr; 2192 2193 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2194 DPRINTFN(4, "port=%d depth=%d speed=%d upport %d", 2195 port, depth, speed, up->up_portno); 2196 2197 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2198 if (dev == NULL) 2199 return USBD_NOMEM; 2200 2201 dev->ud_bus = bus; 2202 2203 /* Set up default endpoint handle. */ 2204 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2205 2206 /* Set up default endpoint descriptor. */ 2207 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2208 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2209 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2210 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2211 /* 4.3, 4.8.2.1 */ 2212 switch (speed) { 2213 case USB_SPEED_SUPER: 2214 case USB_SPEED_SUPER_PLUS: 2215 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2216 break; 2217 case USB_SPEED_FULL: 2218 /* XXX using 64 as initial mps of ep0 in FS */ 2219 case USB_SPEED_HIGH: 2220 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2221 break; 2222 case USB_SPEED_LOW: 2223 default: 2224 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2225 break; 2226 } 2227 dev->ud_ep0desc.bInterval = 0; 2228 2229 /* doesn't matter, just don't let it uninitialized */ 2230 dev->ud_ep0.ue_toggle = 0; 2231 2232 DPRINTFN(4, "up %p portno %d", up, up->up_portno, 0, 0); 2233 2234 dev->ud_quirks = &usbd_no_quirk; 2235 dev->ud_addr = 0; 2236 dev->ud_ddesc.bMaxPacketSize = 0; 2237 dev->ud_depth = depth; 2238 dev->ud_powersrc = up; 2239 dev->ud_myhub = up->up_parent; 2240 2241 up->up_dev = dev; 2242 2243 /* Locate root hub port */ 2244 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2245 uint32_t dep; 2246 2247 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2248 hub, hub->ud_depth, hub->ud_powersrc, 2249 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2250 2251 if (hub->ud_powersrc == NULL) 2252 break; 2253 dep = hub->ud_depth; 2254 if (dep == 0) 2255 break; 2256 rhport = hub->ud_powersrc->up_portno; 2257 if (dep > USB_HUB_MAX_DEPTH) 2258 continue; 2259 2260 route |= 2261 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2262 << ((dep - 1) * 4); 2263 } 2264 route = route >> 4; 2265 DPRINTFN(4, "rhport %d Route %05x hub %p", rhport, route, hub, 0); 2266 2267 /* Locate port on upstream high speed hub */ 2268 for (adev = dev, hub = up->up_parent; 2269 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2270 adev = hub, hub = hub->ud_myhub) 2271 ; 2272 if (hub) { 2273 int p; 2274 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2275 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2276 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2277 goto found; 2278 } 2279 } 2280 panic("xhci_new_device: cannot find HS port"); 2281 found: 2282 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2283 } else { 2284 dev->ud_myhsport = NULL; 2285 } 2286 2287 dev->ud_speed = speed; 2288 dev->ud_langid = USBD_NOLANG; 2289 dev->ud_cookie.cookie = ++usb_cookie_no; 2290 2291 /* Establish the default pipe. */ 2292 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2293 &dev->ud_pipe0); 2294 if (err) { 2295 goto bad; 2296 } 2297 2298 dd = &dev->ud_ddesc; 2299 2300 if ((depth == 0) && (port == 0)) { 2301 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2302 bus->ub_devices[dev->ud_addr] = dev; 2303 err = usbd_get_initial_ddesc(dev, dd); 2304 if (err) 2305 goto bad; 2306 err = usbd_reload_device_desc(dev); 2307 if (err) 2308 goto bad; 2309 } else { 2310 err = xhci_enable_slot(sc, &slot); 2311 if (err) 2312 goto bad; 2313 xs = &sc->sc_slots[slot]; 2314 dev->ud_hcpriv = xs; 2315 err = xhci_init_slot(dev, slot, route, rhport); 2316 if (err) { 2317 dev->ud_hcpriv = NULL; 2318 /* 2319 * We have to disable_slot here because 2320 * xs->xs_idx == 0 when xhci_init_slot fails, 2321 * in that case usbd_remove_dev won't work. 2322 */ 2323 mutex_enter(&sc->sc_lock); 2324 xhci_disable_slot(sc, slot); 2325 mutex_exit(&sc->sc_lock); 2326 goto bad; 2327 } 2328 2329 /* Allow device time to set new address */ 2330 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2331 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2332 //hexdump("slot context", cp, sc->sc_ctxsz); 2333 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2334 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2335 /* XXX ensure we know when the hardware does something 2336 we can't yet cope with */ 2337 KASSERT(addr >= 1 && addr <= 127); 2338 dev->ud_addr = addr; 2339 /* XXX dev->ud_addr not necessarily unique on bus */ 2340 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2341 bus->ub_devices[dev->ud_addr] = dev; 2342 2343 err = usbd_get_initial_ddesc(dev, dd); 2344 if (err) 2345 goto bad; 2346 /* 4.8.2.1 */ 2347 if (USB_IS_SS(speed)) { 2348 if (dd->bMaxPacketSize != 9) { 2349 printf("%s: invalid mps 2^%u for SS ep0," 2350 " using 512\n", 2351 device_xname(sc->sc_dev), 2352 dd->bMaxPacketSize); 2353 dd->bMaxPacketSize = 9; 2354 } 2355 USETW(dev->ud_ep0desc.wMaxPacketSize, 2356 (1 << dd->bMaxPacketSize)); 2357 } else 2358 USETW(dev->ud_ep0desc.wMaxPacketSize, 2359 dd->bMaxPacketSize); 2360 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2361 xhci_update_ep0_mps(sc, xs, 2362 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2363 err = usbd_reload_device_desc(dev); 2364 if (err) 2365 goto bad; 2366 2367 #if 0 2368 /* Re-establish the default pipe with the new MPS. */ 2369 /* In xhci this is done by xhci_update_ep0_mps. */ 2370 usbd_kill_pipe(dev->ud_pipe0); 2371 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2372 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2373 #endif 2374 } 2375 2376 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2377 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2378 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2379 dd->bDeviceClass, dd->bDeviceSubClass, 2380 dd->bDeviceProtocol, 0); 2381 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2382 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2383 dev->ud_speed); 2384 2385 usbd_get_device_strings(dev); 2386 2387 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2388 2389 if ((depth == 0) && (port == 0)) { 2390 usbd_attach_roothub(parent, dev); 2391 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2392 return USBD_NORMAL_COMPLETION; 2393 } 2394 2395 2396 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2397 bad: 2398 if (err != USBD_NORMAL_COMPLETION) { 2399 usbd_remove_device(dev, up); 2400 } 2401 2402 return err; 2403 } 2404 2405 static usbd_status 2406 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2407 size_t ntrb, size_t align) 2408 { 2409 usbd_status err; 2410 size_t size = ntrb * XHCI_TRB_SIZE; 2411 2412 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2413 2414 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2415 if (err) 2416 return err; 2417 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2418 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2419 xr->xr_trb = xhci_ring_trbv(xr, 0); 2420 xr->xr_ntrb = ntrb; 2421 xr->xr_ep = 0; 2422 xr->xr_cs = 1; 2423 memset(xr->xr_trb, 0, size); 2424 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 2425 xr->is_halted = false; 2426 2427 return USBD_NORMAL_COMPLETION; 2428 } 2429 2430 static void 2431 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2432 { 2433 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2434 mutex_destroy(&xr->xr_lock); 2435 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2436 } 2437 2438 static void 2439 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2440 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2441 { 2442 size_t i; 2443 u_int ri; 2444 u_int cs; 2445 uint64_t parameter; 2446 uint32_t status; 2447 uint32_t control; 2448 2449 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2450 2451 KASSERT(ntrbs <= XHCI_XFER_NTRB); 2452 for (i = 0; i < ntrbs; i++) { 2453 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2454 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2455 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2456 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2457 XHCI_TRB_TYPE_LINK); 2458 } 2459 2460 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2461 2462 ri = xr->xr_ep; 2463 cs = xr->xr_cs; 2464 2465 /* 2466 * Although the xhci hardware can do scatter/gather dma from 2467 * arbitrary sized buffers, there is a non-obvious restriction 2468 * that a LINK trb is only allowed at the end of a burst of 2469 * transfers - which might be 16kB. 2470 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2471 * The simple solution is not to allow a LINK trb in the middle 2472 * of anything - as here. 2473 * XXX: (dsl) There are xhci controllers out there (eg some made by 2474 * ASMedia) that seem to lock up if they process a LINK trb but 2475 * cannot process the linked-to trb yet. 2476 * The code should write the 'cycle' bit on the link trb AFTER 2477 * adding the other trb. 2478 */ 2479 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2480 parameter = xhci_ring_trbp(xr, 0); 2481 status = 0; 2482 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2483 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2484 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2485 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2486 BUS_DMASYNC_PREWRITE); 2487 xr->xr_cookies[ri] = NULL; 2488 xr->xr_ep = 0; 2489 xr->xr_cs ^= 1; 2490 ri = xr->xr_ep; 2491 cs = xr->xr_cs; 2492 } 2493 2494 ri++; 2495 2496 /* Write any subsequent TRB first */ 2497 for (i = 1; i < ntrbs; i++) { 2498 parameter = trbs[i].trb_0; 2499 status = trbs[i].trb_2; 2500 control = trbs[i].trb_3; 2501 2502 if (cs) { 2503 control |= XHCI_TRB_3_CYCLE_BIT; 2504 } else { 2505 control &= ~XHCI_TRB_3_CYCLE_BIT; 2506 } 2507 2508 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2509 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2510 BUS_DMASYNC_PREWRITE); 2511 xr->xr_cookies[ri] = cookie; 2512 ri++; 2513 } 2514 2515 /* Write the first TRB last */ 2516 i = 0; 2517 parameter = trbs[i].trb_0; 2518 status = trbs[i].trb_2; 2519 control = trbs[i].trb_3; 2520 2521 if (xr->xr_cs) { 2522 control |= XHCI_TRB_3_CYCLE_BIT; 2523 } else { 2524 control &= ~XHCI_TRB_3_CYCLE_BIT; 2525 } 2526 2527 xhci_trb_put(&xr->xr_trb[xr->xr_ep], parameter, status, control); 2528 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2529 BUS_DMASYNC_PREWRITE); 2530 xr->xr_cookies[xr->xr_ep] = cookie; 2531 2532 xr->xr_ep = ri; 2533 xr->xr_cs = cs; 2534 2535 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2536 } 2537 2538 /* 2539 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2540 * Command completion is notified by cv_signal from xhci_handle_event 2541 * (called from interrupt from xHCI), or timed-out. 2542 * Command validation is performed in xhci_handle_event by checking if 2543 * trb_0 in CMD_COMPLETE TRB and sc->sc_command_addr are identical. 2544 */ 2545 static usbd_status 2546 xhci_do_command_locked(struct xhci_softc * const sc, struct xhci_trb * const trb, 2547 int timeout) 2548 { 2549 struct xhci_ring * const cr = &sc->sc_cr; 2550 usbd_status err; 2551 2552 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2553 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2554 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2555 2556 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2557 KASSERT(mutex_owned(&sc->sc_lock)); 2558 2559 /* XXX KASSERT may fire when cv_timedwait unlocks sc_lock */ 2560 KASSERT(sc->sc_command_addr == 0); 2561 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2562 2563 mutex_enter(&cr->xr_lock); 2564 xhci_ring_put(sc, cr, NULL, trb, 1); 2565 mutex_exit(&cr->xr_lock); 2566 2567 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2568 2569 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2570 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2571 err = USBD_TIMEOUT; 2572 goto timedout; 2573 } 2574 2575 trb->trb_0 = sc->sc_result_trb.trb_0; 2576 trb->trb_2 = sc->sc_result_trb.trb_2; 2577 trb->trb_3 = sc->sc_result_trb.trb_3; 2578 2579 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2580 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2581 2582 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2583 case XHCI_TRB_ERROR_SUCCESS: 2584 err = USBD_NORMAL_COMPLETION; 2585 break; 2586 default: 2587 case 192 ... 223: 2588 err = USBD_IOERROR; 2589 break; 2590 case 224 ... 255: 2591 err = USBD_NORMAL_COMPLETION; 2592 break; 2593 } 2594 2595 timedout: 2596 sc->sc_command_addr = 0; 2597 return err; 2598 } 2599 2600 static usbd_status 2601 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2602 int timeout) 2603 { 2604 2605 mutex_enter(&sc->sc_lock); 2606 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2607 mutex_exit(&sc->sc_lock); 2608 2609 return ret; 2610 } 2611 2612 static usbd_status 2613 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2614 { 2615 struct xhci_trb trb; 2616 usbd_status err; 2617 2618 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2619 2620 trb.trb_0 = 0; 2621 trb.trb_2 = 0; 2622 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2623 2624 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2625 if (err != USBD_NORMAL_COMPLETION) { 2626 return err; 2627 } 2628 2629 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2630 2631 return err; 2632 } 2633 2634 /* 2635 * Deallocate DMA buffer and ring buffer, and disable_slot. 2636 * Should be called with sc_lock held. 2637 */ 2638 static usbd_status 2639 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2640 { 2641 struct xhci_trb trb; 2642 struct xhci_slot *xs; 2643 usbd_status err; 2644 2645 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2646 2647 if (sc->sc_dying) 2648 return USBD_IOERROR; 2649 2650 trb.trb_0 = 0; 2651 trb.trb_2 = 0; 2652 trb.trb_3 = htole32( 2653 XHCI_TRB_3_SLOT_SET(slot) | 2654 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2655 2656 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2657 2658 if (!err) { 2659 xs = &sc->sc_slots[slot]; 2660 if (xs->xs_idx != 0) { 2661 for (int i = XHCI_DCI_SLOT + 1; i < 32; i++) { 2662 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2663 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2664 } 2665 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2666 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2667 xhci_set_dcba(sc, 0, slot); 2668 memset(xs, 0, sizeof(*xs)); 2669 } 2670 } 2671 2672 return err; 2673 } 2674 2675 /* 2676 * Change slot state. 2677 * bsr=0: ENABLED -> ADDRESSED 2678 * bsr=1: ENABLED -> DEFAULT 2679 * see xHCI 1.1 4.5.3, 3.3.4 2680 */ 2681 static usbd_status 2682 xhci_address_device(struct xhci_softc * const sc, 2683 uint64_t icp, uint8_t slot_id, bool bsr) 2684 { 2685 struct xhci_trb trb; 2686 usbd_status err; 2687 2688 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2689 2690 trb.trb_0 = icp; 2691 trb.trb_2 = 0; 2692 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2693 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2694 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2695 2696 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2697 2698 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2699 err = USBD_NO_ADDR; 2700 2701 return err; 2702 } 2703 2704 static usbd_status 2705 xhci_update_ep0_mps(struct xhci_softc * const sc, 2706 struct xhci_slot * const xs, u_int mps) 2707 { 2708 struct xhci_trb trb; 2709 usbd_status err; 2710 uint32_t * cp; 2711 2712 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2713 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2714 2715 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2716 cp[0] = htole32(0); 2717 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2718 2719 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2720 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2721 2722 /* sync input contexts before they are read from memory */ 2723 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2724 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2725 sc->sc_ctxsz * 4); 2726 2727 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2728 trb.trb_2 = 0; 2729 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2730 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2731 2732 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2733 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2734 return err; 2735 } 2736 2737 static void 2738 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2739 { 2740 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2741 2742 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2743 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2744 &dcbaa[si], dcba, si, 0); 2745 2746 dcbaa[si] = htole64(dcba); 2747 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2748 BUS_DMASYNC_PREWRITE); 2749 } 2750 2751 /* 2752 * Allocate DMA buffer and ring buffer for specified slot 2753 * and set Device Context Base Address 2754 * and issue Set Address device command. 2755 */ 2756 static usbd_status 2757 xhci_init_slot(struct usbd_device *dev, uint32_t slot, uint32_t route, int rhport) 2758 { 2759 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2760 struct xhci_slot *xs; 2761 usbd_status err; 2762 u_int dci; 2763 uint32_t *cp; 2764 uint32_t mps = UGETW(dev->ud_ep0desc.wMaxPacketSize); 2765 2766 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2767 DPRINTFN(4, "slot %u speed %d route %05x rhport %d", 2768 slot, dev->ud_speed, route, rhport); 2769 2770 xs = &sc->sc_slots[slot]; 2771 2772 /* allocate contexts */ 2773 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2774 &xs->xs_dc_dma); 2775 if (err) 2776 return err; 2777 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2778 2779 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2780 &xs->xs_ic_dma); 2781 if (err) 2782 goto bad1; 2783 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2784 2785 for (dci = 0; dci < 32; dci++) { 2786 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2787 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2788 if (dci == XHCI_DCI_SLOT) 2789 continue; 2790 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2791 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2792 if (err) { 2793 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2794 goto bad2; 2795 } 2796 } 2797 2798 /* set up initial input control context */ 2799 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2800 cp[0] = htole32(0); 2801 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 2802 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2803 2804 /* set up input slot context */ 2805 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2806 xhci_setup_sctx(dev, cp); 2807 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(1)); 2808 cp[0] |= htole32(XHCI_SCTX_0_ROUTE_SET(route)); 2809 cp[1] |= htole32(XHCI_SCTX_1_RH_PORT_SET(rhport)); 2810 2811 /* set up input EP0 context */ 2812 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2813 cp[0] = htole32(0); 2814 cp[1] = htole32( 2815 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 2816 XHCI_EPCTX_1_EPTYPE_SET(4) | 2817 XHCI_EPCTX_1_CERR_SET(3) 2818 ); 2819 /* can't use xhci_ep_get_dci() yet? */ 2820 *(uint64_t *)(&cp[2]) = htole64( 2821 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 2822 XHCI_EPCTX_2_DCS_SET(1)); 2823 cp[4] = htole32( 2824 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 2825 ); 2826 2827 /* sync input contexts before they are read from memory */ 2828 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2829 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2830 sc->sc_ctxsz * 3); 2831 2832 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2833 2834 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 2835 false); 2836 2837 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2838 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2839 sc->sc_ctxsz * 2); 2840 2841 bad2: 2842 if (err == USBD_NORMAL_COMPLETION) { 2843 xs->xs_idx = slot; 2844 } else { 2845 for (int i = 1; i < dci; i++) { 2846 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2847 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2848 } 2849 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2850 bad1: 2851 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2852 xs->xs_idx = 0; 2853 } 2854 2855 return err; 2856 } 2857 2858 /* ----- */ 2859 2860 static void 2861 xhci_noop(struct usbd_pipe *pipe) 2862 { 2863 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2864 } 2865 2866 /* 2867 * Process root hub request. 2868 */ 2869 static int 2870 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2871 void *buf, int buflen) 2872 { 2873 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2874 usb_port_status_t ps; 2875 int l, totlen = 0; 2876 uint16_t len, value, index; 2877 int port, i; 2878 uint32_t v; 2879 2880 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2881 2882 if (sc->sc_dying) 2883 return -1; 2884 2885 len = UGETW(req->wLength); 2886 value = UGETW(req->wValue); 2887 index = UGETW(req->wIndex); 2888 2889 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 2890 req->bmRequestType | (req->bRequest << 8), value, index, len); 2891 2892 #define C(x,y) ((x) | ((y) << 8)) 2893 switch (C(req->bRequest, req->bmRequestType)) { 2894 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2895 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 2896 if (len == 0) 2897 break; 2898 switch (value) { 2899 case C(0, UDESC_DEVICE): { 2900 usb_device_descriptor_t devd; 2901 totlen = min(buflen, sizeof(devd)); 2902 memcpy(&devd, buf, totlen); 2903 USETW(devd.idVendor, sc->sc_id_vendor); 2904 memcpy(buf, &devd, totlen); 2905 break; 2906 } 2907 #define sd ((usb_string_descriptor_t *)buf) 2908 case C(1, UDESC_STRING): 2909 /* Vendor */ 2910 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2911 break; 2912 case C(2, UDESC_STRING): 2913 /* Product */ 2914 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 2915 break; 2916 #undef sd 2917 default: 2918 /* default from usbroothub */ 2919 return buflen; 2920 } 2921 break; 2922 2923 /* Hub requests */ 2924 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2925 break; 2926 /* Clear Port Feature request */ 2927 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2928 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2929 index, value, 0, 0); 2930 if (index < 1 || index > sc->sc_maxports) { 2931 return -1; 2932 } 2933 port = XHCI_PORTSC(index); 2934 v = xhci_op_read_4(sc, port); 2935 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 2936 v &= ~XHCI_PS_CLEAR; 2937 switch (value) { 2938 case UHF_PORT_ENABLE: 2939 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 2940 break; 2941 case UHF_PORT_SUSPEND: 2942 return -1; 2943 case UHF_PORT_POWER: 2944 break; 2945 case UHF_PORT_TEST: 2946 case UHF_PORT_INDICATOR: 2947 return -1; 2948 case UHF_C_PORT_CONNECTION: 2949 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2950 break; 2951 case UHF_C_PORT_ENABLE: 2952 case UHF_C_PORT_SUSPEND: 2953 case UHF_C_PORT_OVER_CURRENT: 2954 return -1; 2955 case UHF_C_BH_PORT_RESET: 2956 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 2957 break; 2958 case UHF_C_PORT_RESET: 2959 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2960 break; 2961 case UHF_C_PORT_LINK_STATE: 2962 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 2963 break; 2964 case UHF_C_PORT_CONFIG_ERROR: 2965 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 2966 break; 2967 default: 2968 return -1; 2969 } 2970 break; 2971 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2972 if (len == 0) 2973 break; 2974 if ((value & 0xff) != 0) { 2975 return -1; 2976 } 2977 usb_hub_descriptor_t hubd; 2978 2979 totlen = min(buflen, sizeof(hubd)); 2980 memcpy(&hubd, buf, totlen); 2981 hubd.bNbrPorts = sc->sc_maxports; 2982 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2983 hubd.bPwrOn2PwrGood = 200; 2984 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 2985 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2986 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2987 totlen = min(totlen, hubd.bDescLength); 2988 memcpy(buf, &hubd, totlen); 2989 break; 2990 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2991 if (len != 4) { 2992 return -1; 2993 } 2994 memset(buf, 0, len); /* ? XXX */ 2995 totlen = len; 2996 break; 2997 /* Get Port Status request */ 2998 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2999 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 3000 if (index < 1 || index > sc->sc_maxports) { 3001 return -1; 3002 } 3003 if (len != 4) { 3004 return -1; 3005 } 3006 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 3007 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 3008 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3009 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3010 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3011 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3012 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3013 if (v & XHCI_PS_PR) i |= UPS_RESET; 3014 if (v & XHCI_PS_PP) { 3015 if (i & UPS_OTHER_SPEED) 3016 i |= UPS_PORT_POWER_SS; 3017 else 3018 i |= UPS_PORT_POWER; 3019 } 3020 if (i & UPS_OTHER_SPEED) 3021 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3022 if (sc->sc_vendor_port_status) 3023 i = sc->sc_vendor_port_status(sc, v, i); 3024 USETW(ps.wPortStatus, i); 3025 i = 0; 3026 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3027 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3028 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3029 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3030 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3031 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3032 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3033 USETW(ps.wPortChange, i); 3034 totlen = min(len, sizeof(ps)); 3035 memcpy(buf, &ps, totlen); 3036 break; 3037 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3038 return -1; 3039 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3040 break; 3041 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3042 break; 3043 /* Set Port Feature request */ 3044 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3045 int optval = (index >> 8) & 0xff; 3046 index &= 0xff; 3047 if (index < 1 || index > sc->sc_maxports) { 3048 return -1; 3049 } 3050 port = XHCI_PORTSC(index); 3051 v = xhci_op_read_4(sc, port); 3052 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3053 v &= ~XHCI_PS_CLEAR; 3054 switch (value) { 3055 case UHF_PORT_ENABLE: 3056 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3057 break; 3058 case UHF_PORT_SUSPEND: 3059 /* XXX suspend */ 3060 break; 3061 case UHF_PORT_RESET: 3062 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3063 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3064 /* Wait for reset to complete. */ 3065 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3066 if (sc->sc_dying) { 3067 return -1; 3068 } 3069 v = xhci_op_read_4(sc, port); 3070 if (v & XHCI_PS_PR) { 3071 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3072 usb_delay_ms(&sc->sc_bus, 10); 3073 /* XXX */ 3074 } 3075 break; 3076 case UHF_PORT_POWER: 3077 /* XXX power control */ 3078 break; 3079 /* XXX more */ 3080 case UHF_C_PORT_RESET: 3081 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3082 break; 3083 case UHF_PORT_U1_TIMEOUT: 3084 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3085 return -1; 3086 } 3087 port = XHCI_PORTPMSC(index); 3088 v = xhci_op_read_4(sc, port); 3089 v &= ~XHCI_PM3_U1TO_SET(0xff); 3090 v |= XHCI_PM3_U1TO_SET(optval); 3091 xhci_op_write_4(sc, port, v); 3092 break; 3093 case UHF_PORT_U2_TIMEOUT: 3094 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3095 return -1; 3096 } 3097 port = XHCI_PORTPMSC(index); 3098 v = xhci_op_read_4(sc, port); 3099 v &= ~XHCI_PM3_U2TO_SET(0xff); 3100 v |= XHCI_PM3_U2TO_SET(optval); 3101 xhci_op_write_4(sc, port, v); 3102 break; 3103 default: 3104 return -1; 3105 } 3106 } 3107 break; 3108 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3109 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3110 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3111 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3112 break; 3113 default: 3114 /* default from usbroothub */ 3115 return buflen; 3116 } 3117 3118 return totlen; 3119 } 3120 3121 /* root hub interrupt */ 3122 3123 static usbd_status 3124 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3125 { 3126 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3127 usbd_status err; 3128 3129 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3130 3131 /* Insert last in queue. */ 3132 mutex_enter(&sc->sc_lock); 3133 err = usb_insert_transfer(xfer); 3134 mutex_exit(&sc->sc_lock); 3135 if (err) 3136 return err; 3137 3138 /* Pipe isn't running, start first */ 3139 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3140 } 3141 3142 /* Wait for roothub port status/change */ 3143 static usbd_status 3144 xhci_root_intr_start(struct usbd_xfer *xfer) 3145 { 3146 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3147 3148 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3149 3150 if (sc->sc_dying) 3151 return USBD_IOERROR; 3152 3153 mutex_enter(&sc->sc_lock); 3154 sc->sc_intrxfer = xfer; 3155 mutex_exit(&sc->sc_lock); 3156 3157 return USBD_IN_PROGRESS; 3158 } 3159 3160 static void 3161 xhci_root_intr_abort(struct usbd_xfer *xfer) 3162 { 3163 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3164 3165 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3166 3167 KASSERT(mutex_owned(&sc->sc_lock)); 3168 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3169 3170 sc->sc_intrxfer = NULL; 3171 3172 xfer->ux_status = USBD_CANCELLED; 3173 usb_transfer_complete(xfer); 3174 } 3175 3176 static void 3177 xhci_root_intr_close(struct usbd_pipe *pipe) 3178 { 3179 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3180 3181 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3182 3183 KASSERT(mutex_owned(&sc->sc_lock)); 3184 3185 sc->sc_intrxfer = NULL; 3186 } 3187 3188 static void 3189 xhci_root_intr_done(struct usbd_xfer *xfer) 3190 { 3191 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3192 3193 } 3194 3195 /* -------------- */ 3196 /* device control */ 3197 3198 static usbd_status 3199 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3200 { 3201 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3202 usbd_status err; 3203 3204 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3205 3206 /* Insert last in queue. */ 3207 mutex_enter(&sc->sc_lock); 3208 err = usb_insert_transfer(xfer); 3209 mutex_exit(&sc->sc_lock); 3210 if (err) 3211 return err; 3212 3213 /* Pipe isn't running, start first */ 3214 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3215 } 3216 3217 static usbd_status 3218 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3219 { 3220 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3221 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3222 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3223 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3224 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3225 usb_device_request_t * const req = &xfer->ux_request; 3226 const int isread = usbd_xfer_isread(xfer); 3227 const uint32_t len = UGETW(req->wLength); 3228 usb_dma_t * const dma = &xfer->ux_dmabuf; 3229 uint64_t parameter; 3230 uint32_t status; 3231 uint32_t control; 3232 u_int i; 3233 3234 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3235 DPRINTFN(12, "req: %04x %04x %04x %04x", 3236 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3237 UGETW(req->wIndex), UGETW(req->wLength)); 3238 3239 #if 0 /* event handler does this */ 3240 /* XXX */ 3241 if (tr->is_halted) { 3242 DPRINTFN(1, "ctrl xfer %p halted: slot %u dci %u", 3243 xfer, xs->xs_idx, dci, 0); 3244 xhci_reset_endpoint(xfer->ux_pipe); 3245 tr->is_halted = false; 3246 xhci_set_dequeue(xfer->ux_pipe); 3247 } 3248 #endif 3249 3250 /* we rely on the bottom bits for extra info */ 3251 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 3252 3253 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3254 3255 i = 0; 3256 3257 /* setup phase */ 3258 memcpy(¶meter, req, sizeof(*req)); 3259 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3260 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3261 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3262 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3263 XHCI_TRB_3_IDT_BIT; 3264 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3265 3266 if (len != 0) { 3267 /* data phase */ 3268 parameter = DMAADDR(dma, 0); 3269 KASSERT(len <= 0x10000); 3270 status = XHCI_TRB_2_IRQ_SET(0) | 3271 XHCI_TRB_2_TDSZ_SET(1) | 3272 XHCI_TRB_2_BYTES_SET(len); 3273 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3274 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3275 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3276 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3277 3278 parameter = (uintptr_t)xfer | 0x3; 3279 status = XHCI_TRB_2_IRQ_SET(0); 3280 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3281 XHCI_TRB_3_IOC_BIT; 3282 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3283 } 3284 3285 parameter = 0; 3286 status = XHCI_TRB_2_IRQ_SET(0); 3287 /* the status stage has inverted direction */ 3288 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3289 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3290 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3291 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3292 3293 parameter = (uintptr_t)xfer | 0x0; 3294 status = XHCI_TRB_2_IRQ_SET(0); 3295 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3296 XHCI_TRB_3_IOC_BIT; 3297 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3298 3299 mutex_enter(&tr->xr_lock); 3300 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3301 mutex_exit(&tr->xr_lock); 3302 3303 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3304 3305 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3306 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3307 xhci_timeout, xfer); 3308 } 3309 3310 if (sc->sc_bus.ub_usepolling) { 3311 DPRINTFN(1, "polling", 0, 0, 0, 0); 3312 //xhci_waitintr(sc, xfer); 3313 } 3314 3315 return USBD_IN_PROGRESS; 3316 } 3317 3318 static void 3319 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3320 { 3321 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3322 usb_device_request_t *req = &xfer->ux_request; 3323 int len = UGETW(req->wLength); 3324 int rd = req->bmRequestType & UT_READ; 3325 3326 if (len) 3327 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3328 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3329 } 3330 3331 static void 3332 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3333 { 3334 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3335 3336 xhci_abort_xfer(xfer, USBD_CANCELLED); 3337 } 3338 3339 static void 3340 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3341 { 3342 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3343 3344 xhci_close_pipe(pipe); 3345 } 3346 3347 /* ------------------ */ 3348 /* device isochronous */ 3349 3350 /* ----------- */ 3351 /* device bulk */ 3352 3353 static usbd_status 3354 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3355 { 3356 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3357 usbd_status err; 3358 3359 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3360 3361 /* Insert last in queue. */ 3362 mutex_enter(&sc->sc_lock); 3363 err = usb_insert_transfer(xfer); 3364 mutex_exit(&sc->sc_lock); 3365 if (err) 3366 return err; 3367 3368 /* 3369 * Pipe isn't running (otherwise err would be USBD_INPROG), 3370 * so start it first. 3371 */ 3372 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3373 } 3374 3375 static usbd_status 3376 xhci_device_bulk_start(struct usbd_xfer *xfer) 3377 { 3378 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3379 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3380 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3381 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3382 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3383 const uint32_t len = xfer->ux_length; 3384 usb_dma_t * const dma = &xfer->ux_dmabuf; 3385 uint64_t parameter; 3386 uint32_t status; 3387 uint32_t control; 3388 u_int i = 0; 3389 3390 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3391 3392 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3393 3394 if (sc->sc_dying) 3395 return USBD_IOERROR; 3396 3397 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3398 3399 parameter = DMAADDR(dma, 0); 3400 /* 3401 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3402 * If the user supplied buffer crosses such a boundary then 2 3403 * (or more) TRB should be used. 3404 * If multiple TRB are used the td_size field must be set correctly. 3405 * For v1.0 devices (like ivy bridge) this is the number of usb data 3406 * blocks needed to complete the transfer. 3407 * Setting it to 1 in the last TRB causes an extra zero-length 3408 * data block be sent. 3409 * The earlier documentation differs, I don't know how it behaves. 3410 */ 3411 KASSERT(len <= 0x10000); 3412 status = XHCI_TRB_2_IRQ_SET(0) | 3413 XHCI_TRB_2_TDSZ_SET(1) | 3414 XHCI_TRB_2_BYTES_SET(len); 3415 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3416 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3417 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3418 3419 mutex_enter(&tr->xr_lock); 3420 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3421 mutex_exit(&tr->xr_lock); 3422 3423 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3424 3425 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3426 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3427 xhci_timeout, xfer); 3428 } 3429 3430 if (sc->sc_bus.ub_usepolling) { 3431 DPRINTFN(1, "polling", 0, 0, 0, 0); 3432 //xhci_waitintr(sc, xfer); 3433 } 3434 3435 return USBD_IN_PROGRESS; 3436 } 3437 3438 static void 3439 xhci_device_bulk_done(struct usbd_xfer *xfer) 3440 { 3441 #ifdef USB_DEBUG 3442 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3443 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3444 #endif 3445 const int isread = usbd_xfer_isread(xfer); 3446 3447 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3448 3449 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3450 3451 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3452 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3453 } 3454 3455 static void 3456 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3457 { 3458 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3459 3460 xhci_abort_xfer(xfer, USBD_CANCELLED); 3461 } 3462 3463 static void 3464 xhci_device_bulk_close(struct usbd_pipe *pipe) 3465 { 3466 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3467 3468 xhci_close_pipe(pipe); 3469 } 3470 3471 /* ---------------- */ 3472 /* device interrupt */ 3473 3474 static usbd_status 3475 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3476 { 3477 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3478 usbd_status err; 3479 3480 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3481 3482 /* Insert last in queue. */ 3483 mutex_enter(&sc->sc_lock); 3484 err = usb_insert_transfer(xfer); 3485 mutex_exit(&sc->sc_lock); 3486 if (err) 3487 return err; 3488 3489 /* 3490 * Pipe isn't running (otherwise err would be USBD_INPROG), 3491 * so start it first. 3492 */ 3493 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3494 } 3495 3496 static usbd_status 3497 xhci_device_intr_start(struct usbd_xfer *xfer) 3498 { 3499 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3500 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3501 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3502 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3503 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3504 const uint32_t len = xfer->ux_length; 3505 usb_dma_t * const dma = &xfer->ux_dmabuf; 3506 uint64_t parameter; 3507 uint32_t status; 3508 uint32_t control; 3509 u_int i = 0; 3510 3511 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3512 3513 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3514 3515 if (sc->sc_dying) 3516 return USBD_IOERROR; 3517 3518 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3519 3520 parameter = DMAADDR(dma, 0); 3521 KASSERT(len <= 0x10000); 3522 status = XHCI_TRB_2_IRQ_SET(0) | 3523 XHCI_TRB_2_TDSZ_SET(1) | 3524 XHCI_TRB_2_BYTES_SET(len); 3525 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3526 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3527 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3528 3529 mutex_enter(&tr->xr_lock); 3530 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3531 mutex_exit(&tr->xr_lock); 3532 3533 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3534 3535 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3536 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3537 xhci_timeout, xfer); 3538 } 3539 3540 if (sc->sc_bus.ub_usepolling) { 3541 DPRINTFN(1, "polling", 0, 0, 0, 0); 3542 //xhci_waitintr(sc, xfer); 3543 } 3544 3545 return USBD_IN_PROGRESS; 3546 } 3547 3548 static void 3549 xhci_device_intr_done(struct usbd_xfer *xfer) 3550 { 3551 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3552 #ifdef USB_DEBUG 3553 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3554 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3555 #endif 3556 const int isread = usbd_xfer_isread(xfer); 3557 3558 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3559 3560 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3561 3562 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3563 3564 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3565 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3566 3567 #if 0 3568 device_printf(sc->sc_dev, ""); 3569 for (size_t i = 0; i < xfer->ux_length; i++) { 3570 printf(" %02x", ((uint8_t const *)xfer->ux_buffer)[i]); 3571 } 3572 printf("\n"); 3573 #endif 3574 3575 } 3576 3577 static void 3578 xhci_device_intr_abort(struct usbd_xfer *xfer) 3579 { 3580 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3581 3582 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3583 3584 KASSERT(mutex_owned(&sc->sc_lock)); 3585 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3586 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3587 xhci_abort_xfer(xfer, USBD_CANCELLED); 3588 } 3589 3590 static void 3591 xhci_device_intr_close(struct usbd_pipe *pipe) 3592 { 3593 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3594 3595 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3596 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3597 3598 xhci_close_pipe(pipe); 3599 } 3600 3601 /* ------------ */ 3602 3603 static void 3604 xhci_timeout(void *addr) 3605 { 3606 struct xhci_xfer * const xx = addr; 3607 struct usbd_xfer * const xfer = &xx->xx_xfer; 3608 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3609 3610 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3611 3612 if (sc->sc_dying) { 3613 return; 3614 } 3615 3616 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 3617 USB_TASKQ_MPSAFE); 3618 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 3619 USB_TASKQ_HC); 3620 } 3621 3622 static void 3623 xhci_timeout_task(void *addr) 3624 { 3625 struct usbd_xfer * const xfer = addr; 3626 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3627 3628 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3629 3630 mutex_enter(&sc->sc_lock); 3631 #if 0 3632 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3633 #else 3634 xfer->ux_status = USBD_TIMEOUT; 3635 usb_transfer_complete(xfer); 3636 #endif 3637 mutex_exit(&sc->sc_lock); 3638 } 3639
Indexes created Fri Sep 26 20:09:58 GMT 2025