xhci.c revision 1.4
1 /* $NetBSD: xhci.c,v 1.4 2013/10/18 08:39:22 apb Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.4 2013/10/18 08:39:22 apb Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/kmem.h> 36 #include <sys/malloc.h> 37 #include <sys/device.h> 38 #include <sys/select.h> 39 #include <sys/proc.h> 40 #include <sys/queue.h> 41 #include <sys/mutex.h> 42 #include <sys/condvar.h> 43 #include <sys/bus.h> 44 #include <sys/cpu.h> 45 46 #include <machine/endian.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 #include <dev/usb/usbdivar.h> 51 #include <dev/usb/usb_mem.h> 52 #include <dev/usb/usb_quirks.h> 53 54 #include <dev/usb/xhcireg.h> 55 #include <dev/usb/xhcivar.h> 56 #include <dev/usb/usbroothub_subr.h> 57 58 #ifdef XHCI_DEBUG 59 int xhcidebug = 0; 60 #define DPRINTF(x) do { if (xhcidebug) printf x; } while(0) 61 #define DPRINTFN(n,x) do { if (xhcidebug>(n)) printf x; } while (0) 62 #else 63 #define DPRINTF(x) 64 #define DPRINTFN(n,x) 65 #endif 66 67 #define XHCI_DCI_SLOT 0 68 #define XHCI_DCI_EP_CONTROL 1 69 70 #define XHCI_ICI_INPUT_CONTROL 0 71 72 struct xhci_pipe { 73 struct usbd_pipe xp_pipe; 74 }; 75 76 #define XHCI_INTR_ENDPT 1 77 #define XHCI_COMMAND_RING_TRBS 256 78 #define XHCI_EVENT_RING_TRBS 256 79 #define XHCI_EVENT_RING_SEGMENTS 1 80 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 81 82 static usbd_status xhci_open(usbd_pipe_handle); 83 static int xhci_intr1(struct xhci_softc * const); 84 static void xhci_softintr(void *); 85 static void xhci_poll(struct usbd_bus *); 86 static usbd_status xhci_allocm(struct usbd_bus *, usb_dma_t *, uint32_t); 87 static void xhci_freem(struct usbd_bus *, usb_dma_t *); 88 static usbd_xfer_handle xhci_allocx(struct usbd_bus *); 89 static void xhci_freex(struct usbd_bus *, usbd_xfer_handle); 90 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 91 static usbd_status xhci_new_device(device_t, usbd_bus_handle, int, int, int, 92 struct usbd_port *); 93 94 static usbd_status xhci_configure_endpoint(usbd_pipe_handle); 95 static usbd_status xhci_unconfigure_endpoint(usbd_pipe_handle); 96 static usbd_status xhci_reset_endpoint(usbd_pipe_handle); 97 //static usbd_status xhci_stop_endpoint(usbd_pipe_handle); 98 99 static usbd_status xhci_set_dequeue(usbd_pipe_handle); 100 101 static usbd_status xhci_do_command(struct xhci_softc * const, 102 struct xhci_trb * const, int); 103 static usbd_status xhci_init_slot(struct xhci_softc * const, uint32_t, 104 int, int, int, int); 105 static usbd_status xhci_enable_slot(struct xhci_softc * const, 106 uint8_t * const); 107 static usbd_status xhci_address_device(struct xhci_softc * const, 108 uint64_t, uint8_t, bool); 109 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 110 struct xhci_slot * const, u_int); 111 static usbd_status xhci_ring_init(struct xhci_softc * const, 112 struct xhci_ring * const, size_t, size_t); 113 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 114 115 static void xhci_noop(usbd_pipe_handle); 116 117 static usbd_status xhci_root_ctrl_transfer(usbd_xfer_handle); 118 static usbd_status xhci_root_ctrl_start(usbd_xfer_handle); 119 static void xhci_root_ctrl_abort(usbd_xfer_handle); 120 static void xhci_root_ctrl_close(usbd_pipe_handle); 121 static void xhci_root_ctrl_done(usbd_xfer_handle); 122 123 static usbd_status xhci_root_intr_transfer(usbd_xfer_handle); 124 static usbd_status xhci_root_intr_start(usbd_xfer_handle); 125 static void xhci_root_intr_abort(usbd_xfer_handle); 126 static void xhci_root_intr_close(usbd_pipe_handle); 127 static void xhci_root_intr_done(usbd_xfer_handle); 128 129 static usbd_status xhci_device_ctrl_transfer(usbd_xfer_handle); 130 static usbd_status xhci_device_ctrl_start(usbd_xfer_handle); 131 static void xhci_device_ctrl_abort(usbd_xfer_handle); 132 static void xhci_device_ctrl_close(usbd_pipe_handle); 133 static void xhci_device_ctrl_done(usbd_xfer_handle); 134 135 static usbd_status xhci_device_intr_transfer(usbd_xfer_handle); 136 static usbd_status xhci_device_intr_start(usbd_xfer_handle); 137 static void xhci_device_intr_abort(usbd_xfer_handle); 138 static void xhci_device_intr_close(usbd_pipe_handle); 139 static void xhci_device_intr_done(usbd_xfer_handle); 140 141 static usbd_status xhci_device_bulk_transfer(usbd_xfer_handle); 142 static usbd_status xhci_device_bulk_start(usbd_xfer_handle); 143 static void xhci_device_bulk_abort(usbd_xfer_handle); 144 static void xhci_device_bulk_close(usbd_pipe_handle); 145 static void xhci_device_bulk_done(usbd_xfer_handle); 146 147 static void xhci_timeout(void *); 148 static void xhci_timeout_task(void *); 149 150 static const struct usbd_bus_methods xhci_bus_methods = { 151 .open_pipe = xhci_open, 152 .soft_intr = xhci_softintr, 153 .do_poll = xhci_poll, 154 .allocm = xhci_allocm, 155 .freem = xhci_freem, 156 .allocx = xhci_allocx, 157 .freex = xhci_freex, 158 .get_lock = xhci_get_lock, 159 .new_device = xhci_new_device, 160 }; 161 162 static const struct usbd_pipe_methods xhci_root_ctrl_methods = { 163 .transfer = xhci_root_ctrl_transfer, 164 .start = xhci_root_ctrl_start, 165 .abort = xhci_root_ctrl_abort, 166 .close = xhci_root_ctrl_close, 167 .cleartoggle = xhci_noop, 168 .done = xhci_root_ctrl_done, 169 }; 170 171 static const struct usbd_pipe_methods xhci_root_intr_methods = { 172 .transfer = xhci_root_intr_transfer, 173 .start = xhci_root_intr_start, 174 .abort = xhci_root_intr_abort, 175 .close = xhci_root_intr_close, 176 .cleartoggle = xhci_noop, 177 .done = xhci_root_intr_done, 178 }; 179 180 181 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 182 .transfer = xhci_device_ctrl_transfer, 183 .start = xhci_device_ctrl_start, 184 .abort = xhci_device_ctrl_abort, 185 .close = xhci_device_ctrl_close, 186 .cleartoggle = xhci_noop, 187 .done = xhci_device_ctrl_done, 188 }; 189 190 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 191 .cleartoggle = xhci_noop, 192 }; 193 194 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 195 .transfer = xhci_device_bulk_transfer, 196 .start = xhci_device_bulk_start, 197 .abort = xhci_device_bulk_abort, 198 .close = xhci_device_bulk_close, 199 .cleartoggle = xhci_noop, 200 .done = xhci_device_bulk_done, 201 }; 202 203 static const struct usbd_pipe_methods xhci_device_intr_methods = { 204 .transfer = xhci_device_intr_transfer, 205 .start = xhci_device_intr_start, 206 .abort = xhci_device_intr_abort, 207 .close = xhci_device_intr_close, 208 .cleartoggle = xhci_noop, 209 .done = xhci_device_intr_done, 210 }; 211 212 static inline uint32_t 213 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 214 { 215 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 216 } 217 218 #if 0 /* unused */ 219 static inline void 220 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 221 uint32_t value) 222 { 223 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 224 } 225 #endif /* unused */ 226 227 static inline uint32_t 228 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 229 { 230 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 231 } 232 233 static inline uint32_t 234 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 235 { 236 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 237 } 238 239 static inline void 240 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 241 uint32_t value) 242 { 243 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 244 } 245 246 #if 0 /* unused */ 247 static inline uint64_t 248 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 249 { 250 uint64_t value; 251 252 if (sc->sc_ac64) { 253 #ifdef XHCI_USE_BUS_SPACE_8 254 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 255 #else 256 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 257 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 258 offset + 4) << 32; 259 #endif 260 } else { 261 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 262 } 263 264 return value; 265 } 266 #endif /* unused */ 267 268 static inline void 269 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 270 uint64_t value) 271 { 272 if (sc->sc_ac64) { 273 #ifdef XHCI_USE_BUS_SPACE_8 274 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 275 #else 276 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 277 (value >> 0) & 0xffffffff); 278 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 279 (value >> 32) & 0xffffffff); 280 #endif 281 } else { 282 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 283 } 284 } 285 286 static inline uint32_t 287 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 288 { 289 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 290 } 291 292 static inline void 293 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 294 uint32_t value) 295 { 296 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 297 } 298 299 #if 0 /* unused */ 300 static inline uint64_t 301 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 302 { 303 uint64_t value; 304 305 if (sc->sc_ac64) { 306 #ifdef XHCI_USE_BUS_SPACE_8 307 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 308 #else 309 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 310 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 311 offset + 4) << 32; 312 #endif 313 } else { 314 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 315 } 316 317 return value; 318 } 319 #endif /* unused */ 320 321 static inline void 322 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 336 } 337 } 338 339 #if 0 /* unused */ 340 static inline uint32_t 341 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 342 { 343 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 344 } 345 #endif /* unused */ 346 347 static inline void 348 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 349 uint32_t value) 350 { 351 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 352 } 353 354 /* --- */ 355 356 static inline uint8_t 357 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 358 { 359 u_int eptype; 360 361 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 362 case UE_CONTROL: 363 eptype = 0x0; 364 break; 365 case UE_ISOCHRONOUS: 366 eptype = 0x1; 367 break; 368 case UE_BULK: 369 eptype = 0x2; 370 break; 371 case UE_INTERRUPT: 372 eptype = 0x3; 373 break; 374 } 375 376 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 377 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 378 return eptype | 0x4; 379 else 380 return eptype; 381 } 382 383 static u_int 384 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 385 { 386 /* xHCI 1.0 section 4.5.1 */ 387 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 388 u_int in = 0; 389 390 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 391 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 392 in = 1; 393 394 return epaddr * 2 + in; 395 } 396 397 static inline u_int 398 xhci_dci_to_ici(const u_int i) 399 { 400 return i + 1; 401 } 402 403 static inline void * 404 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 405 const u_int dci) 406 { 407 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 408 } 409 410 #if 0 /* unused */ 411 static inline bus_addr_t 412 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 413 const u_int dci) 414 { 415 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 416 } 417 #endif /* unused */ 418 419 static inline void * 420 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 421 const u_int ici) 422 { 423 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 424 } 425 426 static inline bus_addr_t 427 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 428 const u_int ici) 429 { 430 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 431 } 432 433 static inline struct xhci_trb * 434 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 435 { 436 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 437 } 438 439 static inline bus_addr_t 440 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 441 { 442 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 443 } 444 445 static inline void 446 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 447 uint32_t control) 448 { 449 trb->trb_0 = parameter; 450 trb->trb_2 = status; 451 trb->trb_3 = control; 452 } 453 454 /* --- */ 455 456 void 457 xhci_childdet(device_t self, device_t child) 458 { 459 struct xhci_softc * const sc = device_private(self); 460 461 KASSERT(sc->sc_child == child); 462 if (child == sc->sc_child) 463 sc->sc_child = NULL; 464 } 465 466 int 467 xhci_detach(struct xhci_softc *sc, int flags) 468 { 469 int rv = 0; 470 471 if (sc->sc_child != NULL) 472 rv = config_detach(sc->sc_child, flags); 473 474 if (rv != 0) 475 return (rv); 476 477 /* XXX unconfigure/free slots */ 478 479 /* verify: */ 480 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 481 xhci_op_write_4(sc, XHCI_USBCMD, 0); 482 /* do we need to wait for stop? */ 483 484 xhci_op_write_8(sc, XHCI_CRCR, 0); 485 xhci_ring_free(sc, &sc->sc_cr); 486 cv_destroy(&sc->sc_command_cv); 487 488 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 489 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 490 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 491 xhci_ring_free(sc, &sc->sc_er); 492 493 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 494 495 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 496 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 497 498 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 499 500 mutex_destroy(&sc->sc_lock); 501 mutex_destroy(&sc->sc_intr_lock); 502 503 pool_cache_destroy(sc->sc_xferpool); 504 505 return rv; 506 } 507 508 int 509 xhci_activate(device_t self, enum devact act) 510 { 511 struct xhci_softc * const sc = device_private(self); 512 513 switch (act) { 514 case DVACT_DEACTIVATE: 515 sc->sc_dying = true; 516 return 0; 517 default: 518 return EOPNOTSUPP; 519 } 520 } 521 522 bool 523 xhci_suspend(device_t dv, const pmf_qual_t *qual) 524 { 525 return false; 526 } 527 528 bool 529 xhci_resume(device_t dv, const pmf_qual_t *qual) 530 { 531 return false; 532 } 533 534 bool 535 xhci_shutdown(device_t self, int flags) 536 { 537 return false; 538 } 539 540 541 static void 542 hexdump(const char *msg, const void *base, size_t len) 543 { 544 #if 0 545 size_t cnt; 546 const uint32_t *p; 547 extern paddr_t vtophys(vaddr_t); 548 549 p = base; 550 cnt = 0; 551 552 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 553 (void *)vtophys((vaddr_t)base)); 554 555 while (cnt < len) { 556 if (cnt % 16 == 0) 557 printf("%p: ", p); 558 else if (cnt % 8 == 0) 559 printf(" |"); 560 printf(" %08x", *p++); 561 cnt += 4; 562 if (cnt % 16 == 0) 563 printf("\n"); 564 } 565 #endif 566 } 567 568 569 usbd_status 570 xhci_init(struct xhci_softc *sc) 571 { 572 bus_size_t bsz; 573 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 574 uint32_t ecp, ecr; 575 uint32_t usbcmd, usbsts, pagesize, config; 576 int i; 577 uint16_t hciversion; 578 uint8_t caplength; 579 580 DPRINTF(("%s\n", __func__)); 581 582 sc->sc_bus.usbrev = USBREV_2_0; /* XXX Low/Full/High speeds for now */ 583 584 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 585 caplength = XHCI_CAP_CAPLENGTH(cap); 586 hciversion = XHCI_CAP_HCIVERSION(cap); 587 588 if ((hciversion < 0x0096) || (hciversion > 0x0100)) { 589 aprint_normal_dev(sc->sc_dev, 590 "xHCI version %x.%x not known to be supported\n", 591 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 592 } else { 593 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 594 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 595 } 596 597 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 598 &sc->sc_cbh) != 0) { 599 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 600 return USBD_NOMEM; 601 } 602 603 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 604 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 605 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 606 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 607 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 608 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 609 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 610 611 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 612 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 613 device_printf(sc->sc_dev, "ac64 %d ctxsz %d\n", sc->sc_ac64, 614 sc->sc_ctxsz); 615 616 device_printf(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 617 ecp = XHCI_HCC_XECP(hcc) * 4; 618 while (ecp != 0) { 619 ecr = xhci_read_4(sc, ecp); 620 device_printf(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 621 switch (XHCI_XECP_ID(ecr)) { 622 case XHCI_ID_PROTOCOLS: { 623 uint32_t w0, w4, w8; 624 uint16_t w2; 625 w0 = xhci_read_4(sc, ecp + 0); 626 w2 = (w0 >> 16) & 0xffff; 627 w4 = xhci_read_4(sc, ecp + 4); 628 w8 = xhci_read_4(sc, ecp + 8); 629 device_printf(sc->sc_dev, "SP: %08x %08x %08x\n", 630 w0, w4, w8); 631 if (w4 == 0x20425355 && w2 == 0x0300) { 632 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 633 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 634 } 635 if (w4 == 0x20425355 && w2 == 0x0200) { 636 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 637 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 638 } 639 break; 640 } 641 default: 642 break; 643 } 644 ecr = xhci_read_4(sc, ecp); 645 if (XHCI_XECP_NEXT(ecr) == 0) { 646 ecp = 0; 647 } else { 648 ecp += XHCI_XECP_NEXT(ecr) * 4; 649 } 650 } 651 652 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 653 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 654 &sc->sc_obh) != 0) { 655 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 656 return USBD_NOMEM; 657 } 658 659 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 660 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 661 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 662 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 663 return USBD_NOMEM; 664 } 665 666 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 667 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 668 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 669 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 670 return USBD_NOMEM; 671 } 672 673 for (i = 0; i < 100; i++) { 674 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 675 if ((usbsts & XHCI_STS_CNR) == 0) 676 break; 677 usb_delay_ms(&sc->sc_bus, 1); 678 } 679 if (i >= 100) 680 return USBD_IOERROR; 681 682 usbcmd = 0; 683 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 684 usb_delay_ms(&sc->sc_bus, 1); 685 686 usbcmd = XHCI_CMD_HCRST; 687 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 688 for (i = 0; i < 100; i++) { 689 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 690 if ((usbcmd & XHCI_CMD_HCRST) == 0) 691 break; 692 usb_delay_ms(&sc->sc_bus, 1); 693 } 694 if (i >= 100) 695 return USBD_IOERROR; 696 697 for (i = 0; i < 100; i++) { 698 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 699 if ((usbsts & XHCI_STS_CNR) == 0) 700 break; 701 usb_delay_ms(&sc->sc_bus, 1); 702 } 703 if (i >= 100) 704 return USBD_IOERROR; 705 706 device_printf(sc->sc_dev, "maxspbuf %d\n", XHCI_HCS2_MAXSPBUF(hcs2)); 707 if (XHCI_HCS2_MAXSPBUF(hcs2) != 0) { 708 /* XXX */ 709 aprint_error_dev(sc->sc_dev, 710 "TODO implement scratchpad allocation\n"); 711 return USBD_INVAL; 712 } 713 714 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 715 device_printf(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 716 pagesize = ffs(pagesize); 717 if (pagesize == 0) 718 return USBD_IOERROR; 719 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 720 device_printf(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 721 device_printf(sc->sc_dev, "sc_maxslots 0x%08x\n", 722 (uint32_t)sc->sc_maxslots); 723 724 config = xhci_op_read_4(sc, XHCI_CONFIG); 725 config &= ~0xFF; 726 config |= sc->sc_maxslots & 0xFF; 727 xhci_op_write_4(sc, XHCI_CONFIG, config); 728 729 usbd_status err; 730 731 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 732 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 733 if (err) { 734 aprint_error_dev(sc->sc_dev, "command ring init fail\n"); 735 return err; 736 } 737 738 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 739 XHCI_EVENT_RING_SEGMENTS_ALIGN); 740 if (err) { 741 aprint_error_dev(sc->sc_dev, "event ring init fail\n"); 742 return err; 743 } 744 745 { 746 usb_dma_t *dma; 747 size_t size; 748 size_t align; 749 750 dma = &sc->sc_eventst_dma; 751 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 752 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 753 KASSERT(size <= (512 * 1024)); 754 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 755 err = usb_allocmem(&sc->sc_bus, size, align, dma); 756 memset(KERNADDR(dma, 0), 0, size); 757 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 758 device_printf(sc->sc_dev, "eventst: %s %016jx %p %zx\n", 759 usbd_errstr(err), 760 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 761 KERNADDR(&sc->sc_eventst_dma, 0), 762 sc->sc_eventst_dma.block->size); 763 764 dma = &sc->sc_dcbaa_dma; 765 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 766 KASSERT(size <= 2048); 767 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 768 err = usb_allocmem(&sc->sc_bus, size, align, dma); 769 memset(KERNADDR(dma, 0), 0, size); 770 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 771 device_printf(sc->sc_dev, "dcbaa: %s %016jx %p %zx\n", 772 usbd_errstr(err), 773 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 774 KERNADDR(&sc->sc_dcbaa_dma, 0), 775 sc->sc_dcbaa_dma.block->size); 776 } 777 778 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 779 KM_SLEEP); 780 781 cv_init(&sc->sc_command_cv, "xhcicmd"); 782 783 struct xhci_erste *erst; 784 erst = KERNADDR(&sc->sc_eventst_dma, 0); 785 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 786 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 787 erst[0].erste_3 = htole32(0); 788 usb_syncmem(&sc->sc_eventst_dma, 0, 789 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 790 791 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 792 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 793 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 794 XHCI_ERDP_LO_BUSY); 795 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 796 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 797 sc->sc_cr.xr_cs); 798 799 #if 0 800 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 801 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 802 #endif 803 804 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 805 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 806 807 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 808 device_printf(sc->sc_dev, "USBCMD %08"PRIx32"\n", 809 xhci_op_read_4(sc, XHCI_USBCMD)); 810 811 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 812 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 813 cv_init(&sc->sc_softwake_cv, "xhciab"); 814 815 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 816 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 817 818 /* Set up the bus struct. */ 819 sc->sc_bus.methods = &xhci_bus_methods; 820 sc->sc_bus.pipe_size = sizeof(struct xhci_pipe); 821 822 return USBD_NORMAL_COMPLETION; 823 } 824 825 int 826 xhci_intr(void *v) 827 { 828 struct xhci_softc * const sc = v; 829 830 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev)) 831 return 0; 832 833 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 834 835 /* If we get an interrupt while polling, then just ignore it. */ 836 if (sc->sc_bus.use_polling) { 837 #ifdef DIAGNOSTIC 838 DPRINTFN(16, ("xhci_intr: ignored interrupt while polling\n")); 839 #endif 840 return 0; 841 } 842 843 return xhci_intr1(sc); 844 } 845 846 int 847 xhci_intr1(struct xhci_softc * const sc) 848 { 849 uint32_t usbsts; 850 uint32_t iman; 851 852 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 853 //device_printf(sc->sc_dev, "%s USBSTS %08x\n", __func__, usbsts); 854 #if 0 855 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 856 return 0; 857 } 858 #endif 859 xhci_op_write_4(sc, XHCI_USBSTS, 860 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 861 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 862 //device_printf(sc->sc_dev, "%s USBSTS %08x\n", __func__, usbsts); 863 864 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 865 //device_printf(sc->sc_dev, "%s IMAN0 %08x\n", __func__, iman); 866 if ((iman & XHCI_IMAN_INTR_PEND) == 0) { 867 return 0; 868 } 869 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 870 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 871 //device_printf(sc->sc_dev, "%s IMAN0 %08x\n", __func__, iman); 872 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 873 //device_printf(sc->sc_dev, "%s USBSTS %08x\n", __func__, usbsts); 874 875 sc->sc_bus.no_intrs++; 876 usb_schedsoftintr(&sc->sc_bus); 877 878 return 1; 879 } 880 881 static usbd_status 882 xhci_configure_endpoint(usbd_pipe_handle pipe) 883 { 884 struct xhci_softc * const sc = pipe->device->bus->hci_private; 885 struct xhci_slot * const xs = pipe->device->hci_private; 886 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 887 usb_endpoint_descriptor_t * const ed = pipe->endpoint->edesc; 888 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 889 struct xhci_trb trb; 890 usbd_status err; 891 uint32_t *cp; 892 893 device_printf(sc->sc_dev, "%s dci %u (0x%x)\n", __func__, dci, 894 pipe->endpoint->edesc->bEndpointAddress); 895 896 /* XXX ensure input context is available? */ 897 898 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 899 900 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 901 cp[0] = htole32(0); 902 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 903 904 /* set up input slot context */ 905 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 906 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 907 cp[1] = htole32(0); 908 cp[2] = htole32(0); 909 cp[3] = htole32(0); 910 911 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 912 if (xfertype == UE_INTERRUPT) { 913 cp[0] = htole32( 914 XHCI_EPCTX_0_IVAL_SET(3) /* XXX */ 915 ); 916 cp[1] = htole32( 917 XHCI_EPCTX_1_CERR_SET(3) | 918 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(pipe->endpoint->edesc)) | 919 XHCI_EPCTX_1_MAXB_SET(0) | 920 XHCI_EPCTX_1_MAXP_SIZE_SET(8) /* XXX */ 921 ); 922 cp[4] = htole32( 923 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 924 ); 925 } else { 926 cp[0] = htole32(0); 927 cp[1] = htole32( 928 XHCI_EPCTX_1_CERR_SET(3) | 929 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(pipe->endpoint->edesc)) | 930 XHCI_EPCTX_1_MAXB_SET(0) | 931 XHCI_EPCTX_1_MAXP_SIZE_SET(512) /* XXX */ 932 ); 933 } 934 *(uint64_t *)(&cp[2]) = htole64( 935 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 936 XHCI_EPCTX_2_DCS_SET(1)); 937 938 /* sync input contexts before they are read from memory */ 939 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 940 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 941 sc->sc_ctxsz * 1); 942 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 943 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 944 945 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 946 trb.trb_2 = 0; 947 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 948 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 949 950 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 951 952 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 953 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 954 sc->sc_ctxsz * 1); 955 956 return err; 957 } 958 959 static usbd_status 960 xhci_unconfigure_endpoint(usbd_pipe_handle pipe) 961 { 962 return USBD_NORMAL_COMPLETION; 963 } 964 965 static usbd_status 966 xhci_reset_endpoint(usbd_pipe_handle pipe) 967 { 968 struct xhci_softc * const sc = pipe->device->bus->hci_private; 969 struct xhci_slot * const xs = pipe->device->hci_private; 970 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 971 struct xhci_trb trb; 972 usbd_status err; 973 974 device_printf(sc->sc_dev, "%s\n", __func__); 975 976 trb.trb_0 = 0; 977 trb.trb_2 = 0; 978 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 979 XHCI_TRB_3_EP_SET(dci) | 980 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 981 982 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 983 984 return err; 985 } 986 987 #if 0 988 static usbd_status 989 xhci_stop_endpoint(usbd_pipe_handle pipe) 990 { 991 struct xhci_softc * const sc = pipe->device->bus->hci_private; 992 struct xhci_slot * const xs = pipe->device->hci_private; 993 struct xhci_trb trb; 994 usbd_status err; 995 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 996 997 device_printf(sc->sc_dev, "%s\n", __func__); 998 999 trb.trb_0 = 0; 1000 trb.trb_2 = 0; 1001 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1002 XHCI_TRB_3_EP_SET(dci) | 1003 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1004 1005 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1006 1007 return err; 1008 } 1009 #endif 1010 1011 static usbd_status 1012 xhci_set_dequeue(usbd_pipe_handle pipe) 1013 { 1014 struct xhci_softc * const sc = pipe->device->bus->hci_private; 1015 struct xhci_slot * const xs = pipe->device->hci_private; 1016 const u_int dci = xhci_ep_get_dci(pipe->endpoint->edesc); 1017 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1018 struct xhci_trb trb; 1019 usbd_status err; 1020 1021 device_printf(sc->sc_dev, "%s\n", __func__); 1022 1023 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1024 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1025 BUS_DMASYNC_PREWRITE); 1026 1027 xr->xr_ep = 0; 1028 xr->xr_cs = 1; 1029 1030 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1031 trb.trb_2 = 0; 1032 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1033 XHCI_TRB_3_EP_SET(dci) | 1034 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1035 1036 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1037 1038 return err; 1039 } 1040 1041 static usbd_status 1042 xhci_open(usbd_pipe_handle pipe) 1043 { 1044 usbd_device_handle const dev = pipe->device; 1045 struct xhci_softc * const sc = dev->bus->hci_private; 1046 usb_endpoint_descriptor_t * const ed = pipe->endpoint->edesc; 1047 const int8_t addr = dev->address; 1048 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1049 1050 DPRINTF(("%s\n", __func__)); 1051 DPRINTF(("addr %d\n", addr)); 1052 device_printf(sc->sc_dev, "%s addr %d depth %d port %d speed %d\n", 1053 __func__, addr, dev->depth, dev->powersrc->portno, dev->speed); 1054 1055 if (sc->sc_dying) 1056 return USBD_IOERROR; 1057 1058 /* Root Hub */ 1059 if (dev->depth == 0 && dev->powersrc->portno == 0 && 1060 dev->speed != USB_SPEED_SUPER) { 1061 switch (ed->bEndpointAddress) { 1062 case USB_CONTROL_ENDPOINT: 1063 pipe->methods = &xhci_root_ctrl_methods; 1064 break; 1065 case UE_DIR_IN | XHCI_INTR_ENDPT: 1066 pipe->methods = &xhci_root_intr_methods; 1067 break; 1068 default: 1069 pipe->methods = NULL; 1070 DPRINTF(("xhci_open: bad bEndpointAddress 0x%02x\n", 1071 ed->bEndpointAddress)); 1072 return USBD_INVAL; 1073 } 1074 return USBD_NORMAL_COMPLETION; 1075 } 1076 1077 switch (xfertype) { 1078 case UE_CONTROL: 1079 pipe->methods = &xhci_device_ctrl_methods; 1080 break; 1081 case UE_ISOCHRONOUS: 1082 pipe->methods = &xhci_device_isoc_methods; 1083 return USBD_INVAL; 1084 break; 1085 case UE_BULK: 1086 pipe->methods = &xhci_device_bulk_methods; 1087 break; 1088 case UE_INTERRUPT: 1089 pipe->methods = &xhci_device_intr_methods; 1090 break; 1091 default: 1092 return USBD_IOERROR; 1093 break; 1094 } 1095 1096 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1097 xhci_configure_endpoint(pipe); 1098 1099 return USBD_NORMAL_COMPLETION; 1100 } 1101 1102 static void 1103 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1104 { 1105 usbd_xfer_handle const xfer = sc->sc_intrxfer; 1106 uint8_t *p; 1107 1108 device_printf(sc->sc_dev, "port %u status change\n", port); 1109 1110 if (xfer == NULL) 1111 return; 1112 1113 if (!(port >= sc->sc_hs_port_start && 1114 port < sc->sc_hs_port_start + sc->sc_hs_port_count)) 1115 return; 1116 1117 port -= sc->sc_hs_port_start; 1118 port += 1; 1119 device_printf(sc->sc_dev, "hs port %u status change\n", port); 1120 1121 p = KERNADDR(&xfer->dmabuf, 0); 1122 memset(p, 0, xfer->length); 1123 p[port/NBBY] |= 1 << (port%NBBY); 1124 xfer->actlen = xfer->length; 1125 xfer->status = USBD_NORMAL_COMPLETION; 1126 usb_transfer_complete(xfer); 1127 } 1128 1129 static void 1130 xhci_handle_event(struct xhci_softc * const sc, const struct xhci_trb * const trb) 1131 { 1132 uint64_t trb_0; 1133 uint32_t trb_2, trb_3; 1134 1135 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1136 1137 trb_0 = le64toh(trb->trb_0); 1138 trb_2 = le32toh(trb->trb_2); 1139 trb_3 = le32toh(trb->trb_3); 1140 1141 #if 0 1142 device_printf(sc->sc_dev, 1143 "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"\n", trb, 1144 trb_0, trb_2, trb_3); 1145 #endif 1146 1147 switch (XHCI_TRB_3_TYPE_GET(trb_3)){ 1148 case XHCI_TRB_EVENT_TRANSFER: { 1149 u_int slot, dci; 1150 struct xhci_slot *xs; 1151 struct xhci_ring *xr; 1152 struct xhci_xfer *xx; 1153 usbd_xfer_handle xfer; 1154 usbd_status err; 1155 1156 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1157 dci = XHCI_TRB_3_EP_GET(trb_3); 1158 1159 xs = &sc->sc_slots[slot]; 1160 xr = &xs->xs_ep[dci].xe_tr; 1161 1162 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1163 xx = xr->xr_cookies[(trb_0 - xhci_ring_trbp(xr, 0))/ 1164 sizeof(struct xhci_trb)]; 1165 } else { 1166 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1167 } 1168 xfer = &xx->xx_xfer; 1169 #if 0 1170 device_printf(sc->sc_dev, "%s xfer %p\n", __func__, xfer); 1171 #endif 1172 1173 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1174 #if 0 1175 device_printf(sc->sc_dev, "transfer event data: " 1176 "0x%016"PRIx64" 0x%08"PRIx32" %02x\n", 1177 trb_0, XHCI_TRB_2_REM_GET(trb_2), 1178 XHCI_TRB_2_ERROR_GET(trb_2)); 1179 #endif 1180 if ((trb_0 & 0x3) == 0x3) { 1181 xfer->actlen = XHCI_TRB_2_REM_GET(trb_2); 1182 } 1183 } 1184 1185 if (XHCI_TRB_2_ERROR_GET(trb_2) == 1186 XHCI_TRB_ERROR_SUCCESS) { 1187 xfer->actlen = xfer->length - XHCI_TRB_2_REM_GET(trb_2); 1188 err = USBD_NORMAL_COMPLETION; 1189 } else if (XHCI_TRB_2_ERROR_GET(trb_2) == 1190 XHCI_TRB_ERROR_SHORT_PKT) { 1191 xfer->actlen = xfer->length - XHCI_TRB_2_REM_GET(trb_2); 1192 err = USBD_NORMAL_COMPLETION; 1193 } else if (XHCI_TRB_2_ERROR_GET(trb_2) == 1194 XHCI_TRB_ERROR_STALL) { 1195 err = USBD_STALLED; 1196 xr->is_halted = true; 1197 } else { 1198 err = USBD_IOERROR; 1199 } 1200 xfer->status = err; 1201 1202 //mutex_enter(&sc->sc_lock); /* XXX ??? */ 1203 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1204 if ((trb_0 & 0x3) == 0x0) { 1205 usb_transfer_complete(xfer); 1206 } 1207 } else { 1208 usb_transfer_complete(xfer); 1209 } 1210 //mutex_exit(&sc->sc_lock); /* XXX ??? */ 1211 1212 } 1213 break; 1214 case XHCI_TRB_EVENT_CMD_COMPLETE: 1215 if (trb_0 == sc->sc_command_addr) { 1216 sc->sc_result_trb.trb_0 = trb_0; 1217 sc->sc_result_trb.trb_2 = trb_2; 1218 sc->sc_result_trb.trb_3 = trb_3; 1219 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1220 XHCI_TRB_ERROR_SUCCESS) { 1221 device_printf(sc->sc_dev, "command completion " 1222 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1223 "0x%08"PRIx32"\n", trb_0, trb_2, trb_3); 1224 } 1225 cv_signal(&sc->sc_command_cv); 1226 } else { 1227 device_printf(sc->sc_dev, "event: %p 0x%016"PRIx64" " 1228 "0x%08"PRIx32" 0x%08"PRIx32"\n", trb, trb_0, 1229 trb_2, trb_3); 1230 } 1231 break; 1232 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1233 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1234 break; 1235 default: 1236 break; 1237 } 1238 } 1239 1240 static void 1241 xhci_softintr(void *v) 1242 { 1243 struct usbd_bus * const bus = v; 1244 struct xhci_softc * const sc = bus->hci_private; 1245 struct xhci_ring * const er = &sc->sc_er; 1246 struct xhci_trb *trb; 1247 int i, j, k; 1248 1249 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1250 1251 i = er->xr_ep; 1252 j = er->xr_cs; 1253 1254 while (1) { 1255 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 1256 BUS_DMASYNC_POSTREAD); 1257 trb = &er->xr_trb[i]; 1258 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1259 1260 if (j != k) 1261 break; 1262 1263 xhci_handle_event(sc, trb); 1264 1265 i++; 1266 if (i == XHCI_EVENT_RING_TRBS) { 1267 i = 0; 1268 j ^= 1; 1269 } 1270 } 1271 1272 er->xr_ep = i; 1273 er->xr_cs = j; 1274 1275 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 1276 XHCI_ERDP_LO_BUSY); 1277 1278 DPRINTF(("%s: %s ends\n", __func__, device_xname(sc->sc_dev))); 1279 1280 return; 1281 } 1282 1283 static void 1284 xhci_poll(struct usbd_bus *bus) 1285 { 1286 struct xhci_softc * const sc = bus->hci_private; 1287 1288 DPRINTF(("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1289 1290 xhci_intr1(sc); 1291 1292 return; 1293 } 1294 1295 static usbd_status 1296 xhci_allocm(struct usbd_bus *bus, usb_dma_t *dma, uint32_t size) 1297 { 1298 struct xhci_softc * const sc = bus->hci_private; 1299 usbd_status err; 1300 1301 DPRINTF(("%s\n", __func__)); 1302 1303 err = usb_allocmem_flags(&sc->sc_bus, size, 0, dma, 0); 1304 #if 0 1305 if (err == USBD_NOMEM) 1306 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1307 #endif 1308 #ifdef XHCI_DEBUG 1309 if (err) 1310 device_printf(sc->sc_dev, "xhci_allocm: usb_allocmem()=%d\n", 1311 err); 1312 #endif 1313 1314 return err; 1315 } 1316 1317 static void 1318 xhci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1319 { 1320 struct xhci_softc * const sc = bus->hci_private; 1321 1322 // DPRINTF(("%s\n", __func__)); 1323 1324 #if 0 1325 if (dma->block->flags & USB_DMA_RESERVE) { 1326 usb_reserve_freem(&sc->sc_dma_reserve, dma); 1327 return; 1328 } 1329 #endif 1330 usb_freemem(&sc->sc_bus, dma); 1331 } 1332 1333 static usbd_xfer_handle 1334 xhci_allocx(struct usbd_bus *bus) 1335 { 1336 struct xhci_softc * const sc = bus->hci_private; 1337 usbd_xfer_handle xfer; 1338 1339 // DPRINTF(("%s\n", __func__)); 1340 1341 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1342 if (xfer != NULL) { 1343 #ifdef DIAGNOSTIC 1344 memset(xfer, 0, sizeof(struct xhci_xfer)); 1345 xfer->busy_free = XFER_BUSY; 1346 #endif 1347 } 1348 1349 return xfer; 1350 } 1351 1352 static void 1353 xhci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1354 { 1355 struct xhci_softc * const sc = bus->hci_private; 1356 1357 // DPRINTF(("%s\n", __func__)); 1358 1359 #ifdef DIAGNOSTIC 1360 if (xfer->busy_free != XFER_BUSY) { 1361 device_printf(sc->sc_dev, "xhci_freex: xfer=%p " 1362 "not busy, 0x%08x\n", xfer, xfer->busy_free); 1363 } 1364 xfer->busy_free = XFER_FREE; 1365 #endif 1366 pool_cache_put(sc->sc_xferpool, xfer); 1367 } 1368 1369 static void 1370 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1371 { 1372 struct xhci_softc * const sc = bus->hci_private; 1373 1374 *lock = &sc->sc_lock; 1375 } 1376 1377 extern u_int32_t usb_cookie_no; 1378 1379 static usbd_status 1380 xhci_new_device(device_t parent, usbd_bus_handle bus, int depth, 1381 int speed, int port, struct usbd_port *up) 1382 { 1383 struct xhci_softc * const sc = bus->hci_private; 1384 usbd_device_handle dev; 1385 usbd_status err; 1386 usb_device_descriptor_t *dd; 1387 struct usbd_device *hub; 1388 struct usbd_device *adev; 1389 int rhport = 0; 1390 struct xhci_slot *xs; 1391 uint32_t *cp; 1392 uint8_t slot; 1393 uint8_t addr; 1394 1395 dev = malloc(sizeof *dev, M_USB, M_NOWAIT|M_ZERO); 1396 if (dev == NULL) 1397 return USBD_NOMEM; 1398 1399 dev->bus = bus; 1400 1401 /* Set up default endpoint handle. */ 1402 dev->def_ep.edesc = &dev->def_ep_desc; 1403 1404 /* Set up default endpoint descriptor. */ 1405 dev->def_ep_desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 1406 dev->def_ep_desc.bDescriptorType = UDESC_ENDPOINT; 1407 dev->def_ep_desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 1408 dev->def_ep_desc.bmAttributes = UE_CONTROL; 1409 /* XXX */ 1410 USETW(dev->def_ep_desc.wMaxPacketSize, 64); 1411 dev->def_ep_desc.bInterval = 0; 1412 1413 /* doesn't matter, just don't let it uninitialized */ 1414 dev->def_ep.datatoggle = 0; 1415 1416 device_printf(sc->sc_dev, "%s up %p portno %d\n", __func__, up, 1417 up->portno); 1418 1419 dev->quirks = &usbd_no_quirk; 1420 dev->address = 0; 1421 dev->ddesc.bMaxPacketSize = 0; 1422 dev->depth = depth; 1423 dev->powersrc = up; 1424 dev->myhub = up->parent; 1425 1426 up->device = dev; 1427 1428 /* Locate root hub port */ 1429 for (adev = dev, hub = dev; 1430 hub != NULL; 1431 adev = hub, hub = hub->myhub) { 1432 device_printf(sc->sc_dev, "%s hub %p\n", __func__, hub); 1433 } 1434 device_printf(sc->sc_dev, "%s hub %p\n", __func__, hub); 1435 1436 if (hub != NULL) { 1437 for (int p = 0; p < hub->hub->hubdesc.bNbrPorts; p++) { 1438 if (hub->hub->ports[p].device == adev) { 1439 rhport = p; 1440 } 1441 } 1442 } else { 1443 rhport = port; 1444 } 1445 if (speed == USB_SPEED_SUPER) { 1446 rhport += sc->sc_ss_port_start - 1; 1447 } else { 1448 rhport += sc->sc_hs_port_start - 1; 1449 } 1450 device_printf(sc->sc_dev, "%s rhport %d\n", __func__, rhport); 1451 1452 dev->speed = speed; 1453 dev->langid = USBD_NOLANG; 1454 dev->cookie.cookie = ++usb_cookie_no; 1455 1456 /* Establish the default pipe. */ 1457 err = usbd_setup_pipe(dev, 0, &dev->def_ep, USBD_DEFAULT_INTERVAL, 1458 &dev->default_pipe); 1459 if (err) { 1460 usbd_remove_device(dev, up); 1461 return (err); 1462 } 1463 1464 dd = &dev->ddesc; 1465 1466 if ((depth == 0) && (port == 0)) { 1467 KASSERT(bus->devices[dev->address] == NULL); 1468 bus->devices[dev->address] = dev; 1469 err = usbd_get_initial_ddesc(dev, dd); 1470 if (err) 1471 return err; 1472 err = usbd_reload_device_desc(dev); 1473 if (err) 1474 return err; 1475 } else { 1476 err = xhci_enable_slot(sc, &slot); 1477 if (err) 1478 return err; 1479 err = xhci_init_slot(sc, slot, depth, speed, port, rhport); 1480 if (err) 1481 return err; 1482 xs = &sc->sc_slots[slot]; 1483 dev->hci_private = xs; 1484 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 1485 //hexdump("slot context", cp, sc->sc_ctxsz); 1486 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 1487 device_printf(sc->sc_dev, "%s device address %u\n", 1488 __func__, addr); 1489 /* XXX ensure we know when the hardware does something 1490 we can't yet cope with */ 1491 KASSERT(addr >= 1 && addr <= 127); 1492 dev->address = addr; 1493 /* XXX dev->address not necessarily unique on bus */ 1494 KASSERT(bus->devices[dev->address] == NULL); 1495 bus->devices[dev->address] = dev; 1496 1497 err = usbd_get_initial_ddesc(dev, dd); 1498 if (err) 1499 return err; 1500 USETW(dev->def_ep_desc.wMaxPacketSize, dd->bMaxPacketSize); 1501 device_printf(sc->sc_dev, "%s bMaxPacketSize %u\n", __func__, 1502 dd->bMaxPacketSize); 1503 xhci_update_ep0_mps(sc, xs, dd->bMaxPacketSize); 1504 err = usbd_reload_device_desc(dev); 1505 if (err) 1506 return err; 1507 1508 usbd_kill_pipe(dev->default_pipe); 1509 err = usbd_setup_pipe(dev, 0, &dev->def_ep, 1510 USBD_DEFAULT_INTERVAL, &dev->default_pipe); 1511 } 1512 1513 DPRINTF(("usbd_new_device: adding unit addr=%d, rev=%02x, class=%d, " 1514 "subclass=%d, protocol=%d, maxpacket=%d, len=%d, noconf=%d, " 1515 "speed=%d\n", dev->address,UGETW(dd->bcdUSB), 1516 dd->bDeviceClass, dd->bDeviceSubClass, dd->bDeviceProtocol, 1517 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 1518 dev->speed)); 1519 1520 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 1521 1522 if ((depth == 0) && (port == 0)) { 1523 usbd_attach_roothub(parent, dev); 1524 device_printf(sc->sc_dev, "root_hub %p\n", bus->root_hub); 1525 return USBD_NORMAL_COMPLETION; 1526 } 1527 1528 1529 err = usbd_probe_and_attach(parent, dev, port, dev->address); 1530 if (err) { 1531 usbd_remove_device(dev, up); 1532 return (err); 1533 } 1534 1535 return USBD_NORMAL_COMPLETION; 1536 } 1537 1538 static usbd_status 1539 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 1540 size_t ntrb, size_t align) 1541 { 1542 usbd_status err; 1543 size_t size = ntrb * XHCI_TRB_SIZE; 1544 1545 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 1546 if (err) 1547 return err; 1548 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1549 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 1550 xr->xr_trb = xhci_ring_trbv(xr, 0); 1551 xr->xr_ntrb = ntrb; 1552 xr->xr_ep = 0; 1553 xr->xr_cs = 1; 1554 memset(xr->xr_trb, 0, size); 1555 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 1556 xr->is_halted = false; 1557 1558 return USBD_NORMAL_COMPLETION; 1559 } 1560 1561 static void 1562 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 1563 { 1564 usb_freemem(&sc->sc_bus, &xr->xr_dma); 1565 mutex_destroy(&xr->xr_lock); 1566 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 1567 } 1568 1569 static void 1570 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 1571 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 1572 { 1573 size_t i; 1574 u_int ri; 1575 u_int cs; 1576 uint64_t parameter; 1577 uint32_t status; 1578 uint32_t control; 1579 1580 for (i = 0; i < ntrbs; i++) { 1581 #if 0 1582 device_printf(sc->sc_dev, "%s %p %p %zu " 1583 "%016"PRIx64" %08"PRIx32" %08"PRIx32"\n", __func__, xr, 1584 trbs, i, trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3); 1585 #endif 1586 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 1587 XHCI_TRB_TYPE_LINK); 1588 } 1589 1590 #if 0 1591 device_printf(sc->sc_dev, "%s %p xr_ep 0x%x xr_cs %u\n", __func__, 1592 xr, xr->xr_ep, xr->xr_cs); 1593 #endif 1594 1595 ri = xr->xr_ep; 1596 cs = xr->xr_cs; 1597 1598 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 1599 parameter = xhci_ring_trbp(xr, 0); 1600 status = 0; 1601 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1602 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 1603 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 1604 htole32(status), htole32(control)); 1605 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1606 BUS_DMASYNC_PREWRITE); 1607 xr->xr_cookies[ri] = NULL; 1608 xr->xr_ep = 0; 1609 xr->xr_cs ^= 1; 1610 ri = xr->xr_ep; 1611 cs = xr->xr_cs; 1612 } 1613 1614 ri++; 1615 1616 for (i = 1; i < ntrbs; i++) { 1617 parameter = trbs[i].trb_0; 1618 status = trbs[i].trb_2; 1619 control = trbs[i].trb_3; 1620 1621 if (cs) { 1622 control |= XHCI_TRB_3_CYCLE_BIT; 1623 } else { 1624 control &= ~XHCI_TRB_3_CYCLE_BIT; 1625 } 1626 1627 xhci_trb_put(&xr->xr_trb[ri], htole64(parameter), 1628 htole32(status), htole32(control)); 1629 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1630 BUS_DMASYNC_PREWRITE); 1631 xr->xr_cookies[ri] = cookie; 1632 ri++; 1633 } 1634 1635 i = 0; 1636 { 1637 parameter = trbs[i].trb_0; 1638 status = trbs[i].trb_2; 1639 control = trbs[i].trb_3; 1640 1641 if (xr->xr_cs) { 1642 control |= XHCI_TRB_3_CYCLE_BIT; 1643 } else { 1644 control &= ~XHCI_TRB_3_CYCLE_BIT; 1645 } 1646 1647 xhci_trb_put(&xr->xr_trb[xr->xr_ep], htole64(parameter), 1648 htole32(status), htole32(control)); 1649 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 1650 BUS_DMASYNC_PREWRITE); 1651 xr->xr_cookies[xr->xr_ep] = cookie; 1652 } 1653 1654 xr->xr_ep = ri; 1655 xr->xr_cs = cs; 1656 1657 #if 0 1658 device_printf(sc->sc_dev, "%s %p xr_ep 0x%x xr_cs %u\n", __func__, 1659 xr, xr->xr_ep, xr->xr_cs); 1660 #endif 1661 } 1662 1663 static usbd_status 1664 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 1665 int timeout) 1666 { 1667 struct xhci_ring * const cr = &sc->sc_cr; 1668 usbd_status err; 1669 1670 device_printf(sc->sc_dev, "%s input: " 1671 "0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"\n", __func__, 1672 trb->trb_0, trb->trb_2, trb->trb_3); 1673 1674 mutex_enter(&sc->sc_lock); 1675 1676 KASSERT(sc->sc_command_addr == 0); 1677 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 1678 1679 mutex_enter(&cr->xr_lock); 1680 xhci_ring_put(sc, cr, NULL, trb, 1); 1681 mutex_exit(&cr->xr_lock); 1682 1683 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 1684 1685 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 1686 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 1687 err = USBD_TIMEOUT; 1688 goto timedout; 1689 } 1690 1691 trb->trb_0 = sc->sc_result_trb.trb_0; 1692 trb->trb_2 = sc->sc_result_trb.trb_2; 1693 trb->trb_3 = sc->sc_result_trb.trb_3; 1694 1695 device_printf(sc->sc_dev, "%s output: " 1696 "0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"\n", __func__, 1697 trb->trb_0, trb->trb_2, trb->trb_3); 1698 1699 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 1700 case XHCI_TRB_ERROR_SUCCESS: 1701 err = USBD_NORMAL_COMPLETION; 1702 break; 1703 default: 1704 case 192 ... 223: 1705 err = USBD_IOERROR; 1706 break; 1707 case 224 ... 255: 1708 err = USBD_NORMAL_COMPLETION; 1709 break; 1710 } 1711 1712 timedout: 1713 sc->sc_command_addr = 0; 1714 mutex_exit(&sc->sc_lock); 1715 return err; 1716 } 1717 1718 static usbd_status 1719 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 1720 { 1721 struct xhci_trb trb; 1722 usbd_status err; 1723 1724 trb.trb_0 = 0; 1725 trb.trb_2 = 0; 1726 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 1727 1728 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1729 if (err != USBD_NORMAL_COMPLETION) { 1730 return err; 1731 } 1732 1733 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 1734 1735 return err; 1736 } 1737 1738 static usbd_status 1739 xhci_address_device(struct xhci_softc * const sc, 1740 uint64_t icp, uint8_t slot_id, bool bsr) 1741 { 1742 struct xhci_trb trb; 1743 usbd_status err; 1744 1745 trb.trb_0 = icp; 1746 trb.trb_2 = 0; 1747 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 1748 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1749 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 1750 1751 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1752 return err; 1753 } 1754 1755 static usbd_status 1756 xhci_update_ep0_mps(struct xhci_softc * const sc, 1757 struct xhci_slot * const xs, u_int mps) 1758 { 1759 struct xhci_trb trb; 1760 usbd_status err; 1761 uint32_t * cp; 1762 1763 device_printf(sc->sc_dev, "%s\n", __func__); 1764 1765 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1766 cp[0] = htole32(0); 1767 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 1768 1769 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 1770 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1771 1772 /* sync input contexts before they are read from memory */ 1773 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1774 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 1775 sc->sc_ctxsz * 4); 1776 1777 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1778 trb.trb_2 = 0; 1779 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1780 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 1781 1782 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1783 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 1784 return err; 1785 } 1786 1787 static void 1788 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 1789 { 1790 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 1791 1792 device_printf(sc->sc_dev, "dcbaa %p dc %016"PRIx64" slot %d\n", 1793 &dcbaa[si], dcba, si); 1794 1795 dcbaa[si] = dcba; 1796 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 1797 BUS_DMASYNC_PREWRITE); 1798 } 1799 1800 static usbd_status 1801 xhci_init_slot(struct xhci_softc * const sc, uint32_t slot, int depth, 1802 int speed, int port, int rhport) 1803 { 1804 struct xhci_slot *xs; 1805 usbd_status err; 1806 u_int dci; 1807 uint32_t *cp; 1808 uint32_t mps; 1809 uint32_t xspeed; 1810 1811 switch (speed) { 1812 case USB_SPEED_LOW: 1813 xspeed = 2; 1814 mps = USB_MAX_IPACKET; 1815 break; 1816 case USB_SPEED_FULL: 1817 xspeed = 1; 1818 mps = 64; 1819 break; 1820 case USB_SPEED_HIGH: 1821 xspeed = 3; 1822 mps = USB_2_MAX_CTRL_PACKET; 1823 break; 1824 case USB_SPEED_SUPER: 1825 xspeed = 4; 1826 mps = USB_3_MAX_CTRL_PACKET; 1827 break; 1828 } 1829 1830 xs = &sc->sc_slots[slot]; 1831 xs->xs_idx = slot; 1832 1833 /* allocate contexts */ 1834 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 1835 &xs->xs_dc_dma); 1836 if (err) 1837 return err; 1838 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 1839 1840 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 1841 &xs->xs_ic_dma); 1842 if (err) 1843 return err; 1844 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 1845 1846 for (dci = 0; dci < 32; dci++) { 1847 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 1848 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 1849 if (dci == XHCI_DCI_SLOT) 1850 continue; 1851 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 1852 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 1853 if (err) { 1854 device_printf(sc->sc_dev, "ring init failure\n"); 1855 return err; 1856 } 1857 } 1858 1859 /* set up initial input control context */ 1860 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1861 cp[0] = htole32(0); 1862 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 1863 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 1864 1865 /* set up input slot context */ 1866 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1867 cp[0] = htole32( 1868 XHCI_SCTX_0_CTX_NUM_SET(1) | 1869 XHCI_SCTX_0_SPEED_SET(xspeed) 1870 ); 1871 cp[1] = htole32( 1872 XHCI_SCTX_1_RH_PORT_SET(rhport) 1873 ); 1874 cp[2] = htole32( 1875 XHCI_SCTX_2_IRQ_TARGET_SET(0) 1876 ); 1877 cp[3] = htole32(0); 1878 1879 /* set up input EP0 context */ 1880 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 1881 cp[0] = htole32(0); 1882 cp[1] = htole32( 1883 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 1884 XHCI_EPCTX_1_EPTYPE_SET(4) | 1885 XHCI_EPCTX_1_CERR_SET(3) 1886 ); 1887 /* can't use xhci_ep_get_dci() yet? */ 1888 *(uint64_t *)(&cp[2]) = htole64( 1889 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 1890 XHCI_EPCTX_2_DCS_SET(1)); 1891 cp[4] = htole32( 1892 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 1893 ); 1894 1895 /* sync input contexts before they are read from memory */ 1896 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1897 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 1898 sc->sc_ctxsz * 3); 1899 1900 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 1901 1902 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 1903 false); 1904 1905 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1906 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 1907 sc->sc_ctxsz * 2); 1908 1909 return err; 1910 } 1911 1912 /* ----- */ 1913 1914 static void 1915 xhci_noop(usbd_pipe_handle pipe) 1916 { 1917 DPRINTF(("%s\n", __func__)); 1918 } 1919 1920 /* root hub descriptors */ 1921 1922 static const usb_device_descriptor_t xhci_devd = { 1923 USB_DEVICE_DESCRIPTOR_SIZE, 1924 UDESC_DEVICE, /* type */ 1925 {0x00, 0x02}, /* USB version */ 1926 UDCLASS_HUB, /* class */ 1927 UDSUBCLASS_HUB, /* subclass */ 1928 UDPROTO_HSHUBSTT, /* protocol */ 1929 64, /* max packet */ 1930 {0},{0},{0x00,0x01}, /* device id */ 1931 1,2,0, /* string indexes */ 1932 1 /* # of configurations */ 1933 }; 1934 1935 static const usb_device_qualifier_t xhci_odevd = { 1936 USB_DEVICE_DESCRIPTOR_SIZE, 1937 UDESC_DEVICE_QUALIFIER, /* type */ 1938 {0x00, 0x02}, /* USB version */ 1939 UDCLASS_HUB, /* class */ 1940 UDSUBCLASS_HUB, /* subclass */ 1941 UDPROTO_FSHUB, /* protocol */ 1942 64, /* max packet */ 1943 1, /* # of configurations */ 1944 0 1945 }; 1946 1947 static const usb_config_descriptor_t xhci_confd = { 1948 USB_CONFIG_DESCRIPTOR_SIZE, 1949 UDESC_CONFIG, 1950 {USB_CONFIG_DESCRIPTOR_SIZE + 1951 USB_INTERFACE_DESCRIPTOR_SIZE + 1952 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1953 1, 1954 1, 1955 0, 1956 UC_ATTR_MBO | UC_SELF_POWERED, 1957 0 /* max power */ 1958 }; 1959 1960 static const usb_interface_descriptor_t xhci_ifcd = { 1961 USB_INTERFACE_DESCRIPTOR_SIZE, 1962 UDESC_INTERFACE, 1963 0, 1964 0, 1965 1, 1966 UICLASS_HUB, 1967 UISUBCLASS_HUB, 1968 UIPROTO_HSHUBSTT, 1969 0 1970 }; 1971 1972 static const usb_endpoint_descriptor_t xhci_endpd = { 1973 USB_ENDPOINT_DESCRIPTOR_SIZE, 1974 UDESC_ENDPOINT, 1975 UE_DIR_IN | XHCI_INTR_ENDPT, 1976 UE_INTERRUPT, 1977 {8, 0}, /* max packet */ 1978 12 1979 }; 1980 1981 static const usb_hub_descriptor_t xhci_hubd = { 1982 USB_HUB_DESCRIPTOR_SIZE, 1983 UDESC_HUB, 1984 0, 1985 {0,0}, 1986 0, 1987 0, 1988 {""}, 1989 {""}, 1990 }; 1991 1992 /* root hub control */ 1993 1994 static usbd_status 1995 xhci_root_ctrl_transfer(usbd_xfer_handle xfer) 1996 { 1997 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 1998 usbd_status err; 1999 2000 DPRINTF(("%s\n", __func__)); 2001 2002 /* Insert last in queue. */ 2003 mutex_enter(&sc->sc_lock); 2004 err = usb_insert_transfer(xfer); 2005 mutex_exit(&sc->sc_lock); 2006 if (err) 2007 return err; 2008 2009 /* Pipe isn't running, start first */ 2010 return (xhci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2011 } 2012 2013 static usbd_status 2014 xhci_root_ctrl_start(usbd_xfer_handle xfer) 2015 { 2016 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2017 usb_port_status_t ps; 2018 usb_device_request_t *req; 2019 void *buf = NULL; 2020 usb_hub_descriptor_t hubd; 2021 usbd_status err; 2022 int len, value, index; 2023 int l, totlen = 0; 2024 int port, i; 2025 uint32_t v; 2026 2027 DPRINTF(("%s\n", __func__)); 2028 2029 if (sc->sc_dying) 2030 return USBD_IOERROR; 2031 2032 req = &xfer->request; 2033 2034 value = UGETW(req->wValue); 2035 index = UGETW(req->wIndex); 2036 len = UGETW(req->wLength); 2037 2038 if (len != 0) 2039 buf = KERNADDR(&xfer->dmabuf, 0); 2040 2041 DPRINTF(("root req: %02x %02x %04x %04x %04x\n", req->bmRequestType, 2042 req->bRequest, value, index, len)); 2043 2044 #define C(x,y) ((x) | ((y) << 8)) 2045 switch(C(req->bRequest, req->bmRequestType)) { 2046 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2047 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2048 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2049 /* 2050 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2051 * for the integrated root hub. 2052 */ 2053 break; 2054 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2055 if (len > 0) { 2056 *(uint8_t *)buf = sc->sc_conf; 2057 totlen = 1; 2058 } 2059 break; 2060 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2061 DPRINTFN(8,("xhci_root_ctrl_start: wValue=0x%04x\n", value)); 2062 if (len == 0) 2063 break; 2064 switch(value >> 8) { 2065 case UDESC_DEVICE: 2066 if ((value & 0xff) != 0) { 2067 err = USBD_IOERROR; 2068 goto ret; 2069 } 2070 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2071 memcpy(buf, &xhci_devd, l); 2072 break; 2073 case UDESC_DEVICE_QUALIFIER: 2074 if ((value & 0xff) != 0) { 2075 } 2076 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2077 memcpy(buf, &xhci_odevd, l); 2078 break; 2079 case UDESC_OTHER_SPEED_CONFIGURATION: 2080 case UDESC_CONFIG: 2081 if ((value & 0xff) != 0) { 2082 err = USBD_IOERROR; 2083 goto ret; 2084 } 2085 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2086 memcpy(buf, &xhci_confd, l); 2087 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2088 value >> 8; 2089 buf = (char *)buf + l; 2090 len -= l; 2091 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2092 totlen += l; 2093 memcpy(buf, &xhci_ifcd, l); 2094 buf = (char *)buf + l; 2095 len -= l; 2096 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2097 totlen += l; 2098 memcpy(buf, &xhci_endpd, l); 2099 break; 2100 case UDESC_STRING: 2101 #define sd ((usb_string_descriptor_t *)buf) 2102 switch (value & 0xff) { 2103 case 0: /* Language table */ 2104 totlen = usb_makelangtbl(sd, len); 2105 break; 2106 case 1: /* Vendor */ 2107 totlen = usb_makestrdesc(sd, len, "NetBSD"); 2108 break; 2109 case 2: /* Product */ 2110 totlen = usb_makestrdesc(sd, len, 2111 "xHCI Root Hub"); 2112 break; 2113 } 2114 #undef sd 2115 break; 2116 default: 2117 err = USBD_IOERROR; 2118 goto ret; 2119 } 2120 break; 2121 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2122 if (len > 0) { 2123 *(uint8_t *)buf = 0; 2124 totlen = 1; 2125 } 2126 break; 2127 case C(UR_GET_STATUS, UT_READ_DEVICE): 2128 if (len > 1) { 2129 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2130 totlen = 2; 2131 } 2132 break; 2133 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2134 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2135 if (len > 1) { 2136 USETW(((usb_status_t *)buf)->wStatus, 0); 2137 totlen = 2; 2138 } 2139 break; 2140 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2141 if (value >= USB_MAX_DEVICES) { 2142 err = USBD_IOERROR; 2143 goto ret; 2144 } 2145 //sc->sc_addr = value; 2146 break; 2147 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2148 if (value != 0 && value != 1) { 2149 err = USBD_IOERROR; 2150 goto ret; 2151 } 2152 sc->sc_conf = value; 2153 break; 2154 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2155 break; 2156 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2157 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2158 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2159 err = USBD_IOERROR; 2160 goto ret; 2161 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2162 break; 2163 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2164 break; 2165 /* Hub requests */ 2166 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2167 break; 2168 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2169 DPRINTFN(4, ("xhci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2170 "port=%d feature=%d\n", 2171 index, value)); 2172 if (index < 1 || index > sc->sc_hs_port_count) { 2173 err = USBD_IOERROR; 2174 goto ret; 2175 } 2176 port = XHCI_PORTSC(sc->sc_hs_port_start - 1 + index); 2177 v = xhci_op_read_4(sc, port); 2178 DPRINTFN(4, ("xhci_root_ctrl_start: portsc=0x%08x\n", v)); 2179 v &= ~XHCI_PS_CLEAR; 2180 switch (value) { 2181 case UHF_PORT_ENABLE: 2182 xhci_op_write_4(sc, port, v &~ XHCI_PS_PED); 2183 break; 2184 case UHF_PORT_SUSPEND: 2185 err = USBD_IOERROR; 2186 goto ret; 2187 case UHF_PORT_POWER: 2188 break; 2189 case UHF_PORT_TEST: 2190 case UHF_PORT_INDICATOR: 2191 err = USBD_IOERROR; 2192 goto ret; 2193 case UHF_C_PORT_CONNECTION: 2194 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 2195 break; 2196 case UHF_C_PORT_ENABLE: 2197 case UHF_C_PORT_SUSPEND: 2198 case UHF_C_PORT_OVER_CURRENT: 2199 err = USBD_IOERROR; 2200 goto ret; 2201 case UHF_C_PORT_RESET: 2202 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2203 break; 2204 default: 2205 err = USBD_IOERROR; 2206 goto ret; 2207 } 2208 2209 break; 2210 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2211 if (len == 0) 2212 break; 2213 if ((value & 0xff) != 0) { 2214 err = USBD_IOERROR; 2215 goto ret; 2216 } 2217 hubd = xhci_hubd; 2218 hubd.bNbrPorts = sc->sc_hs_port_count; 2219 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 2220 hubd.bPwrOn2PwrGood = 200; 2221 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 2222 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2223 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2224 l = min(len, hubd.bDescLength); 2225 totlen = l; 2226 memcpy(buf, &hubd, l); 2227 break; 2228 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2229 if (len != 4) { 2230 err = USBD_IOERROR; 2231 goto ret; 2232 } 2233 memset(buf, 0, len); /* ? XXX */ 2234 totlen = len; 2235 break; 2236 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2237 DPRINTFN(8,("xhci_root_ctrl_start: get port status i=%d\n", 2238 index)); 2239 if (index < 1 || index > sc->sc_maxports) { 2240 err = USBD_IOERROR; 2241 goto ret; 2242 } 2243 if (len != 4) { 2244 err = USBD_IOERROR; 2245 goto ret; 2246 } 2247 v = xhci_op_read_4(sc, XHCI_PORTSC(sc->sc_hs_port_start - 1 + 2248 index)); 2249 DPRINTF(("%s READ_CLASS_OTHER GET_STATUS PORTSC %d (%d) %08x\n", 2250 __func__, index, sc->sc_hs_port_start - 1 + index, v)); 2251 switch (XHCI_PS_SPEED_GET(v)) { 2252 case 1: 2253 i = UPS_FULL_SPEED; 2254 break; 2255 case 2: 2256 i = UPS_LOW_SPEED; 2257 break; 2258 case 3: 2259 i = UPS_HIGH_SPEED; 2260 break; 2261 default: 2262 i = 0; 2263 break; 2264 } 2265 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 2266 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 2267 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2268 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 2269 if (v & XHCI_PS_PR) i |= UPS_RESET; 2270 if (v & XHCI_PS_PP) i |= UPS_PORT_POWER; 2271 USETW(ps.wPortStatus, i); 2272 i = 0; 2273 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2274 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2275 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2276 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 2277 USETW(ps.wPortChange, i); 2278 l = min(len, sizeof ps); 2279 memcpy(buf, &ps, l); 2280 totlen = l; 2281 break; 2282 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2283 err = USBD_IOERROR; 2284 goto ret; 2285 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2286 break; 2287 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2288 if (index < 1 || index > sc->sc_hs_port_count) { 2289 err = USBD_IOERROR; 2290 goto ret; 2291 } 2292 port = XHCI_PORTSC(sc->sc_hs_port_start - 1 + index); 2293 v = xhci_op_read_4(sc, port); 2294 DPRINTFN(4, ("xhci_root_ctrl_start: portsc=0x%08x\n", v)); 2295 v &= ~XHCI_PS_CLEAR; 2296 switch (value) { 2297 case UHF_PORT_ENABLE: 2298 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 2299 break; 2300 case UHF_PORT_SUSPEND: 2301 /* XXX suspend */ 2302 break; 2303 case UHF_PORT_RESET: 2304 v &= ~ (XHCI_PS_PED | XHCI_PS_PR); 2305 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 2306 /* Wait for reset to complete. */ 2307 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2308 if (sc->sc_dying) { 2309 err = USBD_IOERROR; 2310 goto ret; 2311 } 2312 v = xhci_op_read_4(sc, port); 2313 if (v & XHCI_PS_PR) { 2314 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 2315 usb_delay_ms(&sc->sc_bus, 10); 2316 /* XXX */ 2317 } 2318 break; 2319 case UHF_PORT_POWER: 2320 /* XXX power control */ 2321 break; 2322 /* XXX more */ 2323 case UHF_C_PORT_RESET: 2324 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 2325 break; 2326 default: 2327 err = USBD_IOERROR; 2328 goto ret; 2329 } 2330 break; 2331 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2332 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2333 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2334 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2335 break; 2336 default: 2337 err = USBD_IOERROR; 2338 goto ret; 2339 } 2340 xfer->actlen = totlen; 2341 err = USBD_NORMAL_COMPLETION; 2342 ret: 2343 xfer->status = err; 2344 mutex_enter(&sc->sc_lock); 2345 usb_transfer_complete(xfer); 2346 mutex_exit(&sc->sc_lock); 2347 return USBD_IN_PROGRESS; 2348 } 2349 2350 2351 static void 2352 xhci_root_ctrl_abort(usbd_xfer_handle xfer) 2353 { 2354 /* Nothing to do, all transfers are synchronous. */ 2355 } 2356 2357 2358 static void 2359 xhci_root_ctrl_close(usbd_pipe_handle pipe) 2360 { 2361 DPRINTF(("%s\n", __func__)); 2362 /* Nothing to do. */ 2363 } 2364 2365 static void 2366 xhci_root_ctrl_done(usbd_xfer_handle xfer) 2367 { 2368 xfer->hcpriv = NULL; 2369 } 2370 2371 /* root hub intrerrupt */ 2372 2373 static usbd_status 2374 xhci_root_intr_transfer(usbd_xfer_handle xfer) 2375 { 2376 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2377 usbd_status err; 2378 2379 /* Insert last in queue. */ 2380 mutex_enter(&sc->sc_lock); 2381 err = usb_insert_transfer(xfer); 2382 mutex_exit(&sc->sc_lock); 2383 if (err) 2384 return err; 2385 2386 /* Pipe isn't running, start first */ 2387 return (xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2388 } 2389 2390 static usbd_status 2391 xhci_root_intr_start(usbd_xfer_handle xfer) 2392 { 2393 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2394 2395 if (sc->sc_dying) 2396 return USBD_IOERROR; 2397 2398 mutex_enter(&sc->sc_lock); 2399 sc->sc_intrxfer = xfer; 2400 mutex_exit(&sc->sc_lock); 2401 2402 return USBD_IN_PROGRESS; 2403 } 2404 2405 static void 2406 xhci_root_intr_abort(usbd_xfer_handle xfer) 2407 { 2408 #ifdef DIAGNOSTIC 2409 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2410 #endif 2411 2412 KASSERT(mutex_owned(&sc->sc_lock)); 2413 if (xfer->pipe->intrxfer == xfer) { 2414 DPRINTF(("%s: remove\n", __func__)); 2415 xfer->pipe->intrxfer = NULL; 2416 } 2417 xfer->status = USBD_CANCELLED; 2418 usb_transfer_complete(xfer); 2419 } 2420 2421 static void 2422 xhci_root_intr_close(usbd_pipe_handle pipe) 2423 { 2424 struct xhci_softc * const sc = pipe->device->bus->hci_private; 2425 2426 KASSERT(mutex_owned(&sc->sc_lock)); 2427 2428 DPRINTF(("%s\n", __func__)); 2429 2430 sc->sc_intrxfer = NULL; 2431 } 2432 2433 static void 2434 xhci_root_intr_done(usbd_xfer_handle xfer) 2435 { 2436 xfer->hcpriv = NULL; 2437 } 2438 2439 /* -------------- */ 2440 /* device control */ 2441 2442 static usbd_status 2443 xhci_device_ctrl_transfer(usbd_xfer_handle xfer) 2444 { 2445 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2446 usbd_status err; 2447 2448 /* Insert last in queue. */ 2449 mutex_enter(&sc->sc_lock); 2450 err = usb_insert_transfer(xfer); 2451 mutex_exit(&sc->sc_lock); 2452 if (err) 2453 return (err); 2454 2455 /* Pipe isn't running, start first */ 2456 return (xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2457 } 2458 2459 static usbd_status 2460 xhci_device_ctrl_start(usbd_xfer_handle xfer) 2461 { 2462 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2463 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2464 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2465 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2466 struct xhci_xfer * const xx = (void *)xfer; 2467 usb_device_request_t * const req = &xfer->request; 2468 const bool isread = UT_GET_DIR(req->bmRequestType) == UT_READ; 2469 const uint32_t len = UGETW(req->wLength); 2470 usb_dma_t * const dma = &xfer->dmabuf; 2471 uint64_t parameter; 2472 uint32_t status; 2473 uint32_t control; 2474 u_int i; 2475 2476 DPRINTF(("%s\n", __func__)); 2477 DPRINTF(("req: %02x %02x %04x %04x %04x\n", req->bmRequestType, 2478 req->bRequest, UGETW(req->wValue), UGETW(req->wIndex), 2479 UGETW(req->wLength))); 2480 2481 /* XXX */ 2482 if (tr->is_halted) { 2483 xhci_reset_endpoint(xfer->pipe); 2484 tr->is_halted = false; 2485 xhci_set_dequeue(xfer->pipe); 2486 } 2487 2488 /* we rely on the bottom bits for extra info */ 2489 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 2490 2491 KASSERT((xfer->rqflags & URQ_REQUEST) != 0); 2492 2493 i = 0; 2494 2495 /* setup phase */ 2496 memcpy(¶meter, req, sizeof(*req)); 2497 parameter = le64toh(parameter); 2498 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 2499 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 2500 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 2501 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 2502 XHCI_TRB_3_IDT_BIT; 2503 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2504 2505 if (len == 0) 2506 goto no_data; 2507 2508 /* data phase */ 2509 parameter = DMAADDR(dma, 0); 2510 KASSERT(len <= 0x10000); 2511 status = XHCI_TRB_2_IRQ_SET(0) | 2512 XHCI_TRB_2_TDSZ_SET(1) | 2513 XHCI_TRB_2_BYTES_SET(len); 2514 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 2515 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 2516 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 2517 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2518 2519 parameter = (uintptr_t)xfer | 0x3; 2520 status = XHCI_TRB_2_IRQ_SET(0); 2521 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 2522 XHCI_TRB_3_IOC_BIT; 2523 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2524 2525 no_data: 2526 parameter = 0; 2527 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_TDSZ_SET(1); 2528 /* the status stage has inverted direction */ 2529 control = (isread ? 0 : XHCI_TRB_3_DIR_IN) | 2530 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 2531 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 2532 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2533 2534 parameter = (uintptr_t)xfer | 0x0; 2535 status = XHCI_TRB_2_IRQ_SET(0); 2536 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 2537 XHCI_TRB_3_IOC_BIT; 2538 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2539 2540 mutex_enter(&tr->xr_lock); 2541 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2542 mutex_exit(&tr->xr_lock); 2543 2544 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2545 2546 if (xfer->timeout && !sc->sc_bus.use_polling) { 2547 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 2548 xhci_timeout, xfer); 2549 } 2550 2551 if (sc->sc_bus.use_polling) { 2552 device_printf(sc->sc_dev, "%s polling\n", __func__); 2553 //xhci_waitintr(sc, xfer); 2554 } 2555 2556 return USBD_IN_PROGRESS; 2557 } 2558 2559 static void 2560 xhci_device_ctrl_done(usbd_xfer_handle xfer) 2561 { 2562 DPRINTF(("%s\n", __func__)); 2563 2564 callout_stop(&xfer->timeout_handle); /* XXX wrong place */ 2565 2566 } 2567 2568 static void 2569 xhci_device_ctrl_abort(usbd_xfer_handle xfer) 2570 { 2571 DPRINTF(("%s\n", __func__)); 2572 } 2573 2574 static void 2575 xhci_device_ctrl_close(usbd_pipe_handle pipe) 2576 { 2577 DPRINTF(("%s\n", __func__)); 2578 } 2579 2580 /* ----------------- */ 2581 /* device isochronus */ 2582 2583 /* ----------- */ 2584 /* device bulk */ 2585 2586 static usbd_status 2587 xhci_device_bulk_transfer(usbd_xfer_handle xfer) 2588 { 2589 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2590 usbd_status err; 2591 2592 /* Insert last in queue. */ 2593 mutex_enter(&sc->sc_lock); 2594 err = usb_insert_transfer(xfer); 2595 mutex_exit(&sc->sc_lock); 2596 if (err) 2597 return err; 2598 2599 /* 2600 * Pipe isn't running (otherwise err would be USBD_INPROG), 2601 * so start it first. 2602 */ 2603 return (xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2604 } 2605 2606 static usbd_status 2607 xhci_device_bulk_start(usbd_xfer_handle xfer) 2608 { 2609 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2610 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2611 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2612 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2613 struct xhci_xfer * const xx = (void *)xfer; 2614 const uint32_t len = xfer->length; 2615 usb_dma_t * const dma = &xfer->dmabuf; 2616 uint64_t parameter; 2617 uint32_t status; 2618 uint32_t control; 2619 u_int i = 0; 2620 2621 #if 0 2622 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2623 xs->xs_idx, dci); 2624 #endif 2625 2626 if (sc->sc_dying) 2627 return USBD_IOERROR; 2628 2629 KASSERT((xfer->rqflags & URQ_REQUEST) == 0); 2630 2631 parameter = DMAADDR(dma, 0); 2632 KASSERT(len <= 0x10000); 2633 status = XHCI_TRB_2_IRQ_SET(0) | 2634 XHCI_TRB_2_TDSZ_SET(1) | 2635 XHCI_TRB_2_BYTES_SET(len); 2636 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 2637 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 2638 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2639 2640 mutex_enter(&tr->xr_lock); 2641 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2642 mutex_exit(&tr->xr_lock); 2643 2644 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2645 2646 if (sc->sc_bus.use_polling) { 2647 device_printf(sc->sc_dev, "%s polling\n", __func__); 2648 //xhci_waitintr(sc, xfer); 2649 } 2650 2651 return USBD_IN_PROGRESS; 2652 } 2653 2654 static void 2655 xhci_device_bulk_done(usbd_xfer_handle xfer) 2656 { 2657 //struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2658 //struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2659 //const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2660 const u_int endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 2661 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2662 2663 DPRINTF(("%s\n", __func__)); 2664 2665 #if 0 2666 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2667 xs->xs_idx, dci); 2668 #endif 2669 2670 callout_stop(&xfer->timeout_handle); /* XXX wrong place */ 2671 2672 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 2673 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2674 2675 2676 } 2677 2678 static void 2679 xhci_device_bulk_abort(usbd_xfer_handle xfer) 2680 { 2681 DPRINTF(("%s\n", __func__)); 2682 } 2683 2684 static void 2685 xhci_device_bulk_close(usbd_pipe_handle pipe) 2686 { 2687 DPRINTF(("%s\n", __func__)); 2688 } 2689 2690 /* --------------- */ 2691 /* device intrrupt */ 2692 2693 static usbd_status 2694 xhci_device_intr_transfer(usbd_xfer_handle xfer) 2695 { 2696 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2697 usbd_status err; 2698 2699 /* Insert last in queue. */ 2700 mutex_enter(&sc->sc_lock); 2701 err = usb_insert_transfer(xfer); 2702 mutex_exit(&sc->sc_lock); 2703 if (err) 2704 return err; 2705 2706 /* 2707 * Pipe isn't running (otherwise err would be USBD_INPROG), 2708 * so start it first. 2709 */ 2710 return (xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2711 } 2712 2713 static usbd_status 2714 xhci_device_intr_start(usbd_xfer_handle xfer) 2715 { 2716 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2717 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2718 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2719 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 2720 struct xhci_xfer * const xx = (void *)xfer; 2721 const uint32_t len = xfer->length; 2722 usb_dma_t * const dma = &xfer->dmabuf; 2723 uint64_t parameter; 2724 uint32_t status; 2725 uint32_t control; 2726 u_int i = 0; 2727 2728 #if 0 2729 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2730 xs->xs_idx, dci); 2731 #endif 2732 2733 if (sc->sc_dying) 2734 return USBD_IOERROR; 2735 2736 KASSERT((xfer->rqflags & URQ_REQUEST) == 0); 2737 2738 parameter = DMAADDR(dma, 0); 2739 KASSERT(len <= 0x10000); 2740 status = XHCI_TRB_2_IRQ_SET(0) | 2741 XHCI_TRB_2_TDSZ_SET(1) | 2742 XHCI_TRB_2_BYTES_SET(len); 2743 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 2744 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 2745 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 2746 2747 mutex_enter(&tr->xr_lock); 2748 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 2749 mutex_exit(&tr->xr_lock); 2750 2751 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 2752 2753 if (sc->sc_bus.use_polling) { 2754 device_printf(sc->sc_dev, "%s polling\n", __func__); 2755 //xhci_waitintr(sc, xfer); 2756 } 2757 2758 return USBD_IN_PROGRESS; 2759 } 2760 2761 static void 2762 xhci_device_intr_done(usbd_xfer_handle xfer) 2763 { 2764 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2765 struct xhci_slot * const xs = xfer->pipe->device->hci_private; 2766 const u_int dci = xhci_ep_get_dci(xfer->pipe->endpoint->edesc); 2767 const u_int endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 2768 const bool isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2769 DPRINTF(("%s\n", __func__)); 2770 2771 device_printf(sc->sc_dev, "%s %p slot %u dci %u\n", __func__, xfer, 2772 xs->xs_idx, dci); 2773 2774 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 2775 2776 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 2777 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2778 2779 #if 0 2780 device_printf(sc->sc_dev, ""); 2781 for (size_t i = 0; i < xfer->length; i++) { 2782 printf(" %02x", ((uint8_t const *)xfer->buffer)[i]); 2783 } 2784 printf("\n"); 2785 #endif 2786 2787 if (xfer->pipe->repeat) { 2788 xfer->status = xhci_device_intr_start(xfer); 2789 } else { 2790 callout_stop(&xfer->timeout_handle); /* XXX */ 2791 } 2792 2793 } 2794 2795 static void 2796 xhci_device_intr_abort(usbd_xfer_handle xfer) 2797 { 2798 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2799 DPRINTF(("%s\n", __func__)); 2800 device_printf(sc->sc_dev, "%s %p\n", __func__, xfer); 2801 /* XXX */ 2802 if (xfer->pipe->intrxfer == xfer) { 2803 xfer->pipe->intrxfer = NULL; 2804 } 2805 xfer->status = USBD_CANCELLED; 2806 mutex_enter(&sc->sc_lock); 2807 usb_transfer_complete(xfer); 2808 mutex_exit(&sc->sc_lock); 2809 } 2810 2811 static void 2812 xhci_device_intr_close(usbd_pipe_handle pipe) 2813 { 2814 struct xhci_softc * const sc = pipe->device->bus->hci_private; 2815 DPRINTF(("%s\n", __func__)); 2816 device_printf(sc->sc_dev, "%s %p\n", __func__, pipe); 2817 xhci_unconfigure_endpoint(pipe); 2818 } 2819 2820 /* ------------ */ 2821 2822 static void 2823 xhci_timeout(void *addr) 2824 { 2825 struct xhci_xfer * const xx = addr; 2826 usbd_xfer_handle const xfer = &xx->xx_xfer; 2827 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2828 2829 if (sc->sc_dying) { 2830 return; 2831 } 2832 2833 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 2834 USB_TASKQ_MPSAFE); 2835 usb_add_task(xx->xx_xfer.pipe->device, &xx->xx_abort_task, 2836 USB_TASKQ_HC); 2837 } 2838 2839 static void 2840 xhci_timeout_task(void *addr) 2841 { 2842 usbd_xfer_handle const xfer = addr; 2843 struct xhci_softc * const sc = xfer->pipe->device->bus->hci_private; 2844 2845 mutex_enter(&sc->sc_lock); 2846 #if 0 2847 xhci_abort_xfer(xfer, USBD_TIMEOUT); 2848 #else 2849 xfer->status = USBD_TIMEOUT; 2850 usb_transfer_complete(xfer); 2851 #endif 2852 mutex_exit(&sc->sc_lock); 2853 } 2854
Indexes created Tue Sep 23 22:09:46 GMT 2025