xhci.c revision 1.42
1 /* $NetBSD: xhci.c,v 1.42 2016/05/06 10:24:06 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.42 2016/05/06 10:24:06 skrll Exp $"); 38 39 #include "opt_usb.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/kmem.h> 45 #include <sys/device.h> 46 #include <sys/select.h> 47 #include <sys/proc.h> 48 #include <sys/queue.h> 49 #include <sys/mutex.h> 50 #include <sys/condvar.h> 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/sysctl.h> 54 55 #include <machine/endian.h> 56 57 #include <dev/usb/usb.h> 58 #include <dev/usb/usbdi.h> 59 #include <dev/usb/usbdivar.h> 60 #include <dev/usb/usbdi_util.h> 61 #include <dev/usb/usbhist.h> 62 #include <dev/usb/usb_mem.h> 63 #include <dev/usb/usb_quirks.h> 64 65 #include <dev/usb/xhcireg.h> 66 #include <dev/usb/xhcivar.h> 67 #include <dev/usb/usbroothub.h> 68 69 70 #ifdef USB_DEBUG 71 #ifndef XHCI_DEBUG 72 #define xhcidebug 0 73 #else /* !XHCI_DEBUG */ 74 static int xhcidebug = 0; 75 76 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 77 { 78 int err; 79 const struct sysctlnode *rnode; 80 const struct sysctlnode *cnode; 81 82 err = sysctl_createv(clog, 0, NULL, &rnode, 83 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 84 SYSCTL_DESCR("xhci global controls"), 85 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 86 87 if (err) 88 goto fail; 89 90 /* control debugging printfs */ 91 err = sysctl_createv(clog, 0, &rnode, &cnode, 92 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 93 "debug", SYSCTL_DESCR("Enable debugging output"), 94 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 95 if (err) 96 goto fail; 97 98 return; 99 fail: 100 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 101 } 102 103 #endif /* !XHCI_DEBUG */ 104 #endif /* USB_DEBUG */ 105 106 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 107 #define XHCIHIST_FUNC() USBHIST_FUNC() 108 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 109 110 #define XHCI_DCI_SLOT 0 111 #define XHCI_DCI_EP_CONTROL 1 112 113 #define XHCI_ICI_INPUT_CONTROL 0 114 115 struct xhci_pipe { 116 struct usbd_pipe xp_pipe; 117 struct usb_task xp_async_task; 118 }; 119 120 #define XHCI_COMMAND_RING_TRBS 256 121 #define XHCI_EVENT_RING_TRBS 256 122 #define XHCI_EVENT_RING_SEGMENTS 1 123 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 124 125 static usbd_status xhci_open(struct usbd_pipe *); 126 static void xhci_close_pipe(struct usbd_pipe *); 127 static int xhci_intr1(struct xhci_softc * const); 128 static void xhci_softintr(void *); 129 static void xhci_poll(struct usbd_bus *); 130 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 131 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 132 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 133 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 134 struct usbd_port *); 135 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 136 void *, int); 137 138 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 139 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 140 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 141 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 142 143 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 144 145 static usbd_status xhci_do_command(struct xhci_softc * const, 146 struct xhci_trb * const, int); 147 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 148 struct xhci_trb * const, int); 149 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t, uint32_t, int); 150 static usbd_status xhci_enable_slot(struct xhci_softc * const, 151 uint8_t * const); 152 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 153 static usbd_status xhci_address_device(struct xhci_softc * const, 154 uint64_t, uint8_t, bool); 155 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 156 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 157 struct xhci_slot * const, u_int); 158 static usbd_status xhci_ring_init(struct xhci_softc * const, 159 struct xhci_ring * const, size_t, size_t); 160 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 161 162 static void xhci_noop(struct usbd_pipe *); 163 164 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 165 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 166 static void xhci_root_intr_abort(struct usbd_xfer *); 167 static void xhci_root_intr_close(struct usbd_pipe *); 168 static void xhci_root_intr_done(struct usbd_xfer *); 169 170 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 171 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 172 static void xhci_device_ctrl_abort(struct usbd_xfer *); 173 static void xhci_device_ctrl_close(struct usbd_pipe *); 174 static void xhci_device_ctrl_done(struct usbd_xfer *); 175 176 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 177 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 178 static void xhci_device_intr_abort(struct usbd_xfer *); 179 static void xhci_device_intr_close(struct usbd_pipe *); 180 static void xhci_device_intr_done(struct usbd_xfer *); 181 182 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 183 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 184 static void xhci_device_bulk_abort(struct usbd_xfer *); 185 static void xhci_device_bulk_close(struct usbd_pipe *); 186 static void xhci_device_bulk_done(struct usbd_xfer *); 187 188 static void xhci_timeout(void *); 189 static void xhci_timeout_task(void *); 190 191 static const struct usbd_bus_methods xhci_bus_methods = { 192 .ubm_open = xhci_open, 193 .ubm_softint = xhci_softintr, 194 .ubm_dopoll = xhci_poll, 195 .ubm_allocx = xhci_allocx, 196 .ubm_freex = xhci_freex, 197 .ubm_getlock = xhci_get_lock, 198 .ubm_newdev = xhci_new_device, 199 .ubm_rhctrl = xhci_roothub_ctrl, 200 }; 201 202 static const struct usbd_pipe_methods xhci_root_intr_methods = { 203 .upm_transfer = xhci_root_intr_transfer, 204 .upm_start = xhci_root_intr_start, 205 .upm_abort = xhci_root_intr_abort, 206 .upm_close = xhci_root_intr_close, 207 .upm_cleartoggle = xhci_noop, 208 .upm_done = xhci_root_intr_done, 209 }; 210 211 212 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 213 .upm_transfer = xhci_device_ctrl_transfer, 214 .upm_start = xhci_device_ctrl_start, 215 .upm_abort = xhci_device_ctrl_abort, 216 .upm_close = xhci_device_ctrl_close, 217 .upm_cleartoggle = xhci_noop, 218 .upm_done = xhci_device_ctrl_done, 219 }; 220 221 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 222 .upm_cleartoggle = xhci_noop, 223 }; 224 225 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 226 .upm_transfer = xhci_device_bulk_transfer, 227 .upm_start = xhci_device_bulk_start, 228 .upm_abort = xhci_device_bulk_abort, 229 .upm_close = xhci_device_bulk_close, 230 .upm_cleartoggle = xhci_noop, 231 .upm_done = xhci_device_bulk_done, 232 }; 233 234 static const struct usbd_pipe_methods xhci_device_intr_methods = { 235 .upm_transfer = xhci_device_intr_transfer, 236 .upm_start = xhci_device_intr_start, 237 .upm_abort = xhci_device_intr_abort, 238 .upm_close = xhci_device_intr_close, 239 .upm_cleartoggle = xhci_noop, 240 .upm_done = xhci_device_intr_done, 241 }; 242 243 static inline uint32_t 244 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 245 { 246 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 247 } 248 249 static inline uint32_t 250 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 251 { 252 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 253 } 254 255 static inline void 256 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 257 uint32_t value) 258 { 259 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 260 } 261 262 #if 0 /* unused */ 263 static inline void 264 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 265 uint32_t value) 266 { 267 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 268 } 269 #endif /* unused */ 270 271 static inline uint32_t 272 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 273 { 274 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 275 } 276 277 static inline uint32_t 278 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 279 { 280 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 281 } 282 283 static inline void 284 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 285 uint32_t value) 286 { 287 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 288 } 289 290 static inline uint64_t 291 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 292 { 293 uint64_t value; 294 295 if (sc->sc_ac64) { 296 #ifdef XHCI_USE_BUS_SPACE_8 297 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 298 #else 299 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 300 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 301 offset + 4) << 32; 302 #endif 303 } else { 304 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 305 } 306 307 return value; 308 } 309 310 static inline void 311 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 312 uint64_t value) 313 { 314 if (sc->sc_ac64) { 315 #ifdef XHCI_USE_BUS_SPACE_8 316 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 317 #else 318 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 319 (value >> 0) & 0xffffffff); 320 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 321 (value >> 32) & 0xffffffff); 322 #endif 323 } else { 324 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 325 } 326 } 327 328 static inline uint32_t 329 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 330 { 331 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 332 } 333 334 static inline void 335 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 336 uint32_t value) 337 { 338 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 339 } 340 341 #if 0 /* unused */ 342 static inline uint64_t 343 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 344 { 345 uint64_t value; 346 347 if (sc->sc_ac64) { 348 #ifdef XHCI_USE_BUS_SPACE_8 349 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 350 #else 351 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 352 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 353 offset + 4) << 32; 354 #endif 355 } else { 356 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 357 } 358 359 return value; 360 } 361 #endif /* unused */ 362 363 static inline void 364 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 365 uint64_t value) 366 { 367 if (sc->sc_ac64) { 368 #ifdef XHCI_USE_BUS_SPACE_8 369 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 370 #else 371 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 372 (value >> 0) & 0xffffffff); 373 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 374 (value >> 32) & 0xffffffff); 375 #endif 376 } else { 377 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 378 } 379 } 380 381 #if 0 /* unused */ 382 static inline uint32_t 383 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 384 { 385 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 386 } 387 #endif /* unused */ 388 389 static inline void 390 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 391 uint32_t value) 392 { 393 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 394 } 395 396 /* --- */ 397 398 static inline uint8_t 399 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 400 { 401 u_int eptype = 0; 402 403 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 404 case UE_CONTROL: 405 eptype = 0x0; 406 break; 407 case UE_ISOCHRONOUS: 408 eptype = 0x1; 409 break; 410 case UE_BULK: 411 eptype = 0x2; 412 break; 413 case UE_INTERRUPT: 414 eptype = 0x3; 415 break; 416 } 417 418 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 419 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 420 return eptype | 0x4; 421 else 422 return eptype; 423 } 424 425 static u_int 426 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 427 { 428 /* xHCI 1.0 section 4.5.1 */ 429 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 430 u_int in = 0; 431 432 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 433 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 434 in = 1; 435 436 return epaddr * 2 + in; 437 } 438 439 static inline u_int 440 xhci_dci_to_ici(const u_int i) 441 { 442 return i + 1; 443 } 444 445 static inline void * 446 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 447 const u_int dci) 448 { 449 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 450 } 451 452 #if 0 /* unused */ 453 static inline bus_addr_t 454 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 455 const u_int dci) 456 { 457 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 458 } 459 #endif /* unused */ 460 461 static inline void * 462 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 463 const u_int ici) 464 { 465 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 466 } 467 468 static inline bus_addr_t 469 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 470 const u_int ici) 471 { 472 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 473 } 474 475 static inline struct xhci_trb * 476 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 477 { 478 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 479 } 480 481 static inline bus_addr_t 482 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 483 { 484 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 485 } 486 487 static inline void 488 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 489 uint32_t control) 490 { 491 trb->trb_0 = htole64(parameter); 492 trb->trb_2 = htole32(status); 493 trb->trb_3 = htole32(control); 494 } 495 496 static int 497 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 498 { 499 /* base address of TRBs */ 500 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 501 502 /* trb_0 range sanity check */ 503 if (trb_0 == 0 || trb_0 < trbp || 504 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 505 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 506 return 1; 507 } 508 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 509 return 0; 510 } 511 512 /* --- */ 513 514 void 515 xhci_childdet(device_t self, device_t child) 516 { 517 struct xhci_softc * const sc = device_private(self); 518 519 KASSERT(sc->sc_child == child); 520 if (child == sc->sc_child) 521 sc->sc_child = NULL; 522 } 523 524 int 525 xhci_detach(struct xhci_softc *sc, int flags) 526 { 527 int rv = 0; 528 529 if (sc->sc_child != NULL) 530 rv = config_detach(sc->sc_child, flags); 531 532 if (rv != 0) 533 return rv; 534 535 /* XXX unconfigure/free slots */ 536 537 /* verify: */ 538 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 539 xhci_op_write_4(sc, XHCI_USBCMD, 0); 540 /* do we need to wait for stop? */ 541 542 xhci_op_write_8(sc, XHCI_CRCR, 0); 543 xhci_ring_free(sc, &sc->sc_cr); 544 cv_destroy(&sc->sc_command_cv); 545 546 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 547 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 548 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 549 xhci_ring_free(sc, &sc->sc_er); 550 551 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 552 553 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 554 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 555 556 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 557 558 mutex_destroy(&sc->sc_lock); 559 mutex_destroy(&sc->sc_intr_lock); 560 cv_destroy(&sc->sc_softwake_cv); 561 562 pool_cache_destroy(sc->sc_xferpool); 563 564 return rv; 565 } 566 567 int 568 xhci_activate(device_t self, enum devact act) 569 { 570 struct xhci_softc * const sc = device_private(self); 571 572 switch (act) { 573 case DVACT_DEACTIVATE: 574 sc->sc_dying = true; 575 return 0; 576 default: 577 return EOPNOTSUPP; 578 } 579 } 580 581 bool 582 xhci_suspend(device_t dv, const pmf_qual_t *qual) 583 { 584 return false; 585 } 586 587 bool 588 xhci_resume(device_t dv, const pmf_qual_t *qual) 589 { 590 return false; 591 } 592 593 bool 594 xhci_shutdown(device_t self, int flags) 595 { 596 return false; 597 } 598 599 static int 600 xhci_hc_reset(struct xhci_softc * const sc) 601 { 602 uint32_t usbcmd, usbsts; 603 int i; 604 605 /* Check controller not ready */ 606 for (i = 0; i < XHCI_WAIT_CNR; i++) { 607 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 608 if ((usbsts & XHCI_STS_CNR) == 0) 609 break; 610 usb_delay_ms(&sc->sc_bus, 1); 611 } 612 if (i >= XHCI_WAIT_CNR) { 613 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 614 return EIO; 615 } 616 617 /* Halt controller */ 618 usbcmd = 0; 619 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 620 usb_delay_ms(&sc->sc_bus, 1); 621 622 /* Reset controller */ 623 usbcmd = XHCI_CMD_HCRST; 624 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 625 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 626 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 627 if ((usbcmd & XHCI_CMD_HCRST) == 0) 628 break; 629 usb_delay_ms(&sc->sc_bus, 1); 630 } 631 if (i >= XHCI_WAIT_HCRST) { 632 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 633 return EIO; 634 } 635 636 /* Check controller not ready */ 637 for (i = 0; i < XHCI_WAIT_CNR; i++) { 638 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 639 if ((usbsts & XHCI_STS_CNR) == 0) 640 break; 641 usb_delay_ms(&sc->sc_bus, 1); 642 } 643 if (i >= XHCI_WAIT_CNR) { 644 aprint_error_dev(sc->sc_dev, 645 "controller not ready timeout after reset\n"); 646 return EIO; 647 } 648 649 return 0; 650 } 651 652 653 static void 654 hexdump(const char *msg, const void *base, size_t len) 655 { 656 #if 0 657 size_t cnt; 658 const uint32_t *p; 659 extern paddr_t vtophys(vaddr_t); 660 661 p = base; 662 cnt = 0; 663 664 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 665 (void *)vtophys((vaddr_t)base)); 666 667 while (cnt < len) { 668 if (cnt % 16 == 0) 669 printf("%p: ", p); 670 else if (cnt % 8 == 0) 671 printf(" |"); 672 printf(" %08x", *p++); 673 cnt += 4; 674 if (cnt % 16 == 0) 675 printf("\n"); 676 } 677 #endif 678 } 679 680 /* Process extended capabilities */ 681 static void 682 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 683 { 684 uint32_t ecp, ecr; 685 686 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 687 688 ecp = XHCI_HCC_XECP(hcc) * 4; 689 while (ecp != 0) { 690 ecr = xhci_read_4(sc, ecp); 691 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 692 switch (XHCI_XECP_ID(ecr)) { 693 case XHCI_ID_PROTOCOLS: { 694 uint32_t w4, w8, wc; 695 uint16_t w2; 696 w2 = (ecr >> 16) & 0xffff; 697 w4 = xhci_read_4(sc, ecp + 4); 698 w8 = xhci_read_4(sc, ecp + 8); 699 wc = xhci_read_4(sc, ecp + 0xc); 700 aprint_debug_dev(sc->sc_dev, 701 " SP: %08x %08x %08x %08x\n", ecr, w4, w8, wc); 702 /* unused */ 703 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0300) { 704 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 705 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 706 } 707 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0200) { 708 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 709 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 710 } 711 break; 712 } 713 case XHCI_ID_USB_LEGACY: { 714 uint8_t bios_sem; 715 716 /* Take host controller ownership from BIOS */ 717 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 718 if (bios_sem) { 719 /* sets xHCI to be owned by OS */ 720 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 721 aprint_debug_dev(sc->sc_dev, 722 "waiting for BIOS to give up control\n"); 723 for (int i = 0; i < 5000; i++) { 724 bios_sem = xhci_read_1(sc, ecp + 725 XHCI_XECP_BIOS_SEM); 726 if (bios_sem == 0) 727 break; 728 DELAY(1000); 729 } 730 if (bios_sem) { 731 aprint_error_dev(sc->sc_dev, 732 "timed out waiting for BIOS\n"); 733 } 734 } 735 break; 736 } 737 default: 738 break; 739 } 740 ecr = xhci_read_4(sc, ecp); 741 if (XHCI_XECP_NEXT(ecr) == 0) { 742 ecp = 0; 743 } else { 744 ecp += XHCI_XECP_NEXT(ecr) * 4; 745 } 746 } 747 } 748 749 #define XHCI_HCCPREV1_BITS \ 750 "\177\020" /* New bitmask */ \ 751 "f\020\020XECP\0" \ 752 "f\014\4MAXPSA\0" \ 753 "b\013CFC\0" \ 754 "b\012SEC\0" \ 755 "b\011SBD\0" \ 756 "b\010FSE\0" \ 757 "b\7NSS\0" \ 758 "b\6LTC\0" \ 759 "b\5LHRC\0" \ 760 "b\4PIND\0" \ 761 "b\3PPC\0" \ 762 "b\2CZC\0" \ 763 "b\1BNC\0" \ 764 "b\0AC64\0" \ 765 "\0" 766 #define XHCI_HCCV1_x_BITS \ 767 "\177\020" /* New bitmask */ \ 768 "f\020\020XECP\0" \ 769 "f\014\4MAXPSA\0" \ 770 "b\013CFC\0" \ 771 "b\012SEC\0" \ 772 "b\011SPC\0" \ 773 "b\010PAE\0" \ 774 "b\7NSS\0" \ 775 "b\6LTC\0" \ 776 "b\5LHRC\0" \ 777 "b\4PIND\0" \ 778 "b\3PPC\0" \ 779 "b\2CSZ\0" \ 780 "b\1BNC\0" \ 781 "b\0AC64\0" \ 782 "\0" 783 784 int 785 xhci_init(struct xhci_softc *sc) 786 { 787 bus_size_t bsz; 788 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 789 uint32_t pagesize, config; 790 int i = 0; 791 uint16_t hciversion; 792 uint8_t caplength; 793 794 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 795 796 sc->sc_bus.ub_revision = USBREV_3_0; 797 sc->sc_bus.ub_usedma = true; 798 799 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 800 caplength = XHCI_CAP_CAPLENGTH(cap); 801 hciversion = XHCI_CAP_HCIVERSION(cap); 802 803 if (hciversion < XHCI_HCIVERSION_0_96 || 804 hciversion > XHCI_HCIVERSION_1_0) { 805 aprint_normal_dev(sc->sc_dev, 806 "xHCI version %x.%x not known to be supported\n", 807 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 808 } else { 809 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 810 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 811 } 812 813 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 814 &sc->sc_cbh) != 0) { 815 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 816 return ENOMEM; 817 } 818 819 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 820 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 821 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 822 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 823 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 824 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 825 aprint_debug_dev(sc->sc_dev, 826 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 827 828 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 829 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 830 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 831 832 char sbuf[128]; 833 if (hciversion < XHCI_HCIVERSION_1_0) 834 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 835 else 836 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 837 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 838 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 839 840 /* print PSI and take ownership from BIOS */ 841 xhci_ecp(sc, hcc); 842 843 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 844 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 845 &sc->sc_obh) != 0) { 846 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 847 return ENOMEM; 848 } 849 850 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 851 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 852 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 853 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 854 return ENOMEM; 855 } 856 857 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 858 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 859 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 860 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 861 return ENOMEM; 862 } 863 864 int rv; 865 rv = xhci_hc_reset(sc); 866 if (rv != 0) { 867 return rv; 868 } 869 870 if (sc->sc_vendor_init) 871 sc->sc_vendor_init(sc); 872 873 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 874 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 875 pagesize = ffs(pagesize); 876 if (pagesize == 0) { 877 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 878 return EIO; 879 } 880 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 881 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 882 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 883 (uint32_t)sc->sc_maxslots); 884 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 885 886 usbd_status err; 887 888 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 889 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 890 if (sc->sc_maxspbuf != 0) { 891 err = usb_allocmem(&sc->sc_bus, 892 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 893 &sc->sc_spbufarray_dma); 894 if (err) { 895 aprint_error_dev(sc->sc_dev, 896 "spbufarray init fail, err %d\n", err); 897 return ENOMEM; 898 } 899 900 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 901 sc->sc_maxspbuf, KM_SLEEP); 902 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 903 for (i = 0; i < sc->sc_maxspbuf; i++) { 904 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 905 /* allocate contexts */ 906 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 907 sc->sc_pgsz, dma); 908 if (err) { 909 aprint_error_dev(sc->sc_dev, 910 "spbufarray_dma init fail, err %d\n", err); 911 rv = ENOMEM; 912 goto bad1; 913 } 914 spbufarray[i] = htole64(DMAADDR(dma, 0)); 915 usb_syncmem(dma, 0, sc->sc_pgsz, 916 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 917 } 918 919 usb_syncmem(&sc->sc_spbufarray_dma, 0, 920 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 921 } 922 923 config = xhci_op_read_4(sc, XHCI_CONFIG); 924 config &= ~0xFF; 925 config |= sc->sc_maxslots & 0xFF; 926 xhci_op_write_4(sc, XHCI_CONFIG, config); 927 928 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 929 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 930 if (err) { 931 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 932 err); 933 rv = ENOMEM; 934 goto bad1; 935 } 936 937 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 938 XHCI_EVENT_RING_SEGMENTS_ALIGN); 939 if (err) { 940 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 941 err); 942 rv = ENOMEM; 943 goto bad2; 944 } 945 946 usb_dma_t *dma; 947 size_t size; 948 size_t align; 949 950 dma = &sc->sc_eventst_dma; 951 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 952 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 953 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 954 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 955 err = usb_allocmem(&sc->sc_bus, size, align, dma); 956 if (err) { 957 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 958 err); 959 rv = ENOMEM; 960 goto bad3; 961 } 962 963 memset(KERNADDR(dma, 0), 0, size); 964 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 965 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 966 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 967 KERNADDR(&sc->sc_eventst_dma, 0), 968 sc->sc_eventst_dma.udma_block->size); 969 970 dma = &sc->sc_dcbaa_dma; 971 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 972 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 973 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 974 err = usb_allocmem(&sc->sc_bus, size, align, dma); 975 if (err) { 976 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 977 rv = ENOMEM; 978 goto bad4; 979 } 980 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 981 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 982 KERNADDR(&sc->sc_dcbaa_dma, 0), 983 sc->sc_dcbaa_dma.udma_block->size); 984 985 memset(KERNADDR(dma, 0), 0, size); 986 if (sc->sc_maxspbuf != 0) { 987 /* 988 * DCBA entry 0 hold the scratchbuf array pointer. 989 */ 990 *(uint64_t *)KERNADDR(dma, 0) = 991 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 992 } 993 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 994 995 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 996 KM_SLEEP); 997 if (sc->sc_slots == NULL) { 998 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 999 rv = ENOMEM; 1000 goto bad; 1001 } 1002 1003 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1004 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1005 if (sc->sc_xferpool == NULL) { 1006 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1007 err); 1008 rv = ENOMEM; 1009 goto bad; 1010 } 1011 1012 cv_init(&sc->sc_command_cv, "xhcicmd"); 1013 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1014 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1015 cv_init(&sc->sc_softwake_cv, "xhciab"); 1016 1017 /* Set up the bus struct. */ 1018 sc->sc_bus.ub_methods = &xhci_bus_methods; 1019 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 1020 1021 struct xhci_erste *erst; 1022 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1023 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1024 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 1025 erst[0].erste_3 = htole32(0); 1026 usb_syncmem(&sc->sc_eventst_dma, 0, 1027 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1028 1029 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1030 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1031 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1032 XHCI_ERDP_LO_BUSY); 1033 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1034 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1035 sc->sc_cr.xr_cs); 1036 1037 #if 0 1038 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1039 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1040 #endif 1041 1042 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1043 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1044 /* Intel xhci needs interrupt rate moderated. */ 1045 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1046 else 1047 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1048 aprint_debug_dev(sc->sc_dev, "setting IMOD %u\n", 1049 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1050 1051 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 1052 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1053 xhci_op_read_4(sc, XHCI_USBCMD)); 1054 1055 return 0; 1056 1057 bad: 1058 if (sc->sc_xferpool) { 1059 pool_cache_destroy(sc->sc_xferpool); 1060 sc->sc_xferpool = NULL; 1061 } 1062 1063 if (sc->sc_slots) { 1064 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1065 sc->sc_maxslots); 1066 sc->sc_slots = NULL; 1067 } 1068 1069 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1070 bad4: 1071 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1072 bad3: 1073 xhci_ring_free(sc, &sc->sc_er); 1074 bad2: 1075 xhci_ring_free(sc, &sc->sc_cr); 1076 i = sc->sc_maxspbuf; 1077 bad1: 1078 for (int j = 0; j < i; j++) 1079 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1080 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1081 1082 return rv; 1083 } 1084 1085 int 1086 xhci_intr(void *v) 1087 { 1088 struct xhci_softc * const sc = v; 1089 int ret = 0; 1090 1091 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1092 1093 if (sc == NULL) 1094 return 0; 1095 1096 mutex_spin_enter(&sc->sc_intr_lock); 1097 1098 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1099 goto done; 1100 1101 /* If we get an interrupt while polling, then just ignore it. */ 1102 if (sc->sc_bus.ub_usepolling) { 1103 #ifdef DIAGNOSTIC 1104 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1105 #endif 1106 goto done; 1107 } 1108 1109 ret = xhci_intr1(sc); 1110 done: 1111 mutex_spin_exit(&sc->sc_intr_lock); 1112 return ret; 1113 } 1114 1115 int 1116 xhci_intr1(struct xhci_softc * const sc) 1117 { 1118 uint32_t usbsts; 1119 uint32_t iman; 1120 1121 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1122 1123 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1124 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1125 #if 0 1126 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1127 return 0; 1128 } 1129 #endif 1130 xhci_op_write_4(sc, XHCI_USBSTS, 1131 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1132 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1133 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1134 1135 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1136 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1137 iman |= XHCI_IMAN_INTR_PEND; 1138 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1139 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1140 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1141 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1142 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1143 1144 usb_schedsoftintr(&sc->sc_bus); 1145 1146 return 1; 1147 } 1148 1149 /* 1150 * 3 port speed types used in USB stack 1151 * 1152 * usbdi speed 1153 * definition: USB_SPEED_* in usb.h 1154 * They are used in struct usbd_device in USB stack. 1155 * ioctl interface uses these values too. 1156 * port_status speed 1157 * definition: UPS_*_SPEED in usb.h 1158 * They are used in usb_port_status_t and valid only for USB 2.0. 1159 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1160 * of usb_port_status_ext_t indicates port speed. 1161 * Note that some 3.0 values overlap with 2.0 values. 1162 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1163 * means UPS_LOW_SPEED in HS.) 1164 * port status returned from hub also uses these values. 1165 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1166 * or more. 1167 * xspeed: 1168 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1169 * They are used in only slot context and PORTSC reg of xhci. 1170 * The difference between usbdi speed and xspeed is 1171 * that FS and LS values are swapped. 1172 */ 1173 1174 /* convert usbdi speed to xspeed */ 1175 static int 1176 xhci_speed2xspeed(int speed) 1177 { 1178 switch (speed) { 1179 case USB_SPEED_LOW: return 2; 1180 case USB_SPEED_FULL: return 1; 1181 default: return speed; 1182 } 1183 } 1184 1185 #if 0 1186 /* convert xspeed to usbdi speed */ 1187 static int 1188 xhci_xspeed2speed(int xspeed) 1189 { 1190 switch (xspeed) { 1191 case 1: return USB_SPEED_FULL; 1192 case 2: return USB_SPEED_LOW; 1193 default: return xspeed; 1194 } 1195 } 1196 #endif 1197 1198 /* convert xspeed to port status speed */ 1199 static int 1200 xhci_xspeed2psspeed(int xspeed) 1201 { 1202 switch (xspeed) { 1203 case 0: return 0; 1204 case 1: return UPS_FULL_SPEED; 1205 case 2: return UPS_LOW_SPEED; 1206 case 3: return UPS_HIGH_SPEED; 1207 default: return UPS_OTHER_SPEED; 1208 } 1209 } 1210 1211 /* construct slot context */ 1212 static void 1213 xhci_setup_sctx(struct usbd_device *dev, uint32_t *cp) 1214 { 1215 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 1216 int speed = dev->ud_speed; 1217 int tthubslot, ttportnum; 1218 bool ishub; 1219 bool usemtt; 1220 1221 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1222 1223 /* 1224 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 1225 * tthubslot: 1226 * This is the slot ID of parent HS hub 1227 * if LS/FS device is connected && connected through HS hub. 1228 * This is 0 if device is not LS/FS device || 1229 * parent hub is not HS hub || 1230 * attached to root hub. 1231 * ttportnum: 1232 * This is the downstream facing port of parent HS hub 1233 * if LS/FS device is connected. 1234 * This is 0 if device is not LS/FS device || 1235 * parent hub is not HS hub || 1236 * attached to root hub. 1237 */ 1238 if (dev->ud_myhsport != NULL && 1239 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1240 (dev->ud_myhub != NULL && 1241 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1242 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 1243 ttportnum = dev->ud_myhsport->up_portno; 1244 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 1245 } else { 1246 ttportnum = 0; 1247 tthubslot = 0; 1248 } 1249 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 1250 dev->ud_myhsport, ttportnum, tthubslot, 0); 1251 1252 /* ishub is valid after reading UDESC_DEVICE */ 1253 ishub = (dd->bDeviceClass == UDCLASS_HUB); 1254 1255 /* dev->ud_hub is valid after reading UDESC_HUB */ 1256 if (ishub && dev->ud_hub) { 1257 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 1258 1259 cp[1] |= htole32(XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts)); 1260 cp[2] |= htole32(XHCI_SCTX_2_TT_THINK_TIME_SET( 1261 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK))); 1262 DPRINTFN(4, "nports=%d ttt=%d", 1263 hd->bNbrPorts, XHCI_SCTX_2_TT_THINK_TIME_GET(cp[2]), 0, 0); 1264 } 1265 1266 #define IS_TTHUB(dd) \ 1267 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 1268 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 1269 1270 /* 1271 * MTT flag is set if 1272 * 1. this is HS hub && MTT is enabled 1273 * or 1274 * 2. this is not hub && this is LS or FS device && 1275 * MTT of parent HS hub (and its parent, too) is enabled 1276 */ 1277 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 1278 usemtt = true; 1279 else if (!ishub && 1280 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 1281 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1282 (dev->ud_myhub != NULL && 1283 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1284 dev->ud_myhsport != NULL && 1285 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 1286 usemtt = true; 1287 else 1288 usemtt = false; 1289 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 1290 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 1291 1292 cp[0] |= htole32( 1293 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)) | 1294 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 1295 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0) 1296 ); 1297 cp[1] |= htole32(0); 1298 cp[2] |= htole32( 1299 XHCI_SCTX_2_IRQ_TARGET_SET(0) | 1300 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 1301 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum) 1302 ); 1303 cp[3] |= htole32(0); 1304 } 1305 1306 static uint32_t 1307 xhci_get_maxburst(struct usbd_pipe *pipe) 1308 { 1309 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1310 usbd_desc_iter_t iter; 1311 const usb_cdc_descriptor_t *cdcd; 1312 const usb_endpoint_ss_comp_descriptor_t * esscd = NULL; 1313 uint32_t maxb = 0; 1314 uint8_t ep; 1315 1316 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc( 1317 pipe->up_dev, UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 1318 usb_desc_iter_init(pipe->up_dev, &iter); 1319 iter.cur = (const void *)cdcd; 1320 1321 /* find endpoint_ss_comp desc for ep of this pipe */ 1322 for (ep = 0;;) { 1323 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 1324 if (cdcd == NULL) 1325 break; 1326 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 1327 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 1328 bEndpointAddress; 1329 if (UE_GET_ADDR(ep) == 1330 UE_GET_ADDR(ed->bEndpointAddress)) { 1331 cdcd = (const usb_cdc_descriptor_t *) 1332 usb_desc_iter_next(&iter); 1333 break; 1334 } 1335 ep = 0; 1336 } 1337 } 1338 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 1339 esscd = (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 1340 maxb = esscd->bMaxBurst; 1341 } 1342 1343 return maxb; 1344 } 1345 1346 /* 1347 * Convert endpoint bInterval value to endpoint context interval value 1348 * for Interrupt pipe. 1349 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 1350 */ 1351 static uint32_t 1352 xhci_bival2ival(uint32_t ival, int speed) 1353 { 1354 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 1355 int i; 1356 1357 /* 1358 * round ival down to "the nearest base 2 multiple of 1359 * bInterval * 8". 1360 * bInterval is at most 255 as its type is uByte. 1361 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 1362 */ 1363 for (i = 10; i > 0; i--) { 1364 if ((ival * 8) >= (1 << i)) 1365 break; 1366 } 1367 ival = i; 1368 } else { 1369 /* Interval = bInterval-1 for SS/HS */ 1370 ival--; 1371 } 1372 1373 return ival; 1374 } 1375 1376 /* 1377 * 4.8.2, 6.2.3.2 1378 * construct common endpoint parameters 1379 */ 1380 static void 1381 xhci_setup_endp_ctx(struct usbd_pipe *pipe, uint32_t *cp) 1382 { 1383 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1384 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1385 const u_int dci = xhci_ep_get_dci(ed); 1386 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1387 uint32_t mps = UGETW(ed->wMaxPacketSize); 1388 uint32_t maxb = 0; 1389 int speed = pipe->up_dev->ud_speed; 1390 uint32_t ival = ed->bInterval; 1391 1392 cp[0] = htole32( 1393 XHCI_EPCTX_0_EPSTATE_SET(0) | 1394 XHCI_EPCTX_0_MULT_SET(0) | /* always 0 except SS iscoh */ 1395 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 1396 XHCI_EPCTX_0_LSA_SET(0) | 1397 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0) 1398 ); 1399 cp[1] = htole32( 1400 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 1401 XHCI_EPCTX_1_HID_SET(0) | 1402 XHCI_EPCTX_1_MAXB_SET(0) 1403 ); 1404 if (xfertype != UE_ISOCHRONOUS) 1405 cp[1] |= htole32(XHCI_EPCTX_1_CERR_SET(3)); 1406 1407 /* 6.2.3.4, 4.8.2.4 */ 1408 if (USB_IS_SS(speed)) { 1409 /* UBS 3.1 9.6.6 */ 1410 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1411 /* UBS 3.1 9.6.7 */ 1412 maxb = xhci_get_maxburst(pipe); 1413 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1414 } else { 1415 /* UBS 2.0 9.6.6 */ 1416 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps))); 1417 1418 /* 6.2.3.4 */ 1419 if (speed == USB_SPEED_HIGH && 1420 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 1421 maxb = UE_GET_TRANS(mps); 1422 } else { 1423 /* LS/FS or HS CTRL or HS BULK */ 1424 maxb = 0; 1425 } 1426 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1427 } 1428 1429 if (xfertype == UE_CONTROL) 1430 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(8)); /* 6.2.3 */ 1431 else if (USB_IS_SS(speed)) 1432 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps)); 1433 else 1434 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps))); 1435 1436 switch (xfertype) { 1437 case UE_CONTROL: 1438 break; 1439 case UE_BULK: 1440 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 1441 break; 1442 case UE_INTERRUPT: 1443 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1444 ival = pipe->up_interval; 1445 1446 ival = xhci_bival2ival(ival, speed); 1447 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1448 break; 1449 case UE_ISOCHRONOUS: 1450 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1451 ival = pipe->up_interval; 1452 1453 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 1454 if (speed == USB_SPEED_FULL) 1455 ival += 3; /* 1ms -> 125us */ 1456 ival--; 1457 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1458 1459 if (USB_IS_SS(speed)) { 1460 /* XXX if LEC = 1, set ESIT instead */ 1461 cp[0] |= htole32(XHCI_EPCTX_0_MULT_SET(0)); 1462 } 1463 break; 1464 default: 1465 break; 1466 } 1467 *(uint64_t *)(&cp[2]) = htole64( 1468 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 1469 XHCI_EPCTX_2_DCS_SET(1)); 1470 } 1471 1472 /* 1473 * Construct input contexts and issue TRB 1474 */ 1475 static usbd_status 1476 xhci_configure_endpoint(struct usbd_pipe *pipe) 1477 { 1478 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1479 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1480 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1481 struct xhci_trb trb; 1482 usbd_status err; 1483 uint32_t *cp; 1484 1485 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1486 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1487 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1488 pipe->up_endpoint->ue_edesc->bmAttributes); 1489 1490 /* XXX ensure input context is available? */ 1491 1492 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1493 1494 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1495 cp[0] = htole32(0); 1496 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 1497 1498 /* set up input slot context */ 1499 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1500 xhci_setup_sctx(pipe->up_dev, cp); 1501 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1502 1503 /* set up input endpoint context */ 1504 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 1505 xhci_setup_endp_ctx(pipe, cp); 1506 1507 /* sync input contexts before they are read from memory */ 1508 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1509 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1510 sc->sc_ctxsz * 1); 1511 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1512 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1513 1514 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1515 trb.trb_2 = 0; 1516 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1517 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1518 1519 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1520 1521 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1522 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1523 sc->sc_ctxsz * 1); 1524 1525 return err; 1526 } 1527 1528 #if 0 1529 static usbd_status 1530 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1531 { 1532 #ifdef USB_DEBUG 1533 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1534 #endif 1535 1536 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1537 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1538 1539 return USBD_NORMAL_COMPLETION; 1540 } 1541 #endif 1542 1543 /* 4.6.8, 6.4.3.7 */ 1544 static usbd_status 1545 xhci_reset_endpoint(struct usbd_pipe *pipe) 1546 { 1547 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1548 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1549 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1550 struct xhci_trb trb; 1551 usbd_status err; 1552 1553 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1554 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1555 1556 KASSERT(!mutex_owned(&sc->sc_lock)); 1557 1558 trb.trb_0 = 0; 1559 trb.trb_2 = 0; 1560 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1561 XHCI_TRB_3_EP_SET(dci) | 1562 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1563 1564 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1565 1566 return err; 1567 } 1568 1569 /* 1570 * 4.6.9, 6.4.3.8 1571 * Stop execution of TDs on xfer ring. 1572 * Should be called with sc_lock held. 1573 */ 1574 static usbd_status 1575 xhci_stop_endpoint(struct usbd_pipe *pipe) 1576 { 1577 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1578 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1579 struct xhci_trb trb; 1580 usbd_status err; 1581 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1582 1583 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1584 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1585 1586 KASSERT(mutex_owned(&sc->sc_lock)); 1587 1588 trb.trb_0 = 0; 1589 trb.trb_2 = 0; 1590 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1591 XHCI_TRB_3_EP_SET(dci) | 1592 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1593 1594 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1595 1596 return err; 1597 } 1598 1599 /* 1600 * Set TR Dequeue Pointer. 1601 * xCHI 1.1 4.6.10 6.4.3.9 1602 * Purge all of the transfer requests on ring. 1603 * EPSTATE of endpoint must be ERROR or STOPPED, or CONTEXT_STATE error. 1604 */ 1605 static usbd_status 1606 xhci_set_dequeue(struct usbd_pipe *pipe) 1607 { 1608 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1609 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1610 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1611 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1612 struct xhci_trb trb; 1613 usbd_status err; 1614 1615 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1616 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1617 1618 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1619 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1620 BUS_DMASYNC_PREWRITE); 1621 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1622 1623 xr->xr_ep = 0; 1624 xr->xr_cs = 1; 1625 1626 /* set DCS */ 1627 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1628 trb.trb_2 = 0; 1629 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1630 XHCI_TRB_3_EP_SET(dci) | 1631 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1632 1633 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1634 1635 return err; 1636 } 1637 1638 /* 1639 * Open new pipe: called from usbd_setup_pipe_flags. 1640 * Fills methods of pipe. 1641 * If pipe is not for ep0, calls configure_endpoint. 1642 */ 1643 static usbd_status 1644 xhci_open(struct usbd_pipe *pipe) 1645 { 1646 struct usbd_device * const dev = pipe->up_dev; 1647 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1648 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1649 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1650 1651 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1652 DPRINTFN(1, "addr %d depth %d port %d speed %d", 1653 dev->ud_addr, dev->ud_depth, dev->ud_powersrc->up_portno, 1654 dev->ud_speed); 1655 1656 if (sc->sc_dying) 1657 return USBD_IOERROR; 1658 1659 /* Root Hub */ 1660 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1661 switch (ed->bEndpointAddress) { 1662 case USB_CONTROL_ENDPOINT: 1663 pipe->up_methods = &roothub_ctrl_methods; 1664 break; 1665 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1666 pipe->up_methods = &xhci_root_intr_methods; 1667 break; 1668 default: 1669 pipe->up_methods = NULL; 1670 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1671 ed->bEndpointAddress, 0, 0, 0); 1672 return USBD_INVAL; 1673 } 1674 return USBD_NORMAL_COMPLETION; 1675 } 1676 1677 switch (xfertype) { 1678 case UE_CONTROL: 1679 pipe->up_methods = &xhci_device_ctrl_methods; 1680 break; 1681 case UE_ISOCHRONOUS: 1682 pipe->up_methods = &xhci_device_isoc_methods; 1683 return USBD_INVAL; 1684 break; 1685 case UE_BULK: 1686 pipe->up_methods = &xhci_device_bulk_methods; 1687 break; 1688 case UE_INTERRUPT: 1689 pipe->up_methods = &xhci_device_intr_methods; 1690 break; 1691 default: 1692 return USBD_IOERROR; 1693 break; 1694 } 1695 1696 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1697 return xhci_configure_endpoint(pipe); 1698 1699 return USBD_NORMAL_COMPLETION; 1700 } 1701 1702 /* 1703 * Closes pipe, called from usbd_kill_pipe via close methods. 1704 * If the endpoint to be closed is ep0, disable_slot. 1705 * Should be called with sc_lock held. 1706 */ 1707 static void 1708 xhci_close_pipe(struct usbd_pipe *pipe) 1709 { 1710 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1711 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1712 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1713 const u_int dci = xhci_ep_get_dci(ed); 1714 struct xhci_trb trb; 1715 uint32_t *cp; 1716 1717 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1718 1719 if (sc->sc_dying) 1720 return; 1721 1722 /* xs is uninitialized before xhci_init_slot */ 1723 if (xs == NULL || xs->xs_idx == 0) 1724 return; 1725 1726 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1727 1728 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1729 KASSERT(mutex_owned(&sc->sc_lock)); 1730 1731 if (pipe->up_dev->ud_depth == 0) 1732 return; 1733 1734 if (dci == XHCI_DCI_EP_CONTROL) { 1735 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1736 xhci_disable_slot(sc, xs->xs_idx); 1737 return; 1738 } 1739 1740 /* 1741 * This may fail in the case that xhci_close_pipe is called after 1742 * xhci_abort_xfer e.g. usbd_kill_pipe. 1743 */ 1744 (void)xhci_stop_endpoint(pipe); 1745 1746 /* 1747 * set appropriate bit to be dropped. 1748 * don't set DC bit to 1, otherwise all endpoints 1749 * would be deconfigured. 1750 */ 1751 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1752 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1753 cp[1] = htole32(0); 1754 1755 /* XXX should be most significant one, not dci? */ 1756 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1757 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1758 1759 /* sync input contexts before they are read from memory */ 1760 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1761 1762 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1763 trb.trb_2 = 0; 1764 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1765 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1766 1767 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1768 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1769 } 1770 1771 /* 1772 * Abort transfer. 1773 * Called with sc_lock held. 1774 * May be called from softintr context. 1775 */ 1776 static void 1777 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1778 { 1779 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1780 1781 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1782 DPRINTFN(4, "xfer %p pipe %p status %d", 1783 xfer, xfer->ux_pipe, status, 0); 1784 1785 KASSERT(mutex_owned(&sc->sc_lock)); 1786 1787 if (sc->sc_dying) { 1788 /* If we're dying, just do the software part. */ 1789 DPRINTFN(4, "dying", 0, 0, 0, 0); 1790 xfer->ux_status = status; /* make software ignore it */ 1791 callout_stop(&xfer->ux_callout); 1792 usb_transfer_complete(xfer); 1793 return; 1794 } 1795 1796 /* XXX need more stuff */ 1797 xfer->ux_status = status; 1798 callout_stop(&xfer->ux_callout); 1799 usb_transfer_complete(xfer); 1800 DPRINTFN(14, "end", 0, 0, 0, 0); 1801 1802 KASSERT(mutex_owned(&sc->sc_lock)); 1803 } 1804 1805 /* 1806 * Recover STALLed endpoint. 1807 * xHCI 1.1 sect 4.10.2.1 1808 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1809 * all transfers on transfer ring. 1810 * These are done in thread context asynchronously. 1811 */ 1812 static void 1813 xhci_clear_endpoint_stall_async_task(void *cookie) 1814 { 1815 struct usbd_xfer * const xfer = cookie; 1816 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1817 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1818 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1819 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1820 1821 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1822 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1823 1824 xhci_reset_endpoint(xfer->ux_pipe); 1825 xhci_set_dequeue(xfer->ux_pipe); 1826 1827 mutex_enter(&sc->sc_lock); 1828 tr->is_halted = false; 1829 usb_transfer_complete(xfer); 1830 mutex_exit(&sc->sc_lock); 1831 DPRINTFN(4, "ends", 0, 0, 0, 0); 1832 } 1833 1834 static usbd_status 1835 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1836 { 1837 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1838 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1839 1840 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1841 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1842 1843 if (sc->sc_dying) { 1844 return USBD_IOERROR; 1845 } 1846 1847 usb_init_task(&xp->xp_async_task, 1848 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1849 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1850 DPRINTFN(4, "ends", 0, 0, 0, 0); 1851 1852 return USBD_NORMAL_COMPLETION; 1853 } 1854 1855 /* Process roothub port status/change events and notify to uhub_intr. */ 1856 static void 1857 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1858 { 1859 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1860 uint8_t *p; 1861 1862 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1863 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1864 port, 0, 0); 1865 1866 if (xfer == NULL) 1867 return; 1868 1869 if (port > sc->sc_maxports) 1870 return; 1871 1872 p = xfer->ux_buf; 1873 memset(p, 0, xfer->ux_length); 1874 p[port/NBBY] |= 1 << (port%NBBY); 1875 xfer->ux_actlen = xfer->ux_length; 1876 xfer->ux_status = USBD_NORMAL_COMPLETION; 1877 usb_transfer_complete(xfer); 1878 } 1879 1880 /* Process Transfer Events */ 1881 static void 1882 xhci_event_transfer(struct xhci_softc * const sc, 1883 const struct xhci_trb * const trb) 1884 { 1885 uint64_t trb_0; 1886 uint32_t trb_2, trb_3; 1887 uint8_t trbcode; 1888 u_int slot, dci; 1889 struct xhci_slot *xs; 1890 struct xhci_ring *xr; 1891 struct xhci_xfer *xx; 1892 struct usbd_xfer *xfer; 1893 usbd_status err; 1894 1895 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1896 1897 trb_0 = le64toh(trb->trb_0); 1898 trb_2 = le32toh(trb->trb_2); 1899 trb_3 = le32toh(trb->trb_3); 1900 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1901 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1902 dci = XHCI_TRB_3_EP_GET(trb_3); 1903 xs = &sc->sc_slots[slot]; 1904 xr = &xs->xs_ep[dci].xe_tr; 1905 1906 /* sanity check */ 1907 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1908 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1909 1910 int idx = 0; 1911 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1912 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1913 DPRINTFN(0, "invalid trb_0 0x%"PRIx64, trb_0, 0, 0, 0); 1914 return; 1915 } 1916 xx = xr->xr_cookies[idx]; 1917 1918 /* 1919 * If endpoint is stopped between TDs, TRB pointer points at 1920 * next TRB, however, it is not put yet or is a garbage TRB. 1921 * That's why xr_cookies may be NULL or look like broken. 1922 * Note: this ev happens only when hciversion >= 1.0 or 1923 * hciversion == 0.96 and FSE of hcc1 is set. 1924 */ 1925 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1926 DPRINTFN(1, "xx NULL: #%u: cookie %p: code %u trb_0 %" 1927 PRIx64, idx, xx, trbcode, trb_0); 1928 } 1929 } else { 1930 /* When ED != 0, trb_0 is kaddr of struct xhci_xfer. */ 1931 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1932 } 1933 /* XXX this may not happen */ 1934 if (xx == NULL) { 1935 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1936 return; 1937 } 1938 xfer = &xx->xx_xfer; 1939 /* XXX this may happen when detaching */ 1940 if (xfer == NULL) { 1941 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1942 xx, trb_0, 0, 0); 1943 return; 1944 } 1945 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1946 /* XXX I dunno why this happens */ 1947 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1948 1949 if (!xfer->ux_pipe->up_repeat && 1950 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1951 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1952 return; 1953 } 1954 1955 /* 4.11.5.2 Event Data TRB */ 1956 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1957 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1958 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1959 if ((trb_0 & 0x3) == 0x3) { 1960 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1961 } 1962 } 1963 1964 switch (trbcode) { 1965 case XHCI_TRB_ERROR_SHORT_PKT: 1966 case XHCI_TRB_ERROR_SUCCESS: 1967 xfer->ux_actlen = 1968 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1969 err = USBD_NORMAL_COMPLETION; 1970 break; 1971 case XHCI_TRB_ERROR_STALL: 1972 case XHCI_TRB_ERROR_BABBLE: 1973 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1974 xr->is_halted = true; 1975 err = USBD_STALLED; 1976 /* 1977 * Stalled endpoints can be recoverd by issuing 1978 * command TRB TYPE_RESET_EP on xHCI instead of 1979 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1980 * on the endpoint. However, this function may be 1981 * called from softint context (e.g. from umass), 1982 * in that case driver gets KASSERT in cv_timedwait 1983 * in xhci_do_command. 1984 * To avoid this, this runs reset_endpoint and 1985 * usb_transfer_complete in usb task thread 1986 * asynchronously (and then umass issues clear 1987 * UF_ENDPOINT_HALT). 1988 */ 1989 xfer->ux_status = err; 1990 xhci_clear_endpoint_stall_async(xfer); 1991 return; 1992 default: 1993 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1994 err = USBD_IOERROR; 1995 break; 1996 } 1997 xfer->ux_status = err; 1998 1999 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 2000 if ((trb_0 & 0x3) == 0x0) { 2001 callout_stop(&xfer->ux_callout); 2002 usb_transfer_complete(xfer); 2003 } 2004 } else { 2005 callout_stop(&xfer->ux_callout); 2006 usb_transfer_complete(xfer); 2007 } 2008 } 2009 2010 /* Process Command complete events */ 2011 static void 2012 xhci_event_cmd(struct xhci_softc * const sc, 2013 const struct xhci_trb * const trb) 2014 { 2015 uint64_t trb_0; 2016 uint32_t trb_2, trb_3; 2017 2018 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2019 2020 trb_0 = le64toh(trb->trb_0); 2021 trb_2 = le32toh(trb->trb_2); 2022 trb_3 = le32toh(trb->trb_3); 2023 2024 if (trb_0 == sc->sc_command_addr) { 2025 sc->sc_result_trb.trb_0 = trb_0; 2026 sc->sc_result_trb.trb_2 = trb_2; 2027 sc->sc_result_trb.trb_3 = trb_3; 2028 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2029 XHCI_TRB_ERROR_SUCCESS) { 2030 DPRINTFN(1, "command completion " 2031 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 2032 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 2033 } 2034 cv_signal(&sc->sc_command_cv); 2035 } else { 2036 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 2037 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 2038 trb_2, trb_3); 2039 } 2040 } 2041 2042 /* 2043 * Process events. 2044 * called from xhci_softintr 2045 */ 2046 static void 2047 xhci_handle_event(struct xhci_softc * const sc, 2048 const struct xhci_trb * const trb) 2049 { 2050 uint64_t trb_0; 2051 uint32_t trb_2, trb_3; 2052 2053 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2054 2055 trb_0 = le64toh(trb->trb_0); 2056 trb_2 = le32toh(trb->trb_2); 2057 trb_3 = le32toh(trb->trb_3); 2058 2059 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2060 trb, trb_0, trb_2, trb_3); 2061 2062 /* 2063 * 4.11.3.1, 6.4.2.1 2064 * TRB Pointer is invalid for these completion codes. 2065 */ 2066 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2067 case XHCI_TRB_ERROR_RING_UNDERRUN: 2068 case XHCI_TRB_ERROR_RING_OVERRUN: 2069 case XHCI_TRB_ERROR_VF_RING_FULL: 2070 return; 2071 default: 2072 if (trb_0 == 0) { 2073 return; 2074 } 2075 break; 2076 } 2077 2078 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2079 case XHCI_TRB_EVENT_TRANSFER: 2080 xhci_event_transfer(sc, trb); 2081 break; 2082 case XHCI_TRB_EVENT_CMD_COMPLETE: 2083 xhci_event_cmd(sc, trb); 2084 break; 2085 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2086 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2087 break; 2088 default: 2089 break; 2090 } 2091 } 2092 2093 static void 2094 xhci_softintr(void *v) 2095 { 2096 struct usbd_bus * const bus = v; 2097 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2098 struct xhci_ring * const er = &sc->sc_er; 2099 struct xhci_trb *trb; 2100 int i, j, k; 2101 2102 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2103 2104 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2105 2106 i = er->xr_ep; 2107 j = er->xr_cs; 2108 2109 DPRINTFN(16, "xr_ep %d xr_cs %d", i, j, 0, 0); 2110 2111 while (1) { 2112 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2113 BUS_DMASYNC_POSTREAD); 2114 trb = &er->xr_trb[i]; 2115 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2116 2117 if (j != k) 2118 break; 2119 2120 xhci_handle_event(sc, trb); 2121 2122 i++; 2123 if (i == XHCI_EVENT_RING_TRBS) { 2124 i = 0; 2125 j ^= 1; 2126 } 2127 } 2128 2129 er->xr_ep = i; 2130 er->xr_cs = j; 2131 2132 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2133 XHCI_ERDP_LO_BUSY); 2134 2135 DPRINTFN(16, "ends", 0, 0, 0, 0); 2136 2137 return; 2138 } 2139 2140 static void 2141 xhci_poll(struct usbd_bus *bus) 2142 { 2143 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2144 2145 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2146 2147 mutex_spin_enter(&sc->sc_intr_lock); 2148 xhci_intr1(sc); 2149 mutex_spin_exit(&sc->sc_intr_lock); 2150 2151 return; 2152 } 2153 2154 static struct usbd_xfer * 2155 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2156 { 2157 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2158 struct usbd_xfer *xfer; 2159 2160 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2161 2162 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 2163 if (xfer != NULL) { 2164 memset(xfer, 0, sizeof(struct xhci_xfer)); 2165 #ifdef DIAGNOSTIC 2166 xfer->ux_state = XFER_BUSY; 2167 #endif 2168 } 2169 2170 return xfer; 2171 } 2172 2173 static void 2174 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2175 { 2176 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2177 2178 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2179 2180 #ifdef DIAGNOSTIC 2181 if (xfer->ux_state != XFER_BUSY) { 2182 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 2183 xfer, xfer->ux_state, 0, 0); 2184 } 2185 xfer->ux_state = XFER_FREE; 2186 #endif 2187 pool_cache_put(sc->sc_xferpool, xfer); 2188 } 2189 2190 static void 2191 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2192 { 2193 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2194 2195 *lock = &sc->sc_lock; 2196 } 2197 2198 extern uint32_t usb_cookie_no; 2199 2200 /* 2201 * xHCI 4.3 2202 * Called when uhub_explore finds a new device (via usbd_new_device). 2203 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2204 * This function does: 2205 * Allocate and construct dev structure of default endpoint (ep0). 2206 * Allocate and open pipe of ep0. 2207 * Enable slot and initialize slot context. 2208 * Set Address. 2209 * Read initial device descriptor. 2210 * Determine initial MaxPacketSize (mps) by speed. 2211 * Read full device descriptor. 2212 * Register this device. 2213 */ 2214 static usbd_status 2215 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2216 int speed, int port, struct usbd_port *up) 2217 { 2218 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2219 struct usbd_device *dev; 2220 usbd_status err; 2221 usb_device_descriptor_t *dd; 2222 struct usbd_device *hub; 2223 struct usbd_device *adev; 2224 int rhport = 0; 2225 struct xhci_slot *xs; 2226 uint32_t *cp; 2227 uint32_t route = 0; 2228 uint8_t slot = 0; 2229 uint8_t addr; 2230 2231 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2232 DPRINTFN(4, "port=%d depth=%d speed=%d upport %d", 2233 port, depth, speed, up->up_portno); 2234 2235 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2236 if (dev == NULL) 2237 return USBD_NOMEM; 2238 2239 dev->ud_bus = bus; 2240 2241 /* Set up default endpoint handle. */ 2242 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2243 2244 /* Set up default endpoint descriptor. */ 2245 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2246 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2247 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2248 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2249 /* 4.3, 4.8.2.1 */ 2250 switch (speed) { 2251 case USB_SPEED_SUPER: 2252 case USB_SPEED_SUPER_PLUS: 2253 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2254 break; 2255 case USB_SPEED_FULL: 2256 /* XXX using 64 as initial mps of ep0 in FS */ 2257 case USB_SPEED_HIGH: 2258 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2259 break; 2260 case USB_SPEED_LOW: 2261 default: 2262 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2263 break; 2264 } 2265 dev->ud_ep0desc.bInterval = 0; 2266 2267 /* doesn't matter, just don't let it uninitialized */ 2268 dev->ud_ep0.ue_toggle = 0; 2269 2270 DPRINTFN(4, "up %p portno %d", up, up->up_portno, 0, 0); 2271 2272 dev->ud_quirks = &usbd_no_quirk; 2273 dev->ud_addr = 0; 2274 dev->ud_ddesc.bMaxPacketSize = 0; 2275 dev->ud_depth = depth; 2276 dev->ud_powersrc = up; 2277 dev->ud_myhub = up->up_parent; 2278 2279 up->up_dev = dev; 2280 2281 /* Locate root hub port */ 2282 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2283 uint32_t dep; 2284 2285 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2286 hub, hub->ud_depth, hub->ud_powersrc, 2287 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2288 2289 if (hub->ud_powersrc == NULL) 2290 break; 2291 dep = hub->ud_depth; 2292 if (dep == 0) 2293 break; 2294 rhport = hub->ud_powersrc->up_portno; 2295 if (dep > USB_HUB_MAX_DEPTH) 2296 continue; 2297 2298 route |= 2299 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2300 << ((dep - 1) * 4); 2301 } 2302 route = route >> 4; 2303 DPRINTFN(4, "rhport %d Route %05x hub %p", rhport, route, hub, 0); 2304 2305 /* Locate port on upstream high speed hub */ 2306 for (adev = dev, hub = up->up_parent; 2307 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2308 adev = hub, hub = hub->ud_myhub) 2309 ; 2310 if (hub) { 2311 int p; 2312 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2313 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2314 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2315 goto found; 2316 } 2317 } 2318 panic("xhci_new_device: cannot find HS port"); 2319 found: 2320 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2321 } else { 2322 dev->ud_myhsport = NULL; 2323 } 2324 2325 dev->ud_speed = speed; 2326 dev->ud_langid = USBD_NOLANG; 2327 dev->ud_cookie.cookie = ++usb_cookie_no; 2328 2329 /* Establish the default pipe. */ 2330 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2331 &dev->ud_pipe0); 2332 if (err) { 2333 goto bad; 2334 } 2335 2336 dd = &dev->ud_ddesc; 2337 2338 if ((depth == 0) && (port == 0)) { 2339 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2340 bus->ub_devices[dev->ud_addr] = dev; 2341 err = usbd_get_initial_ddesc(dev, dd); 2342 if (err) 2343 goto bad; 2344 err = usbd_reload_device_desc(dev); 2345 if (err) 2346 goto bad; 2347 } else { 2348 err = xhci_enable_slot(sc, &slot); 2349 if (err) 2350 goto bad; 2351 xs = &sc->sc_slots[slot]; 2352 dev->ud_hcpriv = xs; 2353 err = xhci_init_slot(dev, slot, route, rhport); 2354 if (err) { 2355 dev->ud_hcpriv = NULL; 2356 /* 2357 * We have to disable_slot here because 2358 * xs->xs_idx == 0 when xhci_init_slot fails, 2359 * in that case usbd_remove_dev won't work. 2360 */ 2361 mutex_enter(&sc->sc_lock); 2362 xhci_disable_slot(sc, slot); 2363 mutex_exit(&sc->sc_lock); 2364 goto bad; 2365 } 2366 2367 /* Allow device time to set new address */ 2368 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2369 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2370 //hexdump("slot context", cp, sc->sc_ctxsz); 2371 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2372 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2373 /* XXX ensure we know when the hardware does something 2374 we can't yet cope with */ 2375 KASSERT(addr >= 1 && addr <= 127); 2376 dev->ud_addr = addr; 2377 /* XXX dev->ud_addr not necessarily unique on bus */ 2378 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2379 bus->ub_devices[dev->ud_addr] = dev; 2380 2381 err = usbd_get_initial_ddesc(dev, dd); 2382 if (err) 2383 goto bad; 2384 /* 4.8.2.1 */ 2385 if (USB_IS_SS(speed)) { 2386 if (dd->bMaxPacketSize != 9) { 2387 printf("%s: invalid mps 2^%u for SS ep0," 2388 " using 512\n", 2389 device_xname(sc->sc_dev), 2390 dd->bMaxPacketSize); 2391 dd->bMaxPacketSize = 9; 2392 } 2393 USETW(dev->ud_ep0desc.wMaxPacketSize, 2394 (1 << dd->bMaxPacketSize)); 2395 } else 2396 USETW(dev->ud_ep0desc.wMaxPacketSize, 2397 dd->bMaxPacketSize); 2398 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2399 xhci_update_ep0_mps(sc, xs, 2400 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2401 err = usbd_reload_device_desc(dev); 2402 if (err) 2403 goto bad; 2404 2405 #if 0 2406 /* Re-establish the default pipe with the new MPS. */ 2407 /* In xhci.c xhci_update_ep0_mps() does it instead. */ 2408 usbd_kill_pipe(dev->ud_pipe0); 2409 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, 2410 USBD_DEFAULT_INTERVAL, &dev->ud_pipe0); 2411 #endif 2412 } 2413 2414 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2415 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2416 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2417 dd->bDeviceClass, dd->bDeviceSubClass, 2418 dd->bDeviceProtocol, 0); 2419 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2420 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2421 dev->ud_speed); 2422 2423 usbd_get_device_strings(dev); 2424 2425 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2426 2427 if ((depth == 0) && (port == 0)) { 2428 usbd_attach_roothub(parent, dev); 2429 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2430 return USBD_NORMAL_COMPLETION; 2431 } 2432 2433 2434 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2435 bad: 2436 if (err != USBD_NORMAL_COMPLETION) { 2437 usbd_remove_device(dev, up); 2438 } 2439 2440 return err; 2441 } 2442 2443 static usbd_status 2444 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2445 size_t ntrb, size_t align) 2446 { 2447 usbd_status err; 2448 size_t size = ntrb * XHCI_TRB_SIZE; 2449 2450 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2451 2452 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2453 if (err) 2454 return err; 2455 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2456 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2457 xr->xr_trb = xhci_ring_trbv(xr, 0); 2458 xr->xr_ntrb = ntrb; 2459 xr->xr_ep = 0; 2460 xr->xr_cs = 1; 2461 memset(xr->xr_trb, 0, size); 2462 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 2463 xr->is_halted = false; 2464 2465 return USBD_NORMAL_COMPLETION; 2466 } 2467 2468 static void 2469 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2470 { 2471 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2472 mutex_destroy(&xr->xr_lock); 2473 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2474 } 2475 2476 static void 2477 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2478 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2479 { 2480 size_t i; 2481 u_int ri; 2482 u_int cs; 2483 uint64_t parameter; 2484 uint32_t status; 2485 uint32_t control; 2486 2487 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2488 2489 KASSERT(ntrbs <= XHCI_XFER_NTRB); 2490 for (i = 0; i < ntrbs; i++) { 2491 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2492 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2493 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2494 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2495 XHCI_TRB_TYPE_LINK); 2496 } 2497 2498 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2499 2500 ri = xr->xr_ep; 2501 cs = xr->xr_cs; 2502 2503 /* 2504 * Although the xhci hardware can do scatter/gather dma from 2505 * arbitrary sized buffers, there is a non-obvious restriction 2506 * that a LINK trb is only allowed at the end of a burst of 2507 * transfers - which might be 16kB. 2508 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2509 * The simple solution is not to allow a LINK trb in the middle 2510 * of anything - as here. 2511 * XXX: (dsl) There are xhci controllers out there (eg some made by 2512 * ASMedia) that seem to lock up if they process a LINK trb but 2513 * cannot process the linked-to trb yet. 2514 * The code should write the 'cycle' bit on the link trb AFTER 2515 * adding the other trb. 2516 */ 2517 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2518 parameter = xhci_ring_trbp(xr, 0); 2519 status = 0; 2520 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2521 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2522 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2523 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2524 BUS_DMASYNC_PREWRITE); 2525 xr->xr_cookies[ri] = NULL; 2526 xr->xr_ep = 0; 2527 xr->xr_cs ^= 1; 2528 ri = xr->xr_ep; 2529 cs = xr->xr_cs; 2530 } 2531 2532 ri++; 2533 2534 /* Write any subsequent TRB first */ 2535 for (i = 1; i < ntrbs; i++) { 2536 parameter = trbs[i].trb_0; 2537 status = trbs[i].trb_2; 2538 control = trbs[i].trb_3; 2539 2540 if (cs) { 2541 control |= XHCI_TRB_3_CYCLE_BIT; 2542 } else { 2543 control &= ~XHCI_TRB_3_CYCLE_BIT; 2544 } 2545 2546 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2547 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2548 BUS_DMASYNC_PREWRITE); 2549 xr->xr_cookies[ri] = cookie; 2550 ri++; 2551 } 2552 2553 /* Write the first TRB last */ 2554 i = 0; 2555 parameter = trbs[i].trb_0; 2556 status = trbs[i].trb_2; 2557 control = trbs[i].trb_3; 2558 2559 if (xr->xr_cs) { 2560 control |= XHCI_TRB_3_CYCLE_BIT; 2561 } else { 2562 control &= ~XHCI_TRB_3_CYCLE_BIT; 2563 } 2564 2565 xhci_trb_put(&xr->xr_trb[xr->xr_ep], parameter, status, control); 2566 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2567 BUS_DMASYNC_PREWRITE); 2568 xr->xr_cookies[xr->xr_ep] = cookie; 2569 2570 xr->xr_ep = ri; 2571 xr->xr_cs = cs; 2572 2573 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2574 } 2575 2576 /* 2577 * Stop execution commands, purge all commands on command ring, and 2578 * rewind enqueue pointer. 2579 */ 2580 static void 2581 xhci_abort_command(struct xhci_softc *sc) 2582 { 2583 struct xhci_ring * const cr = &sc->sc_cr; 2584 uint64_t crcr; 2585 int i; 2586 2587 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2588 DPRINTFN(14, "command %#"PRIx64" timeout, aborting", 2589 sc->sc_command_addr, 0, 0, 0); 2590 2591 mutex_enter(&cr->xr_lock); 2592 2593 /* 4.6.1.2 Aborting a Command */ 2594 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2595 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2596 2597 for (i = 0; i < 500; i++) { 2598 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2599 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2600 break; 2601 usb_delay_ms(&sc->sc_bus, 1); 2602 } 2603 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2604 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2605 /* reset HC here? */ 2606 } 2607 2608 /* reset command ring dequeue pointer */ 2609 cr->xr_ep = 0; 2610 cr->xr_cs = 1; 2611 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2612 2613 mutex_exit(&cr->xr_lock); 2614 } 2615 2616 /* 2617 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2618 * Command completion is notified by cv_signal from xhci_handle_event 2619 * (called from interrupt from xHCI), or timed-out. 2620 * Command validation is performed in xhci_handle_event by checking if 2621 * trb_0 in CMD_COMPLETE TRB and sc->sc_command_addr are identical. 2622 */ 2623 static usbd_status 2624 xhci_do_command_locked(struct xhci_softc * const sc, struct xhci_trb * const trb, 2625 int timeout) 2626 { 2627 struct xhci_ring * const cr = &sc->sc_cr; 2628 usbd_status err; 2629 2630 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2631 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2632 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2633 2634 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2635 KASSERT(mutex_owned(&sc->sc_lock)); 2636 2637 /* XXX KASSERT may fire when cv_timedwait unlocks sc_lock */ 2638 KASSERT(sc->sc_command_addr == 0); 2639 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2640 2641 mutex_enter(&cr->xr_lock); 2642 xhci_ring_put(sc, cr, NULL, trb, 1); 2643 mutex_exit(&cr->xr_lock); 2644 2645 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2646 2647 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2648 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2649 xhci_abort_command(sc); 2650 err = USBD_TIMEOUT; 2651 goto timedout; 2652 } 2653 2654 trb->trb_0 = sc->sc_result_trb.trb_0; 2655 trb->trb_2 = sc->sc_result_trb.trb_2; 2656 trb->trb_3 = sc->sc_result_trb.trb_3; 2657 2658 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2659 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2660 2661 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2662 case XHCI_TRB_ERROR_SUCCESS: 2663 err = USBD_NORMAL_COMPLETION; 2664 break; 2665 default: 2666 case 192 ... 223: 2667 err = USBD_IOERROR; 2668 break; 2669 case 224 ... 255: 2670 err = USBD_NORMAL_COMPLETION; 2671 break; 2672 } 2673 2674 timedout: 2675 sc->sc_command_addr = 0; 2676 return err; 2677 } 2678 2679 static usbd_status 2680 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2681 int timeout) 2682 { 2683 2684 mutex_enter(&sc->sc_lock); 2685 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2686 mutex_exit(&sc->sc_lock); 2687 2688 return ret; 2689 } 2690 2691 static usbd_status 2692 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2693 { 2694 struct xhci_trb trb; 2695 usbd_status err; 2696 2697 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2698 2699 trb.trb_0 = 0; 2700 trb.trb_2 = 0; 2701 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2702 2703 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2704 if (err != USBD_NORMAL_COMPLETION) { 2705 return err; 2706 } 2707 2708 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2709 2710 return err; 2711 } 2712 2713 /* 2714 * xHCI 4.6.4 2715 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2716 * All endpoints in the slot should be stopped. 2717 * Should be called with sc_lock held. 2718 */ 2719 static usbd_status 2720 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2721 { 2722 struct xhci_trb trb; 2723 struct xhci_slot *xs; 2724 usbd_status err; 2725 2726 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2727 2728 if (sc->sc_dying) 2729 return USBD_IOERROR; 2730 2731 trb.trb_0 = 0; 2732 trb.trb_2 = 0; 2733 trb.trb_3 = htole32( 2734 XHCI_TRB_3_SLOT_SET(slot) | 2735 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2736 2737 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2738 2739 if (!err) { 2740 xs = &sc->sc_slots[slot]; 2741 if (xs->xs_idx != 0) { 2742 for (int i = XHCI_DCI_SLOT + 1; i < 32; i++) { 2743 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2744 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2745 } 2746 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2747 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2748 xhci_set_dcba(sc, 0, slot); 2749 memset(xs, 0, sizeof(*xs)); 2750 } 2751 } 2752 2753 return err; 2754 } 2755 2756 /* 2757 * Set address of device and transition slot state from ENABLED to ADDRESSED 2758 * if Block Setaddress Request (BSR) is false. 2759 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2760 * see xHCI 1.1 4.5.3, 3.3.4 2761 * Should be called without sc_lock held. 2762 */ 2763 static usbd_status 2764 xhci_address_device(struct xhci_softc * const sc, 2765 uint64_t icp, uint8_t slot_id, bool bsr) 2766 { 2767 struct xhci_trb trb; 2768 usbd_status err; 2769 2770 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2771 2772 trb.trb_0 = icp; 2773 trb.trb_2 = 0; 2774 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2775 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2776 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2777 2778 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2779 2780 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2781 err = USBD_NO_ADDR; 2782 2783 return err; 2784 } 2785 2786 static usbd_status 2787 xhci_update_ep0_mps(struct xhci_softc * const sc, 2788 struct xhci_slot * const xs, u_int mps) 2789 { 2790 struct xhci_trb trb; 2791 usbd_status err; 2792 uint32_t * cp; 2793 2794 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2795 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2796 2797 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2798 cp[0] = htole32(0); 2799 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2800 2801 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2802 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2803 2804 /* sync input contexts before they are read from memory */ 2805 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2806 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2807 sc->sc_ctxsz * 4); 2808 2809 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2810 trb.trb_2 = 0; 2811 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2812 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2813 2814 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2815 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2816 return err; 2817 } 2818 2819 static void 2820 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2821 { 2822 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2823 2824 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2825 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2826 &dcbaa[si], dcba, si, 0); 2827 2828 dcbaa[si] = htole64(dcba); 2829 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2830 BUS_DMASYNC_PREWRITE); 2831 } 2832 2833 /* 2834 * Allocate DMA buffer and ring buffer for specified slot 2835 * and set Device Context Base Address 2836 * and issue Set Address device command. 2837 */ 2838 static usbd_status 2839 xhci_init_slot(struct usbd_device *dev, uint32_t slot, uint32_t route, int rhport) 2840 { 2841 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2842 struct xhci_slot *xs; 2843 usbd_status err; 2844 u_int dci; 2845 uint32_t *cp; 2846 uint32_t mps = UGETW(dev->ud_ep0desc.wMaxPacketSize); 2847 2848 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2849 DPRINTFN(4, "slot %u speed %d route %05x rhport %d", 2850 slot, dev->ud_speed, route, rhport); 2851 2852 xs = &sc->sc_slots[slot]; 2853 2854 /* allocate contexts */ 2855 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2856 &xs->xs_dc_dma); 2857 if (err) 2858 return err; 2859 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2860 2861 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2862 &xs->xs_ic_dma); 2863 if (err) 2864 goto bad1; 2865 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2866 2867 for (dci = 0; dci < 32; dci++) { 2868 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2869 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2870 if (dci == XHCI_DCI_SLOT) 2871 continue; 2872 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2873 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2874 if (err) { 2875 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2876 goto bad2; 2877 } 2878 } 2879 2880 /* set up initial input control context */ 2881 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2882 cp[0] = htole32(0); 2883 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 2884 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2885 2886 /* set up input slot context */ 2887 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2888 xhci_setup_sctx(dev, cp); 2889 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(1)); 2890 cp[0] |= htole32(XHCI_SCTX_0_ROUTE_SET(route)); 2891 cp[1] |= htole32(XHCI_SCTX_1_RH_PORT_SET(rhport)); 2892 2893 /* set up input EP0 context */ 2894 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2895 cp[0] = htole32(0); 2896 cp[1] = htole32( 2897 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 2898 XHCI_EPCTX_1_EPTYPE_SET(4) | 2899 XHCI_EPCTX_1_CERR_SET(3) 2900 ); 2901 /* can't use xhci_ep_get_dci() yet? */ 2902 *(uint64_t *)(&cp[2]) = htole64( 2903 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 2904 XHCI_EPCTX_2_DCS_SET(1)); 2905 cp[4] = htole32( 2906 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 2907 ); 2908 2909 /* sync input contexts before they are read from memory */ 2910 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2911 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2912 sc->sc_ctxsz * 3); 2913 2914 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2915 2916 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 2917 false); 2918 2919 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2920 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2921 sc->sc_ctxsz * 2); 2922 2923 bad2: 2924 if (err == USBD_NORMAL_COMPLETION) { 2925 xs->xs_idx = slot; 2926 } else { 2927 for (int i = 1; i < dci; i++) { 2928 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2929 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2930 } 2931 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2932 bad1: 2933 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2934 xs->xs_idx = 0; 2935 } 2936 2937 return err; 2938 } 2939 2940 /* ----- */ 2941 2942 static void 2943 xhci_noop(struct usbd_pipe *pipe) 2944 { 2945 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2946 } 2947 2948 /* 2949 * Process root hub request. 2950 */ 2951 static int 2952 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2953 void *buf, int buflen) 2954 { 2955 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2956 usb_port_status_t ps; 2957 int l, totlen = 0; 2958 uint16_t len, value, index; 2959 int port, i; 2960 uint32_t v; 2961 2962 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2963 2964 if (sc->sc_dying) 2965 return -1; 2966 2967 len = UGETW(req->wLength); 2968 value = UGETW(req->wValue); 2969 index = UGETW(req->wIndex); 2970 2971 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 2972 req->bmRequestType | (req->bRequest << 8), value, index, len); 2973 2974 #define C(x,y) ((x) | ((y) << 8)) 2975 switch (C(req->bRequest, req->bmRequestType)) { 2976 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2977 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 2978 if (len == 0) 2979 break; 2980 switch (value) { 2981 case C(0, UDESC_DEVICE): { 2982 usb_device_descriptor_t devd; 2983 totlen = min(buflen, sizeof(devd)); 2984 memcpy(&devd, buf, totlen); 2985 USETW(devd.idVendor, sc->sc_id_vendor); 2986 memcpy(buf, &devd, totlen); 2987 break; 2988 } 2989 #define sd ((usb_string_descriptor_t *)buf) 2990 case C(1, UDESC_STRING): 2991 /* Vendor */ 2992 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2993 break; 2994 case C(2, UDESC_STRING): 2995 /* Product */ 2996 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 2997 break; 2998 #undef sd 2999 default: 3000 /* default from usbroothub */ 3001 return buflen; 3002 } 3003 break; 3004 3005 /* Hub requests */ 3006 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3007 break; 3008 /* Clear Port Feature request */ 3009 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3010 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 3011 index, value, 0, 0); 3012 if (index < 1 || index > sc->sc_maxports) { 3013 return -1; 3014 } 3015 port = XHCI_PORTSC(index); 3016 v = xhci_op_read_4(sc, port); 3017 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3018 v &= ~XHCI_PS_CLEAR; 3019 switch (value) { 3020 case UHF_PORT_ENABLE: 3021 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3022 break; 3023 case UHF_PORT_SUSPEND: 3024 return -1; 3025 case UHF_PORT_POWER: 3026 break; 3027 case UHF_PORT_TEST: 3028 case UHF_PORT_INDICATOR: 3029 return -1; 3030 case UHF_C_PORT_CONNECTION: 3031 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3032 break; 3033 case UHF_C_PORT_ENABLE: 3034 case UHF_C_PORT_SUSPEND: 3035 case UHF_C_PORT_OVER_CURRENT: 3036 return -1; 3037 case UHF_C_BH_PORT_RESET: 3038 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3039 break; 3040 case UHF_C_PORT_RESET: 3041 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3042 break; 3043 case UHF_C_PORT_LINK_STATE: 3044 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3045 break; 3046 case UHF_C_PORT_CONFIG_ERROR: 3047 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3048 break; 3049 default: 3050 return -1; 3051 } 3052 break; 3053 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3054 if (len == 0) 3055 break; 3056 if ((value & 0xff) != 0) { 3057 return -1; 3058 } 3059 usb_hub_descriptor_t hubd; 3060 3061 totlen = min(buflen, sizeof(hubd)); 3062 memcpy(&hubd, buf, totlen); 3063 hubd.bNbrPorts = sc->sc_maxports; 3064 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3065 hubd.bPwrOn2PwrGood = 200; 3066 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 3067 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 3068 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3069 totlen = min(totlen, hubd.bDescLength); 3070 memcpy(buf, &hubd, totlen); 3071 break; 3072 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3073 if (len != 4) { 3074 return -1; 3075 } 3076 memset(buf, 0, len); /* ? XXX */ 3077 totlen = len; 3078 break; 3079 /* Get Port Status request */ 3080 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3081 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 3082 if (index < 1 || index > sc->sc_maxports) { 3083 return -1; 3084 } 3085 if (len != 4) { 3086 return -1; 3087 } 3088 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 3089 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 3090 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3091 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3092 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3093 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3094 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3095 if (v & XHCI_PS_PR) i |= UPS_RESET; 3096 if (v & XHCI_PS_PP) { 3097 if (i & UPS_OTHER_SPEED) 3098 i |= UPS_PORT_POWER_SS; 3099 else 3100 i |= UPS_PORT_POWER; 3101 } 3102 if (i & UPS_OTHER_SPEED) 3103 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3104 if (sc->sc_vendor_port_status) 3105 i = sc->sc_vendor_port_status(sc, v, i); 3106 USETW(ps.wPortStatus, i); 3107 i = 0; 3108 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3109 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3110 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3111 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3112 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3113 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3114 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3115 USETW(ps.wPortChange, i); 3116 totlen = min(len, sizeof(ps)); 3117 memcpy(buf, &ps, totlen); 3118 break; 3119 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3120 return -1; 3121 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3122 break; 3123 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3124 break; 3125 /* Set Port Feature request */ 3126 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3127 int optval = (index >> 8) & 0xff; 3128 index &= 0xff; 3129 if (index < 1 || index > sc->sc_maxports) { 3130 return -1; 3131 } 3132 port = XHCI_PORTSC(index); 3133 v = xhci_op_read_4(sc, port); 3134 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3135 v &= ~XHCI_PS_CLEAR; 3136 switch (value) { 3137 case UHF_PORT_ENABLE: 3138 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3139 break; 3140 case UHF_PORT_SUSPEND: 3141 /* XXX suspend */ 3142 break; 3143 case UHF_PORT_RESET: 3144 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3145 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3146 /* Wait for reset to complete. */ 3147 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3148 if (sc->sc_dying) { 3149 return -1; 3150 } 3151 v = xhci_op_read_4(sc, port); 3152 if (v & XHCI_PS_PR) { 3153 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3154 usb_delay_ms(&sc->sc_bus, 10); 3155 /* XXX */ 3156 } 3157 break; 3158 case UHF_PORT_POWER: 3159 /* XXX power control */ 3160 break; 3161 /* XXX more */ 3162 case UHF_C_PORT_RESET: 3163 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3164 break; 3165 case UHF_PORT_U1_TIMEOUT: 3166 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3167 return -1; 3168 } 3169 port = XHCI_PORTPMSC(index); 3170 v = xhci_op_read_4(sc, port); 3171 v &= ~XHCI_PM3_U1TO_SET(0xff); 3172 v |= XHCI_PM3_U1TO_SET(optval); 3173 xhci_op_write_4(sc, port, v); 3174 break; 3175 case UHF_PORT_U2_TIMEOUT: 3176 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3177 return -1; 3178 } 3179 port = XHCI_PORTPMSC(index); 3180 v = xhci_op_read_4(sc, port); 3181 v &= ~XHCI_PM3_U2TO_SET(0xff); 3182 v |= XHCI_PM3_U2TO_SET(optval); 3183 xhci_op_write_4(sc, port, v); 3184 break; 3185 default: 3186 return -1; 3187 } 3188 } 3189 break; 3190 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3191 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3192 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3193 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3194 break; 3195 default: 3196 /* default from usbroothub */ 3197 return buflen; 3198 } 3199 3200 return totlen; 3201 } 3202 3203 /* root hub interrupt */ 3204 3205 static usbd_status 3206 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3207 { 3208 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3209 usbd_status err; 3210 3211 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3212 3213 /* Insert last in queue. */ 3214 mutex_enter(&sc->sc_lock); 3215 err = usb_insert_transfer(xfer); 3216 mutex_exit(&sc->sc_lock); 3217 if (err) 3218 return err; 3219 3220 /* Pipe isn't running, start first */ 3221 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3222 } 3223 3224 /* Wait for roothub port status/change */ 3225 static usbd_status 3226 xhci_root_intr_start(struct usbd_xfer *xfer) 3227 { 3228 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3229 3230 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3231 3232 if (sc->sc_dying) 3233 return USBD_IOERROR; 3234 3235 mutex_enter(&sc->sc_lock); 3236 sc->sc_intrxfer = xfer; 3237 mutex_exit(&sc->sc_lock); 3238 3239 return USBD_IN_PROGRESS; 3240 } 3241 3242 static void 3243 xhci_root_intr_abort(struct usbd_xfer *xfer) 3244 { 3245 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3246 3247 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3248 3249 KASSERT(mutex_owned(&sc->sc_lock)); 3250 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3251 3252 sc->sc_intrxfer = NULL; 3253 3254 xfer->ux_status = USBD_CANCELLED; 3255 usb_transfer_complete(xfer); 3256 } 3257 3258 static void 3259 xhci_root_intr_close(struct usbd_pipe *pipe) 3260 { 3261 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3262 3263 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3264 3265 KASSERT(mutex_owned(&sc->sc_lock)); 3266 3267 sc->sc_intrxfer = NULL; 3268 } 3269 3270 static void 3271 xhci_root_intr_done(struct usbd_xfer *xfer) 3272 { 3273 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3274 3275 } 3276 3277 /* -------------- */ 3278 /* device control */ 3279 3280 static usbd_status 3281 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3282 { 3283 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3284 usbd_status err; 3285 3286 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3287 3288 /* Insert last in queue. */ 3289 mutex_enter(&sc->sc_lock); 3290 err = usb_insert_transfer(xfer); 3291 mutex_exit(&sc->sc_lock); 3292 if (err) 3293 return err; 3294 3295 /* Pipe isn't running, start first */ 3296 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3297 } 3298 3299 static usbd_status 3300 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3301 { 3302 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3303 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3304 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3305 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3306 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3307 usb_device_request_t * const req = &xfer->ux_request; 3308 const int isread = usbd_xfer_isread(xfer); 3309 const uint32_t len = UGETW(req->wLength); 3310 usb_dma_t * const dma = &xfer->ux_dmabuf; 3311 uint64_t parameter; 3312 uint32_t status; 3313 uint32_t control; 3314 u_int i; 3315 3316 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3317 DPRINTFN(12, "req: %04x %04x %04x %04x", 3318 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3319 UGETW(req->wIndex), UGETW(req->wLength)); 3320 3321 #if 0 /* event handler does this */ 3322 /* XXX */ 3323 if (tr->is_halted) { 3324 DPRINTFN(1, "ctrl xfer %p halted: slot %u dci %u", 3325 xfer, xs->xs_idx, dci, 0); 3326 xhci_reset_endpoint(xfer->ux_pipe); 3327 tr->is_halted = false; 3328 xhci_set_dequeue(xfer->ux_pipe); 3329 } 3330 #endif 3331 3332 /* we rely on the bottom bits for extra info */ 3333 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 3334 3335 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3336 3337 i = 0; 3338 3339 /* setup phase */ 3340 memcpy(¶meter, req, sizeof(*req)); 3341 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3342 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3343 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3344 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3345 XHCI_TRB_3_IDT_BIT; 3346 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3347 3348 if (len != 0) { 3349 /* data phase */ 3350 parameter = DMAADDR(dma, 0); 3351 KASSERT(len <= 0x10000); 3352 status = XHCI_TRB_2_IRQ_SET(0) | 3353 XHCI_TRB_2_TDSZ_SET(1) | 3354 XHCI_TRB_2_BYTES_SET(len); 3355 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3356 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3357 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3358 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3359 3360 parameter = (uintptr_t)xfer | 0x3; 3361 status = XHCI_TRB_2_IRQ_SET(0); 3362 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3363 XHCI_TRB_3_IOC_BIT; 3364 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3365 } 3366 3367 parameter = 0; 3368 status = XHCI_TRB_2_IRQ_SET(0); 3369 /* the status stage has inverted direction */ 3370 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3371 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3372 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3373 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3374 3375 parameter = (uintptr_t)xfer | 0x0; 3376 status = XHCI_TRB_2_IRQ_SET(0); 3377 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3378 XHCI_TRB_3_IOC_BIT; 3379 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3380 3381 mutex_enter(&tr->xr_lock); 3382 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3383 mutex_exit(&tr->xr_lock); 3384 3385 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3386 3387 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3388 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3389 xhci_timeout, xfer); 3390 } 3391 3392 if (sc->sc_bus.ub_usepolling) { 3393 DPRINTFN(1, "polling", 0, 0, 0, 0); 3394 //xhci_waitintr(sc, xfer); 3395 } 3396 3397 return USBD_IN_PROGRESS; 3398 } 3399 3400 static void 3401 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3402 { 3403 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3404 usb_device_request_t *req = &xfer->ux_request; 3405 int len = UGETW(req->wLength); 3406 int rd = req->bmRequestType & UT_READ; 3407 3408 if (len) 3409 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3410 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3411 } 3412 3413 static void 3414 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3415 { 3416 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3417 3418 xhci_abort_xfer(xfer, USBD_CANCELLED); 3419 } 3420 3421 static void 3422 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3423 { 3424 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3425 3426 xhci_close_pipe(pipe); 3427 } 3428 3429 /* ------------------ */ 3430 /* device isochronous */ 3431 3432 /* ----------- */ 3433 /* device bulk */ 3434 3435 static usbd_status 3436 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3437 { 3438 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3439 usbd_status err; 3440 3441 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3442 3443 /* Insert last in queue. */ 3444 mutex_enter(&sc->sc_lock); 3445 err = usb_insert_transfer(xfer); 3446 mutex_exit(&sc->sc_lock); 3447 if (err) 3448 return err; 3449 3450 /* 3451 * Pipe isn't running (otherwise err would be USBD_INPROG), 3452 * so start it first. 3453 */ 3454 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3455 } 3456 3457 static usbd_status 3458 xhci_device_bulk_start(struct usbd_xfer *xfer) 3459 { 3460 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3461 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3462 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3463 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3464 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3465 const uint32_t len = xfer->ux_length; 3466 usb_dma_t * const dma = &xfer->ux_dmabuf; 3467 uint64_t parameter; 3468 uint32_t status; 3469 uint32_t control; 3470 u_int i = 0; 3471 3472 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3473 3474 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3475 3476 if (sc->sc_dying) 3477 return USBD_IOERROR; 3478 3479 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3480 3481 parameter = DMAADDR(dma, 0); 3482 /* 3483 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3484 * If the user supplied buffer crosses such a boundary then 2 3485 * (or more) TRB should be used. 3486 * If multiple TRB are used the td_size field must be set correctly. 3487 * For v1.0 devices (like ivy bridge) this is the number of usb data 3488 * blocks needed to complete the transfer. 3489 * Setting it to 1 in the last TRB causes an extra zero-length 3490 * data block be sent. 3491 * The earlier documentation differs, I don't know how it behaves. 3492 */ 3493 KASSERT(len <= 0x10000); 3494 status = XHCI_TRB_2_IRQ_SET(0) | 3495 XHCI_TRB_2_TDSZ_SET(1) | 3496 XHCI_TRB_2_BYTES_SET(len); 3497 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3498 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3499 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3500 3501 mutex_enter(&tr->xr_lock); 3502 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3503 mutex_exit(&tr->xr_lock); 3504 3505 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3506 3507 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3508 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3509 xhci_timeout, xfer); 3510 } 3511 3512 if (sc->sc_bus.ub_usepolling) { 3513 DPRINTFN(1, "polling", 0, 0, 0, 0); 3514 //xhci_waitintr(sc, xfer); 3515 } 3516 3517 return USBD_IN_PROGRESS; 3518 } 3519 3520 static void 3521 xhci_device_bulk_done(struct usbd_xfer *xfer) 3522 { 3523 #ifdef USB_DEBUG 3524 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3525 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3526 #endif 3527 const int isread = usbd_xfer_isread(xfer); 3528 3529 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3530 3531 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3532 3533 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3534 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3535 } 3536 3537 static void 3538 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3539 { 3540 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3541 3542 xhci_abort_xfer(xfer, USBD_CANCELLED); 3543 } 3544 3545 static void 3546 xhci_device_bulk_close(struct usbd_pipe *pipe) 3547 { 3548 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3549 3550 xhci_close_pipe(pipe); 3551 } 3552 3553 /* ---------------- */ 3554 /* device interrupt */ 3555 3556 static usbd_status 3557 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3558 { 3559 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3560 usbd_status err; 3561 3562 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3563 3564 /* Insert last in queue. */ 3565 mutex_enter(&sc->sc_lock); 3566 err = usb_insert_transfer(xfer); 3567 mutex_exit(&sc->sc_lock); 3568 if (err) 3569 return err; 3570 3571 /* 3572 * Pipe isn't running (otherwise err would be USBD_INPROG), 3573 * so start it first. 3574 */ 3575 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3576 } 3577 3578 static usbd_status 3579 xhci_device_intr_start(struct usbd_xfer *xfer) 3580 { 3581 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3582 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3583 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3584 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3585 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3586 const uint32_t len = xfer->ux_length; 3587 usb_dma_t * const dma = &xfer->ux_dmabuf; 3588 uint64_t parameter; 3589 uint32_t status; 3590 uint32_t control; 3591 u_int i = 0; 3592 3593 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3594 3595 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3596 3597 if (sc->sc_dying) 3598 return USBD_IOERROR; 3599 3600 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3601 3602 parameter = DMAADDR(dma, 0); 3603 KASSERT(len <= 0x10000); 3604 status = XHCI_TRB_2_IRQ_SET(0) | 3605 XHCI_TRB_2_TDSZ_SET(1) | 3606 XHCI_TRB_2_BYTES_SET(len); 3607 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3608 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3609 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3610 3611 mutex_enter(&tr->xr_lock); 3612 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3613 mutex_exit(&tr->xr_lock); 3614 3615 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3616 3617 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3618 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3619 xhci_timeout, xfer); 3620 } 3621 3622 if (sc->sc_bus.ub_usepolling) { 3623 DPRINTFN(1, "polling", 0, 0, 0, 0); 3624 //xhci_waitintr(sc, xfer); 3625 } 3626 3627 return USBD_IN_PROGRESS; 3628 } 3629 3630 static void 3631 xhci_device_intr_done(struct usbd_xfer *xfer) 3632 { 3633 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3634 #ifdef USB_DEBUG 3635 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3636 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3637 #endif 3638 const int isread = usbd_xfer_isread(xfer); 3639 3640 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3641 3642 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3643 3644 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3645 3646 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3647 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3648 3649 #if 0 3650 device_printf(sc->sc_dev, ""); 3651 for (size_t i = 0; i < xfer->ux_length; i++) { 3652 printf(" %02x", ((uint8_t const *)xfer->ux_buffer)[i]); 3653 } 3654 printf("\n"); 3655 #endif 3656 3657 } 3658 3659 static void 3660 xhci_device_intr_abort(struct usbd_xfer *xfer) 3661 { 3662 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3663 3664 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3665 3666 KASSERT(mutex_owned(&sc->sc_lock)); 3667 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3668 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3669 xhci_abort_xfer(xfer, USBD_CANCELLED); 3670 } 3671 3672 static void 3673 xhci_device_intr_close(struct usbd_pipe *pipe) 3674 { 3675 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3676 3677 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3678 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3679 3680 xhci_close_pipe(pipe); 3681 } 3682 3683 /* ------------ */ 3684 3685 static void 3686 xhci_timeout(void *addr) 3687 { 3688 struct xhci_xfer * const xx = addr; 3689 struct usbd_xfer * const xfer = &xx->xx_xfer; 3690 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3691 3692 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3693 3694 if (sc->sc_dying) { 3695 return; 3696 } 3697 3698 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 3699 USB_TASKQ_MPSAFE); 3700 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 3701 USB_TASKQ_HC); 3702 } 3703 3704 static void 3705 xhci_timeout_task(void *addr) 3706 { 3707 struct usbd_xfer * const xfer = addr; 3708 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3709 3710 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3711 3712 mutex_enter(&sc->sc_lock); 3713 #if 0 3714 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3715 #else 3716 xfer->ux_status = USBD_TIMEOUT; 3717 usb_transfer_complete(xfer); 3718 #endif 3719 mutex_exit(&sc->sc_lock); 3720 } 3721
Indexes created Tue Sep 23 07:09:52 GMT 2025