xhci.c revision 1.44
1 /* $NetBSD: xhci.c,v 1.44 2016/05/06 10:27:14 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.44 2016/05/06 10:27:14 skrll Exp $"); 38 39 #include "opt_usb.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/kmem.h> 45 #include <sys/device.h> 46 #include <sys/select.h> 47 #include <sys/proc.h> 48 #include <sys/queue.h> 49 #include <sys/mutex.h> 50 #include <sys/condvar.h> 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/sysctl.h> 54 55 #include <machine/endian.h> 56 57 #include <dev/usb/usb.h> 58 #include <dev/usb/usbdi.h> 59 #include <dev/usb/usbdivar.h> 60 #include <dev/usb/usbdi_util.h> 61 #include <dev/usb/usbhist.h> 62 #include <dev/usb/usb_mem.h> 63 #include <dev/usb/usb_quirks.h> 64 65 #include <dev/usb/xhcireg.h> 66 #include <dev/usb/xhcivar.h> 67 #include <dev/usb/usbroothub.h> 68 69 70 #ifdef USB_DEBUG 71 #ifndef XHCI_DEBUG 72 #define xhcidebug 0 73 #else /* !XHCI_DEBUG */ 74 static int xhcidebug = 0; 75 76 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 77 { 78 int err; 79 const struct sysctlnode *rnode; 80 const struct sysctlnode *cnode; 81 82 err = sysctl_createv(clog, 0, NULL, &rnode, 83 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 84 SYSCTL_DESCR("xhci global controls"), 85 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 86 87 if (err) 88 goto fail; 89 90 /* control debugging printfs */ 91 err = sysctl_createv(clog, 0, &rnode, &cnode, 92 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 93 "debug", SYSCTL_DESCR("Enable debugging output"), 94 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 95 if (err) 96 goto fail; 97 98 return; 99 fail: 100 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 101 } 102 103 #endif /* !XHCI_DEBUG */ 104 #endif /* USB_DEBUG */ 105 106 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 107 #define XHCIHIST_FUNC() USBHIST_FUNC() 108 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 109 110 #define XHCI_DCI_SLOT 0 111 #define XHCI_DCI_EP_CONTROL 1 112 113 #define XHCI_ICI_INPUT_CONTROL 0 114 115 struct xhci_pipe { 116 struct usbd_pipe xp_pipe; 117 struct usb_task xp_async_task; 118 }; 119 120 #define XHCI_COMMAND_RING_TRBS 256 121 #define XHCI_EVENT_RING_TRBS 256 122 #define XHCI_EVENT_RING_SEGMENTS 1 123 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 124 125 static usbd_status xhci_open(struct usbd_pipe *); 126 static void xhci_close_pipe(struct usbd_pipe *); 127 static int xhci_intr1(struct xhci_softc * const); 128 static void xhci_softintr(void *); 129 static void xhci_poll(struct usbd_bus *); 130 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 131 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 132 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 133 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 134 struct usbd_port *); 135 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 136 void *, int); 137 138 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 139 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 140 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 141 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 142 143 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 144 145 static usbd_status xhci_do_command(struct xhci_softc * const, 146 struct xhci_trb * const, int); 147 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 148 struct xhci_trb * const, int); 149 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t, uint32_t, int); 150 static usbd_status xhci_enable_slot(struct xhci_softc * const, 151 uint8_t * const); 152 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 153 static usbd_status xhci_address_device(struct xhci_softc * const, 154 uint64_t, uint8_t, bool); 155 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 156 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 157 struct xhci_slot * const, u_int); 158 static usbd_status xhci_ring_init(struct xhci_softc * const, 159 struct xhci_ring * const, size_t, size_t); 160 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 161 162 static void xhci_noop(struct usbd_pipe *); 163 164 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 165 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 166 static void xhci_root_intr_abort(struct usbd_xfer *); 167 static void xhci_root_intr_close(struct usbd_pipe *); 168 static void xhci_root_intr_done(struct usbd_xfer *); 169 170 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 171 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 172 static void xhci_device_ctrl_abort(struct usbd_xfer *); 173 static void xhci_device_ctrl_close(struct usbd_pipe *); 174 static void xhci_device_ctrl_done(struct usbd_xfer *); 175 176 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 177 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 178 static void xhci_device_intr_abort(struct usbd_xfer *); 179 static void xhci_device_intr_close(struct usbd_pipe *); 180 static void xhci_device_intr_done(struct usbd_xfer *); 181 182 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 183 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 184 static void xhci_device_bulk_abort(struct usbd_xfer *); 185 static void xhci_device_bulk_close(struct usbd_pipe *); 186 static void xhci_device_bulk_done(struct usbd_xfer *); 187 188 static void xhci_timeout(void *); 189 static void xhci_timeout_task(void *); 190 191 static const struct usbd_bus_methods xhci_bus_methods = { 192 .ubm_open = xhci_open, 193 .ubm_softint = xhci_softintr, 194 .ubm_dopoll = xhci_poll, 195 .ubm_allocx = xhci_allocx, 196 .ubm_freex = xhci_freex, 197 .ubm_getlock = xhci_get_lock, 198 .ubm_newdev = xhci_new_device, 199 .ubm_rhctrl = xhci_roothub_ctrl, 200 }; 201 202 static const struct usbd_pipe_methods xhci_root_intr_methods = { 203 .upm_transfer = xhci_root_intr_transfer, 204 .upm_start = xhci_root_intr_start, 205 .upm_abort = xhci_root_intr_abort, 206 .upm_close = xhci_root_intr_close, 207 .upm_cleartoggle = xhci_noop, 208 .upm_done = xhci_root_intr_done, 209 }; 210 211 212 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 213 .upm_transfer = xhci_device_ctrl_transfer, 214 .upm_start = xhci_device_ctrl_start, 215 .upm_abort = xhci_device_ctrl_abort, 216 .upm_close = xhci_device_ctrl_close, 217 .upm_cleartoggle = xhci_noop, 218 .upm_done = xhci_device_ctrl_done, 219 }; 220 221 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 222 .upm_cleartoggle = xhci_noop, 223 }; 224 225 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 226 .upm_transfer = xhci_device_bulk_transfer, 227 .upm_start = xhci_device_bulk_start, 228 .upm_abort = xhci_device_bulk_abort, 229 .upm_close = xhci_device_bulk_close, 230 .upm_cleartoggle = xhci_noop, 231 .upm_done = xhci_device_bulk_done, 232 }; 233 234 static const struct usbd_pipe_methods xhci_device_intr_methods = { 235 .upm_transfer = xhci_device_intr_transfer, 236 .upm_start = xhci_device_intr_start, 237 .upm_abort = xhci_device_intr_abort, 238 .upm_close = xhci_device_intr_close, 239 .upm_cleartoggle = xhci_noop, 240 .upm_done = xhci_device_intr_done, 241 }; 242 243 static inline uint32_t 244 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 245 { 246 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 247 } 248 249 static inline uint32_t 250 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 251 { 252 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 253 } 254 255 static inline void 256 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 257 uint32_t value) 258 { 259 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 260 } 261 262 #if 0 /* unused */ 263 static inline void 264 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 265 uint32_t value) 266 { 267 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 268 } 269 #endif /* unused */ 270 271 static inline uint32_t 272 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 273 { 274 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 275 } 276 277 static inline uint32_t 278 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 279 { 280 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 281 } 282 283 static inline void 284 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 285 uint32_t value) 286 { 287 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 288 } 289 290 static inline uint64_t 291 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 292 { 293 uint64_t value; 294 295 if (sc->sc_ac64) { 296 #ifdef XHCI_USE_BUS_SPACE_8 297 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 298 #else 299 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 300 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 301 offset + 4) << 32; 302 #endif 303 } else { 304 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 305 } 306 307 return value; 308 } 309 310 static inline void 311 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 312 uint64_t value) 313 { 314 if (sc->sc_ac64) { 315 #ifdef XHCI_USE_BUS_SPACE_8 316 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 317 #else 318 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 319 (value >> 0) & 0xffffffff); 320 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 321 (value >> 32) & 0xffffffff); 322 #endif 323 } else { 324 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 325 } 326 } 327 328 static inline uint32_t 329 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 330 { 331 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 332 } 333 334 static inline void 335 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 336 uint32_t value) 337 { 338 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 339 } 340 341 #if 0 /* unused */ 342 static inline uint64_t 343 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 344 { 345 uint64_t value; 346 347 if (sc->sc_ac64) { 348 #ifdef XHCI_USE_BUS_SPACE_8 349 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 350 #else 351 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 352 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 353 offset + 4) << 32; 354 #endif 355 } else { 356 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 357 } 358 359 return value; 360 } 361 #endif /* unused */ 362 363 static inline void 364 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 365 uint64_t value) 366 { 367 if (sc->sc_ac64) { 368 #ifdef XHCI_USE_BUS_SPACE_8 369 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 370 #else 371 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 372 (value >> 0) & 0xffffffff); 373 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 374 (value >> 32) & 0xffffffff); 375 #endif 376 } else { 377 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 378 } 379 } 380 381 #if 0 /* unused */ 382 static inline uint32_t 383 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 384 { 385 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 386 } 387 #endif /* unused */ 388 389 static inline void 390 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 391 uint32_t value) 392 { 393 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 394 } 395 396 /* --- */ 397 398 static inline uint8_t 399 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 400 { 401 u_int eptype = 0; 402 403 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 404 case UE_CONTROL: 405 eptype = 0x0; 406 break; 407 case UE_ISOCHRONOUS: 408 eptype = 0x1; 409 break; 410 case UE_BULK: 411 eptype = 0x2; 412 break; 413 case UE_INTERRUPT: 414 eptype = 0x3; 415 break; 416 } 417 418 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 419 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 420 return eptype | 0x4; 421 else 422 return eptype; 423 } 424 425 static u_int 426 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 427 { 428 /* xHCI 1.0 section 4.5.1 */ 429 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 430 u_int in = 0; 431 432 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 433 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 434 in = 1; 435 436 return epaddr * 2 + in; 437 } 438 439 static inline u_int 440 xhci_dci_to_ici(const u_int i) 441 { 442 return i + 1; 443 } 444 445 static inline void * 446 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 447 const u_int dci) 448 { 449 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 450 } 451 452 #if 0 /* unused */ 453 static inline bus_addr_t 454 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 455 const u_int dci) 456 { 457 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 458 } 459 #endif /* unused */ 460 461 static inline void * 462 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 463 const u_int ici) 464 { 465 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 466 } 467 468 static inline bus_addr_t 469 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 470 const u_int ici) 471 { 472 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 473 } 474 475 static inline struct xhci_trb * 476 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 477 { 478 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 479 } 480 481 static inline bus_addr_t 482 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 483 { 484 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 485 } 486 487 static inline void 488 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 489 uint32_t control) 490 { 491 trb->trb_0 = htole64(parameter); 492 trb->trb_2 = htole32(status); 493 trb->trb_3 = htole32(control); 494 } 495 496 static int 497 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 498 { 499 /* base address of TRBs */ 500 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 501 502 /* trb_0 range sanity check */ 503 if (trb_0 == 0 || trb_0 < trbp || 504 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 505 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 506 return 1; 507 } 508 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 509 return 0; 510 } 511 512 /* --- */ 513 514 void 515 xhci_childdet(device_t self, device_t child) 516 { 517 struct xhci_softc * const sc = device_private(self); 518 519 KASSERT(sc->sc_child == child); 520 if (child == sc->sc_child) 521 sc->sc_child = NULL; 522 } 523 524 int 525 xhci_detach(struct xhci_softc *sc, int flags) 526 { 527 int rv = 0; 528 529 if (sc->sc_child != NULL) 530 rv = config_detach(sc->sc_child, flags); 531 532 if (rv != 0) 533 return rv; 534 535 /* XXX unconfigure/free slots */ 536 537 /* verify: */ 538 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 539 xhci_op_write_4(sc, XHCI_USBCMD, 0); 540 /* do we need to wait for stop? */ 541 542 xhci_op_write_8(sc, XHCI_CRCR, 0); 543 xhci_ring_free(sc, &sc->sc_cr); 544 cv_destroy(&sc->sc_command_cv); 545 546 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 547 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 548 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 549 xhci_ring_free(sc, &sc->sc_er); 550 551 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 552 553 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 554 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 555 556 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 557 558 mutex_destroy(&sc->sc_lock); 559 mutex_destroy(&sc->sc_intr_lock); 560 cv_destroy(&sc->sc_softwake_cv); 561 562 pool_cache_destroy(sc->sc_xferpool); 563 564 return rv; 565 } 566 567 int 568 xhci_activate(device_t self, enum devact act) 569 { 570 struct xhci_softc * const sc = device_private(self); 571 572 switch (act) { 573 case DVACT_DEACTIVATE: 574 sc->sc_dying = true; 575 return 0; 576 default: 577 return EOPNOTSUPP; 578 } 579 } 580 581 bool 582 xhci_suspend(device_t dv, const pmf_qual_t *qual) 583 { 584 return false; 585 } 586 587 bool 588 xhci_resume(device_t dv, const pmf_qual_t *qual) 589 { 590 return false; 591 } 592 593 bool 594 xhci_shutdown(device_t self, int flags) 595 { 596 return false; 597 } 598 599 static int 600 xhci_hc_reset(struct xhci_softc * const sc) 601 { 602 uint32_t usbcmd, usbsts; 603 int i; 604 605 /* Check controller not ready */ 606 for (i = 0; i < XHCI_WAIT_CNR; i++) { 607 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 608 if ((usbsts & XHCI_STS_CNR) == 0) 609 break; 610 usb_delay_ms(&sc->sc_bus, 1); 611 } 612 if (i >= XHCI_WAIT_CNR) { 613 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 614 return EIO; 615 } 616 617 /* Halt controller */ 618 usbcmd = 0; 619 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 620 usb_delay_ms(&sc->sc_bus, 1); 621 622 /* Reset controller */ 623 usbcmd = XHCI_CMD_HCRST; 624 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 625 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 626 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 627 if ((usbcmd & XHCI_CMD_HCRST) == 0) 628 break; 629 usb_delay_ms(&sc->sc_bus, 1); 630 } 631 if (i >= XHCI_WAIT_HCRST) { 632 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 633 return EIO; 634 } 635 636 /* Check controller not ready */ 637 for (i = 0; i < XHCI_WAIT_CNR; i++) { 638 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 639 if ((usbsts & XHCI_STS_CNR) == 0) 640 break; 641 usb_delay_ms(&sc->sc_bus, 1); 642 } 643 if (i >= XHCI_WAIT_CNR) { 644 aprint_error_dev(sc->sc_dev, 645 "controller not ready timeout after reset\n"); 646 return EIO; 647 } 648 649 return 0; 650 } 651 652 653 static void 654 hexdump(const char *msg, const void *base, size_t len) 655 { 656 #if 0 657 size_t cnt; 658 const uint32_t *p; 659 extern paddr_t vtophys(vaddr_t); 660 661 p = base; 662 cnt = 0; 663 664 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 665 (void *)vtophys((vaddr_t)base)); 666 667 while (cnt < len) { 668 if (cnt % 16 == 0) 669 printf("%p: ", p); 670 else if (cnt % 8 == 0) 671 printf(" |"); 672 printf(" %08x", *p++); 673 cnt += 4; 674 if (cnt % 16 == 0) 675 printf("\n"); 676 } 677 if (cnt % 16 != 0) 678 printf("\n"); 679 #endif 680 } 681 682 /* Process extended capabilities */ 683 static void 684 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 685 { 686 uint32_t ecp, ecr; 687 688 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 689 690 ecp = XHCI_HCC_XECP(hcc) * 4; 691 while (ecp != 0) { 692 ecr = xhci_read_4(sc, ecp); 693 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 694 switch (XHCI_XECP_ID(ecr)) { 695 case XHCI_ID_PROTOCOLS: { 696 uint32_t w4, w8, wc; 697 uint16_t w2; 698 w2 = (ecr >> 16) & 0xffff; 699 w4 = xhci_read_4(sc, ecp + 4); 700 w8 = xhci_read_4(sc, ecp + 8); 701 wc = xhci_read_4(sc, ecp + 0xc); 702 aprint_debug_dev(sc->sc_dev, 703 " SP: %08x %08x %08x %08x\n", ecr, w4, w8, wc); 704 /* unused */ 705 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0300) { 706 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 707 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 708 } 709 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0200) { 710 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 711 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 712 } 713 break; 714 } 715 case XHCI_ID_USB_LEGACY: { 716 uint8_t bios_sem; 717 718 /* Take host controller ownership from BIOS */ 719 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 720 if (bios_sem) { 721 /* sets xHCI to be owned by OS */ 722 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 723 aprint_debug_dev(sc->sc_dev, 724 "waiting for BIOS to give up control\n"); 725 for (int i = 0; i < 5000; i++) { 726 bios_sem = xhci_read_1(sc, ecp + 727 XHCI_XECP_BIOS_SEM); 728 if (bios_sem == 0) 729 break; 730 DELAY(1000); 731 } 732 if (bios_sem) { 733 aprint_error_dev(sc->sc_dev, 734 "timed out waiting for BIOS\n"); 735 } 736 } 737 break; 738 } 739 default: 740 break; 741 } 742 ecr = xhci_read_4(sc, ecp); 743 if (XHCI_XECP_NEXT(ecr) == 0) { 744 ecp = 0; 745 } else { 746 ecp += XHCI_XECP_NEXT(ecr) * 4; 747 } 748 } 749 } 750 751 #define XHCI_HCCPREV1_BITS \ 752 "\177\020" /* New bitmask */ \ 753 "f\020\020XECP\0" \ 754 "f\014\4MAXPSA\0" \ 755 "b\013CFC\0" \ 756 "b\012SEC\0" \ 757 "b\011SBD\0" \ 758 "b\010FSE\0" \ 759 "b\7NSS\0" \ 760 "b\6LTC\0" \ 761 "b\5LHRC\0" \ 762 "b\4PIND\0" \ 763 "b\3PPC\0" \ 764 "b\2CZC\0" \ 765 "b\1BNC\0" \ 766 "b\0AC64\0" \ 767 "\0" 768 #define XHCI_HCCV1_x_BITS \ 769 "\177\020" /* New bitmask */ \ 770 "f\020\020XECP\0" \ 771 "f\014\4MAXPSA\0" \ 772 "b\013CFC\0" \ 773 "b\012SEC\0" \ 774 "b\011SPC\0" \ 775 "b\010PAE\0" \ 776 "b\7NSS\0" \ 777 "b\6LTC\0" \ 778 "b\5LHRC\0" \ 779 "b\4PIND\0" \ 780 "b\3PPC\0" \ 781 "b\2CSZ\0" \ 782 "b\1BNC\0" \ 783 "b\0AC64\0" \ 784 "\0" 785 786 int 787 xhci_init(struct xhci_softc *sc) 788 { 789 bus_size_t bsz; 790 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 791 uint32_t pagesize, config; 792 int i = 0; 793 uint16_t hciversion; 794 uint8_t caplength; 795 796 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 797 798 sc->sc_bus.ub_revision = USBREV_3_0; 799 sc->sc_bus.ub_usedma = true; 800 801 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 802 caplength = XHCI_CAP_CAPLENGTH(cap); 803 hciversion = XHCI_CAP_HCIVERSION(cap); 804 805 if (hciversion < XHCI_HCIVERSION_0_96 || 806 hciversion > XHCI_HCIVERSION_1_0) { 807 aprint_normal_dev(sc->sc_dev, 808 "xHCI version %x.%x not known to be supported\n", 809 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 810 } else { 811 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 812 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 813 } 814 815 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 816 &sc->sc_cbh) != 0) { 817 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 818 return ENOMEM; 819 } 820 821 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 822 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 823 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 824 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 825 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 826 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 827 aprint_debug_dev(sc->sc_dev, 828 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 829 830 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 831 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 832 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 833 834 char sbuf[128]; 835 if (hciversion < XHCI_HCIVERSION_1_0) 836 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 837 else 838 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 839 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 840 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 841 842 /* print PSI and take ownership from BIOS */ 843 xhci_ecp(sc, hcc); 844 845 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 846 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 847 &sc->sc_obh) != 0) { 848 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 849 return ENOMEM; 850 } 851 852 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 853 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 854 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 855 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 856 return ENOMEM; 857 } 858 859 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 860 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 861 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 862 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 863 return ENOMEM; 864 } 865 866 int rv; 867 rv = xhci_hc_reset(sc); 868 if (rv != 0) { 869 return rv; 870 } 871 872 if (sc->sc_vendor_init) 873 sc->sc_vendor_init(sc); 874 875 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 876 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 877 pagesize = ffs(pagesize); 878 if (pagesize == 0) { 879 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 880 return EIO; 881 } 882 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 883 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 884 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 885 (uint32_t)sc->sc_maxslots); 886 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 887 888 usbd_status err; 889 890 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 891 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 892 if (sc->sc_maxspbuf != 0) { 893 err = usb_allocmem(&sc->sc_bus, 894 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 895 &sc->sc_spbufarray_dma); 896 if (err) { 897 aprint_error_dev(sc->sc_dev, 898 "spbufarray init fail, err %d\n", err); 899 return ENOMEM; 900 } 901 902 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 903 sc->sc_maxspbuf, KM_SLEEP); 904 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 905 for (i = 0; i < sc->sc_maxspbuf; i++) { 906 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 907 /* allocate contexts */ 908 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 909 sc->sc_pgsz, dma); 910 if (err) { 911 aprint_error_dev(sc->sc_dev, 912 "spbufarray_dma init fail, err %d\n", err); 913 rv = ENOMEM; 914 goto bad1; 915 } 916 spbufarray[i] = htole64(DMAADDR(dma, 0)); 917 usb_syncmem(dma, 0, sc->sc_pgsz, 918 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 919 } 920 921 usb_syncmem(&sc->sc_spbufarray_dma, 0, 922 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 923 } 924 925 config = xhci_op_read_4(sc, XHCI_CONFIG); 926 config &= ~0xFF; 927 config |= sc->sc_maxslots & 0xFF; 928 xhci_op_write_4(sc, XHCI_CONFIG, config); 929 930 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 931 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 932 if (err) { 933 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 934 err); 935 rv = ENOMEM; 936 goto bad1; 937 } 938 939 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 940 XHCI_EVENT_RING_SEGMENTS_ALIGN); 941 if (err) { 942 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 943 err); 944 rv = ENOMEM; 945 goto bad2; 946 } 947 948 usb_dma_t *dma; 949 size_t size; 950 size_t align; 951 952 dma = &sc->sc_eventst_dma; 953 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 954 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 955 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 956 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 957 err = usb_allocmem(&sc->sc_bus, size, align, dma); 958 if (err) { 959 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 960 err); 961 rv = ENOMEM; 962 goto bad3; 963 } 964 965 memset(KERNADDR(dma, 0), 0, size); 966 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 967 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 968 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 969 KERNADDR(&sc->sc_eventst_dma, 0), 970 sc->sc_eventst_dma.udma_block->size); 971 972 dma = &sc->sc_dcbaa_dma; 973 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 974 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 975 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 976 err = usb_allocmem(&sc->sc_bus, size, align, dma); 977 if (err) { 978 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 979 rv = ENOMEM; 980 goto bad4; 981 } 982 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 983 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 984 KERNADDR(&sc->sc_dcbaa_dma, 0), 985 sc->sc_dcbaa_dma.udma_block->size); 986 987 memset(KERNADDR(dma, 0), 0, size); 988 if (sc->sc_maxspbuf != 0) { 989 /* 990 * DCBA entry 0 hold the scratchbuf array pointer. 991 */ 992 *(uint64_t *)KERNADDR(dma, 0) = 993 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 994 } 995 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 996 997 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 998 KM_SLEEP); 999 if (sc->sc_slots == NULL) { 1000 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1001 rv = ENOMEM; 1002 goto bad; 1003 } 1004 1005 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1006 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1007 if (sc->sc_xferpool == NULL) { 1008 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1009 err); 1010 rv = ENOMEM; 1011 goto bad; 1012 } 1013 1014 cv_init(&sc->sc_command_cv, "xhcicmd"); 1015 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1016 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1017 cv_init(&sc->sc_softwake_cv, "xhciab"); 1018 1019 /* Set up the bus struct. */ 1020 sc->sc_bus.ub_methods = &xhci_bus_methods; 1021 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 1022 1023 struct xhci_erste *erst; 1024 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1025 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1026 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 1027 erst[0].erste_3 = htole32(0); 1028 usb_syncmem(&sc->sc_eventst_dma, 0, 1029 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1030 1031 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1032 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1033 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1034 XHCI_ERDP_LO_BUSY); 1035 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1036 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1037 sc->sc_cr.xr_cs); 1038 1039 #if 0 1040 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1041 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1042 #endif 1043 1044 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1045 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1046 /* Intel xhci needs interrupt rate moderated. */ 1047 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1048 else 1049 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1050 aprint_debug_dev(sc->sc_dev, "setting IMOD %u\n", 1051 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1052 1053 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 1054 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1055 xhci_op_read_4(sc, XHCI_USBCMD)); 1056 1057 return 0; 1058 1059 bad: 1060 if (sc->sc_xferpool) { 1061 pool_cache_destroy(sc->sc_xferpool); 1062 sc->sc_xferpool = NULL; 1063 } 1064 1065 if (sc->sc_slots) { 1066 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1067 sc->sc_maxslots); 1068 sc->sc_slots = NULL; 1069 } 1070 1071 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1072 bad4: 1073 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1074 bad3: 1075 xhci_ring_free(sc, &sc->sc_er); 1076 bad2: 1077 xhci_ring_free(sc, &sc->sc_cr); 1078 i = sc->sc_maxspbuf; 1079 bad1: 1080 for (int j = 0; j < i; j++) 1081 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1082 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1083 1084 return rv; 1085 } 1086 1087 int 1088 xhci_intr(void *v) 1089 { 1090 struct xhci_softc * const sc = v; 1091 int ret = 0; 1092 1093 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1094 1095 if (sc == NULL) 1096 return 0; 1097 1098 mutex_spin_enter(&sc->sc_intr_lock); 1099 1100 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1101 goto done; 1102 1103 /* If we get an interrupt while polling, then just ignore it. */ 1104 if (sc->sc_bus.ub_usepolling) { 1105 #ifdef DIAGNOSTIC 1106 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1107 #endif 1108 goto done; 1109 } 1110 1111 ret = xhci_intr1(sc); 1112 done: 1113 mutex_spin_exit(&sc->sc_intr_lock); 1114 return ret; 1115 } 1116 1117 int 1118 xhci_intr1(struct xhci_softc * const sc) 1119 { 1120 uint32_t usbsts; 1121 uint32_t iman; 1122 1123 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1124 1125 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1126 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1127 #if 0 1128 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1129 return 0; 1130 } 1131 #endif 1132 xhci_op_write_4(sc, XHCI_USBSTS, 1133 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1134 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1135 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1136 1137 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1138 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1139 iman |= XHCI_IMAN_INTR_PEND; 1140 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1141 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1142 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1143 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1144 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1145 1146 usb_schedsoftintr(&sc->sc_bus); 1147 1148 return 1; 1149 } 1150 1151 /* 1152 * 3 port speed types used in USB stack 1153 * 1154 * usbdi speed 1155 * definition: USB_SPEED_* in usb.h 1156 * They are used in struct usbd_device in USB stack. 1157 * ioctl interface uses these values too. 1158 * port_status speed 1159 * definition: UPS_*_SPEED in usb.h 1160 * They are used in usb_port_status_t and valid only for USB 2.0. 1161 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1162 * of usb_port_status_ext_t indicates port speed. 1163 * Note that some 3.0 values overlap with 2.0 values. 1164 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1165 * means UPS_LOW_SPEED in HS.) 1166 * port status returned from hub also uses these values. 1167 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1168 * or more. 1169 * xspeed: 1170 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1171 * They are used in only slot context and PORTSC reg of xhci. 1172 * The difference between usbdi speed and xspeed is 1173 * that FS and LS values are swapped. 1174 */ 1175 1176 /* convert usbdi speed to xspeed */ 1177 static int 1178 xhci_speed2xspeed(int speed) 1179 { 1180 switch (speed) { 1181 case USB_SPEED_LOW: return 2; 1182 case USB_SPEED_FULL: return 1; 1183 default: return speed; 1184 } 1185 } 1186 1187 #if 0 1188 /* convert xspeed to usbdi speed */ 1189 static int 1190 xhci_xspeed2speed(int xspeed) 1191 { 1192 switch (xspeed) { 1193 case 1: return USB_SPEED_FULL; 1194 case 2: return USB_SPEED_LOW; 1195 default: return xspeed; 1196 } 1197 } 1198 #endif 1199 1200 /* convert xspeed to port status speed */ 1201 static int 1202 xhci_xspeed2psspeed(int xspeed) 1203 { 1204 switch (xspeed) { 1205 case 0: return 0; 1206 case 1: return UPS_FULL_SPEED; 1207 case 2: return UPS_LOW_SPEED; 1208 case 3: return UPS_HIGH_SPEED; 1209 default: return UPS_OTHER_SPEED; 1210 } 1211 } 1212 1213 /* construct slot context */ 1214 static void 1215 xhci_setup_sctx(struct usbd_device *dev, uint32_t *cp) 1216 { 1217 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 1218 int speed = dev->ud_speed; 1219 int tthubslot, ttportnum; 1220 bool ishub; 1221 bool usemtt; 1222 1223 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1224 1225 /* 1226 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 1227 * tthubslot: 1228 * This is the slot ID of parent HS hub 1229 * if LS/FS device is connected && connected through HS hub. 1230 * This is 0 if device is not LS/FS device || 1231 * parent hub is not HS hub || 1232 * attached to root hub. 1233 * ttportnum: 1234 * This is the downstream facing port of parent HS hub 1235 * if LS/FS device is connected. 1236 * This is 0 if device is not LS/FS device || 1237 * parent hub is not HS hub || 1238 * attached to root hub. 1239 */ 1240 if (dev->ud_myhsport != NULL && 1241 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1242 (dev->ud_myhub != NULL && 1243 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1244 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 1245 ttportnum = dev->ud_myhsport->up_portno; 1246 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 1247 } else { 1248 ttportnum = 0; 1249 tthubslot = 0; 1250 } 1251 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 1252 dev->ud_myhsport, ttportnum, tthubslot, 0); 1253 1254 /* ishub is valid after reading UDESC_DEVICE */ 1255 ishub = (dd->bDeviceClass == UDCLASS_HUB); 1256 1257 /* dev->ud_hub is valid after reading UDESC_HUB */ 1258 if (ishub && dev->ud_hub) { 1259 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 1260 1261 cp[1] |= htole32(XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts)); 1262 cp[2] |= htole32(XHCI_SCTX_2_TT_THINK_TIME_SET( 1263 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK))); 1264 DPRINTFN(4, "nports=%d ttt=%d", 1265 hd->bNbrPorts, XHCI_SCTX_2_TT_THINK_TIME_GET(cp[2]), 0, 0); 1266 } 1267 1268 #define IS_TTHUB(dd) \ 1269 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 1270 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 1271 1272 /* 1273 * MTT flag is set if 1274 * 1. this is HS hub && MTT is enabled 1275 * or 1276 * 2. this is not hub && this is LS or FS device && 1277 * MTT of parent HS hub (and its parent, too) is enabled 1278 */ 1279 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 1280 usemtt = true; 1281 else if (!ishub && 1282 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 1283 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1284 (dev->ud_myhub != NULL && 1285 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1286 dev->ud_myhsport != NULL && 1287 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 1288 usemtt = true; 1289 else 1290 usemtt = false; 1291 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 1292 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 1293 1294 cp[0] |= htole32( 1295 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)) | 1296 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 1297 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0) 1298 ); 1299 cp[1] |= htole32(0); 1300 cp[2] |= htole32( 1301 XHCI_SCTX_2_IRQ_TARGET_SET(0) | 1302 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 1303 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum) 1304 ); 1305 cp[3] |= htole32(0); 1306 } 1307 1308 static uint32_t 1309 xhci_get_maxburst(struct usbd_pipe *pipe) 1310 { 1311 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1312 usbd_desc_iter_t iter; 1313 const usb_cdc_descriptor_t *cdcd; 1314 const usb_endpoint_ss_comp_descriptor_t * esscd = NULL; 1315 uint32_t maxb = 0; 1316 uint8_t ep; 1317 1318 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc( 1319 pipe->up_dev, UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 1320 usb_desc_iter_init(pipe->up_dev, &iter); 1321 iter.cur = (const void *)cdcd; 1322 1323 /* find endpoint_ss_comp desc for ep of this pipe */ 1324 for (ep = 0;;) { 1325 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 1326 if (cdcd == NULL) 1327 break; 1328 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 1329 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 1330 bEndpointAddress; 1331 if (UE_GET_ADDR(ep) == 1332 UE_GET_ADDR(ed->bEndpointAddress)) { 1333 cdcd = (const usb_cdc_descriptor_t *) 1334 usb_desc_iter_next(&iter); 1335 break; 1336 } 1337 ep = 0; 1338 } 1339 } 1340 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 1341 esscd = (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 1342 maxb = esscd->bMaxBurst; 1343 } 1344 1345 return maxb; 1346 } 1347 1348 /* 1349 * Convert endpoint bInterval value to endpoint context interval value 1350 * for Interrupt pipe. 1351 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 1352 */ 1353 static uint32_t 1354 xhci_bival2ival(uint32_t ival, int speed) 1355 { 1356 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 1357 int i; 1358 1359 /* 1360 * round ival down to "the nearest base 2 multiple of 1361 * bInterval * 8". 1362 * bInterval is at most 255 as its type is uByte. 1363 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 1364 */ 1365 for (i = 10; i > 0; i--) { 1366 if ((ival * 8) >= (1 << i)) 1367 break; 1368 } 1369 ival = i; 1370 } else { 1371 /* Interval = bInterval-1 for SS/HS */ 1372 ival--; 1373 } 1374 1375 return ival; 1376 } 1377 1378 /* 1379 * 4.8.2, 6.2.3.2 1380 * construct common endpoint parameters 1381 */ 1382 static void 1383 xhci_setup_endp_ctx(struct usbd_pipe *pipe, uint32_t *cp) 1384 { 1385 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1386 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1387 const u_int dci = xhci_ep_get_dci(ed); 1388 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1389 uint32_t mps = UGETW(ed->wMaxPacketSize); 1390 uint32_t maxb = 0; 1391 int speed = pipe->up_dev->ud_speed; 1392 uint32_t ival = ed->bInterval; 1393 1394 cp[0] = htole32( 1395 XHCI_EPCTX_0_EPSTATE_SET(0) | 1396 XHCI_EPCTX_0_MULT_SET(0) | /* always 0 except SS iscoh */ 1397 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 1398 XHCI_EPCTX_0_LSA_SET(0) | 1399 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0) 1400 ); 1401 cp[1] = htole32( 1402 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 1403 XHCI_EPCTX_1_HID_SET(0) | 1404 XHCI_EPCTX_1_MAXB_SET(0) 1405 ); 1406 if (xfertype != UE_ISOCHRONOUS) 1407 cp[1] |= htole32(XHCI_EPCTX_1_CERR_SET(3)); 1408 1409 /* 6.2.3.4, 4.8.2.4 */ 1410 if (USB_IS_SS(speed)) { 1411 /* UBS 3.1 9.6.6 */ 1412 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1413 /* UBS 3.1 9.6.7 */ 1414 maxb = xhci_get_maxburst(pipe); 1415 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1416 } else { 1417 /* UBS 2.0 9.6.6 */ 1418 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps))); 1419 1420 /* 6.2.3.4 */ 1421 if (speed == USB_SPEED_HIGH && 1422 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 1423 maxb = UE_GET_TRANS(mps); 1424 } else { 1425 /* LS/FS or HS CTRL or HS BULK */ 1426 maxb = 0; 1427 } 1428 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1429 } 1430 1431 if (xfertype == UE_CONTROL) 1432 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(8)); /* 6.2.3 */ 1433 else if (USB_IS_SS(speed)) 1434 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps)); 1435 else 1436 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps))); 1437 1438 switch (xfertype) { 1439 case UE_CONTROL: 1440 break; 1441 case UE_BULK: 1442 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 1443 break; 1444 case UE_INTERRUPT: 1445 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1446 ival = pipe->up_interval; 1447 1448 ival = xhci_bival2ival(ival, speed); 1449 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1450 break; 1451 case UE_ISOCHRONOUS: 1452 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1453 ival = pipe->up_interval; 1454 1455 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 1456 if (speed == USB_SPEED_FULL) 1457 ival += 3; /* 1ms -> 125us */ 1458 ival--; 1459 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1460 1461 if (USB_IS_SS(speed)) { 1462 /* XXX if LEC = 1, set ESIT instead */ 1463 cp[0] |= htole32(XHCI_EPCTX_0_MULT_SET(0)); 1464 } 1465 break; 1466 default: 1467 break; 1468 } 1469 *(uint64_t *)(&cp[2]) = htole64( 1470 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 1471 XHCI_EPCTX_2_DCS_SET(1)); 1472 } 1473 1474 /* 1475 * Construct input contexts and issue TRB 1476 */ 1477 static usbd_status 1478 xhci_configure_endpoint(struct usbd_pipe *pipe) 1479 { 1480 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1481 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1482 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1483 struct xhci_trb trb; 1484 usbd_status err; 1485 uint32_t *cp; 1486 1487 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1488 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1489 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1490 pipe->up_endpoint->ue_edesc->bmAttributes); 1491 1492 /* XXX ensure input context is available? */ 1493 1494 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1495 1496 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1497 cp[0] = htole32(0); 1498 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 1499 1500 /* set up input slot context */ 1501 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1502 xhci_setup_sctx(pipe->up_dev, cp); 1503 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1504 1505 /* set up input endpoint context */ 1506 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 1507 xhci_setup_endp_ctx(pipe, cp); 1508 1509 /* sync input contexts before they are read from memory */ 1510 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1511 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1512 sc->sc_ctxsz * 1); 1513 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1514 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1515 1516 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1517 trb.trb_2 = 0; 1518 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1519 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1520 1521 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1522 1523 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1524 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1525 sc->sc_ctxsz * 1); 1526 1527 return err; 1528 } 1529 1530 #if 0 1531 static usbd_status 1532 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1533 { 1534 #ifdef USB_DEBUG 1535 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1536 #endif 1537 1538 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1539 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1540 1541 return USBD_NORMAL_COMPLETION; 1542 } 1543 #endif 1544 1545 /* 4.6.8, 6.4.3.7 */ 1546 static usbd_status 1547 xhci_reset_endpoint(struct usbd_pipe *pipe) 1548 { 1549 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1550 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1551 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1552 struct xhci_trb trb; 1553 usbd_status err; 1554 1555 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1556 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1557 1558 KASSERT(!mutex_owned(&sc->sc_lock)); 1559 1560 trb.trb_0 = 0; 1561 trb.trb_2 = 0; 1562 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1563 XHCI_TRB_3_EP_SET(dci) | 1564 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1565 1566 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1567 1568 return err; 1569 } 1570 1571 /* 1572 * 4.6.9, 6.4.3.8 1573 * Stop execution of TDs on xfer ring. 1574 * Should be called with sc_lock held. 1575 */ 1576 static usbd_status 1577 xhci_stop_endpoint(struct usbd_pipe *pipe) 1578 { 1579 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1580 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1581 struct xhci_trb trb; 1582 usbd_status err; 1583 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1584 1585 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1586 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1587 1588 KASSERT(mutex_owned(&sc->sc_lock)); 1589 1590 trb.trb_0 = 0; 1591 trb.trb_2 = 0; 1592 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1593 XHCI_TRB_3_EP_SET(dci) | 1594 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1595 1596 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1597 1598 return err; 1599 } 1600 1601 /* 1602 * Set TR Dequeue Pointer. 1603 * xCHI 1.1 4.6.10 6.4.3.9 1604 * Purge all of the transfer requests on ring. 1605 * EPSTATE of endpoint must be ERROR or STOPPED, or CONTEXT_STATE error. 1606 */ 1607 static usbd_status 1608 xhci_set_dequeue(struct usbd_pipe *pipe) 1609 { 1610 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1611 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1612 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1613 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1614 struct xhci_trb trb; 1615 usbd_status err; 1616 1617 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1618 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1619 1620 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1621 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1622 BUS_DMASYNC_PREWRITE); 1623 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1624 1625 xr->xr_ep = 0; 1626 xr->xr_cs = 1; 1627 1628 /* set DCS */ 1629 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1630 trb.trb_2 = 0; 1631 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1632 XHCI_TRB_3_EP_SET(dci) | 1633 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1634 1635 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1636 1637 return err; 1638 } 1639 1640 /* 1641 * Open new pipe: called from usbd_setup_pipe_flags. 1642 * Fills methods of pipe. 1643 * If pipe is not for ep0, calls configure_endpoint. 1644 */ 1645 static usbd_status 1646 xhci_open(struct usbd_pipe *pipe) 1647 { 1648 struct usbd_device * const dev = pipe->up_dev; 1649 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1650 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1651 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1652 1653 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1654 DPRINTFN(1, "addr %d depth %d port %d speed %d", 1655 dev->ud_addr, dev->ud_depth, dev->ud_powersrc->up_portno, 1656 dev->ud_speed); 1657 1658 if (sc->sc_dying) 1659 return USBD_IOERROR; 1660 1661 /* Root Hub */ 1662 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1663 switch (ed->bEndpointAddress) { 1664 case USB_CONTROL_ENDPOINT: 1665 pipe->up_methods = &roothub_ctrl_methods; 1666 break; 1667 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1668 pipe->up_methods = &xhci_root_intr_methods; 1669 break; 1670 default: 1671 pipe->up_methods = NULL; 1672 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1673 ed->bEndpointAddress, 0, 0, 0); 1674 return USBD_INVAL; 1675 } 1676 return USBD_NORMAL_COMPLETION; 1677 } 1678 1679 switch (xfertype) { 1680 case UE_CONTROL: 1681 pipe->up_methods = &xhci_device_ctrl_methods; 1682 break; 1683 case UE_ISOCHRONOUS: 1684 pipe->up_methods = &xhci_device_isoc_methods; 1685 return USBD_INVAL; 1686 break; 1687 case UE_BULK: 1688 pipe->up_methods = &xhci_device_bulk_methods; 1689 break; 1690 case UE_INTERRUPT: 1691 pipe->up_methods = &xhci_device_intr_methods; 1692 break; 1693 default: 1694 return USBD_IOERROR; 1695 break; 1696 } 1697 1698 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1699 return xhci_configure_endpoint(pipe); 1700 1701 return USBD_NORMAL_COMPLETION; 1702 } 1703 1704 /* 1705 * Closes pipe, called from usbd_kill_pipe via close methods. 1706 * If the endpoint to be closed is ep0, disable_slot. 1707 * Should be called with sc_lock held. 1708 */ 1709 static void 1710 xhci_close_pipe(struct usbd_pipe *pipe) 1711 { 1712 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1713 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1714 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1715 const u_int dci = xhci_ep_get_dci(ed); 1716 struct xhci_trb trb; 1717 uint32_t *cp; 1718 1719 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1720 1721 if (sc->sc_dying) 1722 return; 1723 1724 /* xs is uninitialized before xhci_init_slot */ 1725 if (xs == NULL || xs->xs_idx == 0) 1726 return; 1727 1728 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1729 1730 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1731 KASSERT(mutex_owned(&sc->sc_lock)); 1732 1733 if (pipe->up_dev->ud_depth == 0) 1734 return; 1735 1736 if (dci == XHCI_DCI_EP_CONTROL) { 1737 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1738 xhci_disable_slot(sc, xs->xs_idx); 1739 return; 1740 } 1741 1742 /* 1743 * This may fail in the case that xhci_close_pipe is called after 1744 * xhci_abort_xfer e.g. usbd_kill_pipe. 1745 */ 1746 (void)xhci_stop_endpoint(pipe); 1747 1748 /* 1749 * set appropriate bit to be dropped. 1750 * don't set DC bit to 1, otherwise all endpoints 1751 * would be deconfigured. 1752 */ 1753 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1754 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1755 cp[1] = htole32(0); 1756 1757 /* XXX should be most significant one, not dci? */ 1758 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1759 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1760 1761 /* sync input contexts before they are read from memory */ 1762 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1763 1764 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1765 trb.trb_2 = 0; 1766 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1767 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1768 1769 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1770 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1771 } 1772 1773 /* 1774 * Abort transfer. 1775 * Called with sc_lock held. 1776 * May be called from softintr context. 1777 */ 1778 static void 1779 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1780 { 1781 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1782 1783 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1784 DPRINTFN(4, "xfer %p pipe %p status %d", 1785 xfer, xfer->ux_pipe, status, 0); 1786 1787 KASSERT(mutex_owned(&sc->sc_lock)); 1788 1789 if (sc->sc_dying) { 1790 /* If we're dying, just do the software part. */ 1791 DPRINTFN(4, "dying", 0, 0, 0, 0); 1792 xfer->ux_status = status; /* make software ignore it */ 1793 callout_stop(&xfer->ux_callout); 1794 usb_transfer_complete(xfer); 1795 return; 1796 } 1797 1798 /* XXX need more stuff */ 1799 xfer->ux_status = status; 1800 callout_stop(&xfer->ux_callout); 1801 usb_transfer_complete(xfer); 1802 DPRINTFN(14, "end", 0, 0, 0, 0); 1803 1804 KASSERT(mutex_owned(&sc->sc_lock)); 1805 } 1806 1807 /* 1808 * Recover STALLed endpoint. 1809 * xHCI 1.1 sect 4.10.2.1 1810 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1811 * all transfers on transfer ring. 1812 * These are done in thread context asynchronously. 1813 */ 1814 static void 1815 xhci_clear_endpoint_stall_async_task(void *cookie) 1816 { 1817 struct usbd_xfer * const xfer = cookie; 1818 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1819 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1820 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1821 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1822 1823 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1824 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1825 1826 xhci_reset_endpoint(xfer->ux_pipe); 1827 xhci_set_dequeue(xfer->ux_pipe); 1828 1829 mutex_enter(&sc->sc_lock); 1830 tr->is_halted = false; 1831 usb_transfer_complete(xfer); 1832 mutex_exit(&sc->sc_lock); 1833 DPRINTFN(4, "ends", 0, 0, 0, 0); 1834 } 1835 1836 static usbd_status 1837 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1838 { 1839 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1840 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1841 1842 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1843 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1844 1845 if (sc->sc_dying) { 1846 return USBD_IOERROR; 1847 } 1848 1849 usb_init_task(&xp->xp_async_task, 1850 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1851 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1852 DPRINTFN(4, "ends", 0, 0, 0, 0); 1853 1854 return USBD_NORMAL_COMPLETION; 1855 } 1856 1857 /* Process roothub port status/change events and notify to uhub_intr. */ 1858 static void 1859 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1860 { 1861 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1862 uint8_t *p; 1863 1864 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1865 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1866 port, 0, 0); 1867 1868 if (xfer == NULL) 1869 return; 1870 1871 if (port > sc->sc_maxports) 1872 return; 1873 1874 p = xfer->ux_buf; 1875 memset(p, 0, xfer->ux_length); 1876 p[port/NBBY] |= 1 << (port%NBBY); 1877 xfer->ux_actlen = xfer->ux_length; 1878 xfer->ux_status = USBD_NORMAL_COMPLETION; 1879 usb_transfer_complete(xfer); 1880 } 1881 1882 /* Process Transfer Events */ 1883 static void 1884 xhci_event_transfer(struct xhci_softc * const sc, 1885 const struct xhci_trb * const trb) 1886 { 1887 uint64_t trb_0; 1888 uint32_t trb_2, trb_3; 1889 uint8_t trbcode; 1890 u_int slot, dci; 1891 struct xhci_slot *xs; 1892 struct xhci_ring *xr; 1893 struct xhci_xfer *xx; 1894 struct usbd_xfer *xfer; 1895 usbd_status err; 1896 1897 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1898 1899 trb_0 = le64toh(trb->trb_0); 1900 trb_2 = le32toh(trb->trb_2); 1901 trb_3 = le32toh(trb->trb_3); 1902 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1903 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1904 dci = XHCI_TRB_3_EP_GET(trb_3); 1905 xs = &sc->sc_slots[slot]; 1906 xr = &xs->xs_ep[dci].xe_tr; 1907 1908 /* sanity check */ 1909 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1910 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1911 1912 int idx = 0; 1913 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1914 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1915 DPRINTFN(0, "invalid trb_0 0x%"PRIx64, trb_0, 0, 0, 0); 1916 return; 1917 } 1918 xx = xr->xr_cookies[idx]; 1919 1920 /* 1921 * If endpoint is stopped between TDs, TRB pointer points at 1922 * next TRB, however, it is not put yet or is a garbage TRB. 1923 * That's why xr_cookies may be NULL or look like broken. 1924 * Note: this ev happens only when hciversion >= 1.0 or 1925 * hciversion == 0.96 and FSE of hcc1 is set. 1926 */ 1927 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1928 DPRINTFN(1, "xx NULL: #%u: cookie %p: code %u trb_0 %" 1929 PRIx64, idx, xx, trbcode, trb_0); 1930 } 1931 } else { 1932 /* When ED != 0, trb_0 is kaddr of struct xhci_xfer. */ 1933 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1934 } 1935 /* XXX this may not happen */ 1936 if (xx == NULL) { 1937 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1938 return; 1939 } 1940 xfer = &xx->xx_xfer; 1941 /* XXX this may happen when detaching */ 1942 if (xfer == NULL) { 1943 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1944 xx, trb_0, 0, 0); 1945 return; 1946 } 1947 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1948 /* XXX I dunno why this happens */ 1949 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1950 1951 if (!xfer->ux_pipe->up_repeat && 1952 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1953 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1954 return; 1955 } 1956 1957 /* 4.11.5.2 Event Data TRB */ 1958 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1959 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1960 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1961 if ((trb_0 & 0x3) == 0x3) { 1962 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1963 } 1964 } 1965 1966 switch (trbcode) { 1967 case XHCI_TRB_ERROR_SHORT_PKT: 1968 case XHCI_TRB_ERROR_SUCCESS: 1969 xfer->ux_actlen = 1970 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1971 err = USBD_NORMAL_COMPLETION; 1972 break; 1973 case XHCI_TRB_ERROR_STALL: 1974 case XHCI_TRB_ERROR_BABBLE: 1975 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1976 xr->is_halted = true; 1977 err = USBD_STALLED; 1978 /* 1979 * Stalled endpoints can be recoverd by issuing 1980 * command TRB TYPE_RESET_EP on xHCI instead of 1981 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1982 * on the endpoint. However, this function may be 1983 * called from softint context (e.g. from umass), 1984 * in that case driver gets KASSERT in cv_timedwait 1985 * in xhci_do_command. 1986 * To avoid this, this runs reset_endpoint and 1987 * usb_transfer_complete in usb task thread 1988 * asynchronously (and then umass issues clear 1989 * UF_ENDPOINT_HALT). 1990 */ 1991 xfer->ux_status = err; 1992 xhci_clear_endpoint_stall_async(xfer); 1993 return; 1994 default: 1995 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1996 err = USBD_IOERROR; 1997 break; 1998 } 1999 xfer->ux_status = err; 2000 2001 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 2002 if ((trb_0 & 0x3) == 0x0) { 2003 callout_stop(&xfer->ux_callout); 2004 usb_transfer_complete(xfer); 2005 } 2006 } else { 2007 callout_stop(&xfer->ux_callout); 2008 usb_transfer_complete(xfer); 2009 } 2010 } 2011 2012 /* Process Command complete events */ 2013 static void 2014 xhci_event_cmd(struct xhci_softc * const sc, 2015 const struct xhci_trb * const trb) 2016 { 2017 uint64_t trb_0; 2018 uint32_t trb_2, trb_3; 2019 2020 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2021 2022 trb_0 = le64toh(trb->trb_0); 2023 trb_2 = le32toh(trb->trb_2); 2024 trb_3 = le32toh(trb->trb_3); 2025 2026 if (trb_0 == sc->sc_command_addr) { 2027 sc->sc_result_trb.trb_0 = trb_0; 2028 sc->sc_result_trb.trb_2 = trb_2; 2029 sc->sc_result_trb.trb_3 = trb_3; 2030 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2031 XHCI_TRB_ERROR_SUCCESS) { 2032 DPRINTFN(1, "command completion " 2033 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 2034 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 2035 } 2036 cv_signal(&sc->sc_command_cv); 2037 } else { 2038 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 2039 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 2040 trb_2, trb_3); 2041 } 2042 } 2043 2044 /* 2045 * Process events. 2046 * called from xhci_softintr 2047 */ 2048 static void 2049 xhci_handle_event(struct xhci_softc * const sc, 2050 const struct xhci_trb * const trb) 2051 { 2052 uint64_t trb_0; 2053 uint32_t trb_2, trb_3; 2054 2055 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2056 2057 trb_0 = le64toh(trb->trb_0); 2058 trb_2 = le32toh(trb->trb_2); 2059 trb_3 = le32toh(trb->trb_3); 2060 2061 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2062 trb, trb_0, trb_2, trb_3); 2063 2064 /* 2065 * 4.11.3.1, 6.4.2.1 2066 * TRB Pointer is invalid for these completion codes. 2067 */ 2068 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2069 case XHCI_TRB_ERROR_RING_UNDERRUN: 2070 case XHCI_TRB_ERROR_RING_OVERRUN: 2071 case XHCI_TRB_ERROR_VF_RING_FULL: 2072 return; 2073 default: 2074 if (trb_0 == 0) { 2075 return; 2076 } 2077 break; 2078 } 2079 2080 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2081 case XHCI_TRB_EVENT_TRANSFER: 2082 xhci_event_transfer(sc, trb); 2083 break; 2084 case XHCI_TRB_EVENT_CMD_COMPLETE: 2085 xhci_event_cmd(sc, trb); 2086 break; 2087 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2088 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2089 break; 2090 default: 2091 break; 2092 } 2093 } 2094 2095 static void 2096 xhci_softintr(void *v) 2097 { 2098 struct usbd_bus * const bus = v; 2099 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2100 struct xhci_ring * const er = &sc->sc_er; 2101 struct xhci_trb *trb; 2102 int i, j, k; 2103 2104 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2105 2106 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2107 2108 i = er->xr_ep; 2109 j = er->xr_cs; 2110 2111 DPRINTFN(16, "xr_ep %d xr_cs %d", i, j, 0, 0); 2112 2113 while (1) { 2114 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2115 BUS_DMASYNC_POSTREAD); 2116 trb = &er->xr_trb[i]; 2117 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2118 2119 if (j != k) 2120 break; 2121 2122 xhci_handle_event(sc, trb); 2123 2124 i++; 2125 if (i == XHCI_EVENT_RING_TRBS) { 2126 i = 0; 2127 j ^= 1; 2128 } 2129 } 2130 2131 er->xr_ep = i; 2132 er->xr_cs = j; 2133 2134 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2135 XHCI_ERDP_LO_BUSY); 2136 2137 DPRINTFN(16, "ends", 0, 0, 0, 0); 2138 2139 return; 2140 } 2141 2142 static void 2143 xhci_poll(struct usbd_bus *bus) 2144 { 2145 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2146 2147 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2148 2149 mutex_spin_enter(&sc->sc_intr_lock); 2150 xhci_intr1(sc); 2151 mutex_spin_exit(&sc->sc_intr_lock); 2152 2153 return; 2154 } 2155 2156 static struct usbd_xfer * 2157 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2158 { 2159 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2160 struct usbd_xfer *xfer; 2161 2162 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2163 2164 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 2165 if (xfer != NULL) { 2166 memset(xfer, 0, sizeof(struct xhci_xfer)); 2167 #ifdef DIAGNOSTIC 2168 xfer->ux_state = XFER_BUSY; 2169 #endif 2170 } 2171 2172 return xfer; 2173 } 2174 2175 static void 2176 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2177 { 2178 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2179 2180 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2181 2182 #ifdef DIAGNOSTIC 2183 if (xfer->ux_state != XFER_BUSY) { 2184 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 2185 xfer, xfer->ux_state, 0, 0); 2186 } 2187 xfer->ux_state = XFER_FREE; 2188 #endif 2189 pool_cache_put(sc->sc_xferpool, xfer); 2190 } 2191 2192 static void 2193 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2194 { 2195 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2196 2197 *lock = &sc->sc_lock; 2198 } 2199 2200 extern uint32_t usb_cookie_no; 2201 2202 /* 2203 * xHCI 4.3 2204 * Called when uhub_explore finds a new device (via usbd_new_device). 2205 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2206 * This function does: 2207 * Allocate and construct dev structure of default endpoint (ep0). 2208 * Allocate and open pipe of ep0. 2209 * Enable slot and initialize slot context. 2210 * Set Address. 2211 * Read initial device descriptor. 2212 * Determine initial MaxPacketSize (mps) by speed. 2213 * Read full device descriptor. 2214 * Register this device. 2215 */ 2216 static usbd_status 2217 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2218 int speed, int port, struct usbd_port *up) 2219 { 2220 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2221 struct usbd_device *dev; 2222 usbd_status err; 2223 usb_device_descriptor_t *dd; 2224 struct usbd_device *hub; 2225 struct usbd_device *adev; 2226 int rhport = 0; 2227 struct xhci_slot *xs; 2228 uint32_t *cp; 2229 uint32_t route = 0; 2230 uint8_t slot = 0; 2231 uint8_t addr; 2232 2233 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2234 DPRINTFN(4, "port=%d depth=%d speed=%d upport %d", 2235 port, depth, speed, up->up_portno); 2236 2237 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2238 if (dev == NULL) 2239 return USBD_NOMEM; 2240 2241 dev->ud_bus = bus; 2242 2243 /* Set up default endpoint handle. */ 2244 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2245 2246 /* Set up default endpoint descriptor. */ 2247 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2248 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2249 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2250 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2251 /* 4.3, 4.8.2.1 */ 2252 switch (speed) { 2253 case USB_SPEED_SUPER: 2254 case USB_SPEED_SUPER_PLUS: 2255 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2256 break; 2257 case USB_SPEED_FULL: 2258 /* XXX using 64 as initial mps of ep0 in FS */ 2259 case USB_SPEED_HIGH: 2260 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2261 break; 2262 case USB_SPEED_LOW: 2263 default: 2264 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2265 break; 2266 } 2267 dev->ud_ep0desc.bInterval = 0; 2268 2269 /* doesn't matter, just don't let it uninitialized */ 2270 dev->ud_ep0.ue_toggle = 0; 2271 2272 DPRINTFN(4, "up %p portno %d", up, up->up_portno, 0, 0); 2273 2274 dev->ud_quirks = &usbd_no_quirk; 2275 dev->ud_addr = 0; 2276 dev->ud_ddesc.bMaxPacketSize = 0; 2277 dev->ud_depth = depth; 2278 dev->ud_powersrc = up; 2279 dev->ud_myhub = up->up_parent; 2280 2281 up->up_dev = dev; 2282 2283 /* Locate root hub port */ 2284 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2285 uint32_t dep; 2286 2287 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2288 hub, hub->ud_depth, hub->ud_powersrc, 2289 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2290 2291 if (hub->ud_powersrc == NULL) 2292 break; 2293 dep = hub->ud_depth; 2294 if (dep == 0) 2295 break; 2296 rhport = hub->ud_powersrc->up_portno; 2297 if (dep > USB_HUB_MAX_DEPTH) 2298 continue; 2299 2300 route |= 2301 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2302 << ((dep - 1) * 4); 2303 } 2304 route = route >> 4; 2305 DPRINTFN(4, "rhport %d Route %05x hub %p", rhport, route, hub, 0); 2306 2307 /* Locate port on upstream high speed hub */ 2308 for (adev = dev, hub = up->up_parent; 2309 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2310 adev = hub, hub = hub->ud_myhub) 2311 ; 2312 if (hub) { 2313 int p; 2314 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2315 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2316 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2317 goto found; 2318 } 2319 } 2320 panic("xhci_new_device: cannot find HS port"); 2321 found: 2322 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2323 } else { 2324 dev->ud_myhsport = NULL; 2325 } 2326 2327 dev->ud_speed = speed; 2328 dev->ud_langid = USBD_NOLANG; 2329 dev->ud_cookie.cookie = ++usb_cookie_no; 2330 2331 /* Establish the default pipe. */ 2332 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2333 &dev->ud_pipe0); 2334 if (err) { 2335 goto bad; 2336 } 2337 2338 dd = &dev->ud_ddesc; 2339 2340 if ((depth == 0) && (port == 0)) { 2341 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2342 bus->ub_devices[dev->ud_addr] = dev; 2343 err = usbd_get_initial_ddesc(dev, dd); 2344 if (err) 2345 goto bad; 2346 err = usbd_reload_device_desc(dev); 2347 if (err) 2348 goto bad; 2349 } else { 2350 err = xhci_enable_slot(sc, &slot); 2351 if (err) 2352 goto bad; 2353 xs = &sc->sc_slots[slot]; 2354 dev->ud_hcpriv = xs; 2355 err = xhci_init_slot(dev, slot, route, rhport); 2356 if (err) { 2357 dev->ud_hcpriv = NULL; 2358 /* 2359 * We have to disable_slot here because 2360 * xs->xs_idx == 0 when xhci_init_slot fails, 2361 * in that case usbd_remove_dev won't work. 2362 */ 2363 mutex_enter(&sc->sc_lock); 2364 xhci_disable_slot(sc, slot); 2365 mutex_exit(&sc->sc_lock); 2366 goto bad; 2367 } 2368 2369 /* Allow device time to set new address */ 2370 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2371 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2372 //hexdump("slot context", cp, sc->sc_ctxsz); 2373 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2374 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2375 /* XXX ensure we know when the hardware does something 2376 we can't yet cope with */ 2377 KASSERT(addr >= 1 && addr <= 127); 2378 dev->ud_addr = addr; 2379 /* XXX dev->ud_addr not necessarily unique on bus */ 2380 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2381 bus->ub_devices[dev->ud_addr] = dev; 2382 2383 err = usbd_get_initial_ddesc(dev, dd); 2384 if (err) 2385 goto bad; 2386 /* 4.8.2.1 */ 2387 if (USB_IS_SS(speed)) { 2388 if (dd->bMaxPacketSize != 9) { 2389 printf("%s: invalid mps 2^%u for SS ep0," 2390 " using 512\n", 2391 device_xname(sc->sc_dev), 2392 dd->bMaxPacketSize); 2393 dd->bMaxPacketSize = 9; 2394 } 2395 USETW(dev->ud_ep0desc.wMaxPacketSize, 2396 (1 << dd->bMaxPacketSize)); 2397 } else 2398 USETW(dev->ud_ep0desc.wMaxPacketSize, 2399 dd->bMaxPacketSize); 2400 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2401 xhci_update_ep0_mps(sc, xs, 2402 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2403 err = usbd_reload_device_desc(dev); 2404 if (err) 2405 goto bad; 2406 } 2407 2408 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2409 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2410 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2411 dd->bDeviceClass, dd->bDeviceSubClass, 2412 dd->bDeviceProtocol, 0); 2413 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2414 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2415 dev->ud_speed); 2416 2417 usbd_get_device_strings(dev); 2418 2419 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2420 2421 if ((depth == 0) && (port == 0)) { 2422 usbd_attach_roothub(parent, dev); 2423 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2424 return USBD_NORMAL_COMPLETION; 2425 } 2426 2427 2428 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2429 bad: 2430 if (err != USBD_NORMAL_COMPLETION) { 2431 usbd_remove_device(dev, up); 2432 } 2433 2434 return err; 2435 } 2436 2437 static usbd_status 2438 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2439 size_t ntrb, size_t align) 2440 { 2441 usbd_status err; 2442 size_t size = ntrb * XHCI_TRB_SIZE; 2443 2444 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2445 2446 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2447 if (err) 2448 return err; 2449 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2450 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2451 xr->xr_trb = xhci_ring_trbv(xr, 0); 2452 xr->xr_ntrb = ntrb; 2453 xr->xr_ep = 0; 2454 xr->xr_cs = 1; 2455 memset(xr->xr_trb, 0, size); 2456 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 2457 xr->is_halted = false; 2458 2459 return USBD_NORMAL_COMPLETION; 2460 } 2461 2462 static void 2463 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2464 { 2465 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2466 mutex_destroy(&xr->xr_lock); 2467 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2468 } 2469 2470 static void 2471 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2472 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2473 { 2474 size_t i; 2475 u_int ri; 2476 u_int cs; 2477 uint64_t parameter; 2478 uint32_t status; 2479 uint32_t control; 2480 2481 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2482 2483 KASSERT(ntrbs <= XHCI_XFER_NTRB); 2484 for (i = 0; i < ntrbs; i++) { 2485 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2486 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2487 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2488 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2489 XHCI_TRB_TYPE_LINK); 2490 } 2491 2492 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2493 2494 ri = xr->xr_ep; 2495 cs = xr->xr_cs; 2496 2497 /* 2498 * Although the xhci hardware can do scatter/gather dma from 2499 * arbitrary sized buffers, there is a non-obvious restriction 2500 * that a LINK trb is only allowed at the end of a burst of 2501 * transfers - which might be 16kB. 2502 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2503 * The simple solution is not to allow a LINK trb in the middle 2504 * of anything - as here. 2505 * XXX: (dsl) There are xhci controllers out there (eg some made by 2506 * ASMedia) that seem to lock up if they process a LINK trb but 2507 * cannot process the linked-to trb yet. 2508 * The code should write the 'cycle' bit on the link trb AFTER 2509 * adding the other trb. 2510 */ 2511 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2512 parameter = xhci_ring_trbp(xr, 0); 2513 status = 0; 2514 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2515 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2516 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2517 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2518 BUS_DMASYNC_PREWRITE); 2519 xr->xr_cookies[ri] = NULL; 2520 xr->xr_ep = 0; 2521 xr->xr_cs ^= 1; 2522 ri = xr->xr_ep; 2523 cs = xr->xr_cs; 2524 } 2525 2526 ri++; 2527 2528 /* Write any subsequent TRB first */ 2529 for (i = 1; i < ntrbs; i++) { 2530 parameter = trbs[i].trb_0; 2531 status = trbs[i].trb_2; 2532 control = trbs[i].trb_3; 2533 2534 if (cs) { 2535 control |= XHCI_TRB_3_CYCLE_BIT; 2536 } else { 2537 control &= ~XHCI_TRB_3_CYCLE_BIT; 2538 } 2539 2540 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2541 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2542 BUS_DMASYNC_PREWRITE); 2543 xr->xr_cookies[ri] = cookie; 2544 ri++; 2545 } 2546 2547 /* Write the first TRB last */ 2548 i = 0; 2549 parameter = trbs[i].trb_0; 2550 status = trbs[i].trb_2; 2551 control = trbs[i].trb_3; 2552 2553 if (xr->xr_cs) { 2554 control |= XHCI_TRB_3_CYCLE_BIT; 2555 } else { 2556 control &= ~XHCI_TRB_3_CYCLE_BIT; 2557 } 2558 2559 xhci_trb_put(&xr->xr_trb[xr->xr_ep], parameter, status, control); 2560 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2561 BUS_DMASYNC_PREWRITE); 2562 xr->xr_cookies[xr->xr_ep] = cookie; 2563 2564 xr->xr_ep = ri; 2565 xr->xr_cs = cs; 2566 2567 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2568 } 2569 2570 /* 2571 * Stop execution commands, purge all commands on command ring, and 2572 * rewind enqueue pointer. 2573 */ 2574 static void 2575 xhci_abort_command(struct xhci_softc *sc) 2576 { 2577 struct xhci_ring * const cr = &sc->sc_cr; 2578 uint64_t crcr; 2579 int i; 2580 2581 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2582 DPRINTFN(14, "command %#"PRIx64" timeout, aborting", 2583 sc->sc_command_addr, 0, 0, 0); 2584 2585 mutex_enter(&cr->xr_lock); 2586 2587 /* 4.6.1.2 Aborting a Command */ 2588 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2589 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2590 2591 for (i = 0; i < 500; i++) { 2592 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2593 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2594 break; 2595 usb_delay_ms(&sc->sc_bus, 1); 2596 } 2597 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2598 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2599 /* reset HC here? */ 2600 } 2601 2602 /* reset command ring dequeue pointer */ 2603 cr->xr_ep = 0; 2604 cr->xr_cs = 1; 2605 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2606 2607 mutex_exit(&cr->xr_lock); 2608 } 2609 2610 /* 2611 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2612 * Command completion is notified by cv_signal from xhci_handle_event 2613 * (called from interrupt from xHCI), or timed-out. 2614 * Command validation is performed in xhci_handle_event by checking if 2615 * trb_0 in CMD_COMPLETE TRB and sc->sc_command_addr are identical. 2616 */ 2617 static usbd_status 2618 xhci_do_command_locked(struct xhci_softc * const sc, struct xhci_trb * const trb, 2619 int timeout) 2620 { 2621 struct xhci_ring * const cr = &sc->sc_cr; 2622 usbd_status err; 2623 2624 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2625 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2626 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2627 2628 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2629 KASSERT(mutex_owned(&sc->sc_lock)); 2630 2631 /* XXX KASSERT may fire when cv_timedwait unlocks sc_lock */ 2632 KASSERT(sc->sc_command_addr == 0); 2633 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2634 2635 mutex_enter(&cr->xr_lock); 2636 xhci_ring_put(sc, cr, NULL, trb, 1); 2637 mutex_exit(&cr->xr_lock); 2638 2639 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2640 2641 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2642 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2643 xhci_abort_command(sc); 2644 err = USBD_TIMEOUT; 2645 goto timedout; 2646 } 2647 2648 trb->trb_0 = sc->sc_result_trb.trb_0; 2649 trb->trb_2 = sc->sc_result_trb.trb_2; 2650 trb->trb_3 = sc->sc_result_trb.trb_3; 2651 2652 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2653 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2654 2655 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2656 case XHCI_TRB_ERROR_SUCCESS: 2657 err = USBD_NORMAL_COMPLETION; 2658 break; 2659 default: 2660 case 192 ... 223: 2661 err = USBD_IOERROR; 2662 break; 2663 case 224 ... 255: 2664 err = USBD_NORMAL_COMPLETION; 2665 break; 2666 } 2667 2668 timedout: 2669 sc->sc_command_addr = 0; 2670 return err; 2671 } 2672 2673 static usbd_status 2674 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2675 int timeout) 2676 { 2677 2678 mutex_enter(&sc->sc_lock); 2679 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2680 mutex_exit(&sc->sc_lock); 2681 2682 return ret; 2683 } 2684 2685 static usbd_status 2686 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2687 { 2688 struct xhci_trb trb; 2689 usbd_status err; 2690 2691 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2692 2693 trb.trb_0 = 0; 2694 trb.trb_2 = 0; 2695 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2696 2697 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2698 if (err != USBD_NORMAL_COMPLETION) { 2699 return err; 2700 } 2701 2702 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2703 2704 return err; 2705 } 2706 2707 /* 2708 * xHCI 4.6.4 2709 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2710 * All endpoints in the slot should be stopped. 2711 * Should be called with sc_lock held. 2712 */ 2713 static usbd_status 2714 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2715 { 2716 struct xhci_trb trb; 2717 struct xhci_slot *xs; 2718 usbd_status err; 2719 2720 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2721 2722 if (sc->sc_dying) 2723 return USBD_IOERROR; 2724 2725 trb.trb_0 = 0; 2726 trb.trb_2 = 0; 2727 trb.trb_3 = htole32( 2728 XHCI_TRB_3_SLOT_SET(slot) | 2729 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2730 2731 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2732 2733 if (!err) { 2734 xs = &sc->sc_slots[slot]; 2735 if (xs->xs_idx != 0) { 2736 for (int i = XHCI_DCI_SLOT + 1; i < 32; i++) { 2737 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2738 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2739 } 2740 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2741 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2742 xhci_set_dcba(sc, 0, slot); 2743 memset(xs, 0, sizeof(*xs)); 2744 } 2745 } 2746 2747 return err; 2748 } 2749 2750 /* 2751 * Set address of device and transition slot state from ENABLED to ADDRESSED 2752 * if Block Setaddress Request (BSR) is false. 2753 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2754 * see xHCI 1.1 4.5.3, 3.3.4 2755 * Should be called without sc_lock held. 2756 */ 2757 static usbd_status 2758 xhci_address_device(struct xhci_softc * const sc, 2759 uint64_t icp, uint8_t slot_id, bool bsr) 2760 { 2761 struct xhci_trb trb; 2762 usbd_status err; 2763 2764 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2765 2766 trb.trb_0 = icp; 2767 trb.trb_2 = 0; 2768 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2769 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2770 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2771 2772 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2773 2774 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2775 err = USBD_NO_ADDR; 2776 2777 return err; 2778 } 2779 2780 static usbd_status 2781 xhci_update_ep0_mps(struct xhci_softc * const sc, 2782 struct xhci_slot * const xs, u_int mps) 2783 { 2784 struct xhci_trb trb; 2785 usbd_status err; 2786 uint32_t * cp; 2787 2788 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2789 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2790 2791 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2792 cp[0] = htole32(0); 2793 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2794 2795 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2796 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2797 2798 /* sync input contexts before they are read from memory */ 2799 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2800 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2801 sc->sc_ctxsz * 4); 2802 2803 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2804 trb.trb_2 = 0; 2805 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2806 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2807 2808 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2809 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2810 return err; 2811 } 2812 2813 static void 2814 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2815 { 2816 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2817 2818 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2819 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2820 &dcbaa[si], dcba, si, 0); 2821 2822 dcbaa[si] = htole64(dcba); 2823 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2824 BUS_DMASYNC_PREWRITE); 2825 } 2826 2827 /* 2828 * Allocate DMA buffer and ring buffer for specified slot 2829 * and set Device Context Base Address 2830 * and issue Set Address device command. 2831 */ 2832 static usbd_status 2833 xhci_init_slot(struct usbd_device *dev, uint32_t slot, uint32_t route, int rhport) 2834 { 2835 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2836 struct xhci_slot *xs; 2837 usbd_status err; 2838 u_int dci; 2839 uint32_t *cp; 2840 uint32_t mps = UGETW(dev->ud_ep0desc.wMaxPacketSize); 2841 2842 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2843 DPRINTFN(4, "slot %u speed %d route %05x rhport %d", 2844 slot, dev->ud_speed, route, rhport); 2845 2846 xs = &sc->sc_slots[slot]; 2847 2848 /* allocate contexts */ 2849 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2850 &xs->xs_dc_dma); 2851 if (err) 2852 return err; 2853 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2854 2855 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2856 &xs->xs_ic_dma); 2857 if (err) 2858 goto bad1; 2859 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2860 2861 for (dci = 0; dci < 32; dci++) { 2862 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2863 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2864 if (dci == XHCI_DCI_SLOT) 2865 continue; 2866 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2867 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2868 if (err) { 2869 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2870 goto bad2; 2871 } 2872 } 2873 2874 /* set up initial input control context */ 2875 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2876 cp[0] = htole32(0); 2877 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 2878 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2879 2880 /* set up input slot context */ 2881 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2882 xhci_setup_sctx(dev, cp); 2883 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(1)); 2884 cp[0] |= htole32(XHCI_SCTX_0_ROUTE_SET(route)); 2885 cp[1] |= htole32(XHCI_SCTX_1_RH_PORT_SET(rhport)); 2886 2887 /* set up input EP0 context */ 2888 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2889 cp[0] = htole32(0); 2890 cp[1] = htole32( 2891 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 2892 XHCI_EPCTX_1_EPTYPE_SET(4) | 2893 XHCI_EPCTX_1_CERR_SET(3) 2894 ); 2895 /* can't use xhci_ep_get_dci() yet? */ 2896 *(uint64_t *)(&cp[2]) = htole64( 2897 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 2898 XHCI_EPCTX_2_DCS_SET(1)); 2899 cp[4] = htole32( 2900 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 2901 ); 2902 2903 /* sync input contexts before they are read from memory */ 2904 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2905 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2906 sc->sc_ctxsz * 3); 2907 2908 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2909 2910 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 2911 false); 2912 2913 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2914 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2915 sc->sc_ctxsz * 2); 2916 2917 bad2: 2918 if (err == USBD_NORMAL_COMPLETION) { 2919 xs->xs_idx = slot; 2920 } else { 2921 for (int i = 1; i < dci; i++) { 2922 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2923 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2924 } 2925 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2926 bad1: 2927 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2928 xs->xs_idx = 0; 2929 } 2930 2931 return err; 2932 } 2933 2934 /* ----- */ 2935 2936 static void 2937 xhci_noop(struct usbd_pipe *pipe) 2938 { 2939 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2940 } 2941 2942 /* 2943 * Process root hub request. 2944 */ 2945 static int 2946 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2947 void *buf, int buflen) 2948 { 2949 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2950 usb_port_status_t ps; 2951 int l, totlen = 0; 2952 uint16_t len, value, index; 2953 int port, i; 2954 uint32_t v; 2955 2956 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2957 2958 if (sc->sc_dying) 2959 return -1; 2960 2961 len = UGETW(req->wLength); 2962 value = UGETW(req->wValue); 2963 index = UGETW(req->wIndex); 2964 2965 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 2966 req->bmRequestType | (req->bRequest << 8), value, index, len); 2967 2968 #define C(x,y) ((x) | ((y) << 8)) 2969 switch (C(req->bRequest, req->bmRequestType)) { 2970 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2971 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 2972 if (len == 0) 2973 break; 2974 switch (value) { 2975 case C(0, UDESC_DEVICE): { 2976 usb_device_descriptor_t devd; 2977 totlen = min(buflen, sizeof(devd)); 2978 memcpy(&devd, buf, totlen); 2979 USETW(devd.idVendor, sc->sc_id_vendor); 2980 memcpy(buf, &devd, totlen); 2981 break; 2982 } 2983 #define sd ((usb_string_descriptor_t *)buf) 2984 case C(1, UDESC_STRING): 2985 /* Vendor */ 2986 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2987 break; 2988 case C(2, UDESC_STRING): 2989 /* Product */ 2990 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 2991 break; 2992 #undef sd 2993 default: 2994 /* default from usbroothub */ 2995 return buflen; 2996 } 2997 break; 2998 2999 /* Hub requests */ 3000 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3001 break; 3002 /* Clear Port Feature request */ 3003 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3004 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 3005 index, value, 0, 0); 3006 if (index < 1 || index > sc->sc_maxports) { 3007 return -1; 3008 } 3009 port = XHCI_PORTSC(index); 3010 v = xhci_op_read_4(sc, port); 3011 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3012 v &= ~XHCI_PS_CLEAR; 3013 switch (value) { 3014 case UHF_PORT_ENABLE: 3015 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3016 break; 3017 case UHF_PORT_SUSPEND: 3018 return -1; 3019 case UHF_PORT_POWER: 3020 break; 3021 case UHF_PORT_TEST: 3022 case UHF_PORT_INDICATOR: 3023 return -1; 3024 case UHF_C_PORT_CONNECTION: 3025 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3026 break; 3027 case UHF_C_PORT_ENABLE: 3028 case UHF_C_PORT_SUSPEND: 3029 case UHF_C_PORT_OVER_CURRENT: 3030 return -1; 3031 case UHF_C_BH_PORT_RESET: 3032 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3033 break; 3034 case UHF_C_PORT_RESET: 3035 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3036 break; 3037 case UHF_C_PORT_LINK_STATE: 3038 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3039 break; 3040 case UHF_C_PORT_CONFIG_ERROR: 3041 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3042 break; 3043 default: 3044 return -1; 3045 } 3046 break; 3047 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3048 if (len == 0) 3049 break; 3050 if ((value & 0xff) != 0) { 3051 return -1; 3052 } 3053 usb_hub_descriptor_t hubd; 3054 3055 totlen = min(buflen, sizeof(hubd)); 3056 memcpy(&hubd, buf, totlen); 3057 hubd.bNbrPorts = sc->sc_maxports; 3058 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3059 hubd.bPwrOn2PwrGood = 200; 3060 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 3061 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 3062 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3063 totlen = min(totlen, hubd.bDescLength); 3064 memcpy(buf, &hubd, totlen); 3065 break; 3066 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3067 if (len != 4) { 3068 return -1; 3069 } 3070 memset(buf, 0, len); /* ? XXX */ 3071 totlen = len; 3072 break; 3073 /* Get Port Status request */ 3074 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3075 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 3076 if (index < 1 || index > sc->sc_maxports) { 3077 return -1; 3078 } 3079 if (len != 4) { 3080 return -1; 3081 } 3082 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 3083 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 3084 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3085 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3086 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3087 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3088 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3089 if (v & XHCI_PS_PR) i |= UPS_RESET; 3090 if (v & XHCI_PS_PP) { 3091 if (i & UPS_OTHER_SPEED) 3092 i |= UPS_PORT_POWER_SS; 3093 else 3094 i |= UPS_PORT_POWER; 3095 } 3096 if (i & UPS_OTHER_SPEED) 3097 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3098 if (sc->sc_vendor_port_status) 3099 i = sc->sc_vendor_port_status(sc, v, i); 3100 USETW(ps.wPortStatus, i); 3101 i = 0; 3102 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3103 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3104 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3105 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3106 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3107 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3108 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3109 USETW(ps.wPortChange, i); 3110 totlen = min(len, sizeof(ps)); 3111 memcpy(buf, &ps, totlen); 3112 break; 3113 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3114 return -1; 3115 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3116 break; 3117 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3118 break; 3119 /* Set Port Feature request */ 3120 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3121 int optval = (index >> 8) & 0xff; 3122 index &= 0xff; 3123 if (index < 1 || index > sc->sc_maxports) { 3124 return -1; 3125 } 3126 port = XHCI_PORTSC(index); 3127 v = xhci_op_read_4(sc, port); 3128 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3129 v &= ~XHCI_PS_CLEAR; 3130 switch (value) { 3131 case UHF_PORT_ENABLE: 3132 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3133 break; 3134 case UHF_PORT_SUSPEND: 3135 /* XXX suspend */ 3136 break; 3137 case UHF_PORT_RESET: 3138 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3139 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3140 /* Wait for reset to complete. */ 3141 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3142 if (sc->sc_dying) { 3143 return -1; 3144 } 3145 v = xhci_op_read_4(sc, port); 3146 if (v & XHCI_PS_PR) { 3147 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3148 usb_delay_ms(&sc->sc_bus, 10); 3149 /* XXX */ 3150 } 3151 break; 3152 case UHF_PORT_POWER: 3153 /* XXX power control */ 3154 break; 3155 /* XXX more */ 3156 case UHF_C_PORT_RESET: 3157 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3158 break; 3159 case UHF_PORT_U1_TIMEOUT: 3160 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3161 return -1; 3162 } 3163 port = XHCI_PORTPMSC(index); 3164 v = xhci_op_read_4(sc, port); 3165 v &= ~XHCI_PM3_U1TO_SET(0xff); 3166 v |= XHCI_PM3_U1TO_SET(optval); 3167 xhci_op_write_4(sc, port, v); 3168 break; 3169 case UHF_PORT_U2_TIMEOUT: 3170 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3171 return -1; 3172 } 3173 port = XHCI_PORTPMSC(index); 3174 v = xhci_op_read_4(sc, port); 3175 v &= ~XHCI_PM3_U2TO_SET(0xff); 3176 v |= XHCI_PM3_U2TO_SET(optval); 3177 xhci_op_write_4(sc, port, v); 3178 break; 3179 default: 3180 return -1; 3181 } 3182 } 3183 break; 3184 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3185 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3186 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3187 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3188 break; 3189 default: 3190 /* default from usbroothub */ 3191 return buflen; 3192 } 3193 3194 return totlen; 3195 } 3196 3197 /* root hub interrupt */ 3198 3199 static usbd_status 3200 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3201 { 3202 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3203 usbd_status err; 3204 3205 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3206 3207 /* Insert last in queue. */ 3208 mutex_enter(&sc->sc_lock); 3209 err = usb_insert_transfer(xfer); 3210 mutex_exit(&sc->sc_lock); 3211 if (err) 3212 return err; 3213 3214 /* Pipe isn't running, start first */ 3215 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3216 } 3217 3218 /* Wait for roothub port status/change */ 3219 static usbd_status 3220 xhci_root_intr_start(struct usbd_xfer *xfer) 3221 { 3222 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3223 3224 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3225 3226 if (sc->sc_dying) 3227 return USBD_IOERROR; 3228 3229 mutex_enter(&sc->sc_lock); 3230 sc->sc_intrxfer = xfer; 3231 mutex_exit(&sc->sc_lock); 3232 3233 return USBD_IN_PROGRESS; 3234 } 3235 3236 static void 3237 xhci_root_intr_abort(struct usbd_xfer *xfer) 3238 { 3239 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3240 3241 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3242 3243 KASSERT(mutex_owned(&sc->sc_lock)); 3244 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3245 3246 sc->sc_intrxfer = NULL; 3247 3248 xfer->ux_status = USBD_CANCELLED; 3249 usb_transfer_complete(xfer); 3250 } 3251 3252 static void 3253 xhci_root_intr_close(struct usbd_pipe *pipe) 3254 { 3255 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3256 3257 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3258 3259 KASSERT(mutex_owned(&sc->sc_lock)); 3260 3261 sc->sc_intrxfer = NULL; 3262 } 3263 3264 static void 3265 xhci_root_intr_done(struct usbd_xfer *xfer) 3266 { 3267 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3268 3269 } 3270 3271 /* -------------- */ 3272 /* device control */ 3273 3274 static usbd_status 3275 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3276 { 3277 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3278 usbd_status err; 3279 3280 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3281 3282 /* Insert last in queue. */ 3283 mutex_enter(&sc->sc_lock); 3284 err = usb_insert_transfer(xfer); 3285 mutex_exit(&sc->sc_lock); 3286 if (err) 3287 return err; 3288 3289 /* Pipe isn't running, start first */ 3290 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3291 } 3292 3293 static usbd_status 3294 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3295 { 3296 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3297 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3298 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3299 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3300 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3301 usb_device_request_t * const req = &xfer->ux_request; 3302 const int isread = usbd_xfer_isread(xfer); 3303 const uint32_t len = UGETW(req->wLength); 3304 usb_dma_t * const dma = &xfer->ux_dmabuf; 3305 uint64_t parameter; 3306 uint32_t status; 3307 uint32_t control; 3308 u_int i; 3309 3310 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3311 DPRINTFN(12, "req: %04x %04x %04x %04x", 3312 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3313 UGETW(req->wIndex), UGETW(req->wLength)); 3314 3315 /* we rely on the bottom bits for extra info */ 3316 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 3317 3318 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3319 3320 i = 0; 3321 3322 /* setup phase */ 3323 memcpy(¶meter, req, sizeof(*req)); 3324 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3325 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3326 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3327 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3328 XHCI_TRB_3_IDT_BIT; 3329 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3330 3331 if (len != 0) { 3332 /* data phase */ 3333 parameter = DMAADDR(dma, 0); 3334 KASSERT(len <= 0x10000); 3335 status = XHCI_TRB_2_IRQ_SET(0) | 3336 XHCI_TRB_2_TDSZ_SET(1) | 3337 XHCI_TRB_2_BYTES_SET(len); 3338 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3339 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3340 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3341 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3342 3343 parameter = (uintptr_t)xfer | 0x3; 3344 status = XHCI_TRB_2_IRQ_SET(0); 3345 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3346 XHCI_TRB_3_IOC_BIT; 3347 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3348 } 3349 3350 parameter = 0; 3351 status = XHCI_TRB_2_IRQ_SET(0); 3352 /* the status stage has inverted direction */ 3353 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3354 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3355 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3356 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3357 3358 parameter = (uintptr_t)xfer | 0x0; 3359 status = XHCI_TRB_2_IRQ_SET(0); 3360 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3361 XHCI_TRB_3_IOC_BIT; 3362 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3363 3364 mutex_enter(&tr->xr_lock); 3365 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3366 mutex_exit(&tr->xr_lock); 3367 3368 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3369 3370 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3371 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3372 xhci_timeout, xfer); 3373 } 3374 3375 if (sc->sc_bus.ub_usepolling) { 3376 DPRINTFN(1, "polling", 0, 0, 0, 0); 3377 //xhci_waitintr(sc, xfer); 3378 } 3379 3380 return USBD_IN_PROGRESS; 3381 } 3382 3383 static void 3384 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3385 { 3386 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3387 usb_device_request_t *req = &xfer->ux_request; 3388 int len = UGETW(req->wLength); 3389 int rd = req->bmRequestType & UT_READ; 3390 3391 if (len) 3392 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3393 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3394 } 3395 3396 static void 3397 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3398 { 3399 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3400 3401 xhci_abort_xfer(xfer, USBD_CANCELLED); 3402 } 3403 3404 static void 3405 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3406 { 3407 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3408 3409 xhci_close_pipe(pipe); 3410 } 3411 3412 /* ------------------ */ 3413 /* device isochronous */ 3414 3415 /* ----------- */ 3416 /* device bulk */ 3417 3418 static usbd_status 3419 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3420 { 3421 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3422 usbd_status err; 3423 3424 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3425 3426 /* Insert last in queue. */ 3427 mutex_enter(&sc->sc_lock); 3428 err = usb_insert_transfer(xfer); 3429 mutex_exit(&sc->sc_lock); 3430 if (err) 3431 return err; 3432 3433 /* 3434 * Pipe isn't running (otherwise err would be USBD_INPROG), 3435 * so start it first. 3436 */ 3437 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3438 } 3439 3440 static usbd_status 3441 xhci_device_bulk_start(struct usbd_xfer *xfer) 3442 { 3443 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3444 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3445 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3446 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3447 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3448 const uint32_t len = xfer->ux_length; 3449 usb_dma_t * const dma = &xfer->ux_dmabuf; 3450 uint64_t parameter; 3451 uint32_t status; 3452 uint32_t control; 3453 u_int i = 0; 3454 3455 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3456 3457 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3458 3459 if (sc->sc_dying) 3460 return USBD_IOERROR; 3461 3462 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3463 3464 parameter = DMAADDR(dma, 0); 3465 /* 3466 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3467 * If the user supplied buffer crosses such a boundary then 2 3468 * (or more) TRB should be used. 3469 * If multiple TRB are used the td_size field must be set correctly. 3470 * For v1.0 devices (like ivy bridge) this is the number of usb data 3471 * blocks needed to complete the transfer. 3472 * Setting it to 1 in the last TRB causes an extra zero-length 3473 * data block be sent. 3474 * The earlier documentation differs, I don't know how it behaves. 3475 */ 3476 KASSERT(len <= 0x10000); 3477 status = XHCI_TRB_2_IRQ_SET(0) | 3478 XHCI_TRB_2_TDSZ_SET(1) | 3479 XHCI_TRB_2_BYTES_SET(len); 3480 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3481 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3482 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3483 3484 mutex_enter(&tr->xr_lock); 3485 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3486 mutex_exit(&tr->xr_lock); 3487 3488 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3489 3490 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3491 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3492 xhci_timeout, xfer); 3493 } 3494 3495 if (sc->sc_bus.ub_usepolling) { 3496 DPRINTFN(1, "polling", 0, 0, 0, 0); 3497 //xhci_waitintr(sc, xfer); 3498 } 3499 3500 return USBD_IN_PROGRESS; 3501 } 3502 3503 static void 3504 xhci_device_bulk_done(struct usbd_xfer *xfer) 3505 { 3506 #ifdef USB_DEBUG 3507 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3508 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3509 #endif 3510 const int isread = usbd_xfer_isread(xfer); 3511 3512 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3513 3514 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3515 3516 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3517 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3518 } 3519 3520 static void 3521 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3522 { 3523 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3524 3525 xhci_abort_xfer(xfer, USBD_CANCELLED); 3526 } 3527 3528 static void 3529 xhci_device_bulk_close(struct usbd_pipe *pipe) 3530 { 3531 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3532 3533 xhci_close_pipe(pipe); 3534 } 3535 3536 /* ---------------- */ 3537 /* device interrupt */ 3538 3539 static usbd_status 3540 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3541 { 3542 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3543 usbd_status err; 3544 3545 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3546 3547 /* Insert last in queue. */ 3548 mutex_enter(&sc->sc_lock); 3549 err = usb_insert_transfer(xfer); 3550 mutex_exit(&sc->sc_lock); 3551 if (err) 3552 return err; 3553 3554 /* 3555 * Pipe isn't running (otherwise err would be USBD_INPROG), 3556 * so start it first. 3557 */ 3558 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3559 } 3560 3561 static usbd_status 3562 xhci_device_intr_start(struct usbd_xfer *xfer) 3563 { 3564 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3565 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3566 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3567 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3568 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3569 const uint32_t len = xfer->ux_length; 3570 usb_dma_t * const dma = &xfer->ux_dmabuf; 3571 uint64_t parameter; 3572 uint32_t status; 3573 uint32_t control; 3574 u_int i = 0; 3575 3576 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3577 3578 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3579 3580 if (sc->sc_dying) 3581 return USBD_IOERROR; 3582 3583 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3584 3585 parameter = DMAADDR(dma, 0); 3586 KASSERT(len <= 0x10000); 3587 status = XHCI_TRB_2_IRQ_SET(0) | 3588 XHCI_TRB_2_TDSZ_SET(1) | 3589 XHCI_TRB_2_BYTES_SET(len); 3590 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3591 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3592 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3593 3594 mutex_enter(&tr->xr_lock); 3595 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3596 mutex_exit(&tr->xr_lock); 3597 3598 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3599 3600 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3601 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3602 xhci_timeout, xfer); 3603 } 3604 3605 if (sc->sc_bus.ub_usepolling) { 3606 DPRINTFN(1, "polling", 0, 0, 0, 0); 3607 //xhci_waitintr(sc, xfer); 3608 } 3609 3610 return USBD_IN_PROGRESS; 3611 } 3612 3613 static void 3614 xhci_device_intr_done(struct usbd_xfer *xfer) 3615 { 3616 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3617 #ifdef USB_DEBUG 3618 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3619 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3620 #endif 3621 const int isread = usbd_xfer_isread(xfer); 3622 3623 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3624 3625 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3626 3627 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3628 3629 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3630 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3631 } 3632 3633 static void 3634 xhci_device_intr_abort(struct usbd_xfer *xfer) 3635 { 3636 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3637 3638 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3639 3640 KASSERT(mutex_owned(&sc->sc_lock)); 3641 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3642 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3643 xhci_abort_xfer(xfer, USBD_CANCELLED); 3644 } 3645 3646 static void 3647 xhci_device_intr_close(struct usbd_pipe *pipe) 3648 { 3649 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3650 3651 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3652 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3653 3654 xhci_close_pipe(pipe); 3655 } 3656 3657 /* ------------ */ 3658 3659 static void 3660 xhci_timeout(void *addr) 3661 { 3662 struct xhci_xfer * const xx = addr; 3663 struct usbd_xfer * const xfer = &xx->xx_xfer; 3664 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3665 3666 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3667 3668 if (sc->sc_dying) { 3669 return; 3670 } 3671 3672 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 3673 USB_TASKQ_MPSAFE); 3674 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 3675 USB_TASKQ_HC); 3676 } 3677 3678 static void 3679 xhci_timeout_task(void *addr) 3680 { 3681 struct usbd_xfer * const xfer = addr; 3682 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3683 3684 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3685 3686 mutex_enter(&sc->sc_lock); 3687 #if 0 3688 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3689 #else 3690 xfer->ux_status = USBD_TIMEOUT; 3691 usb_transfer_complete(xfer); 3692 #endif 3693 mutex_exit(&sc->sc_lock); 3694 } 3695
Indexes created Mon Sep 22 13:09:51 GMT 2025