xhci.c revision 1.47
1 /* $NetBSD: xhci.c,v 1.47 2016/05/31 09:22:11 mlelstv Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.47 2016/05/31 09:22:11 mlelstv Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 146 147 static usbd_status xhci_do_command(struct xhci_softc * const, 148 struct xhci_trb * const, int); 149 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 150 struct xhci_trb * const, int); 151 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t, uint32_t, int); 152 static usbd_status xhci_enable_slot(struct xhci_softc * const, 153 uint8_t * const); 154 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 155 static usbd_status xhci_address_device(struct xhci_softc * const, 156 uint64_t, uint8_t, bool); 157 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 158 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 159 struct xhci_slot * const, u_int); 160 static usbd_status xhci_ring_init(struct xhci_softc * const, 161 struct xhci_ring * const, size_t, size_t); 162 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 163 164 static void xhci_noop(struct usbd_pipe *); 165 166 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 167 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 168 static void xhci_root_intr_abort(struct usbd_xfer *); 169 static void xhci_root_intr_close(struct usbd_pipe *); 170 static void xhci_root_intr_done(struct usbd_xfer *); 171 172 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 173 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 174 static void xhci_device_ctrl_abort(struct usbd_xfer *); 175 static void xhci_device_ctrl_close(struct usbd_pipe *); 176 static void xhci_device_ctrl_done(struct usbd_xfer *); 177 178 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 179 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 180 static void xhci_device_intr_abort(struct usbd_xfer *); 181 static void xhci_device_intr_close(struct usbd_pipe *); 182 static void xhci_device_intr_done(struct usbd_xfer *); 183 184 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 185 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 186 static void xhci_device_bulk_abort(struct usbd_xfer *); 187 static void xhci_device_bulk_close(struct usbd_pipe *); 188 static void xhci_device_bulk_done(struct usbd_xfer *); 189 190 static void xhci_timeout(void *); 191 static void xhci_timeout_task(void *); 192 193 static const struct usbd_bus_methods xhci_bus_methods = { 194 .ubm_open = xhci_open, 195 .ubm_softint = xhci_softintr, 196 .ubm_dopoll = xhci_poll, 197 .ubm_allocx = xhci_allocx, 198 .ubm_freex = xhci_freex, 199 .ubm_getlock = xhci_get_lock, 200 .ubm_newdev = xhci_new_device, 201 .ubm_rhctrl = xhci_roothub_ctrl, 202 }; 203 204 static const struct usbd_pipe_methods xhci_root_intr_methods = { 205 .upm_transfer = xhci_root_intr_transfer, 206 .upm_start = xhci_root_intr_start, 207 .upm_abort = xhci_root_intr_abort, 208 .upm_close = xhci_root_intr_close, 209 .upm_cleartoggle = xhci_noop, 210 .upm_done = xhci_root_intr_done, 211 }; 212 213 214 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 215 .upm_transfer = xhci_device_ctrl_transfer, 216 .upm_start = xhci_device_ctrl_start, 217 .upm_abort = xhci_device_ctrl_abort, 218 .upm_close = xhci_device_ctrl_close, 219 .upm_cleartoggle = xhci_noop, 220 .upm_done = xhci_device_ctrl_done, 221 }; 222 223 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 224 .upm_cleartoggle = xhci_noop, 225 }; 226 227 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 228 .upm_transfer = xhci_device_bulk_transfer, 229 .upm_start = xhci_device_bulk_start, 230 .upm_abort = xhci_device_bulk_abort, 231 .upm_close = xhci_device_bulk_close, 232 .upm_cleartoggle = xhci_noop, 233 .upm_done = xhci_device_bulk_done, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_intr_methods = { 237 .upm_transfer = xhci_device_intr_transfer, 238 .upm_start = xhci_device_intr_start, 239 .upm_abort = xhci_device_intr_abort, 240 .upm_close = xhci_device_intr_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_intr_done, 243 }; 244 245 static inline uint32_t 246 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 247 { 248 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 249 } 250 251 static inline uint32_t 252 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 253 { 254 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 255 } 256 257 static inline void 258 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 259 uint32_t value) 260 { 261 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 262 } 263 264 #if 0 /* unused */ 265 static inline void 266 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 267 uint32_t value) 268 { 269 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 270 } 271 #endif /* unused */ 272 273 static inline uint32_t 274 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 275 { 276 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 277 } 278 279 static inline uint32_t 280 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 281 { 282 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 283 } 284 285 static inline void 286 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 287 uint32_t value) 288 { 289 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 290 } 291 292 static inline uint64_t 293 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 294 { 295 uint64_t value; 296 297 if (sc->sc_ac64) { 298 #ifdef XHCI_USE_BUS_SPACE_8 299 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 300 #else 301 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 302 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 303 offset + 4) << 32; 304 #endif 305 } else { 306 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 307 } 308 309 return value; 310 } 311 312 static inline void 313 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 314 uint64_t value) 315 { 316 if (sc->sc_ac64) { 317 #ifdef XHCI_USE_BUS_SPACE_8 318 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 319 #else 320 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 321 (value >> 0) & 0xffffffff); 322 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 323 (value >> 32) & 0xffffffff); 324 #endif 325 } else { 326 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 327 } 328 } 329 330 static inline uint32_t 331 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 332 { 333 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 334 } 335 336 static inline void 337 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 338 uint32_t value) 339 { 340 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 341 } 342 343 #if 0 /* unused */ 344 static inline uint64_t 345 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 346 { 347 uint64_t value; 348 349 if (sc->sc_ac64) { 350 #ifdef XHCI_USE_BUS_SPACE_8 351 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 352 #else 353 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 354 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 355 offset + 4) << 32; 356 #endif 357 } else { 358 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 359 } 360 361 return value; 362 } 363 #endif /* unused */ 364 365 static inline void 366 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 367 uint64_t value) 368 { 369 if (sc->sc_ac64) { 370 #ifdef XHCI_USE_BUS_SPACE_8 371 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 372 #else 373 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 374 (value >> 0) & 0xffffffff); 375 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 376 (value >> 32) & 0xffffffff); 377 #endif 378 } else { 379 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 380 } 381 } 382 383 #if 0 /* unused */ 384 static inline uint32_t 385 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 386 { 387 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 388 } 389 #endif /* unused */ 390 391 static inline void 392 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 393 uint32_t value) 394 { 395 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 396 } 397 398 /* --- */ 399 400 static inline uint8_t 401 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 402 { 403 u_int eptype = 0; 404 405 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 406 case UE_CONTROL: 407 eptype = 0x0; 408 break; 409 case UE_ISOCHRONOUS: 410 eptype = 0x1; 411 break; 412 case UE_BULK: 413 eptype = 0x2; 414 break; 415 case UE_INTERRUPT: 416 eptype = 0x3; 417 break; 418 } 419 420 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 421 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 422 return eptype | 0x4; 423 else 424 return eptype; 425 } 426 427 static u_int 428 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 429 { 430 /* xHCI 1.0 section 4.5.1 */ 431 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 432 u_int in = 0; 433 434 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 435 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 436 in = 1; 437 438 return epaddr * 2 + in; 439 } 440 441 static inline u_int 442 xhci_dci_to_ici(const u_int i) 443 { 444 return i + 1; 445 } 446 447 static inline void * 448 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 449 const u_int dci) 450 { 451 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 452 } 453 454 #if 0 /* unused */ 455 static inline bus_addr_t 456 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 457 const u_int dci) 458 { 459 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 460 } 461 #endif /* unused */ 462 463 static inline void * 464 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 465 const u_int ici) 466 { 467 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 468 } 469 470 static inline bus_addr_t 471 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 472 const u_int ici) 473 { 474 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 475 } 476 477 static inline struct xhci_trb * 478 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 479 { 480 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 481 } 482 483 static inline bus_addr_t 484 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 485 { 486 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 487 } 488 489 static inline void 490 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 491 uint32_t control) 492 { 493 trb->trb_0 = htole64(parameter); 494 trb->trb_2 = htole32(status); 495 trb->trb_3 = htole32(control); 496 } 497 498 static int 499 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 500 { 501 /* base address of TRBs */ 502 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 503 504 /* trb_0 range sanity check */ 505 if (trb_0 == 0 || trb_0 < trbp || 506 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 507 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 508 return 1; 509 } 510 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 511 return 0; 512 } 513 514 /* --- */ 515 516 void 517 xhci_childdet(device_t self, device_t child) 518 { 519 struct xhci_softc * const sc = device_private(self); 520 521 KASSERT(sc->sc_child == child); 522 if (child == sc->sc_child) 523 sc->sc_child = NULL; 524 } 525 526 int 527 xhci_detach(struct xhci_softc *sc, int flags) 528 { 529 int rv = 0; 530 531 if (sc->sc_child != NULL) 532 rv = config_detach(sc->sc_child, flags); 533 534 if (rv != 0) 535 return rv; 536 537 /* XXX unconfigure/free slots */ 538 539 /* verify: */ 540 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 541 xhci_op_write_4(sc, XHCI_USBCMD, 0); 542 /* do we need to wait for stop? */ 543 544 xhci_op_write_8(sc, XHCI_CRCR, 0); 545 xhci_ring_free(sc, &sc->sc_cr); 546 cv_destroy(&sc->sc_command_cv); 547 548 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 549 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 550 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 551 xhci_ring_free(sc, &sc->sc_er); 552 553 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 554 555 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 556 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 557 558 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 559 560 mutex_destroy(&sc->sc_lock); 561 mutex_destroy(&sc->sc_intr_lock); 562 cv_destroy(&sc->sc_softwake_cv); 563 564 pool_cache_destroy(sc->sc_xferpool); 565 566 return rv; 567 } 568 569 int 570 xhci_activate(device_t self, enum devact act) 571 { 572 struct xhci_softc * const sc = device_private(self); 573 574 switch (act) { 575 case DVACT_DEACTIVATE: 576 sc->sc_dying = true; 577 return 0; 578 default: 579 return EOPNOTSUPP; 580 } 581 } 582 583 bool 584 xhci_suspend(device_t dv, const pmf_qual_t *qual) 585 { 586 return false; 587 } 588 589 bool 590 xhci_resume(device_t dv, const pmf_qual_t *qual) 591 { 592 return false; 593 } 594 595 bool 596 xhci_shutdown(device_t self, int flags) 597 { 598 return false; 599 } 600 601 static int 602 xhci_hc_reset(struct xhci_softc * const sc) 603 { 604 uint32_t usbcmd, usbsts; 605 int i; 606 607 /* Check controller not ready */ 608 for (i = 0; i < XHCI_WAIT_CNR; i++) { 609 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 610 if ((usbsts & XHCI_STS_CNR) == 0) 611 break; 612 usb_delay_ms(&sc->sc_bus, 1); 613 } 614 if (i >= XHCI_WAIT_CNR) { 615 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 616 return EIO; 617 } 618 619 /* Halt controller */ 620 usbcmd = 0; 621 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 622 usb_delay_ms(&sc->sc_bus, 1); 623 624 /* Reset controller */ 625 usbcmd = XHCI_CMD_HCRST; 626 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 627 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 628 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 629 if ((usbcmd & XHCI_CMD_HCRST) == 0) 630 break; 631 usb_delay_ms(&sc->sc_bus, 1); 632 } 633 if (i >= XHCI_WAIT_HCRST) { 634 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 635 return EIO; 636 } 637 638 /* Check controller not ready */ 639 for (i = 0; i < XHCI_WAIT_CNR; i++) { 640 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 641 if ((usbsts & XHCI_STS_CNR) == 0) 642 break; 643 usb_delay_ms(&sc->sc_bus, 1); 644 } 645 if (i >= XHCI_WAIT_CNR) { 646 aprint_error_dev(sc->sc_dev, 647 "controller not ready timeout after reset\n"); 648 return EIO; 649 } 650 651 return 0; 652 } 653 654 655 static void 656 hexdump(const char *msg, const void *base, size_t len) 657 { 658 #if 0 659 size_t cnt; 660 const uint32_t *p; 661 extern paddr_t vtophys(vaddr_t); 662 663 p = base; 664 cnt = 0; 665 666 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 667 (void *)vtophys((vaddr_t)base)); 668 669 while (cnt < len) { 670 if (cnt % 16 == 0) 671 printf("%p: ", p); 672 else if (cnt % 8 == 0) 673 printf(" |"); 674 printf(" %08x", *p++); 675 cnt += 4; 676 if (cnt % 16 == 0) 677 printf("\n"); 678 } 679 if (cnt % 16 != 0) 680 printf("\n"); 681 #endif 682 } 683 684 /* Process extended capabilities */ 685 static void 686 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 687 { 688 uint32_t ecp, ecr; 689 690 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 691 692 ecp = XHCI_HCC_XECP(hcc) * 4; 693 while (ecp != 0) { 694 ecr = xhci_read_4(sc, ecp); 695 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 696 switch (XHCI_XECP_ID(ecr)) { 697 case XHCI_ID_PROTOCOLS: { 698 uint32_t w4, w8, wc; 699 uint16_t w2; 700 w2 = (ecr >> 16) & 0xffff; 701 w4 = xhci_read_4(sc, ecp + 4); 702 w8 = xhci_read_4(sc, ecp + 8); 703 wc = xhci_read_4(sc, ecp + 0xc); 704 aprint_debug_dev(sc->sc_dev, 705 " SP: %08x %08x %08x %08x\n", ecr, w4, w8, wc); 706 /* unused */ 707 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0300) { 708 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 709 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 710 } 711 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0200) { 712 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 713 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 714 } 715 break; 716 } 717 case XHCI_ID_USB_LEGACY: { 718 uint8_t bios_sem; 719 720 /* Take host controller ownership from BIOS */ 721 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 722 if (bios_sem) { 723 /* sets xHCI to be owned by OS */ 724 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 725 aprint_debug_dev(sc->sc_dev, 726 "waiting for BIOS to give up control\n"); 727 for (int i = 0; i < 5000; i++) { 728 bios_sem = xhci_read_1(sc, ecp + 729 XHCI_XECP_BIOS_SEM); 730 if (bios_sem == 0) 731 break; 732 DELAY(1000); 733 } 734 if (bios_sem) { 735 aprint_error_dev(sc->sc_dev, 736 "timed out waiting for BIOS\n"); 737 } 738 } 739 break; 740 } 741 default: 742 break; 743 } 744 ecr = xhci_read_4(sc, ecp); 745 if (XHCI_XECP_NEXT(ecr) == 0) { 746 ecp = 0; 747 } else { 748 ecp += XHCI_XECP_NEXT(ecr) * 4; 749 } 750 } 751 } 752 753 #define XHCI_HCCPREV1_BITS \ 754 "\177\020" /* New bitmask */ \ 755 "f\020\020XECP\0" \ 756 "f\014\4MAXPSA\0" \ 757 "b\013CFC\0" \ 758 "b\012SEC\0" \ 759 "b\011SBD\0" \ 760 "b\010FSE\0" \ 761 "b\7NSS\0" \ 762 "b\6LTC\0" \ 763 "b\5LHRC\0" \ 764 "b\4PIND\0" \ 765 "b\3PPC\0" \ 766 "b\2CZC\0" \ 767 "b\1BNC\0" \ 768 "b\0AC64\0" \ 769 "\0" 770 #define XHCI_HCCV1_x_BITS \ 771 "\177\020" /* New bitmask */ \ 772 "f\020\020XECP\0" \ 773 "f\014\4MAXPSA\0" \ 774 "b\013CFC\0" \ 775 "b\012SEC\0" \ 776 "b\011SPC\0" \ 777 "b\010PAE\0" \ 778 "b\7NSS\0" \ 779 "b\6LTC\0" \ 780 "b\5LHRC\0" \ 781 "b\4PIND\0" \ 782 "b\3PPC\0" \ 783 "b\2CSZ\0" \ 784 "b\1BNC\0" \ 785 "b\0AC64\0" \ 786 "\0" 787 788 int 789 xhci_init(struct xhci_softc *sc) 790 { 791 bus_size_t bsz; 792 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 793 uint32_t pagesize, config; 794 int i = 0; 795 uint16_t hciversion; 796 uint8_t caplength; 797 798 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 799 800 sc->sc_bus.ub_revision = USBREV_3_0; 801 sc->sc_bus.ub_usedma = true; 802 803 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 804 caplength = XHCI_CAP_CAPLENGTH(cap); 805 hciversion = XHCI_CAP_HCIVERSION(cap); 806 807 if (hciversion < XHCI_HCIVERSION_0_96 || 808 hciversion > XHCI_HCIVERSION_1_0) { 809 aprint_normal_dev(sc->sc_dev, 810 "xHCI version %x.%x not known to be supported\n", 811 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 812 } else { 813 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 814 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 815 } 816 817 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 818 &sc->sc_cbh) != 0) { 819 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 820 return ENOMEM; 821 } 822 823 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 824 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 825 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 826 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 827 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 828 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 829 aprint_debug_dev(sc->sc_dev, 830 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 831 832 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 833 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 834 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 835 836 char sbuf[128]; 837 if (hciversion < XHCI_HCIVERSION_1_0) 838 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 839 else 840 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 841 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 842 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 843 844 /* print PSI and take ownership from BIOS */ 845 xhci_ecp(sc, hcc); 846 847 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 848 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 849 &sc->sc_obh) != 0) { 850 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 851 return ENOMEM; 852 } 853 854 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 855 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 856 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 857 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 858 return ENOMEM; 859 } 860 861 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 862 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 863 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 864 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 865 return ENOMEM; 866 } 867 868 int rv; 869 rv = xhci_hc_reset(sc); 870 if (rv != 0) { 871 return rv; 872 } 873 874 if (sc->sc_vendor_init) 875 sc->sc_vendor_init(sc); 876 877 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 878 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 879 pagesize = ffs(pagesize); 880 if (pagesize == 0) { 881 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 882 return EIO; 883 } 884 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 885 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 886 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 887 (uint32_t)sc->sc_maxslots); 888 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 889 890 usbd_status err; 891 892 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 893 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 894 if (sc->sc_maxspbuf != 0) { 895 err = usb_allocmem(&sc->sc_bus, 896 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 897 &sc->sc_spbufarray_dma); 898 if (err) { 899 aprint_error_dev(sc->sc_dev, 900 "spbufarray init fail, err %d\n", err); 901 return ENOMEM; 902 } 903 904 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 905 sc->sc_maxspbuf, KM_SLEEP); 906 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 907 for (i = 0; i < sc->sc_maxspbuf; i++) { 908 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 909 /* allocate contexts */ 910 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 911 sc->sc_pgsz, dma); 912 if (err) { 913 aprint_error_dev(sc->sc_dev, 914 "spbufarray_dma init fail, err %d\n", err); 915 rv = ENOMEM; 916 goto bad1; 917 } 918 spbufarray[i] = htole64(DMAADDR(dma, 0)); 919 usb_syncmem(dma, 0, sc->sc_pgsz, 920 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 921 } 922 923 usb_syncmem(&sc->sc_spbufarray_dma, 0, 924 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 925 } 926 927 config = xhci_op_read_4(sc, XHCI_CONFIG); 928 config &= ~0xFF; 929 config |= sc->sc_maxslots & 0xFF; 930 xhci_op_write_4(sc, XHCI_CONFIG, config); 931 932 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 933 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 934 if (err) { 935 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 936 err); 937 rv = ENOMEM; 938 goto bad1; 939 } 940 941 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 942 XHCI_EVENT_RING_SEGMENTS_ALIGN); 943 if (err) { 944 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 945 err); 946 rv = ENOMEM; 947 goto bad2; 948 } 949 950 usb_dma_t *dma; 951 size_t size; 952 size_t align; 953 954 dma = &sc->sc_eventst_dma; 955 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 956 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 957 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 958 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 959 err = usb_allocmem(&sc->sc_bus, size, align, dma); 960 if (err) { 961 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 962 err); 963 rv = ENOMEM; 964 goto bad3; 965 } 966 967 memset(KERNADDR(dma, 0), 0, size); 968 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 969 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 970 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 971 KERNADDR(&sc->sc_eventst_dma, 0), 972 sc->sc_eventst_dma.udma_block->size); 973 974 dma = &sc->sc_dcbaa_dma; 975 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 976 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 977 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 978 err = usb_allocmem(&sc->sc_bus, size, align, dma); 979 if (err) { 980 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 981 rv = ENOMEM; 982 goto bad4; 983 } 984 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 985 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 986 KERNADDR(&sc->sc_dcbaa_dma, 0), 987 sc->sc_dcbaa_dma.udma_block->size); 988 989 memset(KERNADDR(dma, 0), 0, size); 990 if (sc->sc_maxspbuf != 0) { 991 /* 992 * DCBA entry 0 hold the scratchbuf array pointer. 993 */ 994 *(uint64_t *)KERNADDR(dma, 0) = 995 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 996 } 997 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 998 999 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1000 KM_SLEEP); 1001 if (sc->sc_slots == NULL) { 1002 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1003 rv = ENOMEM; 1004 goto bad; 1005 } 1006 1007 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1008 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1009 if (sc->sc_xferpool == NULL) { 1010 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1011 err); 1012 rv = ENOMEM; 1013 goto bad; 1014 } 1015 1016 cv_init(&sc->sc_command_cv, "xhcicmd"); 1017 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1018 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1019 cv_init(&sc->sc_softwake_cv, "xhciab"); 1020 1021 /* Set up the bus struct. */ 1022 sc->sc_bus.ub_methods = &xhci_bus_methods; 1023 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 1024 1025 struct xhci_erste *erst; 1026 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1027 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1028 erst[0].erste_2 = htole32(XHCI_EVENT_RING_TRBS); 1029 erst[0].erste_3 = htole32(0); 1030 usb_syncmem(&sc->sc_eventst_dma, 0, 1031 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1032 1033 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1034 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1035 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1036 XHCI_ERDP_LO_BUSY); 1037 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1038 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1039 sc->sc_cr.xr_cs); 1040 1041 #if 0 1042 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1043 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1044 #endif 1045 1046 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1047 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1048 /* Intel xhci needs interrupt rate moderated. */ 1049 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1050 else 1051 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1052 aprint_debug_dev(sc->sc_dev, "setting IMOD %u\n", 1053 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1054 1055 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 1056 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1057 xhci_op_read_4(sc, XHCI_USBCMD)); 1058 1059 return 0; 1060 1061 bad: 1062 if (sc->sc_xferpool) { 1063 pool_cache_destroy(sc->sc_xferpool); 1064 sc->sc_xferpool = NULL; 1065 } 1066 1067 if (sc->sc_slots) { 1068 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1069 sc->sc_maxslots); 1070 sc->sc_slots = NULL; 1071 } 1072 1073 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1074 bad4: 1075 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1076 bad3: 1077 xhci_ring_free(sc, &sc->sc_er); 1078 bad2: 1079 xhci_ring_free(sc, &sc->sc_cr); 1080 i = sc->sc_maxspbuf; 1081 bad1: 1082 for (int j = 0; j < i; j++) 1083 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1084 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1085 1086 return rv; 1087 } 1088 1089 int 1090 xhci_intr(void *v) 1091 { 1092 struct xhci_softc * const sc = v; 1093 int ret = 0; 1094 1095 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1096 1097 if (sc == NULL) 1098 return 0; 1099 1100 mutex_spin_enter(&sc->sc_intr_lock); 1101 1102 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1103 goto done; 1104 1105 /* If we get an interrupt while polling, then just ignore it. */ 1106 if (sc->sc_bus.ub_usepolling) { 1107 #ifdef DIAGNOSTIC 1108 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1109 #endif 1110 goto done; 1111 } 1112 1113 ret = xhci_intr1(sc); 1114 done: 1115 mutex_spin_exit(&sc->sc_intr_lock); 1116 return ret; 1117 } 1118 1119 int 1120 xhci_intr1(struct xhci_softc * const sc) 1121 { 1122 uint32_t usbsts; 1123 uint32_t iman; 1124 1125 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1126 1127 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1128 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1129 #if 0 1130 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1131 return 0; 1132 } 1133 #endif 1134 xhci_op_write_4(sc, XHCI_USBSTS, 1135 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1136 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1137 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1138 1139 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1140 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1141 iman |= XHCI_IMAN_INTR_PEND; 1142 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1143 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1144 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1145 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1146 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1147 1148 usb_schedsoftintr(&sc->sc_bus); 1149 1150 return 1; 1151 } 1152 1153 /* 1154 * 3 port speed types used in USB stack 1155 * 1156 * usbdi speed 1157 * definition: USB_SPEED_* in usb.h 1158 * They are used in struct usbd_device in USB stack. 1159 * ioctl interface uses these values too. 1160 * port_status speed 1161 * definition: UPS_*_SPEED in usb.h 1162 * They are used in usb_port_status_t and valid only for USB 2.0. 1163 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1164 * of usb_port_status_ext_t indicates port speed. 1165 * Note that some 3.0 values overlap with 2.0 values. 1166 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1167 * means UPS_LOW_SPEED in HS.) 1168 * port status returned from hub also uses these values. 1169 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1170 * or more. 1171 * xspeed: 1172 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1173 * They are used in only slot context and PORTSC reg of xhci. 1174 * The difference between usbdi speed and xspeed is 1175 * that FS and LS values are swapped. 1176 */ 1177 1178 /* convert usbdi speed to xspeed */ 1179 static int 1180 xhci_speed2xspeed(int speed) 1181 { 1182 switch (speed) { 1183 case USB_SPEED_LOW: return 2; 1184 case USB_SPEED_FULL: return 1; 1185 default: return speed; 1186 } 1187 } 1188 1189 #if 0 1190 /* convert xspeed to usbdi speed */ 1191 static int 1192 xhci_xspeed2speed(int xspeed) 1193 { 1194 switch (xspeed) { 1195 case 1: return USB_SPEED_FULL; 1196 case 2: return USB_SPEED_LOW; 1197 default: return xspeed; 1198 } 1199 } 1200 #endif 1201 1202 /* convert xspeed to port status speed */ 1203 static int 1204 xhci_xspeed2psspeed(int xspeed) 1205 { 1206 switch (xspeed) { 1207 case 0: return 0; 1208 case 1: return UPS_FULL_SPEED; 1209 case 2: return UPS_LOW_SPEED; 1210 case 3: return UPS_HIGH_SPEED; 1211 default: return UPS_OTHER_SPEED; 1212 } 1213 } 1214 1215 /* construct slot context */ 1216 static void 1217 xhci_setup_sctx(struct usbd_device *dev, uint32_t *cp) 1218 { 1219 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 1220 int speed = dev->ud_speed; 1221 int tthubslot, ttportnum; 1222 bool ishub; 1223 bool usemtt; 1224 1225 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1226 1227 /* 1228 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 1229 * tthubslot: 1230 * This is the slot ID of parent HS hub 1231 * if LS/FS device is connected && connected through HS hub. 1232 * This is 0 if device is not LS/FS device || 1233 * parent hub is not HS hub || 1234 * attached to root hub. 1235 * ttportnum: 1236 * This is the downstream facing port of parent HS hub 1237 * if LS/FS device is connected. 1238 * This is 0 if device is not LS/FS device || 1239 * parent hub is not HS hub || 1240 * attached to root hub. 1241 */ 1242 if (dev->ud_myhsport != NULL && 1243 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1244 (dev->ud_myhub != NULL && 1245 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1246 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 1247 ttportnum = dev->ud_myhsport->up_portno; 1248 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 1249 } else { 1250 ttportnum = 0; 1251 tthubslot = 0; 1252 } 1253 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 1254 dev->ud_myhsport, ttportnum, tthubslot, 0); 1255 1256 /* ishub is valid after reading UDESC_DEVICE */ 1257 ishub = (dd->bDeviceClass == UDCLASS_HUB); 1258 1259 /* dev->ud_hub is valid after reading UDESC_HUB */ 1260 if (ishub && dev->ud_hub) { 1261 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 1262 1263 cp[1] |= htole32(XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts)); 1264 cp[2] |= htole32(XHCI_SCTX_2_TT_THINK_TIME_SET( 1265 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK))); 1266 DPRINTFN(4, "nports=%d ttt=%d", 1267 hd->bNbrPorts, XHCI_SCTX_2_TT_THINK_TIME_GET(cp[2]), 0, 0); 1268 } 1269 1270 #define IS_TTHUB(dd) \ 1271 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 1272 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 1273 1274 /* 1275 * MTT flag is set if 1276 * 1. this is HS hub && MTT is enabled 1277 * or 1278 * 2. this is not hub && this is LS or FS device && 1279 * MTT of parent HS hub (and its parent, too) is enabled 1280 */ 1281 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 1282 usemtt = true; 1283 else if (!ishub && 1284 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 1285 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 1286 (dev->ud_myhub != NULL && 1287 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 1288 dev->ud_myhsport != NULL && 1289 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 1290 usemtt = true; 1291 else 1292 usemtt = false; 1293 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 1294 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 1295 1296 cp[0] |= htole32( 1297 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)) | 1298 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 1299 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0) 1300 ); 1301 cp[1] |= htole32(0); 1302 cp[2] |= htole32( 1303 XHCI_SCTX_2_IRQ_TARGET_SET(0) | 1304 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 1305 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum) 1306 ); 1307 cp[3] |= htole32(0); 1308 } 1309 1310 static uint32_t 1311 xhci_get_maxburst(struct usbd_pipe *pipe) 1312 { 1313 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1314 usbd_desc_iter_t iter; 1315 const usb_cdc_descriptor_t *cdcd; 1316 const usb_endpoint_ss_comp_descriptor_t * esscd = NULL; 1317 uint32_t maxb = 0; 1318 uint8_t ep; 1319 1320 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc( 1321 pipe->up_dev, UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 1322 usb_desc_iter_init(pipe->up_dev, &iter); 1323 iter.cur = (const void *)cdcd; 1324 1325 /* find endpoint_ss_comp desc for ep of this pipe */ 1326 for (ep = 0;;) { 1327 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 1328 if (cdcd == NULL) 1329 break; 1330 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 1331 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 1332 bEndpointAddress; 1333 if (UE_GET_ADDR(ep) == 1334 UE_GET_ADDR(ed->bEndpointAddress)) { 1335 cdcd = (const usb_cdc_descriptor_t *) 1336 usb_desc_iter_next(&iter); 1337 break; 1338 } 1339 ep = 0; 1340 } 1341 } 1342 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 1343 esscd = (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 1344 maxb = esscd->bMaxBurst; 1345 } 1346 1347 return maxb; 1348 } 1349 1350 /* 1351 * Convert endpoint bInterval value to endpoint context interval value 1352 * for Interrupt pipe. 1353 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 1354 */ 1355 static uint32_t 1356 xhci_bival2ival(uint32_t ival, int speed) 1357 { 1358 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 1359 int i; 1360 1361 /* 1362 * round ival down to "the nearest base 2 multiple of 1363 * bInterval * 8". 1364 * bInterval is at most 255 as its type is uByte. 1365 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 1366 */ 1367 for (i = 10; i > 0; i--) { 1368 if ((ival * 8) >= (1 << i)) 1369 break; 1370 } 1371 ival = i; 1372 } else { 1373 /* Interval = bInterval-1 for SS/HS */ 1374 ival--; 1375 } 1376 1377 return ival; 1378 } 1379 1380 /* 1381 * 4.8.2, 6.2.3.2 1382 * construct common endpoint parameters 1383 */ 1384 static void 1385 xhci_setup_endp_ctx(struct usbd_pipe *pipe, uint32_t *cp) 1386 { 1387 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1388 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1389 const u_int dci = xhci_ep_get_dci(ed); 1390 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1391 uint32_t mps = UGETW(ed->wMaxPacketSize); 1392 uint32_t maxb = 0; 1393 int speed = pipe->up_dev->ud_speed; 1394 uint32_t ival = ed->bInterval; 1395 1396 cp[0] = htole32( 1397 XHCI_EPCTX_0_EPSTATE_SET(0) | 1398 XHCI_EPCTX_0_MULT_SET(0) | /* always 0 except SS iscoh */ 1399 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 1400 XHCI_EPCTX_0_LSA_SET(0) | 1401 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0) 1402 ); 1403 cp[1] = htole32( 1404 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 1405 XHCI_EPCTX_1_HID_SET(0) | 1406 XHCI_EPCTX_1_MAXB_SET(0) 1407 ); 1408 if (xfertype != UE_ISOCHRONOUS) 1409 cp[1] |= htole32(XHCI_EPCTX_1_CERR_SET(3)); 1410 1411 /* 6.2.3.4, 4.8.2.4 */ 1412 if (USB_IS_SS(speed)) { 1413 /* UBS 3.1 9.6.6 */ 1414 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 1415 /* UBS 3.1 9.6.7 */ 1416 maxb = xhci_get_maxburst(pipe); 1417 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1418 } else { 1419 /* UBS 2.0 9.6.6 */ 1420 cp[1] |= htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps))); 1421 1422 /* 6.2.3.4 */ 1423 if (speed == USB_SPEED_HIGH && 1424 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 1425 maxb = UE_GET_TRANS(mps); 1426 } else { 1427 /* LS/FS or HS CTRL or HS BULK */ 1428 maxb = 0; 1429 } 1430 cp[1] |= htole32(XHCI_EPCTX_1_MAXB_SET(maxb)); 1431 } 1432 1433 if (xfertype == UE_CONTROL) 1434 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(8)); /* 6.2.3 */ 1435 else if (USB_IS_SS(speed)) 1436 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps)); 1437 else 1438 cp[4] = htole32(XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps))); 1439 1440 switch (xfertype) { 1441 case UE_CONTROL: 1442 break; 1443 case UE_BULK: 1444 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 1445 break; 1446 case UE_INTERRUPT: 1447 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1448 ival = pipe->up_interval; 1449 1450 ival = xhci_bival2ival(ival, speed); 1451 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1452 break; 1453 case UE_ISOCHRONOUS: 1454 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 1455 ival = pipe->up_interval; 1456 1457 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 1458 if (speed == USB_SPEED_FULL) 1459 ival += 3; /* 1ms -> 125us */ 1460 ival--; 1461 cp[0] |= htole32(XHCI_EPCTX_0_IVAL_SET(ival)); 1462 1463 if (USB_IS_SS(speed)) { 1464 /* XXX if LEC = 1, set ESIT instead */ 1465 cp[0] |= htole32(XHCI_EPCTX_0_MULT_SET(0)); 1466 } 1467 break; 1468 default: 1469 break; 1470 } 1471 *(uint64_t *)(&cp[2]) = htole64( 1472 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 1473 XHCI_EPCTX_2_DCS_SET(1)); 1474 } 1475 1476 /* 1477 * Construct input contexts and issue TRB 1478 */ 1479 static usbd_status 1480 xhci_configure_endpoint(struct usbd_pipe *pipe) 1481 { 1482 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1483 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1484 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1485 struct xhci_trb trb; 1486 usbd_status err; 1487 uint32_t *cp; 1488 1489 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1490 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1491 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1492 pipe->up_endpoint->ue_edesc->bmAttributes); 1493 1494 /* XXX ensure input context is available? */ 1495 1496 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1497 1498 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1499 cp[0] = htole32(0); 1500 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 1501 1502 /* set up input slot context */ 1503 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1504 xhci_setup_sctx(pipe->up_dev, cp); 1505 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1506 1507 /* set up input endpoint context */ 1508 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 1509 xhci_setup_endp_ctx(pipe, cp); 1510 1511 /* sync input contexts before they are read from memory */ 1512 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1513 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1514 sc->sc_ctxsz * 1); 1515 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1516 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1517 1518 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1519 trb.trb_2 = 0; 1520 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1521 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1522 1523 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1524 1525 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1526 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1527 sc->sc_ctxsz * 1); 1528 1529 return err; 1530 } 1531 1532 #if 0 1533 static usbd_status 1534 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1535 { 1536 #ifdef USB_DEBUG 1537 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1538 #endif 1539 1540 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1541 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1542 1543 return USBD_NORMAL_COMPLETION; 1544 } 1545 #endif 1546 1547 /* 4.6.8, 6.4.3.7 */ 1548 static usbd_status 1549 xhci_reset_endpoint(struct usbd_pipe *pipe) 1550 { 1551 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1552 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1553 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1554 struct xhci_trb trb; 1555 usbd_status err; 1556 1557 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1558 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1559 1560 KASSERT(!mutex_owned(&sc->sc_lock)); 1561 1562 trb.trb_0 = 0; 1563 trb.trb_2 = 0; 1564 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1565 XHCI_TRB_3_EP_SET(dci) | 1566 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1567 1568 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1569 1570 return err; 1571 } 1572 1573 /* 1574 * 4.6.9, 6.4.3.8 1575 * Stop execution of TDs on xfer ring. 1576 * Should be called with sc_lock held. 1577 */ 1578 static usbd_status 1579 xhci_stop_endpoint(struct usbd_pipe *pipe) 1580 { 1581 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1582 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1583 struct xhci_trb trb; 1584 usbd_status err; 1585 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1586 1587 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1588 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1589 1590 KASSERT(mutex_owned(&sc->sc_lock)); 1591 1592 trb.trb_0 = 0; 1593 trb.trb_2 = 0; 1594 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1595 XHCI_TRB_3_EP_SET(dci) | 1596 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1597 1598 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1599 1600 return err; 1601 } 1602 1603 /* 1604 * Set TR Dequeue Pointer. 1605 * xCHI 1.1 4.6.10 6.4.3.9 1606 * Purge all of the transfer requests on ring. 1607 * EPSTATE of endpoint must be ERROR or STOPPED, or CONTEXT_STATE error. 1608 */ 1609 static usbd_status 1610 xhci_set_dequeue(struct usbd_pipe *pipe) 1611 { 1612 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1613 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1614 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1615 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1616 struct xhci_trb trb; 1617 usbd_status err; 1618 1619 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1620 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1621 1622 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1623 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1624 BUS_DMASYNC_PREWRITE); 1625 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1626 1627 xr->xr_ep = 0; 1628 xr->xr_cs = 1; 1629 1630 /* set DCS */ 1631 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1632 trb.trb_2 = 0; 1633 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1634 XHCI_TRB_3_EP_SET(dci) | 1635 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1636 1637 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1638 1639 return err; 1640 } 1641 1642 /* 1643 * Open new pipe: called from usbd_setup_pipe_flags. 1644 * Fills methods of pipe. 1645 * If pipe is not for ep0, calls configure_endpoint. 1646 */ 1647 static usbd_status 1648 xhci_open(struct usbd_pipe *pipe) 1649 { 1650 struct usbd_device * const dev = pipe->up_dev; 1651 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1652 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1653 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1654 1655 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1656 DPRINTFN(1, "addr %d depth %d port %d speed %d", 1657 dev->ud_addr, dev->ud_depth, dev->ud_powersrc->up_portno, 1658 dev->ud_speed); 1659 1660 if (sc->sc_dying) 1661 return USBD_IOERROR; 1662 1663 /* Root Hub */ 1664 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1665 switch (ed->bEndpointAddress) { 1666 case USB_CONTROL_ENDPOINT: 1667 pipe->up_methods = &roothub_ctrl_methods; 1668 break; 1669 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1670 pipe->up_methods = &xhci_root_intr_methods; 1671 break; 1672 default: 1673 pipe->up_methods = NULL; 1674 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1675 ed->bEndpointAddress, 0, 0, 0); 1676 return USBD_INVAL; 1677 } 1678 return USBD_NORMAL_COMPLETION; 1679 } 1680 1681 switch (xfertype) { 1682 case UE_CONTROL: 1683 pipe->up_methods = &xhci_device_ctrl_methods; 1684 break; 1685 case UE_ISOCHRONOUS: 1686 pipe->up_methods = &xhci_device_isoc_methods; 1687 return USBD_INVAL; 1688 break; 1689 case UE_BULK: 1690 pipe->up_methods = &xhci_device_bulk_methods; 1691 break; 1692 case UE_INTERRUPT: 1693 pipe->up_methods = &xhci_device_intr_methods; 1694 break; 1695 default: 1696 return USBD_IOERROR; 1697 break; 1698 } 1699 1700 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1701 return xhci_configure_endpoint(pipe); 1702 1703 return USBD_NORMAL_COMPLETION; 1704 } 1705 1706 /* 1707 * Closes pipe, called from usbd_kill_pipe via close methods. 1708 * If the endpoint to be closed is ep0, disable_slot. 1709 * Should be called with sc_lock held. 1710 */ 1711 static void 1712 xhci_close_pipe(struct usbd_pipe *pipe) 1713 { 1714 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1715 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1716 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1717 const u_int dci = xhci_ep_get_dci(ed); 1718 struct xhci_trb trb; 1719 uint32_t *cp; 1720 1721 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1722 1723 if (sc->sc_dying) 1724 return; 1725 1726 /* xs is uninitialized before xhci_init_slot */ 1727 if (xs == NULL || xs->xs_idx == 0) 1728 return; 1729 1730 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1731 1732 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1733 KASSERT(mutex_owned(&sc->sc_lock)); 1734 1735 if (pipe->up_dev->ud_depth == 0) 1736 return; 1737 1738 if (dci == XHCI_DCI_EP_CONTROL) { 1739 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1740 xhci_disable_slot(sc, xs->xs_idx); 1741 return; 1742 } 1743 1744 /* 1745 * This may fail in the case that xhci_close_pipe is called after 1746 * xhci_abort_xfer e.g. usbd_kill_pipe. 1747 */ 1748 (void)xhci_stop_endpoint(pipe); 1749 1750 /* 1751 * set appropriate bit to be dropped. 1752 * don't set DC bit to 1, otherwise all endpoints 1753 * would be deconfigured. 1754 */ 1755 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1756 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1757 cp[1] = htole32(0); 1758 1759 /* XXX should be most significant one, not dci? */ 1760 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1761 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1762 1763 /* sync input contexts before they are read from memory */ 1764 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1765 1766 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1767 trb.trb_2 = 0; 1768 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1769 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1770 1771 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1772 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1773 } 1774 1775 /* 1776 * Abort transfer. 1777 * Called with sc_lock held. 1778 * May be called from softintr context. 1779 */ 1780 static void 1781 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1782 { 1783 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1784 1785 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1786 DPRINTFN(4, "xfer %p pipe %p status %d", 1787 xfer, xfer->ux_pipe, status, 0); 1788 1789 KASSERT(mutex_owned(&sc->sc_lock)); 1790 1791 if (sc->sc_dying) { 1792 /* If we're dying, just do the software part. */ 1793 DPRINTFN(4, "dying", 0, 0, 0, 0); 1794 xfer->ux_status = status; /* make software ignore it */ 1795 callout_stop(&xfer->ux_callout); 1796 usb_transfer_complete(xfer); 1797 return; 1798 } 1799 1800 /* XXX need more stuff */ 1801 xfer->ux_status = status; 1802 callout_stop(&xfer->ux_callout); 1803 usb_transfer_complete(xfer); 1804 DPRINTFN(14, "end", 0, 0, 0, 0); 1805 1806 KASSERT(mutex_owned(&sc->sc_lock)); 1807 } 1808 1809 /* 1810 * Recover STALLed endpoint. 1811 * xHCI 1.1 sect 4.10.2.1 1812 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1813 * all transfers on transfer ring. 1814 * These are done in thread context asynchronously. 1815 */ 1816 static void 1817 xhci_clear_endpoint_stall_async_task(void *cookie) 1818 { 1819 struct usbd_xfer * const xfer = cookie; 1820 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1821 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1822 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1823 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1824 1825 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1826 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1827 1828 xhci_reset_endpoint(xfer->ux_pipe); 1829 xhci_set_dequeue(xfer->ux_pipe); 1830 1831 mutex_enter(&sc->sc_lock); 1832 tr->is_halted = false; 1833 usb_transfer_complete(xfer); 1834 mutex_exit(&sc->sc_lock); 1835 DPRINTFN(4, "ends", 0, 0, 0, 0); 1836 } 1837 1838 static usbd_status 1839 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1840 { 1841 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1842 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1843 1844 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1845 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1846 1847 if (sc->sc_dying) { 1848 return USBD_IOERROR; 1849 } 1850 1851 usb_init_task(&xp->xp_async_task, 1852 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1853 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1854 DPRINTFN(4, "ends", 0, 0, 0, 0); 1855 1856 return USBD_NORMAL_COMPLETION; 1857 } 1858 1859 /* Process roothub port status/change events and notify to uhub_intr. */ 1860 static void 1861 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1862 { 1863 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1864 uint8_t *p; 1865 1866 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1867 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1868 port, 0, 0); 1869 1870 if (xfer == NULL) 1871 return; 1872 1873 if (port > sc->sc_maxports) 1874 return; 1875 1876 p = xfer->ux_buf; 1877 memset(p, 0, xfer->ux_length); 1878 p[port/NBBY] |= 1 << (port%NBBY); 1879 xfer->ux_actlen = xfer->ux_length; 1880 xfer->ux_status = USBD_NORMAL_COMPLETION; 1881 usb_transfer_complete(xfer); 1882 } 1883 1884 /* Process Transfer Events */ 1885 static void 1886 xhci_event_transfer(struct xhci_softc * const sc, 1887 const struct xhci_trb * const trb) 1888 { 1889 uint64_t trb_0; 1890 uint32_t trb_2, trb_3; 1891 uint8_t trbcode; 1892 u_int slot, dci; 1893 struct xhci_slot *xs; 1894 struct xhci_ring *xr; 1895 struct xhci_xfer *xx; 1896 struct usbd_xfer *xfer; 1897 usbd_status err; 1898 1899 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1900 1901 trb_0 = le64toh(trb->trb_0); 1902 trb_2 = le32toh(trb->trb_2); 1903 trb_3 = le32toh(trb->trb_3); 1904 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1905 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1906 dci = XHCI_TRB_3_EP_GET(trb_3); 1907 xs = &sc->sc_slots[slot]; 1908 xr = &xs->xs_ep[dci].xe_tr; 1909 1910 /* sanity check */ 1911 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1912 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1913 1914 int idx = 0; 1915 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1916 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1917 DPRINTFN(0, "invalid trb_0 0x%"PRIx64, trb_0, 0, 0, 0); 1918 return; 1919 } 1920 xx = xr->xr_cookies[idx]; 1921 1922 /* 1923 * If endpoint is stopped between TDs, TRB pointer points at 1924 * next TRB, however, it is not put yet or is a garbage TRB. 1925 * That's why xr_cookies may be NULL or look like broken. 1926 * Note: this ev happens only when hciversion >= 1.0 or 1927 * hciversion == 0.96 and FSE of hcc1 is set. 1928 */ 1929 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1930 DPRINTFN(1, "xx NULL: #%u: cookie %p: code %u trb_0 %" 1931 PRIx64, idx, xx, trbcode, trb_0); 1932 } 1933 } else { 1934 /* When ED != 0, trb_0 is kaddr of struct xhci_xfer. */ 1935 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1936 } 1937 /* XXX this may not happen */ 1938 if (xx == NULL) { 1939 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1940 return; 1941 } 1942 xfer = &xx->xx_xfer; 1943 /* XXX this may happen when detaching */ 1944 if (xfer == NULL) { 1945 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1946 xx, trb_0, 0, 0); 1947 return; 1948 } 1949 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1950 /* XXX I dunno why this happens */ 1951 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1952 1953 if (!xfer->ux_pipe->up_repeat && 1954 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1955 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1956 return; 1957 } 1958 1959 /* 4.11.5.2 Event Data TRB */ 1960 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1961 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1962 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1963 if ((trb_0 & 0x3) == 0x3) { 1964 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1965 } 1966 } 1967 1968 switch (trbcode) { 1969 case XHCI_TRB_ERROR_SHORT_PKT: 1970 case XHCI_TRB_ERROR_SUCCESS: 1971 xfer->ux_actlen = 1972 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1973 err = USBD_NORMAL_COMPLETION; 1974 break; 1975 case XHCI_TRB_ERROR_STALL: 1976 case XHCI_TRB_ERROR_BABBLE: 1977 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1978 xr->is_halted = true; 1979 err = USBD_STALLED; 1980 /* 1981 * Stalled endpoints can be recoverd by issuing 1982 * command TRB TYPE_RESET_EP on xHCI instead of 1983 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1984 * on the endpoint. However, this function may be 1985 * called from softint context (e.g. from umass), 1986 * in that case driver gets KASSERT in cv_timedwait 1987 * in xhci_do_command. 1988 * To avoid this, this runs reset_endpoint and 1989 * usb_transfer_complete in usb task thread 1990 * asynchronously (and then umass issues clear 1991 * UF_ENDPOINT_HALT). 1992 */ 1993 xfer->ux_status = err; 1994 xhci_clear_endpoint_stall_async(xfer); 1995 return; 1996 default: 1997 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1998 err = USBD_IOERROR; 1999 break; 2000 } 2001 xfer->ux_status = err; 2002 2003 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 2004 if ((trb_0 & 0x3) == 0x0) { 2005 callout_stop(&xfer->ux_callout); 2006 usb_transfer_complete(xfer); 2007 } 2008 } else { 2009 callout_stop(&xfer->ux_callout); 2010 usb_transfer_complete(xfer); 2011 } 2012 } 2013 2014 /* Process Command complete events */ 2015 static void 2016 xhci_event_cmd(struct xhci_softc * const sc, 2017 const struct xhci_trb * const trb) 2018 { 2019 uint64_t trb_0; 2020 uint32_t trb_2, trb_3; 2021 2022 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2023 2024 trb_0 = le64toh(trb->trb_0); 2025 trb_2 = le32toh(trb->trb_2); 2026 trb_3 = le32toh(trb->trb_3); 2027 2028 if (trb_0 == sc->sc_command_addr) { 2029 sc->sc_result_trb.trb_0 = trb_0; 2030 sc->sc_result_trb.trb_2 = trb_2; 2031 sc->sc_result_trb.trb_3 = trb_3; 2032 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2033 XHCI_TRB_ERROR_SUCCESS) { 2034 DPRINTFN(1, "command completion " 2035 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 2036 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 2037 } 2038 cv_signal(&sc->sc_command_cv); 2039 } else { 2040 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 2041 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 2042 trb_2, trb_3); 2043 } 2044 } 2045 2046 /* 2047 * Process events. 2048 * called from xhci_softintr 2049 */ 2050 static void 2051 xhci_handle_event(struct xhci_softc * const sc, 2052 const struct xhci_trb * const trb) 2053 { 2054 uint64_t trb_0; 2055 uint32_t trb_2, trb_3; 2056 2057 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2058 2059 trb_0 = le64toh(trb->trb_0); 2060 trb_2 = le32toh(trb->trb_2); 2061 trb_3 = le32toh(trb->trb_3); 2062 2063 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2064 trb, trb_0, trb_2, trb_3); 2065 2066 /* 2067 * 4.11.3.1, 6.4.2.1 2068 * TRB Pointer is invalid for these completion codes. 2069 */ 2070 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2071 case XHCI_TRB_ERROR_RING_UNDERRUN: 2072 case XHCI_TRB_ERROR_RING_OVERRUN: 2073 case XHCI_TRB_ERROR_VF_RING_FULL: 2074 return; 2075 default: 2076 if (trb_0 == 0) { 2077 return; 2078 } 2079 break; 2080 } 2081 2082 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2083 case XHCI_TRB_EVENT_TRANSFER: 2084 xhci_event_transfer(sc, trb); 2085 break; 2086 case XHCI_TRB_EVENT_CMD_COMPLETE: 2087 xhci_event_cmd(sc, trb); 2088 break; 2089 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2090 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2091 break; 2092 default: 2093 break; 2094 } 2095 } 2096 2097 static void 2098 xhci_softintr(void *v) 2099 { 2100 struct usbd_bus * const bus = v; 2101 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2102 struct xhci_ring * const er = &sc->sc_er; 2103 struct xhci_trb *trb; 2104 int i, j, k; 2105 2106 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2107 2108 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2109 2110 i = er->xr_ep; 2111 j = er->xr_cs; 2112 2113 DPRINTFN(16, "xr_ep %d xr_cs %d", i, j, 0, 0); 2114 2115 while (1) { 2116 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2117 BUS_DMASYNC_POSTREAD); 2118 trb = &er->xr_trb[i]; 2119 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2120 2121 if (j != k) 2122 break; 2123 2124 xhci_handle_event(sc, trb); 2125 2126 i++; 2127 if (i == XHCI_EVENT_RING_TRBS) { 2128 i = 0; 2129 j ^= 1; 2130 } 2131 } 2132 2133 er->xr_ep = i; 2134 er->xr_cs = j; 2135 2136 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2137 XHCI_ERDP_LO_BUSY); 2138 2139 DPRINTFN(16, "ends", 0, 0, 0, 0); 2140 2141 return; 2142 } 2143 2144 static void 2145 xhci_poll(struct usbd_bus *bus) 2146 { 2147 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2148 2149 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2150 2151 mutex_spin_enter(&sc->sc_intr_lock); 2152 xhci_intr1(sc); 2153 mutex_spin_exit(&sc->sc_intr_lock); 2154 2155 return; 2156 } 2157 2158 static struct usbd_xfer * 2159 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2160 { 2161 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2162 struct usbd_xfer *xfer; 2163 2164 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2165 2166 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 2167 if (xfer != NULL) { 2168 memset(xfer, 0, sizeof(struct xhci_xfer)); 2169 #ifdef DIAGNOSTIC 2170 xfer->ux_state = XFER_BUSY; 2171 #endif 2172 } 2173 2174 return xfer; 2175 } 2176 2177 static void 2178 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2179 { 2180 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2181 2182 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2183 2184 #ifdef DIAGNOSTIC 2185 if (xfer->ux_state != XFER_BUSY) { 2186 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 2187 xfer, xfer->ux_state, 0, 0); 2188 } 2189 xfer->ux_state = XFER_FREE; 2190 #endif 2191 pool_cache_put(sc->sc_xferpool, xfer); 2192 } 2193 2194 static void 2195 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2196 { 2197 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2198 2199 *lock = &sc->sc_lock; 2200 } 2201 2202 extern uint32_t usb_cookie_no; 2203 2204 /* 2205 * xHCI 4.3 2206 * Called when uhub_explore finds a new device (via usbd_new_device). 2207 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2208 * This function does: 2209 * Allocate and construct dev structure of default endpoint (ep0). 2210 * Allocate and open pipe of ep0. 2211 * Enable slot and initialize slot context. 2212 * Set Address. 2213 * Read initial device descriptor. 2214 * Determine initial MaxPacketSize (mps) by speed. 2215 * Read full device descriptor. 2216 * Register this device. 2217 */ 2218 static usbd_status 2219 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2220 int speed, int port, struct usbd_port *up) 2221 { 2222 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2223 struct usbd_device *dev; 2224 usbd_status err; 2225 usb_device_descriptor_t *dd; 2226 struct usbd_device *hub; 2227 struct usbd_device *adev; 2228 int rhport = 0; 2229 struct xhci_slot *xs; 2230 uint32_t *cp; 2231 uint32_t route = 0; 2232 uint8_t slot = 0; 2233 uint8_t addr; 2234 2235 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2236 DPRINTFN(4, "port=%d depth=%d speed=%d upport %d", 2237 port, depth, speed, up->up_portno); 2238 2239 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2240 if (dev == NULL) 2241 return USBD_NOMEM; 2242 2243 dev->ud_bus = bus; 2244 2245 /* Set up default endpoint handle. */ 2246 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2247 2248 /* Set up default endpoint descriptor. */ 2249 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2250 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2251 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2252 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2253 /* 4.3, 4.8.2.1 */ 2254 switch (speed) { 2255 case USB_SPEED_SUPER: 2256 case USB_SPEED_SUPER_PLUS: 2257 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2258 break; 2259 case USB_SPEED_FULL: 2260 /* XXX using 64 as initial mps of ep0 in FS */ 2261 case USB_SPEED_HIGH: 2262 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2263 break; 2264 case USB_SPEED_LOW: 2265 default: 2266 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2267 break; 2268 } 2269 dev->ud_ep0desc.bInterval = 0; 2270 2271 /* doesn't matter, just don't let it uninitialized */ 2272 dev->ud_ep0.ue_toggle = 0; 2273 2274 DPRINTFN(4, "up %p portno %d", up, up->up_portno, 0, 0); 2275 2276 dev->ud_quirks = &usbd_no_quirk; 2277 dev->ud_addr = 0; 2278 dev->ud_ddesc.bMaxPacketSize = 0; 2279 dev->ud_depth = depth; 2280 dev->ud_powersrc = up; 2281 dev->ud_myhub = up->up_parent; 2282 2283 up->up_dev = dev; 2284 2285 /* Locate root hub port */ 2286 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2287 uint32_t dep; 2288 2289 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2290 hub, hub->ud_depth, hub->ud_powersrc, 2291 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2292 2293 if (hub->ud_powersrc == NULL) 2294 break; 2295 dep = hub->ud_depth; 2296 if (dep == 0) 2297 break; 2298 rhport = hub->ud_powersrc->up_portno; 2299 if (dep > USB_HUB_MAX_DEPTH) 2300 continue; 2301 2302 route |= 2303 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2304 << ((dep - 1) * 4); 2305 } 2306 route = route >> 4; 2307 DPRINTFN(4, "rhport %d Route %05x hub %p", rhport, route, hub, 0); 2308 2309 /* Locate port on upstream high speed hub */ 2310 for (adev = dev, hub = up->up_parent; 2311 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2312 adev = hub, hub = hub->ud_myhub) 2313 ; 2314 if (hub) { 2315 int p; 2316 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2317 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2318 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2319 goto found; 2320 } 2321 } 2322 panic("xhci_new_device: cannot find HS port"); 2323 found: 2324 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2325 } else { 2326 dev->ud_myhsport = NULL; 2327 } 2328 2329 dev->ud_speed = speed; 2330 dev->ud_langid = USBD_NOLANG; 2331 dev->ud_cookie.cookie = ++usb_cookie_no; 2332 2333 /* Establish the default pipe. */ 2334 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2335 &dev->ud_pipe0); 2336 if (err) { 2337 goto bad; 2338 } 2339 2340 dd = &dev->ud_ddesc; 2341 2342 if ((depth == 0) && (port == 0)) { 2343 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2344 bus->ub_devices[dev->ud_addr] = dev; 2345 err = usbd_get_initial_ddesc(dev, dd); 2346 if (err) 2347 goto bad; 2348 err = usbd_reload_device_desc(dev); 2349 if (err) 2350 goto bad; 2351 } else { 2352 err = xhci_enable_slot(sc, &slot); 2353 if (err) 2354 goto bad; 2355 xs = &sc->sc_slots[slot]; 2356 dev->ud_hcpriv = xs; 2357 err = xhci_init_slot(dev, slot, route, rhport); 2358 if (err) { 2359 dev->ud_hcpriv = NULL; 2360 /* 2361 * We have to disable_slot here because 2362 * xs->xs_idx == 0 when xhci_init_slot fails, 2363 * in that case usbd_remove_dev won't work. 2364 */ 2365 mutex_enter(&sc->sc_lock); 2366 xhci_disable_slot(sc, slot); 2367 mutex_exit(&sc->sc_lock); 2368 goto bad; 2369 } 2370 2371 /* Allow device time to set new address */ 2372 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2373 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2374 //hexdump("slot context", cp, sc->sc_ctxsz); 2375 addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2376 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2377 /* XXX ensure we know when the hardware does something 2378 we can't yet cope with */ 2379 KASSERT(addr >= 1 && addr <= 127); 2380 dev->ud_addr = addr; 2381 /* XXX dev->ud_addr not necessarily unique on bus */ 2382 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2383 bus->ub_devices[dev->ud_addr] = dev; 2384 2385 err = usbd_get_initial_ddesc(dev, dd); 2386 if (err) 2387 goto bad; 2388 /* 4.8.2.1 */ 2389 if (USB_IS_SS(speed)) { 2390 if (dd->bMaxPacketSize != 9) { 2391 printf("%s: invalid mps 2^%u for SS ep0," 2392 " using 512\n", 2393 device_xname(sc->sc_dev), 2394 dd->bMaxPacketSize); 2395 dd->bMaxPacketSize = 9; 2396 } 2397 USETW(dev->ud_ep0desc.wMaxPacketSize, 2398 (1 << dd->bMaxPacketSize)); 2399 } else 2400 USETW(dev->ud_ep0desc.wMaxPacketSize, 2401 dd->bMaxPacketSize); 2402 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2403 xhci_update_ep0_mps(sc, xs, 2404 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2405 err = usbd_reload_device_desc(dev); 2406 if (err) 2407 goto bad; 2408 } 2409 2410 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2411 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2412 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2413 dd->bDeviceClass, dd->bDeviceSubClass, 2414 dd->bDeviceProtocol, 0); 2415 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2416 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2417 dev->ud_speed); 2418 2419 usbd_get_device_strings(dev); 2420 2421 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2422 2423 if ((depth == 0) && (port == 0)) { 2424 usbd_attach_roothub(parent, dev); 2425 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2426 return USBD_NORMAL_COMPLETION; 2427 } 2428 2429 2430 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2431 bad: 2432 if (err != USBD_NORMAL_COMPLETION) { 2433 usbd_remove_device(dev, up); 2434 } 2435 2436 return err; 2437 } 2438 2439 static usbd_status 2440 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2441 size_t ntrb, size_t align) 2442 { 2443 usbd_status err; 2444 size_t size = ntrb * XHCI_TRB_SIZE; 2445 2446 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2447 2448 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2449 if (err) 2450 return err; 2451 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2452 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2453 xr->xr_trb = xhci_ring_trbv(xr, 0); 2454 xr->xr_ntrb = ntrb; 2455 xr->xr_ep = 0; 2456 xr->xr_cs = 1; 2457 memset(xr->xr_trb, 0, size); 2458 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 2459 xr->is_halted = false; 2460 2461 return USBD_NORMAL_COMPLETION; 2462 } 2463 2464 static void 2465 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2466 { 2467 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2468 mutex_destroy(&xr->xr_lock); 2469 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2470 } 2471 2472 static void 2473 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2474 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2475 { 2476 size_t i; 2477 u_int ri; 2478 u_int cs; 2479 uint64_t parameter; 2480 uint32_t status; 2481 uint32_t control; 2482 2483 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2484 2485 KASSERT(ntrbs <= XHCI_XFER_NTRB); 2486 for (i = 0; i < ntrbs; i++) { 2487 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2488 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2489 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2490 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2491 XHCI_TRB_TYPE_LINK); 2492 } 2493 2494 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2495 2496 ri = xr->xr_ep; 2497 cs = xr->xr_cs; 2498 2499 /* 2500 * Although the xhci hardware can do scatter/gather dma from 2501 * arbitrary sized buffers, there is a non-obvious restriction 2502 * that a LINK trb is only allowed at the end of a burst of 2503 * transfers - which might be 16kB. 2504 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2505 * The simple solution is not to allow a LINK trb in the middle 2506 * of anything - as here. 2507 * XXX: (dsl) There are xhci controllers out there (eg some made by 2508 * ASMedia) that seem to lock up if they process a LINK trb but 2509 * cannot process the linked-to trb yet. 2510 * The code should write the 'cycle' bit on the link trb AFTER 2511 * adding the other trb. 2512 */ 2513 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2514 parameter = xhci_ring_trbp(xr, 0); 2515 status = 0; 2516 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2517 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2518 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2519 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2520 BUS_DMASYNC_PREWRITE); 2521 xr->xr_cookies[ri] = NULL; 2522 xr->xr_ep = 0; 2523 xr->xr_cs ^= 1; 2524 ri = xr->xr_ep; 2525 cs = xr->xr_cs; 2526 } 2527 2528 ri++; 2529 2530 /* Write any subsequent TRB first */ 2531 for (i = 1; i < ntrbs; i++) { 2532 parameter = trbs[i].trb_0; 2533 status = trbs[i].trb_2; 2534 control = trbs[i].trb_3; 2535 2536 if (cs) { 2537 control |= XHCI_TRB_3_CYCLE_BIT; 2538 } else { 2539 control &= ~XHCI_TRB_3_CYCLE_BIT; 2540 } 2541 2542 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2543 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2544 BUS_DMASYNC_PREWRITE); 2545 xr->xr_cookies[ri] = cookie; 2546 ri++; 2547 } 2548 2549 /* Write the first TRB last */ 2550 i = 0; 2551 parameter = trbs[i].trb_0; 2552 status = trbs[i].trb_2; 2553 control = trbs[i].trb_3; 2554 2555 if (xr->xr_cs) { 2556 control |= XHCI_TRB_3_CYCLE_BIT; 2557 } else { 2558 control &= ~XHCI_TRB_3_CYCLE_BIT; 2559 } 2560 2561 xhci_trb_put(&xr->xr_trb[xr->xr_ep], parameter, status, control); 2562 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * xr->xr_ep, XHCI_TRB_SIZE * 1, 2563 BUS_DMASYNC_PREWRITE); 2564 xr->xr_cookies[xr->xr_ep] = cookie; 2565 2566 xr->xr_ep = ri; 2567 xr->xr_cs = cs; 2568 2569 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2570 } 2571 2572 /* 2573 * Stop execution commands, purge all commands on command ring, and 2574 * rewind enqueue pointer. 2575 */ 2576 static void 2577 xhci_abort_command(struct xhci_softc *sc) 2578 { 2579 struct xhci_ring * const cr = &sc->sc_cr; 2580 uint64_t crcr; 2581 int i; 2582 2583 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2584 DPRINTFN(14, "command %#"PRIx64" timeout, aborting", 2585 sc->sc_command_addr, 0, 0, 0); 2586 2587 mutex_enter(&cr->xr_lock); 2588 2589 /* 4.6.1.2 Aborting a Command */ 2590 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2591 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2592 2593 for (i = 0; i < 500; i++) { 2594 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2595 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2596 break; 2597 usb_delay_ms(&sc->sc_bus, 1); 2598 } 2599 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2600 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2601 /* reset HC here? */ 2602 } 2603 2604 /* reset command ring dequeue pointer */ 2605 cr->xr_ep = 0; 2606 cr->xr_cs = 1; 2607 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2608 2609 mutex_exit(&cr->xr_lock); 2610 } 2611 2612 /* 2613 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2614 * Command completion is notified by cv_signal from xhci_handle_event 2615 * (called from interrupt from xHCI), or timed-out. 2616 * Command validation is performed in xhci_handle_event by checking if 2617 * trb_0 in CMD_COMPLETE TRB and sc->sc_command_addr are identical. 2618 */ 2619 static usbd_status 2620 xhci_do_command_locked(struct xhci_softc * const sc, struct xhci_trb * const trb, 2621 int timeout) 2622 { 2623 struct xhci_ring * const cr = &sc->sc_cr; 2624 usbd_status err; 2625 2626 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2627 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2628 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2629 2630 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2631 KASSERT(mutex_owned(&sc->sc_lock)); 2632 2633 /* XXX KASSERT may fire when cv_timedwait unlocks sc_lock */ 2634 KASSERT(sc->sc_command_addr == 0); 2635 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2636 2637 mutex_enter(&cr->xr_lock); 2638 xhci_ring_put(sc, cr, NULL, trb, 1); 2639 mutex_exit(&cr->xr_lock); 2640 2641 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2642 2643 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2644 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2645 xhci_abort_command(sc); 2646 err = USBD_TIMEOUT; 2647 goto timedout; 2648 } 2649 2650 trb->trb_0 = sc->sc_result_trb.trb_0; 2651 trb->trb_2 = sc->sc_result_trb.trb_2; 2652 trb->trb_3 = sc->sc_result_trb.trb_3; 2653 2654 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2655 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2656 2657 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2658 case XHCI_TRB_ERROR_SUCCESS: 2659 err = USBD_NORMAL_COMPLETION; 2660 break; 2661 default: 2662 case 192 ... 223: 2663 err = USBD_IOERROR; 2664 break; 2665 case 224 ... 255: 2666 err = USBD_NORMAL_COMPLETION; 2667 break; 2668 } 2669 2670 timedout: 2671 sc->sc_command_addr = 0; 2672 return err; 2673 } 2674 2675 static usbd_status 2676 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2677 int timeout) 2678 { 2679 2680 mutex_enter(&sc->sc_lock); 2681 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2682 mutex_exit(&sc->sc_lock); 2683 2684 return ret; 2685 } 2686 2687 static usbd_status 2688 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2689 { 2690 struct xhci_trb trb; 2691 usbd_status err; 2692 2693 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2694 2695 trb.trb_0 = 0; 2696 trb.trb_2 = 0; 2697 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2698 2699 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2700 if (err != USBD_NORMAL_COMPLETION) { 2701 return err; 2702 } 2703 2704 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2705 2706 return err; 2707 } 2708 2709 /* 2710 * xHCI 4.6.4 2711 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2712 * All endpoints in the slot should be stopped. 2713 * Should be called with sc_lock held. 2714 */ 2715 static usbd_status 2716 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2717 { 2718 struct xhci_trb trb; 2719 struct xhci_slot *xs; 2720 usbd_status err; 2721 2722 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2723 2724 if (sc->sc_dying) 2725 return USBD_IOERROR; 2726 2727 trb.trb_0 = 0; 2728 trb.trb_2 = 0; 2729 trb.trb_3 = htole32( 2730 XHCI_TRB_3_SLOT_SET(slot) | 2731 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2732 2733 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2734 2735 if (!err) { 2736 xs = &sc->sc_slots[slot]; 2737 if (xs->xs_idx != 0) { 2738 for (int i = XHCI_DCI_SLOT + 1; i < 32; i++) { 2739 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2740 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2741 } 2742 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2743 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2744 xhci_set_dcba(sc, 0, slot); 2745 memset(xs, 0, sizeof(*xs)); 2746 } 2747 } 2748 2749 return err; 2750 } 2751 2752 /* 2753 * Set address of device and transition slot state from ENABLED to ADDRESSED 2754 * if Block Setaddress Request (BSR) is false. 2755 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2756 * see xHCI 1.1 4.5.3, 3.3.4 2757 * Should be called without sc_lock held. 2758 */ 2759 static usbd_status 2760 xhci_address_device(struct xhci_softc * const sc, 2761 uint64_t icp, uint8_t slot_id, bool bsr) 2762 { 2763 struct xhci_trb trb; 2764 usbd_status err; 2765 2766 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2767 2768 trb.trb_0 = icp; 2769 trb.trb_2 = 0; 2770 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2771 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2772 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2773 2774 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2775 2776 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2777 err = USBD_NO_ADDR; 2778 2779 return err; 2780 } 2781 2782 static usbd_status 2783 xhci_update_ep0_mps(struct xhci_softc * const sc, 2784 struct xhci_slot * const xs, u_int mps) 2785 { 2786 struct xhci_trb trb; 2787 usbd_status err; 2788 uint32_t * cp; 2789 2790 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2791 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2792 2793 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2794 cp[0] = htole32(0); 2795 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2796 2797 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2798 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2799 2800 /* sync input contexts before they are read from memory */ 2801 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2802 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2803 sc->sc_ctxsz * 4); 2804 2805 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2806 trb.trb_2 = 0; 2807 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2808 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2809 2810 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2811 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2812 return err; 2813 } 2814 2815 static void 2816 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2817 { 2818 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2819 2820 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2821 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2822 &dcbaa[si], dcba, si, 0); 2823 2824 dcbaa[si] = htole64(dcba); 2825 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2826 BUS_DMASYNC_PREWRITE); 2827 } 2828 2829 /* 2830 * Allocate DMA buffer and ring buffer for specified slot 2831 * and set Device Context Base Address 2832 * and issue Set Address device command. 2833 */ 2834 static usbd_status 2835 xhci_init_slot(struct usbd_device *dev, uint32_t slot, uint32_t route, int rhport) 2836 { 2837 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2838 struct xhci_slot *xs; 2839 usbd_status err; 2840 u_int dci; 2841 uint32_t *cp; 2842 uint32_t mps = UGETW(dev->ud_ep0desc.wMaxPacketSize); 2843 2844 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2845 DPRINTFN(4, "slot %u speed %d route %05x rhport %d", 2846 slot, dev->ud_speed, route, rhport); 2847 2848 xs = &sc->sc_slots[slot]; 2849 2850 /* allocate contexts */ 2851 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2852 &xs->xs_dc_dma); 2853 if (err) 2854 return err; 2855 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2856 2857 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2858 &xs->xs_ic_dma); 2859 if (err) 2860 goto bad1; 2861 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2862 2863 for (dci = 0; dci < 32; dci++) { 2864 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2865 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2866 if (dci == XHCI_DCI_SLOT) 2867 continue; 2868 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2869 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2870 if (err) { 2871 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2872 goto bad2; 2873 } 2874 } 2875 2876 /* set up initial input control context */ 2877 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2878 cp[0] = htole32(0); 2879 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)| 2880 XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2881 2882 /* set up input slot context */ 2883 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2884 xhci_setup_sctx(dev, cp); 2885 cp[0] |= htole32(XHCI_SCTX_0_CTX_NUM_SET(1)); 2886 cp[0] |= htole32(XHCI_SCTX_0_ROUTE_SET(route)); 2887 cp[1] |= htole32(XHCI_SCTX_1_RH_PORT_SET(rhport)); 2888 2889 /* set up input EP0 context */ 2890 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2891 cp[0] = htole32(0); 2892 cp[1] = htole32( 2893 XHCI_EPCTX_1_MAXP_SIZE_SET(mps) | 2894 XHCI_EPCTX_1_EPTYPE_SET(4) | 2895 XHCI_EPCTX_1_CERR_SET(3) 2896 ); 2897 /* can't use xhci_ep_get_dci() yet? */ 2898 *(uint64_t *)(&cp[2]) = htole64( 2899 xhci_ring_trbp(&xs->xs_ep[XHCI_DCI_EP_CONTROL].xe_tr, 0) | 2900 XHCI_EPCTX_2_DCS_SET(1)); 2901 cp[4] = htole32( 2902 XHCI_EPCTX_4_AVG_TRB_LEN_SET(8) 2903 ); 2904 2905 /* sync input contexts before they are read from memory */ 2906 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2907 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2908 sc->sc_ctxsz * 3); 2909 2910 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2911 2912 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, 2913 false); 2914 2915 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2916 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2917 sc->sc_ctxsz * 2); 2918 2919 bad2: 2920 if (err == USBD_NORMAL_COMPLETION) { 2921 xs->xs_idx = slot; 2922 } else { 2923 for (int i = 1; i < dci; i++) { 2924 xhci_ring_free(sc, &xs->xs_ep[i].xe_tr); 2925 memset(&xs->xs_ep[i], 0, sizeof(xs->xs_ep[i])); 2926 } 2927 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2928 bad1: 2929 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2930 xs->xs_idx = 0; 2931 } 2932 2933 return err; 2934 } 2935 2936 /* ----- */ 2937 2938 static void 2939 xhci_noop(struct usbd_pipe *pipe) 2940 { 2941 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2942 } 2943 2944 /* 2945 * Process root hub request. 2946 */ 2947 static int 2948 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2949 void *buf, int buflen) 2950 { 2951 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2952 usb_port_status_t ps; 2953 int l, totlen = 0; 2954 uint16_t len, value, index; 2955 int port, i; 2956 uint32_t v; 2957 2958 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2959 2960 if (sc->sc_dying) 2961 return -1; 2962 2963 len = UGETW(req->wLength); 2964 value = UGETW(req->wValue); 2965 index = UGETW(req->wIndex); 2966 2967 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 2968 req->bmRequestType | (req->bRequest << 8), value, index, len); 2969 2970 #define C(x,y) ((x) | ((y) << 8)) 2971 switch (C(req->bRequest, req->bmRequestType)) { 2972 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2973 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 2974 if (len == 0) 2975 break; 2976 switch (value) { 2977 case C(0, UDESC_DEVICE): { 2978 usb_device_descriptor_t devd; 2979 totlen = min(buflen, sizeof(devd)); 2980 memcpy(&devd, buf, totlen); 2981 USETW(devd.idVendor, sc->sc_id_vendor); 2982 memcpy(buf, &devd, totlen); 2983 break; 2984 } 2985 #define sd ((usb_string_descriptor_t *)buf) 2986 case C(1, UDESC_STRING): 2987 /* Vendor */ 2988 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2989 break; 2990 case C(2, UDESC_STRING): 2991 /* Product */ 2992 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 2993 break; 2994 #undef sd 2995 default: 2996 /* default from usbroothub */ 2997 return buflen; 2998 } 2999 break; 3000 3001 /* Hub requests */ 3002 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3003 break; 3004 /* Clear Port Feature request */ 3005 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3006 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 3007 index, value, 0, 0); 3008 if (index < 1 || index > sc->sc_maxports) { 3009 return -1; 3010 } 3011 port = XHCI_PORTSC(index); 3012 v = xhci_op_read_4(sc, port); 3013 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3014 v &= ~XHCI_PS_CLEAR; 3015 switch (value) { 3016 case UHF_PORT_ENABLE: 3017 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3018 break; 3019 case UHF_PORT_SUSPEND: 3020 return -1; 3021 case UHF_PORT_POWER: 3022 break; 3023 case UHF_PORT_TEST: 3024 case UHF_PORT_INDICATOR: 3025 return -1; 3026 case UHF_C_PORT_CONNECTION: 3027 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3028 break; 3029 case UHF_C_PORT_ENABLE: 3030 case UHF_C_PORT_SUSPEND: 3031 case UHF_C_PORT_OVER_CURRENT: 3032 return -1; 3033 case UHF_C_BH_PORT_RESET: 3034 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3035 break; 3036 case UHF_C_PORT_RESET: 3037 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3038 break; 3039 case UHF_C_PORT_LINK_STATE: 3040 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3041 break; 3042 case UHF_C_PORT_CONFIG_ERROR: 3043 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3044 break; 3045 default: 3046 return -1; 3047 } 3048 break; 3049 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3050 if (len == 0) 3051 break; 3052 if ((value & 0xff) != 0) { 3053 return -1; 3054 } 3055 usb_hub_descriptor_t hubd; 3056 3057 totlen = min(buflen, sizeof(hubd)); 3058 memcpy(&hubd, buf, totlen); 3059 hubd.bNbrPorts = sc->sc_maxports; 3060 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3061 hubd.bPwrOn2PwrGood = 200; 3062 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 3063 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 3064 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3065 totlen = min(totlen, hubd.bDescLength); 3066 memcpy(buf, &hubd, totlen); 3067 break; 3068 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3069 if (len != 4) { 3070 return -1; 3071 } 3072 memset(buf, 0, len); /* ? XXX */ 3073 totlen = len; 3074 break; 3075 /* Get Port Status request */ 3076 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3077 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 3078 if (index < 1 || index > sc->sc_maxports) { 3079 return -1; 3080 } 3081 if (len != 4) { 3082 return -1; 3083 } 3084 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 3085 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 3086 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3087 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3088 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3089 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3090 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3091 if (v & XHCI_PS_PR) i |= UPS_RESET; 3092 if (v & XHCI_PS_PP) { 3093 if (i & UPS_OTHER_SPEED) 3094 i |= UPS_PORT_POWER_SS; 3095 else 3096 i |= UPS_PORT_POWER; 3097 } 3098 if (i & UPS_OTHER_SPEED) 3099 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3100 if (sc->sc_vendor_port_status) 3101 i = sc->sc_vendor_port_status(sc, v, i); 3102 USETW(ps.wPortStatus, i); 3103 i = 0; 3104 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3105 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3106 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3107 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3108 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3109 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3110 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3111 USETW(ps.wPortChange, i); 3112 totlen = min(len, sizeof(ps)); 3113 memcpy(buf, &ps, totlen); 3114 break; 3115 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3116 return -1; 3117 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3118 break; 3119 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3120 break; 3121 /* Set Port Feature request */ 3122 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3123 int optval = (index >> 8) & 0xff; 3124 index &= 0xff; 3125 if (index < 1 || index > sc->sc_maxports) { 3126 return -1; 3127 } 3128 port = XHCI_PORTSC(index); 3129 v = xhci_op_read_4(sc, port); 3130 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3131 v &= ~XHCI_PS_CLEAR; 3132 switch (value) { 3133 case UHF_PORT_ENABLE: 3134 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3135 break; 3136 case UHF_PORT_SUSPEND: 3137 /* XXX suspend */ 3138 break; 3139 case UHF_PORT_RESET: 3140 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3141 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3142 /* Wait for reset to complete. */ 3143 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3144 if (sc->sc_dying) { 3145 return -1; 3146 } 3147 v = xhci_op_read_4(sc, port); 3148 if (v & XHCI_PS_PR) { 3149 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3150 usb_delay_ms(&sc->sc_bus, 10); 3151 /* XXX */ 3152 } 3153 break; 3154 case UHF_PORT_POWER: 3155 /* XXX power control */ 3156 break; 3157 /* XXX more */ 3158 case UHF_C_PORT_RESET: 3159 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3160 break; 3161 case UHF_PORT_U1_TIMEOUT: 3162 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3163 return -1; 3164 } 3165 port = XHCI_PORTPMSC(index); 3166 v = xhci_op_read_4(sc, port); 3167 v &= ~XHCI_PM3_U1TO_SET(0xff); 3168 v |= XHCI_PM3_U1TO_SET(optval); 3169 xhci_op_write_4(sc, port, v); 3170 break; 3171 case UHF_PORT_U2_TIMEOUT: 3172 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3173 return -1; 3174 } 3175 port = XHCI_PORTPMSC(index); 3176 v = xhci_op_read_4(sc, port); 3177 v &= ~XHCI_PM3_U2TO_SET(0xff); 3178 v |= XHCI_PM3_U2TO_SET(optval); 3179 xhci_op_write_4(sc, port, v); 3180 break; 3181 default: 3182 return -1; 3183 } 3184 } 3185 break; 3186 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3187 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3188 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3189 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3190 break; 3191 default: 3192 /* default from usbroothub */ 3193 return buflen; 3194 } 3195 3196 return totlen; 3197 } 3198 3199 /* root hub interrupt */ 3200 3201 static usbd_status 3202 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3203 { 3204 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3205 usbd_status err; 3206 3207 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3208 3209 /* Insert last in queue. */ 3210 mutex_enter(&sc->sc_lock); 3211 err = usb_insert_transfer(xfer); 3212 mutex_exit(&sc->sc_lock); 3213 if (err) 3214 return err; 3215 3216 /* Pipe isn't running, start first */ 3217 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3218 } 3219 3220 /* Wait for roothub port status/change */ 3221 static usbd_status 3222 xhci_root_intr_start(struct usbd_xfer *xfer) 3223 { 3224 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3225 3226 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3227 3228 if (sc->sc_dying) 3229 return USBD_IOERROR; 3230 3231 mutex_enter(&sc->sc_lock); 3232 sc->sc_intrxfer = xfer; 3233 mutex_exit(&sc->sc_lock); 3234 3235 return USBD_IN_PROGRESS; 3236 } 3237 3238 static void 3239 xhci_root_intr_abort(struct usbd_xfer *xfer) 3240 { 3241 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3242 3243 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3244 3245 KASSERT(mutex_owned(&sc->sc_lock)); 3246 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3247 3248 sc->sc_intrxfer = NULL; 3249 3250 xfer->ux_status = USBD_CANCELLED; 3251 usb_transfer_complete(xfer); 3252 } 3253 3254 static void 3255 xhci_root_intr_close(struct usbd_pipe *pipe) 3256 { 3257 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3258 3259 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3260 3261 KASSERT(mutex_owned(&sc->sc_lock)); 3262 3263 sc->sc_intrxfer = NULL; 3264 } 3265 3266 static void 3267 xhci_root_intr_done(struct usbd_xfer *xfer) 3268 { 3269 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3270 3271 } 3272 3273 /* -------------- */ 3274 /* device control */ 3275 3276 static usbd_status 3277 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3278 { 3279 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3280 usbd_status err; 3281 3282 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3283 3284 /* Insert last in queue. */ 3285 mutex_enter(&sc->sc_lock); 3286 err = usb_insert_transfer(xfer); 3287 mutex_exit(&sc->sc_lock); 3288 if (err) 3289 return err; 3290 3291 /* Pipe isn't running, start first */ 3292 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3293 } 3294 3295 static usbd_status 3296 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3297 { 3298 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3299 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3300 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3301 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3302 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3303 usb_device_request_t * const req = &xfer->ux_request; 3304 const int isread = usbd_xfer_isread(xfer); 3305 const uint32_t len = UGETW(req->wLength); 3306 usb_dma_t * const dma = &xfer->ux_dmabuf; 3307 uint64_t parameter; 3308 uint32_t status; 3309 uint32_t control; 3310 u_int i; 3311 3312 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3313 DPRINTFN(12, "req: %04x %04x %04x %04x", 3314 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3315 UGETW(req->wIndex), UGETW(req->wLength)); 3316 3317 /* we rely on the bottom bits for extra info */ 3318 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 3319 3320 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3321 3322 i = 0; 3323 3324 /* setup phase */ 3325 memcpy(¶meter, req, sizeof(*req)); 3326 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3327 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3328 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3329 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3330 XHCI_TRB_3_IDT_BIT; 3331 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3332 3333 if (len != 0) { 3334 /* data phase */ 3335 parameter = DMAADDR(dma, 0); 3336 KASSERT(len <= 0x10000); 3337 status = XHCI_TRB_2_IRQ_SET(0) | 3338 XHCI_TRB_2_TDSZ_SET(1) | 3339 XHCI_TRB_2_BYTES_SET(len); 3340 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3341 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3342 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3343 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3344 3345 parameter = (uintptr_t)xfer | 0x3; 3346 status = XHCI_TRB_2_IRQ_SET(0); 3347 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3348 XHCI_TRB_3_IOC_BIT; 3349 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3350 } 3351 3352 parameter = 0; 3353 status = XHCI_TRB_2_IRQ_SET(0); 3354 /* the status stage has inverted direction */ 3355 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3356 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3357 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3358 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3359 3360 parameter = (uintptr_t)xfer | 0x0; 3361 status = XHCI_TRB_2_IRQ_SET(0); 3362 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3363 XHCI_TRB_3_IOC_BIT; 3364 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3365 3366 mutex_enter(&tr->xr_lock); 3367 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3368 mutex_exit(&tr->xr_lock); 3369 3370 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3371 3372 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3373 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3374 xhci_timeout, xfer); 3375 } 3376 3377 return USBD_IN_PROGRESS; 3378 } 3379 3380 static void 3381 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3382 { 3383 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3384 usb_device_request_t *req = &xfer->ux_request; 3385 int len = UGETW(req->wLength); 3386 int rd = req->bmRequestType & UT_READ; 3387 3388 if (len) 3389 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3390 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3391 } 3392 3393 static void 3394 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3395 { 3396 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3397 3398 xhci_abort_xfer(xfer, USBD_CANCELLED); 3399 } 3400 3401 static void 3402 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3403 { 3404 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3405 3406 xhci_close_pipe(pipe); 3407 } 3408 3409 /* ------------------ */ 3410 /* device isochronous */ 3411 3412 /* ----------- */ 3413 /* device bulk */ 3414 3415 static usbd_status 3416 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3417 { 3418 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3419 usbd_status err; 3420 3421 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3422 3423 /* Insert last in queue. */ 3424 mutex_enter(&sc->sc_lock); 3425 err = usb_insert_transfer(xfer); 3426 mutex_exit(&sc->sc_lock); 3427 if (err) 3428 return err; 3429 3430 /* 3431 * Pipe isn't running (otherwise err would be USBD_INPROG), 3432 * so start it first. 3433 */ 3434 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3435 } 3436 3437 static usbd_status 3438 xhci_device_bulk_start(struct usbd_xfer *xfer) 3439 { 3440 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3441 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3442 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3443 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3444 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3445 const uint32_t len = xfer->ux_length; 3446 usb_dma_t * const dma = &xfer->ux_dmabuf; 3447 uint64_t parameter; 3448 uint32_t status; 3449 uint32_t control; 3450 u_int i = 0; 3451 3452 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3453 3454 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3455 3456 if (sc->sc_dying) 3457 return USBD_IOERROR; 3458 3459 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3460 3461 parameter = DMAADDR(dma, 0); 3462 /* 3463 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3464 * If the user supplied buffer crosses such a boundary then 2 3465 * (or more) TRB should be used. 3466 * If multiple TRB are used the td_size field must be set correctly. 3467 * For v1.0 devices (like ivy bridge) this is the number of usb data 3468 * blocks needed to complete the transfer. 3469 * Setting it to 1 in the last TRB causes an extra zero-length 3470 * data block be sent. 3471 * The earlier documentation differs, I don't know how it behaves. 3472 */ 3473 KASSERT(len <= 0x10000); 3474 status = XHCI_TRB_2_IRQ_SET(0) | 3475 XHCI_TRB_2_TDSZ_SET(1) | 3476 XHCI_TRB_2_BYTES_SET(len); 3477 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3478 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3479 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3480 3481 mutex_enter(&tr->xr_lock); 3482 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3483 mutex_exit(&tr->xr_lock); 3484 3485 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3486 3487 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3488 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3489 xhci_timeout, xfer); 3490 } 3491 3492 return USBD_IN_PROGRESS; 3493 } 3494 3495 static void 3496 xhci_device_bulk_done(struct usbd_xfer *xfer) 3497 { 3498 #ifdef USB_DEBUG 3499 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3500 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3501 #endif 3502 const int isread = usbd_xfer_isread(xfer); 3503 3504 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3505 3506 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3507 3508 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3509 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3510 } 3511 3512 static void 3513 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3514 { 3515 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3516 3517 xhci_abort_xfer(xfer, USBD_CANCELLED); 3518 } 3519 3520 static void 3521 xhci_device_bulk_close(struct usbd_pipe *pipe) 3522 { 3523 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3524 3525 xhci_close_pipe(pipe); 3526 } 3527 3528 /* ---------------- */ 3529 /* device interrupt */ 3530 3531 static usbd_status 3532 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3533 { 3534 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3535 usbd_status err; 3536 3537 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3538 3539 /* Insert last in queue. */ 3540 mutex_enter(&sc->sc_lock); 3541 err = usb_insert_transfer(xfer); 3542 mutex_exit(&sc->sc_lock); 3543 if (err) 3544 return err; 3545 3546 /* 3547 * Pipe isn't running (otherwise err would be USBD_INPROG), 3548 * so start it first. 3549 */ 3550 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3551 } 3552 3553 static usbd_status 3554 xhci_device_intr_start(struct usbd_xfer *xfer) 3555 { 3556 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3557 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3558 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3559 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3560 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3561 const uint32_t len = xfer->ux_length; 3562 usb_dma_t * const dma = &xfer->ux_dmabuf; 3563 uint64_t parameter; 3564 uint32_t status; 3565 uint32_t control; 3566 u_int i = 0; 3567 3568 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3569 3570 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3571 3572 if (sc->sc_dying) 3573 return USBD_IOERROR; 3574 3575 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3576 3577 parameter = DMAADDR(dma, 0); 3578 KASSERT(len <= 0x10000); 3579 status = XHCI_TRB_2_IRQ_SET(0) | 3580 XHCI_TRB_2_TDSZ_SET(1) | 3581 XHCI_TRB_2_BYTES_SET(len); 3582 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3583 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3584 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3585 3586 mutex_enter(&tr->xr_lock); 3587 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3588 mutex_exit(&tr->xr_lock); 3589 3590 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3591 3592 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3593 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3594 xhci_timeout, xfer); 3595 } 3596 3597 return USBD_IN_PROGRESS; 3598 } 3599 3600 static void 3601 xhci_device_intr_done(struct usbd_xfer *xfer) 3602 { 3603 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3604 #ifdef USB_DEBUG 3605 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3606 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3607 #endif 3608 const int isread = usbd_xfer_isread(xfer); 3609 3610 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3611 3612 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3613 3614 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3615 3616 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3617 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3618 } 3619 3620 static void 3621 xhci_device_intr_abort(struct usbd_xfer *xfer) 3622 { 3623 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3624 3625 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3626 3627 KASSERT(mutex_owned(&sc->sc_lock)); 3628 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3629 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3630 xhci_abort_xfer(xfer, USBD_CANCELLED); 3631 } 3632 3633 static void 3634 xhci_device_intr_close(struct usbd_pipe *pipe) 3635 { 3636 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3637 3638 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3639 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3640 3641 xhci_close_pipe(pipe); 3642 } 3643 3644 /* ------------ */ 3645 3646 static void 3647 xhci_timeout(void *addr) 3648 { 3649 struct xhci_xfer * const xx = addr; 3650 struct usbd_xfer * const xfer = &xx->xx_xfer; 3651 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3652 3653 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3654 3655 if (sc->sc_dying) { 3656 return; 3657 } 3658 3659 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 3660 USB_TASKQ_MPSAFE); 3661 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 3662 USB_TASKQ_HC); 3663 } 3664 3665 static void 3666 xhci_timeout_task(void *addr) 3667 { 3668 struct usbd_xfer * const xfer = addr; 3669 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3670 3671 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3672 3673 mutex_enter(&sc->sc_lock); 3674 #if 0 3675 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3676 #else 3677 xfer->ux_status = USBD_TIMEOUT; 3678 usb_transfer_complete(xfer); 3679 #endif 3680 mutex_exit(&sc->sc_lock); 3681 } 3682
Indexes created Wed Sep 24 22:09:59 GMT 2025