xhci.c revision 1.52
1 /* $NetBSD: xhci.c,v 1.52 2016/06/05 08:10:59 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.52 2016/06/05 08:10:59 skrll Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 146 147 static usbd_status xhci_do_command(struct xhci_softc * const, 148 struct xhci_trb * const, int); 149 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 150 struct xhci_trb * const, int); 151 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 152 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 153 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 154 static usbd_status xhci_enable_slot(struct xhci_softc * const, 155 uint8_t * const); 156 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 157 static usbd_status xhci_address_device(struct xhci_softc * const, 158 uint64_t, uint8_t, bool); 159 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 160 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 161 struct xhci_slot * const, u_int); 162 static usbd_status xhci_ring_init(struct xhci_softc * const, 163 struct xhci_ring * const, size_t, size_t); 164 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 165 166 static void xhci_setup_ctx(struct usbd_pipe *); 167 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 168 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 169 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 170 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 171 172 static void xhci_noop(struct usbd_pipe *); 173 174 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 175 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 176 static void xhci_root_intr_abort(struct usbd_xfer *); 177 static void xhci_root_intr_close(struct usbd_pipe *); 178 static void xhci_root_intr_done(struct usbd_xfer *); 179 180 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 181 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 182 static void xhci_device_ctrl_abort(struct usbd_xfer *); 183 static void xhci_device_ctrl_close(struct usbd_pipe *); 184 static void xhci_device_ctrl_done(struct usbd_xfer *); 185 186 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 187 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 188 static void xhci_device_intr_abort(struct usbd_xfer *); 189 static void xhci_device_intr_close(struct usbd_pipe *); 190 static void xhci_device_intr_done(struct usbd_xfer *); 191 192 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 193 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 194 static void xhci_device_bulk_abort(struct usbd_xfer *); 195 static void xhci_device_bulk_close(struct usbd_pipe *); 196 static void xhci_device_bulk_done(struct usbd_xfer *); 197 198 static void xhci_timeout(void *); 199 static void xhci_timeout_task(void *); 200 201 static const struct usbd_bus_methods xhci_bus_methods = { 202 .ubm_open = xhci_open, 203 .ubm_softint = xhci_softintr, 204 .ubm_dopoll = xhci_poll, 205 .ubm_allocx = xhci_allocx, 206 .ubm_freex = xhci_freex, 207 .ubm_getlock = xhci_get_lock, 208 .ubm_newdev = xhci_new_device, 209 .ubm_rhctrl = xhci_roothub_ctrl, 210 }; 211 212 static const struct usbd_pipe_methods xhci_root_intr_methods = { 213 .upm_transfer = xhci_root_intr_transfer, 214 .upm_start = xhci_root_intr_start, 215 .upm_abort = xhci_root_intr_abort, 216 .upm_close = xhci_root_intr_close, 217 .upm_cleartoggle = xhci_noop, 218 .upm_done = xhci_root_intr_done, 219 }; 220 221 222 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 223 .upm_transfer = xhci_device_ctrl_transfer, 224 .upm_start = xhci_device_ctrl_start, 225 .upm_abort = xhci_device_ctrl_abort, 226 .upm_close = xhci_device_ctrl_close, 227 .upm_cleartoggle = xhci_noop, 228 .upm_done = xhci_device_ctrl_done, 229 }; 230 231 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 232 .upm_cleartoggle = xhci_noop, 233 }; 234 235 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 236 .upm_transfer = xhci_device_bulk_transfer, 237 .upm_start = xhci_device_bulk_start, 238 .upm_abort = xhci_device_bulk_abort, 239 .upm_close = xhci_device_bulk_close, 240 .upm_cleartoggle = xhci_noop, 241 .upm_done = xhci_device_bulk_done, 242 }; 243 244 static const struct usbd_pipe_methods xhci_device_intr_methods = { 245 .upm_transfer = xhci_device_intr_transfer, 246 .upm_start = xhci_device_intr_start, 247 .upm_abort = xhci_device_intr_abort, 248 .upm_close = xhci_device_intr_close, 249 .upm_cleartoggle = xhci_noop, 250 .upm_done = xhci_device_intr_done, 251 }; 252 253 static inline uint32_t 254 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 255 { 256 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 257 } 258 259 static inline uint32_t 260 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 261 { 262 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 263 } 264 265 static inline void 266 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 267 uint32_t value) 268 { 269 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 270 } 271 272 #if 0 /* unused */ 273 static inline void 274 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 275 uint32_t value) 276 { 277 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 278 } 279 #endif /* unused */ 280 281 static inline uint32_t 282 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 283 { 284 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 285 } 286 287 static inline uint32_t 288 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 289 { 290 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 291 } 292 293 static inline void 294 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 295 uint32_t value) 296 { 297 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 298 } 299 300 static inline uint64_t 301 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 302 { 303 uint64_t value; 304 305 if (sc->sc_ac64) { 306 #ifdef XHCI_USE_BUS_SPACE_8 307 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 308 #else 309 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 310 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 311 offset + 4) << 32; 312 #endif 313 } else { 314 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 315 } 316 317 return value; 318 } 319 320 static inline void 321 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 322 uint64_t value) 323 { 324 if (sc->sc_ac64) { 325 #ifdef XHCI_USE_BUS_SPACE_8 326 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 327 #else 328 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 329 (value >> 0) & 0xffffffff); 330 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 331 (value >> 32) & 0xffffffff); 332 #endif 333 } else { 334 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 335 } 336 } 337 338 static inline uint32_t 339 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 340 { 341 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 342 } 343 344 static inline void 345 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 346 uint32_t value) 347 { 348 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 349 } 350 351 #if 0 /* unused */ 352 static inline uint64_t 353 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 354 { 355 uint64_t value; 356 357 if (sc->sc_ac64) { 358 #ifdef XHCI_USE_BUS_SPACE_8 359 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 360 #else 361 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 362 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 363 offset + 4) << 32; 364 #endif 365 } else { 366 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 367 } 368 369 return value; 370 } 371 #endif /* unused */ 372 373 static inline void 374 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 375 uint64_t value) 376 { 377 if (sc->sc_ac64) { 378 #ifdef XHCI_USE_BUS_SPACE_8 379 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 380 #else 381 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 382 (value >> 0) & 0xffffffff); 383 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 384 (value >> 32) & 0xffffffff); 385 #endif 386 } else { 387 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 388 } 389 } 390 391 #if 0 /* unused */ 392 static inline uint32_t 393 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 394 { 395 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 396 } 397 #endif /* unused */ 398 399 static inline void 400 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 401 uint32_t value) 402 { 403 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 404 } 405 406 /* --- */ 407 408 static inline uint8_t 409 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 410 { 411 u_int eptype = 0; 412 413 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 414 case UE_CONTROL: 415 eptype = 0x0; 416 break; 417 case UE_ISOCHRONOUS: 418 eptype = 0x1; 419 break; 420 case UE_BULK: 421 eptype = 0x2; 422 break; 423 case UE_INTERRUPT: 424 eptype = 0x3; 425 break; 426 } 427 428 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 429 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 430 return eptype | 0x4; 431 else 432 return eptype; 433 } 434 435 static u_int 436 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 437 { 438 /* xHCI 1.0 section 4.5.1 */ 439 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 440 u_int in = 0; 441 442 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 443 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 444 in = 1; 445 446 return epaddr * 2 + in; 447 } 448 449 static inline u_int 450 xhci_dci_to_ici(const u_int i) 451 { 452 return i + 1; 453 } 454 455 static inline void * 456 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 457 const u_int dci) 458 { 459 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 460 } 461 462 #if 0 /* unused */ 463 static inline bus_addr_t 464 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 465 const u_int dci) 466 { 467 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 468 } 469 #endif /* unused */ 470 471 static inline void * 472 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 473 const u_int ici) 474 { 475 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 476 } 477 478 static inline bus_addr_t 479 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 480 const u_int ici) 481 { 482 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 483 } 484 485 static inline struct xhci_trb * 486 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 487 { 488 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 489 } 490 491 static inline bus_addr_t 492 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 493 { 494 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 495 } 496 497 static inline void 498 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 499 uint32_t control) 500 { 501 trb->trb_0 = htole64(parameter); 502 trb->trb_2 = htole32(status); 503 trb->trb_3 = htole32(control); 504 } 505 506 static int 507 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 508 { 509 /* base address of TRBs */ 510 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 511 512 /* trb_0 range sanity check */ 513 if (trb_0 == 0 || trb_0 < trbp || 514 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 515 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 516 return 1; 517 } 518 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 519 return 0; 520 } 521 522 /* --- */ 523 524 void 525 xhci_childdet(device_t self, device_t child) 526 { 527 struct xhci_softc * const sc = device_private(self); 528 529 KASSERT(sc->sc_child == child); 530 if (child == sc->sc_child) 531 sc->sc_child = NULL; 532 } 533 534 int 535 xhci_detach(struct xhci_softc *sc, int flags) 536 { 537 int rv = 0; 538 539 if (sc->sc_child != NULL) 540 rv = config_detach(sc->sc_child, flags); 541 542 if (rv != 0) 543 return rv; 544 545 /* XXX unconfigure/free slots */ 546 547 /* verify: */ 548 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 549 xhci_op_write_4(sc, XHCI_USBCMD, 0); 550 /* do we need to wait for stop? */ 551 552 xhci_op_write_8(sc, XHCI_CRCR, 0); 553 xhci_ring_free(sc, &sc->sc_cr); 554 cv_destroy(&sc->sc_command_cv); 555 556 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 557 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 558 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 559 xhci_ring_free(sc, &sc->sc_er); 560 561 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 562 563 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 564 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 565 566 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 567 568 mutex_destroy(&sc->sc_lock); 569 mutex_destroy(&sc->sc_intr_lock); 570 571 pool_cache_destroy(sc->sc_xferpool); 572 573 return rv; 574 } 575 576 int 577 xhci_activate(device_t self, enum devact act) 578 { 579 struct xhci_softc * const sc = device_private(self); 580 581 switch (act) { 582 case DVACT_DEACTIVATE: 583 sc->sc_dying = true; 584 return 0; 585 default: 586 return EOPNOTSUPP; 587 } 588 } 589 590 bool 591 xhci_suspend(device_t dv, const pmf_qual_t *qual) 592 { 593 return false; 594 } 595 596 bool 597 xhci_resume(device_t dv, const pmf_qual_t *qual) 598 { 599 return false; 600 } 601 602 bool 603 xhci_shutdown(device_t self, int flags) 604 { 605 return false; 606 } 607 608 static int 609 xhci_hc_reset(struct xhci_softc * const sc) 610 { 611 uint32_t usbcmd, usbsts; 612 int i; 613 614 /* Check controller not ready */ 615 for (i = 0; i < XHCI_WAIT_CNR; i++) { 616 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 617 if ((usbsts & XHCI_STS_CNR) == 0) 618 break; 619 usb_delay_ms(&sc->sc_bus, 1); 620 } 621 if (i >= XHCI_WAIT_CNR) { 622 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 623 return EIO; 624 } 625 626 /* Halt controller */ 627 usbcmd = 0; 628 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 629 usb_delay_ms(&sc->sc_bus, 1); 630 631 /* Reset controller */ 632 usbcmd = XHCI_CMD_HCRST; 633 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 634 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 635 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 636 if ((usbcmd & XHCI_CMD_HCRST) == 0) 637 break; 638 usb_delay_ms(&sc->sc_bus, 1); 639 } 640 if (i >= XHCI_WAIT_HCRST) { 641 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 642 return EIO; 643 } 644 645 /* Check controller not ready */ 646 for (i = 0; i < XHCI_WAIT_CNR; i++) { 647 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 648 if ((usbsts & XHCI_STS_CNR) == 0) 649 break; 650 usb_delay_ms(&sc->sc_bus, 1); 651 } 652 if (i >= XHCI_WAIT_CNR) { 653 aprint_error_dev(sc->sc_dev, 654 "controller not ready timeout after reset\n"); 655 return EIO; 656 } 657 658 return 0; 659 } 660 661 662 static void 663 hexdump(const char *msg, const void *base, size_t len) 664 { 665 #if 0 666 size_t cnt; 667 const uint32_t *p; 668 extern paddr_t vtophys(vaddr_t); 669 670 p = base; 671 cnt = 0; 672 673 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 674 (void *)vtophys((vaddr_t)base)); 675 676 while (cnt < len) { 677 if (cnt % 16 == 0) 678 printf("%p: ", p); 679 else if (cnt % 8 == 0) 680 printf(" |"); 681 printf(" %08x", *p++); 682 cnt += 4; 683 if (cnt % 16 == 0) 684 printf("\n"); 685 } 686 if (cnt % 16 != 0) 687 printf("\n"); 688 #endif 689 } 690 691 /* Process extended capabilities */ 692 static void 693 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 694 { 695 uint32_t ecp, ecr; 696 697 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 698 699 ecp = XHCI_HCC_XECP(hcc) * 4; 700 while (ecp != 0) { 701 ecr = xhci_read_4(sc, ecp); 702 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 703 switch (XHCI_XECP_ID(ecr)) { 704 case XHCI_ID_PROTOCOLS: { 705 uint32_t w4, w8, wc; 706 uint16_t w2; 707 w2 = (ecr >> 16) & 0xffff; 708 w4 = xhci_read_4(sc, ecp + 4); 709 w8 = xhci_read_4(sc, ecp + 8); 710 wc = xhci_read_4(sc, ecp + 0xc); 711 aprint_debug_dev(sc->sc_dev, 712 " SP: %08x %08x %08x %08x\n", ecr, w4, w8, wc); 713 /* unused */ 714 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0300) { 715 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 716 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 717 } 718 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0200) { 719 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 720 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 721 } 722 break; 723 } 724 case XHCI_ID_USB_LEGACY: { 725 uint8_t bios_sem; 726 727 /* Take host controller ownership from BIOS */ 728 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 729 if (bios_sem) { 730 /* sets xHCI to be owned by OS */ 731 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 732 aprint_debug_dev(sc->sc_dev, 733 "waiting for BIOS to give up control\n"); 734 for (int i = 0; i < 5000; i++) { 735 bios_sem = xhci_read_1(sc, ecp + 736 XHCI_XECP_BIOS_SEM); 737 if (bios_sem == 0) 738 break; 739 DELAY(1000); 740 } 741 if (bios_sem) { 742 aprint_error_dev(sc->sc_dev, 743 "timed out waiting for BIOS\n"); 744 } 745 } 746 break; 747 } 748 default: 749 break; 750 } 751 ecr = xhci_read_4(sc, ecp); 752 if (XHCI_XECP_NEXT(ecr) == 0) { 753 ecp = 0; 754 } else { 755 ecp += XHCI_XECP_NEXT(ecr) * 4; 756 } 757 } 758 } 759 760 #define XHCI_HCCPREV1_BITS \ 761 "\177\020" /* New bitmask */ \ 762 "f\020\020XECP\0" \ 763 "f\014\4MAXPSA\0" \ 764 "b\013CFC\0" \ 765 "b\012SEC\0" \ 766 "b\011SBD\0" \ 767 "b\010FSE\0" \ 768 "b\7NSS\0" \ 769 "b\6LTC\0" \ 770 "b\5LHRC\0" \ 771 "b\4PIND\0" \ 772 "b\3PPC\0" \ 773 "b\2CZC\0" \ 774 "b\1BNC\0" \ 775 "b\0AC64\0" \ 776 "\0" 777 #define XHCI_HCCV1_x_BITS \ 778 "\177\020" /* New bitmask */ \ 779 "f\020\020XECP\0" \ 780 "f\014\4MAXPSA\0" \ 781 "b\013CFC\0" \ 782 "b\012SEC\0" \ 783 "b\011SPC\0" \ 784 "b\010PAE\0" \ 785 "b\7NSS\0" \ 786 "b\6LTC\0" \ 787 "b\5LHRC\0" \ 788 "b\4PIND\0" \ 789 "b\3PPC\0" \ 790 "b\2CSZ\0" \ 791 "b\1BNC\0" \ 792 "b\0AC64\0" \ 793 "\0" 794 795 int 796 xhci_init(struct xhci_softc *sc) 797 { 798 bus_size_t bsz; 799 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 800 uint32_t pagesize, config; 801 int i = 0; 802 uint16_t hciversion; 803 uint8_t caplength; 804 805 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 806 807 sc->sc_bus.ub_revision = USBREV_3_0; 808 sc->sc_bus.ub_usedma = true; 809 810 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 811 caplength = XHCI_CAP_CAPLENGTH(cap); 812 hciversion = XHCI_CAP_HCIVERSION(cap); 813 814 if (hciversion < XHCI_HCIVERSION_0_96 || 815 hciversion > XHCI_HCIVERSION_1_0) { 816 aprint_normal_dev(sc->sc_dev, 817 "xHCI version %x.%x not known to be supported\n", 818 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 819 } else { 820 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 821 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 822 } 823 824 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 825 &sc->sc_cbh) != 0) { 826 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 827 return ENOMEM; 828 } 829 830 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 831 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 832 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 833 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 834 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 835 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 836 aprint_debug_dev(sc->sc_dev, 837 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 838 839 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 840 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 841 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 842 843 char sbuf[128]; 844 if (hciversion < XHCI_HCIVERSION_1_0) 845 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 846 else 847 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 848 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 849 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 850 851 /* print PSI and take ownership from BIOS */ 852 xhci_ecp(sc, hcc); 853 854 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 855 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 856 &sc->sc_obh) != 0) { 857 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 858 return ENOMEM; 859 } 860 861 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 862 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 863 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 864 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 865 return ENOMEM; 866 } 867 868 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 869 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 870 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 871 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 872 return ENOMEM; 873 } 874 875 int rv; 876 rv = xhci_hc_reset(sc); 877 if (rv != 0) { 878 return rv; 879 } 880 881 if (sc->sc_vendor_init) 882 sc->sc_vendor_init(sc); 883 884 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 885 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 886 pagesize = ffs(pagesize); 887 if (pagesize == 0) { 888 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 889 return EIO; 890 } 891 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 892 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 893 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 894 (uint32_t)sc->sc_maxslots); 895 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 896 897 usbd_status err; 898 899 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 900 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 901 if (sc->sc_maxspbuf != 0) { 902 err = usb_allocmem(&sc->sc_bus, 903 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 904 &sc->sc_spbufarray_dma); 905 if (err) { 906 aprint_error_dev(sc->sc_dev, 907 "spbufarray init fail, err %d\n", err); 908 return ENOMEM; 909 } 910 911 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 912 sc->sc_maxspbuf, KM_SLEEP); 913 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 914 for (i = 0; i < sc->sc_maxspbuf; i++) { 915 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 916 /* allocate contexts */ 917 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 918 sc->sc_pgsz, dma); 919 if (err) { 920 aprint_error_dev(sc->sc_dev, 921 "spbufarray_dma init fail, err %d\n", err); 922 rv = ENOMEM; 923 goto bad1; 924 } 925 spbufarray[i] = htole64(DMAADDR(dma, 0)); 926 usb_syncmem(dma, 0, sc->sc_pgsz, 927 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 928 } 929 930 usb_syncmem(&sc->sc_spbufarray_dma, 0, 931 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 932 } 933 934 config = xhci_op_read_4(sc, XHCI_CONFIG); 935 config &= ~0xFF; 936 config |= sc->sc_maxslots & 0xFF; 937 xhci_op_write_4(sc, XHCI_CONFIG, config); 938 939 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 940 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 941 if (err) { 942 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 943 err); 944 rv = ENOMEM; 945 goto bad1; 946 } 947 948 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 949 XHCI_EVENT_RING_SEGMENTS_ALIGN); 950 if (err) { 951 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 952 err); 953 rv = ENOMEM; 954 goto bad2; 955 } 956 957 usb_dma_t *dma; 958 size_t size; 959 size_t align; 960 961 dma = &sc->sc_eventst_dma; 962 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 963 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 964 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 965 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 966 err = usb_allocmem(&sc->sc_bus, size, align, dma); 967 if (err) { 968 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 969 err); 970 rv = ENOMEM; 971 goto bad3; 972 } 973 974 memset(KERNADDR(dma, 0), 0, size); 975 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 976 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 977 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 978 KERNADDR(&sc->sc_eventst_dma, 0), 979 sc->sc_eventst_dma.udma_block->size); 980 981 dma = &sc->sc_dcbaa_dma; 982 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 983 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 984 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 985 err = usb_allocmem(&sc->sc_bus, size, align, dma); 986 if (err) { 987 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 988 rv = ENOMEM; 989 goto bad4; 990 } 991 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 992 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 993 KERNADDR(&sc->sc_dcbaa_dma, 0), 994 sc->sc_dcbaa_dma.udma_block->size); 995 996 memset(KERNADDR(dma, 0), 0, size); 997 if (sc->sc_maxspbuf != 0) { 998 /* 999 * DCBA entry 0 hold the scratchbuf array pointer. 1000 */ 1001 *(uint64_t *)KERNADDR(dma, 0) = 1002 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1003 } 1004 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1005 1006 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1007 KM_SLEEP); 1008 if (sc->sc_slots == NULL) { 1009 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1010 rv = ENOMEM; 1011 goto bad; 1012 } 1013 1014 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1015 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1016 if (sc->sc_xferpool == NULL) { 1017 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1018 err); 1019 rv = ENOMEM; 1020 goto bad; 1021 } 1022 1023 cv_init(&sc->sc_command_cv, "xhcicmd"); 1024 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1025 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1026 1027 /* Set up the bus struct. */ 1028 sc->sc_bus.ub_methods = &xhci_bus_methods; 1029 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 1030 1031 struct xhci_erste *erst; 1032 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1033 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1034 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1035 erst[0].erste_3 = htole32(0); 1036 usb_syncmem(&sc->sc_eventst_dma, 0, 1037 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1038 1039 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1040 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1041 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1042 XHCI_ERDP_LO_BUSY); 1043 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1044 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1045 sc->sc_cr.xr_cs); 1046 1047 #if 0 1048 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1049 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1050 #endif 1051 1052 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1053 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1054 /* Intel xhci needs interrupt rate moderated. */ 1055 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1056 else 1057 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1058 aprint_debug_dev(sc->sc_dev, "setting IMOD %u\n", 1059 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1060 1061 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 1062 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1063 xhci_op_read_4(sc, XHCI_USBCMD)); 1064 1065 return 0; 1066 1067 bad: 1068 if (sc->sc_xferpool) { 1069 pool_cache_destroy(sc->sc_xferpool); 1070 sc->sc_xferpool = NULL; 1071 } 1072 1073 if (sc->sc_slots) { 1074 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1075 sc->sc_maxslots); 1076 sc->sc_slots = NULL; 1077 } 1078 1079 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1080 bad4: 1081 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1082 bad3: 1083 xhci_ring_free(sc, &sc->sc_er); 1084 bad2: 1085 xhci_ring_free(sc, &sc->sc_cr); 1086 i = sc->sc_maxspbuf; 1087 bad1: 1088 for (int j = 0; j < i; j++) 1089 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1090 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1091 1092 return rv; 1093 } 1094 1095 int 1096 xhci_intr(void *v) 1097 { 1098 struct xhci_softc * const sc = v; 1099 int ret = 0; 1100 1101 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1102 1103 if (sc == NULL) 1104 return 0; 1105 1106 mutex_spin_enter(&sc->sc_intr_lock); 1107 1108 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1109 goto done; 1110 1111 /* If we get an interrupt while polling, then just ignore it. */ 1112 if (sc->sc_bus.ub_usepolling) { 1113 #ifdef DIAGNOSTIC 1114 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1115 #endif 1116 goto done; 1117 } 1118 1119 ret = xhci_intr1(sc); 1120 done: 1121 mutex_spin_exit(&sc->sc_intr_lock); 1122 return ret; 1123 } 1124 1125 int 1126 xhci_intr1(struct xhci_softc * const sc) 1127 { 1128 uint32_t usbsts; 1129 uint32_t iman; 1130 1131 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1132 1133 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1134 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1135 #if 0 1136 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1137 return 0; 1138 } 1139 #endif 1140 xhci_op_write_4(sc, XHCI_USBSTS, 1141 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1142 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1143 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1144 1145 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1146 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1147 iman |= XHCI_IMAN_INTR_PEND; 1148 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1149 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1150 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1151 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1152 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1153 1154 usb_schedsoftintr(&sc->sc_bus); 1155 1156 return 1; 1157 } 1158 1159 /* 1160 * 3 port speed types used in USB stack 1161 * 1162 * usbdi speed 1163 * definition: USB_SPEED_* in usb.h 1164 * They are used in struct usbd_device in USB stack. 1165 * ioctl interface uses these values too. 1166 * port_status speed 1167 * definition: UPS_*_SPEED in usb.h 1168 * They are used in usb_port_status_t and valid only for USB 2.0. 1169 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1170 * of usb_port_status_ext_t indicates port speed. 1171 * Note that some 3.0 values overlap with 2.0 values. 1172 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1173 * means UPS_LOW_SPEED in HS.) 1174 * port status returned from hub also uses these values. 1175 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1176 * or more. 1177 * xspeed: 1178 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1179 * They are used in only slot context and PORTSC reg of xhci. 1180 * The difference between usbdi speed and xspeed is 1181 * that FS and LS values are swapped. 1182 */ 1183 1184 /* convert usbdi speed to xspeed */ 1185 static int 1186 xhci_speed2xspeed(int speed) 1187 { 1188 switch (speed) { 1189 case USB_SPEED_LOW: return 2; 1190 case USB_SPEED_FULL: return 1; 1191 default: return speed; 1192 } 1193 } 1194 1195 #if 0 1196 /* convert xspeed to usbdi speed */ 1197 static int 1198 xhci_xspeed2speed(int xspeed) 1199 { 1200 switch (xspeed) { 1201 case 1: return USB_SPEED_FULL; 1202 case 2: return USB_SPEED_LOW; 1203 default: return xspeed; 1204 } 1205 } 1206 #endif 1207 1208 /* convert xspeed to port status speed */ 1209 static int 1210 xhci_xspeed2psspeed(int xspeed) 1211 { 1212 switch (xspeed) { 1213 case 0: return 0; 1214 case 1: return UPS_FULL_SPEED; 1215 case 2: return UPS_LOW_SPEED; 1216 case 3: return UPS_HIGH_SPEED; 1217 default: return UPS_OTHER_SPEED; 1218 } 1219 } 1220 1221 /* 1222 * Construct input contexts and issue TRB 1223 */ 1224 static usbd_status 1225 xhci_configure_endpoint(struct usbd_pipe *pipe) 1226 { 1227 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1228 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1229 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1230 struct xhci_trb trb; 1231 usbd_status err; 1232 1233 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1234 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1235 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1236 pipe->up_endpoint->ue_edesc->bmAttributes); 1237 1238 KASSERT(!mutex_owned(&sc->sc_lock)); 1239 1240 /* XXX ensure input context is available? */ 1241 1242 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1243 1244 /* set up context */ 1245 xhci_setup_ctx(pipe); 1246 1247 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1248 sc->sc_ctxsz * 1); 1249 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1250 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1251 1252 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1253 trb.trb_2 = 0; 1254 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1255 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1256 1257 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1258 1259 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1260 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1261 sc->sc_ctxsz * 1); 1262 1263 return err; 1264 } 1265 1266 #if 0 1267 static usbd_status 1268 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1269 { 1270 #ifdef USB_DEBUG 1271 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1272 #endif 1273 1274 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1275 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1276 1277 return USBD_NORMAL_COMPLETION; 1278 } 1279 #endif 1280 1281 /* 4.6.8, 6.4.3.7 */ 1282 static usbd_status 1283 xhci_reset_endpoint(struct usbd_pipe *pipe) 1284 { 1285 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1286 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1287 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1288 struct xhci_trb trb; 1289 usbd_status err; 1290 1291 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1292 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1293 1294 KASSERT(!mutex_owned(&sc->sc_lock)); 1295 1296 trb.trb_0 = 0; 1297 trb.trb_2 = 0; 1298 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1299 XHCI_TRB_3_EP_SET(dci) | 1300 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1301 1302 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1303 1304 return err; 1305 } 1306 1307 /* 1308 * 4.6.9, 6.4.3.8 1309 * Stop execution of TDs on xfer ring. 1310 * Should be called with sc_lock held. 1311 */ 1312 static usbd_status 1313 xhci_stop_endpoint(struct usbd_pipe *pipe) 1314 { 1315 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1316 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1317 struct xhci_trb trb; 1318 usbd_status err; 1319 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1320 1321 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1322 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1323 1324 KASSERT(mutex_owned(&sc->sc_lock)); 1325 1326 trb.trb_0 = 0; 1327 trb.trb_2 = 0; 1328 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1329 XHCI_TRB_3_EP_SET(dci) | 1330 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1331 1332 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1333 1334 return err; 1335 } 1336 1337 /* 1338 * Set TR Dequeue Pointer. 1339 * xCHI 1.1 4.6.10 6.4.3.9 1340 * Purge all of the transfer requests on ring. 1341 * EPSTATE of endpoint must be ERROR or STOPPED, or CONTEXT_STATE error. 1342 */ 1343 static usbd_status 1344 xhci_set_dequeue(struct usbd_pipe *pipe) 1345 { 1346 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1347 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1348 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1349 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1350 struct xhci_trb trb; 1351 usbd_status err; 1352 1353 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1354 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1355 1356 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1357 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1358 BUS_DMASYNC_PREWRITE); 1359 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1360 1361 xr->xr_ep = 0; 1362 xr->xr_cs = 1; 1363 1364 /* set DCS */ 1365 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1366 trb.trb_2 = 0; 1367 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1368 XHCI_TRB_3_EP_SET(dci) | 1369 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1370 1371 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1372 1373 return err; 1374 } 1375 1376 /* 1377 * Open new pipe: called from usbd_setup_pipe_flags. 1378 * Fills methods of pipe. 1379 * If pipe is not for ep0, calls configure_endpoint. 1380 */ 1381 static usbd_status 1382 xhci_open(struct usbd_pipe *pipe) 1383 { 1384 struct usbd_device * const dev = pipe->up_dev; 1385 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1386 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1387 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1388 1389 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1390 DPRINTFN(1, "addr %d depth %d port %d speed %d", 1391 dev->ud_addr, dev->ud_depth, dev->ud_powersrc->up_portno, 1392 dev->ud_speed); 1393 1394 if (sc->sc_dying) 1395 return USBD_IOERROR; 1396 1397 /* Root Hub */ 1398 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1399 switch (ed->bEndpointAddress) { 1400 case USB_CONTROL_ENDPOINT: 1401 pipe->up_methods = &roothub_ctrl_methods; 1402 break; 1403 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1404 pipe->up_methods = &xhci_root_intr_methods; 1405 break; 1406 default: 1407 pipe->up_methods = NULL; 1408 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1409 ed->bEndpointAddress, 0, 0, 0); 1410 return USBD_INVAL; 1411 } 1412 return USBD_NORMAL_COMPLETION; 1413 } 1414 1415 switch (xfertype) { 1416 case UE_CONTROL: 1417 pipe->up_methods = &xhci_device_ctrl_methods; 1418 break; 1419 case UE_ISOCHRONOUS: 1420 pipe->up_methods = &xhci_device_isoc_methods; 1421 return USBD_INVAL; 1422 break; 1423 case UE_BULK: 1424 pipe->up_methods = &xhci_device_bulk_methods; 1425 break; 1426 case UE_INTERRUPT: 1427 pipe->up_methods = &xhci_device_intr_methods; 1428 break; 1429 default: 1430 return USBD_IOERROR; 1431 break; 1432 } 1433 1434 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1435 return xhci_configure_endpoint(pipe); 1436 1437 return USBD_NORMAL_COMPLETION; 1438 } 1439 1440 /* 1441 * Closes pipe, called from usbd_kill_pipe via close methods. 1442 * If the endpoint to be closed is ep0, disable_slot. 1443 * Should be called with sc_lock held. 1444 */ 1445 static void 1446 xhci_close_pipe(struct usbd_pipe *pipe) 1447 { 1448 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1449 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1450 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1451 const u_int dci = xhci_ep_get_dci(ed); 1452 struct xhci_trb trb; 1453 uint32_t *cp; 1454 1455 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1456 1457 if (sc->sc_dying) 1458 return; 1459 1460 /* xs is uninitialized before xhci_init_slot */ 1461 if (xs == NULL || xs->xs_idx == 0) 1462 return; 1463 1464 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1465 1466 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1467 KASSERT(mutex_owned(&sc->sc_lock)); 1468 1469 if (pipe->up_dev->ud_depth == 0) 1470 return; 1471 1472 if (dci == XHCI_DCI_EP_CONTROL) { 1473 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1474 xhci_disable_slot(sc, xs->xs_idx); 1475 return; 1476 } 1477 1478 /* 1479 * This may fail in the case that xhci_close_pipe is called after 1480 * xhci_abort_xfer e.g. usbd_kill_pipe. 1481 */ 1482 (void)xhci_stop_endpoint(pipe); 1483 1484 /* 1485 * set appropriate bit to be dropped. 1486 * don't set DC bit to 1, otherwise all endpoints 1487 * would be deconfigured. 1488 */ 1489 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1490 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1491 cp[1] = htole32(0); 1492 1493 /* XXX should be most significant one, not dci? */ 1494 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1495 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1496 1497 /* sync input contexts before they are read from memory */ 1498 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1499 1500 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1501 trb.trb_2 = 0; 1502 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1503 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1504 1505 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1506 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1507 } 1508 1509 /* 1510 * Abort transfer. 1511 * Called with sc_lock held. 1512 * May be called from softintr context. 1513 */ 1514 static void 1515 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1516 { 1517 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1518 1519 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1520 DPRINTFN(4, "xfer %p pipe %p status %d", 1521 xfer, xfer->ux_pipe, status, 0); 1522 1523 KASSERT(mutex_owned(&sc->sc_lock)); 1524 1525 if (sc->sc_dying) { 1526 /* If we're dying, just do the software part. */ 1527 DPRINTFN(4, "dying", 0, 0, 0, 0); 1528 xfer->ux_status = status; /* make software ignore it */ 1529 callout_stop(&xfer->ux_callout); 1530 usb_transfer_complete(xfer); 1531 return; 1532 } 1533 1534 /* XXX need more stuff */ 1535 xfer->ux_status = status; 1536 callout_stop(&xfer->ux_callout); 1537 usb_transfer_complete(xfer); 1538 DPRINTFN(14, "end", 0, 0, 0, 0); 1539 1540 KASSERT(mutex_owned(&sc->sc_lock)); 1541 } 1542 1543 /* 1544 * Recover STALLed endpoint. 1545 * xHCI 1.1 sect 4.10.2.1 1546 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1547 * all transfers on transfer ring. 1548 * These are done in thread context asynchronously. 1549 */ 1550 static void 1551 xhci_clear_endpoint_stall_async_task(void *cookie) 1552 { 1553 struct usbd_xfer * const xfer = cookie; 1554 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1555 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1556 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1557 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1558 1559 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1560 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1561 1562 xhci_reset_endpoint(xfer->ux_pipe); 1563 xhci_set_dequeue(xfer->ux_pipe); 1564 1565 mutex_enter(&sc->sc_lock); 1566 tr->is_halted = false; 1567 usb_transfer_complete(xfer); 1568 mutex_exit(&sc->sc_lock); 1569 DPRINTFN(4, "ends", 0, 0, 0, 0); 1570 } 1571 1572 static usbd_status 1573 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1574 { 1575 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1576 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1577 1578 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1579 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1580 1581 if (sc->sc_dying) { 1582 return USBD_IOERROR; 1583 } 1584 1585 usb_init_task(&xp->xp_async_task, 1586 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1587 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1588 DPRINTFN(4, "ends", 0, 0, 0, 0); 1589 1590 return USBD_NORMAL_COMPLETION; 1591 } 1592 1593 /* Process roothub port status/change events and notify to uhub_intr. */ 1594 static void 1595 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1596 { 1597 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1598 uint8_t *p; 1599 1600 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1601 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1602 port, 0, 0); 1603 1604 if (xfer == NULL) 1605 return; 1606 1607 if (port > sc->sc_maxports) 1608 return; 1609 1610 p = xfer->ux_buf; 1611 memset(p, 0, xfer->ux_length); 1612 p[port/NBBY] |= 1 << (port%NBBY); 1613 xfer->ux_actlen = xfer->ux_length; 1614 xfer->ux_status = USBD_NORMAL_COMPLETION; 1615 usb_transfer_complete(xfer); 1616 } 1617 1618 /* Process Transfer Events */ 1619 static void 1620 xhci_event_transfer(struct xhci_softc * const sc, 1621 const struct xhci_trb * const trb) 1622 { 1623 uint64_t trb_0; 1624 uint32_t trb_2, trb_3; 1625 uint8_t trbcode; 1626 u_int slot, dci; 1627 struct xhci_slot *xs; 1628 struct xhci_ring *xr; 1629 struct xhci_xfer *xx; 1630 struct usbd_xfer *xfer; 1631 usbd_status err; 1632 1633 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1634 1635 trb_0 = le64toh(trb->trb_0); 1636 trb_2 = le32toh(trb->trb_2); 1637 trb_3 = le32toh(trb->trb_3); 1638 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1639 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1640 dci = XHCI_TRB_3_EP_GET(trb_3); 1641 xs = &sc->sc_slots[slot]; 1642 xr = &xs->xs_ep[dci].xe_tr; 1643 1644 /* sanity check */ 1645 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1646 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1647 1648 int idx = 0; 1649 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1650 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1651 DPRINTFN(0, "invalid trb_0 0x%"PRIx64, trb_0, 0, 0, 0); 1652 return; 1653 } 1654 xx = xr->xr_cookies[idx]; 1655 1656 /* 1657 * If endpoint is stopped between TDs, TRB pointer points at 1658 * next TRB, however, it is not put yet or is a garbage TRB. 1659 * That's why xr_cookies may be NULL or look like broken. 1660 * Note: this ev happens only when hciversion >= 1.0 or 1661 * hciversion == 0.96 and FSE of hcc1 is set. 1662 */ 1663 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1664 DPRINTFN(1, "xx NULL: #%u: cookie %p: code %u trb_0 %" 1665 PRIx64, idx, xx, trbcode, trb_0); 1666 } 1667 } else { 1668 /* When ED != 0, trb_0 is kaddr of struct xhci_xfer. */ 1669 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1670 } 1671 /* XXX this may not happen */ 1672 if (xx == NULL) { 1673 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1674 return; 1675 } 1676 xfer = &xx->xx_xfer; 1677 /* XXX this may happen when detaching */ 1678 if (xfer == NULL) { 1679 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1680 xx, trb_0, 0, 0); 1681 return; 1682 } 1683 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1684 /* XXX I dunno why this happens */ 1685 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1686 1687 if (!xfer->ux_pipe->up_repeat && 1688 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1689 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1690 return; 1691 } 1692 1693 /* 4.11.5.2 Event Data TRB */ 1694 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1695 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1696 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1697 if ((trb_0 & 0x3) == 0x3) { 1698 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1699 } 1700 } 1701 1702 switch (trbcode) { 1703 case XHCI_TRB_ERROR_SHORT_PKT: 1704 case XHCI_TRB_ERROR_SUCCESS: 1705 xfer->ux_actlen = 1706 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1707 err = USBD_NORMAL_COMPLETION; 1708 break; 1709 case XHCI_TRB_ERROR_STALL: 1710 case XHCI_TRB_ERROR_BABBLE: 1711 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1712 xr->is_halted = true; 1713 err = USBD_STALLED; 1714 /* 1715 * Stalled endpoints can be recoverd by issuing 1716 * command TRB TYPE_RESET_EP on xHCI instead of 1717 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1718 * on the endpoint. However, this function may be 1719 * called from softint context (e.g. from umass), 1720 * in that case driver gets KASSERT in cv_timedwait 1721 * in xhci_do_command. 1722 * To avoid this, this runs reset_endpoint and 1723 * usb_transfer_complete in usb task thread 1724 * asynchronously (and then umass issues clear 1725 * UF_ENDPOINT_HALT). 1726 */ 1727 xfer->ux_status = err; 1728 xhci_clear_endpoint_stall_async(xfer); 1729 return; 1730 default: 1731 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1732 err = USBD_IOERROR; 1733 break; 1734 } 1735 xfer->ux_status = err; 1736 1737 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1738 if ((trb_0 & 0x3) == 0x0) { 1739 callout_stop(&xfer->ux_callout); 1740 usb_transfer_complete(xfer); 1741 } 1742 } else { 1743 callout_stop(&xfer->ux_callout); 1744 usb_transfer_complete(xfer); 1745 } 1746 } 1747 1748 /* Process Command complete events */ 1749 static void 1750 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 1751 { 1752 uint64_t trb_0; 1753 uint32_t trb_2, trb_3; 1754 1755 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1756 1757 trb_0 = le64toh(trb->trb_0); 1758 trb_2 = le32toh(trb->trb_2); 1759 trb_3 = le32toh(trb->trb_3); 1760 1761 if (trb_0 == sc->sc_command_addr) { 1762 sc->sc_result_trb.trb_0 = trb_0; 1763 sc->sc_result_trb.trb_2 = trb_2; 1764 sc->sc_result_trb.trb_3 = trb_3; 1765 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1766 XHCI_TRB_ERROR_SUCCESS) { 1767 DPRINTFN(1, "command completion " 1768 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1769 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1770 } 1771 cv_signal(&sc->sc_command_cv); 1772 } else { 1773 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 1774 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1775 trb_2, trb_3); 1776 } 1777 } 1778 1779 /* 1780 * Process events. 1781 * called from xhci_softintr 1782 */ 1783 static void 1784 xhci_handle_event(struct xhci_softc * const sc, 1785 const struct xhci_trb * const trb) 1786 { 1787 uint64_t trb_0; 1788 uint32_t trb_2, trb_3; 1789 1790 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1791 1792 trb_0 = le64toh(trb->trb_0); 1793 trb_2 = le32toh(trb->trb_2); 1794 trb_3 = le32toh(trb->trb_3); 1795 1796 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1797 trb, trb_0, trb_2, trb_3); 1798 1799 /* 1800 * 4.11.3.1, 6.4.2.1 1801 * TRB Pointer is invalid for these completion codes. 1802 */ 1803 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 1804 case XHCI_TRB_ERROR_RING_UNDERRUN: 1805 case XHCI_TRB_ERROR_RING_OVERRUN: 1806 case XHCI_TRB_ERROR_VF_RING_FULL: 1807 return; 1808 default: 1809 if (trb_0 == 0) { 1810 return; 1811 } 1812 break; 1813 } 1814 1815 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 1816 case XHCI_TRB_EVENT_TRANSFER: 1817 xhci_event_transfer(sc, trb); 1818 break; 1819 case XHCI_TRB_EVENT_CMD_COMPLETE: 1820 xhci_event_cmd(sc, trb); 1821 break; 1822 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1823 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1824 break; 1825 default: 1826 break; 1827 } 1828 } 1829 1830 static void 1831 xhci_softintr(void *v) 1832 { 1833 struct usbd_bus * const bus = v; 1834 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1835 struct xhci_ring * const er = &sc->sc_er; 1836 struct xhci_trb *trb; 1837 int i, j, k; 1838 1839 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1840 1841 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1842 1843 i = er->xr_ep; 1844 j = er->xr_cs; 1845 1846 DPRINTFN(16, "xr_ep %d xr_cs %d", i, j, 0, 0); 1847 1848 while (1) { 1849 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 1850 BUS_DMASYNC_POSTREAD); 1851 trb = &er->xr_trb[i]; 1852 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1853 1854 if (j != k) 1855 break; 1856 1857 xhci_handle_event(sc, trb); 1858 1859 i++; 1860 if (i == er->xr_ntrb) { 1861 i = 0; 1862 j ^= 1; 1863 } 1864 } 1865 1866 er->xr_ep = i; 1867 er->xr_cs = j; 1868 1869 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 1870 XHCI_ERDP_LO_BUSY); 1871 1872 DPRINTFN(16, "ends", 0, 0, 0, 0); 1873 1874 return; 1875 } 1876 1877 static void 1878 xhci_poll(struct usbd_bus *bus) 1879 { 1880 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1881 1882 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1883 1884 mutex_spin_enter(&sc->sc_intr_lock); 1885 xhci_intr1(sc); 1886 mutex_spin_exit(&sc->sc_intr_lock); 1887 1888 return; 1889 } 1890 1891 static struct usbd_xfer * 1892 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 1893 { 1894 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1895 struct usbd_xfer *xfer; 1896 1897 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1898 1899 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1900 if (xfer != NULL) { 1901 memset(xfer, 0, sizeof(struct xhci_xfer)); 1902 #ifdef DIAGNOSTIC 1903 xfer->ux_state = XFER_BUSY; 1904 #endif 1905 } 1906 1907 return xfer; 1908 } 1909 1910 static void 1911 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1912 { 1913 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1914 1915 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1916 1917 #ifdef DIAGNOSTIC 1918 if (xfer->ux_state != XFER_BUSY) { 1919 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 1920 xfer, xfer->ux_state, 0, 0); 1921 } 1922 xfer->ux_state = XFER_FREE; 1923 #endif 1924 pool_cache_put(sc->sc_xferpool, xfer); 1925 } 1926 1927 static void 1928 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1929 { 1930 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1931 1932 *lock = &sc->sc_lock; 1933 } 1934 1935 extern uint32_t usb_cookie_no; 1936 1937 /* 1938 * xHCI 4.3 1939 * Called when uhub_explore finds a new device (via usbd_new_device). 1940 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 1941 * This function does: 1942 * Allocate and construct dev structure of default endpoint (ep0). 1943 * Allocate and open pipe of ep0. 1944 * Enable slot and initialize slot context. 1945 * Set Address. 1946 * Read initial device descriptor. 1947 * Determine initial MaxPacketSize (mps) by speed. 1948 * Read full device descriptor. 1949 * Register this device. 1950 */ 1951 static usbd_status 1952 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 1953 int speed, int port, struct usbd_port *up) 1954 { 1955 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1956 struct usbd_device *dev; 1957 usbd_status err; 1958 usb_device_descriptor_t *dd; 1959 struct xhci_slot *xs; 1960 uint32_t *cp; 1961 1962 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1963 DPRINTFN(4, "port %u depth %u speed %u up %p", port, depth, speed, up); 1964 1965 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 1966 if (dev == NULL) 1967 return USBD_NOMEM; 1968 1969 dev->ud_bus = bus; 1970 dev->ud_quirks = &usbd_no_quirk; 1971 dev->ud_addr = 0; 1972 dev->ud_ddesc.bMaxPacketSize = 0; 1973 dev->ud_depth = depth; 1974 dev->ud_powersrc = up; 1975 dev->ud_myhub = up->up_parent; 1976 dev->ud_speed = speed; 1977 dev->ud_langid = USBD_NOLANG; 1978 dev->ud_cookie.cookie = ++usb_cookie_no; 1979 1980 /* Set up default endpoint handle. */ 1981 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 1982 /* doesn't matter, just don't let it uninitialized */ 1983 dev->ud_ep0.ue_toggle = 0; 1984 1985 /* Set up default endpoint descriptor. */ 1986 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 1987 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 1988 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 1989 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 1990 dev->ud_ep0desc.bInterval = 0; 1991 1992 /* 4.3, 4.8.2.1 */ 1993 switch (speed) { 1994 case USB_SPEED_SUPER: 1995 case USB_SPEED_SUPER_PLUS: 1996 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 1997 break; 1998 case USB_SPEED_FULL: 1999 /* XXX using 64 as initial mps of ep0 in FS */ 2000 case USB_SPEED_HIGH: 2001 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2002 break; 2003 case USB_SPEED_LOW: 2004 default: 2005 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2006 break; 2007 } 2008 2009 up->up_dev = dev; 2010 2011 /* Establish the default pipe. */ 2012 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2013 &dev->ud_pipe0); 2014 if (err) { 2015 goto bad; 2016 } 2017 2018 dd = &dev->ud_ddesc; 2019 2020 if ((depth == 0) && (port == 0)) { 2021 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2022 bus->ub_devices[dev->ud_addr] = dev; 2023 err = usbd_get_initial_ddesc(dev, dd); 2024 if (err) 2025 goto bad; 2026 err = usbd_reload_device_desc(dev); 2027 if (err) 2028 goto bad; 2029 } else { 2030 uint8_t slot = 0; 2031 2032 /* 4.3.2 */ 2033 err = xhci_enable_slot(sc, &slot); 2034 if (err) 2035 goto bad; 2036 2037 xs = &sc->sc_slots[slot]; 2038 dev->ud_hcpriv = xs; 2039 2040 /* 4.3.3 initialize slot structure */ 2041 err = xhci_init_slot(dev, slot); 2042 if (err) { 2043 dev->ud_hcpriv = NULL; 2044 /* 2045 * We have to disable_slot here because 2046 * xs->xs_idx == 0 when xhci_init_slot fails, 2047 * in that case usbd_remove_dev won't work. 2048 */ 2049 mutex_enter(&sc->sc_lock); 2050 xhci_disable_slot(sc, slot); 2051 mutex_exit(&sc->sc_lock); 2052 goto bad; 2053 } 2054 2055 /* 4.3.4 Address Assignment */ 2056 err = xhci_set_address(dev, slot, false); 2057 if (err) 2058 goto bad; 2059 2060 /* Allow device time to set new address */ 2061 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2062 2063 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2064 //hexdump("slot context", cp, sc->sc_ctxsz); 2065 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2066 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2067 /* XXX ensure we know when the hardware does something 2068 we can't yet cope with */ 2069 KASSERT(addr >= 1 && addr <= 127); 2070 dev->ud_addr = addr; 2071 /* XXX dev->ud_addr not necessarily unique on bus */ 2072 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2073 bus->ub_devices[dev->ud_addr] = dev; 2074 2075 err = usbd_get_initial_ddesc(dev, dd); 2076 if (err) 2077 goto bad; 2078 2079 /* 4.8.2.1 */ 2080 if (USB_IS_SS(speed)) { 2081 if (dd->bMaxPacketSize != 9) { 2082 printf("%s: invalid mps 2^%u for SS ep0," 2083 " using 512\n", 2084 device_xname(sc->sc_dev), 2085 dd->bMaxPacketSize); 2086 dd->bMaxPacketSize = 9; 2087 } 2088 USETW(dev->ud_ep0desc.wMaxPacketSize, 2089 (1 << dd->bMaxPacketSize)); 2090 } else 2091 USETW(dev->ud_ep0desc.wMaxPacketSize, 2092 dd->bMaxPacketSize); 2093 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2094 xhci_update_ep0_mps(sc, xs, 2095 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2096 2097 err = usbd_reload_device_desc(dev); 2098 if (err) 2099 goto bad; 2100 } 2101 2102 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2103 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2104 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2105 dd->bDeviceClass, dd->bDeviceSubClass, 2106 dd->bDeviceProtocol, 0); 2107 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2108 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2109 dev->ud_speed); 2110 2111 usbd_get_device_strings(dev); 2112 2113 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2114 2115 if ((depth == 0) && (port == 0)) { 2116 usbd_attach_roothub(parent, dev); 2117 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2118 return USBD_NORMAL_COMPLETION; 2119 } 2120 2121 2122 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2123 bad: 2124 if (err != USBD_NORMAL_COMPLETION) { 2125 usbd_remove_device(dev, up); 2126 } 2127 2128 return err; 2129 } 2130 2131 static usbd_status 2132 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2133 size_t ntrb, size_t align) 2134 { 2135 usbd_status err; 2136 size_t size = ntrb * XHCI_TRB_SIZE; 2137 2138 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2139 2140 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2141 if (err) 2142 return err; 2143 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2144 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2145 xr->xr_trb = xhci_ring_trbv(xr, 0); 2146 xr->xr_ntrb = ntrb; 2147 xr->xr_ep = 0; 2148 xr->xr_cs = 1; 2149 memset(xr->xr_trb, 0, size); 2150 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 2151 xr->is_halted = false; 2152 2153 return USBD_NORMAL_COMPLETION; 2154 } 2155 2156 static void 2157 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2158 { 2159 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2160 mutex_destroy(&xr->xr_lock); 2161 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2162 } 2163 2164 static void 2165 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2166 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2167 { 2168 size_t i; 2169 u_int ri; 2170 u_int cs; 2171 uint64_t parameter; 2172 uint32_t status; 2173 uint32_t control; 2174 2175 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2176 2177 KASSERT(ntrbs <= XHCI_XFER_NTRB); 2178 for (i = 0; i < ntrbs; i++) { 2179 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2180 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2181 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2182 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2183 XHCI_TRB_TYPE_LINK); 2184 } 2185 2186 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2187 2188 ri = xr->xr_ep; 2189 cs = xr->xr_cs; 2190 2191 /* 2192 * Although the xhci hardware can do scatter/gather dma from 2193 * arbitrary sized buffers, there is a non-obvious restriction 2194 * that a LINK trb is only allowed at the end of a burst of 2195 * transfers - which might be 16kB. 2196 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2197 * The simple solution is not to allow a LINK trb in the middle 2198 * of anything - as here. 2199 * XXX: (dsl) There are xhci controllers out there (eg some made by 2200 * ASMedia) that seem to lock up if they process a LINK trb but 2201 * cannot process the linked-to trb yet. 2202 * The code should write the 'cycle' bit on the link trb AFTER 2203 * adding the other trb. 2204 */ 2205 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2206 parameter = xhci_ring_trbp(xr, 0); 2207 status = 0; 2208 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2209 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2210 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2211 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2212 BUS_DMASYNC_PREWRITE); 2213 xr->xr_cookies[ri] = NULL; 2214 xr->xr_ep = 0; 2215 xr->xr_cs ^= 1; 2216 ri = xr->xr_ep; 2217 cs = xr->xr_cs; 2218 } 2219 2220 ri++; 2221 2222 /* Write any subsequent TRB first */ 2223 for (i = 1; i < ntrbs; i++) { 2224 parameter = trbs[i].trb_0; 2225 status = trbs[i].trb_2; 2226 control = trbs[i].trb_3; 2227 2228 if (cs) { 2229 control |= XHCI_TRB_3_CYCLE_BIT; 2230 } else { 2231 control &= ~XHCI_TRB_3_CYCLE_BIT; 2232 } 2233 2234 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2235 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2236 BUS_DMASYNC_PREWRITE); 2237 xr->xr_cookies[ri] = cookie; 2238 ri++; 2239 } 2240 2241 /* Write the first TRB last */ 2242 i = 0; 2243 parameter = trbs[i].trb_0; 2244 status = trbs[i].trb_2; 2245 control = trbs[i].trb_3; 2246 2247 if (xr->xr_cs) { 2248 control |= XHCI_TRB_3_CYCLE_BIT; 2249 } else { 2250 control &= ~XHCI_TRB_3_CYCLE_BIT; 2251 } 2252 2253 xhci_trb_put(&xr->xr_trb[xr->xr_ep], parameter, status, control); 2254 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * xr->xr_ep, XHCI_TRB_SIZE * 1, 2255 BUS_DMASYNC_PREWRITE); 2256 xr->xr_cookies[xr->xr_ep] = cookie; 2257 2258 xr->xr_ep = ri; 2259 xr->xr_cs = cs; 2260 2261 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2262 } 2263 2264 /* 2265 * Stop execution commands, purge all commands on command ring, and 2266 * rewind enqueue pointer. 2267 */ 2268 static void 2269 xhci_abort_command(struct xhci_softc *sc) 2270 { 2271 struct xhci_ring * const cr = &sc->sc_cr; 2272 uint64_t crcr; 2273 int i; 2274 2275 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2276 DPRINTFN(14, "command %#"PRIx64" timeout, aborting", 2277 sc->sc_command_addr, 0, 0, 0); 2278 2279 mutex_enter(&cr->xr_lock); 2280 2281 /* 4.6.1.2 Aborting a Command */ 2282 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2283 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2284 2285 for (i = 0; i < 500; i++) { 2286 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2287 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2288 break; 2289 usb_delay_ms(&sc->sc_bus, 1); 2290 } 2291 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2292 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2293 /* reset HC here? */ 2294 } 2295 2296 /* reset command ring dequeue pointer */ 2297 cr->xr_ep = 0; 2298 cr->xr_cs = 1; 2299 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2300 2301 mutex_exit(&cr->xr_lock); 2302 } 2303 2304 /* 2305 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2306 * Command completion is notified by cv_signal from xhci_handle_event 2307 * (called from interrupt from xHCI), or timed-out. 2308 * Command validation is performed in xhci_handle_event by checking if 2309 * trb_0 in CMD_COMPLETE TRB and sc->sc_command_addr are identical. 2310 */ 2311 static usbd_status 2312 xhci_do_command_locked(struct xhci_softc * const sc, 2313 struct xhci_trb * const trb, int timeout) 2314 { 2315 struct xhci_ring * const cr = &sc->sc_cr; 2316 usbd_status err; 2317 2318 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2319 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2320 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2321 2322 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2323 KASSERT(mutex_owned(&sc->sc_lock)); 2324 2325 /* XXX KASSERT may fire when cv_timedwait unlocks sc_lock */ 2326 KASSERT(sc->sc_command_addr == 0); 2327 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2328 2329 mutex_enter(&cr->xr_lock); 2330 xhci_ring_put(sc, cr, NULL, trb, 1); 2331 mutex_exit(&cr->xr_lock); 2332 2333 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2334 2335 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2336 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2337 xhci_abort_command(sc); 2338 err = USBD_TIMEOUT; 2339 goto timedout; 2340 } 2341 2342 trb->trb_0 = sc->sc_result_trb.trb_0; 2343 trb->trb_2 = sc->sc_result_trb.trb_2; 2344 trb->trb_3 = sc->sc_result_trb.trb_3; 2345 2346 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2347 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2348 2349 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2350 case XHCI_TRB_ERROR_SUCCESS: 2351 err = USBD_NORMAL_COMPLETION; 2352 break; 2353 default: 2354 case 192 ... 223: 2355 err = USBD_IOERROR; 2356 break; 2357 case 224 ... 255: 2358 err = USBD_NORMAL_COMPLETION; 2359 break; 2360 } 2361 2362 timedout: 2363 sc->sc_command_addr = 0; 2364 return err; 2365 } 2366 2367 static usbd_status 2368 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2369 int timeout) 2370 { 2371 2372 mutex_enter(&sc->sc_lock); 2373 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2374 mutex_exit(&sc->sc_lock); 2375 2376 return ret; 2377 } 2378 2379 static usbd_status 2380 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2381 { 2382 struct xhci_trb trb; 2383 usbd_status err; 2384 2385 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2386 2387 trb.trb_0 = 0; 2388 trb.trb_2 = 0; 2389 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2390 2391 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2392 if (err != USBD_NORMAL_COMPLETION) { 2393 return err; 2394 } 2395 2396 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2397 2398 return err; 2399 } 2400 2401 /* 2402 * xHCI 4.6.4 2403 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2404 * All endpoints in the slot should be stopped. 2405 * Should be called with sc_lock held. 2406 */ 2407 static usbd_status 2408 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2409 { 2410 struct xhci_trb trb; 2411 struct xhci_slot *xs; 2412 usbd_status err; 2413 2414 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2415 2416 if (sc->sc_dying) 2417 return USBD_IOERROR; 2418 2419 trb.trb_0 = 0; 2420 trb.trb_2 = 0; 2421 trb.trb_3 = htole32( 2422 XHCI_TRB_3_SLOT_SET(slot) | 2423 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2424 2425 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2426 2427 if (!err) { 2428 xs = &sc->sc_slots[slot]; 2429 if (xs->xs_idx != 0) { 2430 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2431 xhci_set_dcba(sc, 0, slot); 2432 memset(xs, 0, sizeof(*xs)); 2433 } 2434 } 2435 2436 return err; 2437 } 2438 2439 /* 2440 * Set address of device and transition slot state from ENABLED to ADDRESSED 2441 * if Block Setaddress Request (BSR) is false. 2442 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2443 * see xHCI 1.1 4.5.3, 3.3.4 2444 * Should be called without sc_lock held. 2445 */ 2446 static usbd_status 2447 xhci_address_device(struct xhci_softc * const sc, 2448 uint64_t icp, uint8_t slot_id, bool bsr) 2449 { 2450 struct xhci_trb trb; 2451 usbd_status err; 2452 2453 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2454 2455 trb.trb_0 = icp; 2456 trb.trb_2 = 0; 2457 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2458 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2459 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2460 2461 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2462 2463 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2464 err = USBD_NO_ADDR; 2465 2466 return err; 2467 } 2468 2469 static usbd_status 2470 xhci_update_ep0_mps(struct xhci_softc * const sc, 2471 struct xhci_slot * const xs, u_int mps) 2472 { 2473 struct xhci_trb trb; 2474 usbd_status err; 2475 uint32_t * cp; 2476 2477 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2478 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2479 2480 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2481 cp[0] = htole32(0); 2482 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2483 2484 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2485 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2486 2487 /* sync input contexts before they are read from memory */ 2488 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2489 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2490 sc->sc_ctxsz * 4); 2491 2492 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2493 trb.trb_2 = 0; 2494 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2495 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2496 2497 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2498 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2499 return err; 2500 } 2501 2502 static void 2503 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2504 { 2505 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2506 2507 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2508 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2509 &dcbaa[si], dcba, si, 0); 2510 2511 dcbaa[si] = htole64(dcba); 2512 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2513 BUS_DMASYNC_PREWRITE); 2514 } 2515 2516 /* 2517 * Allocate device and input context DMA buffer, and 2518 * TRB DMA buffer for each endpoint. 2519 */ 2520 static usbd_status 2521 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2522 { 2523 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2524 struct xhci_slot *xs; 2525 usbd_status err; 2526 u_int dci; 2527 2528 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2529 DPRINTFN(4, "slot %u", slot, 0, 0, 0); 2530 2531 xs = &sc->sc_slots[slot]; 2532 2533 /* allocate contexts */ 2534 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2535 &xs->xs_dc_dma); 2536 if (err) 2537 return err; 2538 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2539 2540 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2541 &xs->xs_ic_dma); 2542 if (err) 2543 goto bad1; 2544 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2545 2546 for (dci = 0; dci < 32; dci++) { 2547 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2548 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2549 if (dci == XHCI_DCI_SLOT) 2550 continue; 2551 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2552 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2553 if (err) { 2554 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2555 goto bad2; 2556 } 2557 } 2558 2559 bad2: 2560 if (err == USBD_NORMAL_COMPLETION) { 2561 xs->xs_idx = slot; 2562 } else { 2563 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2564 } 2565 2566 return err; 2567 2568 bad1: 2569 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2570 xs->xs_idx = 0; 2571 return err; 2572 } 2573 2574 static void 2575 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2576 int end_dci) 2577 { 2578 u_int dci; 2579 2580 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2581 DPRINTFN(4, "slot %u start %u end %u", xs->xs_idx, start_dci, end_dci, 2582 0); 2583 2584 for (dci = start_dci; dci < end_dci; dci++) { 2585 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2586 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2587 } 2588 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2589 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2590 xs->xs_idx = 0; 2591 } 2592 2593 /* 2594 * Setup slot context, set Device Context Base Address, and issue 2595 * Set Address Device command. 2596 */ 2597 static usbd_status 2598 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 2599 { 2600 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2601 struct xhci_slot *xs; 2602 usbd_status err; 2603 2604 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2605 DPRINTFN(4, "slot %u bsr %u", slot, bsr, 0, 0); 2606 2607 xs = &sc->sc_slots[slot]; 2608 2609 xhci_setup_ctx(dev->ud_pipe0); 2610 2611 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2612 sc->sc_ctxsz * 3); 2613 2614 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2615 2616 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 2617 2618 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2619 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2620 sc->sc_ctxsz * 2); 2621 2622 return err; 2623 } 2624 2625 /* 2626 * 4.8.2, 6.2.3.2 2627 * construct slot/endpoint context parameters and do syncmem 2628 */ 2629 static void 2630 xhci_setup_ctx(struct usbd_pipe *pipe) 2631 { 2632 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2633 struct usbd_device *dev = pipe->up_dev; 2634 struct xhci_slot * const xs = dev->ud_hcpriv; 2635 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2636 const u_int dci = xhci_ep_get_dci(ed); 2637 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2638 uint32_t *cp; 2639 uint16_t mps = UGETW(ed->wMaxPacketSize); 2640 uint8_t speed = dev->ud_speed; 2641 uint8_t ival = ed->bInterval; 2642 2643 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2644 DPRINTFN(4, "pipe %p: slot %u dci %u speed %u", pipe, xs->xs_idx, dci, 2645 speed); 2646 2647 /* set up initial input control context */ 2648 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2649 cp[0] = htole32(0); 2650 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 2651 if (dci == XHCI_DCI_EP_CONTROL) 2652 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2653 cp[7] = htole32(0); 2654 2655 /* set up input slot context */ 2656 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2657 cp[0] = 2658 XHCI_SCTX_0_CTX_NUM_SET(dci) | 2659 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 2660 cp[1] = 0; 2661 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2662 cp[3] = 0; 2663 xhci_setup_route(pipe, cp); 2664 xhci_setup_tthub(pipe, cp); 2665 2666 cp[0] = htole32(cp[0]); 2667 cp[1] = htole32(cp[1]); 2668 cp[2] = htole32(cp[2]); 2669 cp[3] = htole32(cp[3]); 2670 2671 /* set up input endpoint context */ 2672 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 2673 cp[0] = 2674 XHCI_EPCTX_0_EPSTATE_SET(0) | 2675 XHCI_EPCTX_0_MULT_SET(0) | 2676 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2677 XHCI_EPCTX_0_LSA_SET(0) | 2678 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 2679 cp[1] = 2680 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 2681 XHCI_EPCTX_1_HID_SET(0) | 2682 XHCI_EPCTX_1_MAXB_SET(0); 2683 2684 if (xfertype != UE_ISOCHRONOUS) 2685 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 2686 2687 if (xfertype == UE_CONTROL) 2688 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 2689 else if (USB_IS_SS(speed)) 2690 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 2691 else 2692 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 2693 2694 xhci_setup_maxburst(pipe, cp); 2695 2696 switch (xfertype) { 2697 case UE_CONTROL: 2698 break; 2699 case UE_BULK: 2700 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 2701 break; 2702 case UE_INTERRUPT: 2703 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 2704 ival = pipe->up_interval; 2705 2706 ival = xhci_bival2ival(ival, speed); 2707 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 2708 break; 2709 case UE_ISOCHRONOUS: 2710 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 2711 ival = pipe->up_interval; 2712 2713 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 2714 if (speed == USB_SPEED_FULL) 2715 ival += 3; /* 1ms -> 125us */ 2716 ival--; 2717 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 2718 break; 2719 default: 2720 break; 2721 } 2722 2723 /* can't use xhci_ep_get_dci() yet? */ 2724 *(uint64_t *)(&cp[2]) = htole64( 2725 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 2726 XHCI_EPCTX_2_DCS_SET(1)); 2727 2728 cp[0] = htole32(cp[0]); 2729 cp[1] = htole32(cp[1]); 2730 cp[4] = htole32(cp[4]); 2731 2732 /* sync input contexts before they are read from memory */ 2733 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2734 } 2735 2736 /* 2737 * Setup route string and roothub port of given device for slot context 2738 */ 2739 static void 2740 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 2741 { 2742 struct usbd_device *dev = pipe->up_dev; 2743 struct usbd_port *up = dev->ud_powersrc; 2744 struct usbd_device *hub; 2745 struct usbd_device *adev; 2746 uint8_t rhport = 0; 2747 uint32_t route = 0; 2748 2749 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2750 2751 /* Locate root hub port and Determine route string */ 2752 /* 4.3.3 route string does not include roothub port */ 2753 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2754 uint32_t dep; 2755 2756 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2757 hub, hub->ud_depth, hub->ud_powersrc, 2758 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2759 2760 if (hub->ud_powersrc == NULL) 2761 break; 2762 dep = hub->ud_depth; 2763 if (dep == 0) 2764 break; 2765 rhport = hub->ud_powersrc->up_portno; 2766 if (dep > USB_HUB_MAX_DEPTH) 2767 continue; 2768 2769 route |= 2770 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2771 << ((dep - 1) * 4); 2772 } 2773 route = route >> 4; 2774 DPRINTFN(4, "rhport %u Route %05x hub %p", rhport, route, hub, 0); 2775 2776 /* Locate port on upstream high speed hub */ 2777 for (adev = dev, hub = up->up_parent; 2778 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2779 adev = hub, hub = hub->ud_myhub) 2780 ; 2781 if (hub) { 2782 int p; 2783 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2784 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2785 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2786 goto found; 2787 } 2788 } 2789 panic("xhci_setup_route: cannot find HS port"); 2790 found: 2791 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2792 } else { 2793 dev->ud_myhsport = NULL; 2794 } 2795 2796 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 2797 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(rhport); 2798 } 2799 2800 /* 2801 * Setup whether device is hub, whether device uses MTT, and 2802 * TT informations if it uses MTT. 2803 */ 2804 static void 2805 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 2806 { 2807 struct usbd_device *dev = pipe->up_dev; 2808 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 2809 uint32_t speed = dev->ud_speed; 2810 uint8_t tthubslot, ttportnum; 2811 bool ishub; 2812 bool usemtt; 2813 2814 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2815 2816 /* 2817 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 2818 * tthubslot: 2819 * This is the slot ID of parent HS hub 2820 * if LS/FS device is connected && connected through HS hub. 2821 * This is 0 if device is not LS/FS device || 2822 * parent hub is not HS hub || 2823 * attached to root hub. 2824 * ttportnum: 2825 * This is the downstream facing port of parent HS hub 2826 * if LS/FS device is connected. 2827 * This is 0 if device is not LS/FS device || 2828 * parent hub is not HS hub || 2829 * attached to root hub. 2830 */ 2831 if (dev->ud_myhsport != NULL && 2832 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 2833 (dev->ud_myhub != NULL && 2834 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 2835 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 2836 ttportnum = dev->ud_myhsport->up_portno; 2837 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 2838 } else { 2839 ttportnum = 0; 2840 tthubslot = 0; 2841 } 2842 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 2843 dev->ud_myhsport, ttportnum, tthubslot, 0); 2844 2845 /* ishub is valid after reading UDESC_DEVICE */ 2846 ishub = (dd->bDeviceClass == UDCLASS_HUB); 2847 2848 /* dev->ud_hub is valid after reading UDESC_HUB */ 2849 if (ishub && dev->ud_hub) { 2850 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 2851 uint8_t ttt = 2852 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 2853 2854 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 2855 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 2856 DPRINTFN(4, "nports=%d ttt=%d", hd->bNbrPorts, ttt, 0, 0); 2857 } 2858 2859 #define IS_TTHUB(dd) \ 2860 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 2861 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 2862 2863 /* 2864 * MTT flag is set if 2865 * 1. this is HS hub && MTT is enabled 2866 * or 2867 * 2. this is not hub && this is LS or FS device && 2868 * MTT of parent HS hub (and its parent, too) is enabled 2869 */ 2870 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 2871 usemtt = true; 2872 else if (!ishub && 2873 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 2874 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 2875 (dev->ud_myhub != NULL && 2876 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 2877 dev->ud_myhsport != NULL && 2878 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 2879 usemtt = true; 2880 else 2881 usemtt = false; 2882 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 2883 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 2884 2885 #undef IS_TTHUB 2886 2887 cp[0] |= 2888 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 2889 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 2890 cp[2] |= 2891 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 2892 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 2893 } 2894 2895 /* set up params for periodic endpoint */ 2896 static void 2897 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 2898 { 2899 struct usbd_device *dev = pipe->up_dev; 2900 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2901 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2902 usbd_desc_iter_t iter; 2903 const usb_cdc_descriptor_t *cdcd; 2904 uint32_t maxb = 0; 2905 uint16_t mps = UGETW(ed->wMaxPacketSize); 2906 uint8_t speed = dev->ud_speed; 2907 uint8_t ep; 2908 2909 /* config desc is NULL when opening ep0 */ 2910 if (dev == NULL || dev->ud_cdesc == NULL) 2911 goto no_cdcd; 2912 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 2913 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 2914 if (cdcd == NULL) 2915 goto no_cdcd; 2916 usb_desc_iter_init(dev, &iter); 2917 iter.cur = (const void *)cdcd; 2918 2919 /* find endpoint_ss_comp desc for ep of this pipe */ 2920 for (ep = 0;;) { 2921 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 2922 if (cdcd == NULL) 2923 break; 2924 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 2925 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 2926 bEndpointAddress; 2927 if (UE_GET_ADDR(ep) == 2928 UE_GET_ADDR(ed->bEndpointAddress)) { 2929 cdcd = (const usb_cdc_descriptor_t *) 2930 usb_desc_iter_next(&iter); 2931 break; 2932 } 2933 ep = 0; 2934 } 2935 } 2936 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 2937 const usb_endpoint_ss_comp_descriptor_t * esscd = 2938 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 2939 maxb = esscd->bMaxBurst; 2940 } 2941 2942 no_cdcd: 2943 /* 6.2.3.4, 4.8.2.4 */ 2944 if (USB_IS_SS(speed)) { 2945 /* UBS 3.1 9.6.6 */ 2946 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 2947 /* UBS 3.1 9.6.7 */ 2948 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 2949 #ifdef notyet 2950 if (xfertype == UE_ISOCHRONOUS) { 2951 } 2952 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 2953 /* use ESIT */ 2954 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 2955 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 2956 2957 /* XXX if LEC = 1, set ESIT instead */ 2958 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 2959 } else { 2960 /* use ival */ 2961 } 2962 #endif 2963 } else { 2964 /* UBS 2.0 9.6.6 */ 2965 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 2966 2967 /* 6.2.3.4 */ 2968 if (speed == USB_SPEED_HIGH && 2969 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 2970 maxb = UE_GET_TRANS(mps); 2971 } else { 2972 /* LS/FS or HS CTRL or HS BULK */ 2973 maxb = 0; 2974 } 2975 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 2976 } 2977 } 2978 2979 /* 2980 * Convert endpoint bInterval value to endpoint context interval value 2981 * for Interrupt pipe. 2982 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 2983 */ 2984 static uint32_t 2985 xhci_bival2ival(uint32_t ival, uint32_t speed) 2986 { 2987 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 2988 int i; 2989 2990 /* 2991 * round ival down to "the nearest base 2 multiple of 2992 * bInterval * 8". 2993 * bInterval is at most 255 as its type is uByte. 2994 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 2995 */ 2996 for (i = 10; i > 0; i--) { 2997 if ((ival * 8) >= (1 << i)) 2998 break; 2999 } 3000 ival = i; 3001 } else { 3002 /* Interval = bInterval-1 for SS/HS */ 3003 ival--; 3004 } 3005 3006 return ival; 3007 } 3008 3009 /* ----- */ 3010 3011 static void 3012 xhci_noop(struct usbd_pipe *pipe) 3013 { 3014 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3015 } 3016 3017 /* 3018 * Process root hub request. 3019 */ 3020 static int 3021 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3022 void *buf, int buflen) 3023 { 3024 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3025 usb_port_status_t ps; 3026 int l, totlen = 0; 3027 uint16_t len, value, index; 3028 int port, i; 3029 uint32_t v; 3030 3031 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3032 3033 if (sc->sc_dying) 3034 return -1; 3035 3036 len = UGETW(req->wLength); 3037 value = UGETW(req->wValue); 3038 index = UGETW(req->wIndex); 3039 3040 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 3041 req->bmRequestType | (req->bRequest << 8), value, index, len); 3042 3043 #define C(x,y) ((x) | ((y) << 8)) 3044 switch (C(req->bRequest, req->bmRequestType)) { 3045 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3046 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 3047 if (len == 0) 3048 break; 3049 switch (value) { 3050 case C(0, UDESC_DEVICE): { 3051 usb_device_descriptor_t devd; 3052 totlen = min(buflen, sizeof(devd)); 3053 memcpy(&devd, buf, totlen); 3054 USETW(devd.idVendor, sc->sc_id_vendor); 3055 memcpy(buf, &devd, totlen); 3056 break; 3057 } 3058 #define sd ((usb_string_descriptor_t *)buf) 3059 case C(1, UDESC_STRING): 3060 /* Vendor */ 3061 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3062 break; 3063 case C(2, UDESC_STRING): 3064 /* Product */ 3065 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3066 break; 3067 #undef sd 3068 default: 3069 /* default from usbroothub */ 3070 return buflen; 3071 } 3072 break; 3073 3074 /* Hub requests */ 3075 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3076 break; 3077 /* Clear Port Feature request */ 3078 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3079 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 3080 index, value, 0, 0); 3081 if (index < 1 || index > sc->sc_maxports) { 3082 return -1; 3083 } 3084 port = XHCI_PORTSC(index); 3085 v = xhci_op_read_4(sc, port); 3086 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3087 v &= ~XHCI_PS_CLEAR; 3088 switch (value) { 3089 case UHF_PORT_ENABLE: 3090 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3091 break; 3092 case UHF_PORT_SUSPEND: 3093 return -1; 3094 case UHF_PORT_POWER: 3095 break; 3096 case UHF_PORT_TEST: 3097 case UHF_PORT_INDICATOR: 3098 return -1; 3099 case UHF_C_PORT_CONNECTION: 3100 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3101 break; 3102 case UHF_C_PORT_ENABLE: 3103 case UHF_C_PORT_SUSPEND: 3104 case UHF_C_PORT_OVER_CURRENT: 3105 return -1; 3106 case UHF_C_BH_PORT_RESET: 3107 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3108 break; 3109 case UHF_C_PORT_RESET: 3110 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3111 break; 3112 case UHF_C_PORT_LINK_STATE: 3113 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3114 break; 3115 case UHF_C_PORT_CONFIG_ERROR: 3116 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3117 break; 3118 default: 3119 return -1; 3120 } 3121 break; 3122 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3123 if (len == 0) 3124 break; 3125 if ((value & 0xff) != 0) { 3126 return -1; 3127 } 3128 usb_hub_descriptor_t hubd; 3129 3130 totlen = min(buflen, sizeof(hubd)); 3131 memcpy(&hubd, buf, totlen); 3132 hubd.bNbrPorts = sc->sc_maxports; 3133 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3134 hubd.bPwrOn2PwrGood = 200; 3135 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 3136 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 3137 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3138 totlen = min(totlen, hubd.bDescLength); 3139 memcpy(buf, &hubd, totlen); 3140 break; 3141 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3142 if (len != 4) { 3143 return -1; 3144 } 3145 memset(buf, 0, len); /* ? XXX */ 3146 totlen = len; 3147 break; 3148 /* Get Port Status request */ 3149 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3150 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 3151 if (index < 1 || index > sc->sc_maxports) { 3152 return -1; 3153 } 3154 if (len != 4) { 3155 return -1; 3156 } 3157 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 3158 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 3159 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3160 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3161 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3162 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3163 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3164 if (v & XHCI_PS_PR) i |= UPS_RESET; 3165 if (v & XHCI_PS_PP) { 3166 if (i & UPS_OTHER_SPEED) 3167 i |= UPS_PORT_POWER_SS; 3168 else 3169 i |= UPS_PORT_POWER; 3170 } 3171 if (i & UPS_OTHER_SPEED) 3172 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3173 if (sc->sc_vendor_port_status) 3174 i = sc->sc_vendor_port_status(sc, v, i); 3175 USETW(ps.wPortStatus, i); 3176 i = 0; 3177 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3178 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3179 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3180 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3181 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3182 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3183 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3184 USETW(ps.wPortChange, i); 3185 totlen = min(len, sizeof(ps)); 3186 memcpy(buf, &ps, totlen); 3187 break; 3188 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3189 return -1; 3190 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3191 break; 3192 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3193 break; 3194 /* Set Port Feature request */ 3195 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3196 int optval = (index >> 8) & 0xff; 3197 index &= 0xff; 3198 if (index < 1 || index > sc->sc_maxports) { 3199 return -1; 3200 } 3201 port = XHCI_PORTSC(index); 3202 v = xhci_op_read_4(sc, port); 3203 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3204 v &= ~XHCI_PS_CLEAR; 3205 switch (value) { 3206 case UHF_PORT_ENABLE: 3207 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3208 break; 3209 case UHF_PORT_SUSPEND: 3210 /* XXX suspend */ 3211 break; 3212 case UHF_PORT_RESET: 3213 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3214 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3215 /* Wait for reset to complete. */ 3216 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3217 if (sc->sc_dying) { 3218 return -1; 3219 } 3220 v = xhci_op_read_4(sc, port); 3221 if (v & XHCI_PS_PR) { 3222 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3223 usb_delay_ms(&sc->sc_bus, 10); 3224 /* XXX */ 3225 } 3226 break; 3227 case UHF_PORT_POWER: 3228 /* XXX power control */ 3229 break; 3230 /* XXX more */ 3231 case UHF_C_PORT_RESET: 3232 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3233 break; 3234 case UHF_PORT_U1_TIMEOUT: 3235 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3236 return -1; 3237 } 3238 port = XHCI_PORTPMSC(index); 3239 v = xhci_op_read_4(sc, port); 3240 v &= ~XHCI_PM3_U1TO_SET(0xff); 3241 v |= XHCI_PM3_U1TO_SET(optval); 3242 xhci_op_write_4(sc, port, v); 3243 break; 3244 case UHF_PORT_U2_TIMEOUT: 3245 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3246 return -1; 3247 } 3248 port = XHCI_PORTPMSC(index); 3249 v = xhci_op_read_4(sc, port); 3250 v &= ~XHCI_PM3_U2TO_SET(0xff); 3251 v |= XHCI_PM3_U2TO_SET(optval); 3252 xhci_op_write_4(sc, port, v); 3253 break; 3254 default: 3255 return -1; 3256 } 3257 } 3258 break; 3259 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3260 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3261 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3262 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3263 break; 3264 default: 3265 /* default from usbroothub */ 3266 return buflen; 3267 } 3268 3269 return totlen; 3270 } 3271 3272 /* root hub interrupt */ 3273 3274 static usbd_status 3275 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3276 { 3277 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3278 usbd_status err; 3279 3280 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3281 3282 /* Insert last in queue. */ 3283 mutex_enter(&sc->sc_lock); 3284 err = usb_insert_transfer(xfer); 3285 mutex_exit(&sc->sc_lock); 3286 if (err) 3287 return err; 3288 3289 /* Pipe isn't running, start first */ 3290 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3291 } 3292 3293 /* Wait for roothub port status/change */ 3294 static usbd_status 3295 xhci_root_intr_start(struct usbd_xfer *xfer) 3296 { 3297 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3298 3299 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3300 3301 if (sc->sc_dying) 3302 return USBD_IOERROR; 3303 3304 mutex_enter(&sc->sc_lock); 3305 sc->sc_intrxfer = xfer; 3306 mutex_exit(&sc->sc_lock); 3307 3308 return USBD_IN_PROGRESS; 3309 } 3310 3311 static void 3312 xhci_root_intr_abort(struct usbd_xfer *xfer) 3313 { 3314 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3315 3316 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3317 3318 KASSERT(mutex_owned(&sc->sc_lock)); 3319 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3320 3321 sc->sc_intrxfer = NULL; 3322 3323 xfer->ux_status = USBD_CANCELLED; 3324 usb_transfer_complete(xfer); 3325 } 3326 3327 static void 3328 xhci_root_intr_close(struct usbd_pipe *pipe) 3329 { 3330 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3331 3332 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3333 3334 KASSERT(mutex_owned(&sc->sc_lock)); 3335 3336 sc->sc_intrxfer = NULL; 3337 } 3338 3339 static void 3340 xhci_root_intr_done(struct usbd_xfer *xfer) 3341 { 3342 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3343 3344 } 3345 3346 /* -------------- */ 3347 /* device control */ 3348 3349 static usbd_status 3350 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3351 { 3352 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3353 usbd_status err; 3354 3355 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3356 3357 /* Insert last in queue. */ 3358 mutex_enter(&sc->sc_lock); 3359 err = usb_insert_transfer(xfer); 3360 mutex_exit(&sc->sc_lock); 3361 if (err) 3362 return err; 3363 3364 /* Pipe isn't running, start first */ 3365 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3366 } 3367 3368 static usbd_status 3369 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3370 { 3371 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3372 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3373 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3374 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3375 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3376 usb_device_request_t * const req = &xfer->ux_request; 3377 const int isread = usbd_xfer_isread(xfer); 3378 const uint32_t len = UGETW(req->wLength); 3379 usb_dma_t * const dma = &xfer->ux_dmabuf; 3380 uint64_t parameter; 3381 uint32_t status; 3382 uint32_t control; 3383 u_int i; 3384 3385 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3386 DPRINTFN(12, "req: %04x %04x %04x %04x", 3387 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3388 UGETW(req->wIndex), UGETW(req->wLength)); 3389 3390 /* we rely on the bottom bits for extra info */ 3391 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 3392 3393 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3394 3395 i = 0; 3396 3397 /* setup phase */ 3398 memcpy(¶meter, req, sizeof(*req)); 3399 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3400 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3401 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3402 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3403 XHCI_TRB_3_IDT_BIT; 3404 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3405 3406 if (len != 0) { 3407 /* data phase */ 3408 parameter = DMAADDR(dma, 0); 3409 KASSERT(len <= 0x10000); 3410 status = XHCI_TRB_2_IRQ_SET(0) | 3411 XHCI_TRB_2_TDSZ_SET(1) | 3412 XHCI_TRB_2_BYTES_SET(len); 3413 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3414 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3415 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3416 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3417 3418 parameter = (uintptr_t)xfer | 0x3; 3419 status = XHCI_TRB_2_IRQ_SET(0); 3420 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3421 XHCI_TRB_3_IOC_BIT; 3422 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3423 } 3424 3425 parameter = 0; 3426 status = XHCI_TRB_2_IRQ_SET(0); 3427 /* the status stage has inverted direction */ 3428 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3429 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3430 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3431 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3432 3433 parameter = (uintptr_t)xfer | 0x0; 3434 status = XHCI_TRB_2_IRQ_SET(0); 3435 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3436 XHCI_TRB_3_IOC_BIT; 3437 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3438 3439 mutex_enter(&tr->xr_lock); 3440 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3441 mutex_exit(&tr->xr_lock); 3442 3443 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3444 3445 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3446 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3447 xhci_timeout, xfer); 3448 } 3449 3450 return USBD_IN_PROGRESS; 3451 } 3452 3453 static void 3454 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3455 { 3456 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3457 usb_device_request_t *req = &xfer->ux_request; 3458 int len = UGETW(req->wLength); 3459 int rd = req->bmRequestType & UT_READ; 3460 3461 if (len) 3462 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3463 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3464 } 3465 3466 static void 3467 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3468 { 3469 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3470 3471 xhci_abort_xfer(xfer, USBD_CANCELLED); 3472 } 3473 3474 static void 3475 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3476 { 3477 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3478 3479 xhci_close_pipe(pipe); 3480 } 3481 3482 /* ------------------ */ 3483 /* device isochronous */ 3484 3485 /* ----------- */ 3486 /* device bulk */ 3487 3488 static usbd_status 3489 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3490 { 3491 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3492 usbd_status err; 3493 3494 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3495 3496 /* Insert last in queue. */ 3497 mutex_enter(&sc->sc_lock); 3498 err = usb_insert_transfer(xfer); 3499 mutex_exit(&sc->sc_lock); 3500 if (err) 3501 return err; 3502 3503 /* 3504 * Pipe isn't running (otherwise err would be USBD_INPROG), 3505 * so start it first. 3506 */ 3507 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3508 } 3509 3510 static usbd_status 3511 xhci_device_bulk_start(struct usbd_xfer *xfer) 3512 { 3513 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3514 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3515 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3516 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3517 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3518 const uint32_t len = xfer->ux_length; 3519 usb_dma_t * const dma = &xfer->ux_dmabuf; 3520 uint64_t parameter; 3521 uint32_t status; 3522 uint32_t control; 3523 u_int i = 0; 3524 3525 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3526 3527 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3528 3529 if (sc->sc_dying) 3530 return USBD_IOERROR; 3531 3532 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3533 3534 parameter = DMAADDR(dma, 0); 3535 /* 3536 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3537 * If the user supplied buffer crosses such a boundary then 2 3538 * (or more) TRB should be used. 3539 * If multiple TRB are used the td_size field must be set correctly. 3540 * For v1.0 devices (like ivy bridge) this is the number of usb data 3541 * blocks needed to complete the transfer. 3542 * Setting it to 1 in the last TRB causes an extra zero-length 3543 * data block be sent. 3544 * The earlier documentation differs, I don't know how it behaves. 3545 */ 3546 KASSERT(len <= 0x10000); 3547 status = XHCI_TRB_2_IRQ_SET(0) | 3548 XHCI_TRB_2_TDSZ_SET(1) | 3549 XHCI_TRB_2_BYTES_SET(len); 3550 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3551 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3552 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3553 3554 mutex_enter(&tr->xr_lock); 3555 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3556 mutex_exit(&tr->xr_lock); 3557 3558 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3559 3560 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3561 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3562 xhci_timeout, xfer); 3563 } 3564 3565 return USBD_IN_PROGRESS; 3566 } 3567 3568 static void 3569 xhci_device_bulk_done(struct usbd_xfer *xfer) 3570 { 3571 #ifdef USB_DEBUG 3572 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3573 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3574 #endif 3575 const int isread = usbd_xfer_isread(xfer); 3576 3577 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3578 3579 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3580 3581 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3582 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3583 } 3584 3585 static void 3586 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3587 { 3588 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3589 3590 xhci_abort_xfer(xfer, USBD_CANCELLED); 3591 } 3592 3593 static void 3594 xhci_device_bulk_close(struct usbd_pipe *pipe) 3595 { 3596 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3597 3598 xhci_close_pipe(pipe); 3599 } 3600 3601 /* ---------------- */ 3602 /* device interrupt */ 3603 3604 static usbd_status 3605 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3606 { 3607 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3608 usbd_status err; 3609 3610 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3611 3612 /* Insert last in queue. */ 3613 mutex_enter(&sc->sc_lock); 3614 err = usb_insert_transfer(xfer); 3615 mutex_exit(&sc->sc_lock); 3616 if (err) 3617 return err; 3618 3619 /* 3620 * Pipe isn't running (otherwise err would be USBD_INPROG), 3621 * so start it first. 3622 */ 3623 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3624 } 3625 3626 static usbd_status 3627 xhci_device_intr_start(struct usbd_xfer *xfer) 3628 { 3629 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3630 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3631 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3632 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3633 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3634 const uint32_t len = xfer->ux_length; 3635 usb_dma_t * const dma = &xfer->ux_dmabuf; 3636 uint64_t parameter; 3637 uint32_t status; 3638 uint32_t control; 3639 u_int i = 0; 3640 3641 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3642 3643 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3644 3645 if (sc->sc_dying) 3646 return USBD_IOERROR; 3647 3648 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3649 3650 parameter = DMAADDR(dma, 0); 3651 KASSERT(len <= 0x10000); 3652 status = XHCI_TRB_2_IRQ_SET(0) | 3653 XHCI_TRB_2_TDSZ_SET(1) | 3654 XHCI_TRB_2_BYTES_SET(len); 3655 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3656 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3657 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3658 3659 mutex_enter(&tr->xr_lock); 3660 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3661 mutex_exit(&tr->xr_lock); 3662 3663 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3664 3665 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3666 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3667 xhci_timeout, xfer); 3668 } 3669 3670 return USBD_IN_PROGRESS; 3671 } 3672 3673 static void 3674 xhci_device_intr_done(struct usbd_xfer *xfer) 3675 { 3676 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3677 #ifdef USB_DEBUG 3678 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3679 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3680 #endif 3681 const int isread = usbd_xfer_isread(xfer); 3682 3683 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3684 3685 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3686 3687 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3688 3689 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3690 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3691 } 3692 3693 static void 3694 xhci_device_intr_abort(struct usbd_xfer *xfer) 3695 { 3696 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3697 3698 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3699 3700 KASSERT(mutex_owned(&sc->sc_lock)); 3701 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3702 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3703 xhci_abort_xfer(xfer, USBD_CANCELLED); 3704 } 3705 3706 static void 3707 xhci_device_intr_close(struct usbd_pipe *pipe) 3708 { 3709 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3710 3711 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3712 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3713 3714 xhci_close_pipe(pipe); 3715 } 3716 3717 /* ------------ */ 3718 3719 static void 3720 xhci_timeout(void *addr) 3721 { 3722 struct xhci_xfer * const xx = addr; 3723 struct usbd_xfer * const xfer = &xx->xx_xfer; 3724 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3725 3726 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3727 3728 if (sc->sc_dying) { 3729 return; 3730 } 3731 3732 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 3733 USB_TASKQ_MPSAFE); 3734 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 3735 USB_TASKQ_HC); 3736 } 3737 3738 static void 3739 xhci_timeout_task(void *addr) 3740 { 3741 struct usbd_xfer * const xfer = addr; 3742 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3743 3744 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3745 3746 mutex_enter(&sc->sc_lock); 3747 #if 0 3748 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3749 #else 3750 xfer->ux_status = USBD_TIMEOUT; 3751 usb_transfer_complete(xfer); 3752 #endif 3753 mutex_exit(&sc->sc_lock); 3754 } 3755
Indexes created Tue Sep 23 14:10:03 GMT 2025