xhci.c revision 1.54
1 /* $NetBSD: xhci.c,v 1.54 2016/06/05 08:25:05 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.54 2016/06/05 08:25:05 skrll Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 146 147 static usbd_status xhci_do_command(struct xhci_softc * const, 148 struct xhci_trb * const, int); 149 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 150 struct xhci_trb * const, int); 151 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 152 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 153 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 154 static usbd_status xhci_enable_slot(struct xhci_softc * const, 155 uint8_t * const); 156 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 157 static usbd_status xhci_address_device(struct xhci_softc * const, 158 uint64_t, uint8_t, bool); 159 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 160 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 161 struct xhci_slot * const, u_int); 162 static usbd_status xhci_ring_init(struct xhci_softc * const, 163 struct xhci_ring * const, size_t, size_t); 164 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 165 166 static void xhci_setup_ctx(struct usbd_pipe *); 167 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 168 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 169 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 170 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 171 172 static void xhci_noop(struct usbd_pipe *); 173 174 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 175 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 176 static void xhci_root_intr_abort(struct usbd_xfer *); 177 static void xhci_root_intr_close(struct usbd_pipe *); 178 static void xhci_root_intr_done(struct usbd_xfer *); 179 180 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 181 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 182 static void xhci_device_ctrl_abort(struct usbd_xfer *); 183 static void xhci_device_ctrl_close(struct usbd_pipe *); 184 static void xhci_device_ctrl_done(struct usbd_xfer *); 185 186 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 187 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 188 static void xhci_device_intr_abort(struct usbd_xfer *); 189 static void xhci_device_intr_close(struct usbd_pipe *); 190 static void xhci_device_intr_done(struct usbd_xfer *); 191 192 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 193 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 194 static void xhci_device_bulk_abort(struct usbd_xfer *); 195 static void xhci_device_bulk_close(struct usbd_pipe *); 196 static void xhci_device_bulk_done(struct usbd_xfer *); 197 198 static void xhci_timeout(void *); 199 static void xhci_timeout_task(void *); 200 201 static const struct usbd_bus_methods xhci_bus_methods = { 202 .ubm_open = xhci_open, 203 .ubm_softint = xhci_softintr, 204 .ubm_dopoll = xhci_poll, 205 .ubm_allocx = xhci_allocx, 206 .ubm_freex = xhci_freex, 207 .ubm_getlock = xhci_get_lock, 208 .ubm_newdev = xhci_new_device, 209 .ubm_rhctrl = xhci_roothub_ctrl, 210 }; 211 212 static const struct usbd_pipe_methods xhci_root_intr_methods = { 213 .upm_transfer = xhci_root_intr_transfer, 214 .upm_start = xhci_root_intr_start, 215 .upm_abort = xhci_root_intr_abort, 216 .upm_close = xhci_root_intr_close, 217 .upm_cleartoggle = xhci_noop, 218 .upm_done = xhci_root_intr_done, 219 }; 220 221 222 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 223 .upm_transfer = xhci_device_ctrl_transfer, 224 .upm_start = xhci_device_ctrl_start, 225 .upm_abort = xhci_device_ctrl_abort, 226 .upm_close = xhci_device_ctrl_close, 227 .upm_cleartoggle = xhci_noop, 228 .upm_done = xhci_device_ctrl_done, 229 }; 230 231 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 232 .upm_cleartoggle = xhci_noop, 233 }; 234 235 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 236 .upm_transfer = xhci_device_bulk_transfer, 237 .upm_start = xhci_device_bulk_start, 238 .upm_abort = xhci_device_bulk_abort, 239 .upm_close = xhci_device_bulk_close, 240 .upm_cleartoggle = xhci_noop, 241 .upm_done = xhci_device_bulk_done, 242 }; 243 244 static const struct usbd_pipe_methods xhci_device_intr_methods = { 245 .upm_transfer = xhci_device_intr_transfer, 246 .upm_start = xhci_device_intr_start, 247 .upm_abort = xhci_device_intr_abort, 248 .upm_close = xhci_device_intr_close, 249 .upm_cleartoggle = xhci_noop, 250 .upm_done = xhci_device_intr_done, 251 }; 252 253 static inline uint32_t 254 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 255 { 256 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 257 } 258 259 static inline uint32_t 260 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 261 { 262 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 263 } 264 265 static inline void 266 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 267 uint32_t value) 268 { 269 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 270 } 271 272 #if 0 /* unused */ 273 static inline void 274 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 275 uint32_t value) 276 { 277 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 278 } 279 #endif /* unused */ 280 281 static inline uint32_t 282 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 283 { 284 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 285 } 286 287 static inline uint32_t 288 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 289 { 290 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 291 } 292 293 static inline void 294 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 295 uint32_t value) 296 { 297 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 298 } 299 300 static inline uint64_t 301 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 302 { 303 uint64_t value; 304 305 if (sc->sc_ac64) { 306 #ifdef XHCI_USE_BUS_SPACE_8 307 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 308 #else 309 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 310 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 311 offset + 4) << 32; 312 #endif 313 } else { 314 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 315 } 316 317 return value; 318 } 319 320 static inline void 321 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 322 uint64_t value) 323 { 324 if (sc->sc_ac64) { 325 #ifdef XHCI_USE_BUS_SPACE_8 326 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 327 #else 328 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 329 (value >> 0) & 0xffffffff); 330 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 331 (value >> 32) & 0xffffffff); 332 #endif 333 } else { 334 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 335 } 336 } 337 338 static inline uint32_t 339 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 340 { 341 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 342 } 343 344 static inline void 345 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 346 uint32_t value) 347 { 348 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 349 } 350 351 #if 0 /* unused */ 352 static inline uint64_t 353 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 354 { 355 uint64_t value; 356 357 if (sc->sc_ac64) { 358 #ifdef XHCI_USE_BUS_SPACE_8 359 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 360 #else 361 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 362 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 363 offset + 4) << 32; 364 #endif 365 } else { 366 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 367 } 368 369 return value; 370 } 371 #endif /* unused */ 372 373 static inline void 374 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 375 uint64_t value) 376 { 377 if (sc->sc_ac64) { 378 #ifdef XHCI_USE_BUS_SPACE_8 379 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 380 #else 381 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 382 (value >> 0) & 0xffffffff); 383 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 384 (value >> 32) & 0xffffffff); 385 #endif 386 } else { 387 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 388 } 389 } 390 391 #if 0 /* unused */ 392 static inline uint32_t 393 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 394 { 395 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 396 } 397 #endif /* unused */ 398 399 static inline void 400 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 401 uint32_t value) 402 { 403 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 404 } 405 406 /* --- */ 407 408 static inline uint8_t 409 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 410 { 411 u_int eptype = 0; 412 413 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 414 case UE_CONTROL: 415 eptype = 0x0; 416 break; 417 case UE_ISOCHRONOUS: 418 eptype = 0x1; 419 break; 420 case UE_BULK: 421 eptype = 0x2; 422 break; 423 case UE_INTERRUPT: 424 eptype = 0x3; 425 break; 426 } 427 428 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 429 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 430 return eptype | 0x4; 431 else 432 return eptype; 433 } 434 435 static u_int 436 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 437 { 438 /* xHCI 1.0 section 4.5.1 */ 439 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 440 u_int in = 0; 441 442 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 443 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 444 in = 1; 445 446 return epaddr * 2 + in; 447 } 448 449 static inline u_int 450 xhci_dci_to_ici(const u_int i) 451 { 452 return i + 1; 453 } 454 455 static inline void * 456 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 457 const u_int dci) 458 { 459 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 460 } 461 462 #if 0 /* unused */ 463 static inline bus_addr_t 464 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 465 const u_int dci) 466 { 467 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 468 } 469 #endif /* unused */ 470 471 static inline void * 472 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 473 const u_int ici) 474 { 475 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 476 } 477 478 static inline bus_addr_t 479 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 480 const u_int ici) 481 { 482 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 483 } 484 485 static inline struct xhci_trb * 486 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 487 { 488 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 489 } 490 491 static inline bus_addr_t 492 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 493 { 494 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 495 } 496 497 static inline void 498 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 499 uint32_t control) 500 { 501 trb->trb_0 = htole64(parameter); 502 trb->trb_2 = htole32(status); 503 trb->trb_3 = htole32(control); 504 } 505 506 static int 507 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 508 { 509 /* base address of TRBs */ 510 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 511 512 /* trb_0 range sanity check */ 513 if (trb_0 == 0 || trb_0 < trbp || 514 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 515 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 516 return 1; 517 } 518 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 519 return 0; 520 } 521 522 /* --- */ 523 524 void 525 xhci_childdet(device_t self, device_t child) 526 { 527 struct xhci_softc * const sc = device_private(self); 528 529 KASSERT(sc->sc_child == child); 530 if (child == sc->sc_child) 531 sc->sc_child = NULL; 532 } 533 534 int 535 xhci_detach(struct xhci_softc *sc, int flags) 536 { 537 int rv = 0; 538 539 if (sc->sc_child != NULL) 540 rv = config_detach(sc->sc_child, flags); 541 542 if (rv != 0) 543 return rv; 544 545 /* XXX unconfigure/free slots */ 546 547 /* verify: */ 548 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 549 xhci_op_write_4(sc, XHCI_USBCMD, 0); 550 /* do we need to wait for stop? */ 551 552 xhci_op_write_8(sc, XHCI_CRCR, 0); 553 xhci_ring_free(sc, &sc->sc_cr); 554 cv_destroy(&sc->sc_command_cv); 555 556 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 557 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 558 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 559 xhci_ring_free(sc, &sc->sc_er); 560 561 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 562 563 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 564 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 565 566 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 567 568 mutex_destroy(&sc->sc_lock); 569 mutex_destroy(&sc->sc_intr_lock); 570 571 pool_cache_destroy(sc->sc_xferpool); 572 573 return rv; 574 } 575 576 int 577 xhci_activate(device_t self, enum devact act) 578 { 579 struct xhci_softc * const sc = device_private(self); 580 581 switch (act) { 582 case DVACT_DEACTIVATE: 583 sc->sc_dying = true; 584 return 0; 585 default: 586 return EOPNOTSUPP; 587 } 588 } 589 590 bool 591 xhci_suspend(device_t dv, const pmf_qual_t *qual) 592 { 593 return false; 594 } 595 596 bool 597 xhci_resume(device_t dv, const pmf_qual_t *qual) 598 { 599 return false; 600 } 601 602 bool 603 xhci_shutdown(device_t self, int flags) 604 { 605 return false; 606 } 607 608 static int 609 xhci_hc_reset(struct xhci_softc * const sc) 610 { 611 uint32_t usbcmd, usbsts; 612 int i; 613 614 /* Check controller not ready */ 615 for (i = 0; i < XHCI_WAIT_CNR; i++) { 616 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 617 if ((usbsts & XHCI_STS_CNR) == 0) 618 break; 619 usb_delay_ms(&sc->sc_bus, 1); 620 } 621 if (i >= XHCI_WAIT_CNR) { 622 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 623 return EIO; 624 } 625 626 /* Halt controller */ 627 usbcmd = 0; 628 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 629 usb_delay_ms(&sc->sc_bus, 1); 630 631 /* Reset controller */ 632 usbcmd = XHCI_CMD_HCRST; 633 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 634 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 635 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 636 if ((usbcmd & XHCI_CMD_HCRST) == 0) 637 break; 638 usb_delay_ms(&sc->sc_bus, 1); 639 } 640 if (i >= XHCI_WAIT_HCRST) { 641 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 642 return EIO; 643 } 644 645 /* Check controller not ready */ 646 for (i = 0; i < XHCI_WAIT_CNR; i++) { 647 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 648 if ((usbsts & XHCI_STS_CNR) == 0) 649 break; 650 usb_delay_ms(&sc->sc_bus, 1); 651 } 652 if (i >= XHCI_WAIT_CNR) { 653 aprint_error_dev(sc->sc_dev, 654 "controller not ready timeout after reset\n"); 655 return EIO; 656 } 657 658 return 0; 659 } 660 661 662 static void 663 hexdump(const char *msg, const void *base, size_t len) 664 { 665 #if 0 666 size_t cnt; 667 const uint32_t *p; 668 extern paddr_t vtophys(vaddr_t); 669 670 p = base; 671 cnt = 0; 672 673 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 674 (void *)vtophys((vaddr_t)base)); 675 676 while (cnt < len) { 677 if (cnt % 16 == 0) 678 printf("%p: ", p); 679 else if (cnt % 8 == 0) 680 printf(" |"); 681 printf(" %08x", *p++); 682 cnt += 4; 683 if (cnt % 16 == 0) 684 printf("\n"); 685 } 686 if (cnt % 16 != 0) 687 printf("\n"); 688 #endif 689 } 690 691 /* Process extended capabilities */ 692 static void 693 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 694 { 695 uint32_t ecp, ecr; 696 697 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 698 699 ecp = XHCI_HCC_XECP(hcc) * 4; 700 while (ecp != 0) { 701 ecr = xhci_read_4(sc, ecp); 702 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 703 switch (XHCI_XECP_ID(ecr)) { 704 case XHCI_ID_PROTOCOLS: { 705 uint32_t w4, w8, wc; 706 uint16_t w2; 707 w2 = (ecr >> 16) & 0xffff; 708 w4 = xhci_read_4(sc, ecp + 4); 709 w8 = xhci_read_4(sc, ecp + 8); 710 wc = xhci_read_4(sc, ecp + 0xc); 711 aprint_debug_dev(sc->sc_dev, 712 " SP: %08x %08x %08x %08x\n", ecr, w4, w8, wc); 713 /* unused */ 714 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0300) { 715 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 716 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 717 } 718 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0200) { 719 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 720 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 721 } 722 break; 723 } 724 case XHCI_ID_USB_LEGACY: { 725 uint8_t bios_sem; 726 727 /* Take host controller ownership from BIOS */ 728 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 729 if (bios_sem) { 730 /* sets xHCI to be owned by OS */ 731 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 732 aprint_debug_dev(sc->sc_dev, 733 "waiting for BIOS to give up control\n"); 734 for (int i = 0; i < 5000; i++) { 735 bios_sem = xhci_read_1(sc, ecp + 736 XHCI_XECP_BIOS_SEM); 737 if (bios_sem == 0) 738 break; 739 DELAY(1000); 740 } 741 if (bios_sem) { 742 aprint_error_dev(sc->sc_dev, 743 "timed out waiting for BIOS\n"); 744 } 745 } 746 break; 747 } 748 default: 749 break; 750 } 751 ecr = xhci_read_4(sc, ecp); 752 if (XHCI_XECP_NEXT(ecr) == 0) { 753 ecp = 0; 754 } else { 755 ecp += XHCI_XECP_NEXT(ecr) * 4; 756 } 757 } 758 } 759 760 #define XHCI_HCCPREV1_BITS \ 761 "\177\020" /* New bitmask */ \ 762 "f\020\020XECP\0" \ 763 "f\014\4MAXPSA\0" \ 764 "b\013CFC\0" \ 765 "b\012SEC\0" \ 766 "b\011SBD\0" \ 767 "b\010FSE\0" \ 768 "b\7NSS\0" \ 769 "b\6LTC\0" \ 770 "b\5LHRC\0" \ 771 "b\4PIND\0" \ 772 "b\3PPC\0" \ 773 "b\2CZC\0" \ 774 "b\1BNC\0" \ 775 "b\0AC64\0" \ 776 "\0" 777 #define XHCI_HCCV1_x_BITS \ 778 "\177\020" /* New bitmask */ \ 779 "f\020\020XECP\0" \ 780 "f\014\4MAXPSA\0" \ 781 "b\013CFC\0" \ 782 "b\012SEC\0" \ 783 "b\011SPC\0" \ 784 "b\010PAE\0" \ 785 "b\7NSS\0" \ 786 "b\6LTC\0" \ 787 "b\5LHRC\0" \ 788 "b\4PIND\0" \ 789 "b\3PPC\0" \ 790 "b\2CSZ\0" \ 791 "b\1BNC\0" \ 792 "b\0AC64\0" \ 793 "\0" 794 795 int 796 xhci_init(struct xhci_softc *sc) 797 { 798 bus_size_t bsz; 799 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 800 uint32_t pagesize, config; 801 int i = 0; 802 uint16_t hciversion; 803 uint8_t caplength; 804 805 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 806 807 sc->sc_bus.ub_revision = USBREV_3_0; 808 sc->sc_bus.ub_usedma = true; 809 810 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 811 caplength = XHCI_CAP_CAPLENGTH(cap); 812 hciversion = XHCI_CAP_HCIVERSION(cap); 813 814 if (hciversion < XHCI_HCIVERSION_0_96 || 815 hciversion > XHCI_HCIVERSION_1_0) { 816 aprint_normal_dev(sc->sc_dev, 817 "xHCI version %x.%x not known to be supported\n", 818 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 819 } else { 820 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 821 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 822 } 823 824 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 825 &sc->sc_cbh) != 0) { 826 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 827 return ENOMEM; 828 } 829 830 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 831 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 832 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 833 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 834 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 835 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 836 aprint_debug_dev(sc->sc_dev, 837 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 838 839 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 840 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 841 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 842 843 char sbuf[128]; 844 if (hciversion < XHCI_HCIVERSION_1_0) 845 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 846 else 847 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 848 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 849 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 850 851 /* print PSI and take ownership from BIOS */ 852 xhci_ecp(sc, hcc); 853 854 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 855 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 856 &sc->sc_obh) != 0) { 857 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 858 return ENOMEM; 859 } 860 861 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 862 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 863 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 864 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 865 return ENOMEM; 866 } 867 868 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 869 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 870 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 871 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 872 return ENOMEM; 873 } 874 875 int rv; 876 rv = xhci_hc_reset(sc); 877 if (rv != 0) { 878 return rv; 879 } 880 881 if (sc->sc_vendor_init) 882 sc->sc_vendor_init(sc); 883 884 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 885 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 886 pagesize = ffs(pagesize); 887 if (pagesize == 0) { 888 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 889 return EIO; 890 } 891 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 892 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 893 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 894 (uint32_t)sc->sc_maxslots); 895 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 896 897 usbd_status err; 898 899 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 900 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 901 if (sc->sc_maxspbuf != 0) { 902 err = usb_allocmem(&sc->sc_bus, 903 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 904 &sc->sc_spbufarray_dma); 905 if (err) { 906 aprint_error_dev(sc->sc_dev, 907 "spbufarray init fail, err %d\n", err); 908 return ENOMEM; 909 } 910 911 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 912 sc->sc_maxspbuf, KM_SLEEP); 913 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 914 for (i = 0; i < sc->sc_maxspbuf; i++) { 915 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 916 /* allocate contexts */ 917 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 918 sc->sc_pgsz, dma); 919 if (err) { 920 aprint_error_dev(sc->sc_dev, 921 "spbufarray_dma init fail, err %d\n", err); 922 rv = ENOMEM; 923 goto bad1; 924 } 925 spbufarray[i] = htole64(DMAADDR(dma, 0)); 926 usb_syncmem(dma, 0, sc->sc_pgsz, 927 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 928 } 929 930 usb_syncmem(&sc->sc_spbufarray_dma, 0, 931 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 932 } 933 934 config = xhci_op_read_4(sc, XHCI_CONFIG); 935 config &= ~0xFF; 936 config |= sc->sc_maxslots & 0xFF; 937 xhci_op_write_4(sc, XHCI_CONFIG, config); 938 939 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 940 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 941 if (err) { 942 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 943 err); 944 rv = ENOMEM; 945 goto bad1; 946 } 947 948 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 949 XHCI_EVENT_RING_SEGMENTS_ALIGN); 950 if (err) { 951 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 952 err); 953 rv = ENOMEM; 954 goto bad2; 955 } 956 957 usb_dma_t *dma; 958 size_t size; 959 size_t align; 960 961 dma = &sc->sc_eventst_dma; 962 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 963 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 964 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 965 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 966 err = usb_allocmem(&sc->sc_bus, size, align, dma); 967 if (err) { 968 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 969 err); 970 rv = ENOMEM; 971 goto bad3; 972 } 973 974 memset(KERNADDR(dma, 0), 0, size); 975 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 976 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 977 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 978 KERNADDR(&sc->sc_eventst_dma, 0), 979 sc->sc_eventst_dma.udma_block->size); 980 981 dma = &sc->sc_dcbaa_dma; 982 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 983 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 984 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 985 err = usb_allocmem(&sc->sc_bus, size, align, dma); 986 if (err) { 987 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 988 rv = ENOMEM; 989 goto bad4; 990 } 991 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 992 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 993 KERNADDR(&sc->sc_dcbaa_dma, 0), 994 sc->sc_dcbaa_dma.udma_block->size); 995 996 memset(KERNADDR(dma, 0), 0, size); 997 if (sc->sc_maxspbuf != 0) { 998 /* 999 * DCBA entry 0 hold the scratchbuf array pointer. 1000 */ 1001 *(uint64_t *)KERNADDR(dma, 0) = 1002 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1003 } 1004 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1005 1006 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1007 KM_SLEEP); 1008 if (sc->sc_slots == NULL) { 1009 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1010 rv = ENOMEM; 1011 goto bad; 1012 } 1013 1014 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1015 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1016 if (sc->sc_xferpool == NULL) { 1017 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1018 err); 1019 rv = ENOMEM; 1020 goto bad; 1021 } 1022 1023 cv_init(&sc->sc_command_cv, "xhcicmd"); 1024 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1025 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1026 1027 /* Set up the bus struct. */ 1028 sc->sc_bus.ub_methods = &xhci_bus_methods; 1029 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 1030 1031 struct xhci_erste *erst; 1032 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1033 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1034 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1035 erst[0].erste_3 = htole32(0); 1036 usb_syncmem(&sc->sc_eventst_dma, 0, 1037 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1038 1039 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1040 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1041 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1042 XHCI_ERDP_LO_BUSY); 1043 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1044 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1045 sc->sc_cr.xr_cs); 1046 1047 #if 0 1048 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1049 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1050 #endif 1051 1052 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1053 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1054 /* Intel xhci needs interrupt rate moderated. */ 1055 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1056 else 1057 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1058 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 1059 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1060 1061 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 1062 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1063 xhci_op_read_4(sc, XHCI_USBCMD)); 1064 1065 return 0; 1066 1067 bad: 1068 if (sc->sc_xferpool) { 1069 pool_cache_destroy(sc->sc_xferpool); 1070 sc->sc_xferpool = NULL; 1071 } 1072 1073 if (sc->sc_slots) { 1074 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1075 sc->sc_maxslots); 1076 sc->sc_slots = NULL; 1077 } 1078 1079 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1080 bad4: 1081 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1082 bad3: 1083 xhci_ring_free(sc, &sc->sc_er); 1084 bad2: 1085 xhci_ring_free(sc, &sc->sc_cr); 1086 i = sc->sc_maxspbuf; 1087 bad1: 1088 for (int j = 0; j < i; j++) 1089 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1090 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1091 1092 return rv; 1093 } 1094 1095 int 1096 xhci_intr(void *v) 1097 { 1098 struct xhci_softc * const sc = v; 1099 int ret = 0; 1100 1101 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1102 1103 if (sc == NULL) 1104 return 0; 1105 1106 mutex_spin_enter(&sc->sc_intr_lock); 1107 1108 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1109 goto done; 1110 1111 /* If we get an interrupt while polling, then just ignore it. */ 1112 if (sc->sc_bus.ub_usepolling) { 1113 #ifdef DIAGNOSTIC 1114 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1115 #endif 1116 goto done; 1117 } 1118 1119 ret = xhci_intr1(sc); 1120 done: 1121 mutex_spin_exit(&sc->sc_intr_lock); 1122 return ret; 1123 } 1124 1125 int 1126 xhci_intr1(struct xhci_softc * const sc) 1127 { 1128 uint32_t usbsts; 1129 uint32_t iman; 1130 1131 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1132 1133 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1134 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1135 #if 0 1136 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1137 return 0; 1138 } 1139 #endif 1140 xhci_op_write_4(sc, XHCI_USBSTS, 1141 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1142 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1143 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1144 1145 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1146 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1147 iman |= XHCI_IMAN_INTR_PEND; 1148 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1149 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1150 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1151 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1152 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1153 1154 usb_schedsoftintr(&sc->sc_bus); 1155 1156 return 1; 1157 } 1158 1159 /* 1160 * 3 port speed types used in USB stack 1161 * 1162 * usbdi speed 1163 * definition: USB_SPEED_* in usb.h 1164 * They are used in struct usbd_device in USB stack. 1165 * ioctl interface uses these values too. 1166 * port_status speed 1167 * definition: UPS_*_SPEED in usb.h 1168 * They are used in usb_port_status_t and valid only for USB 2.0. 1169 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1170 * of usb_port_status_ext_t indicates port speed. 1171 * Note that some 3.0 values overlap with 2.0 values. 1172 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1173 * means UPS_LOW_SPEED in HS.) 1174 * port status returned from hub also uses these values. 1175 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1176 * or more. 1177 * xspeed: 1178 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1179 * They are used in only slot context and PORTSC reg of xhci. 1180 * The difference between usbdi speed and xspeed is 1181 * that FS and LS values are swapped. 1182 */ 1183 1184 /* convert usbdi speed to xspeed */ 1185 static int 1186 xhci_speed2xspeed(int speed) 1187 { 1188 switch (speed) { 1189 case USB_SPEED_LOW: return 2; 1190 case USB_SPEED_FULL: return 1; 1191 default: return speed; 1192 } 1193 } 1194 1195 #if 0 1196 /* convert xspeed to usbdi speed */ 1197 static int 1198 xhci_xspeed2speed(int xspeed) 1199 { 1200 switch (xspeed) { 1201 case 1: return USB_SPEED_FULL; 1202 case 2: return USB_SPEED_LOW; 1203 default: return xspeed; 1204 } 1205 } 1206 #endif 1207 1208 /* convert xspeed to port status speed */ 1209 static int 1210 xhci_xspeed2psspeed(int xspeed) 1211 { 1212 switch (xspeed) { 1213 case 0: return 0; 1214 case 1: return UPS_FULL_SPEED; 1215 case 2: return UPS_LOW_SPEED; 1216 case 3: return UPS_HIGH_SPEED; 1217 default: return UPS_OTHER_SPEED; 1218 } 1219 } 1220 1221 /* 1222 * Construct input contexts and issue TRB to open pipe. 1223 */ 1224 static usbd_status 1225 xhci_configure_endpoint(struct usbd_pipe *pipe) 1226 { 1227 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1228 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1229 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1230 struct xhci_trb trb; 1231 usbd_status err; 1232 1233 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1234 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1235 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1236 pipe->up_endpoint->ue_edesc->bmAttributes); 1237 1238 KASSERT(!mutex_owned(&sc->sc_lock)); 1239 1240 /* XXX ensure input context is available? */ 1241 1242 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1243 1244 /* set up context */ 1245 xhci_setup_ctx(pipe); 1246 1247 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1248 sc->sc_ctxsz * 1); 1249 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1250 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1251 1252 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1253 trb.trb_2 = 0; 1254 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1255 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1256 1257 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1258 1259 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1260 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1261 sc->sc_ctxsz * 1); 1262 1263 return err; 1264 } 1265 1266 #if 0 1267 static usbd_status 1268 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1269 { 1270 #ifdef USB_DEBUG 1271 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1272 #endif 1273 1274 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1275 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1276 1277 return USBD_NORMAL_COMPLETION; 1278 } 1279 #endif 1280 1281 /* 4.6.8, 6.4.3.7 */ 1282 static usbd_status 1283 xhci_reset_endpoint(struct usbd_pipe *pipe) 1284 { 1285 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1286 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1287 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1288 struct xhci_trb trb; 1289 usbd_status err; 1290 1291 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1292 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1293 1294 KASSERT(!mutex_owned(&sc->sc_lock)); 1295 1296 trb.trb_0 = 0; 1297 trb.trb_2 = 0; 1298 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1299 XHCI_TRB_3_EP_SET(dci) | 1300 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1301 1302 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1303 1304 return err; 1305 } 1306 1307 /* 1308 * 4.6.9, 6.4.3.8 1309 * Stop execution of TDs on xfer ring. 1310 * Should be called with sc_lock held. 1311 */ 1312 static usbd_status 1313 xhci_stop_endpoint(struct usbd_pipe *pipe) 1314 { 1315 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1316 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1317 struct xhci_trb trb; 1318 usbd_status err; 1319 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1320 1321 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1322 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1323 1324 KASSERT(mutex_owned(&sc->sc_lock)); 1325 1326 trb.trb_0 = 0; 1327 trb.trb_2 = 0; 1328 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1329 XHCI_TRB_3_EP_SET(dci) | 1330 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1331 1332 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1333 1334 return err; 1335 } 1336 1337 /* 1338 * Set TR Dequeue Pointer. 1339 * xHCI 1.1 4.6.10 6.4.3.9 1340 * Purge all of the TRBs on ring and reinitialize ring. 1341 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1342 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1343 * error will be generated. 1344 */ 1345 static usbd_status 1346 xhci_set_dequeue(struct usbd_pipe *pipe) 1347 { 1348 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1349 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1350 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1351 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1352 struct xhci_trb trb; 1353 usbd_status err; 1354 1355 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1356 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1357 1358 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1359 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1360 BUS_DMASYNC_PREWRITE); 1361 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1362 1363 xr->xr_ep = 0; 1364 xr->xr_cs = 1; 1365 1366 /* set DCS */ 1367 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1368 trb.trb_2 = 0; 1369 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1370 XHCI_TRB_3_EP_SET(dci) | 1371 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1372 1373 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1374 1375 return err; 1376 } 1377 1378 /* 1379 * Open new pipe: called from usbd_setup_pipe_flags. 1380 * Fills methods of pipe. 1381 * If pipe is not for ep0, calls configure_endpoint. 1382 */ 1383 static usbd_status 1384 xhci_open(struct usbd_pipe *pipe) 1385 { 1386 struct usbd_device * const dev = pipe->up_dev; 1387 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1388 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1389 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1390 1391 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1392 DPRINTFN(1, "addr %d depth %d port %d speed %d", dev->ud_addr, 1393 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1394 DPRINTFN(1, " dci %u type 0x%02x epaddr 0x%02x attr 0x%02x", 1395 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1396 ed->bmAttributes); 1397 DPRINTFN(1, " mps %u ival %u", UGETW(ed->wMaxPacketSize), ed->bInterval, 1398 0, 0); 1399 1400 if (sc->sc_dying) 1401 return USBD_IOERROR; 1402 1403 /* Root Hub */ 1404 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1405 switch (ed->bEndpointAddress) { 1406 case USB_CONTROL_ENDPOINT: 1407 pipe->up_methods = &roothub_ctrl_methods; 1408 break; 1409 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1410 pipe->up_methods = &xhci_root_intr_methods; 1411 break; 1412 default: 1413 pipe->up_methods = NULL; 1414 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1415 ed->bEndpointAddress, 0, 0, 0); 1416 return USBD_INVAL; 1417 } 1418 return USBD_NORMAL_COMPLETION; 1419 } 1420 1421 switch (xfertype) { 1422 case UE_CONTROL: 1423 pipe->up_methods = &xhci_device_ctrl_methods; 1424 break; 1425 case UE_ISOCHRONOUS: 1426 pipe->up_methods = &xhci_device_isoc_methods; 1427 return USBD_INVAL; 1428 break; 1429 case UE_BULK: 1430 pipe->up_methods = &xhci_device_bulk_methods; 1431 break; 1432 case UE_INTERRUPT: 1433 pipe->up_methods = &xhci_device_intr_methods; 1434 break; 1435 default: 1436 return USBD_IOERROR; 1437 break; 1438 } 1439 1440 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1441 return xhci_configure_endpoint(pipe); 1442 1443 return USBD_NORMAL_COMPLETION; 1444 } 1445 1446 /* 1447 * Closes pipe, called from usbd_kill_pipe via close methods. 1448 * If the endpoint to be closed is ep0, disable_slot. 1449 * Should be called with sc_lock held. 1450 */ 1451 static void 1452 xhci_close_pipe(struct usbd_pipe *pipe) 1453 { 1454 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1455 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1456 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1457 const u_int dci = xhci_ep_get_dci(ed); 1458 struct xhci_trb trb; 1459 uint32_t *cp; 1460 1461 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1462 1463 if (sc->sc_dying) 1464 return; 1465 1466 /* xs is uninitialized before xhci_init_slot */ 1467 if (xs == NULL || xs->xs_idx == 0) 1468 return; 1469 1470 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1471 1472 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1473 KASSERT(mutex_owned(&sc->sc_lock)); 1474 1475 if (pipe->up_dev->ud_depth == 0) 1476 return; 1477 1478 if (dci == XHCI_DCI_EP_CONTROL) { 1479 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1480 xhci_disable_slot(sc, xs->xs_idx); 1481 return; 1482 } 1483 1484 /* 1485 * This may fail in the case that xhci_close_pipe is called after 1486 * xhci_abort_xfer e.g. usbd_kill_pipe. 1487 */ 1488 (void)xhci_stop_endpoint(pipe); 1489 1490 /* 1491 * set appropriate bit to be dropped. 1492 * don't set DC bit to 1, otherwise all endpoints 1493 * would be deconfigured. 1494 */ 1495 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1496 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1497 cp[1] = htole32(0); 1498 1499 /* XXX should be most significant one, not dci? */ 1500 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1501 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1502 1503 /* sync input contexts before they are read from memory */ 1504 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1505 1506 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1507 trb.trb_2 = 0; 1508 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1509 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1510 1511 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1512 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1513 } 1514 1515 /* 1516 * Abort transfer. 1517 * May be called from softintr context. 1518 */ 1519 static void 1520 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1521 { 1522 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1523 1524 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1525 DPRINTFN(4, "xfer %p pipe %p status %d", 1526 xfer, xfer->ux_pipe, status, 0); 1527 1528 KASSERT(mutex_owned(&sc->sc_lock)); 1529 1530 if (sc->sc_dying) { 1531 /* If we're dying, just do the software part. */ 1532 DPRINTFN(4, "xfer %p dying %u", xfer, xfer->ux_status, 0, 0); 1533 xfer->ux_status = status; 1534 callout_stop(&xfer->ux_callout); 1535 usb_transfer_complete(xfer); 1536 return; 1537 } 1538 1539 /* XXX need more stuff */ 1540 xfer->ux_status = status; 1541 callout_stop(&xfer->ux_callout); 1542 usb_transfer_complete(xfer); 1543 DPRINTFN(14, "end", 0, 0, 0, 0); 1544 1545 KASSERT(mutex_owned(&sc->sc_lock)); 1546 } 1547 1548 /* 1549 * Recover STALLed endpoint. 1550 * xHCI 1.1 sect 4.10.2.1 1551 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1552 * all transfers on transfer ring. 1553 * These are done in thread context asynchronously. 1554 */ 1555 static void 1556 xhci_clear_endpoint_stall_async_task(void *cookie) 1557 { 1558 struct usbd_xfer * const xfer = cookie; 1559 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1560 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1561 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1562 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1563 1564 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1565 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1566 1567 xhci_reset_endpoint(xfer->ux_pipe); 1568 xhci_set_dequeue(xfer->ux_pipe); 1569 1570 mutex_enter(&sc->sc_lock); 1571 tr->is_halted = false; 1572 usb_transfer_complete(xfer); 1573 mutex_exit(&sc->sc_lock); 1574 DPRINTFN(4, "ends", 0, 0, 0, 0); 1575 } 1576 1577 static usbd_status 1578 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1579 { 1580 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1581 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1582 1583 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1584 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1585 1586 if (sc->sc_dying) { 1587 return USBD_IOERROR; 1588 } 1589 1590 usb_init_task(&xp->xp_async_task, 1591 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1592 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1593 DPRINTFN(4, "ends", 0, 0, 0, 0); 1594 1595 return USBD_NORMAL_COMPLETION; 1596 } 1597 1598 /* Process roothub port status/change events and notify to uhub_intr. */ 1599 static void 1600 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1601 { 1602 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1603 uint8_t *p; 1604 1605 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1606 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1607 port, 0, 0); 1608 1609 if (xfer == NULL) 1610 return; 1611 1612 if (port > sc->sc_maxports) 1613 return; 1614 1615 p = xfer->ux_buf; 1616 memset(p, 0, xfer->ux_length); 1617 p[port/NBBY] |= 1 << (port%NBBY); 1618 xfer->ux_actlen = xfer->ux_length; 1619 xfer->ux_status = USBD_NORMAL_COMPLETION; 1620 usb_transfer_complete(xfer); 1621 } 1622 1623 /* Process Transfer Events */ 1624 static void 1625 xhci_event_transfer(struct xhci_softc * const sc, 1626 const struct xhci_trb * const trb) 1627 { 1628 uint64_t trb_0; 1629 uint32_t trb_2, trb_3; 1630 uint8_t trbcode; 1631 u_int slot, dci; 1632 struct xhci_slot *xs; 1633 struct xhci_ring *xr; 1634 struct xhci_xfer *xx; 1635 struct usbd_xfer *xfer; 1636 usbd_status err; 1637 1638 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1639 1640 trb_0 = le64toh(trb->trb_0); 1641 trb_2 = le32toh(trb->trb_2); 1642 trb_3 = le32toh(trb->trb_3); 1643 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1644 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1645 dci = XHCI_TRB_3_EP_GET(trb_3); 1646 xs = &sc->sc_slots[slot]; 1647 xr = &xs->xs_ep[dci].xe_tr; 1648 1649 /* sanity check */ 1650 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1651 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1652 1653 int idx = 0; 1654 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1655 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1656 DPRINTFN(0, "invalid trb_0 0x%"PRIx64, trb_0, 0, 0, 0); 1657 return; 1658 } 1659 xx = xr->xr_cookies[idx]; 1660 1661 /* 1662 * If endpoint is stopped between TDs, TRB pointer points at 1663 * next TRB, however, it is not put yet or is a garbage TRB. 1664 * That's why xr_cookies may be NULL or look like broken. 1665 * Note: this ev happens only when hciversion >= 1.0 or 1666 * hciversion == 0.96 and FSE of hcc1 is set. 1667 */ 1668 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1669 DPRINTFN(1, "Ignore #%u: cookie %p cc %u dci %u", 1670 idx, xx, trbcode, dci); 1671 DPRINTFN(1, " orig TRB %"PRIx64" type %u", trb_0, 1672 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1673 0, 0); 1674 } 1675 } else { 1676 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1677 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1678 } 1679 /* XXX this may not happen */ 1680 if (xx == NULL) { 1681 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1682 return; 1683 } 1684 xfer = &xx->xx_xfer; 1685 /* XXX this may happen when detaching */ 1686 if (xfer == NULL) { 1687 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1688 xx, trb_0, 0, 0); 1689 return; 1690 } 1691 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1692 /* XXX I dunno why this happens */ 1693 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1694 1695 if (!xfer->ux_pipe->up_repeat && 1696 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1697 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1698 return; 1699 } 1700 1701 /* 4.11.5.2 Event Data TRB */ 1702 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1703 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1704 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1705 if ((trb_0 & 0x3) == 0x3) { 1706 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1707 } 1708 } 1709 1710 switch (trbcode) { 1711 case XHCI_TRB_ERROR_SHORT_PKT: 1712 case XHCI_TRB_ERROR_SUCCESS: 1713 /* 1714 * A ctrl transfer generates two events if it has a Data stage. 1715 * After a successful Data stage we cannot call call 1716 * usb_transfer_complete - this can only happen after the Data 1717 * stage. 1718 * 1719 * Note: Data and Status stage events point at same xfer. 1720 * ux_actlen and ux_dmabuf will be passed to 1721 * usb_transfer_complete after the Status stage event. 1722 * 1723 * It can be distingished which stage generates the event: 1724 * + by checking least 3 bits of trb_0 if ED==1. 1725 * (see xhci_device_ctrl_start). 1726 * + by checking the type of original TRB if ED==0. 1727 * 1728 * In addition, intr, bulk, and isoc transfer currently 1729 * consists of single TD, so the "skip" is not needed. 1730 * ctrl xfer uses EVENT_DATA, and others do not. 1731 * Thus driver can switch the flow by checking ED bit. 1732 */ 1733 xfer->ux_actlen = 1734 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1735 err = USBD_NORMAL_COMPLETION; 1736 break; 1737 case XHCI_TRB_ERROR_STALL: 1738 case XHCI_TRB_ERROR_BABBLE: 1739 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1740 xr->is_halted = true; 1741 err = USBD_STALLED; 1742 /* 1743 * Stalled endpoints can be recoverd by issuing 1744 * command TRB TYPE_RESET_EP on xHCI instead of 1745 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1746 * on the endpoint. However, this function may be 1747 * called from softint context (e.g. from umass), 1748 * in that case driver gets KASSERT in cv_timedwait 1749 * in xhci_do_command. 1750 * To avoid this, this runs reset_endpoint and 1751 * usb_transfer_complete in usb task thread 1752 * asynchronously (and then umass issues clear 1753 * UF_ENDPOINT_HALT). 1754 */ 1755 xfer->ux_status = err; 1756 xhci_clear_endpoint_stall_async(xfer); 1757 return; 1758 default: 1759 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1760 err = USBD_IOERROR; 1761 break; 1762 } 1763 xfer->ux_status = err; 1764 1765 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1766 if ((trb_0 & 0x3) == 0x0) { 1767 callout_stop(&xfer->ux_callout); 1768 usb_transfer_complete(xfer); 1769 } 1770 } else { 1771 callout_stop(&xfer->ux_callout); 1772 usb_transfer_complete(xfer); 1773 } 1774 } 1775 1776 /* Process Command complete events */ 1777 static void 1778 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 1779 { 1780 uint64_t trb_0; 1781 uint32_t trb_2, trb_3; 1782 1783 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1784 1785 trb_0 = le64toh(trb->trb_0); 1786 trb_2 = le32toh(trb->trb_2); 1787 trb_3 = le32toh(trb->trb_3); 1788 1789 if (trb_0 == sc->sc_command_addr) { 1790 sc->sc_result_trb.trb_0 = trb_0; 1791 sc->sc_result_trb.trb_2 = trb_2; 1792 sc->sc_result_trb.trb_3 = trb_3; 1793 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1794 XHCI_TRB_ERROR_SUCCESS) { 1795 DPRINTFN(1, "command completion " 1796 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1797 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1798 } 1799 cv_signal(&sc->sc_command_cv); 1800 } else { 1801 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 1802 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1803 trb_2, trb_3); 1804 } 1805 } 1806 1807 /* 1808 * Process events. 1809 * called from xhci_softintr 1810 */ 1811 static void 1812 xhci_handle_event(struct xhci_softc * const sc, 1813 const struct xhci_trb * const trb) 1814 { 1815 uint64_t trb_0; 1816 uint32_t trb_2, trb_3; 1817 1818 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1819 1820 trb_0 = le64toh(trb->trb_0); 1821 trb_2 = le32toh(trb->trb_2); 1822 trb_3 = le32toh(trb->trb_3); 1823 1824 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1825 trb, trb_0, trb_2, trb_3); 1826 1827 /* 1828 * 4.11.3.1, 6.4.2.1 1829 * TRB Pointer is invalid for these completion codes. 1830 */ 1831 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 1832 case XHCI_TRB_ERROR_RING_UNDERRUN: 1833 case XHCI_TRB_ERROR_RING_OVERRUN: 1834 case XHCI_TRB_ERROR_VF_RING_FULL: 1835 return; 1836 default: 1837 if (trb_0 == 0) { 1838 return; 1839 } 1840 break; 1841 } 1842 1843 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 1844 case XHCI_TRB_EVENT_TRANSFER: 1845 xhci_event_transfer(sc, trb); 1846 break; 1847 case XHCI_TRB_EVENT_CMD_COMPLETE: 1848 xhci_event_cmd(sc, trb); 1849 break; 1850 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1851 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1852 break; 1853 default: 1854 break; 1855 } 1856 } 1857 1858 static void 1859 xhci_softintr(void *v) 1860 { 1861 struct usbd_bus * const bus = v; 1862 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1863 struct xhci_ring * const er = &sc->sc_er; 1864 struct xhci_trb *trb; 1865 int i, j, k; 1866 1867 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1868 1869 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1870 1871 i = er->xr_ep; 1872 j = er->xr_cs; 1873 1874 DPRINTFN(16, "er: xr_ep %d xr_cs %d", i, j, 0, 0); 1875 1876 while (1) { 1877 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 1878 BUS_DMASYNC_POSTREAD); 1879 trb = &er->xr_trb[i]; 1880 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1881 1882 if (j != k) 1883 break; 1884 1885 xhci_handle_event(sc, trb); 1886 1887 i++; 1888 if (i == er->xr_ntrb) { 1889 i = 0; 1890 j ^= 1; 1891 } 1892 } 1893 1894 er->xr_ep = i; 1895 er->xr_cs = j; 1896 1897 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 1898 XHCI_ERDP_LO_BUSY); 1899 1900 DPRINTFN(16, "ends", 0, 0, 0, 0); 1901 1902 return; 1903 } 1904 1905 static void 1906 xhci_poll(struct usbd_bus *bus) 1907 { 1908 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1909 1910 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1911 1912 mutex_spin_enter(&sc->sc_intr_lock); 1913 xhci_intr1(sc); 1914 mutex_spin_exit(&sc->sc_intr_lock); 1915 1916 return; 1917 } 1918 1919 static struct usbd_xfer * 1920 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 1921 { 1922 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1923 struct usbd_xfer *xfer; 1924 1925 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1926 1927 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1928 if (xfer != NULL) { 1929 memset(xfer, 0, sizeof(struct xhci_xfer)); 1930 #ifdef DIAGNOSTIC 1931 xfer->ux_state = XFER_BUSY; 1932 #endif 1933 } 1934 1935 return xfer; 1936 } 1937 1938 static void 1939 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1940 { 1941 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1942 1943 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1944 1945 #ifdef DIAGNOSTIC 1946 if (xfer->ux_state != XFER_BUSY) { 1947 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 1948 xfer, xfer->ux_state, 0, 0); 1949 } 1950 xfer->ux_state = XFER_FREE; 1951 #endif 1952 pool_cache_put(sc->sc_xferpool, xfer); 1953 } 1954 1955 static void 1956 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1957 { 1958 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1959 1960 *lock = &sc->sc_lock; 1961 } 1962 1963 extern uint32_t usb_cookie_no; 1964 1965 /* 1966 * xHCI 4.3 1967 * Called when uhub_explore finds a new device (via usbd_new_device). 1968 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 1969 * This function does: 1970 * Allocate and construct dev structure of default endpoint (ep0). 1971 * Allocate and open pipe of ep0. 1972 * Enable slot and initialize slot context. 1973 * Set Address. 1974 * Read initial device descriptor. 1975 * Determine initial MaxPacketSize (mps) by speed. 1976 * Read full device descriptor. 1977 * Register this device. 1978 * Finally state of device transitions ADDRESSED. 1979 */ 1980 static usbd_status 1981 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 1982 int speed, int port, struct usbd_port *up) 1983 { 1984 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1985 struct usbd_device *dev; 1986 usbd_status err; 1987 usb_device_descriptor_t *dd; 1988 struct xhci_slot *xs; 1989 uint32_t *cp; 1990 1991 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1992 DPRINTFN(4, "port %u depth %u speed %u up %p", port, depth, speed, up); 1993 1994 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 1995 if (dev == NULL) 1996 return USBD_NOMEM; 1997 1998 dev->ud_bus = bus; 1999 dev->ud_quirks = &usbd_no_quirk; 2000 dev->ud_addr = 0; 2001 dev->ud_ddesc.bMaxPacketSize = 0; 2002 dev->ud_depth = depth; 2003 dev->ud_powersrc = up; 2004 dev->ud_myhub = up->up_parent; 2005 dev->ud_speed = speed; 2006 dev->ud_langid = USBD_NOLANG; 2007 dev->ud_cookie.cookie = ++usb_cookie_no; 2008 2009 /* Set up default endpoint handle. */ 2010 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2011 /* doesn't matter, just don't let it uninitialized */ 2012 dev->ud_ep0.ue_toggle = 0; 2013 2014 /* Set up default endpoint descriptor. */ 2015 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2016 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2017 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2018 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2019 dev->ud_ep0desc.bInterval = 0; 2020 2021 /* 4.3, 4.8.2.1 */ 2022 switch (speed) { 2023 case USB_SPEED_SUPER: 2024 case USB_SPEED_SUPER_PLUS: 2025 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2026 break; 2027 case USB_SPEED_FULL: 2028 /* XXX using 64 as initial mps of ep0 in FS */ 2029 case USB_SPEED_HIGH: 2030 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2031 break; 2032 case USB_SPEED_LOW: 2033 default: 2034 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2035 break; 2036 } 2037 2038 up->up_dev = dev; 2039 2040 /* Establish the default pipe. */ 2041 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2042 &dev->ud_pipe0); 2043 if (err) { 2044 goto bad; 2045 } 2046 2047 dd = &dev->ud_ddesc; 2048 2049 if ((depth == 0) && (port == 0)) { 2050 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2051 bus->ub_devices[dev->ud_addr] = dev; 2052 err = usbd_get_initial_ddesc(dev, dd); 2053 if (err) 2054 goto bad; 2055 err = usbd_reload_device_desc(dev); 2056 if (err) 2057 goto bad; 2058 } else { 2059 uint8_t slot = 0; 2060 2061 /* 4.3.2 */ 2062 err = xhci_enable_slot(sc, &slot); 2063 if (err) 2064 goto bad; 2065 2066 xs = &sc->sc_slots[slot]; 2067 dev->ud_hcpriv = xs; 2068 2069 /* 4.3.3 initialize slot structure */ 2070 err = xhci_init_slot(dev, slot); 2071 if (err) { 2072 dev->ud_hcpriv = NULL; 2073 /* 2074 * We have to disable_slot here because 2075 * xs->xs_idx == 0 when xhci_init_slot fails, 2076 * in that case usbd_remove_dev won't work. 2077 */ 2078 mutex_enter(&sc->sc_lock); 2079 xhci_disable_slot(sc, slot); 2080 mutex_exit(&sc->sc_lock); 2081 goto bad; 2082 } 2083 2084 /* 4.3.4 Address Assignment */ 2085 err = xhci_set_address(dev, slot, false); 2086 if (err) 2087 goto bad; 2088 2089 /* Allow device time to set new address */ 2090 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2091 2092 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2093 //hexdump("slot context", cp, sc->sc_ctxsz); 2094 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2095 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2096 /* XXX ensure we know when the hardware does something 2097 we can't yet cope with */ 2098 KASSERT(addr >= 1 && addr <= 127); 2099 dev->ud_addr = addr; 2100 /* XXX dev->ud_addr not necessarily unique on bus */ 2101 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2102 bus->ub_devices[dev->ud_addr] = dev; 2103 2104 err = usbd_get_initial_ddesc(dev, dd); 2105 if (err) 2106 goto bad; 2107 2108 /* 4.8.2.1 */ 2109 if (USB_IS_SS(speed)) { 2110 if (dd->bMaxPacketSize != 9) { 2111 printf("%s: invalid mps 2^%u for SS ep0," 2112 " using 512\n", 2113 device_xname(sc->sc_dev), 2114 dd->bMaxPacketSize); 2115 dd->bMaxPacketSize = 9; 2116 } 2117 USETW(dev->ud_ep0desc.wMaxPacketSize, 2118 (1 << dd->bMaxPacketSize)); 2119 } else 2120 USETW(dev->ud_ep0desc.wMaxPacketSize, 2121 dd->bMaxPacketSize); 2122 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2123 xhci_update_ep0_mps(sc, xs, 2124 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2125 2126 err = usbd_reload_device_desc(dev); 2127 if (err) 2128 goto bad; 2129 } 2130 2131 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2132 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2133 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2134 dd->bDeviceClass, dd->bDeviceSubClass, 2135 dd->bDeviceProtocol, 0); 2136 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2137 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2138 dev->ud_speed); 2139 2140 usbd_get_device_strings(dev); 2141 2142 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2143 2144 if ((depth == 0) && (port == 0)) { 2145 usbd_attach_roothub(parent, dev); 2146 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2147 return USBD_NORMAL_COMPLETION; 2148 } 2149 2150 2151 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2152 bad: 2153 if (err != USBD_NORMAL_COMPLETION) { 2154 usbd_remove_device(dev, up); 2155 } 2156 2157 return err; 2158 } 2159 2160 static usbd_status 2161 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2162 size_t ntrb, size_t align) 2163 { 2164 usbd_status err; 2165 size_t size = ntrb * XHCI_TRB_SIZE; 2166 2167 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2168 2169 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2170 if (err) 2171 return err; 2172 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2173 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2174 xr->xr_trb = xhci_ring_trbv(xr, 0); 2175 xr->xr_ntrb = ntrb; 2176 xr->xr_ep = 0; 2177 xr->xr_cs = 1; 2178 memset(xr->xr_trb, 0, size); 2179 usb_syncmem(&xr->xr_dma, 0, size, BUS_DMASYNC_PREWRITE); 2180 xr->is_halted = false; 2181 2182 return USBD_NORMAL_COMPLETION; 2183 } 2184 2185 static void 2186 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2187 { 2188 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2189 mutex_destroy(&xr->xr_lock); 2190 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2191 } 2192 2193 static void 2194 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2195 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2196 { 2197 size_t i; 2198 u_int ri; 2199 u_int cs; 2200 uint64_t parameter; 2201 uint32_t status; 2202 uint32_t control; 2203 2204 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2205 2206 KASSERT(ntrbs <= XHCI_XFER_NTRB); 2207 for (i = 0; i < ntrbs; i++) { 2208 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2209 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2210 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2211 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2212 XHCI_TRB_TYPE_LINK); 2213 } 2214 2215 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2216 2217 ri = xr->xr_ep; 2218 cs = xr->xr_cs; 2219 2220 /* 2221 * Although the xhci hardware can do scatter/gather dma from 2222 * arbitrary sized buffers, there is a non-obvious restriction 2223 * that a LINK trb is only allowed at the end of a burst of 2224 * transfers - which might be 16kB. 2225 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2226 * The simple solution is not to allow a LINK trb in the middle 2227 * of anything - as here. 2228 * XXX: (dsl) There are xhci controllers out there (eg some made by 2229 * ASMedia) that seem to lock up if they process a LINK trb but 2230 * cannot process the linked-to trb yet. 2231 * The code should write the 'cycle' bit on the link trb AFTER 2232 * adding the other trb. 2233 */ 2234 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2235 parameter = xhci_ring_trbp(xr, 0); 2236 status = 0; 2237 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2238 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2239 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2240 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2241 BUS_DMASYNC_PREWRITE); 2242 xr->xr_cookies[ri] = NULL; 2243 xr->xr_ep = 0; 2244 xr->xr_cs ^= 1; 2245 ri = xr->xr_ep; 2246 cs = xr->xr_cs; 2247 } 2248 2249 ri++; 2250 2251 /* Write any subsequent TRB first */ 2252 for (i = 1; i < ntrbs; i++) { 2253 parameter = trbs[i].trb_0; 2254 status = trbs[i].trb_2; 2255 control = trbs[i].trb_3; 2256 2257 if (cs) { 2258 control |= XHCI_TRB_3_CYCLE_BIT; 2259 } else { 2260 control &= ~XHCI_TRB_3_CYCLE_BIT; 2261 } 2262 2263 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2264 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2265 BUS_DMASYNC_PREWRITE); 2266 xr->xr_cookies[ri] = cookie; 2267 ri++; 2268 } 2269 2270 /* Write the first TRB last */ 2271 i = 0; 2272 parameter = trbs[i].trb_0; 2273 status = trbs[i].trb_2; 2274 control = trbs[i].trb_3; 2275 2276 if (xr->xr_cs) { 2277 control |= XHCI_TRB_3_CYCLE_BIT; 2278 } else { 2279 control &= ~XHCI_TRB_3_CYCLE_BIT; 2280 } 2281 2282 xhci_trb_put(&xr->xr_trb[xr->xr_ep], parameter, status, control); 2283 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * xr->xr_ep, XHCI_TRB_SIZE * 1, 2284 BUS_DMASYNC_PREWRITE); 2285 xr->xr_cookies[xr->xr_ep] = cookie; 2286 2287 xr->xr_ep = ri; 2288 xr->xr_cs = cs; 2289 2290 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2291 } 2292 2293 /* 2294 * Stop execution commands, purge all commands on command ring, and 2295 * rewind dequeue pointer. 2296 */ 2297 static void 2298 xhci_abort_command(struct xhci_softc *sc) 2299 { 2300 struct xhci_ring * const cr = &sc->sc_cr; 2301 uint64_t crcr; 2302 int i; 2303 2304 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2305 DPRINTFN(14, "command %#"PRIx64" timeout, aborting", 2306 sc->sc_command_addr, 0, 0, 0); 2307 2308 mutex_enter(&cr->xr_lock); 2309 2310 /* 4.6.1.2 Aborting a Command */ 2311 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2312 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2313 2314 for (i = 0; i < 500; i++) { 2315 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2316 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2317 break; 2318 usb_delay_ms(&sc->sc_bus, 1); 2319 } 2320 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2321 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2322 /* reset HC here? */ 2323 } 2324 2325 /* reset command ring dequeue pointer */ 2326 cr->xr_ep = 0; 2327 cr->xr_cs = 1; 2328 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2329 2330 mutex_exit(&cr->xr_lock); 2331 } 2332 2333 /* 2334 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2335 * Command completion is notified by cv_signal from xhci_event_cmd() 2336 * (called from xhci_softint), or timed-out. 2337 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2338 * then do_command examines it. 2339 */ 2340 static usbd_status 2341 xhci_do_command_locked(struct xhci_softc * const sc, 2342 struct xhci_trb * const trb, int timeout) 2343 { 2344 struct xhci_ring * const cr = &sc->sc_cr; 2345 usbd_status err; 2346 2347 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2348 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2349 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2350 2351 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2352 KASSERT(mutex_owned(&sc->sc_lock)); 2353 2354 /* XXX KASSERT may fire when cv_timedwait unlocks sc_lock */ 2355 KASSERT(sc->sc_command_addr == 0); 2356 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2357 2358 mutex_enter(&cr->xr_lock); 2359 xhci_ring_put(sc, cr, NULL, trb, 1); 2360 mutex_exit(&cr->xr_lock); 2361 2362 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2363 2364 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2365 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2366 xhci_abort_command(sc); 2367 err = USBD_TIMEOUT; 2368 goto timedout; 2369 } 2370 2371 trb->trb_0 = sc->sc_result_trb.trb_0; 2372 trb->trb_2 = sc->sc_result_trb.trb_2; 2373 trb->trb_3 = sc->sc_result_trb.trb_3; 2374 2375 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2376 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2377 2378 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2379 case XHCI_TRB_ERROR_SUCCESS: 2380 err = USBD_NORMAL_COMPLETION; 2381 break; 2382 default: 2383 case 192 ... 223: 2384 err = USBD_IOERROR; 2385 break; 2386 case 224 ... 255: 2387 err = USBD_NORMAL_COMPLETION; 2388 break; 2389 } 2390 2391 timedout: 2392 sc->sc_command_addr = 0; 2393 return err; 2394 } 2395 2396 static usbd_status 2397 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2398 int timeout) 2399 { 2400 2401 mutex_enter(&sc->sc_lock); 2402 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2403 mutex_exit(&sc->sc_lock); 2404 2405 return ret; 2406 } 2407 2408 static usbd_status 2409 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2410 { 2411 struct xhci_trb trb; 2412 usbd_status err; 2413 2414 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2415 2416 trb.trb_0 = 0; 2417 trb.trb_2 = 0; 2418 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2419 2420 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2421 if (err != USBD_NORMAL_COMPLETION) { 2422 return err; 2423 } 2424 2425 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2426 2427 return err; 2428 } 2429 2430 /* 2431 * xHCI 4.6.4 2432 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2433 * All endpoints in the slot should be stopped. 2434 * Should be called with sc_lock held. 2435 */ 2436 static usbd_status 2437 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2438 { 2439 struct xhci_trb trb; 2440 struct xhci_slot *xs; 2441 usbd_status err; 2442 2443 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2444 2445 if (sc->sc_dying) 2446 return USBD_IOERROR; 2447 2448 trb.trb_0 = 0; 2449 trb.trb_2 = 0; 2450 trb.trb_3 = htole32( 2451 XHCI_TRB_3_SLOT_SET(slot) | 2452 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2453 2454 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2455 2456 if (!err) { 2457 xs = &sc->sc_slots[slot]; 2458 if (xs->xs_idx != 0) { 2459 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2460 xhci_set_dcba(sc, 0, slot); 2461 memset(xs, 0, sizeof(*xs)); 2462 } 2463 } 2464 2465 return err; 2466 } 2467 2468 /* 2469 * Set address of device and transition slot state from ENABLED to ADDRESSED 2470 * if Block Setaddress Request (BSR) is false. 2471 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2472 * see xHCI 1.1 4.5.3, 3.3.4 2473 * Should be called without sc_lock held. 2474 */ 2475 static usbd_status 2476 xhci_address_device(struct xhci_softc * const sc, 2477 uint64_t icp, uint8_t slot_id, bool bsr) 2478 { 2479 struct xhci_trb trb; 2480 usbd_status err; 2481 2482 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2483 2484 trb.trb_0 = icp; 2485 trb.trb_2 = 0; 2486 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2487 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2488 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2489 2490 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2491 2492 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2493 err = USBD_NO_ADDR; 2494 2495 return err; 2496 } 2497 2498 static usbd_status 2499 xhci_update_ep0_mps(struct xhci_softc * const sc, 2500 struct xhci_slot * const xs, u_int mps) 2501 { 2502 struct xhci_trb trb; 2503 usbd_status err; 2504 uint32_t * cp; 2505 2506 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2507 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2508 2509 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2510 cp[0] = htole32(0); 2511 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2512 2513 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2514 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2515 2516 /* sync input contexts before they are read from memory */ 2517 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2518 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2519 sc->sc_ctxsz * 4); 2520 2521 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2522 trb.trb_2 = 0; 2523 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2524 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2525 2526 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2527 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2528 return err; 2529 } 2530 2531 static void 2532 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2533 { 2534 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2535 2536 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2537 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2538 &dcbaa[si], dcba, si, 0); 2539 2540 dcbaa[si] = htole64(dcba); 2541 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2542 BUS_DMASYNC_PREWRITE); 2543 } 2544 2545 /* 2546 * Allocate device and input context DMA buffer, and 2547 * TRB DMA buffer for each endpoint. 2548 */ 2549 static usbd_status 2550 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2551 { 2552 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2553 struct xhci_slot *xs; 2554 usbd_status err; 2555 u_int dci; 2556 2557 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2558 DPRINTFN(4, "slot %u", slot, 0, 0, 0); 2559 2560 xs = &sc->sc_slots[slot]; 2561 2562 /* allocate contexts */ 2563 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2564 &xs->xs_dc_dma); 2565 if (err) 2566 return err; 2567 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2568 2569 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2570 &xs->xs_ic_dma); 2571 if (err) 2572 goto bad1; 2573 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2574 2575 for (dci = 0; dci < 32; dci++) { 2576 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2577 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2578 if (dci == XHCI_DCI_SLOT) 2579 continue; 2580 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2581 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2582 if (err) { 2583 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2584 goto bad2; 2585 } 2586 } 2587 2588 bad2: 2589 if (err == USBD_NORMAL_COMPLETION) { 2590 xs->xs_idx = slot; 2591 } else { 2592 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2593 } 2594 2595 return err; 2596 2597 bad1: 2598 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2599 xs->xs_idx = 0; 2600 return err; 2601 } 2602 2603 static void 2604 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2605 int end_dci) 2606 { 2607 u_int dci; 2608 2609 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2610 DPRINTFN(4, "slot %u start %u end %u", xs->xs_idx, start_dci, end_dci, 2611 0); 2612 2613 for (dci = start_dci; dci < end_dci; dci++) { 2614 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2615 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2616 } 2617 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2618 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2619 xs->xs_idx = 0; 2620 } 2621 2622 /* 2623 * Setup slot context, set Device Context Base Address, and issue 2624 * Set Address Device command. 2625 */ 2626 static usbd_status 2627 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 2628 { 2629 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2630 struct xhci_slot *xs; 2631 usbd_status err; 2632 2633 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2634 DPRINTFN(4, "slot %u bsr %u", slot, bsr, 0, 0); 2635 2636 xs = &sc->sc_slots[slot]; 2637 2638 xhci_setup_ctx(dev->ud_pipe0); 2639 2640 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2641 sc->sc_ctxsz * 3); 2642 2643 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2644 2645 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 2646 2647 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2648 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2649 sc->sc_ctxsz * 2); 2650 2651 return err; 2652 } 2653 2654 /* 2655 * 4.8.2, 6.2.3.2 2656 * construct slot/endpoint context parameters and do syncmem 2657 */ 2658 static void 2659 xhci_setup_ctx(struct usbd_pipe *pipe) 2660 { 2661 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2662 struct usbd_device *dev = pipe->up_dev; 2663 struct xhci_slot * const xs = dev->ud_hcpriv; 2664 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2665 const u_int dci = xhci_ep_get_dci(ed); 2666 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2667 uint32_t *cp; 2668 uint16_t mps = UGETW(ed->wMaxPacketSize); 2669 uint8_t speed = dev->ud_speed; 2670 uint8_t ival = ed->bInterval; 2671 2672 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2673 DPRINTFN(4, "pipe %p: slot %u dci %u speed %u", pipe, xs->xs_idx, dci, 2674 speed); 2675 2676 /* set up initial input control context */ 2677 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2678 cp[0] = htole32(0); 2679 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 2680 if (dci == XHCI_DCI_EP_CONTROL) 2681 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2682 cp[7] = htole32(0); 2683 2684 /* set up input slot context */ 2685 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2686 cp[0] = 2687 XHCI_SCTX_0_CTX_NUM_SET(dci) | 2688 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 2689 cp[1] = 0; 2690 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2691 cp[3] = 0; 2692 xhci_setup_route(pipe, cp); 2693 xhci_setup_tthub(pipe, cp); 2694 2695 cp[0] = htole32(cp[0]); 2696 cp[1] = htole32(cp[1]); 2697 cp[2] = htole32(cp[2]); 2698 cp[3] = htole32(cp[3]); 2699 2700 /* set up input endpoint context */ 2701 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 2702 cp[0] = 2703 XHCI_EPCTX_0_EPSTATE_SET(0) | 2704 XHCI_EPCTX_0_MULT_SET(0) | 2705 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2706 XHCI_EPCTX_0_LSA_SET(0) | 2707 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 2708 cp[1] = 2709 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 2710 XHCI_EPCTX_1_HID_SET(0) | 2711 XHCI_EPCTX_1_MAXB_SET(0); 2712 2713 if (xfertype != UE_ISOCHRONOUS) 2714 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 2715 2716 if (xfertype == UE_CONTROL) 2717 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 2718 else if (USB_IS_SS(speed)) 2719 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 2720 else 2721 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 2722 2723 xhci_setup_maxburst(pipe, cp); 2724 2725 switch (xfertype) { 2726 case UE_CONTROL: 2727 break; 2728 case UE_BULK: 2729 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 2730 break; 2731 case UE_INTERRUPT: 2732 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 2733 ival = pipe->up_interval; 2734 2735 ival = xhci_bival2ival(ival, speed); 2736 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 2737 break; 2738 case UE_ISOCHRONOUS: 2739 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 2740 ival = pipe->up_interval; 2741 2742 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 2743 if (speed == USB_SPEED_FULL) 2744 ival += 3; /* 1ms -> 125us */ 2745 ival--; 2746 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 2747 break; 2748 default: 2749 break; 2750 } 2751 DPRINTFN(4, "setting ival %u MaxBurst %#x", 2752 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 2753 2754 /* can't use xhci_ep_get_dci() yet? */ 2755 *(uint64_t *)(&cp[2]) = htole64( 2756 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 2757 XHCI_EPCTX_2_DCS_SET(1)); 2758 2759 cp[0] = htole32(cp[0]); 2760 cp[1] = htole32(cp[1]); 2761 cp[4] = htole32(cp[4]); 2762 2763 /* sync input contexts before they are read from memory */ 2764 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2765 } 2766 2767 /* 2768 * Setup route string and roothub port of given device for slot context 2769 */ 2770 static void 2771 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 2772 { 2773 struct usbd_device *dev = pipe->up_dev; 2774 struct usbd_port *up = dev->ud_powersrc; 2775 struct usbd_device *hub; 2776 struct usbd_device *adev; 2777 uint8_t rhport = 0; 2778 uint32_t route = 0; 2779 2780 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2781 2782 /* Locate root hub port and Determine route string */ 2783 /* 4.3.3 route string does not include roothub port */ 2784 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2785 uint32_t dep; 2786 2787 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2788 hub, hub->ud_depth, hub->ud_powersrc, 2789 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2790 2791 if (hub->ud_powersrc == NULL) 2792 break; 2793 dep = hub->ud_depth; 2794 if (dep == 0) 2795 break; 2796 rhport = hub->ud_powersrc->up_portno; 2797 if (dep > USB_HUB_MAX_DEPTH) 2798 continue; 2799 2800 route |= 2801 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2802 << ((dep - 1) * 4); 2803 } 2804 route = route >> 4; 2805 DPRINTFN(4, "rhport %u Route %05x hub %p", rhport, route, hub, 0); 2806 2807 /* Locate port on upstream high speed hub */ 2808 for (adev = dev, hub = up->up_parent; 2809 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2810 adev = hub, hub = hub->ud_myhub) 2811 ; 2812 if (hub) { 2813 int p; 2814 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2815 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2816 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2817 goto found; 2818 } 2819 } 2820 panic("xhci_setup_route: cannot find HS port"); 2821 found: 2822 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2823 } else { 2824 dev->ud_myhsport = NULL; 2825 } 2826 2827 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 2828 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(rhport); 2829 } 2830 2831 /* 2832 * Setup whether device is hub, whether device uses MTT, and 2833 * TT informations if it uses MTT. 2834 */ 2835 static void 2836 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 2837 { 2838 struct usbd_device *dev = pipe->up_dev; 2839 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 2840 uint32_t speed = dev->ud_speed; 2841 uint8_t tthubslot, ttportnum; 2842 bool ishub; 2843 bool usemtt; 2844 2845 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2846 2847 /* 2848 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 2849 * tthubslot: 2850 * This is the slot ID of parent HS hub 2851 * if LS/FS device is connected && connected through HS hub. 2852 * This is 0 if device is not LS/FS device || 2853 * parent hub is not HS hub || 2854 * attached to root hub. 2855 * ttportnum: 2856 * This is the downstream facing port of parent HS hub 2857 * if LS/FS device is connected. 2858 * This is 0 if device is not LS/FS device || 2859 * parent hub is not HS hub || 2860 * attached to root hub. 2861 */ 2862 if (dev->ud_myhsport != NULL && 2863 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 2864 (dev->ud_myhub != NULL && 2865 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 2866 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 2867 ttportnum = dev->ud_myhsport->up_portno; 2868 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 2869 } else { 2870 ttportnum = 0; 2871 tthubslot = 0; 2872 } 2873 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 2874 dev->ud_myhsport, ttportnum, tthubslot, 0); 2875 2876 /* ishub is valid after reading UDESC_DEVICE */ 2877 ishub = (dd->bDeviceClass == UDCLASS_HUB); 2878 2879 /* dev->ud_hub is valid after reading UDESC_HUB */ 2880 if (ishub && dev->ud_hub) { 2881 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 2882 uint8_t ttt = 2883 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 2884 2885 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 2886 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 2887 DPRINTFN(4, "nports=%d ttt=%d", hd->bNbrPorts, ttt, 0, 0); 2888 } 2889 2890 #define IS_TTHUB(dd) \ 2891 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 2892 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 2893 2894 /* 2895 * MTT flag is set if 2896 * 1. this is HS hub && MTT is enabled 2897 * or 2898 * 2. this is not hub && this is LS or FS device && 2899 * MTT of parent HS hub (and its parent, too) is enabled 2900 */ 2901 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 2902 usemtt = true; 2903 else if (!ishub && 2904 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 2905 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 2906 (dev->ud_myhub != NULL && 2907 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 2908 dev->ud_myhsport != NULL && 2909 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 2910 usemtt = true; 2911 else 2912 usemtt = false; 2913 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 2914 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 2915 2916 #undef IS_TTHUB 2917 2918 cp[0] |= 2919 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 2920 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 2921 cp[2] |= 2922 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 2923 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 2924 } 2925 2926 /* set up params for periodic endpoint */ 2927 static void 2928 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 2929 { 2930 struct usbd_device *dev = pipe->up_dev; 2931 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2932 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2933 usbd_desc_iter_t iter; 2934 const usb_cdc_descriptor_t *cdcd; 2935 uint32_t maxb = 0; 2936 uint16_t mps = UGETW(ed->wMaxPacketSize); 2937 uint8_t speed = dev->ud_speed; 2938 uint8_t ep; 2939 2940 /* config desc is NULL when opening ep0 */ 2941 if (dev == NULL || dev->ud_cdesc == NULL) 2942 goto no_cdcd; 2943 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 2944 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 2945 if (cdcd == NULL) 2946 goto no_cdcd; 2947 usb_desc_iter_init(dev, &iter); 2948 iter.cur = (const void *)cdcd; 2949 2950 /* find endpoint_ss_comp desc for ep of this pipe */ 2951 for (ep = 0;;) { 2952 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 2953 if (cdcd == NULL) 2954 break; 2955 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 2956 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 2957 bEndpointAddress; 2958 if (UE_GET_ADDR(ep) == 2959 UE_GET_ADDR(ed->bEndpointAddress)) { 2960 cdcd = (const usb_cdc_descriptor_t *) 2961 usb_desc_iter_next(&iter); 2962 break; 2963 } 2964 ep = 0; 2965 } 2966 } 2967 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 2968 const usb_endpoint_ss_comp_descriptor_t * esscd = 2969 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 2970 maxb = esscd->bMaxBurst; 2971 } 2972 2973 no_cdcd: 2974 /* 6.2.3.4, 4.8.2.4 */ 2975 if (USB_IS_SS(speed)) { 2976 /* UBS 3.1 9.6.6 */ 2977 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 2978 /* UBS 3.1 9.6.7 */ 2979 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 2980 #ifdef notyet 2981 if (xfertype == UE_ISOCHRONOUS) { 2982 } 2983 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 2984 /* use ESIT */ 2985 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 2986 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 2987 2988 /* XXX if LEC = 1, set ESIT instead */ 2989 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 2990 } else { 2991 /* use ival */ 2992 } 2993 #endif 2994 } else { 2995 /* UBS 2.0 9.6.6 */ 2996 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 2997 2998 /* 6.2.3.4 */ 2999 if (speed == USB_SPEED_HIGH && 3000 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3001 maxb = UE_GET_TRANS(mps); 3002 } else { 3003 /* LS/FS or HS CTRL or HS BULK */ 3004 maxb = 0; 3005 } 3006 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3007 } 3008 } 3009 3010 /* 3011 * Convert endpoint bInterval value to endpoint context interval value 3012 * for Interrupt pipe. 3013 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3014 */ 3015 static uint32_t 3016 xhci_bival2ival(uint32_t ival, uint32_t speed) 3017 { 3018 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3019 int i; 3020 3021 /* 3022 * round ival down to "the nearest base 2 multiple of 3023 * bInterval * 8". 3024 * bInterval is at most 255 as its type is uByte. 3025 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3026 */ 3027 for (i = 10; i > 0; i--) { 3028 if ((ival * 8) >= (1 << i)) 3029 break; 3030 } 3031 ival = i; 3032 } else { 3033 /* Interval = bInterval-1 for SS/HS */ 3034 ival--; 3035 } 3036 3037 return ival; 3038 } 3039 3040 /* ----- */ 3041 3042 static void 3043 xhci_noop(struct usbd_pipe *pipe) 3044 { 3045 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3046 } 3047 3048 /* 3049 * Process root hub request. 3050 */ 3051 static int 3052 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3053 void *buf, int buflen) 3054 { 3055 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3056 usb_port_status_t ps; 3057 int l, totlen = 0; 3058 uint16_t len, value, index; 3059 int port, i; 3060 uint32_t v; 3061 3062 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3063 3064 if (sc->sc_dying) 3065 return -1; 3066 3067 len = UGETW(req->wLength); 3068 value = UGETW(req->wValue); 3069 index = UGETW(req->wIndex); 3070 3071 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 3072 req->bmRequestType | (req->bRequest << 8), value, index, len); 3073 3074 #define C(x,y) ((x) | ((y) << 8)) 3075 switch (C(req->bRequest, req->bmRequestType)) { 3076 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3077 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 3078 if (len == 0) 3079 break; 3080 switch (value) { 3081 case C(0, UDESC_DEVICE): { 3082 usb_device_descriptor_t devd; 3083 totlen = min(buflen, sizeof(devd)); 3084 memcpy(&devd, buf, totlen); 3085 USETW(devd.idVendor, sc->sc_id_vendor); 3086 memcpy(buf, &devd, totlen); 3087 break; 3088 } 3089 #define sd ((usb_string_descriptor_t *)buf) 3090 case C(1, UDESC_STRING): 3091 /* Vendor */ 3092 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3093 break; 3094 case C(2, UDESC_STRING): 3095 /* Product */ 3096 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3097 break; 3098 #undef sd 3099 default: 3100 /* default from usbroothub */ 3101 return buflen; 3102 } 3103 break; 3104 3105 /* Hub requests */ 3106 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3107 break; 3108 /* Clear Port Feature request */ 3109 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3110 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 3111 index, value, 0, 0); 3112 if (index < 1 || index > sc->sc_maxports) { 3113 return -1; 3114 } 3115 port = XHCI_PORTSC(index); 3116 v = xhci_op_read_4(sc, port); 3117 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3118 v &= ~XHCI_PS_CLEAR; 3119 switch (value) { 3120 case UHF_PORT_ENABLE: 3121 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3122 break; 3123 case UHF_PORT_SUSPEND: 3124 return -1; 3125 case UHF_PORT_POWER: 3126 break; 3127 case UHF_PORT_TEST: 3128 case UHF_PORT_INDICATOR: 3129 return -1; 3130 case UHF_C_PORT_CONNECTION: 3131 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3132 break; 3133 case UHF_C_PORT_ENABLE: 3134 case UHF_C_PORT_SUSPEND: 3135 case UHF_C_PORT_OVER_CURRENT: 3136 return -1; 3137 case UHF_C_BH_PORT_RESET: 3138 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3139 break; 3140 case UHF_C_PORT_RESET: 3141 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3142 break; 3143 case UHF_C_PORT_LINK_STATE: 3144 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3145 break; 3146 case UHF_C_PORT_CONFIG_ERROR: 3147 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3148 break; 3149 default: 3150 return -1; 3151 } 3152 break; 3153 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3154 if (len == 0) 3155 break; 3156 if ((value & 0xff) != 0) { 3157 return -1; 3158 } 3159 usb_hub_descriptor_t hubd; 3160 3161 totlen = min(buflen, sizeof(hubd)); 3162 memcpy(&hubd, buf, totlen); 3163 hubd.bNbrPorts = sc->sc_maxports; 3164 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3165 hubd.bPwrOn2PwrGood = 200; 3166 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 3167 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 3168 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3169 totlen = min(totlen, hubd.bDescLength); 3170 memcpy(buf, &hubd, totlen); 3171 break; 3172 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3173 if (len != 4) { 3174 return -1; 3175 } 3176 memset(buf, 0, len); /* ? XXX */ 3177 totlen = len; 3178 break; 3179 /* Get Port Status request */ 3180 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3181 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 3182 if (index < 1 || index > sc->sc_maxports) { 3183 return -1; 3184 } 3185 if (len != 4) { 3186 return -1; 3187 } 3188 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 3189 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 3190 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3191 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3192 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3193 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3194 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3195 if (v & XHCI_PS_PR) i |= UPS_RESET; 3196 if (v & XHCI_PS_PP) { 3197 if (i & UPS_OTHER_SPEED) 3198 i |= UPS_PORT_POWER_SS; 3199 else 3200 i |= UPS_PORT_POWER; 3201 } 3202 if (i & UPS_OTHER_SPEED) 3203 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3204 if (sc->sc_vendor_port_status) 3205 i = sc->sc_vendor_port_status(sc, v, i); 3206 USETW(ps.wPortStatus, i); 3207 i = 0; 3208 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3209 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3210 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3211 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3212 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3213 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3214 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3215 USETW(ps.wPortChange, i); 3216 totlen = min(len, sizeof(ps)); 3217 memcpy(buf, &ps, totlen); 3218 break; 3219 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3220 return -1; 3221 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3222 break; 3223 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3224 break; 3225 /* Set Port Feature request */ 3226 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3227 int optval = (index >> 8) & 0xff; 3228 index &= 0xff; 3229 if (index < 1 || index > sc->sc_maxports) { 3230 return -1; 3231 } 3232 port = XHCI_PORTSC(index); 3233 v = xhci_op_read_4(sc, port); 3234 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3235 v &= ~XHCI_PS_CLEAR; 3236 switch (value) { 3237 case UHF_PORT_ENABLE: 3238 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3239 break; 3240 case UHF_PORT_SUSPEND: 3241 /* XXX suspend */ 3242 break; 3243 case UHF_PORT_RESET: 3244 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3245 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3246 /* Wait for reset to complete. */ 3247 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3248 if (sc->sc_dying) { 3249 return -1; 3250 } 3251 v = xhci_op_read_4(sc, port); 3252 if (v & XHCI_PS_PR) { 3253 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3254 usb_delay_ms(&sc->sc_bus, 10); 3255 /* XXX */ 3256 } 3257 break; 3258 case UHF_PORT_POWER: 3259 /* XXX power control */ 3260 break; 3261 /* XXX more */ 3262 case UHF_C_PORT_RESET: 3263 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3264 break; 3265 case UHF_PORT_U1_TIMEOUT: 3266 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3267 return -1; 3268 } 3269 port = XHCI_PORTPMSC(index); 3270 v = xhci_op_read_4(sc, port); 3271 v &= ~XHCI_PM3_U1TO_SET(0xff); 3272 v |= XHCI_PM3_U1TO_SET(optval); 3273 xhci_op_write_4(sc, port, v); 3274 break; 3275 case UHF_PORT_U2_TIMEOUT: 3276 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3277 return -1; 3278 } 3279 port = XHCI_PORTPMSC(index); 3280 v = xhci_op_read_4(sc, port); 3281 v &= ~XHCI_PM3_U2TO_SET(0xff); 3282 v |= XHCI_PM3_U2TO_SET(optval); 3283 xhci_op_write_4(sc, port, v); 3284 break; 3285 default: 3286 return -1; 3287 } 3288 } 3289 break; 3290 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3291 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3292 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3293 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3294 break; 3295 default: 3296 /* default from usbroothub */ 3297 return buflen; 3298 } 3299 3300 return totlen; 3301 } 3302 3303 /* root hub interrupt */ 3304 3305 static usbd_status 3306 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3307 { 3308 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3309 usbd_status err; 3310 3311 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3312 3313 /* Insert last in queue. */ 3314 mutex_enter(&sc->sc_lock); 3315 err = usb_insert_transfer(xfer); 3316 mutex_exit(&sc->sc_lock); 3317 if (err) 3318 return err; 3319 3320 /* Pipe isn't running, start first */ 3321 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3322 } 3323 3324 /* Wait for roothub port status/change */ 3325 static usbd_status 3326 xhci_root_intr_start(struct usbd_xfer *xfer) 3327 { 3328 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3329 3330 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3331 3332 if (sc->sc_dying) 3333 return USBD_IOERROR; 3334 3335 mutex_enter(&sc->sc_lock); 3336 sc->sc_intrxfer = xfer; 3337 mutex_exit(&sc->sc_lock); 3338 3339 return USBD_IN_PROGRESS; 3340 } 3341 3342 static void 3343 xhci_root_intr_abort(struct usbd_xfer *xfer) 3344 { 3345 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3346 3347 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3348 3349 KASSERT(mutex_owned(&sc->sc_lock)); 3350 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3351 3352 sc->sc_intrxfer = NULL; 3353 3354 xfer->ux_status = USBD_CANCELLED; 3355 usb_transfer_complete(xfer); 3356 } 3357 3358 static void 3359 xhci_root_intr_close(struct usbd_pipe *pipe) 3360 { 3361 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3362 3363 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3364 3365 KASSERT(mutex_owned(&sc->sc_lock)); 3366 3367 sc->sc_intrxfer = NULL; 3368 } 3369 3370 static void 3371 xhci_root_intr_done(struct usbd_xfer *xfer) 3372 { 3373 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3374 3375 } 3376 3377 /* -------------- */ 3378 /* device control */ 3379 3380 static usbd_status 3381 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3382 { 3383 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3384 usbd_status err; 3385 3386 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3387 3388 /* Insert last in queue. */ 3389 mutex_enter(&sc->sc_lock); 3390 err = usb_insert_transfer(xfer); 3391 mutex_exit(&sc->sc_lock); 3392 if (err) 3393 return err; 3394 3395 /* Pipe isn't running, start first */ 3396 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3397 } 3398 3399 static usbd_status 3400 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3401 { 3402 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3403 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3404 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3405 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3406 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3407 usb_device_request_t * const req = &xfer->ux_request; 3408 const int isread = usbd_xfer_isread(xfer); 3409 const uint32_t len = UGETW(req->wLength); 3410 usb_dma_t * const dma = &xfer->ux_dmabuf; 3411 uint64_t parameter; 3412 uint32_t status; 3413 uint32_t control; 3414 u_int i; 3415 3416 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3417 DPRINTFN(12, "req: %04x %04x %04x %04x", 3418 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3419 UGETW(req->wIndex), UGETW(req->wLength)); 3420 3421 /* we rely on the bottom bits for extra info */ 3422 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 3423 3424 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3425 3426 i = 0; 3427 3428 /* setup phase */ 3429 memcpy(¶meter, req, sizeof(*req)); 3430 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3431 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3432 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3433 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3434 XHCI_TRB_3_IDT_BIT; 3435 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3436 3437 if (len != 0) { 3438 /* data phase */ 3439 parameter = DMAADDR(dma, 0); 3440 KASSERT(len <= 0x10000); 3441 status = XHCI_TRB_2_IRQ_SET(0) | 3442 XHCI_TRB_2_TDSZ_SET(1) | 3443 XHCI_TRB_2_BYTES_SET(len); 3444 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3445 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3446 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3447 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3448 3449 parameter = (uintptr_t)xfer | 0x3; 3450 status = XHCI_TRB_2_IRQ_SET(0); 3451 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3452 XHCI_TRB_3_IOC_BIT; 3453 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3454 } 3455 3456 parameter = 0; 3457 status = XHCI_TRB_2_IRQ_SET(0); 3458 /* the status stage has inverted direction */ 3459 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3460 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3461 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3462 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3463 3464 parameter = (uintptr_t)xfer | 0x0; 3465 status = XHCI_TRB_2_IRQ_SET(0); 3466 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3467 XHCI_TRB_3_IOC_BIT; 3468 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3469 3470 mutex_enter(&tr->xr_lock); 3471 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3472 mutex_exit(&tr->xr_lock); 3473 3474 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3475 3476 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3477 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3478 xhci_timeout, xfer); 3479 } 3480 3481 return USBD_IN_PROGRESS; 3482 } 3483 3484 static void 3485 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3486 { 3487 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3488 usb_device_request_t *req = &xfer->ux_request; 3489 int len = UGETW(req->wLength); 3490 int rd = req->bmRequestType & UT_READ; 3491 3492 if (len) 3493 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3494 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3495 } 3496 3497 static void 3498 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3499 { 3500 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3501 3502 xhci_abort_xfer(xfer, USBD_CANCELLED); 3503 } 3504 3505 static void 3506 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3507 { 3508 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3509 3510 xhci_close_pipe(pipe); 3511 } 3512 3513 /* ------------------ */ 3514 /* device isochronous */ 3515 3516 /* ----------- */ 3517 /* device bulk */ 3518 3519 static usbd_status 3520 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3521 { 3522 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3523 usbd_status err; 3524 3525 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3526 3527 /* Insert last in queue. */ 3528 mutex_enter(&sc->sc_lock); 3529 err = usb_insert_transfer(xfer); 3530 mutex_exit(&sc->sc_lock); 3531 if (err) 3532 return err; 3533 3534 /* 3535 * Pipe isn't running (otherwise err would be USBD_INPROG), 3536 * so start it first. 3537 */ 3538 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3539 } 3540 3541 static usbd_status 3542 xhci_device_bulk_start(struct usbd_xfer *xfer) 3543 { 3544 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3545 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3546 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3547 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3548 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3549 const uint32_t len = xfer->ux_length; 3550 usb_dma_t * const dma = &xfer->ux_dmabuf; 3551 uint64_t parameter; 3552 uint32_t status; 3553 uint32_t control; 3554 u_int i = 0; 3555 3556 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3557 3558 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3559 3560 if (sc->sc_dying) 3561 return USBD_IOERROR; 3562 3563 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3564 3565 parameter = DMAADDR(dma, 0); 3566 /* 3567 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3568 * If the user supplied buffer crosses such a boundary then 2 3569 * (or more) TRB should be used. 3570 * If multiple TRB are used the td_size field must be set correctly. 3571 * For v1.0 devices (like ivy bridge) this is the number of usb data 3572 * blocks needed to complete the transfer. 3573 * Setting it to 1 in the last TRB causes an extra zero-length 3574 * data block be sent. 3575 * The earlier documentation differs, I don't know how it behaves. 3576 */ 3577 KASSERT(len <= 0x10000); 3578 status = XHCI_TRB_2_IRQ_SET(0) | 3579 XHCI_TRB_2_TDSZ_SET(1) | 3580 XHCI_TRB_2_BYTES_SET(len); 3581 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3582 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3583 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3584 3585 mutex_enter(&tr->xr_lock); 3586 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3587 mutex_exit(&tr->xr_lock); 3588 3589 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3590 3591 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3592 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3593 xhci_timeout, xfer); 3594 } 3595 3596 return USBD_IN_PROGRESS; 3597 } 3598 3599 static void 3600 xhci_device_bulk_done(struct usbd_xfer *xfer) 3601 { 3602 #ifdef USB_DEBUG 3603 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3604 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3605 #endif 3606 const int isread = usbd_xfer_isread(xfer); 3607 3608 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3609 3610 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3611 3612 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3613 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3614 } 3615 3616 static void 3617 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3618 { 3619 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3620 3621 xhci_abort_xfer(xfer, USBD_CANCELLED); 3622 } 3623 3624 static void 3625 xhci_device_bulk_close(struct usbd_pipe *pipe) 3626 { 3627 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3628 3629 xhci_close_pipe(pipe); 3630 } 3631 3632 /* ---------------- */ 3633 /* device interrupt */ 3634 3635 static usbd_status 3636 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3637 { 3638 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3639 usbd_status err; 3640 3641 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3642 3643 /* Insert last in queue. */ 3644 mutex_enter(&sc->sc_lock); 3645 err = usb_insert_transfer(xfer); 3646 mutex_exit(&sc->sc_lock); 3647 if (err) 3648 return err; 3649 3650 /* 3651 * Pipe isn't running (otherwise err would be USBD_INPROG), 3652 * so start it first. 3653 */ 3654 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3655 } 3656 3657 static usbd_status 3658 xhci_device_intr_start(struct usbd_xfer *xfer) 3659 { 3660 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3661 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3662 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3663 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3664 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3665 const uint32_t len = xfer->ux_length; 3666 usb_dma_t * const dma = &xfer->ux_dmabuf; 3667 uint64_t parameter; 3668 uint32_t status; 3669 uint32_t control; 3670 u_int i = 0; 3671 3672 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3673 3674 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3675 3676 if (sc->sc_dying) 3677 return USBD_IOERROR; 3678 3679 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3680 3681 parameter = DMAADDR(dma, 0); 3682 KASSERT(len <= 0x10000); 3683 status = XHCI_TRB_2_IRQ_SET(0) | 3684 XHCI_TRB_2_TDSZ_SET(1) | 3685 XHCI_TRB_2_BYTES_SET(len); 3686 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3687 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3688 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3689 3690 mutex_enter(&tr->xr_lock); 3691 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3692 mutex_exit(&tr->xr_lock); 3693 3694 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3695 3696 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3697 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3698 xhci_timeout, xfer); 3699 } 3700 3701 return USBD_IN_PROGRESS; 3702 } 3703 3704 static void 3705 xhci_device_intr_done(struct usbd_xfer *xfer) 3706 { 3707 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3708 #ifdef USB_DEBUG 3709 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3710 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3711 #endif 3712 const int isread = usbd_xfer_isread(xfer); 3713 3714 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3715 3716 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3717 3718 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3719 3720 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3721 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3722 } 3723 3724 static void 3725 xhci_device_intr_abort(struct usbd_xfer *xfer) 3726 { 3727 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3728 3729 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3730 3731 KASSERT(mutex_owned(&sc->sc_lock)); 3732 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3733 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3734 xhci_abort_xfer(xfer, USBD_CANCELLED); 3735 } 3736 3737 static void 3738 xhci_device_intr_close(struct usbd_pipe *pipe) 3739 { 3740 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3741 3742 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3743 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3744 3745 xhci_close_pipe(pipe); 3746 } 3747 3748 /* ------------ */ 3749 3750 static void 3751 xhci_timeout(void *addr) 3752 { 3753 struct xhci_xfer * const xx = addr; 3754 struct usbd_xfer * const xfer = &xx->xx_xfer; 3755 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3756 3757 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3758 3759 if (sc->sc_dying) { 3760 return; 3761 } 3762 3763 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 3764 USB_TASKQ_MPSAFE); 3765 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 3766 USB_TASKQ_HC); 3767 } 3768 3769 static void 3770 xhci_timeout_task(void *addr) 3771 { 3772 struct usbd_xfer * const xfer = addr; 3773 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3774 3775 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3776 3777 mutex_enter(&sc->sc_lock); 3778 #if 0 3779 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3780 #else 3781 xfer->ux_status = USBD_TIMEOUT; 3782 usb_transfer_complete(xfer); 3783 #endif 3784 mutex_exit(&sc->sc_lock); 3785 } 3786
Indexes created Wed Sep 24 05:09:52 GMT 2025