xhci.c revision 1.55
1 /* $NetBSD: xhci.c,v 1.55 2016/06/05 09:16:02 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.55 2016/06/05 09:16:02 skrll Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static void xhci_host_dequeue(struct xhci_ring * const); 146 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 147 148 static usbd_status xhci_do_command(struct xhci_softc * const, 149 struct xhci_trb * const, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 153 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 154 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 155 static usbd_status xhci_enable_slot(struct xhci_softc * const, 156 uint8_t * const); 157 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 158 static usbd_status xhci_address_device(struct xhci_softc * const, 159 uint64_t, uint8_t, bool); 160 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 161 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 162 struct xhci_slot * const, u_int); 163 static usbd_status xhci_ring_init(struct xhci_softc * const, 164 struct xhci_ring * const, size_t, size_t); 165 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 166 167 static void xhci_setup_ctx(struct usbd_pipe *); 168 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 169 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 170 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 171 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 172 173 static void xhci_noop(struct usbd_pipe *); 174 175 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 176 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 177 static void xhci_root_intr_abort(struct usbd_xfer *); 178 static void xhci_root_intr_close(struct usbd_pipe *); 179 static void xhci_root_intr_done(struct usbd_xfer *); 180 181 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 182 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 183 static void xhci_device_ctrl_abort(struct usbd_xfer *); 184 static void xhci_device_ctrl_close(struct usbd_pipe *); 185 static void xhci_device_ctrl_done(struct usbd_xfer *); 186 187 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 188 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 189 static void xhci_device_intr_abort(struct usbd_xfer *); 190 static void xhci_device_intr_close(struct usbd_pipe *); 191 static void xhci_device_intr_done(struct usbd_xfer *); 192 193 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 194 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 195 static void xhci_device_bulk_abort(struct usbd_xfer *); 196 static void xhci_device_bulk_close(struct usbd_pipe *); 197 static void xhci_device_bulk_done(struct usbd_xfer *); 198 199 static void xhci_timeout(void *); 200 static void xhci_timeout_task(void *); 201 202 static const struct usbd_bus_methods xhci_bus_methods = { 203 .ubm_open = xhci_open, 204 .ubm_softint = xhci_softintr, 205 .ubm_dopoll = xhci_poll, 206 .ubm_allocx = xhci_allocx, 207 .ubm_freex = xhci_freex, 208 .ubm_getlock = xhci_get_lock, 209 .ubm_newdev = xhci_new_device, 210 .ubm_rhctrl = xhci_roothub_ctrl, 211 }; 212 213 static const struct usbd_pipe_methods xhci_root_intr_methods = { 214 .upm_transfer = xhci_root_intr_transfer, 215 .upm_start = xhci_root_intr_start, 216 .upm_abort = xhci_root_intr_abort, 217 .upm_close = xhci_root_intr_close, 218 .upm_cleartoggle = xhci_noop, 219 .upm_done = xhci_root_intr_done, 220 }; 221 222 223 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 224 .upm_transfer = xhci_device_ctrl_transfer, 225 .upm_start = xhci_device_ctrl_start, 226 .upm_abort = xhci_device_ctrl_abort, 227 .upm_close = xhci_device_ctrl_close, 228 .upm_cleartoggle = xhci_noop, 229 .upm_done = xhci_device_ctrl_done, 230 }; 231 232 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 233 .upm_cleartoggle = xhci_noop, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 237 .upm_transfer = xhci_device_bulk_transfer, 238 .upm_start = xhci_device_bulk_start, 239 .upm_abort = xhci_device_bulk_abort, 240 .upm_close = xhci_device_bulk_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_bulk_done, 243 }; 244 245 static const struct usbd_pipe_methods xhci_device_intr_methods = { 246 .upm_transfer = xhci_device_intr_transfer, 247 .upm_start = xhci_device_intr_start, 248 .upm_abort = xhci_device_intr_abort, 249 .upm_close = xhci_device_intr_close, 250 .upm_cleartoggle = xhci_noop, 251 .upm_done = xhci_device_intr_done, 252 }; 253 254 static inline uint32_t 255 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 256 { 257 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 258 } 259 260 static inline uint32_t 261 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 262 { 263 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 264 } 265 266 static inline void 267 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 268 uint32_t value) 269 { 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 271 } 272 273 #if 0 /* unused */ 274 static inline void 275 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 276 uint32_t value) 277 { 278 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 279 } 280 #endif /* unused */ 281 282 static inline uint32_t 283 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 284 { 285 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 286 } 287 288 static inline uint32_t 289 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 290 { 291 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 292 } 293 294 static inline void 295 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 296 uint32_t value) 297 { 298 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 299 } 300 301 static inline uint64_t 302 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 303 { 304 uint64_t value; 305 306 if (sc->sc_ac64) { 307 #ifdef XHCI_USE_BUS_SPACE_8 308 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 309 #else 310 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 311 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 312 offset + 4) << 32; 313 #endif 314 } else { 315 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 316 } 317 318 return value; 319 } 320 321 static inline void 322 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 336 } 337 } 338 339 static inline uint32_t 340 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 341 { 342 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 343 } 344 345 static inline void 346 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 347 uint32_t value) 348 { 349 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 350 } 351 352 #if 0 /* unused */ 353 static inline uint64_t 354 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 355 { 356 uint64_t value; 357 358 if (sc->sc_ac64) { 359 #ifdef XHCI_USE_BUS_SPACE_8 360 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 361 #else 362 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 363 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 364 offset + 4) << 32; 365 #endif 366 } else { 367 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 368 } 369 370 return value; 371 } 372 #endif /* unused */ 373 374 static inline void 375 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 376 uint64_t value) 377 { 378 if (sc->sc_ac64) { 379 #ifdef XHCI_USE_BUS_SPACE_8 380 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 381 #else 382 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 383 (value >> 0) & 0xffffffff); 384 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 385 (value >> 32) & 0xffffffff); 386 #endif 387 } else { 388 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 389 } 390 } 391 392 #if 0 /* unused */ 393 static inline uint32_t 394 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 395 { 396 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 397 } 398 #endif /* unused */ 399 400 static inline void 401 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 402 uint32_t value) 403 { 404 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 405 } 406 407 /* --- */ 408 409 static inline uint8_t 410 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 411 { 412 u_int eptype = 0; 413 414 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 415 case UE_CONTROL: 416 eptype = 0x0; 417 break; 418 case UE_ISOCHRONOUS: 419 eptype = 0x1; 420 break; 421 case UE_BULK: 422 eptype = 0x2; 423 break; 424 case UE_INTERRUPT: 425 eptype = 0x3; 426 break; 427 } 428 429 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 430 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 431 return eptype | 0x4; 432 else 433 return eptype; 434 } 435 436 static u_int 437 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 438 { 439 /* xHCI 1.0 section 4.5.1 */ 440 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 441 u_int in = 0; 442 443 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 444 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 445 in = 1; 446 447 return epaddr * 2 + in; 448 } 449 450 static inline u_int 451 xhci_dci_to_ici(const u_int i) 452 { 453 return i + 1; 454 } 455 456 static inline void * 457 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 458 const u_int dci) 459 { 460 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 461 } 462 463 #if 0 /* unused */ 464 static inline bus_addr_t 465 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 466 const u_int dci) 467 { 468 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 469 } 470 #endif /* unused */ 471 472 static inline void * 473 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline bus_addr_t 480 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 481 const u_int ici) 482 { 483 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 484 } 485 486 static inline struct xhci_trb * 487 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 488 { 489 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 490 } 491 492 static inline bus_addr_t 493 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 494 { 495 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 496 } 497 498 static inline void 499 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 500 uint32_t control) 501 { 502 trb->trb_0 = htole64(parameter); 503 trb->trb_2 = htole32(status); 504 trb->trb_3 = htole32(control); 505 } 506 507 static int 508 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 509 { 510 /* base address of TRBs */ 511 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 512 513 /* trb_0 range sanity check */ 514 if (trb_0 == 0 || trb_0 < trbp || 515 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 516 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 517 return 1; 518 } 519 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 520 return 0; 521 } 522 523 /* --- */ 524 525 void 526 xhci_childdet(device_t self, device_t child) 527 { 528 struct xhci_softc * const sc = device_private(self); 529 530 KASSERT(sc->sc_child == child); 531 if (child == sc->sc_child) 532 sc->sc_child = NULL; 533 } 534 535 int 536 xhci_detach(struct xhci_softc *sc, int flags) 537 { 538 int rv = 0; 539 540 if (sc->sc_child != NULL) 541 rv = config_detach(sc->sc_child, flags); 542 543 if (rv != 0) 544 return rv; 545 546 /* XXX unconfigure/free slots */ 547 548 /* verify: */ 549 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 550 xhci_op_write_4(sc, XHCI_USBCMD, 0); 551 /* do we need to wait for stop? */ 552 553 xhci_op_write_8(sc, XHCI_CRCR, 0); 554 xhci_ring_free(sc, &sc->sc_cr); 555 cv_destroy(&sc->sc_command_cv); 556 557 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 558 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 559 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 560 xhci_ring_free(sc, &sc->sc_er); 561 562 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 563 564 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 565 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 566 567 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 568 569 mutex_destroy(&sc->sc_lock); 570 mutex_destroy(&sc->sc_intr_lock); 571 572 pool_cache_destroy(sc->sc_xferpool); 573 574 return rv; 575 } 576 577 int 578 xhci_activate(device_t self, enum devact act) 579 { 580 struct xhci_softc * const sc = device_private(self); 581 582 switch (act) { 583 case DVACT_DEACTIVATE: 584 sc->sc_dying = true; 585 return 0; 586 default: 587 return EOPNOTSUPP; 588 } 589 } 590 591 bool 592 xhci_suspend(device_t dv, const pmf_qual_t *qual) 593 { 594 return false; 595 } 596 597 bool 598 xhci_resume(device_t dv, const pmf_qual_t *qual) 599 { 600 return false; 601 } 602 603 bool 604 xhci_shutdown(device_t self, int flags) 605 { 606 return false; 607 } 608 609 static int 610 xhci_hc_reset(struct xhci_softc * const sc) 611 { 612 uint32_t usbcmd, usbsts; 613 int i; 614 615 /* Check controller not ready */ 616 for (i = 0; i < XHCI_WAIT_CNR; i++) { 617 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 618 if ((usbsts & XHCI_STS_CNR) == 0) 619 break; 620 usb_delay_ms(&sc->sc_bus, 1); 621 } 622 if (i >= XHCI_WAIT_CNR) { 623 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 624 return EIO; 625 } 626 627 /* Halt controller */ 628 usbcmd = 0; 629 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 630 usb_delay_ms(&sc->sc_bus, 1); 631 632 /* Reset controller */ 633 usbcmd = XHCI_CMD_HCRST; 634 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 635 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 636 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 637 if ((usbcmd & XHCI_CMD_HCRST) == 0) 638 break; 639 usb_delay_ms(&sc->sc_bus, 1); 640 } 641 if (i >= XHCI_WAIT_HCRST) { 642 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 643 return EIO; 644 } 645 646 /* Check controller not ready */ 647 for (i = 0; i < XHCI_WAIT_CNR; i++) { 648 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 649 if ((usbsts & XHCI_STS_CNR) == 0) 650 break; 651 usb_delay_ms(&sc->sc_bus, 1); 652 } 653 if (i >= XHCI_WAIT_CNR) { 654 aprint_error_dev(sc->sc_dev, 655 "controller not ready timeout after reset\n"); 656 return EIO; 657 } 658 659 return 0; 660 } 661 662 663 static void 664 hexdump(const char *msg, const void *base, size_t len) 665 { 666 #if 0 667 size_t cnt; 668 const uint32_t *p; 669 extern paddr_t vtophys(vaddr_t); 670 671 p = base; 672 cnt = 0; 673 674 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 675 (void *)vtophys((vaddr_t)base)); 676 677 while (cnt < len) { 678 if (cnt % 16 == 0) 679 printf("%p: ", p); 680 else if (cnt % 8 == 0) 681 printf(" |"); 682 printf(" %08x", *p++); 683 cnt += 4; 684 if (cnt % 16 == 0) 685 printf("\n"); 686 } 687 if (cnt % 16 != 0) 688 printf("\n"); 689 #endif 690 } 691 692 /* Process extended capabilities */ 693 static void 694 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 695 { 696 uint32_t ecp, ecr; 697 698 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 699 700 ecp = XHCI_HCC_XECP(hcc) * 4; 701 while (ecp != 0) { 702 ecr = xhci_read_4(sc, ecp); 703 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 704 switch (XHCI_XECP_ID(ecr)) { 705 case XHCI_ID_PROTOCOLS: { 706 uint32_t w4, w8, wc; 707 uint16_t w2; 708 w2 = (ecr >> 16) & 0xffff; 709 w4 = xhci_read_4(sc, ecp + 4); 710 w8 = xhci_read_4(sc, ecp + 8); 711 wc = xhci_read_4(sc, ecp + 0xc); 712 aprint_debug_dev(sc->sc_dev, 713 " SP: %08x %08x %08x %08x\n", ecr, w4, w8, wc); 714 /* unused */ 715 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0300) { 716 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 717 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 718 } 719 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0200) { 720 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 721 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 722 } 723 break; 724 } 725 case XHCI_ID_USB_LEGACY: { 726 uint8_t bios_sem; 727 728 /* Take host controller ownership from BIOS */ 729 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 730 if (bios_sem) { 731 /* sets xHCI to be owned by OS */ 732 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 733 aprint_debug_dev(sc->sc_dev, 734 "waiting for BIOS to give up control\n"); 735 for (int i = 0; i < 5000; i++) { 736 bios_sem = xhci_read_1(sc, ecp + 737 XHCI_XECP_BIOS_SEM); 738 if (bios_sem == 0) 739 break; 740 DELAY(1000); 741 } 742 if (bios_sem) { 743 aprint_error_dev(sc->sc_dev, 744 "timed out waiting for BIOS\n"); 745 } 746 } 747 break; 748 } 749 default: 750 break; 751 } 752 ecr = xhci_read_4(sc, ecp); 753 if (XHCI_XECP_NEXT(ecr) == 0) { 754 ecp = 0; 755 } else { 756 ecp += XHCI_XECP_NEXT(ecr) * 4; 757 } 758 } 759 } 760 761 #define XHCI_HCCPREV1_BITS \ 762 "\177\020" /* New bitmask */ \ 763 "f\020\020XECP\0" \ 764 "f\014\4MAXPSA\0" \ 765 "b\013CFC\0" \ 766 "b\012SEC\0" \ 767 "b\011SBD\0" \ 768 "b\010FSE\0" \ 769 "b\7NSS\0" \ 770 "b\6LTC\0" \ 771 "b\5LHRC\0" \ 772 "b\4PIND\0" \ 773 "b\3PPC\0" \ 774 "b\2CZC\0" \ 775 "b\1BNC\0" \ 776 "b\0AC64\0" \ 777 "\0" 778 #define XHCI_HCCV1_x_BITS \ 779 "\177\020" /* New bitmask */ \ 780 "f\020\020XECP\0" \ 781 "f\014\4MAXPSA\0" \ 782 "b\013CFC\0" \ 783 "b\012SEC\0" \ 784 "b\011SPC\0" \ 785 "b\010PAE\0" \ 786 "b\7NSS\0" \ 787 "b\6LTC\0" \ 788 "b\5LHRC\0" \ 789 "b\4PIND\0" \ 790 "b\3PPC\0" \ 791 "b\2CSZ\0" \ 792 "b\1BNC\0" \ 793 "b\0AC64\0" \ 794 "\0" 795 796 int 797 xhci_init(struct xhci_softc *sc) 798 { 799 bus_size_t bsz; 800 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 801 uint32_t pagesize, config; 802 int i = 0; 803 uint16_t hciversion; 804 uint8_t caplength; 805 806 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 807 808 sc->sc_bus.ub_revision = USBREV_3_0; 809 sc->sc_bus.ub_usedma = true; 810 811 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 812 caplength = XHCI_CAP_CAPLENGTH(cap); 813 hciversion = XHCI_CAP_HCIVERSION(cap); 814 815 if (hciversion < XHCI_HCIVERSION_0_96 || 816 hciversion > XHCI_HCIVERSION_1_0) { 817 aprint_normal_dev(sc->sc_dev, 818 "xHCI version %x.%x not known to be supported\n", 819 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 820 } else { 821 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 822 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 823 } 824 825 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 826 &sc->sc_cbh) != 0) { 827 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 828 return ENOMEM; 829 } 830 831 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 832 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 833 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 834 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 835 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 836 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 837 aprint_debug_dev(sc->sc_dev, 838 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 839 840 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 841 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 842 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 843 844 char sbuf[128]; 845 if (hciversion < XHCI_HCIVERSION_1_0) 846 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 847 else 848 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 849 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 850 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 851 852 /* print PSI and take ownership from BIOS */ 853 xhci_ecp(sc, hcc); 854 855 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 856 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 857 &sc->sc_obh) != 0) { 858 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 859 return ENOMEM; 860 } 861 862 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 863 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 864 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 865 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 866 return ENOMEM; 867 } 868 869 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 870 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 871 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 872 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 873 return ENOMEM; 874 } 875 876 int rv; 877 rv = xhci_hc_reset(sc); 878 if (rv != 0) { 879 return rv; 880 } 881 882 if (sc->sc_vendor_init) 883 sc->sc_vendor_init(sc); 884 885 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 886 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 887 pagesize = ffs(pagesize); 888 if (pagesize == 0) { 889 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 890 return EIO; 891 } 892 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 893 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 894 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 895 (uint32_t)sc->sc_maxslots); 896 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 897 898 usbd_status err; 899 900 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 901 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 902 if (sc->sc_maxspbuf != 0) { 903 err = usb_allocmem(&sc->sc_bus, 904 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 905 &sc->sc_spbufarray_dma); 906 if (err) { 907 aprint_error_dev(sc->sc_dev, 908 "spbufarray init fail, err %d\n", err); 909 return ENOMEM; 910 } 911 912 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 913 sc->sc_maxspbuf, KM_SLEEP); 914 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 915 for (i = 0; i < sc->sc_maxspbuf; i++) { 916 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 917 /* allocate contexts */ 918 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 919 sc->sc_pgsz, dma); 920 if (err) { 921 aprint_error_dev(sc->sc_dev, 922 "spbufarray_dma init fail, err %d\n", err); 923 rv = ENOMEM; 924 goto bad1; 925 } 926 spbufarray[i] = htole64(DMAADDR(dma, 0)); 927 usb_syncmem(dma, 0, sc->sc_pgsz, 928 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 929 } 930 931 usb_syncmem(&sc->sc_spbufarray_dma, 0, 932 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 933 } 934 935 config = xhci_op_read_4(sc, XHCI_CONFIG); 936 config &= ~0xFF; 937 config |= sc->sc_maxslots & 0xFF; 938 xhci_op_write_4(sc, XHCI_CONFIG, config); 939 940 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 941 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 942 if (err) { 943 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 944 err); 945 rv = ENOMEM; 946 goto bad1; 947 } 948 949 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 950 XHCI_EVENT_RING_SEGMENTS_ALIGN); 951 if (err) { 952 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 953 err); 954 rv = ENOMEM; 955 goto bad2; 956 } 957 958 usb_dma_t *dma; 959 size_t size; 960 size_t align; 961 962 dma = &sc->sc_eventst_dma; 963 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 964 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 965 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 966 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 967 err = usb_allocmem(&sc->sc_bus, size, align, dma); 968 if (err) { 969 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 970 err); 971 rv = ENOMEM; 972 goto bad3; 973 } 974 975 memset(KERNADDR(dma, 0), 0, size); 976 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 977 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 978 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 979 KERNADDR(&sc->sc_eventst_dma, 0), 980 sc->sc_eventst_dma.udma_block->size); 981 982 dma = &sc->sc_dcbaa_dma; 983 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 984 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 985 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 986 err = usb_allocmem(&sc->sc_bus, size, align, dma); 987 if (err) { 988 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 989 rv = ENOMEM; 990 goto bad4; 991 } 992 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 993 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 994 KERNADDR(&sc->sc_dcbaa_dma, 0), 995 sc->sc_dcbaa_dma.udma_block->size); 996 997 memset(KERNADDR(dma, 0), 0, size); 998 if (sc->sc_maxspbuf != 0) { 999 /* 1000 * DCBA entry 0 hold the scratchbuf array pointer. 1001 */ 1002 *(uint64_t *)KERNADDR(dma, 0) = 1003 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1004 } 1005 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1006 1007 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1008 KM_SLEEP); 1009 if (sc->sc_slots == NULL) { 1010 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1011 rv = ENOMEM; 1012 goto bad; 1013 } 1014 1015 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1016 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1017 if (sc->sc_xferpool == NULL) { 1018 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1019 err); 1020 rv = ENOMEM; 1021 goto bad; 1022 } 1023 1024 cv_init(&sc->sc_command_cv, "xhcicmd"); 1025 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1026 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1027 1028 /* Set up the bus struct. */ 1029 sc->sc_bus.ub_methods = &xhci_bus_methods; 1030 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 1031 1032 struct xhci_erste *erst; 1033 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1034 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1035 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1036 erst[0].erste_3 = htole32(0); 1037 usb_syncmem(&sc->sc_eventst_dma, 0, 1038 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1039 1040 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1041 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1042 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1043 XHCI_ERDP_LO_BUSY); 1044 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1045 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1046 sc->sc_cr.xr_cs); 1047 1048 #if 0 1049 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1050 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1051 #endif 1052 1053 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1054 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1055 /* Intel xhci needs interrupt rate moderated. */ 1056 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1057 else 1058 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1059 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 1060 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1061 1062 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 1063 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1064 xhci_op_read_4(sc, XHCI_USBCMD)); 1065 1066 return 0; 1067 1068 bad: 1069 if (sc->sc_xferpool) { 1070 pool_cache_destroy(sc->sc_xferpool); 1071 sc->sc_xferpool = NULL; 1072 } 1073 1074 if (sc->sc_slots) { 1075 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1076 sc->sc_maxslots); 1077 sc->sc_slots = NULL; 1078 } 1079 1080 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1081 bad4: 1082 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1083 bad3: 1084 xhci_ring_free(sc, &sc->sc_er); 1085 bad2: 1086 xhci_ring_free(sc, &sc->sc_cr); 1087 i = sc->sc_maxspbuf; 1088 bad1: 1089 for (int j = 0; j < i; j++) 1090 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1091 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1092 1093 return rv; 1094 } 1095 1096 int 1097 xhci_intr(void *v) 1098 { 1099 struct xhci_softc * const sc = v; 1100 int ret = 0; 1101 1102 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1103 1104 if (sc == NULL) 1105 return 0; 1106 1107 mutex_spin_enter(&sc->sc_intr_lock); 1108 1109 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1110 goto done; 1111 1112 /* If we get an interrupt while polling, then just ignore it. */ 1113 if (sc->sc_bus.ub_usepolling) { 1114 #ifdef DIAGNOSTIC 1115 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1116 #endif 1117 goto done; 1118 } 1119 1120 ret = xhci_intr1(sc); 1121 done: 1122 mutex_spin_exit(&sc->sc_intr_lock); 1123 return ret; 1124 } 1125 1126 int 1127 xhci_intr1(struct xhci_softc * const sc) 1128 { 1129 uint32_t usbsts; 1130 uint32_t iman; 1131 1132 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1133 1134 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1135 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1136 #if 0 1137 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1138 return 0; 1139 } 1140 #endif 1141 xhci_op_write_4(sc, XHCI_USBSTS, 1142 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1143 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1144 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1145 1146 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1147 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1148 iman |= XHCI_IMAN_INTR_PEND; 1149 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1150 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1151 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1152 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1153 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1154 1155 usb_schedsoftintr(&sc->sc_bus); 1156 1157 return 1; 1158 } 1159 1160 /* 1161 * 3 port speed types used in USB stack 1162 * 1163 * usbdi speed 1164 * definition: USB_SPEED_* in usb.h 1165 * They are used in struct usbd_device in USB stack. 1166 * ioctl interface uses these values too. 1167 * port_status speed 1168 * definition: UPS_*_SPEED in usb.h 1169 * They are used in usb_port_status_t and valid only for USB 2.0. 1170 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1171 * of usb_port_status_ext_t indicates port speed. 1172 * Note that some 3.0 values overlap with 2.0 values. 1173 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1174 * means UPS_LOW_SPEED in HS.) 1175 * port status returned from hub also uses these values. 1176 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1177 * or more. 1178 * xspeed: 1179 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1180 * They are used in only slot context and PORTSC reg of xhci. 1181 * The difference between usbdi speed and xspeed is 1182 * that FS and LS values are swapped. 1183 */ 1184 1185 /* convert usbdi speed to xspeed */ 1186 static int 1187 xhci_speed2xspeed(int speed) 1188 { 1189 switch (speed) { 1190 case USB_SPEED_LOW: return 2; 1191 case USB_SPEED_FULL: return 1; 1192 default: return speed; 1193 } 1194 } 1195 1196 #if 0 1197 /* convert xspeed to usbdi speed */ 1198 static int 1199 xhci_xspeed2speed(int xspeed) 1200 { 1201 switch (xspeed) { 1202 case 1: return USB_SPEED_FULL; 1203 case 2: return USB_SPEED_LOW; 1204 default: return xspeed; 1205 } 1206 } 1207 #endif 1208 1209 /* convert xspeed to port status speed */ 1210 static int 1211 xhci_xspeed2psspeed(int xspeed) 1212 { 1213 switch (xspeed) { 1214 case 0: return 0; 1215 case 1: return UPS_FULL_SPEED; 1216 case 2: return UPS_LOW_SPEED; 1217 case 3: return UPS_HIGH_SPEED; 1218 default: return UPS_OTHER_SPEED; 1219 } 1220 } 1221 1222 /* 1223 * Construct input contexts and issue TRB to open pipe. 1224 */ 1225 static usbd_status 1226 xhci_configure_endpoint(struct usbd_pipe *pipe) 1227 { 1228 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1229 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1230 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1231 struct xhci_trb trb; 1232 usbd_status err; 1233 1234 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1235 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1236 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1237 pipe->up_endpoint->ue_edesc->bmAttributes); 1238 1239 KASSERT(!mutex_owned(&sc->sc_lock)); 1240 1241 /* XXX ensure input context is available? */ 1242 1243 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1244 1245 /* set up context */ 1246 xhci_setup_ctx(pipe); 1247 1248 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1249 sc->sc_ctxsz * 1); 1250 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1251 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1252 1253 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1254 trb.trb_2 = 0; 1255 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1256 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1257 1258 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1259 1260 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1261 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1262 sc->sc_ctxsz * 1); 1263 1264 return err; 1265 } 1266 1267 #if 0 1268 static usbd_status 1269 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1270 { 1271 #ifdef USB_DEBUG 1272 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1273 #endif 1274 1275 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1276 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1277 1278 return USBD_NORMAL_COMPLETION; 1279 } 1280 #endif 1281 1282 /* 4.6.8, 6.4.3.7 */ 1283 static usbd_status 1284 xhci_reset_endpoint(struct usbd_pipe *pipe) 1285 { 1286 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1287 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1288 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1289 struct xhci_trb trb; 1290 usbd_status err; 1291 1292 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1293 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1294 1295 KASSERT(!mutex_owned(&sc->sc_lock)); 1296 1297 trb.trb_0 = 0; 1298 trb.trb_2 = 0; 1299 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1300 XHCI_TRB_3_EP_SET(dci) | 1301 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1302 1303 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1304 1305 return err; 1306 } 1307 1308 /* 1309 * 4.6.9, 6.4.3.8 1310 * Stop execution of TDs on xfer ring. 1311 * Should be called with sc_lock held. 1312 */ 1313 static usbd_status 1314 xhci_stop_endpoint(struct usbd_pipe *pipe) 1315 { 1316 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1317 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1318 struct xhci_trb trb; 1319 usbd_status err; 1320 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1321 1322 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1323 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1324 1325 KASSERT(mutex_owned(&sc->sc_lock)); 1326 1327 trb.trb_0 = 0; 1328 trb.trb_2 = 0; 1329 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1330 XHCI_TRB_3_EP_SET(dci) | 1331 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1332 1333 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1334 1335 return err; 1336 } 1337 1338 /* 1339 * Set TR Dequeue Pointer. 1340 * xHCI 1.1 4.6.10 6.4.3.9 1341 * Purge all of the TRBs on ring and reinitialize ring. 1342 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1343 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1344 * error will be generated. 1345 */ 1346 static usbd_status 1347 xhci_set_dequeue(struct usbd_pipe *pipe) 1348 { 1349 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1350 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1351 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1352 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1353 struct xhci_trb trb; 1354 usbd_status err; 1355 1356 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1357 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1358 1359 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1360 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1361 BUS_DMASYNC_PREWRITE); 1362 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1363 1364 xr->xr_ep = 0; 1365 xr->xr_cs = 1; 1366 1367 /* set DCS */ 1368 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1369 trb.trb_2 = 0; 1370 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1371 XHCI_TRB_3_EP_SET(dci) | 1372 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1373 1374 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1375 1376 return err; 1377 } 1378 1379 /* 1380 * Open new pipe: called from usbd_setup_pipe_flags. 1381 * Fills methods of pipe. 1382 * If pipe is not for ep0, calls configure_endpoint. 1383 */ 1384 static usbd_status 1385 xhci_open(struct usbd_pipe *pipe) 1386 { 1387 struct usbd_device * const dev = pipe->up_dev; 1388 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1389 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1390 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1391 1392 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1393 DPRINTFN(1, "addr %d depth %d port %d speed %d", dev->ud_addr, 1394 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1395 DPRINTFN(1, " dci %u type 0x%02x epaddr 0x%02x attr 0x%02x", 1396 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1397 ed->bmAttributes); 1398 DPRINTFN(1, " mps %u ival %u", UGETW(ed->wMaxPacketSize), ed->bInterval, 1399 0, 0); 1400 1401 if (sc->sc_dying) 1402 return USBD_IOERROR; 1403 1404 /* Root Hub */ 1405 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1406 switch (ed->bEndpointAddress) { 1407 case USB_CONTROL_ENDPOINT: 1408 pipe->up_methods = &roothub_ctrl_methods; 1409 break; 1410 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1411 pipe->up_methods = &xhci_root_intr_methods; 1412 break; 1413 default: 1414 pipe->up_methods = NULL; 1415 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1416 ed->bEndpointAddress, 0, 0, 0); 1417 return USBD_INVAL; 1418 } 1419 return USBD_NORMAL_COMPLETION; 1420 } 1421 1422 switch (xfertype) { 1423 case UE_CONTROL: 1424 pipe->up_methods = &xhci_device_ctrl_methods; 1425 break; 1426 case UE_ISOCHRONOUS: 1427 pipe->up_methods = &xhci_device_isoc_methods; 1428 return USBD_INVAL; 1429 break; 1430 case UE_BULK: 1431 pipe->up_methods = &xhci_device_bulk_methods; 1432 break; 1433 case UE_INTERRUPT: 1434 pipe->up_methods = &xhci_device_intr_methods; 1435 break; 1436 default: 1437 return USBD_IOERROR; 1438 break; 1439 } 1440 1441 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1442 return xhci_configure_endpoint(pipe); 1443 1444 return USBD_NORMAL_COMPLETION; 1445 } 1446 1447 /* 1448 * Closes pipe, called from usbd_kill_pipe via close methods. 1449 * If the endpoint to be closed is ep0, disable_slot. 1450 * Should be called with sc_lock held. 1451 */ 1452 static void 1453 xhci_close_pipe(struct usbd_pipe *pipe) 1454 { 1455 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1456 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1457 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1458 const u_int dci = xhci_ep_get_dci(ed); 1459 struct xhci_trb trb; 1460 uint32_t *cp; 1461 1462 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1463 1464 if (sc->sc_dying) 1465 return; 1466 1467 /* xs is uninitialized before xhci_init_slot */ 1468 if (xs == NULL || xs->xs_idx == 0) 1469 return; 1470 1471 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1472 1473 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1474 KASSERT(mutex_owned(&sc->sc_lock)); 1475 1476 if (pipe->up_dev->ud_depth == 0) 1477 return; 1478 1479 if (dci == XHCI_DCI_EP_CONTROL) { 1480 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1481 xhci_disable_slot(sc, xs->xs_idx); 1482 return; 1483 } 1484 1485 /* 1486 * This may fail in the case that xhci_close_pipe is called after 1487 * xhci_abort_xfer e.g. usbd_kill_pipe. 1488 */ 1489 (void)xhci_stop_endpoint(pipe); 1490 1491 /* 1492 * set appropriate bit to be dropped. 1493 * don't set DC bit to 1, otherwise all endpoints 1494 * would be deconfigured. 1495 */ 1496 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1497 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1498 cp[1] = htole32(0); 1499 1500 /* XXX should be most significant one, not dci? */ 1501 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1502 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1503 1504 /* configure ep context performs an implicit dequeue */ 1505 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 1506 1507 /* sync input contexts before they are read from memory */ 1508 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1509 1510 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1511 trb.trb_2 = 0; 1512 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1513 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1514 1515 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1516 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1517 } 1518 1519 /* 1520 * Abort transfer. 1521 * May be called from softintr context. 1522 */ 1523 static void 1524 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1525 { 1526 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1527 1528 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1529 DPRINTFN(4, "xfer %p pipe %p status %d", 1530 xfer, xfer->ux_pipe, status, 0); 1531 1532 KASSERT(mutex_owned(&sc->sc_lock)); 1533 1534 if (sc->sc_dying) { 1535 /* If we're dying, just do the software part. */ 1536 DPRINTFN(4, "xfer %p dying %u", xfer, xfer->ux_status, 0, 0); 1537 xfer->ux_status = status; 1538 callout_stop(&xfer->ux_callout); 1539 usb_transfer_complete(xfer); 1540 return; 1541 } 1542 1543 /* XXX need more stuff */ 1544 xfer->ux_status = status; 1545 callout_stop(&xfer->ux_callout); 1546 usb_transfer_complete(xfer); 1547 DPRINTFN(14, "end", 0, 0, 0, 0); 1548 1549 KASSERT(mutex_owned(&sc->sc_lock)); 1550 } 1551 1552 static void 1553 xhci_host_dequeue(struct xhci_ring * const xr) 1554 { 1555 /* When dequeueing the controller, update our struct copy too */ 1556 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1557 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1558 BUS_DMASYNC_PREWRITE); 1559 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1560 1561 xr->xr_ep = 0; 1562 xr->xr_cs = 1; 1563 } 1564 1565 /* 1566 * Recover STALLed endpoint. 1567 * xHCI 1.1 sect 4.10.2.1 1568 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1569 * all transfers on transfer ring. 1570 * These are done in thread context asynchronously. 1571 */ 1572 static void 1573 xhci_clear_endpoint_stall_async_task(void *cookie) 1574 { 1575 struct usbd_xfer * const xfer = cookie; 1576 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1577 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1578 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1579 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1580 1581 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1582 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1583 1584 xhci_reset_endpoint(xfer->ux_pipe); 1585 xhci_set_dequeue(xfer->ux_pipe); 1586 1587 mutex_enter(&sc->sc_lock); 1588 tr->is_halted = false; 1589 usb_transfer_complete(xfer); 1590 mutex_exit(&sc->sc_lock); 1591 DPRINTFN(4, "ends", 0, 0, 0, 0); 1592 } 1593 1594 static usbd_status 1595 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1596 { 1597 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1598 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1599 1600 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1601 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1602 1603 if (sc->sc_dying) { 1604 return USBD_IOERROR; 1605 } 1606 1607 usb_init_task(&xp->xp_async_task, 1608 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1609 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1610 DPRINTFN(4, "ends", 0, 0, 0, 0); 1611 1612 return USBD_NORMAL_COMPLETION; 1613 } 1614 1615 /* Process roothub port status/change events and notify to uhub_intr. */ 1616 static void 1617 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1618 { 1619 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1620 uint8_t *p; 1621 1622 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1623 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1624 port, 0, 0); 1625 1626 if (xfer == NULL) 1627 return; 1628 1629 if (port > sc->sc_maxports) 1630 return; 1631 1632 p = xfer->ux_buf; 1633 memset(p, 0, xfer->ux_length); 1634 p[port/NBBY] |= 1 << (port%NBBY); 1635 xfer->ux_actlen = xfer->ux_length; 1636 xfer->ux_status = USBD_NORMAL_COMPLETION; 1637 usb_transfer_complete(xfer); 1638 } 1639 1640 /* Process Transfer Events */ 1641 static void 1642 xhci_event_transfer(struct xhci_softc * const sc, 1643 const struct xhci_trb * const trb) 1644 { 1645 uint64_t trb_0; 1646 uint32_t trb_2, trb_3; 1647 uint8_t trbcode; 1648 u_int slot, dci; 1649 struct xhci_slot *xs; 1650 struct xhci_ring *xr; 1651 struct xhci_xfer *xx; 1652 struct usbd_xfer *xfer; 1653 usbd_status err; 1654 1655 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1656 1657 trb_0 = le64toh(trb->trb_0); 1658 trb_2 = le32toh(trb->trb_2); 1659 trb_3 = le32toh(trb->trb_3); 1660 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1661 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1662 dci = XHCI_TRB_3_EP_GET(trb_3); 1663 xs = &sc->sc_slots[slot]; 1664 xr = &xs->xs_ep[dci].xe_tr; 1665 1666 /* sanity check */ 1667 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1668 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1669 1670 int idx = 0; 1671 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1672 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1673 DPRINTFN(0, "invalid trb_0 0x%"PRIx64, trb_0, 0, 0, 0); 1674 return; 1675 } 1676 xx = xr->xr_cookies[idx]; 1677 1678 /* 1679 * If endpoint is stopped between TDs, TRB pointer points at 1680 * next TRB, however, it is not put yet or is a garbage TRB. 1681 * That's why xr_cookies may be NULL or look like broken. 1682 * Note: this ev happens only when hciversion >= 1.0 or 1683 * hciversion == 0.96 and FSE of hcc1 is set. 1684 */ 1685 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1686 DPRINTFN(1, "Ignore #%u: cookie %p cc %u dci %u", 1687 idx, xx, trbcode, dci); 1688 DPRINTFN(1, " orig TRB %"PRIx64" type %u", trb_0, 1689 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1690 0, 0); 1691 } 1692 } else { 1693 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1694 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1695 } 1696 /* XXX this may not happen */ 1697 if (xx == NULL) { 1698 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1699 return; 1700 } 1701 xfer = &xx->xx_xfer; 1702 /* XXX this may happen when detaching */ 1703 if (xfer == NULL) { 1704 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1705 xx, trb_0, 0, 0); 1706 return; 1707 } 1708 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1709 /* XXX I dunno why this happens */ 1710 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1711 1712 if (!xfer->ux_pipe->up_repeat && 1713 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1714 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1715 return; 1716 } 1717 1718 /* 4.11.5.2 Event Data TRB */ 1719 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1720 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1721 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1722 if ((trb_0 & 0x3) == 0x3) { 1723 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1724 } 1725 } 1726 1727 switch (trbcode) { 1728 case XHCI_TRB_ERROR_SHORT_PKT: 1729 case XHCI_TRB_ERROR_SUCCESS: 1730 /* 1731 * A ctrl transfer generates two events if it has a Data stage. 1732 * After a successful Data stage we cannot call call 1733 * usb_transfer_complete - this can only happen after the Data 1734 * stage. 1735 * 1736 * Note: Data and Status stage events point at same xfer. 1737 * ux_actlen and ux_dmabuf will be passed to 1738 * usb_transfer_complete after the Status stage event. 1739 * 1740 * It can be distingished which stage generates the event: 1741 * + by checking least 3 bits of trb_0 if ED==1. 1742 * (see xhci_device_ctrl_start). 1743 * + by checking the type of original TRB if ED==0. 1744 * 1745 * In addition, intr, bulk, and isoc transfer currently 1746 * consists of single TD, so the "skip" is not needed. 1747 * ctrl xfer uses EVENT_DATA, and others do not. 1748 * Thus driver can switch the flow by checking ED bit. 1749 */ 1750 xfer->ux_actlen = 1751 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1752 err = USBD_NORMAL_COMPLETION; 1753 break; 1754 case XHCI_TRB_ERROR_STALL: 1755 case XHCI_TRB_ERROR_BABBLE: 1756 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1757 xr->is_halted = true; 1758 err = USBD_STALLED; 1759 /* 1760 * Stalled endpoints can be recoverd by issuing 1761 * command TRB TYPE_RESET_EP on xHCI instead of 1762 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1763 * on the endpoint. However, this function may be 1764 * called from softint context (e.g. from umass), 1765 * in that case driver gets KASSERT in cv_timedwait 1766 * in xhci_do_command. 1767 * To avoid this, this runs reset_endpoint and 1768 * usb_transfer_complete in usb task thread 1769 * asynchronously (and then umass issues clear 1770 * UF_ENDPOINT_HALT). 1771 */ 1772 xfer->ux_status = err; 1773 xhci_clear_endpoint_stall_async(xfer); 1774 return; 1775 default: 1776 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1777 err = USBD_IOERROR; 1778 break; 1779 } 1780 xfer->ux_status = err; 1781 1782 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1783 if ((trb_0 & 0x3) == 0x0) { 1784 callout_stop(&xfer->ux_callout); 1785 usb_transfer_complete(xfer); 1786 } 1787 } else { 1788 callout_stop(&xfer->ux_callout); 1789 usb_transfer_complete(xfer); 1790 } 1791 } 1792 1793 /* Process Command complete events */ 1794 static void 1795 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 1796 { 1797 uint64_t trb_0; 1798 uint32_t trb_2, trb_3; 1799 1800 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1801 1802 trb_0 = le64toh(trb->trb_0); 1803 trb_2 = le32toh(trb->trb_2); 1804 trb_3 = le32toh(trb->trb_3); 1805 1806 if (trb_0 == sc->sc_command_addr) { 1807 sc->sc_result_trb.trb_0 = trb_0; 1808 sc->sc_result_trb.trb_2 = trb_2; 1809 sc->sc_result_trb.trb_3 = trb_3; 1810 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1811 XHCI_TRB_ERROR_SUCCESS) { 1812 DPRINTFN(1, "command completion " 1813 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1814 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1815 } 1816 cv_signal(&sc->sc_command_cv); 1817 } else { 1818 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 1819 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1820 trb_2, trb_3); 1821 } 1822 } 1823 1824 /* 1825 * Process events. 1826 * called from xhci_softintr 1827 */ 1828 static void 1829 xhci_handle_event(struct xhci_softc * const sc, 1830 const struct xhci_trb * const trb) 1831 { 1832 uint64_t trb_0; 1833 uint32_t trb_2, trb_3; 1834 1835 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1836 1837 trb_0 = le64toh(trb->trb_0); 1838 trb_2 = le32toh(trb->trb_2); 1839 trb_3 = le32toh(trb->trb_3); 1840 1841 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1842 trb, trb_0, trb_2, trb_3); 1843 1844 /* 1845 * 4.11.3.1, 6.4.2.1 1846 * TRB Pointer is invalid for these completion codes. 1847 */ 1848 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 1849 case XHCI_TRB_ERROR_RING_UNDERRUN: 1850 case XHCI_TRB_ERROR_RING_OVERRUN: 1851 case XHCI_TRB_ERROR_VF_RING_FULL: 1852 return; 1853 default: 1854 if (trb_0 == 0) { 1855 return; 1856 } 1857 break; 1858 } 1859 1860 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 1861 case XHCI_TRB_EVENT_TRANSFER: 1862 xhci_event_transfer(sc, trb); 1863 break; 1864 case XHCI_TRB_EVENT_CMD_COMPLETE: 1865 xhci_event_cmd(sc, trb); 1866 break; 1867 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1868 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1869 break; 1870 default: 1871 break; 1872 } 1873 } 1874 1875 static void 1876 xhci_softintr(void *v) 1877 { 1878 struct usbd_bus * const bus = v; 1879 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1880 struct xhci_ring * const er = &sc->sc_er; 1881 struct xhci_trb *trb; 1882 int i, j, k; 1883 1884 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1885 1886 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1887 1888 i = er->xr_ep; 1889 j = er->xr_cs; 1890 1891 DPRINTFN(16, "er: xr_ep %d xr_cs %d", i, j, 0, 0); 1892 1893 while (1) { 1894 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 1895 BUS_DMASYNC_POSTREAD); 1896 trb = &er->xr_trb[i]; 1897 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1898 1899 if (j != k) 1900 break; 1901 1902 xhci_handle_event(sc, trb); 1903 1904 i++; 1905 if (i == er->xr_ntrb) { 1906 i = 0; 1907 j ^= 1; 1908 } 1909 } 1910 1911 er->xr_ep = i; 1912 er->xr_cs = j; 1913 1914 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 1915 XHCI_ERDP_LO_BUSY); 1916 1917 DPRINTFN(16, "ends", 0, 0, 0, 0); 1918 1919 return; 1920 } 1921 1922 static void 1923 xhci_poll(struct usbd_bus *bus) 1924 { 1925 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1926 1927 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1928 1929 mutex_spin_enter(&sc->sc_intr_lock); 1930 xhci_intr1(sc); 1931 mutex_spin_exit(&sc->sc_intr_lock); 1932 1933 return; 1934 } 1935 1936 static struct usbd_xfer * 1937 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 1938 { 1939 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1940 struct usbd_xfer *xfer; 1941 1942 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1943 1944 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1945 if (xfer != NULL) { 1946 memset(xfer, 0, sizeof(struct xhci_xfer)); 1947 #ifdef DIAGNOSTIC 1948 xfer->ux_state = XFER_BUSY; 1949 #endif 1950 } 1951 1952 return xfer; 1953 } 1954 1955 static void 1956 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1957 { 1958 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1959 1960 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1961 1962 #ifdef DIAGNOSTIC 1963 if (xfer->ux_state != XFER_BUSY) { 1964 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 1965 xfer, xfer->ux_state, 0, 0); 1966 } 1967 xfer->ux_state = XFER_FREE; 1968 #endif 1969 pool_cache_put(sc->sc_xferpool, xfer); 1970 } 1971 1972 static void 1973 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1974 { 1975 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1976 1977 *lock = &sc->sc_lock; 1978 } 1979 1980 extern uint32_t usb_cookie_no; 1981 1982 /* 1983 * xHCI 4.3 1984 * Called when uhub_explore finds a new device (via usbd_new_device). 1985 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 1986 * This function does: 1987 * Allocate and construct dev structure of default endpoint (ep0). 1988 * Allocate and open pipe of ep0. 1989 * Enable slot and initialize slot context. 1990 * Set Address. 1991 * Read initial device descriptor. 1992 * Determine initial MaxPacketSize (mps) by speed. 1993 * Read full device descriptor. 1994 * Register this device. 1995 * Finally state of device transitions ADDRESSED. 1996 */ 1997 static usbd_status 1998 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 1999 int speed, int port, struct usbd_port *up) 2000 { 2001 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2002 struct usbd_device *dev; 2003 usbd_status err; 2004 usb_device_descriptor_t *dd; 2005 struct xhci_slot *xs; 2006 uint32_t *cp; 2007 2008 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2009 DPRINTFN(4, "port %u depth %u speed %u up %p", port, depth, speed, up); 2010 2011 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2012 if (dev == NULL) 2013 return USBD_NOMEM; 2014 2015 dev->ud_bus = bus; 2016 dev->ud_quirks = &usbd_no_quirk; 2017 dev->ud_addr = 0; 2018 dev->ud_ddesc.bMaxPacketSize = 0; 2019 dev->ud_depth = depth; 2020 dev->ud_powersrc = up; 2021 dev->ud_myhub = up->up_parent; 2022 dev->ud_speed = speed; 2023 dev->ud_langid = USBD_NOLANG; 2024 dev->ud_cookie.cookie = ++usb_cookie_no; 2025 2026 /* Set up default endpoint handle. */ 2027 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2028 /* doesn't matter, just don't let it uninitialized */ 2029 dev->ud_ep0.ue_toggle = 0; 2030 2031 /* Set up default endpoint descriptor. */ 2032 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2033 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2034 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2035 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2036 dev->ud_ep0desc.bInterval = 0; 2037 2038 /* 4.3, 4.8.2.1 */ 2039 switch (speed) { 2040 case USB_SPEED_SUPER: 2041 case USB_SPEED_SUPER_PLUS: 2042 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2043 break; 2044 case USB_SPEED_FULL: 2045 /* XXX using 64 as initial mps of ep0 in FS */ 2046 case USB_SPEED_HIGH: 2047 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2048 break; 2049 case USB_SPEED_LOW: 2050 default: 2051 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2052 break; 2053 } 2054 2055 up->up_dev = dev; 2056 2057 /* Establish the default pipe. */ 2058 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2059 &dev->ud_pipe0); 2060 if (err) { 2061 goto bad; 2062 } 2063 2064 dd = &dev->ud_ddesc; 2065 2066 if ((depth == 0) && (port == 0)) { 2067 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2068 bus->ub_devices[dev->ud_addr] = dev; 2069 err = usbd_get_initial_ddesc(dev, dd); 2070 if (err) 2071 goto bad; 2072 err = usbd_reload_device_desc(dev); 2073 if (err) 2074 goto bad; 2075 } else { 2076 uint8_t slot = 0; 2077 2078 /* 4.3.2 */ 2079 err = xhci_enable_slot(sc, &slot); 2080 if (err) 2081 goto bad; 2082 2083 xs = &sc->sc_slots[slot]; 2084 dev->ud_hcpriv = xs; 2085 2086 /* 4.3.3 initialize slot structure */ 2087 err = xhci_init_slot(dev, slot); 2088 if (err) { 2089 dev->ud_hcpriv = NULL; 2090 /* 2091 * We have to disable_slot here because 2092 * xs->xs_idx == 0 when xhci_init_slot fails, 2093 * in that case usbd_remove_dev won't work. 2094 */ 2095 mutex_enter(&sc->sc_lock); 2096 xhci_disable_slot(sc, slot); 2097 mutex_exit(&sc->sc_lock); 2098 goto bad; 2099 } 2100 2101 /* 4.3.4 Address Assignment */ 2102 err = xhci_set_address(dev, slot, false); 2103 if (err) 2104 goto bad; 2105 2106 /* Allow device time to set new address */ 2107 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2108 2109 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2110 //hexdump("slot context", cp, sc->sc_ctxsz); 2111 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2112 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2113 /* XXX ensure we know when the hardware does something 2114 we can't yet cope with */ 2115 KASSERT(addr >= 1 && addr <= 127); 2116 dev->ud_addr = addr; 2117 /* XXX dev->ud_addr not necessarily unique on bus */ 2118 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2119 bus->ub_devices[dev->ud_addr] = dev; 2120 2121 err = usbd_get_initial_ddesc(dev, dd); 2122 if (err) 2123 goto bad; 2124 2125 /* 4.8.2.1 */ 2126 if (USB_IS_SS(speed)) { 2127 if (dd->bMaxPacketSize != 9) { 2128 printf("%s: invalid mps 2^%u for SS ep0," 2129 " using 512\n", 2130 device_xname(sc->sc_dev), 2131 dd->bMaxPacketSize); 2132 dd->bMaxPacketSize = 9; 2133 } 2134 USETW(dev->ud_ep0desc.wMaxPacketSize, 2135 (1 << dd->bMaxPacketSize)); 2136 } else 2137 USETW(dev->ud_ep0desc.wMaxPacketSize, 2138 dd->bMaxPacketSize); 2139 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2140 xhci_update_ep0_mps(sc, xs, 2141 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2142 2143 err = usbd_reload_device_desc(dev); 2144 if (err) 2145 goto bad; 2146 } 2147 2148 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2149 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2150 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2151 dd->bDeviceClass, dd->bDeviceSubClass, 2152 dd->bDeviceProtocol, 0); 2153 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2154 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2155 dev->ud_speed); 2156 2157 usbd_get_device_strings(dev); 2158 2159 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2160 2161 if ((depth == 0) && (port == 0)) { 2162 usbd_attach_roothub(parent, dev); 2163 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2164 return USBD_NORMAL_COMPLETION; 2165 } 2166 2167 2168 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2169 bad: 2170 if (err != USBD_NORMAL_COMPLETION) { 2171 usbd_remove_device(dev, up); 2172 } 2173 2174 return err; 2175 } 2176 2177 static usbd_status 2178 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2179 size_t ntrb, size_t align) 2180 { 2181 usbd_status err; 2182 size_t size = ntrb * XHCI_TRB_SIZE; 2183 2184 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2185 2186 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2187 if (err) 2188 return err; 2189 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2190 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2191 xr->xr_trb = xhci_ring_trbv(xr, 0); 2192 xr->xr_ntrb = ntrb; 2193 xr->is_halted = false; 2194 xhci_host_dequeue(xr); 2195 2196 return USBD_NORMAL_COMPLETION; 2197 } 2198 2199 static void 2200 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2201 { 2202 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2203 mutex_destroy(&xr->xr_lock); 2204 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2205 } 2206 2207 static void 2208 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2209 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2210 { 2211 size_t i; 2212 u_int ri; 2213 u_int cs; 2214 uint64_t parameter; 2215 uint32_t status; 2216 uint32_t control; 2217 2218 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2219 2220 KASSERT(ntrbs <= XHCI_XFER_NTRB); 2221 for (i = 0; i < ntrbs; i++) { 2222 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2223 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2224 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2225 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2226 XHCI_TRB_TYPE_LINK); 2227 } 2228 2229 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2230 2231 ri = xr->xr_ep; 2232 cs = xr->xr_cs; 2233 2234 /* 2235 * Although the xhci hardware can do scatter/gather dma from 2236 * arbitrary sized buffers, there is a non-obvious restriction 2237 * that a LINK trb is only allowed at the end of a burst of 2238 * transfers - which might be 16kB. 2239 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2240 * The simple solution is not to allow a LINK trb in the middle 2241 * of anything - as here. 2242 * XXX: (dsl) There are xhci controllers out there (eg some made by 2243 * ASMedia) that seem to lock up if they process a LINK trb but 2244 * cannot process the linked-to trb yet. 2245 * The code should write the 'cycle' bit on the link trb AFTER 2246 * adding the other trb. 2247 */ 2248 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2249 parameter = xhci_ring_trbp(xr, 0); 2250 status = 0; 2251 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2252 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2253 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2254 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2255 BUS_DMASYNC_PREWRITE); 2256 xr->xr_cookies[ri] = NULL; 2257 xr->xr_ep = 0; 2258 xr->xr_cs ^= 1; 2259 ri = xr->xr_ep; 2260 cs = xr->xr_cs; 2261 } 2262 2263 ri++; 2264 2265 /* Write any subsequent TRB first */ 2266 for (i = 1; i < ntrbs; i++) { 2267 parameter = trbs[i].trb_0; 2268 status = trbs[i].trb_2; 2269 control = trbs[i].trb_3; 2270 2271 if (cs) { 2272 control |= XHCI_TRB_3_CYCLE_BIT; 2273 } else { 2274 control &= ~XHCI_TRB_3_CYCLE_BIT; 2275 } 2276 2277 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2278 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2279 BUS_DMASYNC_PREWRITE); 2280 xr->xr_cookies[ri] = cookie; 2281 ri++; 2282 } 2283 2284 /* Write the first TRB last */ 2285 i = 0; 2286 parameter = trbs[i].trb_0; 2287 status = trbs[i].trb_2; 2288 control = trbs[i].trb_3; 2289 2290 if (xr->xr_cs) { 2291 control |= XHCI_TRB_3_CYCLE_BIT; 2292 } else { 2293 control &= ~XHCI_TRB_3_CYCLE_BIT; 2294 } 2295 2296 xhci_trb_put(&xr->xr_trb[xr->xr_ep], parameter, status, control); 2297 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * xr->xr_ep, XHCI_TRB_SIZE * 1, 2298 BUS_DMASYNC_PREWRITE); 2299 xr->xr_cookies[xr->xr_ep] = cookie; 2300 2301 xr->xr_ep = ri; 2302 xr->xr_cs = cs; 2303 2304 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2305 } 2306 2307 /* 2308 * Stop execution commands, purge all commands on command ring, and 2309 * rewind dequeue pointer. 2310 */ 2311 static void 2312 xhci_abort_command(struct xhci_softc *sc) 2313 { 2314 struct xhci_ring * const cr = &sc->sc_cr; 2315 uint64_t crcr; 2316 int i; 2317 2318 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2319 DPRINTFN(14, "command %#"PRIx64" timeout, aborting", 2320 sc->sc_command_addr, 0, 0, 0); 2321 2322 mutex_enter(&cr->xr_lock); 2323 2324 /* 4.6.1.2 Aborting a Command */ 2325 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2326 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2327 2328 for (i = 0; i < 500; i++) { 2329 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2330 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2331 break; 2332 usb_delay_ms(&sc->sc_bus, 1); 2333 } 2334 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2335 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2336 /* reset HC here? */ 2337 } 2338 2339 /* reset command ring dequeue pointer */ 2340 cr->xr_ep = 0; 2341 cr->xr_cs = 1; 2342 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2343 2344 mutex_exit(&cr->xr_lock); 2345 } 2346 2347 /* 2348 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2349 * Command completion is notified by cv_signal from xhci_event_cmd() 2350 * (called from xhci_softint), or timed-out. 2351 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2352 * then do_command examines it. 2353 */ 2354 static usbd_status 2355 xhci_do_command_locked(struct xhci_softc * const sc, 2356 struct xhci_trb * const trb, int timeout) 2357 { 2358 struct xhci_ring * const cr = &sc->sc_cr; 2359 usbd_status err; 2360 2361 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2362 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2363 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2364 2365 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2366 KASSERT(mutex_owned(&sc->sc_lock)); 2367 2368 /* XXX KASSERT may fire when cv_timedwait unlocks sc_lock */ 2369 KASSERT(sc->sc_command_addr == 0); 2370 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2371 2372 mutex_enter(&cr->xr_lock); 2373 xhci_ring_put(sc, cr, NULL, trb, 1); 2374 mutex_exit(&cr->xr_lock); 2375 2376 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2377 2378 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2379 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2380 xhci_abort_command(sc); 2381 err = USBD_TIMEOUT; 2382 goto timedout; 2383 } 2384 2385 trb->trb_0 = sc->sc_result_trb.trb_0; 2386 trb->trb_2 = sc->sc_result_trb.trb_2; 2387 trb->trb_3 = sc->sc_result_trb.trb_3; 2388 2389 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2390 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2391 2392 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2393 case XHCI_TRB_ERROR_SUCCESS: 2394 err = USBD_NORMAL_COMPLETION; 2395 break; 2396 default: 2397 case 192 ... 223: 2398 err = USBD_IOERROR; 2399 break; 2400 case 224 ... 255: 2401 err = USBD_NORMAL_COMPLETION; 2402 break; 2403 } 2404 2405 timedout: 2406 sc->sc_command_addr = 0; 2407 return err; 2408 } 2409 2410 static usbd_status 2411 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2412 int timeout) 2413 { 2414 2415 mutex_enter(&sc->sc_lock); 2416 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2417 mutex_exit(&sc->sc_lock); 2418 2419 return ret; 2420 } 2421 2422 static usbd_status 2423 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2424 { 2425 struct xhci_trb trb; 2426 usbd_status err; 2427 2428 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2429 2430 trb.trb_0 = 0; 2431 trb.trb_2 = 0; 2432 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2433 2434 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2435 if (err != USBD_NORMAL_COMPLETION) { 2436 return err; 2437 } 2438 2439 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2440 2441 return err; 2442 } 2443 2444 /* 2445 * xHCI 4.6.4 2446 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2447 * All endpoints in the slot should be stopped. 2448 * Should be called with sc_lock held. 2449 */ 2450 static usbd_status 2451 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2452 { 2453 struct xhci_trb trb; 2454 struct xhci_slot *xs; 2455 usbd_status err; 2456 2457 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2458 2459 if (sc->sc_dying) 2460 return USBD_IOERROR; 2461 2462 trb.trb_0 = 0; 2463 trb.trb_2 = 0; 2464 trb.trb_3 = htole32( 2465 XHCI_TRB_3_SLOT_SET(slot) | 2466 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2467 2468 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2469 2470 if (!err) { 2471 xs = &sc->sc_slots[slot]; 2472 if (xs->xs_idx != 0) { 2473 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2474 xhci_set_dcba(sc, 0, slot); 2475 memset(xs, 0, sizeof(*xs)); 2476 } 2477 } 2478 2479 return err; 2480 } 2481 2482 /* 2483 * Set address of device and transition slot state from ENABLED to ADDRESSED 2484 * if Block Setaddress Request (BSR) is false. 2485 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2486 * see xHCI 1.1 4.5.3, 3.3.4 2487 * Should be called without sc_lock held. 2488 */ 2489 static usbd_status 2490 xhci_address_device(struct xhci_softc * const sc, 2491 uint64_t icp, uint8_t slot_id, bool bsr) 2492 { 2493 struct xhci_trb trb; 2494 usbd_status err; 2495 2496 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2497 2498 trb.trb_0 = icp; 2499 trb.trb_2 = 0; 2500 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2501 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2502 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2503 2504 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2505 2506 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2507 err = USBD_NO_ADDR; 2508 2509 return err; 2510 } 2511 2512 static usbd_status 2513 xhci_update_ep0_mps(struct xhci_softc * const sc, 2514 struct xhci_slot * const xs, u_int mps) 2515 { 2516 struct xhci_trb trb; 2517 usbd_status err; 2518 uint32_t * cp; 2519 2520 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2521 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2522 2523 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2524 cp[0] = htole32(0); 2525 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2526 2527 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2528 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2529 2530 /* sync input contexts before they are read from memory */ 2531 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2532 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2533 sc->sc_ctxsz * 4); 2534 2535 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2536 trb.trb_2 = 0; 2537 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2538 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2539 2540 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2541 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2542 return err; 2543 } 2544 2545 static void 2546 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2547 { 2548 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2549 2550 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2551 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2552 &dcbaa[si], dcba, si, 0); 2553 2554 dcbaa[si] = htole64(dcba); 2555 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2556 BUS_DMASYNC_PREWRITE); 2557 } 2558 2559 /* 2560 * Allocate device and input context DMA buffer, and 2561 * TRB DMA buffer for each endpoint. 2562 */ 2563 static usbd_status 2564 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2565 { 2566 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2567 struct xhci_slot *xs; 2568 usbd_status err; 2569 u_int dci; 2570 2571 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2572 DPRINTFN(4, "slot %u", slot, 0, 0, 0); 2573 2574 xs = &sc->sc_slots[slot]; 2575 2576 /* allocate contexts */ 2577 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2578 &xs->xs_dc_dma); 2579 if (err) 2580 return err; 2581 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2582 2583 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2584 &xs->xs_ic_dma); 2585 if (err) 2586 goto bad1; 2587 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2588 2589 for (dci = 0; dci < 32; dci++) { 2590 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2591 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2592 if (dci == XHCI_DCI_SLOT) 2593 continue; 2594 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2595 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2596 if (err) { 2597 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2598 goto bad2; 2599 } 2600 } 2601 2602 bad2: 2603 if (err == USBD_NORMAL_COMPLETION) { 2604 xs->xs_idx = slot; 2605 } else { 2606 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2607 } 2608 2609 return err; 2610 2611 bad1: 2612 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2613 xs->xs_idx = 0; 2614 return err; 2615 } 2616 2617 static void 2618 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2619 int end_dci) 2620 { 2621 u_int dci; 2622 2623 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2624 DPRINTFN(4, "slot %u start %u end %u", xs->xs_idx, start_dci, end_dci, 2625 0); 2626 2627 for (dci = start_dci; dci < end_dci; dci++) { 2628 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2629 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2630 } 2631 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2632 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2633 xs->xs_idx = 0; 2634 } 2635 2636 /* 2637 * Setup slot context, set Device Context Base Address, and issue 2638 * Set Address Device command. 2639 */ 2640 static usbd_status 2641 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 2642 { 2643 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2644 struct xhci_slot *xs; 2645 usbd_status err; 2646 2647 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2648 DPRINTFN(4, "slot %u bsr %u", slot, bsr, 0, 0); 2649 2650 xs = &sc->sc_slots[slot]; 2651 2652 xhci_setup_ctx(dev->ud_pipe0); 2653 2654 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2655 sc->sc_ctxsz * 3); 2656 2657 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2658 2659 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 2660 2661 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2662 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2663 sc->sc_ctxsz * 2); 2664 2665 return err; 2666 } 2667 2668 /* 2669 * 4.8.2, 6.2.3.2 2670 * construct slot/endpoint context parameters and do syncmem 2671 */ 2672 static void 2673 xhci_setup_ctx(struct usbd_pipe *pipe) 2674 { 2675 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2676 struct usbd_device *dev = pipe->up_dev; 2677 struct xhci_slot * const xs = dev->ud_hcpriv; 2678 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2679 const u_int dci = xhci_ep_get_dci(ed); 2680 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2681 uint32_t *cp; 2682 uint16_t mps = UGETW(ed->wMaxPacketSize); 2683 uint8_t speed = dev->ud_speed; 2684 uint8_t ival = ed->bInterval; 2685 2686 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2687 DPRINTFN(4, "pipe %p: slot %u dci %u speed %u", pipe, xs->xs_idx, dci, 2688 speed); 2689 2690 /* set up initial input control context */ 2691 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2692 cp[0] = htole32(0); 2693 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 2694 if (dci == XHCI_DCI_EP_CONTROL) 2695 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2696 cp[7] = htole32(0); 2697 2698 /* set up input slot context */ 2699 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2700 cp[0] = 2701 XHCI_SCTX_0_CTX_NUM_SET(dci) | 2702 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 2703 cp[1] = 0; 2704 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2705 cp[3] = 0; 2706 xhci_setup_route(pipe, cp); 2707 xhci_setup_tthub(pipe, cp); 2708 2709 cp[0] = htole32(cp[0]); 2710 cp[1] = htole32(cp[1]); 2711 cp[2] = htole32(cp[2]); 2712 cp[3] = htole32(cp[3]); 2713 2714 /* set up input endpoint context */ 2715 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 2716 cp[0] = 2717 XHCI_EPCTX_0_EPSTATE_SET(0) | 2718 XHCI_EPCTX_0_MULT_SET(0) | 2719 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2720 XHCI_EPCTX_0_LSA_SET(0) | 2721 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 2722 cp[1] = 2723 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 2724 XHCI_EPCTX_1_HID_SET(0) | 2725 XHCI_EPCTX_1_MAXB_SET(0); 2726 2727 if (xfertype != UE_ISOCHRONOUS) 2728 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 2729 2730 if (xfertype == UE_CONTROL) 2731 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 2732 else if (USB_IS_SS(speed)) 2733 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 2734 else 2735 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 2736 2737 xhci_setup_maxburst(pipe, cp); 2738 2739 switch (xfertype) { 2740 case UE_CONTROL: 2741 break; 2742 case UE_BULK: 2743 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 2744 break; 2745 case UE_INTERRUPT: 2746 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 2747 ival = pipe->up_interval; 2748 2749 ival = xhci_bival2ival(ival, speed); 2750 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 2751 break; 2752 case UE_ISOCHRONOUS: 2753 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 2754 ival = pipe->up_interval; 2755 2756 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 2757 if (speed == USB_SPEED_FULL) 2758 ival += 3; /* 1ms -> 125us */ 2759 ival--; 2760 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 2761 break; 2762 default: 2763 break; 2764 } 2765 DPRINTFN(4, "setting ival %u MaxBurst %#x", 2766 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 2767 2768 /* rewind TR dequeue pointer in xHC */ 2769 /* can't use xhci_ep_get_dci() yet? */ 2770 *(uint64_t *)(&cp[2]) = htole64( 2771 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 2772 XHCI_EPCTX_2_DCS_SET(1)); 2773 2774 cp[0] = htole32(cp[0]); 2775 cp[1] = htole32(cp[1]); 2776 cp[4] = htole32(cp[4]); 2777 2778 /* rewind TR dequeue pointer in driver */ 2779 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 2780 mutex_enter(&xr->xr_lock); 2781 xhci_host_dequeue(xr); 2782 mutex_exit(&xr->xr_lock); 2783 2784 /* sync input contexts before they are read from memory */ 2785 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2786 } 2787 2788 /* 2789 * Setup route string and roothub port of given device for slot context 2790 */ 2791 static void 2792 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 2793 { 2794 struct usbd_device *dev = pipe->up_dev; 2795 struct usbd_port *up = dev->ud_powersrc; 2796 struct usbd_device *hub; 2797 struct usbd_device *adev; 2798 uint8_t rhport = 0; 2799 uint32_t route = 0; 2800 2801 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2802 2803 /* Locate root hub port and Determine route string */ 2804 /* 4.3.3 route string does not include roothub port */ 2805 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2806 uint32_t dep; 2807 2808 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2809 hub, hub->ud_depth, hub->ud_powersrc, 2810 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2811 2812 if (hub->ud_powersrc == NULL) 2813 break; 2814 dep = hub->ud_depth; 2815 if (dep == 0) 2816 break; 2817 rhport = hub->ud_powersrc->up_portno; 2818 if (dep > USB_HUB_MAX_DEPTH) 2819 continue; 2820 2821 route |= 2822 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2823 << ((dep - 1) * 4); 2824 } 2825 route = route >> 4; 2826 DPRINTFN(4, "rhport %u Route %05x hub %p", rhport, route, hub, 0); 2827 2828 /* Locate port on upstream high speed hub */ 2829 for (adev = dev, hub = up->up_parent; 2830 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2831 adev = hub, hub = hub->ud_myhub) 2832 ; 2833 if (hub) { 2834 int p; 2835 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2836 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2837 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2838 goto found; 2839 } 2840 } 2841 panic("xhci_setup_route: cannot find HS port"); 2842 found: 2843 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2844 } else { 2845 dev->ud_myhsport = NULL; 2846 } 2847 2848 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 2849 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(rhport); 2850 } 2851 2852 /* 2853 * Setup whether device is hub, whether device uses MTT, and 2854 * TT informations if it uses MTT. 2855 */ 2856 static void 2857 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 2858 { 2859 struct usbd_device *dev = pipe->up_dev; 2860 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 2861 uint32_t speed = dev->ud_speed; 2862 uint8_t tthubslot, ttportnum; 2863 bool ishub; 2864 bool usemtt; 2865 2866 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2867 2868 /* 2869 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 2870 * tthubslot: 2871 * This is the slot ID of parent HS hub 2872 * if LS/FS device is connected && connected through HS hub. 2873 * This is 0 if device is not LS/FS device || 2874 * parent hub is not HS hub || 2875 * attached to root hub. 2876 * ttportnum: 2877 * This is the downstream facing port of parent HS hub 2878 * if LS/FS device is connected. 2879 * This is 0 if device is not LS/FS device || 2880 * parent hub is not HS hub || 2881 * attached to root hub. 2882 */ 2883 if (dev->ud_myhsport != NULL && 2884 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 2885 (dev->ud_myhub != NULL && 2886 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 2887 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 2888 ttportnum = dev->ud_myhsport->up_portno; 2889 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 2890 } else { 2891 ttportnum = 0; 2892 tthubslot = 0; 2893 } 2894 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 2895 dev->ud_myhsport, ttportnum, tthubslot, 0); 2896 2897 /* ishub is valid after reading UDESC_DEVICE */ 2898 ishub = (dd->bDeviceClass == UDCLASS_HUB); 2899 2900 /* dev->ud_hub is valid after reading UDESC_HUB */ 2901 if (ishub && dev->ud_hub) { 2902 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 2903 uint8_t ttt = 2904 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 2905 2906 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 2907 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 2908 DPRINTFN(4, "nports=%d ttt=%d", hd->bNbrPorts, ttt, 0, 0); 2909 } 2910 2911 #define IS_TTHUB(dd) \ 2912 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 2913 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 2914 2915 /* 2916 * MTT flag is set if 2917 * 1. this is HS hub && MTT is enabled 2918 * or 2919 * 2. this is not hub && this is LS or FS device && 2920 * MTT of parent HS hub (and its parent, too) is enabled 2921 */ 2922 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 2923 usemtt = true; 2924 else if (!ishub && 2925 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 2926 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 2927 (dev->ud_myhub != NULL && 2928 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 2929 dev->ud_myhsport != NULL && 2930 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 2931 usemtt = true; 2932 else 2933 usemtt = false; 2934 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 2935 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 2936 2937 #undef IS_TTHUB 2938 2939 cp[0] |= 2940 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 2941 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 2942 cp[2] |= 2943 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 2944 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 2945 } 2946 2947 /* set up params for periodic endpoint */ 2948 static void 2949 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 2950 { 2951 struct usbd_device *dev = pipe->up_dev; 2952 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2953 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2954 usbd_desc_iter_t iter; 2955 const usb_cdc_descriptor_t *cdcd; 2956 uint32_t maxb = 0; 2957 uint16_t mps = UGETW(ed->wMaxPacketSize); 2958 uint8_t speed = dev->ud_speed; 2959 uint8_t ep; 2960 2961 /* config desc is NULL when opening ep0 */ 2962 if (dev == NULL || dev->ud_cdesc == NULL) 2963 goto no_cdcd; 2964 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 2965 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 2966 if (cdcd == NULL) 2967 goto no_cdcd; 2968 usb_desc_iter_init(dev, &iter); 2969 iter.cur = (const void *)cdcd; 2970 2971 /* find endpoint_ss_comp desc for ep of this pipe */ 2972 for (ep = 0;;) { 2973 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 2974 if (cdcd == NULL) 2975 break; 2976 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 2977 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 2978 bEndpointAddress; 2979 if (UE_GET_ADDR(ep) == 2980 UE_GET_ADDR(ed->bEndpointAddress)) { 2981 cdcd = (const usb_cdc_descriptor_t *) 2982 usb_desc_iter_next(&iter); 2983 break; 2984 } 2985 ep = 0; 2986 } 2987 } 2988 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 2989 const usb_endpoint_ss_comp_descriptor_t * esscd = 2990 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 2991 maxb = esscd->bMaxBurst; 2992 } 2993 2994 no_cdcd: 2995 /* 6.2.3.4, 4.8.2.4 */ 2996 if (USB_IS_SS(speed)) { 2997 /* UBS 3.1 9.6.6 */ 2998 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 2999 /* UBS 3.1 9.6.7 */ 3000 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3001 #ifdef notyet 3002 if (xfertype == UE_ISOCHRONOUS) { 3003 } 3004 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3005 /* use ESIT */ 3006 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3007 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3008 3009 /* XXX if LEC = 1, set ESIT instead */ 3010 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3011 } else { 3012 /* use ival */ 3013 } 3014 #endif 3015 } else { 3016 /* UBS 2.0 9.6.6 */ 3017 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3018 3019 /* 6.2.3.4 */ 3020 if (speed == USB_SPEED_HIGH && 3021 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3022 maxb = UE_GET_TRANS(mps); 3023 } else { 3024 /* LS/FS or HS CTRL or HS BULK */ 3025 maxb = 0; 3026 } 3027 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3028 } 3029 } 3030 3031 /* 3032 * Convert endpoint bInterval value to endpoint context interval value 3033 * for Interrupt pipe. 3034 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3035 */ 3036 static uint32_t 3037 xhci_bival2ival(uint32_t ival, uint32_t speed) 3038 { 3039 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3040 int i; 3041 3042 /* 3043 * round ival down to "the nearest base 2 multiple of 3044 * bInterval * 8". 3045 * bInterval is at most 255 as its type is uByte. 3046 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3047 */ 3048 for (i = 10; i > 0; i--) { 3049 if ((ival * 8) >= (1 << i)) 3050 break; 3051 } 3052 ival = i; 3053 } else { 3054 /* Interval = bInterval-1 for SS/HS */ 3055 ival--; 3056 } 3057 3058 return ival; 3059 } 3060 3061 /* ----- */ 3062 3063 static void 3064 xhci_noop(struct usbd_pipe *pipe) 3065 { 3066 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3067 } 3068 3069 /* 3070 * Process root hub request. 3071 */ 3072 static int 3073 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3074 void *buf, int buflen) 3075 { 3076 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3077 usb_port_status_t ps; 3078 int l, totlen = 0; 3079 uint16_t len, value, index; 3080 int port, i; 3081 uint32_t v; 3082 3083 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3084 3085 if (sc->sc_dying) 3086 return -1; 3087 3088 len = UGETW(req->wLength); 3089 value = UGETW(req->wValue); 3090 index = UGETW(req->wIndex); 3091 3092 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 3093 req->bmRequestType | (req->bRequest << 8), value, index, len); 3094 3095 #define C(x,y) ((x) | ((y) << 8)) 3096 switch (C(req->bRequest, req->bmRequestType)) { 3097 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3098 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 3099 if (len == 0) 3100 break; 3101 switch (value) { 3102 case C(0, UDESC_DEVICE): { 3103 usb_device_descriptor_t devd; 3104 totlen = min(buflen, sizeof(devd)); 3105 memcpy(&devd, buf, totlen); 3106 USETW(devd.idVendor, sc->sc_id_vendor); 3107 memcpy(buf, &devd, totlen); 3108 break; 3109 } 3110 #define sd ((usb_string_descriptor_t *)buf) 3111 case C(1, UDESC_STRING): 3112 /* Vendor */ 3113 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3114 break; 3115 case C(2, UDESC_STRING): 3116 /* Product */ 3117 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3118 break; 3119 #undef sd 3120 default: 3121 /* default from usbroothub */ 3122 return buflen; 3123 } 3124 break; 3125 3126 /* Hub requests */ 3127 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3128 break; 3129 /* Clear Port Feature request */ 3130 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3131 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 3132 index, value, 0, 0); 3133 if (index < 1 || index > sc->sc_maxports) { 3134 return -1; 3135 } 3136 port = XHCI_PORTSC(index); 3137 v = xhci_op_read_4(sc, port); 3138 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3139 v &= ~XHCI_PS_CLEAR; 3140 switch (value) { 3141 case UHF_PORT_ENABLE: 3142 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3143 break; 3144 case UHF_PORT_SUSPEND: 3145 return -1; 3146 case UHF_PORT_POWER: 3147 break; 3148 case UHF_PORT_TEST: 3149 case UHF_PORT_INDICATOR: 3150 return -1; 3151 case UHF_C_PORT_CONNECTION: 3152 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3153 break; 3154 case UHF_C_PORT_ENABLE: 3155 case UHF_C_PORT_SUSPEND: 3156 case UHF_C_PORT_OVER_CURRENT: 3157 return -1; 3158 case UHF_C_BH_PORT_RESET: 3159 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3160 break; 3161 case UHF_C_PORT_RESET: 3162 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3163 break; 3164 case UHF_C_PORT_LINK_STATE: 3165 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3166 break; 3167 case UHF_C_PORT_CONFIG_ERROR: 3168 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3169 break; 3170 default: 3171 return -1; 3172 } 3173 break; 3174 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3175 if (len == 0) 3176 break; 3177 if ((value & 0xff) != 0) { 3178 return -1; 3179 } 3180 usb_hub_descriptor_t hubd; 3181 3182 totlen = min(buflen, sizeof(hubd)); 3183 memcpy(&hubd, buf, totlen); 3184 hubd.bNbrPorts = sc->sc_maxports; 3185 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3186 hubd.bPwrOn2PwrGood = 200; 3187 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 3188 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 3189 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3190 totlen = min(totlen, hubd.bDescLength); 3191 memcpy(buf, &hubd, totlen); 3192 break; 3193 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3194 if (len != 4) { 3195 return -1; 3196 } 3197 memset(buf, 0, len); /* ? XXX */ 3198 totlen = len; 3199 break; 3200 /* Get Port Status request */ 3201 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3202 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 3203 if (index < 1 || index > sc->sc_maxports) { 3204 return -1; 3205 } 3206 if (len != 4) { 3207 return -1; 3208 } 3209 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 3210 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 3211 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3212 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3213 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3214 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3215 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3216 if (v & XHCI_PS_PR) i |= UPS_RESET; 3217 if (v & XHCI_PS_PP) { 3218 if (i & UPS_OTHER_SPEED) 3219 i |= UPS_PORT_POWER_SS; 3220 else 3221 i |= UPS_PORT_POWER; 3222 } 3223 if (i & UPS_OTHER_SPEED) 3224 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3225 if (sc->sc_vendor_port_status) 3226 i = sc->sc_vendor_port_status(sc, v, i); 3227 USETW(ps.wPortStatus, i); 3228 i = 0; 3229 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3230 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3231 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3232 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3233 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3234 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3235 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3236 USETW(ps.wPortChange, i); 3237 totlen = min(len, sizeof(ps)); 3238 memcpy(buf, &ps, totlen); 3239 break; 3240 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3241 return -1; 3242 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3243 break; 3244 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3245 break; 3246 /* Set Port Feature request */ 3247 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3248 int optval = (index >> 8) & 0xff; 3249 index &= 0xff; 3250 if (index < 1 || index > sc->sc_maxports) { 3251 return -1; 3252 } 3253 port = XHCI_PORTSC(index); 3254 v = xhci_op_read_4(sc, port); 3255 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3256 v &= ~XHCI_PS_CLEAR; 3257 switch (value) { 3258 case UHF_PORT_ENABLE: 3259 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3260 break; 3261 case UHF_PORT_SUSPEND: 3262 /* XXX suspend */ 3263 break; 3264 case UHF_PORT_RESET: 3265 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3266 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3267 /* Wait for reset to complete. */ 3268 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3269 if (sc->sc_dying) { 3270 return -1; 3271 } 3272 v = xhci_op_read_4(sc, port); 3273 if (v & XHCI_PS_PR) { 3274 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3275 usb_delay_ms(&sc->sc_bus, 10); 3276 /* XXX */ 3277 } 3278 break; 3279 case UHF_PORT_POWER: 3280 /* XXX power control */ 3281 break; 3282 /* XXX more */ 3283 case UHF_C_PORT_RESET: 3284 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3285 break; 3286 case UHF_PORT_U1_TIMEOUT: 3287 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3288 return -1; 3289 } 3290 port = XHCI_PORTPMSC(index); 3291 v = xhci_op_read_4(sc, port); 3292 v &= ~XHCI_PM3_U1TO_SET(0xff); 3293 v |= XHCI_PM3_U1TO_SET(optval); 3294 xhci_op_write_4(sc, port, v); 3295 break; 3296 case UHF_PORT_U2_TIMEOUT: 3297 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3298 return -1; 3299 } 3300 port = XHCI_PORTPMSC(index); 3301 v = xhci_op_read_4(sc, port); 3302 v &= ~XHCI_PM3_U2TO_SET(0xff); 3303 v |= XHCI_PM3_U2TO_SET(optval); 3304 xhci_op_write_4(sc, port, v); 3305 break; 3306 default: 3307 return -1; 3308 } 3309 } 3310 break; 3311 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3312 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3313 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3314 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3315 break; 3316 default: 3317 /* default from usbroothub */ 3318 return buflen; 3319 } 3320 3321 return totlen; 3322 } 3323 3324 /* root hub interrupt */ 3325 3326 static usbd_status 3327 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3328 { 3329 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3330 usbd_status err; 3331 3332 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3333 3334 /* Insert last in queue. */ 3335 mutex_enter(&sc->sc_lock); 3336 err = usb_insert_transfer(xfer); 3337 mutex_exit(&sc->sc_lock); 3338 if (err) 3339 return err; 3340 3341 /* Pipe isn't running, start first */ 3342 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3343 } 3344 3345 /* Wait for roothub port status/change */ 3346 static usbd_status 3347 xhci_root_intr_start(struct usbd_xfer *xfer) 3348 { 3349 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3350 3351 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3352 3353 if (sc->sc_dying) 3354 return USBD_IOERROR; 3355 3356 mutex_enter(&sc->sc_lock); 3357 sc->sc_intrxfer = xfer; 3358 mutex_exit(&sc->sc_lock); 3359 3360 return USBD_IN_PROGRESS; 3361 } 3362 3363 static void 3364 xhci_root_intr_abort(struct usbd_xfer *xfer) 3365 { 3366 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3367 3368 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3369 3370 KASSERT(mutex_owned(&sc->sc_lock)); 3371 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3372 3373 sc->sc_intrxfer = NULL; 3374 3375 xfer->ux_status = USBD_CANCELLED; 3376 usb_transfer_complete(xfer); 3377 } 3378 3379 static void 3380 xhci_root_intr_close(struct usbd_pipe *pipe) 3381 { 3382 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3383 3384 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3385 3386 KASSERT(mutex_owned(&sc->sc_lock)); 3387 3388 sc->sc_intrxfer = NULL; 3389 } 3390 3391 static void 3392 xhci_root_intr_done(struct usbd_xfer *xfer) 3393 { 3394 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3395 3396 } 3397 3398 /* -------------- */ 3399 /* device control */ 3400 3401 static usbd_status 3402 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3403 { 3404 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3405 usbd_status err; 3406 3407 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3408 3409 /* Insert last in queue. */ 3410 mutex_enter(&sc->sc_lock); 3411 err = usb_insert_transfer(xfer); 3412 mutex_exit(&sc->sc_lock); 3413 if (err) 3414 return err; 3415 3416 /* Pipe isn't running, start first */ 3417 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3418 } 3419 3420 static usbd_status 3421 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3422 { 3423 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3424 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3425 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3426 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3427 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3428 usb_device_request_t * const req = &xfer->ux_request; 3429 const int isread = usbd_xfer_isread(xfer); 3430 const uint32_t len = UGETW(req->wLength); 3431 usb_dma_t * const dma = &xfer->ux_dmabuf; 3432 uint64_t parameter; 3433 uint32_t status; 3434 uint32_t control; 3435 u_int i; 3436 3437 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3438 DPRINTFN(12, "req: %04x %04x %04x %04x", 3439 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3440 UGETW(req->wIndex), UGETW(req->wLength)); 3441 3442 /* we rely on the bottom bits for extra info */ 3443 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 3444 3445 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3446 3447 i = 0; 3448 3449 /* setup phase */ 3450 memcpy(¶meter, req, sizeof(*req)); 3451 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3452 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3453 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3454 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3455 XHCI_TRB_3_IDT_BIT; 3456 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3457 3458 if (len != 0) { 3459 /* data phase */ 3460 parameter = DMAADDR(dma, 0); 3461 KASSERT(len <= 0x10000); 3462 status = XHCI_TRB_2_IRQ_SET(0) | 3463 XHCI_TRB_2_TDSZ_SET(1) | 3464 XHCI_TRB_2_BYTES_SET(len); 3465 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3466 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3467 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3468 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3469 3470 parameter = (uintptr_t)xfer | 0x3; 3471 status = XHCI_TRB_2_IRQ_SET(0); 3472 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3473 XHCI_TRB_3_IOC_BIT; 3474 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3475 } 3476 3477 parameter = 0; 3478 status = XHCI_TRB_2_IRQ_SET(0); 3479 /* the status stage has inverted direction */ 3480 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3481 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3482 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3483 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3484 3485 parameter = (uintptr_t)xfer | 0x0; 3486 status = XHCI_TRB_2_IRQ_SET(0); 3487 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3488 XHCI_TRB_3_IOC_BIT; 3489 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3490 3491 mutex_enter(&tr->xr_lock); 3492 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3493 mutex_exit(&tr->xr_lock); 3494 3495 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3496 3497 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3498 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3499 xhci_timeout, xfer); 3500 } 3501 3502 return USBD_IN_PROGRESS; 3503 } 3504 3505 static void 3506 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3507 { 3508 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3509 usb_device_request_t *req = &xfer->ux_request; 3510 int len = UGETW(req->wLength); 3511 int rd = req->bmRequestType & UT_READ; 3512 3513 if (len) 3514 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3515 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3516 } 3517 3518 static void 3519 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3520 { 3521 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3522 3523 xhci_abort_xfer(xfer, USBD_CANCELLED); 3524 } 3525 3526 static void 3527 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3528 { 3529 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3530 3531 xhci_close_pipe(pipe); 3532 } 3533 3534 /* ------------------ */ 3535 /* device isochronous */ 3536 3537 /* ----------- */ 3538 /* device bulk */ 3539 3540 static usbd_status 3541 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3542 { 3543 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3544 usbd_status err; 3545 3546 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3547 3548 /* Insert last in queue. */ 3549 mutex_enter(&sc->sc_lock); 3550 err = usb_insert_transfer(xfer); 3551 mutex_exit(&sc->sc_lock); 3552 if (err) 3553 return err; 3554 3555 /* 3556 * Pipe isn't running (otherwise err would be USBD_INPROG), 3557 * so start it first. 3558 */ 3559 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3560 } 3561 3562 static usbd_status 3563 xhci_device_bulk_start(struct usbd_xfer *xfer) 3564 { 3565 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3566 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3567 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3568 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3569 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3570 const uint32_t len = xfer->ux_length; 3571 usb_dma_t * const dma = &xfer->ux_dmabuf; 3572 uint64_t parameter; 3573 uint32_t status; 3574 uint32_t control; 3575 u_int i = 0; 3576 3577 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3578 3579 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3580 3581 if (sc->sc_dying) 3582 return USBD_IOERROR; 3583 3584 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3585 3586 parameter = DMAADDR(dma, 0); 3587 /* 3588 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3589 * If the user supplied buffer crosses such a boundary then 2 3590 * (or more) TRB should be used. 3591 * If multiple TRB are used the td_size field must be set correctly. 3592 * For v1.0 devices (like ivy bridge) this is the number of usb data 3593 * blocks needed to complete the transfer. 3594 * Setting it to 1 in the last TRB causes an extra zero-length 3595 * data block be sent. 3596 * The earlier documentation differs, I don't know how it behaves. 3597 */ 3598 KASSERT(len <= 0x10000); 3599 status = XHCI_TRB_2_IRQ_SET(0) | 3600 XHCI_TRB_2_TDSZ_SET(1) | 3601 XHCI_TRB_2_BYTES_SET(len); 3602 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3603 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3604 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3605 3606 mutex_enter(&tr->xr_lock); 3607 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3608 mutex_exit(&tr->xr_lock); 3609 3610 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3611 3612 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3613 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3614 xhci_timeout, xfer); 3615 } 3616 3617 return USBD_IN_PROGRESS; 3618 } 3619 3620 static void 3621 xhci_device_bulk_done(struct usbd_xfer *xfer) 3622 { 3623 #ifdef USB_DEBUG 3624 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3625 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3626 #endif 3627 const int isread = usbd_xfer_isread(xfer); 3628 3629 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3630 3631 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3632 3633 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3634 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3635 } 3636 3637 static void 3638 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3639 { 3640 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3641 3642 xhci_abort_xfer(xfer, USBD_CANCELLED); 3643 } 3644 3645 static void 3646 xhci_device_bulk_close(struct usbd_pipe *pipe) 3647 { 3648 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3649 3650 xhci_close_pipe(pipe); 3651 } 3652 3653 /* ---------------- */ 3654 /* device interrupt */ 3655 3656 static usbd_status 3657 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3658 { 3659 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3660 usbd_status err; 3661 3662 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3663 3664 /* Insert last in queue. */ 3665 mutex_enter(&sc->sc_lock); 3666 err = usb_insert_transfer(xfer); 3667 mutex_exit(&sc->sc_lock); 3668 if (err) 3669 return err; 3670 3671 /* 3672 * Pipe isn't running (otherwise err would be USBD_INPROG), 3673 * so start it first. 3674 */ 3675 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3676 } 3677 3678 static usbd_status 3679 xhci_device_intr_start(struct usbd_xfer *xfer) 3680 { 3681 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3682 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3683 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3684 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3685 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3686 const uint32_t len = xfer->ux_length; 3687 usb_dma_t * const dma = &xfer->ux_dmabuf; 3688 uint64_t parameter; 3689 uint32_t status; 3690 uint32_t control; 3691 u_int i = 0; 3692 3693 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3694 3695 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3696 3697 if (sc->sc_dying) 3698 return USBD_IOERROR; 3699 3700 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3701 3702 parameter = DMAADDR(dma, 0); 3703 KASSERT(len <= 0x10000); 3704 status = XHCI_TRB_2_IRQ_SET(0) | 3705 XHCI_TRB_2_TDSZ_SET(1) | 3706 XHCI_TRB_2_BYTES_SET(len); 3707 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3708 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3709 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3710 3711 mutex_enter(&tr->xr_lock); 3712 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3713 mutex_exit(&tr->xr_lock); 3714 3715 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3716 3717 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3718 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3719 xhci_timeout, xfer); 3720 } 3721 3722 return USBD_IN_PROGRESS; 3723 } 3724 3725 static void 3726 xhci_device_intr_done(struct usbd_xfer *xfer) 3727 { 3728 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3729 #ifdef USB_DEBUG 3730 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3731 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3732 #endif 3733 const int isread = usbd_xfer_isread(xfer); 3734 3735 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3736 3737 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3738 3739 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3740 3741 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3742 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3743 } 3744 3745 static void 3746 xhci_device_intr_abort(struct usbd_xfer *xfer) 3747 { 3748 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3749 3750 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3751 3752 KASSERT(mutex_owned(&sc->sc_lock)); 3753 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3754 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3755 xhci_abort_xfer(xfer, USBD_CANCELLED); 3756 } 3757 3758 static void 3759 xhci_device_intr_close(struct usbd_pipe *pipe) 3760 { 3761 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3762 3763 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3764 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3765 3766 xhci_close_pipe(pipe); 3767 } 3768 3769 /* ------------ */ 3770 3771 static void 3772 xhci_timeout(void *addr) 3773 { 3774 struct xhci_xfer * const xx = addr; 3775 struct usbd_xfer * const xfer = &xx->xx_xfer; 3776 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3777 3778 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3779 3780 if (sc->sc_dying) { 3781 return; 3782 } 3783 3784 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 3785 USB_TASKQ_MPSAFE); 3786 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 3787 USB_TASKQ_HC); 3788 } 3789 3790 static void 3791 xhci_timeout_task(void *addr) 3792 { 3793 struct usbd_xfer * const xfer = addr; 3794 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3795 3796 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3797 3798 mutex_enter(&sc->sc_lock); 3799 #if 0 3800 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3801 #else 3802 xfer->ux_status = USBD_TIMEOUT; 3803 usb_transfer_complete(xfer); 3804 #endif 3805 mutex_exit(&sc->sc_lock); 3806 } 3807
Indexes created Mon Sep 22 21:09:42 GMT 2025