xhci.c revision 1.57
1 /* $NetBSD: xhci.c,v 1.57 2016/06/10 15:19:27 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.57 2016/06/10 15:19:27 skrll Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static void xhci_host_dequeue(struct xhci_ring * const); 146 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 147 148 static usbd_status xhci_do_command(struct xhci_softc * const, 149 struct xhci_trb * const, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 153 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 154 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 155 static usbd_status xhci_enable_slot(struct xhci_softc * const, 156 uint8_t * const); 157 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 158 static usbd_status xhci_address_device(struct xhci_softc * const, 159 uint64_t, uint8_t, bool); 160 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 161 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 162 struct xhci_slot * const, u_int); 163 static usbd_status xhci_ring_init(struct xhci_softc * const, 164 struct xhci_ring * const, size_t, size_t); 165 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 166 167 static void xhci_setup_ctx(struct usbd_pipe *); 168 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 169 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 170 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 171 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 172 173 static void xhci_noop(struct usbd_pipe *); 174 175 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 176 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 177 static void xhci_root_intr_abort(struct usbd_xfer *); 178 static void xhci_root_intr_close(struct usbd_pipe *); 179 static void xhci_root_intr_done(struct usbd_xfer *); 180 181 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 182 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 183 static void xhci_device_ctrl_abort(struct usbd_xfer *); 184 static void xhci_device_ctrl_close(struct usbd_pipe *); 185 static void xhci_device_ctrl_done(struct usbd_xfer *); 186 187 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 188 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 189 static void xhci_device_intr_abort(struct usbd_xfer *); 190 static void xhci_device_intr_close(struct usbd_pipe *); 191 static void xhci_device_intr_done(struct usbd_xfer *); 192 193 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 194 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 195 static void xhci_device_bulk_abort(struct usbd_xfer *); 196 static void xhci_device_bulk_close(struct usbd_pipe *); 197 static void xhci_device_bulk_done(struct usbd_xfer *); 198 199 static void xhci_timeout(void *); 200 static void xhci_timeout_task(void *); 201 202 static const struct usbd_bus_methods xhci_bus_methods = { 203 .ubm_open = xhci_open, 204 .ubm_softint = xhci_softintr, 205 .ubm_dopoll = xhci_poll, 206 .ubm_allocx = xhci_allocx, 207 .ubm_freex = xhci_freex, 208 .ubm_getlock = xhci_get_lock, 209 .ubm_newdev = xhci_new_device, 210 .ubm_rhctrl = xhci_roothub_ctrl, 211 }; 212 213 static const struct usbd_pipe_methods xhci_root_intr_methods = { 214 .upm_transfer = xhci_root_intr_transfer, 215 .upm_start = xhci_root_intr_start, 216 .upm_abort = xhci_root_intr_abort, 217 .upm_close = xhci_root_intr_close, 218 .upm_cleartoggle = xhci_noop, 219 .upm_done = xhci_root_intr_done, 220 }; 221 222 223 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 224 .upm_transfer = xhci_device_ctrl_transfer, 225 .upm_start = xhci_device_ctrl_start, 226 .upm_abort = xhci_device_ctrl_abort, 227 .upm_close = xhci_device_ctrl_close, 228 .upm_cleartoggle = xhci_noop, 229 .upm_done = xhci_device_ctrl_done, 230 }; 231 232 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 233 .upm_cleartoggle = xhci_noop, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 237 .upm_transfer = xhci_device_bulk_transfer, 238 .upm_start = xhci_device_bulk_start, 239 .upm_abort = xhci_device_bulk_abort, 240 .upm_close = xhci_device_bulk_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_bulk_done, 243 }; 244 245 static const struct usbd_pipe_methods xhci_device_intr_methods = { 246 .upm_transfer = xhci_device_intr_transfer, 247 .upm_start = xhci_device_intr_start, 248 .upm_abort = xhci_device_intr_abort, 249 .upm_close = xhci_device_intr_close, 250 .upm_cleartoggle = xhci_noop, 251 .upm_done = xhci_device_intr_done, 252 }; 253 254 static inline uint32_t 255 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 256 { 257 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 258 } 259 260 static inline uint32_t 261 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 262 { 263 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 264 } 265 266 static inline void 267 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 268 uint32_t value) 269 { 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 271 } 272 273 #if 0 /* unused */ 274 static inline void 275 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 276 uint32_t value) 277 { 278 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 279 } 280 #endif /* unused */ 281 282 static inline uint32_t 283 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 284 { 285 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 286 } 287 288 static inline uint32_t 289 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 290 { 291 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 292 } 293 294 static inline void 295 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 296 uint32_t value) 297 { 298 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 299 } 300 301 static inline uint64_t 302 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 303 { 304 uint64_t value; 305 306 if (sc->sc_ac64) { 307 #ifdef XHCI_USE_BUS_SPACE_8 308 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 309 #else 310 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 311 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 312 offset + 4) << 32; 313 #endif 314 } else { 315 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 316 } 317 318 return value; 319 } 320 321 static inline void 322 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 336 } 337 } 338 339 static inline uint32_t 340 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 341 { 342 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 343 } 344 345 static inline void 346 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 347 uint32_t value) 348 { 349 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 350 } 351 352 #if 0 /* unused */ 353 static inline uint64_t 354 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 355 { 356 uint64_t value; 357 358 if (sc->sc_ac64) { 359 #ifdef XHCI_USE_BUS_SPACE_8 360 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 361 #else 362 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 363 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 364 offset + 4) << 32; 365 #endif 366 } else { 367 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 368 } 369 370 return value; 371 } 372 #endif /* unused */ 373 374 static inline void 375 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 376 uint64_t value) 377 { 378 if (sc->sc_ac64) { 379 #ifdef XHCI_USE_BUS_SPACE_8 380 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 381 #else 382 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 383 (value >> 0) & 0xffffffff); 384 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 385 (value >> 32) & 0xffffffff); 386 #endif 387 } else { 388 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 389 } 390 } 391 392 #if 0 /* unused */ 393 static inline uint32_t 394 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 395 { 396 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 397 } 398 #endif /* unused */ 399 400 static inline void 401 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 402 uint32_t value) 403 { 404 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 405 } 406 407 /* --- */ 408 409 static inline uint8_t 410 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 411 { 412 u_int eptype = 0; 413 414 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 415 case UE_CONTROL: 416 eptype = 0x0; 417 break; 418 case UE_ISOCHRONOUS: 419 eptype = 0x1; 420 break; 421 case UE_BULK: 422 eptype = 0x2; 423 break; 424 case UE_INTERRUPT: 425 eptype = 0x3; 426 break; 427 } 428 429 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 430 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 431 return eptype | 0x4; 432 else 433 return eptype; 434 } 435 436 static u_int 437 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 438 { 439 /* xHCI 1.0 section 4.5.1 */ 440 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 441 u_int in = 0; 442 443 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 444 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 445 in = 1; 446 447 return epaddr * 2 + in; 448 } 449 450 static inline u_int 451 xhci_dci_to_ici(const u_int i) 452 { 453 return i + 1; 454 } 455 456 static inline void * 457 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 458 const u_int dci) 459 { 460 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 461 } 462 463 #if 0 /* unused */ 464 static inline bus_addr_t 465 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 466 const u_int dci) 467 { 468 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 469 } 470 #endif /* unused */ 471 472 static inline void * 473 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline bus_addr_t 480 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 481 const u_int ici) 482 { 483 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 484 } 485 486 static inline struct xhci_trb * 487 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 488 { 489 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 490 } 491 492 static inline bus_addr_t 493 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 494 { 495 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 496 } 497 498 static inline void 499 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 500 uint32_t control) 501 { 502 trb->trb_0 = htole64(parameter); 503 trb->trb_2 = htole32(status); 504 trb->trb_3 = htole32(control); 505 } 506 507 static int 508 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 509 { 510 /* base address of TRBs */ 511 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 512 513 /* trb_0 range sanity check */ 514 if (trb_0 == 0 || trb_0 < trbp || 515 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 516 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 517 return 1; 518 } 519 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 520 return 0; 521 } 522 523 /* --- */ 524 525 void 526 xhci_childdet(device_t self, device_t child) 527 { 528 struct xhci_softc * const sc = device_private(self); 529 530 KASSERT(sc->sc_child == child); 531 if (child == sc->sc_child) 532 sc->sc_child = NULL; 533 } 534 535 int 536 xhci_detach(struct xhci_softc *sc, int flags) 537 { 538 int rv = 0; 539 540 if (sc->sc_child != NULL) 541 rv = config_detach(sc->sc_child, flags); 542 543 if (rv != 0) 544 return rv; 545 546 /* XXX unconfigure/free slots */ 547 548 /* verify: */ 549 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 550 xhci_op_write_4(sc, XHCI_USBCMD, 0); 551 /* do we need to wait for stop? */ 552 553 xhci_op_write_8(sc, XHCI_CRCR, 0); 554 xhci_ring_free(sc, &sc->sc_cr); 555 cv_destroy(&sc->sc_command_cv); 556 557 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 558 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 559 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 560 xhci_ring_free(sc, &sc->sc_er); 561 562 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 563 564 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 565 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 566 567 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 568 569 mutex_destroy(&sc->sc_lock); 570 mutex_destroy(&sc->sc_intr_lock); 571 572 pool_cache_destroy(sc->sc_xferpool); 573 574 return rv; 575 } 576 577 int 578 xhci_activate(device_t self, enum devact act) 579 { 580 struct xhci_softc * const sc = device_private(self); 581 582 switch (act) { 583 case DVACT_DEACTIVATE: 584 sc->sc_dying = true; 585 return 0; 586 default: 587 return EOPNOTSUPP; 588 } 589 } 590 591 bool 592 xhci_suspend(device_t dv, const pmf_qual_t *qual) 593 { 594 return false; 595 } 596 597 bool 598 xhci_resume(device_t dv, const pmf_qual_t *qual) 599 { 600 return false; 601 } 602 603 bool 604 xhci_shutdown(device_t self, int flags) 605 { 606 return false; 607 } 608 609 static int 610 xhci_hc_reset(struct xhci_softc * const sc) 611 { 612 uint32_t usbcmd, usbsts; 613 int i; 614 615 /* Check controller not ready */ 616 for (i = 0; i < XHCI_WAIT_CNR; i++) { 617 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 618 if ((usbsts & XHCI_STS_CNR) == 0) 619 break; 620 usb_delay_ms(&sc->sc_bus, 1); 621 } 622 if (i >= XHCI_WAIT_CNR) { 623 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 624 return EIO; 625 } 626 627 /* Halt controller */ 628 usbcmd = 0; 629 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 630 usb_delay_ms(&sc->sc_bus, 1); 631 632 /* Reset controller */ 633 usbcmd = XHCI_CMD_HCRST; 634 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 635 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 636 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 637 if ((usbcmd & XHCI_CMD_HCRST) == 0) 638 break; 639 usb_delay_ms(&sc->sc_bus, 1); 640 } 641 if (i >= XHCI_WAIT_HCRST) { 642 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 643 return EIO; 644 } 645 646 /* Check controller not ready */ 647 for (i = 0; i < XHCI_WAIT_CNR; i++) { 648 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 649 if ((usbsts & XHCI_STS_CNR) == 0) 650 break; 651 usb_delay_ms(&sc->sc_bus, 1); 652 } 653 if (i >= XHCI_WAIT_CNR) { 654 aprint_error_dev(sc->sc_dev, 655 "controller not ready timeout after reset\n"); 656 return EIO; 657 } 658 659 return 0; 660 } 661 662 663 static void 664 hexdump(const char *msg, const void *base, size_t len) 665 { 666 #if 0 667 size_t cnt; 668 const uint32_t *p; 669 extern paddr_t vtophys(vaddr_t); 670 671 p = base; 672 cnt = 0; 673 674 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 675 (void *)vtophys((vaddr_t)base)); 676 677 while (cnt < len) { 678 if (cnt % 16 == 0) 679 printf("%p: ", p); 680 else if (cnt % 8 == 0) 681 printf(" |"); 682 printf(" %08x", *p++); 683 cnt += 4; 684 if (cnt % 16 == 0) 685 printf("\n"); 686 } 687 if (cnt % 16 != 0) 688 printf("\n"); 689 #endif 690 } 691 692 /* Process extended capabilities */ 693 static void 694 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 695 { 696 uint32_t ecp, ecr; 697 698 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 699 700 ecp = XHCI_HCC_XECP(hcc) * 4; 701 while (ecp != 0) { 702 ecr = xhci_read_4(sc, ecp); 703 aprint_debug_dev(sc->sc_dev, "ECR %x: %08x\n", ecp, ecr); 704 switch (XHCI_XECP_ID(ecr)) { 705 case XHCI_ID_PROTOCOLS: { 706 uint32_t w4, w8, wc; 707 uint16_t w2; 708 w2 = (ecr >> 16) & 0xffff; 709 w4 = xhci_read_4(sc, ecp + 4); 710 w8 = xhci_read_4(sc, ecp + 8); 711 wc = xhci_read_4(sc, ecp + 0xc); 712 aprint_debug_dev(sc->sc_dev, 713 " SP: %08x %08x %08x %08x\n", ecr, w4, w8, wc); 714 /* unused */ 715 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0300) { 716 sc->sc_ss_port_start = (w8 >> 0) & 0xff;; 717 sc->sc_ss_port_count = (w8 >> 8) & 0xff;; 718 } 719 if (w4 == 0x20425355 && (w2 & 0xff00) == 0x0200) { 720 sc->sc_hs_port_start = (w8 >> 0) & 0xff; 721 sc->sc_hs_port_count = (w8 >> 8) & 0xff; 722 } 723 break; 724 } 725 case XHCI_ID_USB_LEGACY: { 726 uint8_t bios_sem; 727 728 /* Take host controller ownership from BIOS */ 729 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 730 if (bios_sem) { 731 /* sets xHCI to be owned by OS */ 732 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 733 aprint_debug_dev(sc->sc_dev, 734 "waiting for BIOS to give up control\n"); 735 for (int i = 0; i < 5000; i++) { 736 bios_sem = xhci_read_1(sc, ecp + 737 XHCI_XECP_BIOS_SEM); 738 if (bios_sem == 0) 739 break; 740 DELAY(1000); 741 } 742 if (bios_sem) { 743 aprint_error_dev(sc->sc_dev, 744 "timed out waiting for BIOS\n"); 745 } 746 } 747 break; 748 } 749 default: 750 break; 751 } 752 ecr = xhci_read_4(sc, ecp); 753 if (XHCI_XECP_NEXT(ecr) == 0) { 754 ecp = 0; 755 } else { 756 ecp += XHCI_XECP_NEXT(ecr) * 4; 757 } 758 } 759 } 760 761 #define XHCI_HCCPREV1_BITS \ 762 "\177\020" /* New bitmask */ \ 763 "f\020\020XECP\0" \ 764 "f\014\4MAXPSA\0" \ 765 "b\013CFC\0" \ 766 "b\012SEC\0" \ 767 "b\011SBD\0" \ 768 "b\010FSE\0" \ 769 "b\7NSS\0" \ 770 "b\6LTC\0" \ 771 "b\5LHRC\0" \ 772 "b\4PIND\0" \ 773 "b\3PPC\0" \ 774 "b\2CZC\0" \ 775 "b\1BNC\0" \ 776 "b\0AC64\0" \ 777 "\0" 778 #define XHCI_HCCV1_x_BITS \ 779 "\177\020" /* New bitmask */ \ 780 "f\020\020XECP\0" \ 781 "f\014\4MAXPSA\0" \ 782 "b\013CFC\0" \ 783 "b\012SEC\0" \ 784 "b\011SPC\0" \ 785 "b\010PAE\0" \ 786 "b\7NSS\0" \ 787 "b\6LTC\0" \ 788 "b\5LHRC\0" \ 789 "b\4PIND\0" \ 790 "b\3PPC\0" \ 791 "b\2CSZ\0" \ 792 "b\1BNC\0" \ 793 "b\0AC64\0" \ 794 "\0" 795 796 int 797 xhci_init(struct xhci_softc *sc) 798 { 799 bus_size_t bsz; 800 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 801 uint32_t pagesize, config; 802 int i = 0; 803 uint16_t hciversion; 804 uint8_t caplength; 805 806 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 807 808 sc->sc_bus.ub_revision = USBREV_3_0; 809 sc->sc_bus.ub_usedma = true; 810 811 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 812 caplength = XHCI_CAP_CAPLENGTH(cap); 813 hciversion = XHCI_CAP_HCIVERSION(cap); 814 815 if (hciversion < XHCI_HCIVERSION_0_96 || 816 hciversion > XHCI_HCIVERSION_1_0) { 817 aprint_normal_dev(sc->sc_dev, 818 "xHCI version %x.%x not known to be supported\n", 819 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 820 } else { 821 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 822 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 823 } 824 825 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 826 &sc->sc_cbh) != 0) { 827 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 828 return ENOMEM; 829 } 830 831 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 832 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 833 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 834 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 835 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 836 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 837 aprint_debug_dev(sc->sc_dev, 838 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 839 840 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 841 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 842 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 843 844 char sbuf[128]; 845 if (hciversion < XHCI_HCIVERSION_1_0) 846 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 847 else 848 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 849 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 850 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 851 852 /* print PSI and take ownership from BIOS */ 853 xhci_ecp(sc, hcc); 854 855 bsz = XHCI_PORTSC(sc->sc_maxports + 1); 856 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 857 &sc->sc_obh) != 0) { 858 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 859 return ENOMEM; 860 } 861 862 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 863 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 864 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 865 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 866 return ENOMEM; 867 } 868 869 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 870 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 871 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 872 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 873 return ENOMEM; 874 } 875 876 int rv; 877 rv = xhci_hc_reset(sc); 878 if (rv != 0) { 879 return rv; 880 } 881 882 if (sc->sc_vendor_init) 883 sc->sc_vendor_init(sc); 884 885 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 886 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 887 pagesize = ffs(pagesize); 888 if (pagesize == 0) { 889 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 890 return EIO; 891 } 892 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 893 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 894 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 895 (uint32_t)sc->sc_maxslots); 896 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 897 898 usbd_status err; 899 900 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 901 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 902 if (sc->sc_maxspbuf != 0) { 903 err = usb_allocmem(&sc->sc_bus, 904 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 905 &sc->sc_spbufarray_dma); 906 if (err) { 907 aprint_error_dev(sc->sc_dev, 908 "spbufarray init fail, err %d\n", err); 909 return ENOMEM; 910 } 911 912 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 913 sc->sc_maxspbuf, KM_SLEEP); 914 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 915 for (i = 0; i < sc->sc_maxspbuf; i++) { 916 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 917 /* allocate contexts */ 918 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 919 sc->sc_pgsz, dma); 920 if (err) { 921 aprint_error_dev(sc->sc_dev, 922 "spbufarray_dma init fail, err %d\n", err); 923 rv = ENOMEM; 924 goto bad1; 925 } 926 spbufarray[i] = htole64(DMAADDR(dma, 0)); 927 usb_syncmem(dma, 0, sc->sc_pgsz, 928 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 929 } 930 931 usb_syncmem(&sc->sc_spbufarray_dma, 0, 932 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 933 } 934 935 config = xhci_op_read_4(sc, XHCI_CONFIG); 936 config &= ~0xFF; 937 config |= sc->sc_maxslots & 0xFF; 938 xhci_op_write_4(sc, XHCI_CONFIG, config); 939 940 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 941 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 942 if (err) { 943 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 944 err); 945 rv = ENOMEM; 946 goto bad1; 947 } 948 949 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 950 XHCI_EVENT_RING_SEGMENTS_ALIGN); 951 if (err) { 952 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 953 err); 954 rv = ENOMEM; 955 goto bad2; 956 } 957 958 usb_dma_t *dma; 959 size_t size; 960 size_t align; 961 962 dma = &sc->sc_eventst_dma; 963 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 964 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 965 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 966 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 967 err = usb_allocmem(&sc->sc_bus, size, align, dma); 968 if (err) { 969 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 970 err); 971 rv = ENOMEM; 972 goto bad3; 973 } 974 975 memset(KERNADDR(dma, 0), 0, size); 976 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 977 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 978 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 979 KERNADDR(&sc->sc_eventst_dma, 0), 980 sc->sc_eventst_dma.udma_block->size); 981 982 dma = &sc->sc_dcbaa_dma; 983 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 984 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 985 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 986 err = usb_allocmem(&sc->sc_bus, size, align, dma); 987 if (err) { 988 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 989 rv = ENOMEM; 990 goto bad4; 991 } 992 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 993 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 994 KERNADDR(&sc->sc_dcbaa_dma, 0), 995 sc->sc_dcbaa_dma.udma_block->size); 996 997 memset(KERNADDR(dma, 0), 0, size); 998 if (sc->sc_maxspbuf != 0) { 999 /* 1000 * DCBA entry 0 hold the scratchbuf array pointer. 1001 */ 1002 *(uint64_t *)KERNADDR(dma, 0) = 1003 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1004 } 1005 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1006 1007 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1008 KM_SLEEP); 1009 if (sc->sc_slots == NULL) { 1010 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1011 rv = ENOMEM; 1012 goto bad; 1013 } 1014 1015 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1016 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1017 if (sc->sc_xferpool == NULL) { 1018 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1019 err); 1020 rv = ENOMEM; 1021 goto bad; 1022 } 1023 1024 cv_init(&sc->sc_command_cv, "xhcicmd"); 1025 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1026 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1027 1028 /* Set up the bus struct. */ 1029 sc->sc_bus.ub_methods = &xhci_bus_methods; 1030 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 1031 1032 struct xhci_erste *erst; 1033 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1034 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1035 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1036 erst[0].erste_3 = htole32(0); 1037 usb_syncmem(&sc->sc_eventst_dma, 0, 1038 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1039 1040 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1041 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1042 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1043 XHCI_ERDP_LO_BUSY); 1044 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1045 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1046 sc->sc_cr.xr_cs); 1047 1048 #if 0 1049 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1050 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1051 #endif 1052 1053 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1054 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1055 /* Intel xhci needs interrupt rate moderated. */ 1056 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1057 else 1058 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1059 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 1060 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1061 1062 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 1063 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1064 xhci_op_read_4(sc, XHCI_USBCMD)); 1065 1066 return 0; 1067 1068 bad: 1069 if (sc->sc_xferpool) { 1070 pool_cache_destroy(sc->sc_xferpool); 1071 sc->sc_xferpool = NULL; 1072 } 1073 1074 if (sc->sc_slots) { 1075 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1076 sc->sc_maxslots); 1077 sc->sc_slots = NULL; 1078 } 1079 1080 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1081 bad4: 1082 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1083 bad3: 1084 xhci_ring_free(sc, &sc->sc_er); 1085 bad2: 1086 xhci_ring_free(sc, &sc->sc_cr); 1087 i = sc->sc_maxspbuf; 1088 bad1: 1089 for (int j = 0; j < i; j++) 1090 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1091 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1092 1093 return rv; 1094 } 1095 1096 int 1097 xhci_intr(void *v) 1098 { 1099 struct xhci_softc * const sc = v; 1100 int ret = 0; 1101 1102 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1103 1104 if (sc == NULL) 1105 return 0; 1106 1107 mutex_spin_enter(&sc->sc_intr_lock); 1108 1109 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1110 goto done; 1111 1112 /* If we get an interrupt while polling, then just ignore it. */ 1113 if (sc->sc_bus.ub_usepolling) { 1114 #ifdef DIAGNOSTIC 1115 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1116 #endif 1117 goto done; 1118 } 1119 1120 ret = xhci_intr1(sc); 1121 done: 1122 mutex_spin_exit(&sc->sc_intr_lock); 1123 return ret; 1124 } 1125 1126 int 1127 xhci_intr1(struct xhci_softc * const sc) 1128 { 1129 uint32_t usbsts; 1130 uint32_t iman; 1131 1132 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1133 1134 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1135 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1136 #if 0 1137 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1138 return 0; 1139 } 1140 #endif 1141 xhci_op_write_4(sc, XHCI_USBSTS, 1142 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1143 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1144 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1145 1146 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1147 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1148 iman |= XHCI_IMAN_INTR_PEND; 1149 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1150 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1151 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1152 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1153 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1154 1155 usb_schedsoftintr(&sc->sc_bus); 1156 1157 return 1; 1158 } 1159 1160 /* 1161 * 3 port speed types used in USB stack 1162 * 1163 * usbdi speed 1164 * definition: USB_SPEED_* in usb.h 1165 * They are used in struct usbd_device in USB stack. 1166 * ioctl interface uses these values too. 1167 * port_status speed 1168 * definition: UPS_*_SPEED in usb.h 1169 * They are used in usb_port_status_t and valid only for USB 2.0. 1170 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1171 * of usb_port_status_ext_t indicates port speed. 1172 * Note that some 3.0 values overlap with 2.0 values. 1173 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1174 * means UPS_LOW_SPEED in HS.) 1175 * port status returned from hub also uses these values. 1176 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1177 * or more. 1178 * xspeed: 1179 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1180 * They are used in only slot context and PORTSC reg of xhci. 1181 * The difference between usbdi speed and xspeed is 1182 * that FS and LS values are swapped. 1183 */ 1184 1185 /* convert usbdi speed to xspeed */ 1186 static int 1187 xhci_speed2xspeed(int speed) 1188 { 1189 switch (speed) { 1190 case USB_SPEED_LOW: return 2; 1191 case USB_SPEED_FULL: return 1; 1192 default: return speed; 1193 } 1194 } 1195 1196 #if 0 1197 /* convert xspeed to usbdi speed */ 1198 static int 1199 xhci_xspeed2speed(int xspeed) 1200 { 1201 switch (xspeed) { 1202 case 1: return USB_SPEED_FULL; 1203 case 2: return USB_SPEED_LOW; 1204 default: return xspeed; 1205 } 1206 } 1207 #endif 1208 1209 /* convert xspeed to port status speed */ 1210 static int 1211 xhci_xspeed2psspeed(int xspeed) 1212 { 1213 switch (xspeed) { 1214 case 0: return 0; 1215 case 1: return UPS_FULL_SPEED; 1216 case 2: return UPS_LOW_SPEED; 1217 case 3: return UPS_HIGH_SPEED; 1218 default: return UPS_OTHER_SPEED; 1219 } 1220 } 1221 1222 /* 1223 * Construct input contexts and issue TRB to open pipe. 1224 */ 1225 static usbd_status 1226 xhci_configure_endpoint(struct usbd_pipe *pipe) 1227 { 1228 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1229 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1230 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1231 struct xhci_trb trb; 1232 usbd_status err; 1233 1234 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1235 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1236 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1237 pipe->up_endpoint->ue_edesc->bmAttributes); 1238 1239 KASSERT(!mutex_owned(&sc->sc_lock)); 1240 1241 /* XXX ensure input context is available? */ 1242 1243 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1244 1245 /* set up context */ 1246 xhci_setup_ctx(pipe); 1247 1248 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1249 sc->sc_ctxsz * 1); 1250 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1251 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1252 1253 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1254 trb.trb_2 = 0; 1255 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1256 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1257 1258 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1259 1260 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1261 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1262 sc->sc_ctxsz * 1); 1263 1264 return err; 1265 } 1266 1267 #if 0 1268 static usbd_status 1269 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1270 { 1271 #ifdef USB_DEBUG 1272 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1273 #endif 1274 1275 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1276 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1277 1278 return USBD_NORMAL_COMPLETION; 1279 } 1280 #endif 1281 1282 /* 4.6.8, 6.4.3.7 */ 1283 static usbd_status 1284 xhci_reset_endpoint(struct usbd_pipe *pipe) 1285 { 1286 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1287 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1288 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1289 struct xhci_trb trb; 1290 usbd_status err; 1291 1292 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1293 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1294 1295 KASSERT(!mutex_owned(&sc->sc_lock)); 1296 1297 trb.trb_0 = 0; 1298 trb.trb_2 = 0; 1299 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1300 XHCI_TRB_3_EP_SET(dci) | 1301 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1302 1303 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1304 1305 return err; 1306 } 1307 1308 /* 1309 * 4.6.9, 6.4.3.8 1310 * Stop execution of TDs on xfer ring. 1311 * Should be called with sc_lock held. 1312 */ 1313 static usbd_status 1314 xhci_stop_endpoint(struct usbd_pipe *pipe) 1315 { 1316 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1317 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1318 struct xhci_trb trb; 1319 usbd_status err; 1320 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1321 1322 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1323 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1324 1325 KASSERT(mutex_owned(&sc->sc_lock)); 1326 1327 trb.trb_0 = 0; 1328 trb.trb_2 = 0; 1329 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1330 XHCI_TRB_3_EP_SET(dci) | 1331 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1332 1333 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1334 1335 return err; 1336 } 1337 1338 /* 1339 * Set TR Dequeue Pointer. 1340 * xHCI 1.1 4.6.10 6.4.3.9 1341 * Purge all of the TRBs on ring and reinitialize ring. 1342 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1343 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1344 * error will be generated. 1345 */ 1346 static usbd_status 1347 xhci_set_dequeue(struct usbd_pipe *pipe) 1348 { 1349 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1350 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1351 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1352 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1353 struct xhci_trb trb; 1354 usbd_status err; 1355 1356 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1357 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1358 1359 xhci_host_dequeue(xr); 1360 1361 /* set DCS */ 1362 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1363 trb.trb_2 = 0; 1364 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1365 XHCI_TRB_3_EP_SET(dci) | 1366 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1367 1368 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1369 1370 return err; 1371 } 1372 1373 /* 1374 * Open new pipe: called from usbd_setup_pipe_flags. 1375 * Fills methods of pipe. 1376 * If pipe is not for ep0, calls configure_endpoint. 1377 */ 1378 static usbd_status 1379 xhci_open(struct usbd_pipe *pipe) 1380 { 1381 struct usbd_device * const dev = pipe->up_dev; 1382 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1383 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1384 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1385 1386 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1387 DPRINTFN(1, "addr %d depth %d port %d speed %d", dev->ud_addr, 1388 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1389 DPRINTFN(1, " dci %u type 0x%02x epaddr 0x%02x attr 0x%02x", 1390 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1391 ed->bmAttributes); 1392 DPRINTFN(1, " mps %u ival %u", UGETW(ed->wMaxPacketSize), ed->bInterval, 1393 0, 0); 1394 1395 if (sc->sc_dying) 1396 return USBD_IOERROR; 1397 1398 /* Root Hub */ 1399 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1400 switch (ed->bEndpointAddress) { 1401 case USB_CONTROL_ENDPOINT: 1402 pipe->up_methods = &roothub_ctrl_methods; 1403 break; 1404 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1405 pipe->up_methods = &xhci_root_intr_methods; 1406 break; 1407 default: 1408 pipe->up_methods = NULL; 1409 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1410 ed->bEndpointAddress, 0, 0, 0); 1411 return USBD_INVAL; 1412 } 1413 return USBD_NORMAL_COMPLETION; 1414 } 1415 1416 switch (xfertype) { 1417 case UE_CONTROL: 1418 pipe->up_methods = &xhci_device_ctrl_methods; 1419 break; 1420 case UE_ISOCHRONOUS: 1421 pipe->up_methods = &xhci_device_isoc_methods; 1422 return USBD_INVAL; 1423 break; 1424 case UE_BULK: 1425 pipe->up_methods = &xhci_device_bulk_methods; 1426 break; 1427 case UE_INTERRUPT: 1428 pipe->up_methods = &xhci_device_intr_methods; 1429 break; 1430 default: 1431 return USBD_IOERROR; 1432 break; 1433 } 1434 1435 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1436 return xhci_configure_endpoint(pipe); 1437 1438 return USBD_NORMAL_COMPLETION; 1439 } 1440 1441 /* 1442 * Closes pipe, called from usbd_kill_pipe via close methods. 1443 * If the endpoint to be closed is ep0, disable_slot. 1444 * Should be called with sc_lock held. 1445 */ 1446 static void 1447 xhci_close_pipe(struct usbd_pipe *pipe) 1448 { 1449 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1450 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1451 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1452 const u_int dci = xhci_ep_get_dci(ed); 1453 struct xhci_trb trb; 1454 uint32_t *cp; 1455 1456 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1457 1458 if (sc->sc_dying) 1459 return; 1460 1461 /* xs is uninitialized before xhci_init_slot */ 1462 if (xs == NULL || xs->xs_idx == 0) 1463 return; 1464 1465 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1466 1467 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1468 KASSERT(mutex_owned(&sc->sc_lock)); 1469 1470 if (pipe->up_dev->ud_depth == 0) 1471 return; 1472 1473 if (dci == XHCI_DCI_EP_CONTROL) { 1474 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1475 xhci_disable_slot(sc, xs->xs_idx); 1476 return; 1477 } 1478 1479 /* 1480 * This may fail in the case that xhci_close_pipe is called after 1481 * xhci_abort_xfer e.g. usbd_kill_pipe. 1482 */ 1483 (void)xhci_stop_endpoint(pipe); 1484 1485 /* 1486 * set appropriate bit to be dropped. 1487 * don't set DC bit to 1, otherwise all endpoints 1488 * would be deconfigured. 1489 */ 1490 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1491 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1492 cp[1] = htole32(0); 1493 1494 /* XXX should be most significant one, not dci? */ 1495 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1496 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1497 1498 /* configure ep context performs an implicit dequeue */ 1499 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 1500 1501 /* sync input contexts before they are read from memory */ 1502 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1503 1504 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1505 trb.trb_2 = 0; 1506 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1507 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1508 1509 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1510 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1511 } 1512 1513 /* 1514 * Abort transfer. 1515 * May be called from softintr context. 1516 */ 1517 static void 1518 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1519 { 1520 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1521 1522 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1523 DPRINTFN(4, "xfer %p pipe %p status %d", 1524 xfer, xfer->ux_pipe, status, 0); 1525 1526 KASSERT(mutex_owned(&sc->sc_lock)); 1527 1528 if (sc->sc_dying) { 1529 /* If we're dying, just do the software part. */ 1530 DPRINTFN(4, "xfer %p dying %u", xfer, xfer->ux_status, 0, 0); 1531 xfer->ux_status = status; 1532 callout_stop(&xfer->ux_callout); 1533 usb_transfer_complete(xfer); 1534 return; 1535 } 1536 1537 /* XXX need more stuff */ 1538 xfer->ux_status = status; 1539 callout_stop(&xfer->ux_callout); 1540 usb_transfer_complete(xfer); 1541 DPRINTFN(14, "end", 0, 0, 0, 0); 1542 1543 KASSERT(mutex_owned(&sc->sc_lock)); 1544 } 1545 1546 static void 1547 xhci_host_dequeue(struct xhci_ring * const xr) 1548 { 1549 /* When dequeueing the controller, update our struct copy too */ 1550 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1551 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1552 BUS_DMASYNC_PREWRITE); 1553 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1554 1555 xr->xr_ep = 0; 1556 xr->xr_cs = 1; 1557 } 1558 1559 /* 1560 * Recover STALLed endpoint. 1561 * xHCI 1.1 sect 4.10.2.1 1562 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1563 * all transfers on transfer ring. 1564 * These are done in thread context asynchronously. 1565 */ 1566 static void 1567 xhci_clear_endpoint_stall_async_task(void *cookie) 1568 { 1569 struct usbd_xfer * const xfer = cookie; 1570 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1571 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1572 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1573 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1574 1575 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1576 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1577 1578 xhci_reset_endpoint(xfer->ux_pipe); 1579 xhci_set_dequeue(xfer->ux_pipe); 1580 1581 mutex_enter(&sc->sc_lock); 1582 tr->is_halted = false; 1583 usb_transfer_complete(xfer); 1584 mutex_exit(&sc->sc_lock); 1585 DPRINTFN(4, "ends", 0, 0, 0, 0); 1586 } 1587 1588 static usbd_status 1589 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1590 { 1591 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1592 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1593 1594 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1595 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1596 1597 if (sc->sc_dying) { 1598 return USBD_IOERROR; 1599 } 1600 1601 usb_init_task(&xp->xp_async_task, 1602 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1603 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1604 DPRINTFN(4, "ends", 0, 0, 0, 0); 1605 1606 return USBD_NORMAL_COMPLETION; 1607 } 1608 1609 /* Process roothub port status/change events and notify to uhub_intr. */ 1610 static void 1611 xhci_rhpsc(struct xhci_softc * const sc, u_int port) 1612 { 1613 struct usbd_xfer * const xfer = sc->sc_intrxfer; 1614 uint8_t *p; 1615 1616 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1617 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1618 port, 0, 0); 1619 1620 if (xfer == NULL) 1621 return; 1622 1623 if (port > sc->sc_maxports) 1624 return; 1625 1626 p = xfer->ux_buf; 1627 memset(p, 0, xfer->ux_length); 1628 p[port/NBBY] |= 1 << (port%NBBY); 1629 xfer->ux_actlen = xfer->ux_length; 1630 xfer->ux_status = USBD_NORMAL_COMPLETION; 1631 usb_transfer_complete(xfer); 1632 } 1633 1634 /* Process Transfer Events */ 1635 static void 1636 xhci_event_transfer(struct xhci_softc * const sc, 1637 const struct xhci_trb * const trb) 1638 { 1639 uint64_t trb_0; 1640 uint32_t trb_2, trb_3; 1641 uint8_t trbcode; 1642 u_int slot, dci; 1643 struct xhci_slot *xs; 1644 struct xhci_ring *xr; 1645 struct xhci_xfer *xx; 1646 struct usbd_xfer *xfer; 1647 usbd_status err; 1648 1649 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1650 1651 trb_0 = le64toh(trb->trb_0); 1652 trb_2 = le32toh(trb->trb_2); 1653 trb_3 = le32toh(trb->trb_3); 1654 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1655 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1656 dci = XHCI_TRB_3_EP_GET(trb_3); 1657 xs = &sc->sc_slots[slot]; 1658 xr = &xs->xs_ep[dci].xe_tr; 1659 1660 /* sanity check */ 1661 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1662 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1663 1664 int idx = 0; 1665 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1666 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1667 DPRINTFN(0, "invalid trb_0 0x%"PRIx64, trb_0, 0, 0, 0); 1668 return; 1669 } 1670 xx = xr->xr_cookies[idx]; 1671 1672 /* 1673 * If endpoint is stopped between TDs, TRB pointer points at 1674 * next TRB, however, it is not put yet or is a garbage TRB. 1675 * That's why xr_cookies may be NULL or look like broken. 1676 * Note: this ev happens only when hciversion >= 1.0 or 1677 * hciversion == 0.96 and FSE of hcc1 is set. 1678 */ 1679 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1680 DPRINTFN(1, "Ignore #%u: cookie %p cc %u dci %u", 1681 idx, xx, trbcode, dci); 1682 DPRINTFN(1, " orig TRB %"PRIx64" type %u", trb_0, 1683 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1684 0, 0); 1685 } 1686 } else { 1687 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1688 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1689 } 1690 /* XXX this may not happen */ 1691 if (xx == NULL) { 1692 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1693 return; 1694 } 1695 xfer = &xx->xx_xfer; 1696 /* XXX this may happen when detaching */ 1697 if (xfer == NULL) { 1698 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1699 xx, trb_0, 0, 0); 1700 return; 1701 } 1702 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1703 /* XXX I dunno why this happens */ 1704 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1705 1706 if (!xfer->ux_pipe->up_repeat && 1707 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1708 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1709 return; 1710 } 1711 1712 /* 4.11.5.2 Event Data TRB */ 1713 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1714 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1715 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1716 if ((trb_0 & 0x3) == 0x3) { 1717 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1718 } 1719 } 1720 1721 switch (trbcode) { 1722 case XHCI_TRB_ERROR_SHORT_PKT: 1723 case XHCI_TRB_ERROR_SUCCESS: 1724 /* 1725 * A ctrl transfer generates two events if it has a Data stage. 1726 * After a successful Data stage we cannot call call 1727 * usb_transfer_complete - this can only happen after the Data 1728 * stage. 1729 * 1730 * Note: Data and Status stage events point at same xfer. 1731 * ux_actlen and ux_dmabuf will be passed to 1732 * usb_transfer_complete after the Status stage event. 1733 * 1734 * It can be distingished which stage generates the event: 1735 * + by checking least 3 bits of trb_0 if ED==1. 1736 * (see xhci_device_ctrl_start). 1737 * + by checking the type of original TRB if ED==0. 1738 * 1739 * In addition, intr, bulk, and isoc transfer currently 1740 * consists of single TD, so the "skip" is not needed. 1741 * ctrl xfer uses EVENT_DATA, and others do not. 1742 * Thus driver can switch the flow by checking ED bit. 1743 */ 1744 xfer->ux_actlen = 1745 xfer->ux_length - XHCI_TRB_2_REM_GET(trb_2); 1746 err = USBD_NORMAL_COMPLETION; 1747 break; 1748 case XHCI_TRB_ERROR_STALL: 1749 case XHCI_TRB_ERROR_BABBLE: 1750 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1751 xr->is_halted = true; 1752 err = USBD_STALLED; 1753 /* 1754 * Stalled endpoints can be recoverd by issuing 1755 * command TRB TYPE_RESET_EP on xHCI instead of 1756 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1757 * on the endpoint. However, this function may be 1758 * called from softint context (e.g. from umass), 1759 * in that case driver gets KASSERT in cv_timedwait 1760 * in xhci_do_command. 1761 * To avoid this, this runs reset_endpoint and 1762 * usb_transfer_complete in usb task thread 1763 * asynchronously (and then umass issues clear 1764 * UF_ENDPOINT_HALT). 1765 */ 1766 xfer->ux_status = err; 1767 callout_stop(&xfer->ux_callout); 1768 xhci_clear_endpoint_stall_async(xfer); 1769 return; 1770 default: 1771 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1772 err = USBD_IOERROR; 1773 break; 1774 } 1775 xfer->ux_status = err; 1776 1777 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1778 if ((trb_0 & 0x3) == 0x0) { 1779 callout_stop(&xfer->ux_callout); 1780 usb_transfer_complete(xfer); 1781 } 1782 } else { 1783 callout_stop(&xfer->ux_callout); 1784 usb_transfer_complete(xfer); 1785 } 1786 } 1787 1788 /* Process Command complete events */ 1789 static void 1790 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 1791 { 1792 uint64_t trb_0; 1793 uint32_t trb_2, trb_3; 1794 1795 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1796 1797 trb_0 = le64toh(trb->trb_0); 1798 trb_2 = le32toh(trb->trb_2); 1799 trb_3 = le32toh(trb->trb_3); 1800 1801 if (trb_0 == sc->sc_command_addr) { 1802 sc->sc_result_trb.trb_0 = trb_0; 1803 sc->sc_result_trb.trb_2 = trb_2; 1804 sc->sc_result_trb.trb_3 = trb_3; 1805 if (XHCI_TRB_2_ERROR_GET(trb_2) != 1806 XHCI_TRB_ERROR_SUCCESS) { 1807 DPRINTFN(1, "command completion " 1808 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 1809 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 1810 } 1811 cv_signal(&sc->sc_command_cv); 1812 } else { 1813 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 1814 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 1815 trb_2, trb_3); 1816 } 1817 } 1818 1819 /* 1820 * Process events. 1821 * called from xhci_softintr 1822 */ 1823 static void 1824 xhci_handle_event(struct xhci_softc * const sc, 1825 const struct xhci_trb * const trb) 1826 { 1827 uint64_t trb_0; 1828 uint32_t trb_2, trb_3; 1829 1830 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1831 1832 trb_0 = le64toh(trb->trb_0); 1833 trb_2 = le32toh(trb->trb_2); 1834 trb_3 = le32toh(trb->trb_3); 1835 1836 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 1837 trb, trb_0, trb_2, trb_3); 1838 1839 /* 1840 * 4.11.3.1, 6.4.2.1 1841 * TRB Pointer is invalid for these completion codes. 1842 */ 1843 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 1844 case XHCI_TRB_ERROR_RING_UNDERRUN: 1845 case XHCI_TRB_ERROR_RING_OVERRUN: 1846 case XHCI_TRB_ERROR_VF_RING_FULL: 1847 return; 1848 default: 1849 if (trb_0 == 0) { 1850 return; 1851 } 1852 break; 1853 } 1854 1855 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 1856 case XHCI_TRB_EVENT_TRANSFER: 1857 xhci_event_transfer(sc, trb); 1858 break; 1859 case XHCI_TRB_EVENT_CMD_COMPLETE: 1860 xhci_event_cmd(sc, trb); 1861 break; 1862 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 1863 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 1864 break; 1865 default: 1866 break; 1867 } 1868 } 1869 1870 static void 1871 xhci_softintr(void *v) 1872 { 1873 struct usbd_bus * const bus = v; 1874 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1875 struct xhci_ring * const er = &sc->sc_er; 1876 struct xhci_trb *trb; 1877 int i, j, k; 1878 1879 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1880 1881 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1882 1883 i = er->xr_ep; 1884 j = er->xr_cs; 1885 1886 DPRINTFN(16, "er: xr_ep %d xr_cs %d", i, j, 0, 0); 1887 1888 while (1) { 1889 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 1890 BUS_DMASYNC_POSTREAD); 1891 trb = &er->xr_trb[i]; 1892 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1893 1894 if (j != k) 1895 break; 1896 1897 xhci_handle_event(sc, trb); 1898 1899 i++; 1900 if (i == er->xr_ntrb) { 1901 i = 0; 1902 j ^= 1; 1903 } 1904 } 1905 1906 er->xr_ep = i; 1907 er->xr_cs = j; 1908 1909 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 1910 XHCI_ERDP_LO_BUSY); 1911 1912 DPRINTFN(16, "ends", 0, 0, 0, 0); 1913 1914 return; 1915 } 1916 1917 static void 1918 xhci_poll(struct usbd_bus *bus) 1919 { 1920 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1921 1922 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1923 1924 mutex_spin_enter(&sc->sc_intr_lock); 1925 xhci_intr1(sc); 1926 mutex_spin_exit(&sc->sc_intr_lock); 1927 1928 return; 1929 } 1930 1931 static struct usbd_xfer * 1932 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 1933 { 1934 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1935 struct usbd_xfer *xfer; 1936 1937 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1938 1939 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1940 if (xfer != NULL) { 1941 memset(xfer, 0, sizeof(struct xhci_xfer)); 1942 #ifdef DIAGNOSTIC 1943 xfer->ux_state = XFER_BUSY; 1944 #endif 1945 } 1946 1947 return xfer; 1948 } 1949 1950 static void 1951 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1952 { 1953 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1954 1955 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1956 1957 #ifdef DIAGNOSTIC 1958 if (xfer->ux_state != XFER_BUSY) { 1959 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 1960 xfer, xfer->ux_state, 0, 0); 1961 } 1962 xfer->ux_state = XFER_FREE; 1963 #endif 1964 pool_cache_put(sc->sc_xferpool, xfer); 1965 } 1966 1967 static void 1968 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1969 { 1970 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1971 1972 *lock = &sc->sc_lock; 1973 } 1974 1975 extern uint32_t usb_cookie_no; 1976 1977 /* 1978 * xHCI 4.3 1979 * Called when uhub_explore finds a new device (via usbd_new_device). 1980 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 1981 * This function does: 1982 * Allocate and construct dev structure of default endpoint (ep0). 1983 * Allocate and open pipe of ep0. 1984 * Enable slot and initialize slot context. 1985 * Set Address. 1986 * Read initial device descriptor. 1987 * Determine initial MaxPacketSize (mps) by speed. 1988 * Read full device descriptor. 1989 * Register this device. 1990 * Finally state of device transitions ADDRESSED. 1991 */ 1992 static usbd_status 1993 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 1994 int speed, int port, struct usbd_port *up) 1995 { 1996 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 1997 struct usbd_device *dev; 1998 usbd_status err; 1999 usb_device_descriptor_t *dd; 2000 struct xhci_slot *xs; 2001 uint32_t *cp; 2002 2003 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2004 DPRINTFN(4, "port %u depth %u speed %u up %p", port, depth, speed, up); 2005 2006 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2007 if (dev == NULL) 2008 return USBD_NOMEM; 2009 2010 dev->ud_bus = bus; 2011 dev->ud_quirks = &usbd_no_quirk; 2012 dev->ud_addr = 0; 2013 dev->ud_ddesc.bMaxPacketSize = 0; 2014 dev->ud_depth = depth; 2015 dev->ud_powersrc = up; 2016 dev->ud_myhub = up->up_parent; 2017 dev->ud_speed = speed; 2018 dev->ud_langid = USBD_NOLANG; 2019 dev->ud_cookie.cookie = ++usb_cookie_no; 2020 2021 /* Set up default endpoint handle. */ 2022 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2023 /* doesn't matter, just don't let it uninitialized */ 2024 dev->ud_ep0.ue_toggle = 0; 2025 2026 /* Set up default endpoint descriptor. */ 2027 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2028 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2029 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2030 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2031 dev->ud_ep0desc.bInterval = 0; 2032 2033 /* 4.3, 4.8.2.1 */ 2034 switch (speed) { 2035 case USB_SPEED_SUPER: 2036 case USB_SPEED_SUPER_PLUS: 2037 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2038 break; 2039 case USB_SPEED_FULL: 2040 /* XXX using 64 as initial mps of ep0 in FS */ 2041 case USB_SPEED_HIGH: 2042 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2043 break; 2044 case USB_SPEED_LOW: 2045 default: 2046 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2047 break; 2048 } 2049 2050 up->up_dev = dev; 2051 2052 /* Establish the default pipe. */ 2053 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2054 &dev->ud_pipe0); 2055 if (err) { 2056 goto bad; 2057 } 2058 2059 dd = &dev->ud_ddesc; 2060 2061 if ((depth == 0) && (port == 0)) { 2062 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2063 bus->ub_devices[dev->ud_addr] = dev; 2064 err = usbd_get_initial_ddesc(dev, dd); 2065 if (err) 2066 goto bad; 2067 err = usbd_reload_device_desc(dev); 2068 if (err) 2069 goto bad; 2070 } else { 2071 uint8_t slot = 0; 2072 2073 /* 4.3.2 */ 2074 err = xhci_enable_slot(sc, &slot); 2075 if (err) 2076 goto bad; 2077 2078 xs = &sc->sc_slots[slot]; 2079 dev->ud_hcpriv = xs; 2080 2081 /* 4.3.3 initialize slot structure */ 2082 err = xhci_init_slot(dev, slot); 2083 if (err) { 2084 dev->ud_hcpriv = NULL; 2085 /* 2086 * We have to disable_slot here because 2087 * xs->xs_idx == 0 when xhci_init_slot fails, 2088 * in that case usbd_remove_dev won't work. 2089 */ 2090 mutex_enter(&sc->sc_lock); 2091 xhci_disable_slot(sc, slot); 2092 mutex_exit(&sc->sc_lock); 2093 goto bad; 2094 } 2095 2096 /* 4.3.4 Address Assignment */ 2097 err = xhci_set_address(dev, slot, false); 2098 if (err) 2099 goto bad; 2100 2101 /* Allow device time to set new address */ 2102 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2103 2104 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2105 //hexdump("slot context", cp, sc->sc_ctxsz); 2106 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2107 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2108 /* XXX ensure we know when the hardware does something 2109 we can't yet cope with */ 2110 KASSERT(addr >= 1 && addr <= 127); 2111 dev->ud_addr = addr; 2112 /* XXX dev->ud_addr not necessarily unique on bus */ 2113 KASSERT(bus->ub_devices[dev->ud_addr] == NULL); 2114 bus->ub_devices[dev->ud_addr] = dev; 2115 2116 err = usbd_get_initial_ddesc(dev, dd); 2117 if (err) 2118 goto bad; 2119 2120 /* 4.8.2.1 */ 2121 if (USB_IS_SS(speed)) { 2122 if (dd->bMaxPacketSize != 9) { 2123 printf("%s: invalid mps 2^%u for SS ep0," 2124 " using 512\n", 2125 device_xname(sc->sc_dev), 2126 dd->bMaxPacketSize); 2127 dd->bMaxPacketSize = 9; 2128 } 2129 USETW(dev->ud_ep0desc.wMaxPacketSize, 2130 (1 << dd->bMaxPacketSize)); 2131 } else 2132 USETW(dev->ud_ep0desc.wMaxPacketSize, 2133 dd->bMaxPacketSize); 2134 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2135 xhci_update_ep0_mps(sc, xs, 2136 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2137 2138 err = usbd_reload_device_desc(dev); 2139 if (err) 2140 goto bad; 2141 } 2142 2143 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2144 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2145 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2146 dd->bDeviceClass, dd->bDeviceSubClass, 2147 dd->bDeviceProtocol, 0); 2148 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2149 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2150 dev->ud_speed); 2151 2152 usbd_get_device_strings(dev); 2153 2154 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2155 2156 if ((depth == 0) && (port == 0)) { 2157 usbd_attach_roothub(parent, dev); 2158 DPRINTFN(1, "root_hub %p", bus->ub_roothub, 0, 0, 0); 2159 return USBD_NORMAL_COMPLETION; 2160 } 2161 2162 2163 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2164 bad: 2165 if (err != USBD_NORMAL_COMPLETION) { 2166 usbd_remove_device(dev, up); 2167 } 2168 2169 return err; 2170 } 2171 2172 static usbd_status 2173 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2174 size_t ntrb, size_t align) 2175 { 2176 usbd_status err; 2177 size_t size = ntrb * XHCI_TRB_SIZE; 2178 2179 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2180 2181 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2182 if (err) 2183 return err; 2184 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2185 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2186 xr->xr_trb = xhci_ring_trbv(xr, 0); 2187 xr->xr_ntrb = ntrb; 2188 xr->is_halted = false; 2189 xhci_host_dequeue(xr); 2190 2191 return USBD_NORMAL_COMPLETION; 2192 } 2193 2194 static void 2195 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2196 { 2197 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2198 mutex_destroy(&xr->xr_lock); 2199 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2200 } 2201 2202 static void 2203 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2204 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2205 { 2206 size_t i; 2207 u_int ri; 2208 u_int cs; 2209 uint64_t parameter; 2210 uint32_t status; 2211 uint32_t control; 2212 2213 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2214 2215 KASSERT(ntrbs <= XHCI_XFER_NTRB); 2216 for (i = 0; i < ntrbs; i++) { 2217 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2218 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2219 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2220 KASSERT(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2221 XHCI_TRB_TYPE_LINK); 2222 } 2223 2224 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2225 2226 ri = xr->xr_ep; 2227 cs = xr->xr_cs; 2228 2229 /* 2230 * Although the xhci hardware can do scatter/gather dma from 2231 * arbitrary sized buffers, there is a non-obvious restriction 2232 * that a LINK trb is only allowed at the end of a burst of 2233 * transfers - which might be 16kB. 2234 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2235 * The simple solution is not to allow a LINK trb in the middle 2236 * of anything - as here. 2237 * XXX: (dsl) There are xhci controllers out there (eg some made by 2238 * ASMedia) that seem to lock up if they process a LINK trb but 2239 * cannot process the linked-to trb yet. 2240 * The code should write the 'cycle' bit on the link trb AFTER 2241 * adding the other trb. 2242 */ 2243 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2244 parameter = xhci_ring_trbp(xr, 0); 2245 status = 0; 2246 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2247 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2248 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2249 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2250 BUS_DMASYNC_PREWRITE); 2251 xr->xr_cookies[ri] = NULL; 2252 xr->xr_ep = 0; 2253 xr->xr_cs ^= 1; 2254 ri = xr->xr_ep; 2255 cs = xr->xr_cs; 2256 } 2257 2258 ri++; 2259 2260 /* Write any subsequent TRB first */ 2261 for (i = 1; i < ntrbs; i++) { 2262 parameter = trbs[i].trb_0; 2263 status = trbs[i].trb_2; 2264 control = trbs[i].trb_3; 2265 2266 if (cs) { 2267 control |= XHCI_TRB_3_CYCLE_BIT; 2268 } else { 2269 control &= ~XHCI_TRB_3_CYCLE_BIT; 2270 } 2271 2272 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2273 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2274 BUS_DMASYNC_PREWRITE); 2275 xr->xr_cookies[ri] = cookie; 2276 ri++; 2277 } 2278 2279 /* Write the first TRB last */ 2280 i = 0; 2281 parameter = trbs[i].trb_0; 2282 status = trbs[i].trb_2; 2283 control = trbs[i].trb_3; 2284 2285 if (xr->xr_cs) { 2286 control |= XHCI_TRB_3_CYCLE_BIT; 2287 } else { 2288 control &= ~XHCI_TRB_3_CYCLE_BIT; 2289 } 2290 2291 xhci_trb_put(&xr->xr_trb[xr->xr_ep], parameter, status, control); 2292 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * xr->xr_ep, XHCI_TRB_SIZE * 1, 2293 BUS_DMASYNC_PREWRITE); 2294 xr->xr_cookies[xr->xr_ep] = cookie; 2295 2296 xr->xr_ep = ri; 2297 xr->xr_cs = cs; 2298 2299 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2300 } 2301 2302 /* 2303 * Stop execution commands, purge all commands on command ring, and 2304 * rewind dequeue pointer. 2305 */ 2306 static void 2307 xhci_abort_command(struct xhci_softc *sc) 2308 { 2309 struct xhci_ring * const cr = &sc->sc_cr; 2310 uint64_t crcr; 2311 int i; 2312 2313 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2314 DPRINTFN(14, "command %#"PRIx64" timeout, aborting", 2315 sc->sc_command_addr, 0, 0, 0); 2316 2317 mutex_enter(&cr->xr_lock); 2318 2319 /* 4.6.1.2 Aborting a Command */ 2320 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2321 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2322 2323 for (i = 0; i < 500; i++) { 2324 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2325 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2326 break; 2327 usb_delay_ms(&sc->sc_bus, 1); 2328 } 2329 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2330 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2331 /* reset HC here? */ 2332 } 2333 2334 /* reset command ring dequeue pointer */ 2335 cr->xr_ep = 0; 2336 cr->xr_cs = 1; 2337 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2338 2339 mutex_exit(&cr->xr_lock); 2340 } 2341 2342 /* 2343 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2344 * Command completion is notified by cv_signal from xhci_event_cmd() 2345 * (called from xhci_softint), or timed-out. 2346 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2347 * then do_command examines it. 2348 */ 2349 static usbd_status 2350 xhci_do_command_locked(struct xhci_softc * const sc, 2351 struct xhci_trb * const trb, int timeout) 2352 { 2353 struct xhci_ring * const cr = &sc->sc_cr; 2354 usbd_status err; 2355 2356 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2357 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2358 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2359 2360 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2361 KASSERT(mutex_owned(&sc->sc_lock)); 2362 2363 /* XXX KASSERT may fire when cv_timedwait unlocks sc_lock */ 2364 KASSERT(sc->sc_command_addr == 0); 2365 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2366 2367 mutex_enter(&cr->xr_lock); 2368 xhci_ring_put(sc, cr, NULL, trb, 1); 2369 mutex_exit(&cr->xr_lock); 2370 2371 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2372 2373 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2374 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2375 xhci_abort_command(sc); 2376 err = USBD_TIMEOUT; 2377 goto timedout; 2378 } 2379 2380 trb->trb_0 = sc->sc_result_trb.trb_0; 2381 trb->trb_2 = sc->sc_result_trb.trb_2; 2382 trb->trb_3 = sc->sc_result_trb.trb_3; 2383 2384 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2385 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2386 2387 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2388 case XHCI_TRB_ERROR_SUCCESS: 2389 err = USBD_NORMAL_COMPLETION; 2390 break; 2391 default: 2392 case 192 ... 223: 2393 err = USBD_IOERROR; 2394 break; 2395 case 224 ... 255: 2396 err = USBD_NORMAL_COMPLETION; 2397 break; 2398 } 2399 2400 timedout: 2401 sc->sc_command_addr = 0; 2402 return err; 2403 } 2404 2405 static usbd_status 2406 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2407 int timeout) 2408 { 2409 2410 mutex_enter(&sc->sc_lock); 2411 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2412 mutex_exit(&sc->sc_lock); 2413 2414 return ret; 2415 } 2416 2417 static usbd_status 2418 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2419 { 2420 struct xhci_trb trb; 2421 usbd_status err; 2422 2423 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2424 2425 trb.trb_0 = 0; 2426 trb.trb_2 = 0; 2427 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2428 2429 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2430 if (err != USBD_NORMAL_COMPLETION) { 2431 return err; 2432 } 2433 2434 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2435 2436 return err; 2437 } 2438 2439 /* 2440 * xHCI 4.6.4 2441 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2442 * All endpoints in the slot should be stopped. 2443 * Should be called with sc_lock held. 2444 */ 2445 static usbd_status 2446 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2447 { 2448 struct xhci_trb trb; 2449 struct xhci_slot *xs; 2450 usbd_status err; 2451 2452 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2453 2454 if (sc->sc_dying) 2455 return USBD_IOERROR; 2456 2457 trb.trb_0 = 0; 2458 trb.trb_2 = 0; 2459 trb.trb_3 = htole32( 2460 XHCI_TRB_3_SLOT_SET(slot) | 2461 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2462 2463 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2464 2465 if (!err) { 2466 xs = &sc->sc_slots[slot]; 2467 if (xs->xs_idx != 0) { 2468 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2469 xhci_set_dcba(sc, 0, slot); 2470 memset(xs, 0, sizeof(*xs)); 2471 } 2472 } 2473 2474 return err; 2475 } 2476 2477 /* 2478 * Set address of device and transition slot state from ENABLED to ADDRESSED 2479 * if Block Setaddress Request (BSR) is false. 2480 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2481 * see xHCI 1.1 4.5.3, 3.3.4 2482 * Should be called without sc_lock held. 2483 */ 2484 static usbd_status 2485 xhci_address_device(struct xhci_softc * const sc, 2486 uint64_t icp, uint8_t slot_id, bool bsr) 2487 { 2488 struct xhci_trb trb; 2489 usbd_status err; 2490 2491 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2492 2493 trb.trb_0 = icp; 2494 trb.trb_2 = 0; 2495 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2496 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2497 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2498 2499 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2500 2501 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2502 err = USBD_NO_ADDR; 2503 2504 return err; 2505 } 2506 2507 static usbd_status 2508 xhci_update_ep0_mps(struct xhci_softc * const sc, 2509 struct xhci_slot * const xs, u_int mps) 2510 { 2511 struct xhci_trb trb; 2512 usbd_status err; 2513 uint32_t * cp; 2514 2515 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2516 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2517 2518 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2519 cp[0] = htole32(0); 2520 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2521 2522 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2523 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2524 2525 /* sync input contexts before they are read from memory */ 2526 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2527 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2528 sc->sc_ctxsz * 4); 2529 2530 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2531 trb.trb_2 = 0; 2532 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2533 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2534 2535 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2536 KASSERT(err == USBD_NORMAL_COMPLETION); /* XXX */ 2537 return err; 2538 } 2539 2540 static void 2541 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2542 { 2543 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2544 2545 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2546 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2547 &dcbaa[si], dcba, si, 0); 2548 2549 dcbaa[si] = htole64(dcba); 2550 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2551 BUS_DMASYNC_PREWRITE); 2552 } 2553 2554 /* 2555 * Allocate device and input context DMA buffer, and 2556 * TRB DMA buffer for each endpoint. 2557 */ 2558 static usbd_status 2559 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2560 { 2561 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2562 struct xhci_slot *xs; 2563 usbd_status err; 2564 u_int dci; 2565 2566 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2567 DPRINTFN(4, "slot %u", slot, 0, 0, 0); 2568 2569 xs = &sc->sc_slots[slot]; 2570 2571 /* allocate contexts */ 2572 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2573 &xs->xs_dc_dma); 2574 if (err) 2575 return err; 2576 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2577 2578 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2579 &xs->xs_ic_dma); 2580 if (err) 2581 goto bad1; 2582 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2583 2584 for (dci = 0; dci < 32; dci++) { 2585 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2586 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2587 if (dci == XHCI_DCI_SLOT) 2588 continue; 2589 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2590 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2591 if (err) { 2592 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2593 goto bad2; 2594 } 2595 } 2596 2597 bad2: 2598 if (err == USBD_NORMAL_COMPLETION) { 2599 xs->xs_idx = slot; 2600 } else { 2601 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2602 } 2603 2604 return err; 2605 2606 bad1: 2607 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2608 xs->xs_idx = 0; 2609 return err; 2610 } 2611 2612 static void 2613 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2614 int end_dci) 2615 { 2616 u_int dci; 2617 2618 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2619 DPRINTFN(4, "slot %u start %u end %u", xs->xs_idx, start_dci, end_dci, 2620 0); 2621 2622 for (dci = start_dci; dci < end_dci; dci++) { 2623 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2624 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2625 } 2626 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2627 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2628 xs->xs_idx = 0; 2629 } 2630 2631 /* 2632 * Setup slot context, set Device Context Base Address, and issue 2633 * Set Address Device command. 2634 */ 2635 static usbd_status 2636 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 2637 { 2638 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2639 struct xhci_slot *xs; 2640 usbd_status err; 2641 2642 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2643 DPRINTFN(4, "slot %u bsr %u", slot, bsr, 0, 0); 2644 2645 xs = &sc->sc_slots[slot]; 2646 2647 xhci_setup_ctx(dev->ud_pipe0); 2648 2649 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2650 sc->sc_ctxsz * 3); 2651 2652 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2653 2654 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 2655 2656 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2657 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2658 sc->sc_ctxsz * 2); 2659 2660 return err; 2661 } 2662 2663 /* 2664 * 4.8.2, 6.2.3.2 2665 * construct slot/endpoint context parameters and do syncmem 2666 */ 2667 static void 2668 xhci_setup_ctx(struct usbd_pipe *pipe) 2669 { 2670 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2671 struct usbd_device *dev = pipe->up_dev; 2672 struct xhci_slot * const xs = dev->ud_hcpriv; 2673 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2674 const u_int dci = xhci_ep_get_dci(ed); 2675 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2676 uint32_t *cp; 2677 uint16_t mps = UGETW(ed->wMaxPacketSize); 2678 uint8_t speed = dev->ud_speed; 2679 uint8_t ival = ed->bInterval; 2680 2681 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2682 DPRINTFN(4, "pipe %p: slot %u dci %u speed %u", pipe, xs->xs_idx, dci, 2683 speed); 2684 2685 /* set up initial input control context */ 2686 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2687 cp[0] = htole32(0); 2688 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 2689 if (dci == XHCI_DCI_EP_CONTROL) 2690 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2691 cp[7] = htole32(0); 2692 2693 /* set up input slot context */ 2694 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2695 cp[0] = 2696 XHCI_SCTX_0_CTX_NUM_SET(dci) | 2697 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 2698 cp[1] = 0; 2699 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2700 cp[3] = 0; 2701 xhci_setup_route(pipe, cp); 2702 xhci_setup_tthub(pipe, cp); 2703 2704 cp[0] = htole32(cp[0]); 2705 cp[1] = htole32(cp[1]); 2706 cp[2] = htole32(cp[2]); 2707 cp[3] = htole32(cp[3]); 2708 2709 /* set up input endpoint context */ 2710 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 2711 cp[0] = 2712 XHCI_EPCTX_0_EPSTATE_SET(0) | 2713 XHCI_EPCTX_0_MULT_SET(0) | 2714 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2715 XHCI_EPCTX_0_LSA_SET(0) | 2716 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 2717 cp[1] = 2718 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 2719 XHCI_EPCTX_1_HID_SET(0) | 2720 XHCI_EPCTX_1_MAXB_SET(0); 2721 2722 if (xfertype != UE_ISOCHRONOUS) 2723 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 2724 2725 if (xfertype == UE_CONTROL) 2726 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 2727 else if (USB_IS_SS(speed)) 2728 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 2729 else 2730 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 2731 2732 xhci_setup_maxburst(pipe, cp); 2733 2734 switch (xfertype) { 2735 case UE_CONTROL: 2736 break; 2737 case UE_BULK: 2738 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 2739 break; 2740 case UE_INTERRUPT: 2741 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 2742 ival = pipe->up_interval; 2743 2744 ival = xhci_bival2ival(ival, speed); 2745 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 2746 break; 2747 case UE_ISOCHRONOUS: 2748 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 2749 ival = pipe->up_interval; 2750 2751 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 2752 if (speed == USB_SPEED_FULL) 2753 ival += 3; /* 1ms -> 125us */ 2754 ival--; 2755 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 2756 break; 2757 default: 2758 break; 2759 } 2760 DPRINTFN(4, "setting ival %u MaxBurst %#x", 2761 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 2762 2763 /* rewind TR dequeue pointer in xHC */ 2764 /* can't use xhci_ep_get_dci() yet? */ 2765 *(uint64_t *)(&cp[2]) = htole64( 2766 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 2767 XHCI_EPCTX_2_DCS_SET(1)); 2768 2769 cp[0] = htole32(cp[0]); 2770 cp[1] = htole32(cp[1]); 2771 cp[4] = htole32(cp[4]); 2772 2773 /* rewind TR dequeue pointer in driver */ 2774 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 2775 mutex_enter(&xr->xr_lock); 2776 xhci_host_dequeue(xr); 2777 mutex_exit(&xr->xr_lock); 2778 2779 /* sync input contexts before they are read from memory */ 2780 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2781 } 2782 2783 /* 2784 * Setup route string and roothub port of given device for slot context 2785 */ 2786 static void 2787 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 2788 { 2789 struct usbd_device *dev = pipe->up_dev; 2790 struct usbd_port *up = dev->ud_powersrc; 2791 struct usbd_device *hub; 2792 struct usbd_device *adev; 2793 uint8_t rhport = 0; 2794 uint32_t route = 0; 2795 2796 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2797 2798 /* Locate root hub port and Determine route string */ 2799 /* 4.3.3 route string does not include roothub port */ 2800 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 2801 uint32_t dep; 2802 2803 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 2804 hub, hub->ud_depth, hub->ud_powersrc, 2805 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 2806 2807 if (hub->ud_powersrc == NULL) 2808 break; 2809 dep = hub->ud_depth; 2810 if (dep == 0) 2811 break; 2812 rhport = hub->ud_powersrc->up_portno; 2813 if (dep > USB_HUB_MAX_DEPTH) 2814 continue; 2815 2816 route |= 2817 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 2818 << ((dep - 1) * 4); 2819 } 2820 route = route >> 4; 2821 DPRINTFN(4, "rhport %u Route %05x hub %p", rhport, route, hub, 0); 2822 2823 /* Locate port on upstream high speed hub */ 2824 for (adev = dev, hub = up->up_parent; 2825 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 2826 adev = hub, hub = hub->ud_myhub) 2827 ; 2828 if (hub) { 2829 int p; 2830 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 2831 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 2832 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 2833 goto found; 2834 } 2835 } 2836 panic("xhci_setup_route: cannot find HS port"); 2837 found: 2838 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 2839 } else { 2840 dev->ud_myhsport = NULL; 2841 } 2842 2843 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 2844 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(rhport); 2845 } 2846 2847 /* 2848 * Setup whether device is hub, whether device uses MTT, and 2849 * TT informations if it uses MTT. 2850 */ 2851 static void 2852 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 2853 { 2854 struct usbd_device *dev = pipe->up_dev; 2855 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 2856 uint32_t speed = dev->ud_speed; 2857 uint8_t tthubslot, ttportnum; 2858 bool ishub; 2859 bool usemtt; 2860 2861 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2862 2863 /* 2864 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 2865 * tthubslot: 2866 * This is the slot ID of parent HS hub 2867 * if LS/FS device is connected && connected through HS hub. 2868 * This is 0 if device is not LS/FS device || 2869 * parent hub is not HS hub || 2870 * attached to root hub. 2871 * ttportnum: 2872 * This is the downstream facing port of parent HS hub 2873 * if LS/FS device is connected. 2874 * This is 0 if device is not LS/FS device || 2875 * parent hub is not HS hub || 2876 * attached to root hub. 2877 */ 2878 if (dev->ud_myhsport != NULL && 2879 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 2880 (dev->ud_myhub != NULL && 2881 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 2882 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 2883 ttportnum = dev->ud_myhsport->up_portno; 2884 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 2885 } else { 2886 ttportnum = 0; 2887 tthubslot = 0; 2888 } 2889 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 2890 dev->ud_myhsport, ttportnum, tthubslot, 0); 2891 2892 /* ishub is valid after reading UDESC_DEVICE */ 2893 ishub = (dd->bDeviceClass == UDCLASS_HUB); 2894 2895 /* dev->ud_hub is valid after reading UDESC_HUB */ 2896 if (ishub && dev->ud_hub) { 2897 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 2898 uint8_t ttt = 2899 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 2900 2901 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 2902 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 2903 DPRINTFN(4, "nports=%d ttt=%d", hd->bNbrPorts, ttt, 0, 0); 2904 } 2905 2906 #define IS_TTHUB(dd) \ 2907 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 2908 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 2909 2910 /* 2911 * MTT flag is set if 2912 * 1. this is HS hub && MTT is enabled 2913 * or 2914 * 2. this is not hub && this is LS or FS device && 2915 * MTT of parent HS hub (and its parent, too) is enabled 2916 */ 2917 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 2918 usemtt = true; 2919 else if (!ishub && 2920 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 2921 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 2922 (dev->ud_myhub != NULL && 2923 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 2924 dev->ud_myhsport != NULL && 2925 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 2926 usemtt = true; 2927 else 2928 usemtt = false; 2929 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 2930 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 2931 2932 #undef IS_TTHUB 2933 2934 cp[0] |= 2935 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 2936 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 2937 cp[2] |= 2938 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 2939 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 2940 } 2941 2942 /* set up params for periodic endpoint */ 2943 static void 2944 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 2945 { 2946 struct usbd_device *dev = pipe->up_dev; 2947 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2948 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2949 usbd_desc_iter_t iter; 2950 const usb_cdc_descriptor_t *cdcd; 2951 uint32_t maxb = 0; 2952 uint16_t mps = UGETW(ed->wMaxPacketSize); 2953 uint8_t speed = dev->ud_speed; 2954 uint8_t ep; 2955 2956 /* config desc is NULL when opening ep0 */ 2957 if (dev == NULL || dev->ud_cdesc == NULL) 2958 goto no_cdcd; 2959 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 2960 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 2961 if (cdcd == NULL) 2962 goto no_cdcd; 2963 usb_desc_iter_init(dev, &iter); 2964 iter.cur = (const void *)cdcd; 2965 2966 /* find endpoint_ss_comp desc for ep of this pipe */ 2967 for (ep = 0;;) { 2968 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 2969 if (cdcd == NULL) 2970 break; 2971 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 2972 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 2973 bEndpointAddress; 2974 if (UE_GET_ADDR(ep) == 2975 UE_GET_ADDR(ed->bEndpointAddress)) { 2976 cdcd = (const usb_cdc_descriptor_t *) 2977 usb_desc_iter_next(&iter); 2978 break; 2979 } 2980 ep = 0; 2981 } 2982 } 2983 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 2984 const usb_endpoint_ss_comp_descriptor_t * esscd = 2985 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 2986 maxb = esscd->bMaxBurst; 2987 } 2988 2989 no_cdcd: 2990 /* 6.2.3.4, 4.8.2.4 */ 2991 if (USB_IS_SS(speed)) { 2992 /* UBS 3.1 9.6.6 */ 2993 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 2994 /* UBS 3.1 9.6.7 */ 2995 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 2996 #ifdef notyet 2997 if (xfertype == UE_ISOCHRONOUS) { 2998 } 2999 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3000 /* use ESIT */ 3001 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3002 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3003 3004 /* XXX if LEC = 1, set ESIT instead */ 3005 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3006 } else { 3007 /* use ival */ 3008 } 3009 #endif 3010 } else { 3011 /* UBS 2.0 9.6.6 */ 3012 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3013 3014 /* 6.2.3.4 */ 3015 if (speed == USB_SPEED_HIGH && 3016 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3017 maxb = UE_GET_TRANS(mps); 3018 } else { 3019 /* LS/FS or HS CTRL or HS BULK */ 3020 maxb = 0; 3021 } 3022 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3023 } 3024 } 3025 3026 /* 3027 * Convert endpoint bInterval value to endpoint context interval value 3028 * for Interrupt pipe. 3029 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3030 */ 3031 static uint32_t 3032 xhci_bival2ival(uint32_t ival, uint32_t speed) 3033 { 3034 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3035 int i; 3036 3037 /* 3038 * round ival down to "the nearest base 2 multiple of 3039 * bInterval * 8". 3040 * bInterval is at most 255 as its type is uByte. 3041 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3042 */ 3043 for (i = 10; i > 0; i--) { 3044 if ((ival * 8) >= (1 << i)) 3045 break; 3046 } 3047 ival = i; 3048 } else { 3049 /* Interval = bInterval-1 for SS/HS */ 3050 ival--; 3051 } 3052 3053 return ival; 3054 } 3055 3056 /* ----- */ 3057 3058 static void 3059 xhci_noop(struct usbd_pipe *pipe) 3060 { 3061 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3062 } 3063 3064 /* 3065 * Process root hub request. 3066 */ 3067 static int 3068 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3069 void *buf, int buflen) 3070 { 3071 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3072 usb_port_status_t ps; 3073 int l, totlen = 0; 3074 uint16_t len, value, index; 3075 int port, i; 3076 uint32_t v; 3077 3078 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3079 3080 if (sc->sc_dying) 3081 return -1; 3082 3083 len = UGETW(req->wLength); 3084 value = UGETW(req->wValue); 3085 index = UGETW(req->wIndex); 3086 3087 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 3088 req->bmRequestType | (req->bRequest << 8), value, index, len); 3089 3090 #define C(x,y) ((x) | ((y) << 8)) 3091 switch (C(req->bRequest, req->bmRequestType)) { 3092 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3093 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 3094 if (len == 0) 3095 break; 3096 switch (value) { 3097 case C(0, UDESC_DEVICE): { 3098 usb_device_descriptor_t devd; 3099 totlen = min(buflen, sizeof(devd)); 3100 memcpy(&devd, buf, totlen); 3101 USETW(devd.idVendor, sc->sc_id_vendor); 3102 memcpy(buf, &devd, totlen); 3103 break; 3104 } 3105 #define sd ((usb_string_descriptor_t *)buf) 3106 case C(1, UDESC_STRING): 3107 /* Vendor */ 3108 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3109 break; 3110 case C(2, UDESC_STRING): 3111 /* Product */ 3112 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3113 break; 3114 #undef sd 3115 default: 3116 /* default from usbroothub */ 3117 return buflen; 3118 } 3119 break; 3120 3121 /* Hub requests */ 3122 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3123 break; 3124 /* Clear Port Feature request */ 3125 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3126 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 3127 index, value, 0, 0); 3128 if (index < 1 || index > sc->sc_maxports) { 3129 return -1; 3130 } 3131 port = XHCI_PORTSC(index); 3132 v = xhci_op_read_4(sc, port); 3133 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3134 v &= ~XHCI_PS_CLEAR; 3135 switch (value) { 3136 case UHF_PORT_ENABLE: 3137 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3138 break; 3139 case UHF_PORT_SUSPEND: 3140 return -1; 3141 case UHF_PORT_POWER: 3142 break; 3143 case UHF_PORT_TEST: 3144 case UHF_PORT_INDICATOR: 3145 return -1; 3146 case UHF_C_PORT_CONNECTION: 3147 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3148 break; 3149 case UHF_C_PORT_ENABLE: 3150 case UHF_C_PORT_SUSPEND: 3151 case UHF_C_PORT_OVER_CURRENT: 3152 return -1; 3153 case UHF_C_BH_PORT_RESET: 3154 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3155 break; 3156 case UHF_C_PORT_RESET: 3157 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3158 break; 3159 case UHF_C_PORT_LINK_STATE: 3160 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3161 break; 3162 case UHF_C_PORT_CONFIG_ERROR: 3163 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3164 break; 3165 default: 3166 return -1; 3167 } 3168 break; 3169 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3170 if (len == 0) 3171 break; 3172 if ((value & 0xff) != 0) { 3173 return -1; 3174 } 3175 usb_hub_descriptor_t hubd; 3176 3177 totlen = min(buflen, sizeof(hubd)); 3178 memcpy(&hubd, buf, totlen); 3179 hubd.bNbrPorts = sc->sc_maxports; 3180 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3181 hubd.bPwrOn2PwrGood = 200; 3182 for (i = 0, l = sc->sc_maxports; l > 0; i++, l -= 8) 3183 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 3184 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3185 totlen = min(totlen, hubd.bDescLength); 3186 memcpy(buf, &hubd, totlen); 3187 break; 3188 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3189 if (len != 4) { 3190 return -1; 3191 } 3192 memset(buf, 0, len); /* ? XXX */ 3193 totlen = len; 3194 break; 3195 /* Get Port Status request */ 3196 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3197 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 3198 if (index < 1 || index > sc->sc_maxports) { 3199 return -1; 3200 } 3201 if (len != 4) { 3202 return -1; 3203 } 3204 v = xhci_op_read_4(sc, XHCI_PORTSC(index)); 3205 DPRINTFN(4, "getrhportsc %d %08x", index, v, 0, 0); 3206 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3207 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3208 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3209 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3210 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3211 if (v & XHCI_PS_PR) i |= UPS_RESET; 3212 if (v & XHCI_PS_PP) { 3213 if (i & UPS_OTHER_SPEED) 3214 i |= UPS_PORT_POWER_SS; 3215 else 3216 i |= UPS_PORT_POWER; 3217 } 3218 if (i & UPS_OTHER_SPEED) 3219 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3220 if (sc->sc_vendor_port_status) 3221 i = sc->sc_vendor_port_status(sc, v, i); 3222 USETW(ps.wPortStatus, i); 3223 i = 0; 3224 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3225 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3226 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3227 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3228 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3229 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3230 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3231 USETW(ps.wPortChange, i); 3232 totlen = min(len, sizeof(ps)); 3233 memcpy(buf, &ps, totlen); 3234 break; 3235 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3236 return -1; 3237 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3238 break; 3239 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3240 break; 3241 /* Set Port Feature request */ 3242 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3243 int optval = (index >> 8) & 0xff; 3244 index &= 0xff; 3245 if (index < 1 || index > sc->sc_maxports) { 3246 return -1; 3247 } 3248 port = XHCI_PORTSC(index); 3249 v = xhci_op_read_4(sc, port); 3250 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3251 v &= ~XHCI_PS_CLEAR; 3252 switch (value) { 3253 case UHF_PORT_ENABLE: 3254 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3255 break; 3256 case UHF_PORT_SUSPEND: 3257 /* XXX suspend */ 3258 break; 3259 case UHF_PORT_RESET: 3260 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3261 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3262 /* Wait for reset to complete. */ 3263 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3264 if (sc->sc_dying) { 3265 return -1; 3266 } 3267 v = xhci_op_read_4(sc, port); 3268 if (v & XHCI_PS_PR) { 3269 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3270 usb_delay_ms(&sc->sc_bus, 10); 3271 /* XXX */ 3272 } 3273 break; 3274 case UHF_PORT_POWER: 3275 /* XXX power control */ 3276 break; 3277 /* XXX more */ 3278 case UHF_C_PORT_RESET: 3279 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3280 break; 3281 case UHF_PORT_U1_TIMEOUT: 3282 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3283 return -1; 3284 } 3285 port = XHCI_PORTPMSC(index); 3286 v = xhci_op_read_4(sc, port); 3287 v &= ~XHCI_PM3_U1TO_SET(0xff); 3288 v |= XHCI_PM3_U1TO_SET(optval); 3289 xhci_op_write_4(sc, port, v); 3290 break; 3291 case UHF_PORT_U2_TIMEOUT: 3292 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3293 return -1; 3294 } 3295 port = XHCI_PORTPMSC(index); 3296 v = xhci_op_read_4(sc, port); 3297 v &= ~XHCI_PM3_U2TO_SET(0xff); 3298 v |= XHCI_PM3_U2TO_SET(optval); 3299 xhci_op_write_4(sc, port, v); 3300 break; 3301 default: 3302 return -1; 3303 } 3304 } 3305 break; 3306 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3307 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3308 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3309 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3310 break; 3311 default: 3312 /* default from usbroothub */ 3313 return buflen; 3314 } 3315 3316 return totlen; 3317 } 3318 3319 /* root hub interrupt */ 3320 3321 static usbd_status 3322 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3323 { 3324 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3325 usbd_status err; 3326 3327 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3328 3329 /* Insert last in queue. */ 3330 mutex_enter(&sc->sc_lock); 3331 err = usb_insert_transfer(xfer); 3332 mutex_exit(&sc->sc_lock); 3333 if (err) 3334 return err; 3335 3336 /* Pipe isn't running, start first */ 3337 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3338 } 3339 3340 /* Wait for roothub port status/change */ 3341 static usbd_status 3342 xhci_root_intr_start(struct usbd_xfer *xfer) 3343 { 3344 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3345 3346 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3347 3348 if (sc->sc_dying) 3349 return USBD_IOERROR; 3350 3351 mutex_enter(&sc->sc_lock); 3352 sc->sc_intrxfer = xfer; 3353 mutex_exit(&sc->sc_lock); 3354 3355 return USBD_IN_PROGRESS; 3356 } 3357 3358 static void 3359 xhci_root_intr_abort(struct usbd_xfer *xfer) 3360 { 3361 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3362 3363 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3364 3365 KASSERT(mutex_owned(&sc->sc_lock)); 3366 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3367 3368 sc->sc_intrxfer = NULL; 3369 3370 xfer->ux_status = USBD_CANCELLED; 3371 usb_transfer_complete(xfer); 3372 } 3373 3374 static void 3375 xhci_root_intr_close(struct usbd_pipe *pipe) 3376 { 3377 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3378 3379 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3380 3381 KASSERT(mutex_owned(&sc->sc_lock)); 3382 3383 sc->sc_intrxfer = NULL; 3384 } 3385 3386 static void 3387 xhci_root_intr_done(struct usbd_xfer *xfer) 3388 { 3389 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3390 3391 } 3392 3393 /* -------------- */ 3394 /* device control */ 3395 3396 static usbd_status 3397 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3398 { 3399 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3400 usbd_status err; 3401 3402 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3403 3404 /* Insert last in queue. */ 3405 mutex_enter(&sc->sc_lock); 3406 err = usb_insert_transfer(xfer); 3407 mutex_exit(&sc->sc_lock); 3408 if (err) 3409 return err; 3410 3411 /* Pipe isn't running, start first */ 3412 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3413 } 3414 3415 static usbd_status 3416 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3417 { 3418 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3419 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3420 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3421 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3422 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3423 usb_device_request_t * const req = &xfer->ux_request; 3424 const int isread = usbd_xfer_isread(xfer); 3425 const uint32_t len = UGETW(req->wLength); 3426 usb_dma_t * const dma = &xfer->ux_dmabuf; 3427 uint64_t parameter; 3428 uint32_t status; 3429 uint32_t control; 3430 u_int i; 3431 3432 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3433 DPRINTFN(12, "req: %04x %04x %04x %04x", 3434 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3435 UGETW(req->wIndex), UGETW(req->wLength)); 3436 3437 /* we rely on the bottom bits for extra info */ 3438 KASSERT(((uintptr_t)xfer & 0x3) == 0x0); 3439 3440 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3441 3442 i = 0; 3443 3444 /* setup phase */ 3445 memcpy(¶meter, req, sizeof(*req)); 3446 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3447 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3448 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3449 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3450 XHCI_TRB_3_IDT_BIT; 3451 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3452 3453 if (len != 0) { 3454 /* data phase */ 3455 parameter = DMAADDR(dma, 0); 3456 KASSERT(len <= 0x10000); 3457 status = XHCI_TRB_2_IRQ_SET(0) | 3458 XHCI_TRB_2_TDSZ_SET(1) | 3459 XHCI_TRB_2_BYTES_SET(len); 3460 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3461 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3462 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3463 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3464 3465 parameter = (uintptr_t)xfer | 0x3; 3466 status = XHCI_TRB_2_IRQ_SET(0); 3467 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3468 XHCI_TRB_3_IOC_BIT; 3469 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3470 } 3471 3472 parameter = 0; 3473 status = XHCI_TRB_2_IRQ_SET(0); 3474 /* the status stage has inverted direction */ 3475 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3476 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3477 XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_ENT_BIT; 3478 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3479 3480 parameter = (uintptr_t)xfer | 0x0; 3481 status = XHCI_TRB_2_IRQ_SET(0); 3482 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVENT_DATA) | 3483 XHCI_TRB_3_IOC_BIT; 3484 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3485 3486 mutex_enter(&tr->xr_lock); 3487 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3488 mutex_exit(&tr->xr_lock); 3489 3490 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3491 3492 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3493 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3494 xhci_timeout, xfer); 3495 } 3496 3497 return USBD_IN_PROGRESS; 3498 } 3499 3500 static void 3501 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3502 { 3503 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3504 usb_device_request_t *req = &xfer->ux_request; 3505 int len = UGETW(req->wLength); 3506 int rd = req->bmRequestType & UT_READ; 3507 3508 if (len) 3509 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3510 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3511 } 3512 3513 static void 3514 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3515 { 3516 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3517 3518 xhci_abort_xfer(xfer, USBD_CANCELLED); 3519 } 3520 3521 static void 3522 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3523 { 3524 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3525 3526 xhci_close_pipe(pipe); 3527 } 3528 3529 /* ------------------ */ 3530 /* device isochronous */ 3531 3532 /* ----------- */ 3533 /* device bulk */ 3534 3535 static usbd_status 3536 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3537 { 3538 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3539 usbd_status err; 3540 3541 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3542 3543 /* Insert last in queue. */ 3544 mutex_enter(&sc->sc_lock); 3545 err = usb_insert_transfer(xfer); 3546 mutex_exit(&sc->sc_lock); 3547 if (err) 3548 return err; 3549 3550 /* 3551 * Pipe isn't running (otherwise err would be USBD_INPROG), 3552 * so start it first. 3553 */ 3554 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3555 } 3556 3557 static usbd_status 3558 xhci_device_bulk_start(struct usbd_xfer *xfer) 3559 { 3560 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3561 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3562 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3563 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3564 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3565 const uint32_t len = xfer->ux_length; 3566 usb_dma_t * const dma = &xfer->ux_dmabuf; 3567 uint64_t parameter; 3568 uint32_t status; 3569 uint32_t control; 3570 u_int i = 0; 3571 3572 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3573 3574 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3575 3576 if (sc->sc_dying) 3577 return USBD_IOERROR; 3578 3579 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3580 3581 parameter = DMAADDR(dma, 0); 3582 /* 3583 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3584 * If the user supplied buffer crosses such a boundary then 2 3585 * (or more) TRB should be used. 3586 * If multiple TRB are used the td_size field must be set correctly. 3587 * For v1.0 devices (like ivy bridge) this is the number of usb data 3588 * blocks needed to complete the transfer. 3589 * Setting it to 1 in the last TRB causes an extra zero-length 3590 * data block be sent. 3591 * The earlier documentation differs, I don't know how it behaves. 3592 */ 3593 KASSERT(len <= 0x10000); 3594 status = XHCI_TRB_2_IRQ_SET(0) | 3595 XHCI_TRB_2_TDSZ_SET(1) | 3596 XHCI_TRB_2_BYTES_SET(len); 3597 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3598 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3599 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3600 3601 mutex_enter(&tr->xr_lock); 3602 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3603 mutex_exit(&tr->xr_lock); 3604 3605 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3606 3607 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3608 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3609 xhci_timeout, xfer); 3610 } 3611 3612 return USBD_IN_PROGRESS; 3613 } 3614 3615 static void 3616 xhci_device_bulk_done(struct usbd_xfer *xfer) 3617 { 3618 #ifdef USB_DEBUG 3619 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3620 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3621 #endif 3622 const int isread = usbd_xfer_isread(xfer); 3623 3624 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3625 3626 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3627 3628 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3629 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3630 } 3631 3632 static void 3633 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3634 { 3635 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3636 3637 xhci_abort_xfer(xfer, USBD_CANCELLED); 3638 } 3639 3640 static void 3641 xhci_device_bulk_close(struct usbd_pipe *pipe) 3642 { 3643 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3644 3645 xhci_close_pipe(pipe); 3646 } 3647 3648 /* ---------------- */ 3649 /* device interrupt */ 3650 3651 static usbd_status 3652 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3653 { 3654 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3655 usbd_status err; 3656 3657 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3658 3659 /* Insert last in queue. */ 3660 mutex_enter(&sc->sc_lock); 3661 err = usb_insert_transfer(xfer); 3662 mutex_exit(&sc->sc_lock); 3663 if (err) 3664 return err; 3665 3666 /* 3667 * Pipe isn't running (otherwise err would be USBD_INPROG), 3668 * so start it first. 3669 */ 3670 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3671 } 3672 3673 static usbd_status 3674 xhci_device_intr_start(struct usbd_xfer *xfer) 3675 { 3676 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3677 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3678 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3679 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3680 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3681 const uint32_t len = xfer->ux_length; 3682 usb_dma_t * const dma = &xfer->ux_dmabuf; 3683 uint64_t parameter; 3684 uint32_t status; 3685 uint32_t control; 3686 u_int i = 0; 3687 3688 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3689 3690 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3691 3692 if (sc->sc_dying) 3693 return USBD_IOERROR; 3694 3695 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3696 3697 parameter = DMAADDR(dma, 0); 3698 KASSERT(len <= 0x10000); 3699 status = XHCI_TRB_2_IRQ_SET(0) | 3700 XHCI_TRB_2_TDSZ_SET(1) | 3701 XHCI_TRB_2_BYTES_SET(len); 3702 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3703 XHCI_TRB_3_ISP_BIT | XHCI_TRB_3_IOC_BIT; 3704 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3705 3706 mutex_enter(&tr->xr_lock); 3707 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3708 mutex_exit(&tr->xr_lock); 3709 3710 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3711 3712 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3713 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3714 xhci_timeout, xfer); 3715 } 3716 3717 return USBD_IN_PROGRESS; 3718 } 3719 3720 static void 3721 xhci_device_intr_done(struct usbd_xfer *xfer) 3722 { 3723 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3724 #ifdef USB_DEBUG 3725 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3726 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3727 #endif 3728 const int isread = usbd_xfer_isread(xfer); 3729 3730 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3731 3732 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3733 3734 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3735 3736 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3737 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3738 } 3739 3740 static void 3741 xhci_device_intr_abort(struct usbd_xfer *xfer) 3742 { 3743 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3744 3745 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3746 3747 KASSERT(mutex_owned(&sc->sc_lock)); 3748 DPRINTFN(15, "%p", xfer, 0, 0, 0); 3749 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3750 xhci_abort_xfer(xfer, USBD_CANCELLED); 3751 } 3752 3753 static void 3754 xhci_device_intr_close(struct usbd_pipe *pipe) 3755 { 3756 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3757 3758 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3759 DPRINTFN(15, "%p", pipe, 0, 0, 0); 3760 3761 xhci_close_pipe(pipe); 3762 } 3763 3764 /* ------------ */ 3765 3766 static void 3767 xhci_timeout(void *addr) 3768 { 3769 struct xhci_xfer * const xx = addr; 3770 struct usbd_xfer * const xfer = &xx->xx_xfer; 3771 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3772 3773 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3774 3775 if (sc->sc_dying) { 3776 return; 3777 } 3778 3779 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 3780 USB_TASKQ_MPSAFE); 3781 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 3782 USB_TASKQ_HC); 3783 } 3784 3785 static void 3786 xhci_timeout_task(void *addr) 3787 { 3788 struct usbd_xfer * const xfer = addr; 3789 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3790 3791 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3792 3793 mutex_enter(&sc->sc_lock); 3794 #if 0 3795 xhci_abort_xfer(xfer, USBD_TIMEOUT); 3796 #else 3797 xfer->ux_status = USBD_TIMEOUT; 3798 usb_transfer_complete(xfer); 3799 #endif 3800 mutex_exit(&sc->sc_lock); 3801 } 3802
Indexes created Fri Sep 26 08:10:20 GMT 2025