xhci.c revision 1.62.2.3
1 /* $NetBSD: xhci.c,v 1.62.2.3 2017/04/26 02:53:24 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.62.2.3 2017/04/26 02:53:24 pgoyette Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static void xhci_host_dequeue(struct xhci_ring * const); 146 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 147 148 static usbd_status xhci_do_command(struct xhci_softc * const, 149 struct xhci_trb * const, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 153 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 154 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 155 static usbd_status xhci_enable_slot(struct xhci_softc * const, 156 uint8_t * const); 157 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 158 static usbd_status xhci_address_device(struct xhci_softc * const, 159 uint64_t, uint8_t, bool); 160 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 161 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 162 struct xhci_slot * const, u_int); 163 static usbd_status xhci_ring_init(struct xhci_softc * const, 164 struct xhci_ring * const, size_t, size_t); 165 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 166 167 static void xhci_setup_ctx(struct usbd_pipe *); 168 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 169 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 170 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 171 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 172 173 static void xhci_noop(struct usbd_pipe *); 174 175 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 176 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 177 static void xhci_root_intr_abort(struct usbd_xfer *); 178 static void xhci_root_intr_close(struct usbd_pipe *); 179 static void xhci_root_intr_done(struct usbd_xfer *); 180 181 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 182 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 183 static void xhci_device_ctrl_abort(struct usbd_xfer *); 184 static void xhci_device_ctrl_close(struct usbd_pipe *); 185 static void xhci_device_ctrl_done(struct usbd_xfer *); 186 187 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 188 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 189 static void xhci_device_intr_abort(struct usbd_xfer *); 190 static void xhci_device_intr_close(struct usbd_pipe *); 191 static void xhci_device_intr_done(struct usbd_xfer *); 192 193 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 194 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 195 static void xhci_device_bulk_abort(struct usbd_xfer *); 196 static void xhci_device_bulk_close(struct usbd_pipe *); 197 static void xhci_device_bulk_done(struct usbd_xfer *); 198 199 static void xhci_timeout(void *); 200 static void xhci_timeout_task(void *); 201 202 static const struct usbd_bus_methods xhci_bus_methods = { 203 .ubm_open = xhci_open, 204 .ubm_softint = xhci_softintr, 205 .ubm_dopoll = xhci_poll, 206 .ubm_allocx = xhci_allocx, 207 .ubm_freex = xhci_freex, 208 .ubm_getlock = xhci_get_lock, 209 .ubm_newdev = xhci_new_device, 210 .ubm_rhctrl = xhci_roothub_ctrl, 211 }; 212 213 static const struct usbd_pipe_methods xhci_root_intr_methods = { 214 .upm_transfer = xhci_root_intr_transfer, 215 .upm_start = xhci_root_intr_start, 216 .upm_abort = xhci_root_intr_abort, 217 .upm_close = xhci_root_intr_close, 218 .upm_cleartoggle = xhci_noop, 219 .upm_done = xhci_root_intr_done, 220 }; 221 222 223 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 224 .upm_transfer = xhci_device_ctrl_transfer, 225 .upm_start = xhci_device_ctrl_start, 226 .upm_abort = xhci_device_ctrl_abort, 227 .upm_close = xhci_device_ctrl_close, 228 .upm_cleartoggle = xhci_noop, 229 .upm_done = xhci_device_ctrl_done, 230 }; 231 232 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 233 .upm_cleartoggle = xhci_noop, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 237 .upm_transfer = xhci_device_bulk_transfer, 238 .upm_start = xhci_device_bulk_start, 239 .upm_abort = xhci_device_bulk_abort, 240 .upm_close = xhci_device_bulk_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_bulk_done, 243 }; 244 245 static const struct usbd_pipe_methods xhci_device_intr_methods = { 246 .upm_transfer = xhci_device_intr_transfer, 247 .upm_start = xhci_device_intr_start, 248 .upm_abort = xhci_device_intr_abort, 249 .upm_close = xhci_device_intr_close, 250 .upm_cleartoggle = xhci_noop, 251 .upm_done = xhci_device_intr_done, 252 }; 253 254 static inline uint32_t 255 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 256 { 257 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 258 } 259 260 static inline uint32_t 261 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 262 { 263 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 264 } 265 266 static inline void 267 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 268 uint32_t value) 269 { 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 271 } 272 273 #if 0 /* unused */ 274 static inline void 275 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 276 uint32_t value) 277 { 278 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 279 } 280 #endif /* unused */ 281 282 static inline uint32_t 283 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 284 { 285 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 286 } 287 288 static inline uint32_t 289 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 290 { 291 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 292 } 293 294 static inline void 295 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 296 uint32_t value) 297 { 298 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 299 } 300 301 static inline uint64_t 302 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 303 { 304 uint64_t value; 305 306 if (sc->sc_ac64) { 307 #ifdef XHCI_USE_BUS_SPACE_8 308 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 309 #else 310 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 311 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 312 offset + 4) << 32; 313 #endif 314 } else { 315 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 316 } 317 318 return value; 319 } 320 321 static inline void 322 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 336 } 337 } 338 339 static inline uint32_t 340 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 341 { 342 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 343 } 344 345 static inline void 346 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 347 uint32_t value) 348 { 349 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 350 } 351 352 #if 0 /* unused */ 353 static inline uint64_t 354 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 355 { 356 uint64_t value; 357 358 if (sc->sc_ac64) { 359 #ifdef XHCI_USE_BUS_SPACE_8 360 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 361 #else 362 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 363 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 364 offset + 4) << 32; 365 #endif 366 } else { 367 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 368 } 369 370 return value; 371 } 372 #endif /* unused */ 373 374 static inline void 375 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 376 uint64_t value) 377 { 378 if (sc->sc_ac64) { 379 #ifdef XHCI_USE_BUS_SPACE_8 380 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 381 #else 382 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 383 (value >> 0) & 0xffffffff); 384 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 385 (value >> 32) & 0xffffffff); 386 #endif 387 } else { 388 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 389 } 390 } 391 392 #if 0 /* unused */ 393 static inline uint32_t 394 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 395 { 396 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 397 } 398 #endif /* unused */ 399 400 static inline void 401 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 402 uint32_t value) 403 { 404 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 405 } 406 407 /* --- */ 408 409 static inline uint8_t 410 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 411 { 412 u_int eptype = 0; 413 414 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 415 case UE_CONTROL: 416 eptype = 0x0; 417 break; 418 case UE_ISOCHRONOUS: 419 eptype = 0x1; 420 break; 421 case UE_BULK: 422 eptype = 0x2; 423 break; 424 case UE_INTERRUPT: 425 eptype = 0x3; 426 break; 427 } 428 429 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 430 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 431 return eptype | 0x4; 432 else 433 return eptype; 434 } 435 436 static u_int 437 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 438 { 439 /* xHCI 1.0 section 4.5.1 */ 440 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 441 u_int in = 0; 442 443 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 444 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 445 in = 1; 446 447 return epaddr * 2 + in; 448 } 449 450 static inline u_int 451 xhci_dci_to_ici(const u_int i) 452 { 453 return i + 1; 454 } 455 456 static inline void * 457 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 458 const u_int dci) 459 { 460 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 461 } 462 463 #if 0 /* unused */ 464 static inline bus_addr_t 465 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 466 const u_int dci) 467 { 468 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 469 } 470 #endif /* unused */ 471 472 static inline void * 473 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline bus_addr_t 480 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 481 const u_int ici) 482 { 483 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 484 } 485 486 static inline struct xhci_trb * 487 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 488 { 489 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 490 } 491 492 static inline bus_addr_t 493 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 494 { 495 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 496 } 497 498 static inline void 499 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 500 uint32_t control) 501 { 502 trb->trb_0 = htole64(parameter); 503 trb->trb_2 = htole32(status); 504 trb->trb_3 = htole32(control); 505 } 506 507 static int 508 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 509 { 510 /* base address of TRBs */ 511 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 512 513 /* trb_0 range sanity check */ 514 if (trb_0 == 0 || trb_0 < trbp || 515 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 516 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 517 return 1; 518 } 519 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 520 return 0; 521 } 522 523 static unsigned int 524 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 525 u_int dci) 526 { 527 uint32_t *cp; 528 529 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 530 cp = xhci_slot_get_dcv(sc, xs, dci); 531 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 532 } 533 534 static inline unsigned int 535 xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport) 536 { 537 const unsigned int port = ctlrport - 1; 538 const uint8_t bit = __BIT(port % NBBY); 539 540 return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit); 541 } 542 543 /* 544 * Return the roothub port for a controller port. Both are 1..n. 545 */ 546 static inline unsigned int 547 xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport) 548 { 549 550 return sc->sc_ctlrportmap[ctrlport - 1]; 551 } 552 553 /* 554 * Return the controller port for a bus roothub port. Both are 1..n. 555 */ 556 static inline unsigned int 557 xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn, 558 unsigned int rhport) 559 { 560 561 return sc->sc_rhportmap[bn][rhport - 1]; 562 } 563 564 /* --- */ 565 566 void 567 xhci_childdet(device_t self, device_t child) 568 { 569 struct xhci_softc * const sc = device_private(self); 570 571 KASSERT(sc->sc_child == child); 572 if (child == sc->sc_child) 573 sc->sc_child = NULL; 574 } 575 576 int 577 xhci_detach(struct xhci_softc *sc, int flags) 578 { 579 int rv = 0; 580 581 if (sc->sc_child2 != NULL) { 582 rv = config_detach(sc->sc_child2, flags); 583 if (rv != 0) 584 return rv; 585 } 586 587 if (sc->sc_child != NULL) { 588 rv = config_detach(sc->sc_child, flags); 589 if (rv != 0) 590 return rv; 591 } 592 593 /* XXX unconfigure/free slots */ 594 595 /* verify: */ 596 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 597 xhci_op_write_4(sc, XHCI_USBCMD, 0); 598 /* do we need to wait for stop? */ 599 600 xhci_op_write_8(sc, XHCI_CRCR, 0); 601 xhci_ring_free(sc, &sc->sc_cr); 602 cv_destroy(&sc->sc_command_cv); 603 cv_destroy(&sc->sc_cmdbusy_cv); 604 605 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 606 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 607 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 608 xhci_ring_free(sc, &sc->sc_er); 609 610 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 611 612 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 613 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 614 615 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 616 617 kmem_free(sc->sc_ctlrportbus, 618 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY)); 619 kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int)); 620 621 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 622 kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int)); 623 } 624 625 mutex_destroy(&sc->sc_lock); 626 mutex_destroy(&sc->sc_intr_lock); 627 628 pool_cache_destroy(sc->sc_xferpool); 629 630 return rv; 631 } 632 633 int 634 xhci_activate(device_t self, enum devact act) 635 { 636 struct xhci_softc * const sc = device_private(self); 637 638 switch (act) { 639 case DVACT_DEACTIVATE: 640 sc->sc_dying = true; 641 return 0; 642 default: 643 return EOPNOTSUPP; 644 } 645 } 646 647 bool 648 xhci_suspend(device_t dv, const pmf_qual_t *qual) 649 { 650 return false; 651 } 652 653 bool 654 xhci_resume(device_t dv, const pmf_qual_t *qual) 655 { 656 return false; 657 } 658 659 bool 660 xhci_shutdown(device_t self, int flags) 661 { 662 return false; 663 } 664 665 static int 666 xhci_hc_reset(struct xhci_softc * const sc) 667 { 668 uint32_t usbcmd, usbsts; 669 int i; 670 671 /* Check controller not ready */ 672 for (i = 0; i < XHCI_WAIT_CNR; i++) { 673 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 674 if ((usbsts & XHCI_STS_CNR) == 0) 675 break; 676 usb_delay_ms(&sc->sc_bus, 1); 677 } 678 if (i >= XHCI_WAIT_CNR) { 679 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 680 return EIO; 681 } 682 683 /* Halt controller */ 684 usbcmd = 0; 685 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 686 usb_delay_ms(&sc->sc_bus, 1); 687 688 /* Reset controller */ 689 usbcmd = XHCI_CMD_HCRST; 690 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 691 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 692 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 693 if ((usbcmd & XHCI_CMD_HCRST) == 0) 694 break; 695 usb_delay_ms(&sc->sc_bus, 1); 696 } 697 if (i >= XHCI_WAIT_HCRST) { 698 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 699 return EIO; 700 } 701 702 /* Check controller not ready */ 703 for (i = 0; i < XHCI_WAIT_CNR; i++) { 704 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 705 if ((usbsts & XHCI_STS_CNR) == 0) 706 break; 707 usb_delay_ms(&sc->sc_bus, 1); 708 } 709 if (i >= XHCI_WAIT_CNR) { 710 aprint_error_dev(sc->sc_dev, 711 "controller not ready timeout after reset\n"); 712 return EIO; 713 } 714 715 return 0; 716 } 717 718 719 static void 720 hexdump(const char *msg, const void *base, size_t len) 721 { 722 #if 0 723 size_t cnt; 724 const uint32_t *p; 725 extern paddr_t vtophys(vaddr_t); 726 727 p = base; 728 cnt = 0; 729 730 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 731 (void *)vtophys((vaddr_t)base)); 732 733 while (cnt < len) { 734 if (cnt % 16 == 0) 735 printf("%p: ", p); 736 else if (cnt % 8 == 0) 737 printf(" |"); 738 printf(" %08x", *p++); 739 cnt += 4; 740 if (cnt % 16 == 0) 741 printf("\n"); 742 } 743 if (cnt % 16 != 0) 744 printf("\n"); 745 #endif 746 } 747 748 /* 7.2 xHCI Support Protocol Capability */ 749 static void 750 xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp) 751 { 752 /* XXX Cache this lot */ 753 754 const uint32_t w0 = xhci_read_4(sc, ecp); 755 const uint32_t w4 = xhci_read_4(sc, ecp + 4); 756 const uint32_t w8 = xhci_read_4(sc, ecp + 8); 757 const uint32_t wc = xhci_read_4(sc, ecp + 0xc); 758 759 aprint_debug_dev(sc->sc_dev, 760 " SP: %08x %08x %08x %08x\n", w0, w4, w8, wc); 761 762 if (w4 != XHCI_XECP_USBID) 763 return; 764 765 const int major = XHCI_XECP_SP_W0_MAJOR(w0); 766 const int minor = XHCI_XECP_SP_W0_MINOR(w0); 767 const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8); 768 const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8); 769 770 const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16)); 771 switch (mm) { 772 case 0x0200: 773 case 0x0300: 774 case 0x0301: 775 aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n", 776 major == 3 ? "ss" : "hs", cpo, cpo + cpc -1); 777 break; 778 default: 779 aprint_debug_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n", 780 major, minor); 781 return; 782 } 783 784 const size_t bus = (major == 3) ? 0 : 1; 785 786 /* Index arrays with 0..n-1 where ports are numbered 1..n */ 787 for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) { 788 if (sc->sc_ctlrportmap[cp] != 0) { 789 aprint_error_dev(sc->sc_dev, "contoller port %zu " 790 "already assigned", cp); 791 continue; 792 } 793 794 sc->sc_ctlrportbus[cp / NBBY] |= 795 bus == 0 ? 0 : __BIT(cp % NBBY); 796 797 const size_t rhp = sc->sc_rhportcount[bus]++; 798 799 KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0, 800 "bus %zu rhp %zu is %d", bus, rhp, 801 sc->sc_rhportmap[bus][rhp]); 802 803 sc->sc_rhportmap[bus][rhp] = cp + 1; 804 sc->sc_ctlrportmap[cp] = rhp + 1; 805 } 806 } 807 808 /* Process extended capabilities */ 809 static void 810 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 811 { 812 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 813 814 bus_size_t ecp = XHCI_HCC_XECP(hcc) * 4; 815 while (ecp != 0) { 816 uint32_t ecr = xhci_read_4(sc, ecp); 817 aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr); 818 switch (XHCI_XECP_ID(ecr)) { 819 case XHCI_ID_PROTOCOLS: { 820 xhci_id_protocols(sc, ecp); 821 break; 822 } 823 case XHCI_ID_USB_LEGACY: { 824 uint8_t bios_sem; 825 826 /* Take host controller ownership from BIOS */ 827 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 828 if (bios_sem) { 829 /* sets xHCI to be owned by OS */ 830 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 831 aprint_debug_dev(sc->sc_dev, 832 "waiting for BIOS to give up control\n"); 833 for (int i = 0; i < 5000; i++) { 834 bios_sem = xhci_read_1(sc, ecp + 835 XHCI_XECP_BIOS_SEM); 836 if (bios_sem == 0) 837 break; 838 DELAY(1000); 839 } 840 if (bios_sem) { 841 aprint_error_dev(sc->sc_dev, 842 "timed out waiting for BIOS\n"); 843 } 844 } 845 break; 846 } 847 default: 848 break; 849 } 850 ecr = xhci_read_4(sc, ecp); 851 if (XHCI_XECP_NEXT(ecr) == 0) { 852 ecp = 0; 853 } else { 854 ecp += XHCI_XECP_NEXT(ecr) * 4; 855 } 856 } 857 } 858 859 #define XHCI_HCCPREV1_BITS \ 860 "\177\020" /* New bitmask */ \ 861 "f\020\020XECP\0" \ 862 "f\014\4MAXPSA\0" \ 863 "b\013CFC\0" \ 864 "b\012SEC\0" \ 865 "b\011SBD\0" \ 866 "b\010FSE\0" \ 867 "b\7NSS\0" \ 868 "b\6LTC\0" \ 869 "b\5LHRC\0" \ 870 "b\4PIND\0" \ 871 "b\3PPC\0" \ 872 "b\2CZC\0" \ 873 "b\1BNC\0" \ 874 "b\0AC64\0" \ 875 "\0" 876 #define XHCI_HCCV1_x_BITS \ 877 "\177\020" /* New bitmask */ \ 878 "f\020\020XECP\0" \ 879 "f\014\4MAXPSA\0" \ 880 "b\013CFC\0" \ 881 "b\012SEC\0" \ 882 "b\011SPC\0" \ 883 "b\010PAE\0" \ 884 "b\7NSS\0" \ 885 "b\6LTC\0" \ 886 "b\5LHRC\0" \ 887 "b\4PIND\0" \ 888 "b\3PPC\0" \ 889 "b\2CSZ\0" \ 890 "b\1BNC\0" \ 891 "b\0AC64\0" \ 892 "\0" 893 894 int 895 xhci_init(struct xhci_softc *sc) 896 { 897 bus_size_t bsz; 898 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 899 uint32_t pagesize, config; 900 int i = 0; 901 uint16_t hciversion; 902 uint8_t caplength; 903 904 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 905 906 /* Set up the bus struct for the usb 3 and usb 2 buses */ 907 sc->sc_bus.ub_methods = &xhci_bus_methods; 908 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 909 sc->sc_bus.ub_revision = USBREV_3_0; 910 sc->sc_bus.ub_usedma = true; 911 sc->sc_bus.ub_hcpriv = sc; 912 913 sc->sc_bus2.ub_methods = &xhci_bus_methods; 914 sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe); 915 sc->sc_bus2.ub_revision = USBREV_2_0; 916 sc->sc_bus2.ub_usedma = true; 917 sc->sc_bus2.ub_hcpriv = sc; 918 sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag; 919 920 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 921 caplength = XHCI_CAP_CAPLENGTH(cap); 922 hciversion = XHCI_CAP_HCIVERSION(cap); 923 924 if (hciversion < XHCI_HCIVERSION_0_96 || 925 hciversion > XHCI_HCIVERSION_1_0) { 926 aprint_normal_dev(sc->sc_dev, 927 "xHCI version %x.%x not known to be supported\n", 928 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 929 } else { 930 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 931 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 932 } 933 934 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 935 &sc->sc_cbh) != 0) { 936 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 937 return ENOMEM; 938 } 939 940 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 941 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 942 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 943 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 944 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 945 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 946 aprint_debug_dev(sc->sc_dev, 947 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 948 949 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 950 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 951 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 952 953 char sbuf[128]; 954 if (hciversion < XHCI_HCIVERSION_1_0) 955 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 956 else 957 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 958 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 959 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 960 961 /* default all ports to bus 0, i.e. usb 3 */ 962 sc->sc_ctlrportbus = kmem_zalloc( 963 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP); 964 sc->sc_ctlrportmap = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 965 966 /* controller port to bus roothub port map */ 967 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 968 sc->sc_rhportmap[j] = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 969 } 970 971 /* 972 * Process all Extended Capabilities 973 */ 974 xhci_ecp(sc, hcc); 975 976 bsz = XHCI_PORTSC(sc->sc_maxports); 977 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 978 &sc->sc_obh) != 0) { 979 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 980 return ENOMEM; 981 } 982 983 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 984 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 985 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 986 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 987 return ENOMEM; 988 } 989 990 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 991 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 992 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 993 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 994 return ENOMEM; 995 } 996 997 int rv; 998 rv = xhci_hc_reset(sc); 999 if (rv != 0) { 1000 return rv; 1001 } 1002 1003 if (sc->sc_vendor_init) 1004 sc->sc_vendor_init(sc); 1005 1006 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 1007 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 1008 pagesize = ffs(pagesize); 1009 if (pagesize == 0) { 1010 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 1011 return EIO; 1012 } 1013 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 1014 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 1015 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 1016 (uint32_t)sc->sc_maxslots); 1017 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 1018 1019 usbd_status err; 1020 1021 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 1022 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 1023 if (sc->sc_maxspbuf != 0) { 1024 err = usb_allocmem(&sc->sc_bus, 1025 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 1026 &sc->sc_spbufarray_dma); 1027 if (err) { 1028 aprint_error_dev(sc->sc_dev, 1029 "spbufarray init fail, err %d\n", err); 1030 return ENOMEM; 1031 } 1032 1033 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 1034 sc->sc_maxspbuf, KM_SLEEP); 1035 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 1036 for (i = 0; i < sc->sc_maxspbuf; i++) { 1037 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 1038 /* allocate contexts */ 1039 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 1040 sc->sc_pgsz, dma); 1041 if (err) { 1042 aprint_error_dev(sc->sc_dev, 1043 "spbufarray_dma init fail, err %d\n", err); 1044 rv = ENOMEM; 1045 goto bad1; 1046 } 1047 spbufarray[i] = htole64(DMAADDR(dma, 0)); 1048 usb_syncmem(dma, 0, sc->sc_pgsz, 1049 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1050 } 1051 1052 usb_syncmem(&sc->sc_spbufarray_dma, 0, 1053 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 1054 } 1055 1056 config = xhci_op_read_4(sc, XHCI_CONFIG); 1057 config &= ~0xFF; 1058 config |= sc->sc_maxslots & 0xFF; 1059 xhci_op_write_4(sc, XHCI_CONFIG, config); 1060 1061 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 1062 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 1063 if (err) { 1064 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 1065 err); 1066 rv = ENOMEM; 1067 goto bad1; 1068 } 1069 1070 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 1071 XHCI_EVENT_RING_SEGMENTS_ALIGN); 1072 if (err) { 1073 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 1074 err); 1075 rv = ENOMEM; 1076 goto bad2; 1077 } 1078 1079 usb_dma_t *dma; 1080 size_t size; 1081 size_t align; 1082 1083 dma = &sc->sc_eventst_dma; 1084 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 1085 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 1086 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 1087 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 1088 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1089 if (err) { 1090 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 1091 err); 1092 rv = ENOMEM; 1093 goto bad3; 1094 } 1095 1096 memset(KERNADDR(dma, 0), 0, size); 1097 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1098 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 1099 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 1100 KERNADDR(&sc->sc_eventst_dma, 0), 1101 sc->sc_eventst_dma.udma_block->size); 1102 1103 dma = &sc->sc_dcbaa_dma; 1104 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 1105 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 1106 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 1107 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1108 if (err) { 1109 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1110 rv = ENOMEM; 1111 goto bad4; 1112 } 1113 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 1114 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1115 KERNADDR(&sc->sc_dcbaa_dma, 0), 1116 sc->sc_dcbaa_dma.udma_block->size); 1117 1118 memset(KERNADDR(dma, 0), 0, size); 1119 if (sc->sc_maxspbuf != 0) { 1120 /* 1121 * DCBA entry 0 hold the scratchbuf array pointer. 1122 */ 1123 *(uint64_t *)KERNADDR(dma, 0) = 1124 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1125 } 1126 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1127 1128 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1129 KM_SLEEP); 1130 if (sc->sc_slots == NULL) { 1131 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1132 rv = ENOMEM; 1133 goto bad; 1134 } 1135 1136 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1137 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1138 if (sc->sc_xferpool == NULL) { 1139 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1140 err); 1141 rv = ENOMEM; 1142 goto bad; 1143 } 1144 1145 cv_init(&sc->sc_command_cv, "xhcicmd"); 1146 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1147 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1148 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1149 1150 struct xhci_erste *erst; 1151 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1152 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1153 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1154 erst[0].erste_3 = htole32(0); 1155 usb_syncmem(&sc->sc_eventst_dma, 0, 1156 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1157 1158 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1159 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1160 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1161 XHCI_ERDP_LO_BUSY); 1162 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1163 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1164 sc->sc_cr.xr_cs); 1165 1166 #if 0 1167 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1168 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1169 #endif 1170 1171 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1172 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1173 /* Intel xhci needs interrupt rate moderated. */ 1174 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1175 else 1176 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1177 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 1178 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1179 1180 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 1181 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1182 xhci_op_read_4(sc, XHCI_USBCMD)); 1183 1184 return 0; 1185 1186 bad: 1187 if (sc->sc_xferpool) { 1188 pool_cache_destroy(sc->sc_xferpool); 1189 sc->sc_xferpool = NULL; 1190 } 1191 1192 if (sc->sc_slots) { 1193 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1194 sc->sc_maxslots); 1195 sc->sc_slots = NULL; 1196 } 1197 1198 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1199 bad4: 1200 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1201 bad3: 1202 xhci_ring_free(sc, &sc->sc_er); 1203 bad2: 1204 xhci_ring_free(sc, &sc->sc_cr); 1205 i = sc->sc_maxspbuf; 1206 bad1: 1207 for (int j = 0; j < i; j++) 1208 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1209 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1210 1211 return rv; 1212 } 1213 1214 int 1215 xhci_intr(void *v) 1216 { 1217 struct xhci_softc * const sc = v; 1218 int ret = 0; 1219 1220 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1221 1222 if (sc == NULL) 1223 return 0; 1224 1225 mutex_spin_enter(&sc->sc_intr_lock); 1226 1227 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1228 goto done; 1229 1230 /* If we get an interrupt while polling, then just ignore it. */ 1231 if (sc->sc_bus.ub_usepolling) { 1232 #ifdef DIAGNOSTIC 1233 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1234 #endif 1235 goto done; 1236 } 1237 1238 ret = xhci_intr1(sc); 1239 done: 1240 mutex_spin_exit(&sc->sc_intr_lock); 1241 return ret; 1242 } 1243 1244 int 1245 xhci_intr1(struct xhci_softc * const sc) 1246 { 1247 uint32_t usbsts; 1248 uint32_t iman; 1249 1250 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1251 1252 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1253 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1254 #if 0 1255 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1256 return 0; 1257 } 1258 #endif 1259 xhci_op_write_4(sc, XHCI_USBSTS, 1260 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1261 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1262 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1263 1264 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1265 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1266 iman |= XHCI_IMAN_INTR_PEND; 1267 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1268 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1269 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1270 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1271 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1272 1273 usb_schedsoftintr(&sc->sc_bus); 1274 1275 return 1; 1276 } 1277 1278 /* 1279 * 3 port speed types used in USB stack 1280 * 1281 * usbdi speed 1282 * definition: USB_SPEED_* in usb.h 1283 * They are used in struct usbd_device in USB stack. 1284 * ioctl interface uses these values too. 1285 * port_status speed 1286 * definition: UPS_*_SPEED in usb.h 1287 * They are used in usb_port_status_t and valid only for USB 2.0. 1288 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1289 * of usb_port_status_ext_t indicates port speed. 1290 * Note that some 3.0 values overlap with 2.0 values. 1291 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1292 * means UPS_LOW_SPEED in HS.) 1293 * port status returned from hub also uses these values. 1294 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1295 * or more. 1296 * xspeed: 1297 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1298 * They are used in only slot context and PORTSC reg of xhci. 1299 * The difference between usbdi speed and xspeed is 1300 * that FS and LS values are swapped. 1301 */ 1302 1303 /* convert usbdi speed to xspeed */ 1304 static int 1305 xhci_speed2xspeed(int speed) 1306 { 1307 switch (speed) { 1308 case USB_SPEED_LOW: return 2; 1309 case USB_SPEED_FULL: return 1; 1310 default: return speed; 1311 } 1312 } 1313 1314 #if 0 1315 /* convert xspeed to usbdi speed */ 1316 static int 1317 xhci_xspeed2speed(int xspeed) 1318 { 1319 switch (xspeed) { 1320 case 1: return USB_SPEED_FULL; 1321 case 2: return USB_SPEED_LOW; 1322 default: return xspeed; 1323 } 1324 } 1325 #endif 1326 1327 /* convert xspeed to port status speed */ 1328 static int 1329 xhci_xspeed2psspeed(int xspeed) 1330 { 1331 switch (xspeed) { 1332 case 0: return 0; 1333 case 1: return UPS_FULL_SPEED; 1334 case 2: return UPS_LOW_SPEED; 1335 case 3: return UPS_HIGH_SPEED; 1336 default: return UPS_OTHER_SPEED; 1337 } 1338 } 1339 1340 /* 1341 * Construct input contexts and issue TRB to open pipe. 1342 */ 1343 static usbd_status 1344 xhci_configure_endpoint(struct usbd_pipe *pipe) 1345 { 1346 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1347 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1348 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1349 struct xhci_trb trb; 1350 usbd_status err; 1351 1352 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1353 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1354 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1355 pipe->up_endpoint->ue_edesc->bmAttributes); 1356 1357 /* XXX ensure input context is available? */ 1358 1359 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1360 1361 /* set up context */ 1362 xhci_setup_ctx(pipe); 1363 1364 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1365 sc->sc_ctxsz * 1); 1366 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1367 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1368 1369 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1370 trb.trb_2 = 0; 1371 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1372 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1373 1374 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1375 1376 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1377 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1378 sc->sc_ctxsz * 1); 1379 1380 return err; 1381 } 1382 1383 #if 0 1384 static usbd_status 1385 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1386 { 1387 #ifdef USB_DEBUG 1388 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1389 #endif 1390 1391 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1392 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1393 1394 return USBD_NORMAL_COMPLETION; 1395 } 1396 #endif 1397 1398 /* 4.6.8, 6.4.3.7 */ 1399 static usbd_status 1400 xhci_reset_endpoint_locked(struct usbd_pipe *pipe) 1401 { 1402 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1403 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1404 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1405 struct xhci_trb trb; 1406 usbd_status err; 1407 1408 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1409 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1410 1411 KASSERT(mutex_owned(&sc->sc_lock)); 1412 1413 trb.trb_0 = 0; 1414 trb.trb_2 = 0; 1415 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1416 XHCI_TRB_3_EP_SET(dci) | 1417 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1418 1419 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1420 1421 return err; 1422 } 1423 1424 static usbd_status 1425 xhci_reset_endpoint(struct usbd_pipe *pipe) 1426 { 1427 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1428 1429 mutex_enter(&sc->sc_lock); 1430 usbd_status ret = xhci_reset_endpoint_locked(pipe); 1431 mutex_exit(&sc->sc_lock); 1432 1433 return ret; 1434 } 1435 1436 /* 1437 * 4.6.9, 6.4.3.8 1438 * Stop execution of TDs on xfer ring. 1439 * Should be called with sc_lock held. 1440 */ 1441 static usbd_status 1442 xhci_stop_endpoint(struct usbd_pipe *pipe) 1443 { 1444 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1445 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1446 struct xhci_trb trb; 1447 usbd_status err; 1448 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1449 1450 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1451 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1452 1453 KASSERT(mutex_owned(&sc->sc_lock)); 1454 1455 trb.trb_0 = 0; 1456 trb.trb_2 = 0; 1457 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1458 XHCI_TRB_3_EP_SET(dci) | 1459 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1460 1461 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1462 1463 return err; 1464 } 1465 1466 /* 1467 * Set TR Dequeue Pointer. 1468 * xHCI 1.1 4.6.10 6.4.3.9 1469 * Purge all of the TRBs on ring and reinitialize ring. 1470 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1471 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1472 * error will be generated. 1473 */ 1474 static usbd_status 1475 xhci_set_dequeue_locked(struct usbd_pipe *pipe) 1476 { 1477 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1478 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1479 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1480 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1481 struct xhci_trb trb; 1482 usbd_status err; 1483 1484 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1485 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1486 1487 KASSERT(mutex_owned(&sc->sc_lock)); 1488 1489 xhci_host_dequeue(xr); 1490 1491 /* set DCS */ 1492 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1493 trb.trb_2 = 0; 1494 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1495 XHCI_TRB_3_EP_SET(dci) | 1496 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1497 1498 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1499 1500 return err; 1501 } 1502 1503 static usbd_status 1504 xhci_set_dequeue(struct usbd_pipe *pipe) 1505 { 1506 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1507 1508 mutex_enter(&sc->sc_lock); 1509 usbd_status ret = xhci_set_dequeue_locked(pipe); 1510 mutex_exit(&sc->sc_lock); 1511 1512 return ret; 1513 } 1514 1515 /* 1516 * Open new pipe: called from usbd_setup_pipe_flags. 1517 * Fills methods of pipe. 1518 * If pipe is not for ep0, calls configure_endpoint. 1519 */ 1520 static usbd_status 1521 xhci_open(struct usbd_pipe *pipe) 1522 { 1523 struct usbd_device * const dev = pipe->up_dev; 1524 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1525 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1526 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1527 1528 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1529 DPRINTFN(1, "addr %d depth %d port %d speed %d", dev->ud_addr, 1530 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1531 DPRINTFN(1, " dci %u type 0x%02x epaddr 0x%02x attr 0x%02x", 1532 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1533 ed->bmAttributes); 1534 DPRINTFN(1, " mps %u ival %u", UGETW(ed->wMaxPacketSize), ed->bInterval, 1535 0, 0); 1536 1537 if (sc->sc_dying) 1538 return USBD_IOERROR; 1539 1540 /* Root Hub */ 1541 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1542 switch (ed->bEndpointAddress) { 1543 case USB_CONTROL_ENDPOINT: 1544 pipe->up_methods = &roothub_ctrl_methods; 1545 break; 1546 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1547 pipe->up_methods = &xhci_root_intr_methods; 1548 break; 1549 default: 1550 pipe->up_methods = NULL; 1551 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1552 ed->bEndpointAddress, 0, 0, 0); 1553 return USBD_INVAL; 1554 } 1555 return USBD_NORMAL_COMPLETION; 1556 } 1557 1558 switch (xfertype) { 1559 case UE_CONTROL: 1560 pipe->up_methods = &xhci_device_ctrl_methods; 1561 break; 1562 case UE_ISOCHRONOUS: 1563 pipe->up_methods = &xhci_device_isoc_methods; 1564 return USBD_INVAL; 1565 break; 1566 case UE_BULK: 1567 pipe->up_methods = &xhci_device_bulk_methods; 1568 break; 1569 case UE_INTERRUPT: 1570 pipe->up_methods = &xhci_device_intr_methods; 1571 break; 1572 default: 1573 return USBD_IOERROR; 1574 break; 1575 } 1576 1577 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1578 return xhci_configure_endpoint(pipe); 1579 1580 return USBD_NORMAL_COMPLETION; 1581 } 1582 1583 /* 1584 * Closes pipe, called from usbd_kill_pipe via close methods. 1585 * If the endpoint to be closed is ep0, disable_slot. 1586 * Should be called with sc_lock held. 1587 */ 1588 static void 1589 xhci_close_pipe(struct usbd_pipe *pipe) 1590 { 1591 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1592 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1593 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1594 const u_int dci = xhci_ep_get_dci(ed); 1595 struct xhci_trb trb; 1596 uint32_t *cp; 1597 1598 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1599 1600 if (sc->sc_dying) 1601 return; 1602 1603 /* xs is uninitialized before xhci_init_slot */ 1604 if (xs == NULL || xs->xs_idx == 0) 1605 return; 1606 1607 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1608 1609 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1610 KASSERT(mutex_owned(&sc->sc_lock)); 1611 1612 if (pipe->up_dev->ud_depth == 0) 1613 return; 1614 1615 if (dci == XHCI_DCI_EP_CONTROL) { 1616 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1617 xhci_disable_slot(sc, xs->xs_idx); 1618 return; 1619 } 1620 1621 /* 1622 * This may fail in the case that xhci_close_pipe is called after 1623 * xhci_abort_xfer e.g. usbd_kill_pipe. 1624 */ 1625 (void)xhci_stop_endpoint(pipe); 1626 1627 /* 1628 * set appropriate bit to be dropped. 1629 * don't set DC bit to 1, otherwise all endpoints 1630 * would be deconfigured. 1631 */ 1632 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1633 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1634 cp[1] = htole32(0); 1635 1636 /* XXX should be most significant one, not dci? */ 1637 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1638 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1639 1640 /* configure ep context performs an implicit dequeue */ 1641 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 1642 1643 /* sync input contexts before they are read from memory */ 1644 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1645 1646 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1647 trb.trb_2 = 0; 1648 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1649 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1650 1651 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1652 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1653 } 1654 1655 /* 1656 * Abort transfer. 1657 * Should be called with sc_lock held. 1658 */ 1659 static void 1660 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1661 { 1662 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1663 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1664 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1665 1666 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1667 DPRINTFN(4, "xfer %p pipe %p status %d", 1668 xfer, xfer->ux_pipe, status, 0); 1669 1670 KASSERT(mutex_owned(&sc->sc_lock)); 1671 1672 if (sc->sc_dying) { 1673 /* If we're dying, just do the software part. */ 1674 DPRINTFN(4, "xfer %p dying %u", xfer, xfer->ux_status, 0, 0); 1675 xfer->ux_status = status; 1676 callout_stop(&xfer->ux_callout); 1677 usb_transfer_complete(xfer); 1678 return; 1679 } 1680 1681 /* 1682 * If an abort is already in progress then just wait for it to 1683 * complete and return. 1684 */ 1685 if (xfer->ux_hcflags & UXFER_ABORTING) { 1686 DPRINTFN(4, "already aborting", 0, 0, 0, 0); 1687 #ifdef DIAGNOSTIC 1688 if (status == USBD_TIMEOUT) 1689 DPRINTFN(4, "TIMEOUT while aborting", 0, 0, 0, 0); 1690 #endif 1691 /* Override the status which might be USBD_TIMEOUT. */ 1692 xfer->ux_status = status; 1693 DPRINTFN(4, "xfer %p waiting for abort to finish", xfer, 0, 0, 1694 0); 1695 xfer->ux_hcflags |= UXFER_ABORTWAIT; 1696 while (xfer->ux_hcflags & UXFER_ABORTING) 1697 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 1698 return; 1699 } 1700 xfer->ux_hcflags |= UXFER_ABORTING; 1701 1702 /* 1703 * Step 1: Stop xfer timeout timer. 1704 */ 1705 xfer->ux_status = status; 1706 callout_stop(&xfer->ux_callout); 1707 1708 /* 1709 * Step 2: Stop execution of TD on the ring. 1710 */ 1711 switch (xhci_get_epstate(sc, xs, dci)) { 1712 case XHCI_EPSTATE_HALTED: 1713 (void)xhci_reset_endpoint_locked(xfer->ux_pipe); 1714 break; 1715 case XHCI_EPSTATE_STOPPED: 1716 break; 1717 default: 1718 (void)xhci_stop_endpoint(xfer->ux_pipe); 1719 break; 1720 } 1721 #ifdef DIAGNOSTIC 1722 uint32_t epst = xhci_get_epstate(sc, xs, dci); 1723 if (epst != XHCI_EPSTATE_STOPPED) 1724 DPRINTFN(4, "dci %u not stopped %u", dci, epst, 0, 0); 1725 #endif 1726 1727 /* 1728 * Step 3: Remove any vestiges of the xfer from the ring. 1729 */ 1730 xhci_set_dequeue_locked(xfer->ux_pipe); 1731 1732 /* 1733 * Step 4: Notify completion to waiting xfers. 1734 */ 1735 int wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 1736 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 1737 usb_transfer_complete(xfer); 1738 if (wake) { 1739 cv_broadcast(&xfer->ux_hccv); 1740 } 1741 DPRINTFN(14, "end", 0, 0, 0, 0); 1742 1743 KASSERT(mutex_owned(&sc->sc_lock)); 1744 } 1745 1746 static void 1747 xhci_host_dequeue(struct xhci_ring * const xr) 1748 { 1749 /* When dequeueing the controller, update our struct copy too */ 1750 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1751 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1752 BUS_DMASYNC_PREWRITE); 1753 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1754 1755 xr->xr_ep = 0; 1756 xr->xr_cs = 1; 1757 } 1758 1759 /* 1760 * Recover STALLed endpoint. 1761 * xHCI 1.1 sect 4.10.2.1 1762 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1763 * all transfers on transfer ring. 1764 * These are done in thread context asynchronously. 1765 */ 1766 static void 1767 xhci_clear_endpoint_stall_async_task(void *cookie) 1768 { 1769 struct usbd_xfer * const xfer = cookie; 1770 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1771 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1772 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1773 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1774 1775 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1776 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1777 1778 xhci_reset_endpoint(xfer->ux_pipe); 1779 xhci_set_dequeue(xfer->ux_pipe); 1780 1781 mutex_enter(&sc->sc_lock); 1782 tr->is_halted = false; 1783 usb_transfer_complete(xfer); 1784 mutex_exit(&sc->sc_lock); 1785 DPRINTFN(4, "ends", 0, 0, 0, 0); 1786 } 1787 1788 static usbd_status 1789 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1790 { 1791 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1792 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1793 1794 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1795 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1796 1797 if (sc->sc_dying) { 1798 return USBD_IOERROR; 1799 } 1800 1801 usb_init_task(&xp->xp_async_task, 1802 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1803 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1804 DPRINTFN(4, "ends", 0, 0, 0, 0); 1805 1806 return USBD_NORMAL_COMPLETION; 1807 } 1808 1809 /* Process roothub port status/change events and notify to uhub_intr. */ 1810 static void 1811 xhci_rhpsc(struct xhci_softc * const sc, u_int ctlrport) 1812 { 1813 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1814 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1815 ctlrport, 0, 0); 1816 1817 if (ctlrport > sc->sc_maxports) 1818 return; 1819 1820 const size_t bn = xhci_ctlrport2bus(sc, ctlrport); 1821 const size_t rhp = xhci_ctlrport2rhport(sc, ctlrport); 1822 struct usbd_xfer * const xfer = sc->sc_intrxfer[bn]; 1823 1824 DPRINTFN(4, "xhci%d: bus %d bp %u xfer %p status change", 1825 device_unit(sc->sc_dev), bn, rhp, xfer); 1826 1827 if (xfer == NULL) 1828 return; 1829 1830 uint8_t *p = xfer->ux_buf; 1831 memset(p, 0, xfer->ux_length); 1832 p[rhp / NBBY] |= 1 << (rhp % NBBY); 1833 xfer->ux_actlen = xfer->ux_length; 1834 xfer->ux_status = USBD_NORMAL_COMPLETION; 1835 usb_transfer_complete(xfer); 1836 } 1837 1838 /* Process Transfer Events */ 1839 static void 1840 xhci_event_transfer(struct xhci_softc * const sc, 1841 const struct xhci_trb * const trb) 1842 { 1843 uint64_t trb_0; 1844 uint32_t trb_2, trb_3; 1845 uint8_t trbcode; 1846 u_int slot, dci; 1847 struct xhci_slot *xs; 1848 struct xhci_ring *xr; 1849 struct xhci_xfer *xx; 1850 struct usbd_xfer *xfer; 1851 usbd_status err; 1852 1853 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1854 1855 trb_0 = le64toh(trb->trb_0); 1856 trb_2 = le32toh(trb->trb_2); 1857 trb_3 = le32toh(trb->trb_3); 1858 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1859 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1860 dci = XHCI_TRB_3_EP_GET(trb_3); 1861 xs = &sc->sc_slots[slot]; 1862 xr = &xs->xs_ep[dci].xe_tr; 1863 1864 /* sanity check */ 1865 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1866 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1867 1868 int idx = 0; 1869 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1870 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1871 DPRINTFN(0, "invalid trb_0 0x%"PRIx64, trb_0, 0, 0, 0); 1872 return; 1873 } 1874 xx = xr->xr_cookies[idx]; 1875 1876 /* clear cookie of consumed TRB */ 1877 xr->xr_cookies[idx] = NULL; 1878 1879 /* 1880 * xx is NULL if pipe is opened but xfer is not started. 1881 * It happens when stopping idle pipe. 1882 */ 1883 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1884 DPRINTFN(1, "Ignore #%u: cookie %p cc %u dci %u", 1885 idx, xx, trbcode, dci); 1886 DPRINTFN(1, " orig TRB %"PRIx64" type %u", trb_0, 1887 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1888 0, 0); 1889 return; 1890 } 1891 } else { 1892 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1893 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1894 } 1895 /* XXX this may not happen */ 1896 if (xx == NULL) { 1897 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1898 return; 1899 } 1900 xfer = &xx->xx_xfer; 1901 /* XXX this may happen when detaching */ 1902 if (xfer == NULL) { 1903 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1904 xx, trb_0, 0, 0); 1905 return; 1906 } 1907 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1908 /* XXX I dunno why this happens */ 1909 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1910 1911 if (!xfer->ux_pipe->up_repeat && 1912 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1913 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1914 return; 1915 } 1916 1917 /* 4.11.5.2 Event Data TRB */ 1918 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1919 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1920 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1921 if ((trb_0 & 0x3) == 0x3) { 1922 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1923 } 1924 } 1925 1926 switch (trbcode) { 1927 case XHCI_TRB_ERROR_SHORT_PKT: 1928 case XHCI_TRB_ERROR_SUCCESS: 1929 /* 1930 * A ctrl transfer can generate two events if it has a Data 1931 * stage. A short data stage can be OK and should not 1932 * complete the transfer as the status stage needs to be 1933 * performed. 1934 * 1935 * Note: Data and Status stage events point at same xfer. 1936 * ux_actlen and ux_dmabuf will be passed to 1937 * usb_transfer_complete after the Status stage event. 1938 * 1939 * It can be distingished which stage generates the event: 1940 * + by checking least 3 bits of trb_0 if ED==1. 1941 * (see xhci_device_ctrl_start). 1942 * + by checking the type of original TRB if ED==0. 1943 * 1944 * In addition, intr, bulk, and isoc transfer currently 1945 * consists of single TD, so the "skip" is not needed. 1946 * ctrl xfer uses EVENT_DATA, and others do not. 1947 * Thus driver can switch the flow by checking ED bit. 1948 */ 1949 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1950 if (xfer->ux_actlen == 0) 1951 xfer->ux_actlen = xfer->ux_length - 1952 XHCI_TRB_2_REM_GET(trb_2); 1953 if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)) 1954 == XHCI_TRB_TYPE_DATA_STAGE) { 1955 return; 1956 } 1957 } else if ((trb_0 & 0x3) == 0x3) { 1958 return; 1959 } 1960 err = USBD_NORMAL_COMPLETION; 1961 break; 1962 case XHCI_TRB_ERROR_STOPPED: 1963 case XHCI_TRB_ERROR_LENGTH: 1964 case XHCI_TRB_ERROR_STOPPED_SHORT: 1965 /* 1966 * don't complete the transfer being aborted 1967 * as abort_xfer does instead. 1968 */ 1969 if (xfer->ux_hcflags & UXFER_ABORTING) { 1970 DPRINTFN(14, "ignore aborting xfer %p", xfer, 0, 0, 0); 1971 return; 1972 } 1973 err = USBD_CANCELLED; 1974 break; 1975 case XHCI_TRB_ERROR_STALL: 1976 case XHCI_TRB_ERROR_BABBLE: 1977 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1978 xr->is_halted = true; 1979 err = USBD_STALLED; 1980 /* 1981 * Stalled endpoints can be recoverd by issuing 1982 * command TRB TYPE_RESET_EP on xHCI instead of 1983 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1984 * on the endpoint. However, this function may be 1985 * called from softint context (e.g. from umass), 1986 * in that case driver gets KASSERT in cv_timedwait 1987 * in xhci_do_command. 1988 * To avoid this, this runs reset_endpoint and 1989 * usb_transfer_complete in usb task thread 1990 * asynchronously (and then umass issues clear 1991 * UF_ENDPOINT_HALT). 1992 */ 1993 xfer->ux_status = err; 1994 callout_stop(&xfer->ux_callout); 1995 xhci_clear_endpoint_stall_async(xfer); 1996 return; 1997 default: 1998 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1999 err = USBD_IOERROR; 2000 break; 2001 } 2002 xfer->ux_status = err; 2003 2004 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 2005 if ((trb_0 & 0x3) == 0x0) { 2006 callout_stop(&xfer->ux_callout); 2007 usb_transfer_complete(xfer); 2008 } 2009 } else { 2010 callout_stop(&xfer->ux_callout); 2011 usb_transfer_complete(xfer); 2012 } 2013 } 2014 2015 /* Process Command complete events */ 2016 static void 2017 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 2018 { 2019 uint64_t trb_0; 2020 uint32_t trb_2, trb_3; 2021 2022 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2023 2024 KASSERT(mutex_owned(&sc->sc_lock)); 2025 2026 trb_0 = le64toh(trb->trb_0); 2027 trb_2 = le32toh(trb->trb_2); 2028 trb_3 = le32toh(trb->trb_3); 2029 2030 if (trb_0 == sc->sc_command_addr) { 2031 sc->sc_resultpending = false; 2032 2033 sc->sc_result_trb.trb_0 = trb_0; 2034 sc->sc_result_trb.trb_2 = trb_2; 2035 sc->sc_result_trb.trb_3 = trb_3; 2036 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2037 XHCI_TRB_ERROR_SUCCESS) { 2038 DPRINTFN(1, "command completion " 2039 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 2040 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 2041 } 2042 cv_signal(&sc->sc_command_cv); 2043 } else { 2044 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 2045 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 2046 trb_2, trb_3); 2047 } 2048 } 2049 2050 /* 2051 * Process events. 2052 * called from xhci_softintr 2053 */ 2054 static void 2055 xhci_handle_event(struct xhci_softc * const sc, 2056 const struct xhci_trb * const trb) 2057 { 2058 uint64_t trb_0; 2059 uint32_t trb_2, trb_3; 2060 2061 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2062 2063 trb_0 = le64toh(trb->trb_0); 2064 trb_2 = le32toh(trb->trb_2); 2065 trb_3 = le32toh(trb->trb_3); 2066 2067 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2068 trb, trb_0, trb_2, trb_3); 2069 2070 /* 2071 * 4.11.3.1, 6.4.2.1 2072 * TRB Pointer is invalid for these completion codes. 2073 */ 2074 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2075 case XHCI_TRB_ERROR_RING_UNDERRUN: 2076 case XHCI_TRB_ERROR_RING_OVERRUN: 2077 case XHCI_TRB_ERROR_VF_RING_FULL: 2078 return; 2079 default: 2080 if (trb_0 == 0) { 2081 return; 2082 } 2083 break; 2084 } 2085 2086 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2087 case XHCI_TRB_EVENT_TRANSFER: 2088 xhci_event_transfer(sc, trb); 2089 break; 2090 case XHCI_TRB_EVENT_CMD_COMPLETE: 2091 xhci_event_cmd(sc, trb); 2092 break; 2093 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2094 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2095 break; 2096 default: 2097 break; 2098 } 2099 } 2100 2101 static void 2102 xhci_softintr(void *v) 2103 { 2104 struct usbd_bus * const bus = v; 2105 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2106 struct xhci_ring * const er = &sc->sc_er; 2107 struct xhci_trb *trb; 2108 int i, j, k; 2109 2110 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2111 2112 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2113 2114 i = er->xr_ep; 2115 j = er->xr_cs; 2116 2117 DPRINTFN(16, "er: xr_ep %d xr_cs %d", i, j, 0, 0); 2118 2119 while (1) { 2120 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2121 BUS_DMASYNC_POSTREAD); 2122 trb = &er->xr_trb[i]; 2123 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2124 2125 if (j != k) 2126 break; 2127 2128 xhci_handle_event(sc, trb); 2129 2130 i++; 2131 if (i == er->xr_ntrb) { 2132 i = 0; 2133 j ^= 1; 2134 } 2135 } 2136 2137 er->xr_ep = i; 2138 er->xr_cs = j; 2139 2140 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2141 XHCI_ERDP_LO_BUSY); 2142 2143 DPRINTFN(16, "ends", 0, 0, 0, 0); 2144 2145 return; 2146 } 2147 2148 static void 2149 xhci_poll(struct usbd_bus *bus) 2150 { 2151 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2152 2153 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2154 2155 mutex_spin_enter(&sc->sc_intr_lock); 2156 xhci_intr1(sc); 2157 mutex_spin_exit(&sc->sc_intr_lock); 2158 2159 return; 2160 } 2161 2162 static struct usbd_xfer * 2163 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2164 { 2165 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2166 struct usbd_xfer *xfer; 2167 2168 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2169 2170 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 2171 if (xfer != NULL) { 2172 memset(xfer, 0, sizeof(struct xhci_xfer)); 2173 #ifdef DIAGNOSTIC 2174 xfer->ux_state = XFER_BUSY; 2175 #endif 2176 } 2177 2178 return xfer; 2179 } 2180 2181 static void 2182 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2183 { 2184 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2185 2186 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2187 2188 #ifdef DIAGNOSTIC 2189 if (xfer->ux_state != XFER_BUSY) { 2190 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 2191 xfer, xfer->ux_state, 0, 0); 2192 } 2193 xfer->ux_state = XFER_FREE; 2194 #endif 2195 pool_cache_put(sc->sc_xferpool, xfer); 2196 } 2197 2198 static void 2199 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2200 { 2201 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2202 2203 *lock = &sc->sc_lock; 2204 } 2205 2206 extern uint32_t usb_cookie_no; 2207 2208 /* 2209 * xHCI 4.3 2210 * Called when uhub_explore finds a new device (via usbd_new_device). 2211 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2212 * This function does: 2213 * Allocate and construct dev structure of default endpoint (ep0). 2214 * Allocate and open pipe of ep0. 2215 * Enable slot and initialize slot context. 2216 * Set Address. 2217 * Read initial device descriptor. 2218 * Determine initial MaxPacketSize (mps) by speed. 2219 * Read full device descriptor. 2220 * Register this device. 2221 * Finally state of device transitions ADDRESSED. 2222 */ 2223 static usbd_status 2224 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2225 int speed, int port, struct usbd_port *up) 2226 { 2227 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2228 struct usbd_device *dev; 2229 usbd_status err; 2230 usb_device_descriptor_t *dd; 2231 struct xhci_slot *xs; 2232 uint32_t *cp; 2233 2234 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2235 DPRINTFN(4, "port %u depth %u speed %u up %p", port, depth, speed, up); 2236 2237 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2238 if (dev == NULL) 2239 return USBD_NOMEM; 2240 2241 dev->ud_bus = bus; 2242 dev->ud_quirks = &usbd_no_quirk; 2243 dev->ud_addr = 0; 2244 dev->ud_ddesc.bMaxPacketSize = 0; 2245 dev->ud_depth = depth; 2246 dev->ud_powersrc = up; 2247 dev->ud_myhub = up->up_parent; 2248 dev->ud_speed = speed; 2249 dev->ud_langid = USBD_NOLANG; 2250 dev->ud_cookie.cookie = ++usb_cookie_no; 2251 2252 /* Set up default endpoint handle. */ 2253 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2254 /* doesn't matter, just don't let it uninitialized */ 2255 dev->ud_ep0.ue_toggle = 0; 2256 2257 /* Set up default endpoint descriptor. */ 2258 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2259 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2260 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2261 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2262 dev->ud_ep0desc.bInterval = 0; 2263 2264 /* 4.3, 4.8.2.1 */ 2265 switch (speed) { 2266 case USB_SPEED_SUPER: 2267 case USB_SPEED_SUPER_PLUS: 2268 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2269 break; 2270 case USB_SPEED_FULL: 2271 /* XXX using 64 as initial mps of ep0 in FS */ 2272 case USB_SPEED_HIGH: 2273 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2274 break; 2275 case USB_SPEED_LOW: 2276 default: 2277 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2278 break; 2279 } 2280 2281 up->up_dev = dev; 2282 2283 /* Establish the default pipe. */ 2284 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2285 &dev->ud_pipe0); 2286 if (err) { 2287 goto bad; 2288 } 2289 2290 dd = &dev->ud_ddesc; 2291 2292 if (depth == 0 && port == 0) { 2293 KASSERT(bus->ub_devices[USB_ROOTHUB_INDEX] == NULL); 2294 bus->ub_devices[USB_ROOTHUB_INDEX] = dev; 2295 err = usbd_get_initial_ddesc(dev, dd); 2296 if (err) { 2297 DPRINTFN(1, "get_initial_ddesc %u", err, 0, 0, 0); 2298 goto bad; 2299 } 2300 2301 err = usbd_reload_device_desc(dev); 2302 if (err) { 2303 DPRINTFN(1, "reload desc %u", err, 0, 0, 0); 2304 goto bad; 2305 } 2306 } else { 2307 uint8_t slot = 0; 2308 2309 /* 4.3.2 */ 2310 err = xhci_enable_slot(sc, &slot); 2311 if (err) { 2312 DPRINTFN(1, "enable slot %u", err, 0, 0, 0); 2313 goto bad; 2314 } 2315 2316 xs = &sc->sc_slots[slot]; 2317 dev->ud_hcpriv = xs; 2318 2319 /* 4.3.3 initialize slot structure */ 2320 err = xhci_init_slot(dev, slot); 2321 if (err) { 2322 DPRINTFN(1, "init slot %u", err, 0, 0, 0); 2323 dev->ud_hcpriv = NULL; 2324 /* 2325 * We have to disable_slot here because 2326 * xs->xs_idx == 0 when xhci_init_slot fails, 2327 * in that case usbd_remove_dev won't work. 2328 */ 2329 mutex_enter(&sc->sc_lock); 2330 xhci_disable_slot(sc, slot); 2331 mutex_exit(&sc->sc_lock); 2332 goto bad; 2333 } 2334 2335 /* 4.3.4 Address Assignment */ 2336 err = xhci_set_address(dev, slot, false); 2337 if (err) { 2338 DPRINTFN(1, "set address w/o bsr %u", err, 0, 0, 0); 2339 goto bad; 2340 } 2341 2342 /* Allow device time to set new address */ 2343 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2344 2345 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2346 //hexdump("slot context", cp, sc->sc_ctxsz); 2347 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(cp[3]); 2348 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2349 /* 2350 * XXX ensure we know when the hardware does something 2351 * we can't yet cope with 2352 */ 2353 KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr); 2354 dev->ud_addr = addr; 2355 2356 KASSERTMSG(bus->ub_devices[usb_addr2dindex(dev->ud_addr)] == NULL, 2357 "addr %d already allocated", dev->ud_addr); 2358 /* 2359 * The root hub is given its own slot 2360 */ 2361 bus->ub_devices[usb_addr2dindex(dev->ud_addr)] = dev; 2362 2363 err = usbd_get_initial_ddesc(dev, dd); 2364 if (err) { 2365 DPRINTFN(1, "get_initial_ddesc %u", err, 0, 0, 0); 2366 goto bad; 2367 } 2368 2369 /* 4.8.2.1 */ 2370 if (USB_IS_SS(speed)) { 2371 if (dd->bMaxPacketSize != 9) { 2372 printf("%s: invalid mps 2^%u for SS ep0," 2373 " using 512\n", 2374 device_xname(sc->sc_dev), 2375 dd->bMaxPacketSize); 2376 dd->bMaxPacketSize = 9; 2377 } 2378 USETW(dev->ud_ep0desc.wMaxPacketSize, 2379 (1 << dd->bMaxPacketSize)); 2380 } else 2381 USETW(dev->ud_ep0desc.wMaxPacketSize, 2382 dd->bMaxPacketSize); 2383 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2384 err = xhci_update_ep0_mps(sc, xs, 2385 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2386 if (err) { 2387 DPRINTFN(1, "update mps of ep0 %u", err, 0, 0, 0); 2388 goto bad; 2389 } 2390 2391 err = usbd_reload_device_desc(dev); 2392 if (err) { 2393 DPRINTFN(1, "reload desc %u", err, 0, 0, 0); 2394 goto bad; 2395 } 2396 } 2397 2398 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2399 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2400 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2401 dd->bDeviceClass, dd->bDeviceSubClass, 2402 dd->bDeviceProtocol, 0); 2403 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2404 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2405 dev->ud_speed); 2406 2407 usbd_get_device_strings(dev); 2408 2409 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2410 2411 if (depth == 0 && port == 0) { 2412 usbd_attach_roothub(parent, dev); 2413 DPRINTFN(1, "root hub %p", dev, 0, 0, 0); 2414 return USBD_NORMAL_COMPLETION; 2415 } 2416 2417 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2418 bad: 2419 if (err != USBD_NORMAL_COMPLETION) { 2420 usbd_remove_device(dev, up); 2421 } 2422 2423 return err; 2424 } 2425 2426 static usbd_status 2427 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2428 size_t ntrb, size_t align) 2429 { 2430 usbd_status err; 2431 size_t size = ntrb * XHCI_TRB_SIZE; 2432 2433 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2434 2435 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2436 if (err) 2437 return err; 2438 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2439 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2440 xr->xr_trb = xhci_ring_trbv(xr, 0); 2441 xr->xr_ntrb = ntrb; 2442 xr->is_halted = false; 2443 xhci_host_dequeue(xr); 2444 2445 return USBD_NORMAL_COMPLETION; 2446 } 2447 2448 static void 2449 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2450 { 2451 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2452 mutex_destroy(&xr->xr_lock); 2453 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2454 } 2455 2456 static void 2457 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2458 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2459 { 2460 size_t i; 2461 u_int ri; 2462 u_int cs; 2463 uint64_t parameter; 2464 uint32_t status; 2465 uint32_t control; 2466 2467 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2468 2469 KASSERTMSG(ntrbs <= XHCI_XFER_NTRB, "ntrbs %zu", ntrbs); 2470 for (i = 0; i < ntrbs; i++) { 2471 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2472 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2473 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2474 KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2475 XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3); 2476 } 2477 2478 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2479 2480 ri = xr->xr_ep; 2481 cs = xr->xr_cs; 2482 2483 /* 2484 * Although the xhci hardware can do scatter/gather dma from 2485 * arbitrary sized buffers, there is a non-obvious restriction 2486 * that a LINK trb is only allowed at the end of a burst of 2487 * transfers - which might be 16kB. 2488 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2489 * The simple solution is not to allow a LINK trb in the middle 2490 * of anything - as here. 2491 * XXX: (dsl) There are xhci controllers out there (eg some made by 2492 * ASMedia) that seem to lock up if they process a LINK trb but 2493 * cannot process the linked-to trb yet. 2494 * The code should write the 'cycle' bit on the link trb AFTER 2495 * adding the other trb. 2496 */ 2497 if (ri + ntrbs >= (xr->xr_ntrb - 1)) { 2498 parameter = xhci_ring_trbp(xr, 0); 2499 status = 0; 2500 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2501 XHCI_TRB_3_TC_BIT | (cs ? XHCI_TRB_3_CYCLE_BIT : 0); 2502 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2503 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2504 BUS_DMASYNC_PREWRITE); 2505 xr->xr_cookies[ri] = NULL; 2506 xr->xr_ep = 0; 2507 xr->xr_cs ^= 1; 2508 ri = xr->xr_ep; 2509 cs = xr->xr_cs; 2510 } 2511 2512 ri++; 2513 2514 /* Write any subsequent TRB first */ 2515 for (i = 1; i < ntrbs; i++) { 2516 parameter = trbs[i].trb_0; 2517 status = trbs[i].trb_2; 2518 control = trbs[i].trb_3; 2519 2520 if (cs) { 2521 control |= XHCI_TRB_3_CYCLE_BIT; 2522 } else { 2523 control &= ~XHCI_TRB_3_CYCLE_BIT; 2524 } 2525 2526 xhci_trb_put(&xr->xr_trb[ri], parameter, status, control); 2527 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * ri, XHCI_TRB_SIZE * 1, 2528 BUS_DMASYNC_PREWRITE); 2529 xr->xr_cookies[ri] = cookie; 2530 ri++; 2531 } 2532 2533 /* Write the first TRB last */ 2534 i = 0; 2535 parameter = trbs[i].trb_0; 2536 status = trbs[i].trb_2; 2537 control = trbs[i].trb_3; 2538 2539 if (xr->xr_cs) { 2540 control |= XHCI_TRB_3_CYCLE_BIT; 2541 } else { 2542 control &= ~XHCI_TRB_3_CYCLE_BIT; 2543 } 2544 2545 xhci_trb_put(&xr->xr_trb[xr->xr_ep], parameter, status, control); 2546 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * xr->xr_ep, XHCI_TRB_SIZE * 1, 2547 BUS_DMASYNC_PREWRITE); 2548 xr->xr_cookies[xr->xr_ep] = cookie; 2549 2550 xr->xr_ep = ri; 2551 xr->xr_cs = cs; 2552 2553 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2554 } 2555 2556 /* 2557 * Stop execution commands, purge all commands on command ring, and 2558 * rewind dequeue pointer. 2559 */ 2560 static void 2561 xhci_abort_command(struct xhci_softc *sc) 2562 { 2563 struct xhci_ring * const cr = &sc->sc_cr; 2564 uint64_t crcr; 2565 int i; 2566 2567 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2568 DPRINTFN(14, "command %#"PRIx64" timeout, aborting", 2569 sc->sc_command_addr, 0, 0, 0); 2570 2571 mutex_enter(&cr->xr_lock); 2572 2573 /* 4.6.1.2 Aborting a Command */ 2574 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2575 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2576 2577 for (i = 0; i < 500; i++) { 2578 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2579 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2580 break; 2581 usb_delay_ms(&sc->sc_bus, 1); 2582 } 2583 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2584 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2585 /* reset HC here? */ 2586 } 2587 2588 /* reset command ring dequeue pointer */ 2589 cr->xr_ep = 0; 2590 cr->xr_cs = 1; 2591 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2592 2593 mutex_exit(&cr->xr_lock); 2594 } 2595 2596 /* 2597 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2598 * Command completion is notified by cv_signal from xhci_event_cmd() 2599 * (called from xhci_softint), or timed-out. 2600 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2601 * then do_command examines it. 2602 */ 2603 static usbd_status 2604 xhci_do_command_locked(struct xhci_softc * const sc, 2605 struct xhci_trb * const trb, int timeout) 2606 { 2607 struct xhci_ring * const cr = &sc->sc_cr; 2608 usbd_status err; 2609 2610 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2611 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2612 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2613 2614 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2615 KASSERT(mutex_owned(&sc->sc_lock)); 2616 2617 while (sc->sc_command_addr != 0) 2618 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 2619 2620 /* 2621 * If enqueue pointer points at last of ring, it's Link TRB, 2622 * command TRB will be stored in 0th TRB. 2623 */ 2624 if (cr->xr_ep == cr->xr_ntrb - 1) 2625 sc->sc_command_addr = xhci_ring_trbp(cr, 0); 2626 else 2627 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2628 2629 sc->sc_resultpending = true; 2630 2631 mutex_enter(&cr->xr_lock); 2632 xhci_ring_put(sc, cr, NULL, trb, 1); 2633 mutex_exit(&cr->xr_lock); 2634 2635 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2636 2637 while (sc->sc_resultpending) { 2638 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2639 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2640 xhci_abort_command(sc); 2641 err = USBD_TIMEOUT; 2642 goto timedout; 2643 } 2644 } 2645 2646 trb->trb_0 = sc->sc_result_trb.trb_0; 2647 trb->trb_2 = sc->sc_result_trb.trb_2; 2648 trb->trb_3 = sc->sc_result_trb.trb_3; 2649 2650 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2651 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2652 2653 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2654 case XHCI_TRB_ERROR_SUCCESS: 2655 err = USBD_NORMAL_COMPLETION; 2656 break; 2657 default: 2658 case 192 ... 223: 2659 err = USBD_IOERROR; 2660 break; 2661 case 224 ... 255: 2662 err = USBD_NORMAL_COMPLETION; 2663 break; 2664 } 2665 2666 timedout: 2667 sc->sc_resultpending = false; 2668 sc->sc_command_addr = 0; 2669 cv_broadcast(&sc->sc_cmdbusy_cv); 2670 2671 return err; 2672 } 2673 2674 static usbd_status 2675 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2676 int timeout) 2677 { 2678 2679 mutex_enter(&sc->sc_lock); 2680 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2681 mutex_exit(&sc->sc_lock); 2682 2683 return ret; 2684 } 2685 2686 static usbd_status 2687 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2688 { 2689 struct xhci_trb trb; 2690 usbd_status err; 2691 2692 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2693 2694 trb.trb_0 = 0; 2695 trb.trb_2 = 0; 2696 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2697 2698 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2699 if (err != USBD_NORMAL_COMPLETION) { 2700 return err; 2701 } 2702 2703 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2704 2705 return err; 2706 } 2707 2708 /* 2709 * xHCI 4.6.4 2710 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2711 * All endpoints in the slot should be stopped. 2712 * Should be called with sc_lock held. 2713 */ 2714 static usbd_status 2715 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2716 { 2717 struct xhci_trb trb; 2718 struct xhci_slot *xs; 2719 usbd_status err; 2720 2721 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2722 2723 if (sc->sc_dying) 2724 return USBD_IOERROR; 2725 2726 trb.trb_0 = 0; 2727 trb.trb_2 = 0; 2728 trb.trb_3 = htole32( 2729 XHCI_TRB_3_SLOT_SET(slot) | 2730 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2731 2732 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2733 2734 if (!err) { 2735 xs = &sc->sc_slots[slot]; 2736 if (xs->xs_idx != 0) { 2737 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2738 xhci_set_dcba(sc, 0, slot); 2739 memset(xs, 0, sizeof(*xs)); 2740 } 2741 } 2742 2743 return err; 2744 } 2745 2746 /* 2747 * Set address of device and transition slot state from ENABLED to ADDRESSED 2748 * if Block Setaddress Request (BSR) is false. 2749 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2750 * see xHCI 1.1 4.5.3, 3.3.4 2751 * Should be called without sc_lock held. 2752 */ 2753 static usbd_status 2754 xhci_address_device(struct xhci_softc * const sc, 2755 uint64_t icp, uint8_t slot_id, bool bsr) 2756 { 2757 struct xhci_trb trb; 2758 usbd_status err; 2759 2760 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2761 2762 trb.trb_0 = icp; 2763 trb.trb_2 = 0; 2764 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2765 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2766 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2767 2768 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2769 2770 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2771 err = USBD_NO_ADDR; 2772 2773 return err; 2774 } 2775 2776 static usbd_status 2777 xhci_update_ep0_mps(struct xhci_softc * const sc, 2778 struct xhci_slot * const xs, u_int mps) 2779 { 2780 struct xhci_trb trb; 2781 usbd_status err; 2782 uint32_t * cp; 2783 2784 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2785 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2786 2787 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2788 cp[0] = htole32(0); 2789 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2790 2791 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2792 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2793 2794 /* sync input contexts before they are read from memory */ 2795 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2796 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2797 sc->sc_ctxsz * 4); 2798 2799 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2800 trb.trb_2 = 0; 2801 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2802 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2803 2804 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2805 return err; 2806 } 2807 2808 static void 2809 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2810 { 2811 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2812 2813 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2814 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2815 &dcbaa[si], dcba, si, 0); 2816 2817 dcbaa[si] = htole64(dcba); 2818 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2819 BUS_DMASYNC_PREWRITE); 2820 } 2821 2822 /* 2823 * Allocate device and input context DMA buffer, and 2824 * TRB DMA buffer for each endpoint. 2825 */ 2826 static usbd_status 2827 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2828 { 2829 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2830 struct xhci_slot *xs; 2831 usbd_status err; 2832 u_int dci; 2833 2834 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2835 DPRINTFN(4, "slot %u", slot, 0, 0, 0); 2836 2837 xs = &sc->sc_slots[slot]; 2838 2839 /* allocate contexts */ 2840 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2841 &xs->xs_dc_dma); 2842 if (err) 2843 return err; 2844 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2845 2846 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2847 &xs->xs_ic_dma); 2848 if (err) 2849 goto bad1; 2850 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2851 2852 for (dci = 0; dci < 32; dci++) { 2853 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2854 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2855 if (dci == XHCI_DCI_SLOT) 2856 continue; 2857 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2858 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2859 if (err) { 2860 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2861 goto bad2; 2862 } 2863 } 2864 2865 bad2: 2866 if (err == USBD_NORMAL_COMPLETION) { 2867 xs->xs_idx = slot; 2868 } else { 2869 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2870 } 2871 2872 return err; 2873 2874 bad1: 2875 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2876 xs->xs_idx = 0; 2877 return err; 2878 } 2879 2880 static void 2881 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2882 int end_dci) 2883 { 2884 u_int dci; 2885 2886 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2887 DPRINTFN(4, "slot %u start %u end %u", xs->xs_idx, start_dci, end_dci, 2888 0); 2889 2890 for (dci = start_dci; dci < end_dci; dci++) { 2891 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2892 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2893 } 2894 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2895 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2896 xs->xs_idx = 0; 2897 } 2898 2899 /* 2900 * Setup slot context, set Device Context Base Address, and issue 2901 * Set Address Device command. 2902 */ 2903 static usbd_status 2904 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 2905 { 2906 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2907 struct xhci_slot *xs; 2908 usbd_status err; 2909 2910 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2911 DPRINTFN(4, "slot %u bsr %u", slot, bsr, 0, 0); 2912 2913 xs = &sc->sc_slots[slot]; 2914 2915 xhci_setup_ctx(dev->ud_pipe0); 2916 2917 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2918 sc->sc_ctxsz * 3); 2919 2920 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2921 2922 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 2923 2924 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2925 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2926 sc->sc_ctxsz * 2); 2927 2928 return err; 2929 } 2930 2931 /* 2932 * 4.8.2, 6.2.3.2 2933 * construct slot/endpoint context parameters and do syncmem 2934 */ 2935 static void 2936 xhci_setup_ctx(struct usbd_pipe *pipe) 2937 { 2938 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2939 struct usbd_device *dev = pipe->up_dev; 2940 struct xhci_slot * const xs = dev->ud_hcpriv; 2941 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2942 const u_int dci = xhci_ep_get_dci(ed); 2943 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2944 uint32_t *cp; 2945 uint16_t mps = UGETW(ed->wMaxPacketSize); 2946 uint8_t speed = dev->ud_speed; 2947 uint8_t ival = ed->bInterval; 2948 2949 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2950 DPRINTFN(4, "pipe %p: slot %u dci %u speed %u", pipe, xs->xs_idx, dci, 2951 speed); 2952 2953 /* set up initial input control context */ 2954 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2955 cp[0] = htole32(0); 2956 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 2957 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2958 cp[7] = htole32(0); 2959 2960 /* set up input slot context */ 2961 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2962 cp[0] = 2963 XHCI_SCTX_0_CTX_NUM_SET(dci) | 2964 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 2965 cp[1] = 0; 2966 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2967 cp[3] = 0; 2968 xhci_setup_route(pipe, cp); 2969 xhci_setup_tthub(pipe, cp); 2970 2971 cp[0] = htole32(cp[0]); 2972 cp[1] = htole32(cp[1]); 2973 cp[2] = htole32(cp[2]); 2974 cp[3] = htole32(cp[3]); 2975 2976 /* set up input endpoint context */ 2977 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 2978 cp[0] = 2979 XHCI_EPCTX_0_EPSTATE_SET(0) | 2980 XHCI_EPCTX_0_MULT_SET(0) | 2981 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2982 XHCI_EPCTX_0_LSA_SET(0) | 2983 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 2984 cp[1] = 2985 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 2986 XHCI_EPCTX_1_HID_SET(0) | 2987 XHCI_EPCTX_1_MAXB_SET(0); 2988 2989 if (xfertype != UE_ISOCHRONOUS) 2990 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 2991 2992 if (xfertype == UE_CONTROL) 2993 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 2994 else if (USB_IS_SS(speed)) 2995 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 2996 else 2997 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 2998 2999 xhci_setup_maxburst(pipe, cp); 3000 3001 switch (xfertype) { 3002 case UE_CONTROL: 3003 break; 3004 case UE_BULK: 3005 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 3006 break; 3007 case UE_INTERRUPT: 3008 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3009 ival = pipe->up_interval; 3010 3011 ival = xhci_bival2ival(ival, speed); 3012 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3013 break; 3014 case UE_ISOCHRONOUS: 3015 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3016 ival = pipe->up_interval; 3017 3018 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 3019 if (speed == USB_SPEED_FULL) 3020 ival += 3; /* 1ms -> 125us */ 3021 ival--; 3022 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3023 break; 3024 default: 3025 break; 3026 } 3027 DPRINTFN(4, "setting ival %u MaxBurst %#x", 3028 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 3029 3030 /* rewind TR dequeue pointer in xHC */ 3031 /* can't use xhci_ep_get_dci() yet? */ 3032 *(uint64_t *)(&cp[2]) = htole64( 3033 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 3034 XHCI_EPCTX_2_DCS_SET(1)); 3035 3036 cp[0] = htole32(cp[0]); 3037 cp[1] = htole32(cp[1]); 3038 cp[4] = htole32(cp[4]); 3039 3040 /* rewind TR dequeue pointer in driver */ 3041 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 3042 mutex_enter(&xr->xr_lock); 3043 xhci_host_dequeue(xr); 3044 mutex_exit(&xr->xr_lock); 3045 3046 /* sync input contexts before they are read from memory */ 3047 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3048 } 3049 3050 /* 3051 * Setup route string and roothub port of given device for slot context 3052 */ 3053 static void 3054 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 3055 { 3056 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3057 struct usbd_device *dev = pipe->up_dev; 3058 struct usbd_port *up = dev->ud_powersrc; 3059 struct usbd_device *hub; 3060 struct usbd_device *adev; 3061 uint8_t rhport = 0; 3062 uint32_t route = 0; 3063 3064 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3065 3066 /* Locate root hub port and Determine route string */ 3067 /* 4.3.3 route string does not include roothub port */ 3068 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 3069 uint32_t dep; 3070 3071 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 3072 hub, hub->ud_depth, hub->ud_powersrc, 3073 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 3074 3075 if (hub->ud_powersrc == NULL) 3076 break; 3077 dep = hub->ud_depth; 3078 if (dep == 0) 3079 break; 3080 rhport = hub->ud_powersrc->up_portno; 3081 if (dep > USB_HUB_MAX_DEPTH) 3082 continue; 3083 3084 route |= 3085 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 3086 << ((dep - 1) * 4); 3087 } 3088 route = route >> 4; 3089 size_t bn = hub == sc->sc_bus.ub_roothub ? 0 : 1; 3090 3091 /* Locate port on upstream high speed hub */ 3092 for (adev = dev, hub = up->up_parent; 3093 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 3094 adev = hub, hub = hub->ud_myhub) 3095 ; 3096 if (hub) { 3097 int p; 3098 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 3099 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 3100 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 3101 goto found; 3102 } 3103 } 3104 panic("%s: cannot find HS port", __func__); 3105 found: 3106 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 3107 } else { 3108 dev->ud_myhsport = NULL; 3109 } 3110 3111 const size_t ctlrport = xhci_rhport2ctlrport(sc, bn, rhport); 3112 3113 DPRINTFN(4, "rhport %u ctlrport %u Route %05x hub %p", rhport, 3114 ctlrport, route, hub); 3115 3116 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 3117 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(ctlrport); 3118 } 3119 3120 /* 3121 * Setup whether device is hub, whether device uses MTT, and 3122 * TT informations if it uses MTT. 3123 */ 3124 static void 3125 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 3126 { 3127 struct usbd_device *dev = pipe->up_dev; 3128 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 3129 uint32_t speed = dev->ud_speed; 3130 uint8_t tthubslot, ttportnum; 3131 bool ishub; 3132 bool usemtt; 3133 3134 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3135 3136 /* 3137 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 3138 * tthubslot: 3139 * This is the slot ID of parent HS hub 3140 * if LS/FS device is connected && connected through HS hub. 3141 * This is 0 if device is not LS/FS device || 3142 * parent hub is not HS hub || 3143 * attached to root hub. 3144 * ttportnum: 3145 * This is the downstream facing port of parent HS hub 3146 * if LS/FS device is connected. 3147 * This is 0 if device is not LS/FS device || 3148 * parent hub is not HS hub || 3149 * attached to root hub. 3150 */ 3151 if (dev->ud_myhsport != NULL && 3152 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3153 (dev->ud_myhub != NULL && 3154 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3155 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 3156 ttportnum = dev->ud_myhsport->up_portno; 3157 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 3158 } else { 3159 ttportnum = 0; 3160 tthubslot = 0; 3161 } 3162 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 3163 dev->ud_myhsport, ttportnum, tthubslot, 0); 3164 3165 /* ishub is valid after reading UDESC_DEVICE */ 3166 ishub = (dd->bDeviceClass == UDCLASS_HUB); 3167 3168 /* dev->ud_hub is valid after reading UDESC_HUB */ 3169 if (ishub && dev->ud_hub) { 3170 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 3171 uint8_t ttt = 3172 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 3173 3174 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 3175 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 3176 DPRINTFN(4, "nports=%d ttt=%d", hd->bNbrPorts, ttt, 0, 0); 3177 } 3178 3179 #define IS_TTHUB(dd) \ 3180 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 3181 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 3182 3183 /* 3184 * MTT flag is set if 3185 * 1. this is HS hub && MTT is enabled 3186 * or 3187 * 2. this is not hub && this is LS or FS device && 3188 * MTT of parent HS hub (and its parent, too) is enabled 3189 */ 3190 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 3191 usemtt = true; 3192 else if (!ishub && 3193 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 3194 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3195 (dev->ud_myhub != NULL && 3196 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3197 dev->ud_myhsport != NULL && 3198 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 3199 usemtt = true; 3200 else 3201 usemtt = false; 3202 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 3203 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 3204 3205 #undef IS_TTHUB 3206 3207 cp[0] |= 3208 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 3209 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 3210 cp[2] |= 3211 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 3212 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 3213 } 3214 3215 /* set up params for periodic endpoint */ 3216 static void 3217 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 3218 { 3219 struct usbd_device *dev = pipe->up_dev; 3220 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3221 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3222 usbd_desc_iter_t iter; 3223 const usb_cdc_descriptor_t *cdcd; 3224 uint32_t maxb = 0; 3225 uint16_t mps = UGETW(ed->wMaxPacketSize); 3226 uint8_t speed = dev->ud_speed; 3227 uint8_t ep; 3228 3229 /* config desc is NULL when opening ep0 */ 3230 if (dev == NULL || dev->ud_cdesc == NULL) 3231 goto no_cdcd; 3232 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 3233 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 3234 if (cdcd == NULL) 3235 goto no_cdcd; 3236 usb_desc_iter_init(dev, &iter); 3237 iter.cur = (const void *)cdcd; 3238 3239 /* find endpoint_ss_comp desc for ep of this pipe */ 3240 for (ep = 0;;) { 3241 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 3242 if (cdcd == NULL) 3243 break; 3244 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 3245 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 3246 bEndpointAddress; 3247 if (UE_GET_ADDR(ep) == 3248 UE_GET_ADDR(ed->bEndpointAddress)) { 3249 cdcd = (const usb_cdc_descriptor_t *) 3250 usb_desc_iter_next(&iter); 3251 break; 3252 } 3253 ep = 0; 3254 } 3255 } 3256 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 3257 const usb_endpoint_ss_comp_descriptor_t * esscd = 3258 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3259 maxb = esscd->bMaxBurst; 3260 } 3261 3262 no_cdcd: 3263 /* 6.2.3.4, 4.8.2.4 */ 3264 if (USB_IS_SS(speed)) { 3265 /* USB 3.1 9.6.6 */ 3266 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3267 /* USB 3.1 9.6.7 */ 3268 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3269 #ifdef notyet 3270 if (xfertype == UE_ISOCHRONOUS) { 3271 } 3272 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3273 /* use ESIT */ 3274 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3275 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3276 3277 /* XXX if LEC = 1, set ESIT instead */ 3278 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3279 } else { 3280 /* use ival */ 3281 } 3282 #endif 3283 } else { 3284 /* USB 2.0 9.6.6 */ 3285 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3286 3287 /* 6.2.3.4 */ 3288 if (speed == USB_SPEED_HIGH && 3289 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3290 maxb = UE_GET_TRANS(mps); 3291 } else { 3292 /* LS/FS or HS CTRL or HS BULK */ 3293 maxb = 0; 3294 } 3295 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3296 } 3297 } 3298 3299 /* 3300 * Convert endpoint bInterval value to endpoint context interval value 3301 * for Interrupt pipe. 3302 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3303 */ 3304 static uint32_t 3305 xhci_bival2ival(uint32_t ival, uint32_t speed) 3306 { 3307 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3308 int i; 3309 3310 /* 3311 * round ival down to "the nearest base 2 multiple of 3312 * bInterval * 8". 3313 * bInterval is at most 255 as its type is uByte. 3314 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3315 */ 3316 for (i = 10; i > 0; i--) { 3317 if ((ival * 8) >= (1 << i)) 3318 break; 3319 } 3320 ival = i; 3321 } else { 3322 /* Interval = bInterval-1 for SS/HS */ 3323 ival--; 3324 } 3325 3326 return ival; 3327 } 3328 3329 /* ----- */ 3330 3331 static void 3332 xhci_noop(struct usbd_pipe *pipe) 3333 { 3334 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3335 } 3336 3337 /* 3338 * Process root hub request. 3339 */ 3340 static int 3341 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3342 void *buf, int buflen) 3343 { 3344 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3345 usb_port_status_t ps; 3346 int l, totlen = 0; 3347 uint16_t len, value, index; 3348 int port, i; 3349 uint32_t v; 3350 3351 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3352 3353 if (sc->sc_dying) 3354 return -1; 3355 3356 size_t bn = bus == &sc->sc_bus ? 0 : 1; 3357 3358 len = UGETW(req->wLength); 3359 value = UGETW(req->wValue); 3360 index = UGETW(req->wIndex); 3361 3362 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 3363 req->bmRequestType | (req->bRequest << 8), value, index, len); 3364 3365 #define C(x,y) ((x) | ((y) << 8)) 3366 switch (C(req->bRequest, req->bmRequestType)) { 3367 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3368 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 3369 if (len == 0) 3370 break; 3371 switch (value) { 3372 case C(0, UDESC_DEVICE): { 3373 usb_device_descriptor_t devd; 3374 totlen = min(buflen, sizeof(devd)); 3375 memcpy(&devd, buf, totlen); 3376 USETW(devd.idVendor, sc->sc_id_vendor); 3377 memcpy(buf, &devd, totlen); 3378 break; 3379 } 3380 #define sd ((usb_string_descriptor_t *)buf) 3381 case C(1, UDESC_STRING): 3382 /* Vendor */ 3383 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3384 break; 3385 case C(2, UDESC_STRING): 3386 /* Product */ 3387 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3388 break; 3389 #undef sd 3390 default: 3391 /* default from usbroothub */ 3392 return buflen; 3393 } 3394 break; 3395 3396 /* Hub requests */ 3397 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3398 break; 3399 /* Clear Port Feature request */ 3400 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): { 3401 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3402 3403 DPRINTFN(4, "UR_CLEAR_PORT_FEAT bp=%d feat=%d bus=%d cp=%d", 3404 index, value, bn, cp); 3405 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3406 return -1; 3407 } 3408 port = XHCI_PORTSC(cp); 3409 v = xhci_op_read_4(sc, port); 3410 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3411 v &= ~XHCI_PS_CLEAR; 3412 switch (value) { 3413 case UHF_PORT_ENABLE: 3414 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3415 break; 3416 case UHF_PORT_SUSPEND: 3417 return -1; 3418 case UHF_PORT_POWER: 3419 break; 3420 case UHF_PORT_TEST: 3421 case UHF_PORT_INDICATOR: 3422 return -1; 3423 case UHF_C_PORT_CONNECTION: 3424 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3425 break; 3426 case UHF_C_PORT_ENABLE: 3427 case UHF_C_PORT_SUSPEND: 3428 case UHF_C_PORT_OVER_CURRENT: 3429 return -1; 3430 case UHF_C_BH_PORT_RESET: 3431 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3432 break; 3433 case UHF_C_PORT_RESET: 3434 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3435 break; 3436 case UHF_C_PORT_LINK_STATE: 3437 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3438 break; 3439 case UHF_C_PORT_CONFIG_ERROR: 3440 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3441 break; 3442 default: 3443 return -1; 3444 } 3445 break; 3446 } 3447 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3448 if (len == 0) 3449 break; 3450 if ((value & 0xff) != 0) { 3451 return -1; 3452 } 3453 usb_hub_descriptor_t hubd; 3454 3455 totlen = min(buflen, sizeof(hubd)); 3456 memcpy(&hubd, buf, totlen); 3457 hubd.bNbrPorts = sc->sc_rhportcount[bn]; 3458 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3459 hubd.bPwrOn2PwrGood = 200; 3460 for (i = 0, l = sc->sc_rhportcount[bn]; l > 0; i++, l -= 8) { 3461 /* XXX can't find out? */ 3462 hubd.DeviceRemovable[i++] = 0; 3463 } 3464 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3465 totlen = min(totlen, hubd.bDescLength); 3466 memcpy(buf, &hubd, totlen); 3467 break; 3468 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3469 if (len != 4) { 3470 return -1; 3471 } 3472 memset(buf, 0, len); /* ? XXX */ 3473 totlen = len; 3474 break; 3475 /* Get Port Status request */ 3476 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): { 3477 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3478 3479 DPRINTFN(8, "get port status bn=%d i=%d cp=%zu", bn, index, cp, 3480 0); 3481 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3482 return -1; 3483 } 3484 if (len != 4) { 3485 return -1; 3486 } 3487 v = xhci_op_read_4(sc, XHCI_PORTSC(cp)); 3488 DPRINTFN(4, "getrhportsc %d %08x", cp, v, 0, 0); 3489 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3490 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3491 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3492 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3493 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3494 if (v & XHCI_PS_PR) i |= UPS_RESET; 3495 if (v & XHCI_PS_PP) { 3496 if (i & UPS_OTHER_SPEED) 3497 i |= UPS_PORT_POWER_SS; 3498 else 3499 i |= UPS_PORT_POWER; 3500 } 3501 if (i & UPS_OTHER_SPEED) 3502 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3503 if (sc->sc_vendor_port_status) 3504 i = sc->sc_vendor_port_status(sc, v, i); 3505 USETW(ps.wPortStatus, i); 3506 i = 0; 3507 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3508 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3509 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3510 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3511 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3512 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3513 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3514 USETW(ps.wPortChange, i); 3515 totlen = min(len, sizeof(ps)); 3516 memcpy(buf, &ps, totlen); 3517 break; 3518 } 3519 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3520 return -1; 3521 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3522 break; 3523 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3524 break; 3525 /* Set Port Feature request */ 3526 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3527 int optval = (index >> 8) & 0xff; 3528 index &= 0xff; 3529 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3530 return -1; 3531 } 3532 3533 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3534 3535 port = XHCI_PORTSC(cp); 3536 v = xhci_op_read_4(sc, port); 3537 DPRINTFN(4, "index %d cp %d portsc=0x%08x", index, cp, v, 0); 3538 v &= ~XHCI_PS_CLEAR; 3539 switch (value) { 3540 case UHF_PORT_ENABLE: 3541 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3542 break; 3543 case UHF_PORT_SUSPEND: 3544 /* XXX suspend */ 3545 break; 3546 case UHF_PORT_RESET: 3547 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3548 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3549 /* Wait for reset to complete. */ 3550 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3551 if (sc->sc_dying) { 3552 return -1; 3553 } 3554 v = xhci_op_read_4(sc, port); 3555 if (v & XHCI_PS_PR) { 3556 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3557 usb_delay_ms(&sc->sc_bus, 10); 3558 /* XXX */ 3559 } 3560 break; 3561 case UHF_PORT_POWER: 3562 /* XXX power control */ 3563 break; 3564 /* XXX more */ 3565 case UHF_C_PORT_RESET: 3566 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3567 break; 3568 case UHF_PORT_U1_TIMEOUT: 3569 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3570 return -1; 3571 } 3572 port = XHCI_PORTPMSC(cp); 3573 v = xhci_op_read_4(sc, port); 3574 DPRINTFN(4, "index %d cp %d portpmsc=0x%08x", index, cp, v, 0); 3575 v &= ~XHCI_PM3_U1TO_SET(0xff); 3576 v |= XHCI_PM3_U1TO_SET(optval); 3577 xhci_op_write_4(sc, port, v); 3578 break; 3579 case UHF_PORT_U2_TIMEOUT: 3580 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3581 return -1; 3582 } 3583 port = XHCI_PORTPMSC(cp); 3584 v = xhci_op_read_4(sc, port); 3585 DPRINTFN(4, "index %d cp %d portpmsc=0x%08x", index, cp, v, 0); 3586 v &= ~XHCI_PM3_U2TO_SET(0xff); 3587 v |= XHCI_PM3_U2TO_SET(optval); 3588 xhci_op_write_4(sc, port, v); 3589 break; 3590 default: 3591 return -1; 3592 } 3593 } 3594 break; 3595 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3596 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3597 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3598 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3599 break; 3600 default: 3601 /* default from usbroothub */ 3602 return buflen; 3603 } 3604 3605 return totlen; 3606 } 3607 3608 /* root hub interrupt */ 3609 3610 static usbd_status 3611 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3612 { 3613 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3614 usbd_status err; 3615 3616 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3617 3618 /* Insert last in queue. */ 3619 mutex_enter(&sc->sc_lock); 3620 err = usb_insert_transfer(xfer); 3621 mutex_exit(&sc->sc_lock); 3622 if (err) 3623 return err; 3624 3625 /* Pipe isn't running, start first */ 3626 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3627 } 3628 3629 /* Wait for roothub port status/change */ 3630 static usbd_status 3631 xhci_root_intr_start(struct usbd_xfer *xfer) 3632 { 3633 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3634 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3635 3636 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3637 3638 if (sc->sc_dying) 3639 return USBD_IOERROR; 3640 3641 mutex_enter(&sc->sc_lock); 3642 sc->sc_intrxfer[bn] = xfer; 3643 mutex_exit(&sc->sc_lock); 3644 3645 return USBD_IN_PROGRESS; 3646 } 3647 3648 static void 3649 xhci_root_intr_abort(struct usbd_xfer *xfer) 3650 { 3651 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3652 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3653 3654 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3655 3656 KASSERT(mutex_owned(&sc->sc_lock)); 3657 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3658 3659 sc->sc_intrxfer[bn] = NULL; 3660 3661 xfer->ux_status = USBD_CANCELLED; 3662 usb_transfer_complete(xfer); 3663 } 3664 3665 static void 3666 xhci_root_intr_close(struct usbd_pipe *pipe) 3667 { 3668 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3669 const struct usbd_xfer *xfer = pipe->up_intrxfer; 3670 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3671 3672 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3673 3674 KASSERT(mutex_owned(&sc->sc_lock)); 3675 3676 sc->sc_intrxfer[bn] = NULL; 3677 } 3678 3679 static void 3680 xhci_root_intr_done(struct usbd_xfer *xfer) 3681 { 3682 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3683 3684 } 3685 3686 /* -------------- */ 3687 /* device control */ 3688 3689 static usbd_status 3690 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3691 { 3692 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3693 usbd_status err; 3694 3695 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3696 3697 /* Insert last in queue. */ 3698 mutex_enter(&sc->sc_lock); 3699 err = usb_insert_transfer(xfer); 3700 mutex_exit(&sc->sc_lock); 3701 if (err) 3702 return err; 3703 3704 /* Pipe isn't running, start first */ 3705 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3706 } 3707 3708 static usbd_status 3709 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3710 { 3711 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3712 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3713 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3714 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3715 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3716 usb_device_request_t * const req = &xfer->ux_request; 3717 const int isread = usbd_xfer_isread(xfer); 3718 const uint32_t len = UGETW(req->wLength); 3719 usb_dma_t * const dma = &xfer->ux_dmabuf; 3720 uint64_t parameter; 3721 uint32_t status; 3722 uint32_t control; 3723 u_int i; 3724 3725 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3726 DPRINTFN(12, "req: %04x %04x %04x %04x", 3727 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3728 UGETW(req->wIndex), UGETW(req->wLength)); 3729 3730 /* we rely on the bottom bits for extra info */ 3731 KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx", 3732 (uintptr_t) xfer); 3733 3734 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3735 3736 i = 0; 3737 3738 /* setup phase */ 3739 memcpy(¶meter, req, sizeof(parameter)); 3740 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3741 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3742 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3743 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3744 XHCI_TRB_3_IDT_BIT; 3745 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3746 3747 if (len != 0) { 3748 /* data phase */ 3749 parameter = DMAADDR(dma, 0); 3750 KASSERTMSG(len <= 0x10000, "len %d", len); 3751 status = XHCI_TRB_2_IRQ_SET(0) | 3752 XHCI_TRB_2_TDSZ_SET(1) | 3753 XHCI_TRB_2_BYTES_SET(len); 3754 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3755 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3756 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3757 XHCI_TRB_3_IOC_BIT; 3758 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3759 } 3760 3761 parameter = 0; 3762 status = XHCI_TRB_2_IRQ_SET(0); 3763 /* the status stage has inverted direction */ 3764 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3765 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3766 XHCI_TRB_3_IOC_BIT; 3767 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3768 3769 mutex_enter(&tr->xr_lock); 3770 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3771 mutex_exit(&tr->xr_lock); 3772 3773 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3774 3775 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3776 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3777 xhci_timeout, xfer); 3778 } 3779 3780 return USBD_IN_PROGRESS; 3781 } 3782 3783 static void 3784 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3785 { 3786 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3787 usb_device_request_t *req = &xfer->ux_request; 3788 int len = UGETW(req->wLength); 3789 int rd = req->bmRequestType & UT_READ; 3790 3791 if (len) 3792 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3793 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3794 } 3795 3796 static void 3797 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3798 { 3799 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3800 3801 xhci_abort_xfer(xfer, USBD_CANCELLED); 3802 } 3803 3804 static void 3805 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3806 { 3807 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3808 3809 xhci_close_pipe(pipe); 3810 } 3811 3812 /* ------------------ */ 3813 /* device isochronous */ 3814 3815 /* ----------- */ 3816 /* device bulk */ 3817 3818 static usbd_status 3819 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3820 { 3821 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3822 usbd_status err; 3823 3824 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3825 3826 /* Insert last in queue. */ 3827 mutex_enter(&sc->sc_lock); 3828 err = usb_insert_transfer(xfer); 3829 mutex_exit(&sc->sc_lock); 3830 if (err) 3831 return err; 3832 3833 /* 3834 * Pipe isn't running (otherwise err would be USBD_INPROG), 3835 * so start it first. 3836 */ 3837 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3838 } 3839 3840 static usbd_status 3841 xhci_device_bulk_start(struct usbd_xfer *xfer) 3842 { 3843 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3844 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3845 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3846 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3847 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3848 const uint32_t len = xfer->ux_length; 3849 usb_dma_t * const dma = &xfer->ux_dmabuf; 3850 uint64_t parameter; 3851 uint32_t status; 3852 uint32_t control; 3853 u_int i = 0; 3854 3855 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3856 3857 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3858 3859 if (sc->sc_dying) 3860 return USBD_IOERROR; 3861 3862 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3863 3864 parameter = DMAADDR(dma, 0); 3865 /* 3866 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3867 * If the user supplied buffer crosses such a boundary then 2 3868 * (or more) TRB should be used. 3869 * If multiple TRB are used the td_size field must be set correctly. 3870 * For v1.0 devices (like ivy bridge) this is the number of usb data 3871 * blocks needed to complete the transfer. 3872 * Setting it to 1 in the last TRB causes an extra zero-length 3873 * data block be sent. 3874 * The earlier documentation differs, I don't know how it behaves. 3875 */ 3876 KASSERTMSG(len <= 0x10000, "len %d", len); 3877 status = XHCI_TRB_2_IRQ_SET(0) | 3878 XHCI_TRB_2_TDSZ_SET(1) | 3879 XHCI_TRB_2_BYTES_SET(len); 3880 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3881 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3882 XHCI_TRB_3_IOC_BIT; 3883 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3884 3885 mutex_enter(&tr->xr_lock); 3886 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3887 mutex_exit(&tr->xr_lock); 3888 3889 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3890 3891 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3892 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3893 xhci_timeout, xfer); 3894 } 3895 3896 return USBD_IN_PROGRESS; 3897 } 3898 3899 static void 3900 xhci_device_bulk_done(struct usbd_xfer *xfer) 3901 { 3902 #ifdef USB_DEBUG 3903 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3904 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3905 #endif 3906 const int isread = usbd_xfer_isread(xfer); 3907 3908 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3909 3910 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3911 3912 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3913 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3914 } 3915 3916 static void 3917 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3918 { 3919 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3920 3921 xhci_abort_xfer(xfer, USBD_CANCELLED); 3922 } 3923 3924 static void 3925 xhci_device_bulk_close(struct usbd_pipe *pipe) 3926 { 3927 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3928 3929 xhci_close_pipe(pipe); 3930 } 3931 3932 /* ---------------- */ 3933 /* device interrupt */ 3934 3935 static usbd_status 3936 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3937 { 3938 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3939 usbd_status err; 3940 3941 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3942 3943 /* Insert last in queue. */ 3944 mutex_enter(&sc->sc_lock); 3945 err = usb_insert_transfer(xfer); 3946 mutex_exit(&sc->sc_lock); 3947 if (err) 3948 return err; 3949 3950 /* 3951 * Pipe isn't running (otherwise err would be USBD_INPROG), 3952 * so start it first. 3953 */ 3954 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3955 } 3956 3957 static usbd_status 3958 xhci_device_intr_start(struct usbd_xfer *xfer) 3959 { 3960 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3961 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3962 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3963 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3964 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3965 const uint32_t len = xfer->ux_length; 3966 usb_dma_t * const dma = &xfer->ux_dmabuf; 3967 uint64_t parameter; 3968 uint32_t status; 3969 uint32_t control; 3970 u_int i = 0; 3971 3972 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3973 3974 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3975 3976 if (sc->sc_dying) 3977 return USBD_IOERROR; 3978 3979 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3980 3981 parameter = DMAADDR(dma, 0); 3982 KASSERTMSG(len <= 0x10000, "len %d", len); 3983 status = XHCI_TRB_2_IRQ_SET(0) | 3984 XHCI_TRB_2_TDSZ_SET(1) | 3985 XHCI_TRB_2_BYTES_SET(len); 3986 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3987 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3988 XHCI_TRB_3_IOC_BIT; 3989 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3990 3991 mutex_enter(&tr->xr_lock); 3992 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3993 mutex_exit(&tr->xr_lock); 3994 3995 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3996 3997 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3998 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3999 xhci_timeout, xfer); 4000 } 4001 4002 return USBD_IN_PROGRESS; 4003 } 4004 4005 static void 4006 xhci_device_intr_done(struct usbd_xfer *xfer) 4007 { 4008 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4009 #ifdef USB_DEBUG 4010 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4011 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4012 #endif 4013 const int isread = usbd_xfer_isread(xfer); 4014 4015 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4016 4017 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 4018 4019 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4020 4021 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4022 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4023 } 4024 4025 static void 4026 xhci_device_intr_abort(struct usbd_xfer *xfer) 4027 { 4028 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4029 4030 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4031 4032 KASSERT(mutex_owned(&sc->sc_lock)); 4033 DPRINTFN(15, "%p", xfer, 0, 0, 0); 4034 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4035 xhci_abort_xfer(xfer, USBD_CANCELLED); 4036 } 4037 4038 static void 4039 xhci_device_intr_close(struct usbd_pipe *pipe) 4040 { 4041 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 4042 4043 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4044 DPRINTFN(15, "%p", pipe, 0, 0, 0); 4045 4046 xhci_close_pipe(pipe); 4047 } 4048 4049 /* ------------ */ 4050 4051 static void 4052 xhci_timeout(void *addr) 4053 { 4054 struct xhci_xfer * const xx = addr; 4055 struct usbd_xfer * const xfer = &xx->xx_xfer; 4056 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4057 4058 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4059 4060 if (sc->sc_dying) { 4061 return; 4062 } 4063 4064 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 4065 USB_TASKQ_MPSAFE); 4066 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 4067 USB_TASKQ_HC); 4068 } 4069 4070 static void 4071 xhci_timeout_task(void *addr) 4072 { 4073 struct usbd_xfer * const xfer = addr; 4074 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4075 4076 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4077 4078 mutex_enter(&sc->sc_lock); 4079 xhci_abort_xfer(xfer, USBD_TIMEOUT); 4080 mutex_exit(&sc->sc_lock); 4081 } 4082
Indexes created Wed Oct 01 18:09:54 GMT 2025