xhci.c revision 1.68
1 /* $NetBSD: xhci.c,v 1.68 2017/01/19 16:05:00 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.68 2017/01/19 16:05:00 skrll Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static void xhci_host_dequeue(struct xhci_ring * const); 146 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 147 148 static usbd_status xhci_do_command(struct xhci_softc * const, 149 struct xhci_trb * const, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 153 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 154 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 155 static usbd_status xhci_enable_slot(struct xhci_softc * const, 156 uint8_t * const); 157 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 158 static usbd_status xhci_address_device(struct xhci_softc * const, 159 uint64_t, uint8_t, bool); 160 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 161 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 162 struct xhci_slot * const, u_int); 163 static usbd_status xhci_ring_init(struct xhci_softc * const, 164 struct xhci_ring * const, size_t, size_t); 165 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 166 167 static void xhci_setup_ctx(struct usbd_pipe *); 168 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 169 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 170 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 171 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 172 173 static void xhci_noop(struct usbd_pipe *); 174 175 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 176 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 177 static void xhci_root_intr_abort(struct usbd_xfer *); 178 static void xhci_root_intr_close(struct usbd_pipe *); 179 static void xhci_root_intr_done(struct usbd_xfer *); 180 181 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 182 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 183 static void xhci_device_ctrl_abort(struct usbd_xfer *); 184 static void xhci_device_ctrl_close(struct usbd_pipe *); 185 static void xhci_device_ctrl_done(struct usbd_xfer *); 186 187 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 188 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 189 static void xhci_device_intr_abort(struct usbd_xfer *); 190 static void xhci_device_intr_close(struct usbd_pipe *); 191 static void xhci_device_intr_done(struct usbd_xfer *); 192 193 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 194 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 195 static void xhci_device_bulk_abort(struct usbd_xfer *); 196 static void xhci_device_bulk_close(struct usbd_pipe *); 197 static void xhci_device_bulk_done(struct usbd_xfer *); 198 199 static void xhci_timeout(void *); 200 static void xhci_timeout_task(void *); 201 202 static const struct usbd_bus_methods xhci_bus_methods = { 203 .ubm_open = xhci_open, 204 .ubm_softint = xhci_softintr, 205 .ubm_dopoll = xhci_poll, 206 .ubm_allocx = xhci_allocx, 207 .ubm_freex = xhci_freex, 208 .ubm_getlock = xhci_get_lock, 209 .ubm_newdev = xhci_new_device, 210 .ubm_rhctrl = xhci_roothub_ctrl, 211 }; 212 213 static const struct usbd_pipe_methods xhci_root_intr_methods = { 214 .upm_transfer = xhci_root_intr_transfer, 215 .upm_start = xhci_root_intr_start, 216 .upm_abort = xhci_root_intr_abort, 217 .upm_close = xhci_root_intr_close, 218 .upm_cleartoggle = xhci_noop, 219 .upm_done = xhci_root_intr_done, 220 }; 221 222 223 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 224 .upm_transfer = xhci_device_ctrl_transfer, 225 .upm_start = xhci_device_ctrl_start, 226 .upm_abort = xhci_device_ctrl_abort, 227 .upm_close = xhci_device_ctrl_close, 228 .upm_cleartoggle = xhci_noop, 229 .upm_done = xhci_device_ctrl_done, 230 }; 231 232 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 233 .upm_cleartoggle = xhci_noop, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 237 .upm_transfer = xhci_device_bulk_transfer, 238 .upm_start = xhci_device_bulk_start, 239 .upm_abort = xhci_device_bulk_abort, 240 .upm_close = xhci_device_bulk_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_bulk_done, 243 }; 244 245 static const struct usbd_pipe_methods xhci_device_intr_methods = { 246 .upm_transfer = xhci_device_intr_transfer, 247 .upm_start = xhci_device_intr_start, 248 .upm_abort = xhci_device_intr_abort, 249 .upm_close = xhci_device_intr_close, 250 .upm_cleartoggle = xhci_noop, 251 .upm_done = xhci_device_intr_done, 252 }; 253 254 static inline uint32_t 255 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 256 { 257 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 258 } 259 260 static inline uint32_t 261 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 262 { 263 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 264 } 265 266 static inline void 267 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 268 uint32_t value) 269 { 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 271 } 272 273 #if 0 /* unused */ 274 static inline void 275 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 276 uint32_t value) 277 { 278 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 279 } 280 #endif /* unused */ 281 282 static inline uint32_t 283 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 284 { 285 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 286 } 287 288 static inline uint32_t 289 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 290 { 291 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 292 } 293 294 static inline void 295 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 296 uint32_t value) 297 { 298 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 299 } 300 301 static inline uint64_t 302 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 303 { 304 uint64_t value; 305 306 if (sc->sc_ac64) { 307 #ifdef XHCI_USE_BUS_SPACE_8 308 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 309 #else 310 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 311 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 312 offset + 4) << 32; 313 #endif 314 } else { 315 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 316 } 317 318 return value; 319 } 320 321 static inline void 322 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 336 } 337 } 338 339 static inline uint32_t 340 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 341 { 342 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 343 } 344 345 static inline void 346 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 347 uint32_t value) 348 { 349 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 350 } 351 352 #if 0 /* unused */ 353 static inline uint64_t 354 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 355 { 356 uint64_t value; 357 358 if (sc->sc_ac64) { 359 #ifdef XHCI_USE_BUS_SPACE_8 360 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 361 #else 362 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 363 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 364 offset + 4) << 32; 365 #endif 366 } else { 367 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 368 } 369 370 return value; 371 } 372 #endif /* unused */ 373 374 static inline void 375 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 376 uint64_t value) 377 { 378 if (sc->sc_ac64) { 379 #ifdef XHCI_USE_BUS_SPACE_8 380 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 381 #else 382 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 383 (value >> 0) & 0xffffffff); 384 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 385 (value >> 32) & 0xffffffff); 386 #endif 387 } else { 388 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 389 } 390 } 391 392 #if 0 /* unused */ 393 static inline uint32_t 394 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 395 { 396 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 397 } 398 #endif /* unused */ 399 400 static inline void 401 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 402 uint32_t value) 403 { 404 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 405 } 406 407 /* --- */ 408 409 static inline uint8_t 410 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 411 { 412 u_int eptype = 0; 413 414 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 415 case UE_CONTROL: 416 eptype = 0x0; 417 break; 418 case UE_ISOCHRONOUS: 419 eptype = 0x1; 420 break; 421 case UE_BULK: 422 eptype = 0x2; 423 break; 424 case UE_INTERRUPT: 425 eptype = 0x3; 426 break; 427 } 428 429 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 430 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 431 return eptype | 0x4; 432 else 433 return eptype; 434 } 435 436 static u_int 437 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 438 { 439 /* xHCI 1.0 section 4.5.1 */ 440 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 441 u_int in = 0; 442 443 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 444 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 445 in = 1; 446 447 return epaddr * 2 + in; 448 } 449 450 static inline u_int 451 xhci_dci_to_ici(const u_int i) 452 { 453 return i + 1; 454 } 455 456 static inline void * 457 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 458 const u_int dci) 459 { 460 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 461 } 462 463 #if 0 /* unused */ 464 static inline bus_addr_t 465 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 466 const u_int dci) 467 { 468 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 469 } 470 #endif /* unused */ 471 472 static inline void * 473 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline bus_addr_t 480 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 481 const u_int ici) 482 { 483 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 484 } 485 486 static inline struct xhci_trb * 487 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 488 { 489 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 490 } 491 492 static inline bus_addr_t 493 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 494 { 495 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 496 } 497 498 static inline void 499 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 500 uint32_t control) 501 { 502 trb->trb_0 = htole64(parameter); 503 trb->trb_2 = htole32(status); 504 trb->trb_3 = htole32(control); 505 } 506 507 static int 508 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 509 { 510 /* base address of TRBs */ 511 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 512 513 /* trb_0 range sanity check */ 514 if (trb_0 == 0 || trb_0 < trbp || 515 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 516 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 517 return 1; 518 } 519 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 520 return 0; 521 } 522 523 static unsigned int 524 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 525 u_int dci) 526 { 527 uint32_t *cp; 528 529 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 530 cp = xhci_slot_get_dcv(sc, xs, dci); 531 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 532 } 533 534 static inline unsigned int 535 xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport) 536 { 537 const unsigned int port = ctlrport - 1; 538 const uint8_t bit = __BIT(port % NBBY); 539 540 return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit); 541 } 542 543 /* 544 * Return the roothub port for a controller port. Both are 1..n. 545 */ 546 static inline unsigned int 547 xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport) 548 { 549 550 return sc->sc_ctlrportmap[ctrlport - 1]; 551 } 552 553 /* 554 * Return the controller port for a bus roothub port. Both are 1..n. 555 */ 556 static inline unsigned int 557 xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn, 558 unsigned int rhport) 559 { 560 561 return sc->sc_rhportmap[bn][rhport - 1]; 562 } 563 564 /* --- */ 565 566 void 567 xhci_childdet(device_t self, device_t child) 568 { 569 struct xhci_softc * const sc = device_private(self); 570 571 KASSERT(sc->sc_child == child); 572 if (child == sc->sc_child) 573 sc->sc_child = NULL; 574 } 575 576 int 577 xhci_detach(struct xhci_softc *sc, int flags) 578 { 579 int rv = 0; 580 581 if (sc->sc_child2 != NULL) { 582 rv = config_detach(sc->sc_child2, flags); 583 if (rv != 0) 584 return rv; 585 } 586 587 if (sc->sc_child != NULL) { 588 rv = config_detach(sc->sc_child, flags); 589 if (rv != 0) 590 return rv; 591 } 592 593 /* XXX unconfigure/free slots */ 594 595 /* verify: */ 596 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 597 xhci_op_write_4(sc, XHCI_USBCMD, 0); 598 /* do we need to wait for stop? */ 599 600 xhci_op_write_8(sc, XHCI_CRCR, 0); 601 xhci_ring_free(sc, &sc->sc_cr); 602 cv_destroy(&sc->sc_command_cv); 603 cv_destroy(&sc->sc_cmdbusy_cv); 604 605 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 606 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 607 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 608 xhci_ring_free(sc, &sc->sc_er); 609 610 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 611 612 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 613 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 614 615 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 616 617 kmem_free(sc->sc_ctlrportbus, sc->sc_maxports * sizeof(uint8_t) / NBBY); 618 kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int)); 619 620 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 621 kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int)); 622 } 623 624 mutex_destroy(&sc->sc_lock); 625 mutex_destroy(&sc->sc_intr_lock); 626 627 pool_cache_destroy(sc->sc_xferpool); 628 629 return rv; 630 } 631 632 int 633 xhci_activate(device_t self, enum devact act) 634 { 635 struct xhci_softc * const sc = device_private(self); 636 637 switch (act) { 638 case DVACT_DEACTIVATE: 639 sc->sc_dying = true; 640 return 0; 641 default: 642 return EOPNOTSUPP; 643 } 644 } 645 646 bool 647 xhci_suspend(device_t dv, const pmf_qual_t *qual) 648 { 649 return false; 650 } 651 652 bool 653 xhci_resume(device_t dv, const pmf_qual_t *qual) 654 { 655 return false; 656 } 657 658 bool 659 xhci_shutdown(device_t self, int flags) 660 { 661 return false; 662 } 663 664 static int 665 xhci_hc_reset(struct xhci_softc * const sc) 666 { 667 uint32_t usbcmd, usbsts; 668 int i; 669 670 /* Check controller not ready */ 671 for (i = 0; i < XHCI_WAIT_CNR; i++) { 672 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 673 if ((usbsts & XHCI_STS_CNR) == 0) 674 break; 675 usb_delay_ms(&sc->sc_bus, 1); 676 } 677 if (i >= XHCI_WAIT_CNR) { 678 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 679 return EIO; 680 } 681 682 /* Halt controller */ 683 usbcmd = 0; 684 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 685 usb_delay_ms(&sc->sc_bus, 1); 686 687 /* Reset controller */ 688 usbcmd = XHCI_CMD_HCRST; 689 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 690 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 691 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 692 if ((usbcmd & XHCI_CMD_HCRST) == 0) 693 break; 694 usb_delay_ms(&sc->sc_bus, 1); 695 } 696 if (i >= XHCI_WAIT_HCRST) { 697 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 698 return EIO; 699 } 700 701 /* Check controller not ready */ 702 for (i = 0; i < XHCI_WAIT_CNR; i++) { 703 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 704 if ((usbsts & XHCI_STS_CNR) == 0) 705 break; 706 usb_delay_ms(&sc->sc_bus, 1); 707 } 708 if (i >= XHCI_WAIT_CNR) { 709 aprint_error_dev(sc->sc_dev, 710 "controller not ready timeout after reset\n"); 711 return EIO; 712 } 713 714 return 0; 715 } 716 717 718 static void 719 hexdump(const char *msg, const void *base, size_t len) 720 { 721 #if 0 722 size_t cnt; 723 const uint32_t *p; 724 extern paddr_t vtophys(vaddr_t); 725 726 p = base; 727 cnt = 0; 728 729 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 730 (void *)vtophys((vaddr_t)base)); 731 732 while (cnt < len) { 733 if (cnt % 16 == 0) 734 printf("%p: ", p); 735 else if (cnt % 8 == 0) 736 printf(" |"); 737 printf(" %08x", *p++); 738 cnt += 4; 739 if (cnt % 16 == 0) 740 printf("\n"); 741 } 742 if (cnt % 16 != 0) 743 printf("\n"); 744 #endif 745 } 746 747 /* 7.2 xHCI Support Protocol Capability */ 748 static void 749 xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp) 750 { 751 /* XXX Cache this lot */ 752 753 const uint32_t w0 = xhci_read_4(sc, ecp); 754 const uint32_t w4 = xhci_read_4(sc, ecp + 4); 755 const uint32_t w8 = xhci_read_4(sc, ecp + 8); 756 const uint32_t wc = xhci_read_4(sc, ecp + 0xc); 757 758 aprint_debug_dev(sc->sc_dev, 759 " SP: %08x %08x %08x %08x\n", w0, w4, w8, wc); 760 761 if (w4 != XHCI_XECP_USBID) 762 return; 763 764 const int major = XHCI_XECP_SP_W0_MAJOR(w0); 765 const int minor = XHCI_XECP_SP_W0_MINOR(w0); 766 const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8); 767 const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8); 768 769 const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16)); 770 switch (mm) { 771 case 0x0200: 772 case 0x0300: 773 case 0x0301: 774 aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n", 775 major == 3 ? "ss" : "hs", cpo, cpo + cpc -1); 776 break; 777 default: 778 aprint_debug_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n", 779 major, minor); 780 return; 781 } 782 783 const size_t bus = (major == 3) ? 0 : 1; 784 785 /* Index arrays with 0..n-1 where ports are numbered 1..n */ 786 for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) { 787 if (sc->sc_ctlrportmap[cp] != 0) { 788 aprint_error_dev(sc->sc_dev, "contoller port %zu " 789 "already assigned", cp); 790 continue; 791 } 792 793 sc->sc_ctlrportbus[cp / NBBY] |= 794 bus == 0 ? 0 : __BIT(cp % NBBY); 795 796 const size_t rhp = sc->sc_rhportcount[bus]++; 797 798 KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0, 799 "bus %zu rhp %zu is %d", bus, rhp, 800 sc->sc_rhportmap[bus][rhp]); 801 802 sc->sc_rhportmap[bus][rhp] = cp + 1; 803 sc->sc_ctlrportmap[cp] = rhp + 1; 804 } 805 } 806 807 /* Process extended capabilities */ 808 static void 809 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 810 { 811 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 812 813 bus_size_t ecp = XHCI_HCC_XECP(hcc) * 4; 814 while (ecp != 0) { 815 uint32_t ecr = xhci_read_4(sc, ecp); 816 aprint_debug_dev(sc->sc_dev, "ECR %lx: %08x\n", ecp, ecr); 817 switch (XHCI_XECP_ID(ecr)) { 818 case XHCI_ID_PROTOCOLS: { 819 xhci_id_protocols(sc, ecp); 820 break; 821 } 822 case XHCI_ID_USB_LEGACY: { 823 uint8_t bios_sem; 824 825 /* Take host controller ownership from BIOS */ 826 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 827 if (bios_sem) { 828 /* sets xHCI to be owned by OS */ 829 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 830 aprint_debug_dev(sc->sc_dev, 831 "waiting for BIOS to give up control\n"); 832 for (int i = 0; i < 5000; i++) { 833 bios_sem = xhci_read_1(sc, ecp + 834 XHCI_XECP_BIOS_SEM); 835 if (bios_sem == 0) 836 break; 837 DELAY(1000); 838 } 839 if (bios_sem) { 840 aprint_error_dev(sc->sc_dev, 841 "timed out waiting for BIOS\n"); 842 } 843 } 844 break; 845 } 846 default: 847 break; 848 } 849 ecr = xhci_read_4(sc, ecp); 850 if (XHCI_XECP_NEXT(ecr) == 0) { 851 ecp = 0; 852 } else { 853 ecp += XHCI_XECP_NEXT(ecr) * 4; 854 } 855 } 856 } 857 858 #define XHCI_HCCPREV1_BITS \ 859 "\177\020" /* New bitmask */ \ 860 "f\020\020XECP\0" \ 861 "f\014\4MAXPSA\0" \ 862 "b\013CFC\0" \ 863 "b\012SEC\0" \ 864 "b\011SBD\0" \ 865 "b\010FSE\0" \ 866 "b\7NSS\0" \ 867 "b\6LTC\0" \ 868 "b\5LHRC\0" \ 869 "b\4PIND\0" \ 870 "b\3PPC\0" \ 871 "b\2CZC\0" \ 872 "b\1BNC\0" \ 873 "b\0AC64\0" \ 874 "\0" 875 #define XHCI_HCCV1_x_BITS \ 876 "\177\020" /* New bitmask */ \ 877 "f\020\020XECP\0" \ 878 "f\014\4MAXPSA\0" \ 879 "b\013CFC\0" \ 880 "b\012SEC\0" \ 881 "b\011SPC\0" \ 882 "b\010PAE\0" \ 883 "b\7NSS\0" \ 884 "b\6LTC\0" \ 885 "b\5LHRC\0" \ 886 "b\4PIND\0" \ 887 "b\3PPC\0" \ 888 "b\2CSZ\0" \ 889 "b\1BNC\0" \ 890 "b\0AC64\0" \ 891 "\0" 892 893 int 894 xhci_init(struct xhci_softc *sc) 895 { 896 bus_size_t bsz; 897 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 898 uint32_t pagesize, config; 899 int i = 0; 900 uint16_t hciversion; 901 uint8_t caplength; 902 903 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 904 905 /* Set up the bus struct for the usb 3 and usb 2 buses */ 906 sc->sc_bus.ub_methods = &xhci_bus_methods; 907 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 908 sc->sc_bus.ub_revision = USBREV_3_0; 909 sc->sc_bus.ub_usedma = true; 910 sc->sc_bus.ub_hcpriv = sc; 911 912 sc->sc_bus2.ub_methods = &xhci_bus_methods; 913 sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe); 914 sc->sc_bus2.ub_revision = USBREV_2_0; 915 sc->sc_bus2.ub_usedma = true; 916 sc->sc_bus2.ub_hcpriv = sc; 917 sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag; 918 919 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 920 caplength = XHCI_CAP_CAPLENGTH(cap); 921 hciversion = XHCI_CAP_HCIVERSION(cap); 922 923 if (hciversion < XHCI_HCIVERSION_0_96 || 924 hciversion > XHCI_HCIVERSION_1_0) { 925 aprint_normal_dev(sc->sc_dev, 926 "xHCI version %x.%x not known to be supported\n", 927 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 928 } else { 929 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 930 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 931 } 932 933 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 934 &sc->sc_cbh) != 0) { 935 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 936 return ENOMEM; 937 } 938 939 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 940 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 941 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 942 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 943 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 944 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 945 aprint_debug_dev(sc->sc_dev, 946 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 947 948 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 949 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 950 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 951 952 char sbuf[128]; 953 if (hciversion < XHCI_HCIVERSION_1_0) 954 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 955 else 956 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 957 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 958 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 959 960 /* default all ports to bus 0, i.e. usb 3 */ 961 sc->sc_ctlrportbus = kmem_zalloc(sc->sc_maxports * sizeof(uint8_t) / NBBY, KM_SLEEP); 962 sc->sc_ctlrportmap = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 963 964 /* controller port to bus roothub port map */ 965 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 966 sc->sc_rhportmap[j] = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 967 } 968 969 /* 970 * Process all Extended Capabilities 971 */ 972 xhci_ecp(sc, hcc); 973 974 bsz = XHCI_PORTSC(sc->sc_maxports); 975 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 976 &sc->sc_obh) != 0) { 977 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 978 return ENOMEM; 979 } 980 981 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 982 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 983 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 984 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 985 return ENOMEM; 986 } 987 988 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 989 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 990 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 991 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 992 return ENOMEM; 993 } 994 995 int rv; 996 rv = xhci_hc_reset(sc); 997 if (rv != 0) { 998 return rv; 999 } 1000 1001 if (sc->sc_vendor_init) 1002 sc->sc_vendor_init(sc); 1003 1004 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 1005 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 1006 pagesize = ffs(pagesize); 1007 if (pagesize == 0) { 1008 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 1009 return EIO; 1010 } 1011 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 1012 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 1013 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 1014 (uint32_t)sc->sc_maxslots); 1015 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 1016 1017 usbd_status err; 1018 1019 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 1020 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 1021 if (sc->sc_maxspbuf != 0) { 1022 err = usb_allocmem(&sc->sc_bus, 1023 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 1024 &sc->sc_spbufarray_dma); 1025 if (err) { 1026 aprint_error_dev(sc->sc_dev, 1027 "spbufarray init fail, err %d\n", err); 1028 return ENOMEM; 1029 } 1030 1031 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 1032 sc->sc_maxspbuf, KM_SLEEP); 1033 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 1034 for (i = 0; i < sc->sc_maxspbuf; i++) { 1035 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 1036 /* allocate contexts */ 1037 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 1038 sc->sc_pgsz, dma); 1039 if (err) { 1040 aprint_error_dev(sc->sc_dev, 1041 "spbufarray_dma init fail, err %d\n", err); 1042 rv = ENOMEM; 1043 goto bad1; 1044 } 1045 spbufarray[i] = htole64(DMAADDR(dma, 0)); 1046 usb_syncmem(dma, 0, sc->sc_pgsz, 1047 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1048 } 1049 1050 usb_syncmem(&sc->sc_spbufarray_dma, 0, 1051 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 1052 } 1053 1054 config = xhci_op_read_4(sc, XHCI_CONFIG); 1055 config &= ~0xFF; 1056 config |= sc->sc_maxslots & 0xFF; 1057 xhci_op_write_4(sc, XHCI_CONFIG, config); 1058 1059 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 1060 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 1061 if (err) { 1062 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 1063 err); 1064 rv = ENOMEM; 1065 goto bad1; 1066 } 1067 1068 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 1069 XHCI_EVENT_RING_SEGMENTS_ALIGN); 1070 if (err) { 1071 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 1072 err); 1073 rv = ENOMEM; 1074 goto bad2; 1075 } 1076 1077 usb_dma_t *dma; 1078 size_t size; 1079 size_t align; 1080 1081 dma = &sc->sc_eventst_dma; 1082 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 1083 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 1084 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 1085 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 1086 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1087 if (err) { 1088 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 1089 err); 1090 rv = ENOMEM; 1091 goto bad3; 1092 } 1093 1094 memset(KERNADDR(dma, 0), 0, size); 1095 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1096 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 1097 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 1098 KERNADDR(&sc->sc_eventst_dma, 0), 1099 sc->sc_eventst_dma.udma_block->size); 1100 1101 dma = &sc->sc_dcbaa_dma; 1102 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 1103 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 1104 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 1105 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1106 if (err) { 1107 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1108 rv = ENOMEM; 1109 goto bad4; 1110 } 1111 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 1112 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1113 KERNADDR(&sc->sc_dcbaa_dma, 0), 1114 sc->sc_dcbaa_dma.udma_block->size); 1115 1116 memset(KERNADDR(dma, 0), 0, size); 1117 if (sc->sc_maxspbuf != 0) { 1118 /* 1119 * DCBA entry 0 hold the scratchbuf array pointer. 1120 */ 1121 *(uint64_t *)KERNADDR(dma, 0) = 1122 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1123 } 1124 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1125 1126 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1127 KM_SLEEP); 1128 if (sc->sc_slots == NULL) { 1129 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1130 rv = ENOMEM; 1131 goto bad; 1132 } 1133 1134 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1135 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1136 if (sc->sc_xferpool == NULL) { 1137 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1138 err); 1139 rv = ENOMEM; 1140 goto bad; 1141 } 1142 1143 cv_init(&sc->sc_command_cv, "xhcicmd"); 1144 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1145 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1146 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1147 1148 struct xhci_erste *erst; 1149 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1150 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1151 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1152 erst[0].erste_3 = htole32(0); 1153 usb_syncmem(&sc->sc_eventst_dma, 0, 1154 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1155 1156 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1157 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1158 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1159 XHCI_ERDP_LO_BUSY); 1160 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1161 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1162 sc->sc_cr.xr_cs); 1163 1164 #if 0 1165 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1166 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1167 #endif 1168 1169 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1170 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1171 /* Intel xhci needs interrupt rate moderated. */ 1172 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1173 else 1174 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1175 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 1176 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1177 1178 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 1179 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1180 xhci_op_read_4(sc, XHCI_USBCMD)); 1181 1182 return 0; 1183 1184 bad: 1185 if (sc->sc_xferpool) { 1186 pool_cache_destroy(sc->sc_xferpool); 1187 sc->sc_xferpool = NULL; 1188 } 1189 1190 if (sc->sc_slots) { 1191 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1192 sc->sc_maxslots); 1193 sc->sc_slots = NULL; 1194 } 1195 1196 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1197 bad4: 1198 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1199 bad3: 1200 xhci_ring_free(sc, &sc->sc_er); 1201 bad2: 1202 xhci_ring_free(sc, &sc->sc_cr); 1203 i = sc->sc_maxspbuf; 1204 bad1: 1205 for (int j = 0; j < i; j++) 1206 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1207 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1208 1209 return rv; 1210 } 1211 1212 int 1213 xhci_intr(void *v) 1214 { 1215 struct xhci_softc * const sc = v; 1216 int ret = 0; 1217 1218 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1219 1220 if (sc == NULL) 1221 return 0; 1222 1223 mutex_spin_enter(&sc->sc_intr_lock); 1224 1225 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1226 goto done; 1227 1228 /* If we get an interrupt while polling, then just ignore it. */ 1229 if (sc->sc_bus.ub_usepolling) { 1230 #ifdef DIAGNOSTIC 1231 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1232 #endif 1233 goto done; 1234 } 1235 1236 ret = xhci_intr1(sc); 1237 done: 1238 mutex_spin_exit(&sc->sc_intr_lock); 1239 return ret; 1240 } 1241 1242 int 1243 xhci_intr1(struct xhci_softc * const sc) 1244 { 1245 uint32_t usbsts; 1246 uint32_t iman; 1247 1248 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1249 1250 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1251 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1252 #if 0 1253 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1254 return 0; 1255 } 1256 #endif 1257 xhci_op_write_4(sc, XHCI_USBSTS, 1258 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1259 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1260 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1261 1262 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1263 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1264 iman |= XHCI_IMAN_INTR_PEND; 1265 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1266 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1267 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1268 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1269 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1270 1271 usb_schedsoftintr(&sc->sc_bus); 1272 1273 return 1; 1274 } 1275 1276 /* 1277 * 3 port speed types used in USB stack 1278 * 1279 * usbdi speed 1280 * definition: USB_SPEED_* in usb.h 1281 * They are used in struct usbd_device in USB stack. 1282 * ioctl interface uses these values too. 1283 * port_status speed 1284 * definition: UPS_*_SPEED in usb.h 1285 * They are used in usb_port_status_t and valid only for USB 2.0. 1286 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1287 * of usb_port_status_ext_t indicates port speed. 1288 * Note that some 3.0 values overlap with 2.0 values. 1289 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1290 * means UPS_LOW_SPEED in HS.) 1291 * port status returned from hub also uses these values. 1292 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1293 * or more. 1294 * xspeed: 1295 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1296 * They are used in only slot context and PORTSC reg of xhci. 1297 * The difference between usbdi speed and xspeed is 1298 * that FS and LS values are swapped. 1299 */ 1300 1301 /* convert usbdi speed to xspeed */ 1302 static int 1303 xhci_speed2xspeed(int speed) 1304 { 1305 switch (speed) { 1306 case USB_SPEED_LOW: return 2; 1307 case USB_SPEED_FULL: return 1; 1308 default: return speed; 1309 } 1310 } 1311 1312 #if 0 1313 /* convert xspeed to usbdi speed */ 1314 static int 1315 xhci_xspeed2speed(int xspeed) 1316 { 1317 switch (xspeed) { 1318 case 1: return USB_SPEED_FULL; 1319 case 2: return USB_SPEED_LOW; 1320 default: return xspeed; 1321 } 1322 } 1323 #endif 1324 1325 /* convert xspeed to port status speed */ 1326 static int 1327 xhci_xspeed2psspeed(int xspeed) 1328 { 1329 switch (xspeed) { 1330 case 0: return 0; 1331 case 1: return UPS_FULL_SPEED; 1332 case 2: return UPS_LOW_SPEED; 1333 case 3: return UPS_HIGH_SPEED; 1334 default: return UPS_OTHER_SPEED; 1335 } 1336 } 1337 1338 /* 1339 * Construct input contexts and issue TRB to open pipe. 1340 */ 1341 static usbd_status 1342 xhci_configure_endpoint(struct usbd_pipe *pipe) 1343 { 1344 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1345 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1346 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1347 struct xhci_trb trb; 1348 usbd_status err; 1349 1350 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1351 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1352 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1353 pipe->up_endpoint->ue_edesc->bmAttributes); 1354 1355 /* XXX ensure input context is available? */ 1356 1357 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1358 1359 /* set up context */ 1360 xhci_setup_ctx(pipe); 1361 1362 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1363 sc->sc_ctxsz * 1); 1364 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1365 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1366 1367 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1368 trb.trb_2 = 0; 1369 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1370 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1371 1372 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1373 1374 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1375 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1376 sc->sc_ctxsz * 1); 1377 1378 return err; 1379 } 1380 1381 #if 0 1382 static usbd_status 1383 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1384 { 1385 #ifdef USB_DEBUG 1386 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1387 #endif 1388 1389 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1390 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1391 1392 return USBD_NORMAL_COMPLETION; 1393 } 1394 #endif 1395 1396 /* 4.6.8, 6.4.3.7 */ 1397 static usbd_status 1398 xhci_reset_endpoint_locked(struct usbd_pipe *pipe) 1399 { 1400 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1401 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1402 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1403 struct xhci_trb trb; 1404 usbd_status err; 1405 1406 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1407 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1408 1409 KASSERT(mutex_owned(&sc->sc_lock)); 1410 1411 trb.trb_0 = 0; 1412 trb.trb_2 = 0; 1413 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1414 XHCI_TRB_3_EP_SET(dci) | 1415 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1416 1417 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1418 1419 return err; 1420 } 1421 1422 static usbd_status 1423 xhci_reset_endpoint(struct usbd_pipe *pipe) 1424 { 1425 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1426 1427 mutex_enter(&sc->sc_lock); 1428 usbd_status ret = xhci_reset_endpoint_locked(pipe); 1429 mutex_exit(&sc->sc_lock); 1430 1431 return ret; 1432 } 1433 1434 /* 1435 * 4.6.9, 6.4.3.8 1436 * Stop execution of TDs on xfer ring. 1437 * Should be called with sc_lock held. 1438 */ 1439 static usbd_status 1440 xhci_stop_endpoint(struct usbd_pipe *pipe) 1441 { 1442 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1443 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1444 struct xhci_trb trb; 1445 usbd_status err; 1446 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1447 1448 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1449 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1450 1451 KASSERT(mutex_owned(&sc->sc_lock)); 1452 1453 trb.trb_0 = 0; 1454 trb.trb_2 = 0; 1455 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1456 XHCI_TRB_3_EP_SET(dci) | 1457 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1458 1459 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1460 1461 return err; 1462 } 1463 1464 /* 1465 * Set TR Dequeue Pointer. 1466 * xHCI 1.1 4.6.10 6.4.3.9 1467 * Purge all of the TRBs on ring and reinitialize ring. 1468 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1469 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1470 * error will be generated. 1471 */ 1472 static usbd_status 1473 xhci_set_dequeue_locked(struct usbd_pipe *pipe) 1474 { 1475 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1476 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1477 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1478 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1479 struct xhci_trb trb; 1480 usbd_status err; 1481 1482 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1483 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1484 1485 KASSERT(mutex_owned(&sc->sc_lock)); 1486 1487 xhci_host_dequeue(xr); 1488 1489 /* set DCS */ 1490 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1491 trb.trb_2 = 0; 1492 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1493 XHCI_TRB_3_EP_SET(dci) | 1494 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1495 1496 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1497 1498 return err; 1499 } 1500 1501 static usbd_status 1502 xhci_set_dequeue(struct usbd_pipe *pipe) 1503 { 1504 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1505 1506 mutex_enter(&sc->sc_lock); 1507 usbd_status ret = xhci_set_dequeue_locked(pipe); 1508 mutex_exit(&sc->sc_lock); 1509 1510 return ret; 1511 } 1512 1513 /* 1514 * Open new pipe: called from usbd_setup_pipe_flags. 1515 * Fills methods of pipe. 1516 * If pipe is not for ep0, calls configure_endpoint. 1517 */ 1518 static usbd_status 1519 xhci_open(struct usbd_pipe *pipe) 1520 { 1521 struct usbd_device * const dev = pipe->up_dev; 1522 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1523 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1524 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1525 1526 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1527 DPRINTFN(1, "addr %d depth %d port %d speed %d", dev->ud_addr, 1528 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1529 DPRINTFN(1, " dci %u type 0x%02x epaddr 0x%02x attr 0x%02x", 1530 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1531 ed->bmAttributes); 1532 DPRINTFN(1, " mps %u ival %u", UGETW(ed->wMaxPacketSize), ed->bInterval, 1533 0, 0); 1534 1535 if (sc->sc_dying) 1536 return USBD_IOERROR; 1537 1538 /* Root Hub */ 1539 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1540 switch (ed->bEndpointAddress) { 1541 case USB_CONTROL_ENDPOINT: 1542 pipe->up_methods = &roothub_ctrl_methods; 1543 break; 1544 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1545 pipe->up_methods = &xhci_root_intr_methods; 1546 break; 1547 default: 1548 pipe->up_methods = NULL; 1549 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1550 ed->bEndpointAddress, 0, 0, 0); 1551 return USBD_INVAL; 1552 } 1553 return USBD_NORMAL_COMPLETION; 1554 } 1555 1556 switch (xfertype) { 1557 case UE_CONTROL: 1558 pipe->up_methods = &xhci_device_ctrl_methods; 1559 break; 1560 case UE_ISOCHRONOUS: 1561 pipe->up_methods = &xhci_device_isoc_methods; 1562 return USBD_INVAL; 1563 break; 1564 case UE_BULK: 1565 pipe->up_methods = &xhci_device_bulk_methods; 1566 break; 1567 case UE_INTERRUPT: 1568 pipe->up_methods = &xhci_device_intr_methods; 1569 break; 1570 default: 1571 return USBD_IOERROR; 1572 break; 1573 } 1574 1575 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1576 return xhci_configure_endpoint(pipe); 1577 1578 return USBD_NORMAL_COMPLETION; 1579 } 1580 1581 /* 1582 * Closes pipe, called from usbd_kill_pipe via close methods. 1583 * If the endpoint to be closed is ep0, disable_slot. 1584 * Should be called with sc_lock held. 1585 */ 1586 static void 1587 xhci_close_pipe(struct usbd_pipe *pipe) 1588 { 1589 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1590 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1591 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1592 const u_int dci = xhci_ep_get_dci(ed); 1593 struct xhci_trb trb; 1594 uint32_t *cp; 1595 1596 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1597 1598 if (sc->sc_dying) 1599 return; 1600 1601 /* xs is uninitialized before xhci_init_slot */ 1602 if (xs == NULL || xs->xs_idx == 0) 1603 return; 1604 1605 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1606 1607 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1608 KASSERT(mutex_owned(&sc->sc_lock)); 1609 1610 if (pipe->up_dev->ud_depth == 0) 1611 return; 1612 1613 if (dci == XHCI_DCI_EP_CONTROL) { 1614 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1615 xhci_disable_slot(sc, xs->xs_idx); 1616 return; 1617 } 1618 1619 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED) 1620 (void)xhci_stop_endpoint(pipe); 1621 1622 /* 1623 * set appropriate bit to be dropped. 1624 * don't set DC bit to 1, otherwise all endpoints 1625 * would be deconfigured. 1626 */ 1627 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1628 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1629 cp[1] = htole32(0); 1630 1631 /* XXX should be most significant one, not dci? */ 1632 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1633 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1634 1635 /* configure ep context performs an implicit dequeue */ 1636 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 1637 1638 /* sync input contexts before they are read from memory */ 1639 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1640 1641 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1642 trb.trb_2 = 0; 1643 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1644 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1645 1646 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1647 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1648 } 1649 1650 /* 1651 * Abort transfer. 1652 * Should be called with sc_lock held. 1653 */ 1654 static void 1655 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1656 { 1657 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1658 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1659 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1660 1661 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1662 DPRINTFN(4, "xfer %p pipe %p status %d", 1663 xfer, xfer->ux_pipe, status, 0); 1664 1665 KASSERT(mutex_owned(&sc->sc_lock)); 1666 1667 if (sc->sc_dying) { 1668 /* If we're dying, just do the software part. */ 1669 DPRINTFN(4, "xfer %p dying %u", xfer, xfer->ux_status, 0, 0); 1670 xfer->ux_status = status; 1671 callout_stop(&xfer->ux_callout); 1672 usb_transfer_complete(xfer); 1673 return; 1674 } 1675 1676 /* 1677 * If an abort is already in progress then just wait for it to 1678 * complete and return. 1679 */ 1680 if (xfer->ux_hcflags & UXFER_ABORTING) { 1681 DPRINTFN(4, "already aborting", 0, 0, 0, 0); 1682 #ifdef DIAGNOSTIC 1683 if (status == USBD_TIMEOUT) 1684 DPRINTFN(4, "TIMEOUT while aborting", 0, 0, 0, 0); 1685 #endif 1686 /* Override the status which might be USBD_TIMEOUT. */ 1687 xfer->ux_status = status; 1688 DPRINTFN(4, "xfer %p waiting for abort to finish", xfer, 0, 0, 1689 0); 1690 xfer->ux_hcflags |= UXFER_ABORTWAIT; 1691 while (xfer->ux_hcflags & UXFER_ABORTING) 1692 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 1693 return; 1694 } 1695 xfer->ux_hcflags |= UXFER_ABORTING; 1696 1697 /* 1698 * Step 1: Stop xfer timeout timer. 1699 */ 1700 xfer->ux_status = status; 1701 callout_stop(&xfer->ux_callout); 1702 1703 /* 1704 * Step 2: Stop execution of TD on the ring. 1705 */ 1706 switch (xhci_get_epstate(sc, xs, dci)) { 1707 case XHCI_EPSTATE_HALTED: 1708 (void)xhci_reset_endpoint_locked(xfer->ux_pipe); 1709 break; 1710 case XHCI_EPSTATE_STOPPED: 1711 break; 1712 default: 1713 (void)xhci_stop_endpoint(xfer->ux_pipe); 1714 break; 1715 } 1716 #ifdef DIAGNOSTIC 1717 uint32_t epst = xhci_get_epstate(sc, xs, dci); 1718 if (epst != XHCI_EPSTATE_STOPPED) 1719 DPRINTFN(4, "dci %u not stopped %u", dci, epst, 0, 0); 1720 #endif 1721 1722 /* 1723 * Step 3: Remove any vestiges of the xfer from the ring. 1724 */ 1725 xhci_set_dequeue_locked(xfer->ux_pipe); 1726 1727 /* 1728 * Step 4: Notify completion to waiting xfers. 1729 */ 1730 int wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 1731 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 1732 usb_transfer_complete(xfer); 1733 if (wake) { 1734 cv_broadcast(&xfer->ux_hccv); 1735 } 1736 DPRINTFN(14, "end", 0, 0, 0, 0); 1737 1738 KASSERT(mutex_owned(&sc->sc_lock)); 1739 } 1740 1741 static void 1742 xhci_host_dequeue(struct xhci_ring * const xr) 1743 { 1744 /* When dequeueing the controller, update our struct copy too */ 1745 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1746 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1747 BUS_DMASYNC_PREWRITE); 1748 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1749 1750 xr->xr_ep = 0; 1751 xr->xr_cs = 1; 1752 } 1753 1754 /* 1755 * Recover STALLed endpoint. 1756 * xHCI 1.1 sect 4.10.2.1 1757 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1758 * all transfers on transfer ring. 1759 * These are done in thread context asynchronously. 1760 */ 1761 static void 1762 xhci_clear_endpoint_stall_async_task(void *cookie) 1763 { 1764 struct usbd_xfer * const xfer = cookie; 1765 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1766 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1767 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1768 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1769 1770 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1771 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1772 1773 xhci_reset_endpoint(xfer->ux_pipe); 1774 xhci_set_dequeue(xfer->ux_pipe); 1775 1776 mutex_enter(&sc->sc_lock); 1777 tr->is_halted = false; 1778 usb_transfer_complete(xfer); 1779 mutex_exit(&sc->sc_lock); 1780 DPRINTFN(4, "ends", 0, 0, 0, 0); 1781 } 1782 1783 static usbd_status 1784 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1785 { 1786 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1787 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1788 1789 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1790 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1791 1792 if (sc->sc_dying) { 1793 return USBD_IOERROR; 1794 } 1795 1796 usb_init_task(&xp->xp_async_task, 1797 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1798 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1799 DPRINTFN(4, "ends", 0, 0, 0, 0); 1800 1801 return USBD_NORMAL_COMPLETION; 1802 } 1803 1804 /* Process roothub port status/change events and notify to uhub_intr. */ 1805 static void 1806 xhci_rhpsc(struct xhci_softc * const sc, u_int ctlrport) 1807 { 1808 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1809 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1810 ctlrport, 0, 0); 1811 1812 if (ctlrport > sc->sc_maxports) 1813 return; 1814 1815 const size_t bn = xhci_ctlrport2bus(sc, ctlrport); 1816 const size_t rhp = xhci_ctlrport2rhport(sc, ctlrport); 1817 struct usbd_xfer * const xfer = sc->sc_intrxfer[bn]; 1818 1819 DPRINTFN(4, "xhci%d: bus %d bp %u xfer %p status change", 1820 device_unit(sc->sc_dev), bn, rhp, xfer); 1821 1822 if (xfer == NULL) 1823 return; 1824 1825 uint8_t *p = xfer->ux_buf; 1826 memset(p, 0, xfer->ux_length); 1827 p[rhp / NBBY] |= 1 << (rhp % NBBY); 1828 xfer->ux_actlen = xfer->ux_length; 1829 xfer->ux_status = USBD_NORMAL_COMPLETION; 1830 usb_transfer_complete(xfer); 1831 } 1832 1833 /* Process Transfer Events */ 1834 static void 1835 xhci_event_transfer(struct xhci_softc * const sc, 1836 const struct xhci_trb * const trb) 1837 { 1838 uint64_t trb_0; 1839 uint32_t trb_2, trb_3; 1840 uint8_t trbcode; 1841 u_int slot, dci; 1842 struct xhci_slot *xs; 1843 struct xhci_ring *xr; 1844 struct xhci_xfer *xx; 1845 struct usbd_xfer *xfer; 1846 usbd_status err; 1847 1848 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1849 1850 trb_0 = le64toh(trb->trb_0); 1851 trb_2 = le32toh(trb->trb_2); 1852 trb_3 = le32toh(trb->trb_3); 1853 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1854 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1855 dci = XHCI_TRB_3_EP_GET(trb_3); 1856 xs = &sc->sc_slots[slot]; 1857 xr = &xs->xs_ep[dci].xe_tr; 1858 1859 /* sanity check */ 1860 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1861 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1862 1863 int idx = 0; 1864 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1865 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1866 DPRINTFN(0, "invalid trb_0 0x%"PRIx64, trb_0, 0, 0, 0); 1867 return; 1868 } 1869 xx = xr->xr_cookies[idx]; 1870 1871 /* clear cookie of consumed TRB */ 1872 xr->xr_cookies[idx] = NULL; 1873 1874 /* 1875 * xx is NULL if pipe is opened but xfer is not started. 1876 * It happens when stopping idle pipe. 1877 */ 1878 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1879 DPRINTFN(1, "Ignore #%u: cookie %p cc %u dci %u", 1880 idx, xx, trbcode, dci); 1881 DPRINTFN(1, " orig TRB %"PRIx64" type %u", trb_0, 1882 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1883 0, 0); 1884 return; 1885 } 1886 } else { 1887 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1888 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1889 } 1890 /* XXX this may not happen */ 1891 if (xx == NULL) { 1892 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1893 return; 1894 } 1895 xfer = &xx->xx_xfer; 1896 /* XXX this may happen when detaching */ 1897 if (xfer == NULL) { 1898 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1899 xx, trb_0, 0, 0); 1900 return; 1901 } 1902 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1903 /* XXX I dunno why this happens */ 1904 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1905 1906 if (!xfer->ux_pipe->up_repeat && 1907 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1908 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1909 return; 1910 } 1911 1912 /* 4.11.5.2 Event Data TRB */ 1913 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1914 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1915 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1916 if ((trb_0 & 0x3) == 0x3) { 1917 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1918 } 1919 } 1920 1921 switch (trbcode) { 1922 case XHCI_TRB_ERROR_SHORT_PKT: 1923 case XHCI_TRB_ERROR_SUCCESS: 1924 /* 1925 * A ctrl transfer can generate two events if it has a Data 1926 * stage. A short data stage can be OK and should not 1927 * complete the transfer as the status stage needs to be 1928 * performed. 1929 * 1930 * Note: Data and Status stage events point at same xfer. 1931 * ux_actlen and ux_dmabuf will be passed to 1932 * usb_transfer_complete after the Status stage event. 1933 * 1934 * It can be distingished which stage generates the event: 1935 * + by checking least 3 bits of trb_0 if ED==1. 1936 * (see xhci_device_ctrl_start). 1937 * + by checking the type of original TRB if ED==0. 1938 * 1939 * In addition, intr, bulk, and isoc transfer currently 1940 * consists of single TD, so the "skip" is not needed. 1941 * ctrl xfer uses EVENT_DATA, and others do not. 1942 * Thus driver can switch the flow by checking ED bit. 1943 */ 1944 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1945 if (xfer->ux_actlen == 0) 1946 xfer->ux_actlen = xfer->ux_length - 1947 XHCI_TRB_2_REM_GET(trb_2); 1948 if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)) 1949 == XHCI_TRB_TYPE_DATA_STAGE) { 1950 return; 1951 } 1952 } else if ((trb_0 & 0x3) == 0x3) { 1953 return; 1954 } 1955 err = USBD_NORMAL_COMPLETION; 1956 break; 1957 case XHCI_TRB_ERROR_STOPPED: 1958 case XHCI_TRB_ERROR_LENGTH: 1959 case XHCI_TRB_ERROR_STOPPED_SHORT: 1960 /* 1961 * don't complete the transfer being aborted 1962 * as abort_xfer does instead. 1963 */ 1964 if (xfer->ux_hcflags & UXFER_ABORTING) { 1965 DPRINTFN(14, "ignore aborting xfer %p", xfer, 0, 0, 0); 1966 return; 1967 } 1968 err = USBD_CANCELLED; 1969 break; 1970 case XHCI_TRB_ERROR_STALL: 1971 case XHCI_TRB_ERROR_BABBLE: 1972 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1973 xr->is_halted = true; 1974 err = USBD_STALLED; 1975 /* 1976 * Stalled endpoints can be recoverd by issuing 1977 * command TRB TYPE_RESET_EP on xHCI instead of 1978 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1979 * on the endpoint. However, this function may be 1980 * called from softint context (e.g. from umass), 1981 * in that case driver gets KASSERT in cv_timedwait 1982 * in xhci_do_command. 1983 * To avoid this, this runs reset_endpoint and 1984 * usb_transfer_complete in usb task thread 1985 * asynchronously (and then umass issues clear 1986 * UF_ENDPOINT_HALT). 1987 */ 1988 xfer->ux_status = err; 1989 callout_stop(&xfer->ux_callout); 1990 xhci_clear_endpoint_stall_async(xfer); 1991 return; 1992 default: 1993 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1994 err = USBD_IOERROR; 1995 break; 1996 } 1997 xfer->ux_status = err; 1998 1999 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 2000 if ((trb_0 & 0x3) == 0x0) { 2001 callout_stop(&xfer->ux_callout); 2002 usb_transfer_complete(xfer); 2003 } 2004 } else { 2005 callout_stop(&xfer->ux_callout); 2006 usb_transfer_complete(xfer); 2007 } 2008 } 2009 2010 /* Process Command complete events */ 2011 static void 2012 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 2013 { 2014 uint64_t trb_0; 2015 uint32_t trb_2, trb_3; 2016 2017 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2018 2019 KASSERT(mutex_owned(&sc->sc_lock)); 2020 2021 trb_0 = le64toh(trb->trb_0); 2022 trb_2 = le32toh(trb->trb_2); 2023 trb_3 = le32toh(trb->trb_3); 2024 2025 if (trb_0 == sc->sc_command_addr) { 2026 sc->sc_resultpending = false; 2027 2028 sc->sc_result_trb.trb_0 = trb_0; 2029 sc->sc_result_trb.trb_2 = trb_2; 2030 sc->sc_result_trb.trb_3 = trb_3; 2031 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2032 XHCI_TRB_ERROR_SUCCESS) { 2033 DPRINTFN(1, "command completion " 2034 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 2035 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 2036 } 2037 cv_signal(&sc->sc_command_cv); 2038 } else { 2039 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 2040 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 2041 trb_2, trb_3); 2042 } 2043 } 2044 2045 /* 2046 * Process events. 2047 * called from xhci_softintr 2048 */ 2049 static void 2050 xhci_handle_event(struct xhci_softc * const sc, 2051 const struct xhci_trb * const trb) 2052 { 2053 uint64_t trb_0; 2054 uint32_t trb_2, trb_3; 2055 2056 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2057 2058 trb_0 = le64toh(trb->trb_0); 2059 trb_2 = le32toh(trb->trb_2); 2060 trb_3 = le32toh(trb->trb_3); 2061 2062 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2063 trb, trb_0, trb_2, trb_3); 2064 2065 /* 2066 * 4.11.3.1, 6.4.2.1 2067 * TRB Pointer is invalid for these completion codes. 2068 */ 2069 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2070 case XHCI_TRB_ERROR_RING_UNDERRUN: 2071 case XHCI_TRB_ERROR_RING_OVERRUN: 2072 case XHCI_TRB_ERROR_VF_RING_FULL: 2073 return; 2074 default: 2075 if (trb_0 == 0) { 2076 return; 2077 } 2078 break; 2079 } 2080 2081 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2082 case XHCI_TRB_EVENT_TRANSFER: 2083 xhci_event_transfer(sc, trb); 2084 break; 2085 case XHCI_TRB_EVENT_CMD_COMPLETE: 2086 xhci_event_cmd(sc, trb); 2087 break; 2088 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2089 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2090 break; 2091 default: 2092 break; 2093 } 2094 } 2095 2096 static void 2097 xhci_softintr(void *v) 2098 { 2099 struct usbd_bus * const bus = v; 2100 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2101 struct xhci_ring * const er = &sc->sc_er; 2102 struct xhci_trb *trb; 2103 int i, j, k; 2104 2105 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2106 2107 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2108 2109 i = er->xr_ep; 2110 j = er->xr_cs; 2111 2112 DPRINTFN(16, "er: xr_ep %d xr_cs %d", i, j, 0, 0); 2113 2114 while (1) { 2115 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2116 BUS_DMASYNC_POSTREAD); 2117 trb = &er->xr_trb[i]; 2118 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2119 2120 if (j != k) 2121 break; 2122 2123 xhci_handle_event(sc, trb); 2124 2125 i++; 2126 if (i == er->xr_ntrb) { 2127 i = 0; 2128 j ^= 1; 2129 } 2130 } 2131 2132 er->xr_ep = i; 2133 er->xr_cs = j; 2134 2135 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2136 XHCI_ERDP_LO_BUSY); 2137 2138 DPRINTFN(16, "ends", 0, 0, 0, 0); 2139 2140 return; 2141 } 2142 2143 static void 2144 xhci_poll(struct usbd_bus *bus) 2145 { 2146 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2147 2148 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2149 2150 mutex_spin_enter(&sc->sc_intr_lock); 2151 xhci_intr1(sc); 2152 mutex_spin_exit(&sc->sc_intr_lock); 2153 2154 return; 2155 } 2156 2157 static struct usbd_xfer * 2158 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2159 { 2160 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2161 struct usbd_xfer *xfer; 2162 2163 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2164 2165 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 2166 if (xfer != NULL) { 2167 memset(xfer, 0, sizeof(struct xhci_xfer)); 2168 #ifdef DIAGNOSTIC 2169 xfer->ux_state = XFER_BUSY; 2170 #endif 2171 } 2172 2173 return xfer; 2174 } 2175 2176 static void 2177 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2178 { 2179 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2180 2181 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2182 2183 #ifdef DIAGNOSTIC 2184 if (xfer->ux_state != XFER_BUSY) { 2185 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 2186 xfer, xfer->ux_state, 0, 0); 2187 } 2188 xfer->ux_state = XFER_FREE; 2189 #endif 2190 pool_cache_put(sc->sc_xferpool, xfer); 2191 } 2192 2193 static void 2194 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2195 { 2196 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2197 2198 *lock = &sc->sc_lock; 2199 } 2200 2201 extern uint32_t usb_cookie_no; 2202 2203 /* 2204 * xHCI 4.3 2205 * Called when uhub_explore finds a new device (via usbd_new_device). 2206 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2207 * This function does: 2208 * Allocate and construct dev structure of default endpoint (ep0). 2209 * Allocate and open pipe of ep0. 2210 * Enable slot and initialize slot context. 2211 * Set Address. 2212 * Read initial device descriptor. 2213 * Determine initial MaxPacketSize (mps) by speed. 2214 * Read full device descriptor. 2215 * Register this device. 2216 * Finally state of device transitions ADDRESSED. 2217 */ 2218 static usbd_status 2219 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2220 int speed, int port, struct usbd_port *up) 2221 { 2222 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2223 struct usbd_device *dev; 2224 usbd_status err; 2225 usb_device_descriptor_t *dd; 2226 struct xhci_slot *xs; 2227 uint32_t *cp; 2228 2229 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2230 DPRINTFN(4, "port %u depth %u speed %u up %p", port, depth, speed, up); 2231 2232 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2233 if (dev == NULL) 2234 return USBD_NOMEM; 2235 2236 dev->ud_bus = bus; 2237 dev->ud_quirks = &usbd_no_quirk; 2238 dev->ud_addr = 0; 2239 dev->ud_ddesc.bMaxPacketSize = 0; 2240 dev->ud_depth = depth; 2241 dev->ud_powersrc = up; 2242 dev->ud_myhub = up->up_parent; 2243 dev->ud_speed = speed; 2244 dev->ud_langid = USBD_NOLANG; 2245 dev->ud_cookie.cookie = ++usb_cookie_no; 2246 2247 /* Set up default endpoint handle. */ 2248 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2249 /* doesn't matter, just don't let it uninitialized */ 2250 dev->ud_ep0.ue_toggle = 0; 2251 2252 /* Set up default endpoint descriptor. */ 2253 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2254 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2255 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2256 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2257 dev->ud_ep0desc.bInterval = 0; 2258 2259 /* 4.3, 4.8.2.1 */ 2260 switch (speed) { 2261 case USB_SPEED_SUPER: 2262 case USB_SPEED_SUPER_PLUS: 2263 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2264 break; 2265 case USB_SPEED_FULL: 2266 /* XXX using 64 as initial mps of ep0 in FS */ 2267 case USB_SPEED_HIGH: 2268 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2269 break; 2270 case USB_SPEED_LOW: 2271 default: 2272 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2273 break; 2274 } 2275 2276 up->up_dev = dev; 2277 2278 /* Establish the default pipe. */ 2279 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2280 &dev->ud_pipe0); 2281 if (err) { 2282 goto bad; 2283 } 2284 2285 dd = &dev->ud_ddesc; 2286 2287 if (depth == 0 && port == 0) { 2288 KASSERT(bus->ub_devices[USB_ROOTHUB_INDEX] == NULL); 2289 bus->ub_devices[USB_ROOTHUB_INDEX] = dev; 2290 err = usbd_get_initial_ddesc(dev, dd); 2291 if (err) { 2292 DPRINTFN(1, "get_initial_ddesc %u", err, 0, 0, 0); 2293 goto bad; 2294 } 2295 2296 err = usbd_reload_device_desc(dev); 2297 if (err) { 2298 DPRINTFN(1, "reload desc %u", err, 0, 0, 0); 2299 goto bad; 2300 } 2301 } else { 2302 uint8_t slot = 0; 2303 2304 /* 4.3.2 */ 2305 err = xhci_enable_slot(sc, &slot); 2306 if (err) { 2307 DPRINTFN(1, "enable slot %u", err, 0, 0, 0); 2308 goto bad; 2309 } 2310 2311 xs = &sc->sc_slots[slot]; 2312 dev->ud_hcpriv = xs; 2313 2314 /* 4.3.3 initialize slot structure */ 2315 err = xhci_init_slot(dev, slot); 2316 if (err) { 2317 DPRINTFN(1, "init slot %u", err, 0, 0, 0); 2318 dev->ud_hcpriv = NULL; 2319 /* 2320 * We have to disable_slot here because 2321 * xs->xs_idx == 0 when xhci_init_slot fails, 2322 * in that case usbd_remove_dev won't work. 2323 */ 2324 mutex_enter(&sc->sc_lock); 2325 xhci_disable_slot(sc, slot); 2326 mutex_exit(&sc->sc_lock); 2327 goto bad; 2328 } 2329 2330 /* 4.3.4 Address Assignment */ 2331 err = xhci_set_address(dev, slot, false); 2332 if (err) { 2333 DPRINTFN(1, "set address w/o bsr %u", err, 0, 0, 0); 2334 goto bad; 2335 } 2336 2337 /* Allow device time to set new address */ 2338 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2339 2340 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2341 //hexdump("slot context", cp, sc->sc_ctxsz); 2342 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3])); 2343 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2344 /* 2345 * XXX ensure we know when the hardware does something 2346 * we can't yet cope with 2347 */ 2348 KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr); 2349 dev->ud_addr = addr; 2350 2351 KASSERTMSG(bus->ub_devices[usb_addr2dindex(dev->ud_addr)] == NULL, 2352 "addr %d already allocated", dev->ud_addr); 2353 /* 2354 * The root hub is given its own slot 2355 */ 2356 bus->ub_devices[usb_addr2dindex(dev->ud_addr)] = dev; 2357 2358 err = usbd_get_initial_ddesc(dev, dd); 2359 if (err) { 2360 DPRINTFN(1, "get_initial_ddesc %u", err, 0, 0, 0); 2361 goto bad; 2362 } 2363 2364 /* 4.8.2.1 */ 2365 if (USB_IS_SS(speed)) { 2366 if (dd->bMaxPacketSize != 9) { 2367 printf("%s: invalid mps 2^%u for SS ep0," 2368 " using 512\n", 2369 device_xname(sc->sc_dev), 2370 dd->bMaxPacketSize); 2371 dd->bMaxPacketSize = 9; 2372 } 2373 USETW(dev->ud_ep0desc.wMaxPacketSize, 2374 (1 << dd->bMaxPacketSize)); 2375 } else 2376 USETW(dev->ud_ep0desc.wMaxPacketSize, 2377 dd->bMaxPacketSize); 2378 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2379 err = xhci_update_ep0_mps(sc, xs, 2380 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2381 if (err) { 2382 DPRINTFN(1, "update mps of ep0 %u", err, 0, 0, 0); 2383 goto bad; 2384 } 2385 2386 err = usbd_reload_device_desc(dev); 2387 if (err) { 2388 DPRINTFN(1, "reload desc %u", err, 0, 0, 0); 2389 goto bad; 2390 } 2391 } 2392 2393 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2394 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2395 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2396 dd->bDeviceClass, dd->bDeviceSubClass, 2397 dd->bDeviceProtocol, 0); 2398 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2399 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2400 dev->ud_speed); 2401 2402 usbd_get_device_strings(dev); 2403 2404 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2405 2406 if (depth == 0 && port == 0) { 2407 usbd_attach_roothub(parent, dev); 2408 DPRINTFN(1, "root hub %p", dev, 0, 0, 0); 2409 return USBD_NORMAL_COMPLETION; 2410 } 2411 2412 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2413 bad: 2414 if (err != USBD_NORMAL_COMPLETION) { 2415 usbd_remove_device(dev, up); 2416 } 2417 2418 return err; 2419 } 2420 2421 static usbd_status 2422 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2423 size_t ntrb, size_t align) 2424 { 2425 usbd_status err; 2426 size_t size = ntrb * XHCI_TRB_SIZE; 2427 2428 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2429 2430 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2431 if (err) 2432 return err; 2433 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2434 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2435 xr->xr_trb = xhci_ring_trbv(xr, 0); 2436 xr->xr_ntrb = ntrb; 2437 xr->is_halted = false; 2438 xhci_host_dequeue(xr); 2439 2440 return USBD_NORMAL_COMPLETION; 2441 } 2442 2443 static void 2444 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2445 { 2446 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2447 mutex_destroy(&xr->xr_lock); 2448 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2449 } 2450 2451 static void 2452 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2453 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2454 { 2455 size_t i; 2456 u_int ri; 2457 u_int cs; 2458 uint64_t parameter; 2459 uint32_t status; 2460 uint32_t control; 2461 2462 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2463 2464 KASSERTMSG(ntrbs <= XHCI_XFER_NTRB, "ntrbs %zu", ntrbs); 2465 for (i = 0; i < ntrbs; i++) { 2466 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2467 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2468 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2469 KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2470 XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3); 2471 } 2472 2473 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2474 2475 ri = xr->xr_ep; 2476 cs = xr->xr_cs; 2477 2478 /* 2479 * Although the xhci hardware can do scatter/gather dma from 2480 * arbitrary sized buffers, there is a non-obvious restriction 2481 * that a LINK trb is only allowed at the end of a burst of 2482 * transfers - which might be 16kB. 2483 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2484 * The simple solution is not to allow a LINK trb in the middle 2485 * of anything - as here. 2486 * XXX: (dsl) There are xhci controllers out there (eg some made by 2487 * ASMedia) that seem to lock up if they process a LINK trb but 2488 * cannot process the linked-to trb yet. 2489 * The code should write the 'cycle' bit on the link trb AFTER 2490 * adding the other trb. 2491 */ 2492 u_int firstep = xr->xr_ep; 2493 u_int firstcs = xr->xr_cs; 2494 2495 for (i = 0; i < ntrbs; ) { 2496 u_int oldri = ri; 2497 u_int oldcs = cs; 2498 2499 if (ri >= (xr->xr_ntrb - 1)) { 2500 /* Put Link TD at the end of ring */ 2501 parameter = xhci_ring_trbp(xr, 0); 2502 status = 0; 2503 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2504 XHCI_TRB_3_TC_BIT; 2505 xr->xr_cookies[ri] = NULL; 2506 xr->xr_ep = 0; 2507 xr->xr_cs ^= 1; 2508 ri = xr->xr_ep; 2509 cs = xr->xr_cs; 2510 } else { 2511 parameter = trbs[i].trb_0; 2512 status = trbs[i].trb_2; 2513 control = trbs[i].trb_3; 2514 2515 xr->xr_cookies[ri] = cookie; 2516 ri++; 2517 i++; 2518 } 2519 /* 2520 * If this is a first TRB, mark it invalid to prevent 2521 * xHC from running it immediately. 2522 */ 2523 if (oldri == firstep) { 2524 if (oldcs) { 2525 control &= ~XHCI_TRB_3_CYCLE_BIT; 2526 } else { 2527 control |= XHCI_TRB_3_CYCLE_BIT; 2528 } 2529 } else { 2530 if (oldcs) { 2531 control |= XHCI_TRB_3_CYCLE_BIT; 2532 } else { 2533 control &= ~XHCI_TRB_3_CYCLE_BIT; 2534 } 2535 } 2536 xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control); 2537 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri, 2538 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2539 } 2540 2541 /* Now invert cycle bit of first TRB */ 2542 if (firstcs) { 2543 xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 2544 } else { 2545 xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 2546 } 2547 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep, 2548 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2549 2550 xr->xr_ep = ri; 2551 xr->xr_cs = cs; 2552 2553 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2554 } 2555 2556 /* 2557 * Stop execution commands, purge all commands on command ring, and 2558 * rewind dequeue pointer. 2559 */ 2560 static void 2561 xhci_abort_command(struct xhci_softc *sc) 2562 { 2563 struct xhci_ring * const cr = &sc->sc_cr; 2564 uint64_t crcr; 2565 int i; 2566 2567 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2568 DPRINTFN(14, "command %#"PRIx64" timeout, aborting", 2569 sc->sc_command_addr, 0, 0, 0); 2570 2571 mutex_enter(&cr->xr_lock); 2572 2573 /* 4.6.1.2 Aborting a Command */ 2574 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2575 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2576 2577 for (i = 0; i < 500; i++) { 2578 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2579 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2580 break; 2581 usb_delay_ms(&sc->sc_bus, 1); 2582 } 2583 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2584 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2585 /* reset HC here? */ 2586 } 2587 2588 /* reset command ring dequeue pointer */ 2589 cr->xr_ep = 0; 2590 cr->xr_cs = 1; 2591 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2592 2593 mutex_exit(&cr->xr_lock); 2594 } 2595 2596 /* 2597 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2598 * Command completion is notified by cv_signal from xhci_event_cmd() 2599 * (called from xhci_softint), or timed-out. 2600 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2601 * then do_command examines it. 2602 */ 2603 static usbd_status 2604 xhci_do_command_locked(struct xhci_softc * const sc, 2605 struct xhci_trb * const trb, int timeout) 2606 { 2607 struct xhci_ring * const cr = &sc->sc_cr; 2608 usbd_status err; 2609 2610 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2611 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2612 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2613 2614 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2615 KASSERT(mutex_owned(&sc->sc_lock)); 2616 2617 while (sc->sc_command_addr != 0) 2618 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 2619 2620 /* 2621 * If enqueue pointer points at last of ring, it's Link TRB, 2622 * command TRB will be stored in 0th TRB. 2623 */ 2624 if (cr->xr_ep == cr->xr_ntrb - 1) 2625 sc->sc_command_addr = xhci_ring_trbp(cr, 0); 2626 else 2627 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2628 2629 sc->sc_resultpending = true; 2630 2631 mutex_enter(&cr->xr_lock); 2632 xhci_ring_put(sc, cr, NULL, trb, 1); 2633 mutex_exit(&cr->xr_lock); 2634 2635 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2636 2637 while (sc->sc_resultpending) { 2638 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2639 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2640 xhci_abort_command(sc); 2641 err = USBD_TIMEOUT; 2642 goto timedout; 2643 } 2644 } 2645 2646 trb->trb_0 = sc->sc_result_trb.trb_0; 2647 trb->trb_2 = sc->sc_result_trb.trb_2; 2648 trb->trb_3 = sc->sc_result_trb.trb_3; 2649 2650 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2651 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2652 2653 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2654 case XHCI_TRB_ERROR_SUCCESS: 2655 err = USBD_NORMAL_COMPLETION; 2656 break; 2657 default: 2658 case 192 ... 223: 2659 err = USBD_IOERROR; 2660 break; 2661 case 224 ... 255: 2662 err = USBD_NORMAL_COMPLETION; 2663 break; 2664 } 2665 2666 timedout: 2667 sc->sc_resultpending = false; 2668 sc->sc_command_addr = 0; 2669 cv_broadcast(&sc->sc_cmdbusy_cv); 2670 2671 return err; 2672 } 2673 2674 static usbd_status 2675 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2676 int timeout) 2677 { 2678 2679 mutex_enter(&sc->sc_lock); 2680 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2681 mutex_exit(&sc->sc_lock); 2682 2683 return ret; 2684 } 2685 2686 static usbd_status 2687 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2688 { 2689 struct xhci_trb trb; 2690 usbd_status err; 2691 2692 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2693 2694 trb.trb_0 = 0; 2695 trb.trb_2 = 0; 2696 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2697 2698 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2699 if (err != USBD_NORMAL_COMPLETION) { 2700 return err; 2701 } 2702 2703 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2704 2705 return err; 2706 } 2707 2708 /* 2709 * xHCI 4.6.4 2710 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2711 * All endpoints in the slot should be stopped. 2712 * Should be called with sc_lock held. 2713 */ 2714 static usbd_status 2715 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2716 { 2717 struct xhci_trb trb; 2718 struct xhci_slot *xs; 2719 usbd_status err; 2720 2721 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2722 2723 if (sc->sc_dying) 2724 return USBD_IOERROR; 2725 2726 trb.trb_0 = 0; 2727 trb.trb_2 = 0; 2728 trb.trb_3 = htole32( 2729 XHCI_TRB_3_SLOT_SET(slot) | 2730 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2731 2732 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2733 2734 if (!err) { 2735 xs = &sc->sc_slots[slot]; 2736 if (xs->xs_idx != 0) { 2737 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2738 xhci_set_dcba(sc, 0, slot); 2739 memset(xs, 0, sizeof(*xs)); 2740 } 2741 } 2742 2743 return err; 2744 } 2745 2746 /* 2747 * Set address of device and transition slot state from ENABLED to ADDRESSED 2748 * if Block Setaddress Request (BSR) is false. 2749 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2750 * see xHCI 1.1 4.5.3, 3.3.4 2751 * Should be called without sc_lock held. 2752 */ 2753 static usbd_status 2754 xhci_address_device(struct xhci_softc * const sc, 2755 uint64_t icp, uint8_t slot_id, bool bsr) 2756 { 2757 struct xhci_trb trb; 2758 usbd_status err; 2759 2760 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2761 2762 trb.trb_0 = icp; 2763 trb.trb_2 = 0; 2764 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2765 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2766 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2767 2768 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2769 2770 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2771 err = USBD_NO_ADDR; 2772 2773 return err; 2774 } 2775 2776 static usbd_status 2777 xhci_update_ep0_mps(struct xhci_softc * const sc, 2778 struct xhci_slot * const xs, u_int mps) 2779 { 2780 struct xhci_trb trb; 2781 usbd_status err; 2782 uint32_t * cp; 2783 2784 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2785 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2786 2787 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2788 cp[0] = htole32(0); 2789 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2790 2791 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2792 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2793 2794 /* sync input contexts before they are read from memory */ 2795 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2796 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2797 sc->sc_ctxsz * 4); 2798 2799 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2800 trb.trb_2 = 0; 2801 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2802 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2803 2804 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2805 return err; 2806 } 2807 2808 static void 2809 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2810 { 2811 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2812 2813 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2814 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2815 &dcbaa[si], dcba, si, 0); 2816 2817 dcbaa[si] = htole64(dcba); 2818 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2819 BUS_DMASYNC_PREWRITE); 2820 } 2821 2822 /* 2823 * Allocate device and input context DMA buffer, and 2824 * TRB DMA buffer for each endpoint. 2825 */ 2826 static usbd_status 2827 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2828 { 2829 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2830 struct xhci_slot *xs; 2831 usbd_status err; 2832 u_int dci; 2833 2834 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2835 DPRINTFN(4, "slot %u", slot, 0, 0, 0); 2836 2837 xs = &sc->sc_slots[slot]; 2838 2839 /* allocate contexts */ 2840 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2841 &xs->xs_dc_dma); 2842 if (err) 2843 return err; 2844 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2845 2846 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2847 &xs->xs_ic_dma); 2848 if (err) 2849 goto bad1; 2850 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2851 2852 for (dci = 0; dci < 32; dci++) { 2853 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2854 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2855 if (dci == XHCI_DCI_SLOT) 2856 continue; 2857 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2858 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2859 if (err) { 2860 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2861 goto bad2; 2862 } 2863 } 2864 2865 bad2: 2866 if (err == USBD_NORMAL_COMPLETION) { 2867 xs->xs_idx = slot; 2868 } else { 2869 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2870 } 2871 2872 return err; 2873 2874 bad1: 2875 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2876 xs->xs_idx = 0; 2877 return err; 2878 } 2879 2880 static void 2881 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2882 int end_dci) 2883 { 2884 u_int dci; 2885 2886 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2887 DPRINTFN(4, "slot %u start %u end %u", xs->xs_idx, start_dci, end_dci, 2888 0); 2889 2890 for (dci = start_dci; dci < end_dci; dci++) { 2891 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2892 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2893 } 2894 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2895 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2896 xs->xs_idx = 0; 2897 } 2898 2899 /* 2900 * Setup slot context, set Device Context Base Address, and issue 2901 * Set Address Device command. 2902 */ 2903 static usbd_status 2904 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 2905 { 2906 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2907 struct xhci_slot *xs; 2908 usbd_status err; 2909 2910 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2911 DPRINTFN(4, "slot %u bsr %u", slot, bsr, 0, 0); 2912 2913 xs = &sc->sc_slots[slot]; 2914 2915 xhci_setup_ctx(dev->ud_pipe0); 2916 2917 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2918 sc->sc_ctxsz * 3); 2919 2920 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2921 2922 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 2923 2924 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2925 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2926 sc->sc_ctxsz * 2); 2927 2928 return err; 2929 } 2930 2931 /* 2932 * 4.8.2, 6.2.3.2 2933 * construct slot/endpoint context parameters and do syncmem 2934 */ 2935 static void 2936 xhci_setup_ctx(struct usbd_pipe *pipe) 2937 { 2938 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2939 struct usbd_device *dev = pipe->up_dev; 2940 struct xhci_slot * const xs = dev->ud_hcpriv; 2941 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2942 const u_int dci = xhci_ep_get_dci(ed); 2943 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2944 uint32_t *cp; 2945 uint16_t mps = UGETW(ed->wMaxPacketSize); 2946 uint8_t speed = dev->ud_speed; 2947 uint8_t ival = ed->bInterval; 2948 2949 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2950 DPRINTFN(4, "pipe %p: slot %u dci %u speed %u", pipe, xs->xs_idx, dci, 2951 speed); 2952 2953 /* set up initial input control context */ 2954 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2955 cp[0] = htole32(0); 2956 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 2957 if (dci == XHCI_DCI_EP_CONTROL) 2958 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2959 cp[7] = htole32(0); 2960 2961 /* set up input slot context */ 2962 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2963 cp[0] = 2964 XHCI_SCTX_0_CTX_NUM_SET(dci) | 2965 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 2966 cp[1] = 0; 2967 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2968 cp[3] = 0; 2969 xhci_setup_route(pipe, cp); 2970 xhci_setup_tthub(pipe, cp); 2971 2972 cp[0] = htole32(cp[0]); 2973 cp[1] = htole32(cp[1]); 2974 cp[2] = htole32(cp[2]); 2975 cp[3] = htole32(cp[3]); 2976 2977 /* set up input endpoint context */ 2978 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 2979 cp[0] = 2980 XHCI_EPCTX_0_EPSTATE_SET(0) | 2981 XHCI_EPCTX_0_MULT_SET(0) | 2982 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2983 XHCI_EPCTX_0_LSA_SET(0) | 2984 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 2985 cp[1] = 2986 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 2987 XHCI_EPCTX_1_HID_SET(0) | 2988 XHCI_EPCTX_1_MAXB_SET(0); 2989 2990 if (xfertype != UE_ISOCHRONOUS) 2991 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 2992 2993 if (xfertype == UE_CONTROL) 2994 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 2995 else if (USB_IS_SS(speed)) 2996 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 2997 else 2998 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 2999 3000 xhci_setup_maxburst(pipe, cp); 3001 3002 switch (xfertype) { 3003 case UE_CONTROL: 3004 break; 3005 case UE_BULK: 3006 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 3007 break; 3008 case UE_INTERRUPT: 3009 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3010 ival = pipe->up_interval; 3011 3012 ival = xhci_bival2ival(ival, speed); 3013 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3014 break; 3015 case UE_ISOCHRONOUS: 3016 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3017 ival = pipe->up_interval; 3018 3019 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 3020 if (speed == USB_SPEED_FULL) 3021 ival += 3; /* 1ms -> 125us */ 3022 ival--; 3023 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3024 break; 3025 default: 3026 break; 3027 } 3028 DPRINTFN(4, "setting ival %u MaxBurst %#x", 3029 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 3030 3031 /* rewind TR dequeue pointer in xHC */ 3032 /* can't use xhci_ep_get_dci() yet? */ 3033 *(uint64_t *)(&cp[2]) = htole64( 3034 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 3035 XHCI_EPCTX_2_DCS_SET(1)); 3036 3037 cp[0] = htole32(cp[0]); 3038 cp[1] = htole32(cp[1]); 3039 cp[4] = htole32(cp[4]); 3040 3041 /* rewind TR dequeue pointer in driver */ 3042 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 3043 mutex_enter(&xr->xr_lock); 3044 xhci_host_dequeue(xr); 3045 mutex_exit(&xr->xr_lock); 3046 3047 /* sync input contexts before they are read from memory */ 3048 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3049 } 3050 3051 /* 3052 * Setup route string and roothub port of given device for slot context 3053 */ 3054 static void 3055 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 3056 { 3057 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3058 struct usbd_device *dev = pipe->up_dev; 3059 struct usbd_port *up = dev->ud_powersrc; 3060 struct usbd_device *hub; 3061 struct usbd_device *adev; 3062 uint8_t rhport = 0; 3063 uint32_t route = 0; 3064 3065 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3066 3067 /* Locate root hub port and Determine route string */ 3068 /* 4.3.3 route string does not include roothub port */ 3069 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 3070 uint32_t dep; 3071 3072 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 3073 hub, hub->ud_depth, hub->ud_powersrc, 3074 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 3075 3076 if (hub->ud_powersrc == NULL) 3077 break; 3078 dep = hub->ud_depth; 3079 if (dep == 0) 3080 break; 3081 rhport = hub->ud_powersrc->up_portno; 3082 if (dep > USB_HUB_MAX_DEPTH) 3083 continue; 3084 3085 route |= 3086 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 3087 << ((dep - 1) * 4); 3088 } 3089 route = route >> 4; 3090 size_t bn = hub == sc->sc_bus.ub_roothub ? 0 : 1; 3091 3092 /* Locate port on upstream high speed hub */ 3093 for (adev = dev, hub = up->up_parent; 3094 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 3095 adev = hub, hub = hub->ud_myhub) 3096 ; 3097 if (hub) { 3098 int p; 3099 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 3100 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 3101 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 3102 goto found; 3103 } 3104 } 3105 panic("%s: cannot find HS port", __func__); 3106 found: 3107 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 3108 } else { 3109 dev->ud_myhsport = NULL; 3110 } 3111 3112 const size_t ctlrport = xhci_rhport2ctlrport(sc, bn, rhport); 3113 3114 DPRINTFN(4, "rhport %u ctlrport %u Route %05x hub %p", rhport, 3115 ctlrport, route, hub); 3116 3117 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 3118 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(ctlrport); 3119 } 3120 3121 /* 3122 * Setup whether device is hub, whether device uses MTT, and 3123 * TT informations if it uses MTT. 3124 */ 3125 static void 3126 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 3127 { 3128 struct usbd_device *dev = pipe->up_dev; 3129 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 3130 uint32_t speed = dev->ud_speed; 3131 uint8_t tthubslot, ttportnum; 3132 bool ishub; 3133 bool usemtt; 3134 3135 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3136 3137 /* 3138 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 3139 * tthubslot: 3140 * This is the slot ID of parent HS hub 3141 * if LS/FS device is connected && connected through HS hub. 3142 * This is 0 if device is not LS/FS device || 3143 * parent hub is not HS hub || 3144 * attached to root hub. 3145 * ttportnum: 3146 * This is the downstream facing port of parent HS hub 3147 * if LS/FS device is connected. 3148 * This is 0 if device is not LS/FS device || 3149 * parent hub is not HS hub || 3150 * attached to root hub. 3151 */ 3152 if (dev->ud_myhsport != NULL && 3153 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3154 (dev->ud_myhub != NULL && 3155 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3156 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 3157 ttportnum = dev->ud_myhsport->up_portno; 3158 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 3159 } else { 3160 ttportnum = 0; 3161 tthubslot = 0; 3162 } 3163 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 3164 dev->ud_myhsport, ttportnum, tthubslot, 0); 3165 3166 /* ishub is valid after reading UDESC_DEVICE */ 3167 ishub = (dd->bDeviceClass == UDCLASS_HUB); 3168 3169 /* dev->ud_hub is valid after reading UDESC_HUB */ 3170 if (ishub && dev->ud_hub) { 3171 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 3172 uint8_t ttt = 3173 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 3174 3175 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 3176 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 3177 DPRINTFN(4, "nports=%d ttt=%d", hd->bNbrPorts, ttt, 0, 0); 3178 } 3179 3180 #define IS_TTHUB(dd) \ 3181 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 3182 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 3183 3184 /* 3185 * MTT flag is set if 3186 * 1. this is HS hub && MTT is enabled 3187 * or 3188 * 2. this is not hub && this is LS or FS device && 3189 * MTT of parent HS hub (and its parent, too) is enabled 3190 */ 3191 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 3192 usemtt = true; 3193 else if (!ishub && 3194 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 3195 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3196 (dev->ud_myhub != NULL && 3197 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3198 dev->ud_myhsport != NULL && 3199 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 3200 usemtt = true; 3201 else 3202 usemtt = false; 3203 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 3204 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 3205 3206 #undef IS_TTHUB 3207 3208 cp[0] |= 3209 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 3210 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 3211 cp[2] |= 3212 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 3213 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 3214 } 3215 3216 /* set up params for periodic endpoint */ 3217 static void 3218 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 3219 { 3220 struct usbd_device *dev = pipe->up_dev; 3221 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3222 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3223 usbd_desc_iter_t iter; 3224 const usb_cdc_descriptor_t *cdcd; 3225 uint32_t maxb = 0; 3226 uint16_t mps = UGETW(ed->wMaxPacketSize); 3227 uint8_t speed = dev->ud_speed; 3228 uint8_t ep; 3229 3230 /* config desc is NULL when opening ep0 */ 3231 if (dev == NULL || dev->ud_cdesc == NULL) 3232 goto no_cdcd; 3233 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 3234 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 3235 if (cdcd == NULL) 3236 goto no_cdcd; 3237 usb_desc_iter_init(dev, &iter); 3238 iter.cur = (const void *)cdcd; 3239 3240 /* find endpoint_ss_comp desc for ep of this pipe */ 3241 for (ep = 0;;) { 3242 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 3243 if (cdcd == NULL) 3244 break; 3245 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 3246 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 3247 bEndpointAddress; 3248 if (UE_GET_ADDR(ep) == 3249 UE_GET_ADDR(ed->bEndpointAddress)) { 3250 cdcd = (const usb_cdc_descriptor_t *) 3251 usb_desc_iter_next(&iter); 3252 break; 3253 } 3254 ep = 0; 3255 } 3256 } 3257 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 3258 const usb_endpoint_ss_comp_descriptor_t * esscd = 3259 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3260 maxb = esscd->bMaxBurst; 3261 } 3262 3263 no_cdcd: 3264 /* 6.2.3.4, 4.8.2.4 */ 3265 if (USB_IS_SS(speed)) { 3266 /* USB 3.1 9.6.6 */ 3267 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3268 /* USB 3.1 9.6.7 */ 3269 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3270 #ifdef notyet 3271 if (xfertype == UE_ISOCHRONOUS) { 3272 } 3273 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3274 /* use ESIT */ 3275 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3276 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3277 3278 /* XXX if LEC = 1, set ESIT instead */ 3279 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3280 } else { 3281 /* use ival */ 3282 } 3283 #endif 3284 } else { 3285 /* USB 2.0 9.6.6 */ 3286 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3287 3288 /* 6.2.3.4 */ 3289 if (speed == USB_SPEED_HIGH && 3290 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3291 maxb = UE_GET_TRANS(mps); 3292 } else { 3293 /* LS/FS or HS CTRL or HS BULK */ 3294 maxb = 0; 3295 } 3296 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3297 } 3298 } 3299 3300 /* 3301 * Convert endpoint bInterval value to endpoint context interval value 3302 * for Interrupt pipe. 3303 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3304 */ 3305 static uint32_t 3306 xhci_bival2ival(uint32_t ival, uint32_t speed) 3307 { 3308 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3309 int i; 3310 3311 /* 3312 * round ival down to "the nearest base 2 multiple of 3313 * bInterval * 8". 3314 * bInterval is at most 255 as its type is uByte. 3315 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3316 */ 3317 for (i = 10; i > 0; i--) { 3318 if ((ival * 8) >= (1 << i)) 3319 break; 3320 } 3321 ival = i; 3322 } else { 3323 /* Interval = bInterval-1 for SS/HS */ 3324 ival--; 3325 } 3326 3327 return ival; 3328 } 3329 3330 /* ----- */ 3331 3332 static void 3333 xhci_noop(struct usbd_pipe *pipe) 3334 { 3335 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3336 } 3337 3338 /* 3339 * Process root hub request. 3340 */ 3341 static int 3342 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3343 void *buf, int buflen) 3344 { 3345 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3346 usb_port_status_t ps; 3347 int l, totlen = 0; 3348 uint16_t len, value, index; 3349 int port, i; 3350 uint32_t v; 3351 3352 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3353 3354 if (sc->sc_dying) 3355 return -1; 3356 3357 size_t bn = bus == &sc->sc_bus ? 0 : 1; 3358 3359 len = UGETW(req->wLength); 3360 value = UGETW(req->wValue); 3361 index = UGETW(req->wIndex); 3362 3363 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 3364 req->bmRequestType | (req->bRequest << 8), value, index, len); 3365 3366 #define C(x,y) ((x) | ((y) << 8)) 3367 switch (C(req->bRequest, req->bmRequestType)) { 3368 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3369 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 3370 if (len == 0) 3371 break; 3372 switch (value) { 3373 case C(0, UDESC_DEVICE): { 3374 usb_device_descriptor_t devd; 3375 totlen = min(buflen, sizeof(devd)); 3376 memcpy(&devd, buf, totlen); 3377 USETW(devd.idVendor, sc->sc_id_vendor); 3378 memcpy(buf, &devd, totlen); 3379 break; 3380 } 3381 #define sd ((usb_string_descriptor_t *)buf) 3382 case C(1, UDESC_STRING): 3383 /* Vendor */ 3384 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3385 break; 3386 case C(2, UDESC_STRING): 3387 /* Product */ 3388 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3389 break; 3390 #undef sd 3391 default: 3392 /* default from usbroothub */ 3393 return buflen; 3394 } 3395 break; 3396 3397 /* Hub requests */ 3398 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3399 break; 3400 /* Clear Port Feature request */ 3401 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): { 3402 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3403 3404 DPRINTFN(4, "UR_CLEAR_PORT_FEAT bp=%d feat=%d bus=%d cp=%d", 3405 index, value, bn, cp); 3406 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3407 return -1; 3408 } 3409 port = XHCI_PORTSC(cp); 3410 v = xhci_op_read_4(sc, port); 3411 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3412 v &= ~XHCI_PS_CLEAR; 3413 switch (value) { 3414 case UHF_PORT_ENABLE: 3415 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3416 break; 3417 case UHF_PORT_SUSPEND: 3418 return -1; 3419 case UHF_PORT_POWER: 3420 break; 3421 case UHF_PORT_TEST: 3422 case UHF_PORT_INDICATOR: 3423 return -1; 3424 case UHF_C_PORT_CONNECTION: 3425 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3426 break; 3427 case UHF_C_PORT_ENABLE: 3428 case UHF_C_PORT_SUSPEND: 3429 case UHF_C_PORT_OVER_CURRENT: 3430 return -1; 3431 case UHF_C_BH_PORT_RESET: 3432 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3433 break; 3434 case UHF_C_PORT_RESET: 3435 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3436 break; 3437 case UHF_C_PORT_LINK_STATE: 3438 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3439 break; 3440 case UHF_C_PORT_CONFIG_ERROR: 3441 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3442 break; 3443 default: 3444 return -1; 3445 } 3446 break; 3447 } 3448 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3449 if (len == 0) 3450 break; 3451 if ((value & 0xff) != 0) { 3452 return -1; 3453 } 3454 usb_hub_descriptor_t hubd; 3455 3456 totlen = min(buflen, sizeof(hubd)); 3457 memcpy(&hubd, buf, totlen); 3458 hubd.bNbrPorts = sc->sc_rhportcount[bn]; 3459 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3460 hubd.bPwrOn2PwrGood = 200; 3461 for (i = 0, l = sc->sc_rhportcount[bn]; l > 0; i++, l -= 8) { 3462 /* XXX can't find out? */ 3463 hubd.DeviceRemovable[i++] = 0; 3464 } 3465 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3466 totlen = min(totlen, hubd.bDescLength); 3467 memcpy(buf, &hubd, totlen); 3468 break; 3469 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3470 if (len != 4) { 3471 return -1; 3472 } 3473 memset(buf, 0, len); /* ? XXX */ 3474 totlen = len; 3475 break; 3476 /* Get Port Status request */ 3477 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): { 3478 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3479 3480 DPRINTFN(8, "get port status bn=%d i=%d cp=%zu", bn, index, cp, 3481 0); 3482 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3483 return -1; 3484 } 3485 if (len != 4) { 3486 return -1; 3487 } 3488 v = xhci_op_read_4(sc, XHCI_PORTSC(cp)); 3489 DPRINTFN(4, "getrhportsc %d %08x", cp, v, 0, 0); 3490 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3491 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3492 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3493 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3494 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3495 if (v & XHCI_PS_PR) i |= UPS_RESET; 3496 if (v & XHCI_PS_PP) { 3497 if (i & UPS_OTHER_SPEED) 3498 i |= UPS_PORT_POWER_SS; 3499 else 3500 i |= UPS_PORT_POWER; 3501 } 3502 if (i & UPS_OTHER_SPEED) 3503 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3504 if (sc->sc_vendor_port_status) 3505 i = sc->sc_vendor_port_status(sc, v, i); 3506 USETW(ps.wPortStatus, i); 3507 i = 0; 3508 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3509 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3510 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3511 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3512 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3513 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3514 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3515 USETW(ps.wPortChange, i); 3516 totlen = min(len, sizeof(ps)); 3517 memcpy(buf, &ps, totlen); 3518 break; 3519 } 3520 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3521 return -1; 3522 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3523 break; 3524 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3525 break; 3526 /* Set Port Feature request */ 3527 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3528 int optval = (index >> 8) & 0xff; 3529 index &= 0xff; 3530 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3531 return -1; 3532 } 3533 3534 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3535 3536 port = XHCI_PORTSC(cp); 3537 v = xhci_op_read_4(sc, port); 3538 DPRINTFN(4, "index %d cp %d portsc=0x%08x", index, cp, v, 0); 3539 v &= ~XHCI_PS_CLEAR; 3540 switch (value) { 3541 case UHF_PORT_ENABLE: 3542 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3543 break; 3544 case UHF_PORT_SUSPEND: 3545 /* XXX suspend */ 3546 break; 3547 case UHF_PORT_RESET: 3548 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3549 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3550 /* Wait for reset to complete. */ 3551 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3552 if (sc->sc_dying) { 3553 return -1; 3554 } 3555 v = xhci_op_read_4(sc, port); 3556 if (v & XHCI_PS_PR) { 3557 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3558 usb_delay_ms(&sc->sc_bus, 10); 3559 /* XXX */ 3560 } 3561 break; 3562 case UHF_PORT_POWER: 3563 /* XXX power control */ 3564 break; 3565 /* XXX more */ 3566 case UHF_C_PORT_RESET: 3567 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3568 break; 3569 case UHF_PORT_U1_TIMEOUT: 3570 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3571 return -1; 3572 } 3573 port = XHCI_PORTPMSC(cp); 3574 v = xhci_op_read_4(sc, port); 3575 DPRINTFN(4, "index %d cp %d portpmsc=0x%08x", index, cp, v, 0); 3576 v &= ~XHCI_PM3_U1TO_SET(0xff); 3577 v |= XHCI_PM3_U1TO_SET(optval); 3578 xhci_op_write_4(sc, port, v); 3579 break; 3580 case UHF_PORT_U2_TIMEOUT: 3581 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3582 return -1; 3583 } 3584 port = XHCI_PORTPMSC(cp); 3585 v = xhci_op_read_4(sc, port); 3586 DPRINTFN(4, "index %d cp %d portpmsc=0x%08x", index, cp, v, 0); 3587 v &= ~XHCI_PM3_U2TO_SET(0xff); 3588 v |= XHCI_PM3_U2TO_SET(optval); 3589 xhci_op_write_4(sc, port, v); 3590 break; 3591 default: 3592 return -1; 3593 } 3594 } 3595 break; 3596 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3597 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3598 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3599 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3600 break; 3601 default: 3602 /* default from usbroothub */ 3603 return buflen; 3604 } 3605 3606 return totlen; 3607 } 3608 3609 /* root hub interrupt */ 3610 3611 static usbd_status 3612 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3613 { 3614 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3615 usbd_status err; 3616 3617 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3618 3619 /* Insert last in queue. */ 3620 mutex_enter(&sc->sc_lock); 3621 err = usb_insert_transfer(xfer); 3622 mutex_exit(&sc->sc_lock); 3623 if (err) 3624 return err; 3625 3626 /* Pipe isn't running, start first */ 3627 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3628 } 3629 3630 /* Wait for roothub port status/change */ 3631 static usbd_status 3632 xhci_root_intr_start(struct usbd_xfer *xfer) 3633 { 3634 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3635 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3636 3637 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3638 3639 if (sc->sc_dying) 3640 return USBD_IOERROR; 3641 3642 mutex_enter(&sc->sc_lock); 3643 sc->sc_intrxfer[bn] = xfer; 3644 mutex_exit(&sc->sc_lock); 3645 3646 return USBD_IN_PROGRESS; 3647 } 3648 3649 static void 3650 xhci_root_intr_abort(struct usbd_xfer *xfer) 3651 { 3652 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3653 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3654 3655 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3656 3657 KASSERT(mutex_owned(&sc->sc_lock)); 3658 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3659 3660 sc->sc_intrxfer[bn] = NULL; 3661 3662 xfer->ux_status = USBD_CANCELLED; 3663 usb_transfer_complete(xfer); 3664 } 3665 3666 static void 3667 xhci_root_intr_close(struct usbd_pipe *pipe) 3668 { 3669 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3670 const struct usbd_xfer *xfer = pipe->up_intrxfer; 3671 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3672 3673 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3674 3675 KASSERT(mutex_owned(&sc->sc_lock)); 3676 3677 sc->sc_intrxfer[bn] = NULL; 3678 } 3679 3680 static void 3681 xhci_root_intr_done(struct usbd_xfer *xfer) 3682 { 3683 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3684 3685 } 3686 3687 /* -------------- */ 3688 /* device control */ 3689 3690 static usbd_status 3691 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3692 { 3693 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3694 usbd_status err; 3695 3696 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3697 3698 /* Insert last in queue. */ 3699 mutex_enter(&sc->sc_lock); 3700 err = usb_insert_transfer(xfer); 3701 mutex_exit(&sc->sc_lock); 3702 if (err) 3703 return err; 3704 3705 /* Pipe isn't running, start first */ 3706 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3707 } 3708 3709 static usbd_status 3710 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3711 { 3712 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3713 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3714 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3715 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3716 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3717 usb_device_request_t * const req = &xfer->ux_request; 3718 const int isread = usbd_xfer_isread(xfer); 3719 const uint32_t len = UGETW(req->wLength); 3720 usb_dma_t * const dma = &xfer->ux_dmabuf; 3721 uint64_t parameter; 3722 uint32_t status; 3723 uint32_t control; 3724 u_int i; 3725 3726 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3727 DPRINTFN(12, "req: %04x %04x %04x %04x", 3728 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3729 UGETW(req->wIndex), UGETW(req->wLength)); 3730 3731 /* we rely on the bottom bits for extra info */ 3732 KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx", 3733 (uintptr_t) xfer); 3734 3735 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3736 3737 i = 0; 3738 3739 /* setup phase */ 3740 memcpy(¶meter, req, sizeof(parameter)); 3741 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3742 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3743 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3744 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3745 XHCI_TRB_3_IDT_BIT; 3746 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3747 3748 if (len != 0) { 3749 /* data phase */ 3750 parameter = DMAADDR(dma, 0); 3751 KASSERTMSG(len <= 0x10000, "len %d", len); 3752 status = XHCI_TRB_2_IRQ_SET(0) | 3753 XHCI_TRB_2_TDSZ_SET(1) | 3754 XHCI_TRB_2_BYTES_SET(len); 3755 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3756 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3757 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3758 XHCI_TRB_3_IOC_BIT; 3759 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3760 } 3761 3762 parameter = 0; 3763 status = XHCI_TRB_2_IRQ_SET(0); 3764 /* the status stage has inverted direction */ 3765 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3766 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3767 XHCI_TRB_3_IOC_BIT; 3768 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3769 3770 mutex_enter(&tr->xr_lock); 3771 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3772 mutex_exit(&tr->xr_lock); 3773 3774 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3775 3776 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3777 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3778 xhci_timeout, xfer); 3779 } 3780 3781 return USBD_IN_PROGRESS; 3782 } 3783 3784 static void 3785 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3786 { 3787 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3788 usb_device_request_t *req = &xfer->ux_request; 3789 int len = UGETW(req->wLength); 3790 int rd = req->bmRequestType & UT_READ; 3791 3792 if (len) 3793 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3794 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3795 } 3796 3797 static void 3798 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3799 { 3800 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3801 3802 xhci_abort_xfer(xfer, USBD_CANCELLED); 3803 } 3804 3805 static void 3806 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3807 { 3808 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3809 3810 xhci_close_pipe(pipe); 3811 } 3812 3813 /* ------------------ */ 3814 /* device isochronous */ 3815 3816 /* ----------- */ 3817 /* device bulk */ 3818 3819 static usbd_status 3820 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3821 { 3822 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3823 usbd_status err; 3824 3825 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3826 3827 /* Insert last in queue. */ 3828 mutex_enter(&sc->sc_lock); 3829 err = usb_insert_transfer(xfer); 3830 mutex_exit(&sc->sc_lock); 3831 if (err) 3832 return err; 3833 3834 /* 3835 * Pipe isn't running (otherwise err would be USBD_INPROG), 3836 * so start it first. 3837 */ 3838 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3839 } 3840 3841 static usbd_status 3842 xhci_device_bulk_start(struct usbd_xfer *xfer) 3843 { 3844 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3845 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3846 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3847 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3848 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3849 const uint32_t len = xfer->ux_length; 3850 usb_dma_t * const dma = &xfer->ux_dmabuf; 3851 uint64_t parameter; 3852 uint32_t status; 3853 uint32_t control; 3854 u_int i = 0; 3855 3856 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3857 3858 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3859 3860 if (sc->sc_dying) 3861 return USBD_IOERROR; 3862 3863 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3864 3865 parameter = DMAADDR(dma, 0); 3866 /* 3867 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3868 * If the user supplied buffer crosses such a boundary then 2 3869 * (or more) TRB should be used. 3870 * If multiple TRB are used the td_size field must be set correctly. 3871 * For v1.0 devices (like ivy bridge) this is the number of usb data 3872 * blocks needed to complete the transfer. 3873 * Setting it to 1 in the last TRB causes an extra zero-length 3874 * data block be sent. 3875 * The earlier documentation differs, I don't know how it behaves. 3876 */ 3877 KASSERTMSG(len <= 0x10000, "len %d", len); 3878 status = XHCI_TRB_2_IRQ_SET(0) | 3879 XHCI_TRB_2_TDSZ_SET(1) | 3880 XHCI_TRB_2_BYTES_SET(len); 3881 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3882 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3883 XHCI_TRB_3_IOC_BIT; 3884 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3885 3886 mutex_enter(&tr->xr_lock); 3887 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3888 mutex_exit(&tr->xr_lock); 3889 3890 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3891 3892 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3893 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3894 xhci_timeout, xfer); 3895 } 3896 3897 return USBD_IN_PROGRESS; 3898 } 3899 3900 static void 3901 xhci_device_bulk_done(struct usbd_xfer *xfer) 3902 { 3903 #ifdef USB_DEBUG 3904 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3905 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3906 #endif 3907 const int isread = usbd_xfer_isread(xfer); 3908 3909 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3910 3911 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3912 3913 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3914 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3915 } 3916 3917 static void 3918 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3919 { 3920 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3921 3922 xhci_abort_xfer(xfer, USBD_CANCELLED); 3923 } 3924 3925 static void 3926 xhci_device_bulk_close(struct usbd_pipe *pipe) 3927 { 3928 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3929 3930 xhci_close_pipe(pipe); 3931 } 3932 3933 /* ---------------- */ 3934 /* device interrupt */ 3935 3936 static usbd_status 3937 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3938 { 3939 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3940 usbd_status err; 3941 3942 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3943 3944 /* Insert last in queue. */ 3945 mutex_enter(&sc->sc_lock); 3946 err = usb_insert_transfer(xfer); 3947 mutex_exit(&sc->sc_lock); 3948 if (err) 3949 return err; 3950 3951 /* 3952 * Pipe isn't running (otherwise err would be USBD_INPROG), 3953 * so start it first. 3954 */ 3955 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3956 } 3957 3958 static usbd_status 3959 xhci_device_intr_start(struct usbd_xfer *xfer) 3960 { 3961 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3962 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3963 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3964 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3965 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3966 const uint32_t len = xfer->ux_length; 3967 usb_dma_t * const dma = &xfer->ux_dmabuf; 3968 uint64_t parameter; 3969 uint32_t status; 3970 uint32_t control; 3971 u_int i = 0; 3972 3973 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3974 3975 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3976 3977 if (sc->sc_dying) 3978 return USBD_IOERROR; 3979 3980 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3981 3982 parameter = DMAADDR(dma, 0); 3983 KASSERTMSG(len <= 0x10000, "len %d", len); 3984 status = XHCI_TRB_2_IRQ_SET(0) | 3985 XHCI_TRB_2_TDSZ_SET(1) | 3986 XHCI_TRB_2_BYTES_SET(len); 3987 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3988 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3989 XHCI_TRB_3_IOC_BIT; 3990 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3991 3992 mutex_enter(&tr->xr_lock); 3993 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3994 mutex_exit(&tr->xr_lock); 3995 3996 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3997 3998 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3999 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4000 xhci_timeout, xfer); 4001 } 4002 4003 return USBD_IN_PROGRESS; 4004 } 4005 4006 static void 4007 xhci_device_intr_done(struct usbd_xfer *xfer) 4008 { 4009 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4010 #ifdef USB_DEBUG 4011 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4012 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4013 #endif 4014 const int isread = usbd_xfer_isread(xfer); 4015 4016 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4017 4018 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 4019 4020 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4021 4022 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4023 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4024 } 4025 4026 static void 4027 xhci_device_intr_abort(struct usbd_xfer *xfer) 4028 { 4029 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4030 4031 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4032 4033 KASSERT(mutex_owned(&sc->sc_lock)); 4034 DPRINTFN(15, "%p", xfer, 0, 0, 0); 4035 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4036 xhci_abort_xfer(xfer, USBD_CANCELLED); 4037 } 4038 4039 static void 4040 xhci_device_intr_close(struct usbd_pipe *pipe) 4041 { 4042 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 4043 4044 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4045 DPRINTFN(15, "%p", pipe, 0, 0, 0); 4046 4047 xhci_close_pipe(pipe); 4048 } 4049 4050 /* ------------ */ 4051 4052 static void 4053 xhci_timeout(void *addr) 4054 { 4055 struct xhci_xfer * const xx = addr; 4056 struct usbd_xfer * const xfer = &xx->xx_xfer; 4057 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4058 4059 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4060 4061 if (sc->sc_dying) { 4062 return; 4063 } 4064 4065 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 4066 USB_TASKQ_MPSAFE); 4067 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 4068 USB_TASKQ_HC); 4069 } 4070 4071 static void 4072 xhci_timeout_task(void *addr) 4073 { 4074 struct usbd_xfer * const xfer = addr; 4075 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4076 4077 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4078 4079 mutex_enter(&sc->sc_lock); 4080 xhci_abort_xfer(xfer, USBD_TIMEOUT); 4081 mutex_exit(&sc->sc_lock); 4082 } 4083
Indexes created Wed Sep 24 22:09:59 GMT 2025