xhci.c revision 1.70
1 /* $NetBSD: xhci.c,v 1.70 2017/01/21 07:39:30 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.70 2017/01/21 07:39:30 skrll Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static void xhci_host_dequeue(struct xhci_ring * const); 146 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 147 148 static usbd_status xhci_do_command(struct xhci_softc * const, 149 struct xhci_trb * const, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 153 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 154 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 155 static usbd_status xhci_enable_slot(struct xhci_softc * const, 156 uint8_t * const); 157 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 158 static usbd_status xhci_address_device(struct xhci_softc * const, 159 uint64_t, uint8_t, bool); 160 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 161 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 162 struct xhci_slot * const, u_int); 163 static usbd_status xhci_ring_init(struct xhci_softc * const, 164 struct xhci_ring * const, size_t, size_t); 165 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 166 167 static void xhci_setup_ctx(struct usbd_pipe *); 168 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 169 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 170 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 171 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 172 173 static void xhci_noop(struct usbd_pipe *); 174 175 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 176 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 177 static void xhci_root_intr_abort(struct usbd_xfer *); 178 static void xhci_root_intr_close(struct usbd_pipe *); 179 static void xhci_root_intr_done(struct usbd_xfer *); 180 181 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 182 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 183 static void xhci_device_ctrl_abort(struct usbd_xfer *); 184 static void xhci_device_ctrl_close(struct usbd_pipe *); 185 static void xhci_device_ctrl_done(struct usbd_xfer *); 186 187 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 188 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 189 static void xhci_device_intr_abort(struct usbd_xfer *); 190 static void xhci_device_intr_close(struct usbd_pipe *); 191 static void xhci_device_intr_done(struct usbd_xfer *); 192 193 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 194 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 195 static void xhci_device_bulk_abort(struct usbd_xfer *); 196 static void xhci_device_bulk_close(struct usbd_pipe *); 197 static void xhci_device_bulk_done(struct usbd_xfer *); 198 199 static void xhci_timeout(void *); 200 static void xhci_timeout_task(void *); 201 202 static const struct usbd_bus_methods xhci_bus_methods = { 203 .ubm_open = xhci_open, 204 .ubm_softint = xhci_softintr, 205 .ubm_dopoll = xhci_poll, 206 .ubm_allocx = xhci_allocx, 207 .ubm_freex = xhci_freex, 208 .ubm_getlock = xhci_get_lock, 209 .ubm_newdev = xhci_new_device, 210 .ubm_rhctrl = xhci_roothub_ctrl, 211 }; 212 213 static const struct usbd_pipe_methods xhci_root_intr_methods = { 214 .upm_transfer = xhci_root_intr_transfer, 215 .upm_start = xhci_root_intr_start, 216 .upm_abort = xhci_root_intr_abort, 217 .upm_close = xhci_root_intr_close, 218 .upm_cleartoggle = xhci_noop, 219 .upm_done = xhci_root_intr_done, 220 }; 221 222 223 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 224 .upm_transfer = xhci_device_ctrl_transfer, 225 .upm_start = xhci_device_ctrl_start, 226 .upm_abort = xhci_device_ctrl_abort, 227 .upm_close = xhci_device_ctrl_close, 228 .upm_cleartoggle = xhci_noop, 229 .upm_done = xhci_device_ctrl_done, 230 }; 231 232 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 233 .upm_cleartoggle = xhci_noop, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 237 .upm_transfer = xhci_device_bulk_transfer, 238 .upm_start = xhci_device_bulk_start, 239 .upm_abort = xhci_device_bulk_abort, 240 .upm_close = xhci_device_bulk_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_bulk_done, 243 }; 244 245 static const struct usbd_pipe_methods xhci_device_intr_methods = { 246 .upm_transfer = xhci_device_intr_transfer, 247 .upm_start = xhci_device_intr_start, 248 .upm_abort = xhci_device_intr_abort, 249 .upm_close = xhci_device_intr_close, 250 .upm_cleartoggle = xhci_noop, 251 .upm_done = xhci_device_intr_done, 252 }; 253 254 static inline uint32_t 255 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 256 { 257 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 258 } 259 260 static inline uint32_t 261 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 262 { 263 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 264 } 265 266 static inline void 267 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 268 uint32_t value) 269 { 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 271 } 272 273 #if 0 /* unused */ 274 static inline void 275 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 276 uint32_t value) 277 { 278 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 279 } 280 #endif /* unused */ 281 282 static inline uint32_t 283 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 284 { 285 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 286 } 287 288 static inline uint32_t 289 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 290 { 291 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 292 } 293 294 static inline void 295 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 296 uint32_t value) 297 { 298 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 299 } 300 301 static inline uint64_t 302 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 303 { 304 uint64_t value; 305 306 if (sc->sc_ac64) { 307 #ifdef XHCI_USE_BUS_SPACE_8 308 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 309 #else 310 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 311 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 312 offset + 4) << 32; 313 #endif 314 } else { 315 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 316 } 317 318 return value; 319 } 320 321 static inline void 322 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 336 } 337 } 338 339 static inline uint32_t 340 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 341 { 342 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 343 } 344 345 static inline void 346 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 347 uint32_t value) 348 { 349 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 350 } 351 352 #if 0 /* unused */ 353 static inline uint64_t 354 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 355 { 356 uint64_t value; 357 358 if (sc->sc_ac64) { 359 #ifdef XHCI_USE_BUS_SPACE_8 360 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 361 #else 362 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 363 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 364 offset + 4) << 32; 365 #endif 366 } else { 367 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 368 } 369 370 return value; 371 } 372 #endif /* unused */ 373 374 static inline void 375 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 376 uint64_t value) 377 { 378 if (sc->sc_ac64) { 379 #ifdef XHCI_USE_BUS_SPACE_8 380 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 381 #else 382 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 383 (value >> 0) & 0xffffffff); 384 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 385 (value >> 32) & 0xffffffff); 386 #endif 387 } else { 388 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 389 } 390 } 391 392 #if 0 /* unused */ 393 static inline uint32_t 394 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 395 { 396 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 397 } 398 #endif /* unused */ 399 400 static inline void 401 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 402 uint32_t value) 403 { 404 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 405 } 406 407 /* --- */ 408 409 static inline uint8_t 410 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 411 { 412 u_int eptype = 0; 413 414 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 415 case UE_CONTROL: 416 eptype = 0x0; 417 break; 418 case UE_ISOCHRONOUS: 419 eptype = 0x1; 420 break; 421 case UE_BULK: 422 eptype = 0x2; 423 break; 424 case UE_INTERRUPT: 425 eptype = 0x3; 426 break; 427 } 428 429 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 430 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 431 return eptype | 0x4; 432 else 433 return eptype; 434 } 435 436 static u_int 437 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 438 { 439 /* xHCI 1.0 section 4.5.1 */ 440 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 441 u_int in = 0; 442 443 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 444 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 445 in = 1; 446 447 return epaddr * 2 + in; 448 } 449 450 static inline u_int 451 xhci_dci_to_ici(const u_int i) 452 { 453 return i + 1; 454 } 455 456 static inline void * 457 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 458 const u_int dci) 459 { 460 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 461 } 462 463 #if 0 /* unused */ 464 static inline bus_addr_t 465 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 466 const u_int dci) 467 { 468 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 469 } 470 #endif /* unused */ 471 472 static inline void * 473 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline bus_addr_t 480 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 481 const u_int ici) 482 { 483 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 484 } 485 486 static inline struct xhci_trb * 487 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 488 { 489 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 490 } 491 492 static inline bus_addr_t 493 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 494 { 495 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 496 } 497 498 static inline void 499 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 500 uint32_t control) 501 { 502 trb->trb_0 = htole64(parameter); 503 trb->trb_2 = htole32(status); 504 trb->trb_3 = htole32(control); 505 } 506 507 static int 508 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 509 { 510 /* base address of TRBs */ 511 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 512 513 /* trb_0 range sanity check */ 514 if (trb_0 == 0 || trb_0 < trbp || 515 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 516 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 517 return 1; 518 } 519 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 520 return 0; 521 } 522 523 static unsigned int 524 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 525 u_int dci) 526 { 527 uint32_t *cp; 528 529 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 530 cp = xhci_slot_get_dcv(sc, xs, dci); 531 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 532 } 533 534 static inline unsigned int 535 xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport) 536 { 537 const unsigned int port = ctlrport - 1; 538 const uint8_t bit = __BIT(port % NBBY); 539 540 return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit); 541 } 542 543 /* 544 * Return the roothub port for a controller port. Both are 1..n. 545 */ 546 static inline unsigned int 547 xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport) 548 { 549 550 return sc->sc_ctlrportmap[ctrlport - 1]; 551 } 552 553 /* 554 * Return the controller port for a bus roothub port. Both are 1..n. 555 */ 556 static inline unsigned int 557 xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn, 558 unsigned int rhport) 559 { 560 561 return sc->sc_rhportmap[bn][rhport - 1]; 562 } 563 564 /* --- */ 565 566 void 567 xhci_childdet(device_t self, device_t child) 568 { 569 struct xhci_softc * const sc = device_private(self); 570 571 KASSERT(sc->sc_child == child); 572 if (child == sc->sc_child) 573 sc->sc_child = NULL; 574 } 575 576 int 577 xhci_detach(struct xhci_softc *sc, int flags) 578 { 579 int rv = 0; 580 581 if (sc->sc_child2 != NULL) { 582 rv = config_detach(sc->sc_child2, flags); 583 if (rv != 0) 584 return rv; 585 } 586 587 if (sc->sc_child != NULL) { 588 rv = config_detach(sc->sc_child, flags); 589 if (rv != 0) 590 return rv; 591 } 592 593 /* XXX unconfigure/free slots */ 594 595 /* verify: */ 596 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 597 xhci_op_write_4(sc, XHCI_USBCMD, 0); 598 /* do we need to wait for stop? */ 599 600 xhci_op_write_8(sc, XHCI_CRCR, 0); 601 xhci_ring_free(sc, &sc->sc_cr); 602 cv_destroy(&sc->sc_command_cv); 603 cv_destroy(&sc->sc_cmdbusy_cv); 604 605 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 606 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 607 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 608 xhci_ring_free(sc, &sc->sc_er); 609 610 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 611 612 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 613 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 614 615 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 616 617 kmem_free(sc->sc_ctlrportbus, 618 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY)); 619 kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int)); 620 621 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 622 kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int)); 623 } 624 625 mutex_destroy(&sc->sc_lock); 626 mutex_destroy(&sc->sc_intr_lock); 627 628 pool_cache_destroy(sc->sc_xferpool); 629 630 return rv; 631 } 632 633 int 634 xhci_activate(device_t self, enum devact act) 635 { 636 struct xhci_softc * const sc = device_private(self); 637 638 switch (act) { 639 case DVACT_DEACTIVATE: 640 sc->sc_dying = true; 641 return 0; 642 default: 643 return EOPNOTSUPP; 644 } 645 } 646 647 bool 648 xhci_suspend(device_t dv, const pmf_qual_t *qual) 649 { 650 return false; 651 } 652 653 bool 654 xhci_resume(device_t dv, const pmf_qual_t *qual) 655 { 656 return false; 657 } 658 659 bool 660 xhci_shutdown(device_t self, int flags) 661 { 662 return false; 663 } 664 665 static int 666 xhci_hc_reset(struct xhci_softc * const sc) 667 { 668 uint32_t usbcmd, usbsts; 669 int i; 670 671 /* Check controller not ready */ 672 for (i = 0; i < XHCI_WAIT_CNR; i++) { 673 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 674 if ((usbsts & XHCI_STS_CNR) == 0) 675 break; 676 usb_delay_ms(&sc->sc_bus, 1); 677 } 678 if (i >= XHCI_WAIT_CNR) { 679 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 680 return EIO; 681 } 682 683 /* Halt controller */ 684 usbcmd = 0; 685 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 686 usb_delay_ms(&sc->sc_bus, 1); 687 688 /* Reset controller */ 689 usbcmd = XHCI_CMD_HCRST; 690 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 691 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 692 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 693 if ((usbcmd & XHCI_CMD_HCRST) == 0) 694 break; 695 usb_delay_ms(&sc->sc_bus, 1); 696 } 697 if (i >= XHCI_WAIT_HCRST) { 698 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 699 return EIO; 700 } 701 702 /* Check controller not ready */ 703 for (i = 0; i < XHCI_WAIT_CNR; i++) { 704 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 705 if ((usbsts & XHCI_STS_CNR) == 0) 706 break; 707 usb_delay_ms(&sc->sc_bus, 1); 708 } 709 if (i >= XHCI_WAIT_CNR) { 710 aprint_error_dev(sc->sc_dev, 711 "controller not ready timeout after reset\n"); 712 return EIO; 713 } 714 715 return 0; 716 } 717 718 719 static void 720 hexdump(const char *msg, const void *base, size_t len) 721 { 722 #if 0 723 size_t cnt; 724 const uint32_t *p; 725 extern paddr_t vtophys(vaddr_t); 726 727 p = base; 728 cnt = 0; 729 730 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 731 (void *)vtophys((vaddr_t)base)); 732 733 while (cnt < len) { 734 if (cnt % 16 == 0) 735 printf("%p: ", p); 736 else if (cnt % 8 == 0) 737 printf(" |"); 738 printf(" %08x", *p++); 739 cnt += 4; 740 if (cnt % 16 == 0) 741 printf("\n"); 742 } 743 if (cnt % 16 != 0) 744 printf("\n"); 745 #endif 746 } 747 748 /* 7.2 xHCI Support Protocol Capability */ 749 static void 750 xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp) 751 { 752 /* XXX Cache this lot */ 753 754 const uint32_t w0 = xhci_read_4(sc, ecp); 755 const uint32_t w4 = xhci_read_4(sc, ecp + 4); 756 const uint32_t w8 = xhci_read_4(sc, ecp + 8); 757 const uint32_t wc = xhci_read_4(sc, ecp + 0xc); 758 759 aprint_debug_dev(sc->sc_dev, 760 " SP: %08x %08x %08x %08x\n", w0, w4, w8, wc); 761 762 if (w4 != XHCI_XECP_USBID) 763 return; 764 765 const int major = XHCI_XECP_SP_W0_MAJOR(w0); 766 const int minor = XHCI_XECP_SP_W0_MINOR(w0); 767 const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8); 768 const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8); 769 770 const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16)); 771 switch (mm) { 772 case 0x0200: 773 case 0x0300: 774 case 0x0301: 775 aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n", 776 major == 3 ? "ss" : "hs", cpo, cpo + cpc -1); 777 break; 778 default: 779 aprint_debug_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n", 780 major, minor); 781 return; 782 } 783 784 const size_t bus = (major == 3) ? 0 : 1; 785 786 /* Index arrays with 0..n-1 where ports are numbered 1..n */ 787 for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) { 788 if (sc->sc_ctlrportmap[cp] != 0) { 789 aprint_error_dev(sc->sc_dev, "contoller port %zu " 790 "already assigned", cp); 791 continue; 792 } 793 794 sc->sc_ctlrportbus[cp / NBBY] |= 795 bus == 0 ? 0 : __BIT(cp % NBBY); 796 797 const size_t rhp = sc->sc_rhportcount[bus]++; 798 799 KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0, 800 "bus %zu rhp %zu is %d", bus, rhp, 801 sc->sc_rhportmap[bus][rhp]); 802 803 sc->sc_rhportmap[bus][rhp] = cp + 1; 804 sc->sc_ctlrportmap[cp] = rhp + 1; 805 } 806 } 807 808 /* Process extended capabilities */ 809 static void 810 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 811 { 812 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 813 814 bus_size_t ecp = XHCI_HCC_XECP(hcc) * 4; 815 while (ecp != 0) { 816 uint32_t ecr = xhci_read_4(sc, ecp); 817 aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr); 818 switch (XHCI_XECP_ID(ecr)) { 819 case XHCI_ID_PROTOCOLS: { 820 xhci_id_protocols(sc, ecp); 821 break; 822 } 823 case XHCI_ID_USB_LEGACY: { 824 uint8_t bios_sem; 825 826 /* Take host controller ownership from BIOS */ 827 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 828 if (bios_sem) { 829 /* sets xHCI to be owned by OS */ 830 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 831 aprint_debug_dev(sc->sc_dev, 832 "waiting for BIOS to give up control\n"); 833 for (int i = 0; i < 5000; i++) { 834 bios_sem = xhci_read_1(sc, ecp + 835 XHCI_XECP_BIOS_SEM); 836 if (bios_sem == 0) 837 break; 838 DELAY(1000); 839 } 840 if (bios_sem) { 841 aprint_error_dev(sc->sc_dev, 842 "timed out waiting for BIOS\n"); 843 } 844 } 845 break; 846 } 847 default: 848 break; 849 } 850 ecr = xhci_read_4(sc, ecp); 851 if (XHCI_XECP_NEXT(ecr) == 0) { 852 ecp = 0; 853 } else { 854 ecp += XHCI_XECP_NEXT(ecr) * 4; 855 } 856 } 857 } 858 859 #define XHCI_HCCPREV1_BITS \ 860 "\177\020" /* New bitmask */ \ 861 "f\020\020XECP\0" \ 862 "f\014\4MAXPSA\0" \ 863 "b\013CFC\0" \ 864 "b\012SEC\0" \ 865 "b\011SBD\0" \ 866 "b\010FSE\0" \ 867 "b\7NSS\0" \ 868 "b\6LTC\0" \ 869 "b\5LHRC\0" \ 870 "b\4PIND\0" \ 871 "b\3PPC\0" \ 872 "b\2CZC\0" \ 873 "b\1BNC\0" \ 874 "b\0AC64\0" \ 875 "\0" 876 #define XHCI_HCCV1_x_BITS \ 877 "\177\020" /* New bitmask */ \ 878 "f\020\020XECP\0" \ 879 "f\014\4MAXPSA\0" \ 880 "b\013CFC\0" \ 881 "b\012SEC\0" \ 882 "b\011SPC\0" \ 883 "b\010PAE\0" \ 884 "b\7NSS\0" \ 885 "b\6LTC\0" \ 886 "b\5LHRC\0" \ 887 "b\4PIND\0" \ 888 "b\3PPC\0" \ 889 "b\2CSZ\0" \ 890 "b\1BNC\0" \ 891 "b\0AC64\0" \ 892 "\0" 893 894 int 895 xhci_init(struct xhci_softc *sc) 896 { 897 bus_size_t bsz; 898 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 899 uint32_t pagesize, config; 900 int i = 0; 901 uint16_t hciversion; 902 uint8_t caplength; 903 904 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 905 906 /* Set up the bus struct for the usb 3 and usb 2 buses */ 907 sc->sc_bus.ub_methods = &xhci_bus_methods; 908 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 909 sc->sc_bus.ub_revision = USBREV_3_0; 910 sc->sc_bus.ub_usedma = true; 911 sc->sc_bus.ub_hcpriv = sc; 912 913 sc->sc_bus2.ub_methods = &xhci_bus_methods; 914 sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe); 915 sc->sc_bus2.ub_revision = USBREV_2_0; 916 sc->sc_bus2.ub_usedma = true; 917 sc->sc_bus2.ub_hcpriv = sc; 918 sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag; 919 920 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 921 caplength = XHCI_CAP_CAPLENGTH(cap); 922 hciversion = XHCI_CAP_HCIVERSION(cap); 923 924 if (hciversion < XHCI_HCIVERSION_0_96 || 925 hciversion > XHCI_HCIVERSION_1_0) { 926 aprint_normal_dev(sc->sc_dev, 927 "xHCI version %x.%x not known to be supported\n", 928 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 929 } else { 930 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 931 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 932 } 933 934 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 935 &sc->sc_cbh) != 0) { 936 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 937 return ENOMEM; 938 } 939 940 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 941 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 942 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 943 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 944 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 945 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 946 aprint_debug_dev(sc->sc_dev, 947 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 948 949 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 950 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 951 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 952 953 char sbuf[128]; 954 if (hciversion < XHCI_HCIVERSION_1_0) 955 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 956 else 957 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 958 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 959 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 960 961 /* default all ports to bus 0, i.e. usb 3 */ 962 sc->sc_ctlrportbus = kmem_zalloc( 963 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP); 964 sc->sc_ctlrportmap = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 965 966 /* controller port to bus roothub port map */ 967 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 968 sc->sc_rhportmap[j] = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 969 } 970 971 /* 972 * Process all Extended Capabilities 973 */ 974 xhci_ecp(sc, hcc); 975 976 bsz = XHCI_PORTSC(sc->sc_maxports); 977 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 978 &sc->sc_obh) != 0) { 979 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 980 return ENOMEM; 981 } 982 983 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 984 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 985 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 986 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 987 return ENOMEM; 988 } 989 990 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 991 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 992 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 993 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 994 return ENOMEM; 995 } 996 997 int rv; 998 rv = xhci_hc_reset(sc); 999 if (rv != 0) { 1000 return rv; 1001 } 1002 1003 if (sc->sc_vendor_init) 1004 sc->sc_vendor_init(sc); 1005 1006 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 1007 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 1008 pagesize = ffs(pagesize); 1009 if (pagesize == 0) { 1010 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 1011 return EIO; 1012 } 1013 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 1014 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 1015 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 1016 (uint32_t)sc->sc_maxslots); 1017 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 1018 1019 usbd_status err; 1020 1021 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 1022 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 1023 if (sc->sc_maxspbuf != 0) { 1024 err = usb_allocmem(&sc->sc_bus, 1025 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 1026 &sc->sc_spbufarray_dma); 1027 if (err) { 1028 aprint_error_dev(sc->sc_dev, 1029 "spbufarray init fail, err %d\n", err); 1030 return ENOMEM; 1031 } 1032 1033 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 1034 sc->sc_maxspbuf, KM_SLEEP); 1035 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 1036 for (i = 0; i < sc->sc_maxspbuf; i++) { 1037 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 1038 /* allocate contexts */ 1039 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 1040 sc->sc_pgsz, dma); 1041 if (err) { 1042 aprint_error_dev(sc->sc_dev, 1043 "spbufarray_dma init fail, err %d\n", err); 1044 rv = ENOMEM; 1045 goto bad1; 1046 } 1047 spbufarray[i] = htole64(DMAADDR(dma, 0)); 1048 usb_syncmem(dma, 0, sc->sc_pgsz, 1049 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1050 } 1051 1052 usb_syncmem(&sc->sc_spbufarray_dma, 0, 1053 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 1054 } 1055 1056 config = xhci_op_read_4(sc, XHCI_CONFIG); 1057 config &= ~0xFF; 1058 config |= sc->sc_maxslots & 0xFF; 1059 xhci_op_write_4(sc, XHCI_CONFIG, config); 1060 1061 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 1062 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 1063 if (err) { 1064 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 1065 err); 1066 rv = ENOMEM; 1067 goto bad1; 1068 } 1069 1070 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 1071 XHCI_EVENT_RING_SEGMENTS_ALIGN); 1072 if (err) { 1073 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 1074 err); 1075 rv = ENOMEM; 1076 goto bad2; 1077 } 1078 1079 usb_dma_t *dma; 1080 size_t size; 1081 size_t align; 1082 1083 dma = &sc->sc_eventst_dma; 1084 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 1085 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 1086 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 1087 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 1088 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1089 if (err) { 1090 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 1091 err); 1092 rv = ENOMEM; 1093 goto bad3; 1094 } 1095 1096 memset(KERNADDR(dma, 0), 0, size); 1097 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1098 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 1099 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 1100 KERNADDR(&sc->sc_eventst_dma, 0), 1101 sc->sc_eventst_dma.udma_block->size); 1102 1103 dma = &sc->sc_dcbaa_dma; 1104 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 1105 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 1106 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 1107 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1108 if (err) { 1109 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1110 rv = ENOMEM; 1111 goto bad4; 1112 } 1113 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 1114 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1115 KERNADDR(&sc->sc_dcbaa_dma, 0), 1116 sc->sc_dcbaa_dma.udma_block->size); 1117 1118 memset(KERNADDR(dma, 0), 0, size); 1119 if (sc->sc_maxspbuf != 0) { 1120 /* 1121 * DCBA entry 0 hold the scratchbuf array pointer. 1122 */ 1123 *(uint64_t *)KERNADDR(dma, 0) = 1124 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1125 } 1126 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1127 1128 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1129 KM_SLEEP); 1130 if (sc->sc_slots == NULL) { 1131 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1132 rv = ENOMEM; 1133 goto bad; 1134 } 1135 1136 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1137 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1138 if (sc->sc_xferpool == NULL) { 1139 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1140 err); 1141 rv = ENOMEM; 1142 goto bad; 1143 } 1144 1145 cv_init(&sc->sc_command_cv, "xhcicmd"); 1146 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1147 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1148 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1149 1150 struct xhci_erste *erst; 1151 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1152 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1153 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1154 erst[0].erste_3 = htole32(0); 1155 usb_syncmem(&sc->sc_eventst_dma, 0, 1156 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1157 1158 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1159 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1160 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1161 XHCI_ERDP_LO_BUSY); 1162 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1163 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1164 sc->sc_cr.xr_cs); 1165 1166 #if 0 1167 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1168 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1169 #endif 1170 1171 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1172 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1173 /* Intel xhci needs interrupt rate moderated. */ 1174 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1175 else 1176 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1177 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 1178 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1179 1180 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 1181 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1182 xhci_op_read_4(sc, XHCI_USBCMD)); 1183 1184 return 0; 1185 1186 bad: 1187 if (sc->sc_xferpool) { 1188 pool_cache_destroy(sc->sc_xferpool); 1189 sc->sc_xferpool = NULL; 1190 } 1191 1192 if (sc->sc_slots) { 1193 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1194 sc->sc_maxslots); 1195 sc->sc_slots = NULL; 1196 } 1197 1198 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1199 bad4: 1200 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1201 bad3: 1202 xhci_ring_free(sc, &sc->sc_er); 1203 bad2: 1204 xhci_ring_free(sc, &sc->sc_cr); 1205 i = sc->sc_maxspbuf; 1206 bad1: 1207 for (int j = 0; j < i; j++) 1208 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1209 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1210 1211 return rv; 1212 } 1213 1214 int 1215 xhci_intr(void *v) 1216 { 1217 struct xhci_softc * const sc = v; 1218 int ret = 0; 1219 1220 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1221 1222 if (sc == NULL) 1223 return 0; 1224 1225 mutex_spin_enter(&sc->sc_intr_lock); 1226 1227 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1228 goto done; 1229 1230 /* If we get an interrupt while polling, then just ignore it. */ 1231 if (sc->sc_bus.ub_usepolling) { 1232 #ifdef DIAGNOSTIC 1233 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1234 #endif 1235 goto done; 1236 } 1237 1238 ret = xhci_intr1(sc); 1239 done: 1240 mutex_spin_exit(&sc->sc_intr_lock); 1241 return ret; 1242 } 1243 1244 int 1245 xhci_intr1(struct xhci_softc * const sc) 1246 { 1247 uint32_t usbsts; 1248 uint32_t iman; 1249 1250 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1251 1252 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1253 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1254 #if 0 1255 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1256 return 0; 1257 } 1258 #endif 1259 xhci_op_write_4(sc, XHCI_USBSTS, 1260 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1261 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1262 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1263 1264 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1265 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1266 iman |= XHCI_IMAN_INTR_PEND; 1267 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1268 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1269 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1270 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1271 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1272 1273 usb_schedsoftintr(&sc->sc_bus); 1274 1275 return 1; 1276 } 1277 1278 /* 1279 * 3 port speed types used in USB stack 1280 * 1281 * usbdi speed 1282 * definition: USB_SPEED_* in usb.h 1283 * They are used in struct usbd_device in USB stack. 1284 * ioctl interface uses these values too. 1285 * port_status speed 1286 * definition: UPS_*_SPEED in usb.h 1287 * They are used in usb_port_status_t and valid only for USB 2.0. 1288 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1289 * of usb_port_status_ext_t indicates port speed. 1290 * Note that some 3.0 values overlap with 2.0 values. 1291 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1292 * means UPS_LOW_SPEED in HS.) 1293 * port status returned from hub also uses these values. 1294 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1295 * or more. 1296 * xspeed: 1297 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1298 * They are used in only slot context and PORTSC reg of xhci. 1299 * The difference between usbdi speed and xspeed is 1300 * that FS and LS values are swapped. 1301 */ 1302 1303 /* convert usbdi speed to xspeed */ 1304 static int 1305 xhci_speed2xspeed(int speed) 1306 { 1307 switch (speed) { 1308 case USB_SPEED_LOW: return 2; 1309 case USB_SPEED_FULL: return 1; 1310 default: return speed; 1311 } 1312 } 1313 1314 #if 0 1315 /* convert xspeed to usbdi speed */ 1316 static int 1317 xhci_xspeed2speed(int xspeed) 1318 { 1319 switch (xspeed) { 1320 case 1: return USB_SPEED_FULL; 1321 case 2: return USB_SPEED_LOW; 1322 default: return xspeed; 1323 } 1324 } 1325 #endif 1326 1327 /* convert xspeed to port status speed */ 1328 static int 1329 xhci_xspeed2psspeed(int xspeed) 1330 { 1331 switch (xspeed) { 1332 case 0: return 0; 1333 case 1: return UPS_FULL_SPEED; 1334 case 2: return UPS_LOW_SPEED; 1335 case 3: return UPS_HIGH_SPEED; 1336 default: return UPS_OTHER_SPEED; 1337 } 1338 } 1339 1340 /* 1341 * Construct input contexts and issue TRB to open pipe. 1342 */ 1343 static usbd_status 1344 xhci_configure_endpoint(struct usbd_pipe *pipe) 1345 { 1346 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1347 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1348 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1349 struct xhci_trb trb; 1350 usbd_status err; 1351 1352 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1353 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1354 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1355 pipe->up_endpoint->ue_edesc->bmAttributes); 1356 1357 /* XXX ensure input context is available? */ 1358 1359 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1360 1361 /* set up context */ 1362 xhci_setup_ctx(pipe); 1363 1364 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1365 sc->sc_ctxsz * 1); 1366 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1367 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1368 1369 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1370 trb.trb_2 = 0; 1371 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1372 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1373 1374 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1375 1376 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1377 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1378 sc->sc_ctxsz * 1); 1379 1380 return err; 1381 } 1382 1383 #if 0 1384 static usbd_status 1385 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1386 { 1387 #ifdef USB_DEBUG 1388 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1389 #endif 1390 1391 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1392 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1393 1394 return USBD_NORMAL_COMPLETION; 1395 } 1396 #endif 1397 1398 /* 4.6.8, 6.4.3.7 */ 1399 static usbd_status 1400 xhci_reset_endpoint_locked(struct usbd_pipe *pipe) 1401 { 1402 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1403 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1404 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1405 struct xhci_trb trb; 1406 usbd_status err; 1407 1408 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1409 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1410 1411 KASSERT(mutex_owned(&sc->sc_lock)); 1412 1413 trb.trb_0 = 0; 1414 trb.trb_2 = 0; 1415 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1416 XHCI_TRB_3_EP_SET(dci) | 1417 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1418 1419 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1420 1421 return err; 1422 } 1423 1424 static usbd_status 1425 xhci_reset_endpoint(struct usbd_pipe *pipe) 1426 { 1427 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1428 1429 mutex_enter(&sc->sc_lock); 1430 usbd_status ret = xhci_reset_endpoint_locked(pipe); 1431 mutex_exit(&sc->sc_lock); 1432 1433 return ret; 1434 } 1435 1436 /* 1437 * 4.6.9, 6.4.3.8 1438 * Stop execution of TDs on xfer ring. 1439 * Should be called with sc_lock held. 1440 */ 1441 static usbd_status 1442 xhci_stop_endpoint(struct usbd_pipe *pipe) 1443 { 1444 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1445 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1446 struct xhci_trb trb; 1447 usbd_status err; 1448 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1449 1450 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1451 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1452 1453 KASSERT(mutex_owned(&sc->sc_lock)); 1454 1455 trb.trb_0 = 0; 1456 trb.trb_2 = 0; 1457 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1458 XHCI_TRB_3_EP_SET(dci) | 1459 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1460 1461 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1462 1463 return err; 1464 } 1465 1466 /* 1467 * Set TR Dequeue Pointer. 1468 * xHCI 1.1 4.6.10 6.4.3.9 1469 * Purge all of the TRBs on ring and reinitialize ring. 1470 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1471 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1472 * error will be generated. 1473 */ 1474 static usbd_status 1475 xhci_set_dequeue_locked(struct usbd_pipe *pipe) 1476 { 1477 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1478 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1479 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1480 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1481 struct xhci_trb trb; 1482 usbd_status err; 1483 1484 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1485 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1486 1487 KASSERT(mutex_owned(&sc->sc_lock)); 1488 1489 xhci_host_dequeue(xr); 1490 1491 /* set DCS */ 1492 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1493 trb.trb_2 = 0; 1494 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1495 XHCI_TRB_3_EP_SET(dci) | 1496 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1497 1498 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1499 1500 return err; 1501 } 1502 1503 static usbd_status 1504 xhci_set_dequeue(struct usbd_pipe *pipe) 1505 { 1506 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1507 1508 mutex_enter(&sc->sc_lock); 1509 usbd_status ret = xhci_set_dequeue_locked(pipe); 1510 mutex_exit(&sc->sc_lock); 1511 1512 return ret; 1513 } 1514 1515 /* 1516 * Open new pipe: called from usbd_setup_pipe_flags. 1517 * Fills methods of pipe. 1518 * If pipe is not for ep0, calls configure_endpoint. 1519 */ 1520 static usbd_status 1521 xhci_open(struct usbd_pipe *pipe) 1522 { 1523 struct usbd_device * const dev = pipe->up_dev; 1524 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1525 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1526 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1527 1528 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1529 DPRINTFN(1, "addr %d depth %d port %d speed %d", dev->ud_addr, 1530 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1531 DPRINTFN(1, " dci %u type 0x%02x epaddr 0x%02x attr 0x%02x", 1532 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1533 ed->bmAttributes); 1534 DPRINTFN(1, " mps %u ival %u", UGETW(ed->wMaxPacketSize), ed->bInterval, 1535 0, 0); 1536 1537 if (sc->sc_dying) 1538 return USBD_IOERROR; 1539 1540 /* Root Hub */ 1541 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1542 switch (ed->bEndpointAddress) { 1543 case USB_CONTROL_ENDPOINT: 1544 pipe->up_methods = &roothub_ctrl_methods; 1545 break; 1546 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1547 pipe->up_methods = &xhci_root_intr_methods; 1548 break; 1549 default: 1550 pipe->up_methods = NULL; 1551 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1552 ed->bEndpointAddress, 0, 0, 0); 1553 return USBD_INVAL; 1554 } 1555 return USBD_NORMAL_COMPLETION; 1556 } 1557 1558 switch (xfertype) { 1559 case UE_CONTROL: 1560 pipe->up_methods = &xhci_device_ctrl_methods; 1561 break; 1562 case UE_ISOCHRONOUS: 1563 pipe->up_methods = &xhci_device_isoc_methods; 1564 return USBD_INVAL; 1565 break; 1566 case UE_BULK: 1567 pipe->up_methods = &xhci_device_bulk_methods; 1568 break; 1569 case UE_INTERRUPT: 1570 pipe->up_methods = &xhci_device_intr_methods; 1571 break; 1572 default: 1573 return USBD_IOERROR; 1574 break; 1575 } 1576 1577 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1578 return xhci_configure_endpoint(pipe); 1579 1580 return USBD_NORMAL_COMPLETION; 1581 } 1582 1583 /* 1584 * Closes pipe, called from usbd_kill_pipe via close methods. 1585 * If the endpoint to be closed is ep0, disable_slot. 1586 * Should be called with sc_lock held. 1587 */ 1588 static void 1589 xhci_close_pipe(struct usbd_pipe *pipe) 1590 { 1591 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1592 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1593 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1594 const u_int dci = xhci_ep_get_dci(ed); 1595 struct xhci_trb trb; 1596 uint32_t *cp; 1597 1598 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1599 1600 if (sc->sc_dying) 1601 return; 1602 1603 /* xs is uninitialized before xhci_init_slot */ 1604 if (xs == NULL || xs->xs_idx == 0) 1605 return; 1606 1607 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1608 1609 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1610 KASSERT(mutex_owned(&sc->sc_lock)); 1611 1612 if (pipe->up_dev->ud_depth == 0) 1613 return; 1614 1615 if (dci == XHCI_DCI_EP_CONTROL) { 1616 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1617 xhci_disable_slot(sc, xs->xs_idx); 1618 return; 1619 } 1620 1621 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED) 1622 (void)xhci_stop_endpoint(pipe); 1623 1624 /* 1625 * set appropriate bit to be dropped. 1626 * don't set DC bit to 1, otherwise all endpoints 1627 * would be deconfigured. 1628 */ 1629 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1630 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1631 cp[1] = htole32(0); 1632 1633 /* XXX should be most significant one, not dci? */ 1634 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1635 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1636 1637 /* configure ep context performs an implicit dequeue */ 1638 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 1639 1640 /* sync input contexts before they are read from memory */ 1641 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1642 1643 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1644 trb.trb_2 = 0; 1645 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1646 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1647 1648 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1649 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1650 } 1651 1652 /* 1653 * Abort transfer. 1654 * Should be called with sc_lock held. 1655 */ 1656 static void 1657 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1658 { 1659 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1660 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1661 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1662 1663 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1664 DPRINTFN(4, "xfer %p pipe %p status %d", 1665 xfer, xfer->ux_pipe, status, 0); 1666 1667 KASSERT(mutex_owned(&sc->sc_lock)); 1668 1669 if (sc->sc_dying) { 1670 /* If we're dying, just do the software part. */ 1671 DPRINTFN(4, "xfer %p dying %u", xfer, xfer->ux_status, 0, 0); 1672 xfer->ux_status = status; 1673 callout_stop(&xfer->ux_callout); 1674 usb_transfer_complete(xfer); 1675 return; 1676 } 1677 1678 /* 1679 * If an abort is already in progress then just wait for it to 1680 * complete and return. 1681 */ 1682 if (xfer->ux_hcflags & UXFER_ABORTING) { 1683 DPRINTFN(4, "already aborting", 0, 0, 0, 0); 1684 #ifdef DIAGNOSTIC 1685 if (status == USBD_TIMEOUT) 1686 DPRINTFN(4, "TIMEOUT while aborting", 0, 0, 0, 0); 1687 #endif 1688 /* Override the status which might be USBD_TIMEOUT. */ 1689 xfer->ux_status = status; 1690 DPRINTFN(4, "xfer %p waiting for abort to finish", xfer, 0, 0, 1691 0); 1692 xfer->ux_hcflags |= UXFER_ABORTWAIT; 1693 while (xfer->ux_hcflags & UXFER_ABORTING) 1694 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 1695 return; 1696 } 1697 xfer->ux_hcflags |= UXFER_ABORTING; 1698 1699 /* 1700 * Step 1: Stop xfer timeout timer. 1701 */ 1702 xfer->ux_status = status; 1703 callout_stop(&xfer->ux_callout); 1704 1705 /* 1706 * Step 2: Stop execution of TD on the ring. 1707 */ 1708 switch (xhci_get_epstate(sc, xs, dci)) { 1709 case XHCI_EPSTATE_HALTED: 1710 (void)xhci_reset_endpoint_locked(xfer->ux_pipe); 1711 break; 1712 case XHCI_EPSTATE_STOPPED: 1713 break; 1714 default: 1715 (void)xhci_stop_endpoint(xfer->ux_pipe); 1716 break; 1717 } 1718 #ifdef DIAGNOSTIC 1719 uint32_t epst = xhci_get_epstate(sc, xs, dci); 1720 if (epst != XHCI_EPSTATE_STOPPED) 1721 DPRINTFN(4, "dci %u not stopped %u", dci, epst, 0, 0); 1722 #endif 1723 1724 /* 1725 * Step 3: Remove any vestiges of the xfer from the ring. 1726 */ 1727 xhci_set_dequeue_locked(xfer->ux_pipe); 1728 1729 /* 1730 * Step 4: Notify completion to waiting xfers. 1731 */ 1732 int wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 1733 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 1734 usb_transfer_complete(xfer); 1735 if (wake) { 1736 cv_broadcast(&xfer->ux_hccv); 1737 } 1738 DPRINTFN(14, "end", 0, 0, 0, 0); 1739 1740 KASSERT(mutex_owned(&sc->sc_lock)); 1741 } 1742 1743 static void 1744 xhci_host_dequeue(struct xhci_ring * const xr) 1745 { 1746 /* When dequeueing the controller, update our struct copy too */ 1747 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1748 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1749 BUS_DMASYNC_PREWRITE); 1750 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1751 1752 xr->xr_ep = 0; 1753 xr->xr_cs = 1; 1754 } 1755 1756 /* 1757 * Recover STALLed endpoint. 1758 * xHCI 1.1 sect 4.10.2.1 1759 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1760 * all transfers on transfer ring. 1761 * These are done in thread context asynchronously. 1762 */ 1763 static void 1764 xhci_clear_endpoint_stall_async_task(void *cookie) 1765 { 1766 struct usbd_xfer * const xfer = cookie; 1767 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1768 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1769 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1770 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1771 1772 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1773 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1774 1775 xhci_reset_endpoint(xfer->ux_pipe); 1776 xhci_set_dequeue(xfer->ux_pipe); 1777 1778 mutex_enter(&sc->sc_lock); 1779 tr->is_halted = false; 1780 usb_transfer_complete(xfer); 1781 mutex_exit(&sc->sc_lock); 1782 DPRINTFN(4, "ends", 0, 0, 0, 0); 1783 } 1784 1785 static usbd_status 1786 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1787 { 1788 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1789 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1790 1791 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1792 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1793 1794 if (sc->sc_dying) { 1795 return USBD_IOERROR; 1796 } 1797 1798 usb_init_task(&xp->xp_async_task, 1799 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1800 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1801 DPRINTFN(4, "ends", 0, 0, 0, 0); 1802 1803 return USBD_NORMAL_COMPLETION; 1804 } 1805 1806 /* Process roothub port status/change events and notify to uhub_intr. */ 1807 static void 1808 xhci_rhpsc(struct xhci_softc * const sc, u_int ctlrport) 1809 { 1810 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1811 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1812 ctlrport, 0, 0); 1813 1814 if (ctlrport > sc->sc_maxports) 1815 return; 1816 1817 const size_t bn = xhci_ctlrport2bus(sc, ctlrport); 1818 const size_t rhp = xhci_ctlrport2rhport(sc, ctlrport); 1819 struct usbd_xfer * const xfer = sc->sc_intrxfer[bn]; 1820 1821 DPRINTFN(4, "xhci%d: bus %d bp %u xfer %p status change", 1822 device_unit(sc->sc_dev), bn, rhp, xfer); 1823 1824 if (xfer == NULL) 1825 return; 1826 1827 uint8_t *p = xfer->ux_buf; 1828 memset(p, 0, xfer->ux_length); 1829 p[rhp / NBBY] |= 1 << (rhp % NBBY); 1830 xfer->ux_actlen = xfer->ux_length; 1831 xfer->ux_status = USBD_NORMAL_COMPLETION; 1832 usb_transfer_complete(xfer); 1833 } 1834 1835 /* Process Transfer Events */ 1836 static void 1837 xhci_event_transfer(struct xhci_softc * const sc, 1838 const struct xhci_trb * const trb) 1839 { 1840 uint64_t trb_0; 1841 uint32_t trb_2, trb_3; 1842 uint8_t trbcode; 1843 u_int slot, dci; 1844 struct xhci_slot *xs; 1845 struct xhci_ring *xr; 1846 struct xhci_xfer *xx; 1847 struct usbd_xfer *xfer; 1848 usbd_status err; 1849 1850 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1851 1852 trb_0 = le64toh(trb->trb_0); 1853 trb_2 = le32toh(trb->trb_2); 1854 trb_3 = le32toh(trb->trb_3); 1855 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1856 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1857 dci = XHCI_TRB_3_EP_GET(trb_3); 1858 xs = &sc->sc_slots[slot]; 1859 xr = &xs->xs_ep[dci].xe_tr; 1860 1861 /* sanity check */ 1862 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1863 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1864 1865 int idx = 0; 1866 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1867 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1868 DPRINTFN(0, "invalid trb_0 0x%"PRIx64, trb_0, 0, 0, 0); 1869 return; 1870 } 1871 xx = xr->xr_cookies[idx]; 1872 1873 /* clear cookie of consumed TRB */ 1874 xr->xr_cookies[idx] = NULL; 1875 1876 /* 1877 * xx is NULL if pipe is opened but xfer is not started. 1878 * It happens when stopping idle pipe. 1879 */ 1880 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1881 DPRINTFN(1, "Ignore #%u: cookie %p cc %u dci %u", 1882 idx, xx, trbcode, dci); 1883 DPRINTFN(1, " orig TRB %"PRIx64" type %u", trb_0, 1884 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1885 0, 0); 1886 return; 1887 } 1888 } else { 1889 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1890 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1891 } 1892 /* XXX this may not happen */ 1893 if (xx == NULL) { 1894 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1895 return; 1896 } 1897 xfer = &xx->xx_xfer; 1898 /* XXX this may happen when detaching */ 1899 if (xfer == NULL) { 1900 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1901 xx, trb_0, 0, 0); 1902 return; 1903 } 1904 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1905 /* XXX I dunno why this happens */ 1906 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1907 1908 if (!xfer->ux_pipe->up_repeat && 1909 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1910 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1911 return; 1912 } 1913 1914 /* 4.11.5.2 Event Data TRB */ 1915 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1916 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1917 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1918 if ((trb_0 & 0x3) == 0x3) { 1919 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1920 } 1921 } 1922 1923 switch (trbcode) { 1924 case XHCI_TRB_ERROR_SHORT_PKT: 1925 case XHCI_TRB_ERROR_SUCCESS: 1926 /* 1927 * A ctrl transfer can generate two events if it has a Data 1928 * stage. A short data stage can be OK and should not 1929 * complete the transfer as the status stage needs to be 1930 * performed. 1931 * 1932 * Note: Data and Status stage events point at same xfer. 1933 * ux_actlen and ux_dmabuf will be passed to 1934 * usb_transfer_complete after the Status stage event. 1935 * 1936 * It can be distingished which stage generates the event: 1937 * + by checking least 3 bits of trb_0 if ED==1. 1938 * (see xhci_device_ctrl_start). 1939 * + by checking the type of original TRB if ED==0. 1940 * 1941 * In addition, intr, bulk, and isoc transfer currently 1942 * consists of single TD, so the "skip" is not needed. 1943 * ctrl xfer uses EVENT_DATA, and others do not. 1944 * Thus driver can switch the flow by checking ED bit. 1945 */ 1946 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1947 if (xfer->ux_actlen == 0) 1948 xfer->ux_actlen = xfer->ux_length - 1949 XHCI_TRB_2_REM_GET(trb_2); 1950 if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)) 1951 == XHCI_TRB_TYPE_DATA_STAGE) { 1952 return; 1953 } 1954 } else if ((trb_0 & 0x3) == 0x3) { 1955 return; 1956 } 1957 err = USBD_NORMAL_COMPLETION; 1958 break; 1959 case XHCI_TRB_ERROR_STOPPED: 1960 case XHCI_TRB_ERROR_LENGTH: 1961 case XHCI_TRB_ERROR_STOPPED_SHORT: 1962 /* 1963 * don't complete the transfer being aborted 1964 * as abort_xfer does instead. 1965 */ 1966 if (xfer->ux_hcflags & UXFER_ABORTING) { 1967 DPRINTFN(14, "ignore aborting xfer %p", xfer, 0, 0, 0); 1968 return; 1969 } 1970 err = USBD_CANCELLED; 1971 break; 1972 case XHCI_TRB_ERROR_STALL: 1973 case XHCI_TRB_ERROR_BABBLE: 1974 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1975 xr->is_halted = true; 1976 err = USBD_STALLED; 1977 /* 1978 * Stalled endpoints can be recoverd by issuing 1979 * command TRB TYPE_RESET_EP on xHCI instead of 1980 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1981 * on the endpoint. However, this function may be 1982 * called from softint context (e.g. from umass), 1983 * in that case driver gets KASSERT in cv_timedwait 1984 * in xhci_do_command. 1985 * To avoid this, this runs reset_endpoint and 1986 * usb_transfer_complete in usb task thread 1987 * asynchronously (and then umass issues clear 1988 * UF_ENDPOINT_HALT). 1989 */ 1990 xfer->ux_status = err; 1991 callout_stop(&xfer->ux_callout); 1992 xhci_clear_endpoint_stall_async(xfer); 1993 return; 1994 default: 1995 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1996 err = USBD_IOERROR; 1997 break; 1998 } 1999 xfer->ux_status = err; 2000 2001 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 2002 if ((trb_0 & 0x3) == 0x0) { 2003 callout_stop(&xfer->ux_callout); 2004 usb_transfer_complete(xfer); 2005 } 2006 } else { 2007 callout_stop(&xfer->ux_callout); 2008 usb_transfer_complete(xfer); 2009 } 2010 } 2011 2012 /* Process Command complete events */ 2013 static void 2014 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 2015 { 2016 uint64_t trb_0; 2017 uint32_t trb_2, trb_3; 2018 2019 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2020 2021 KASSERT(mutex_owned(&sc->sc_lock)); 2022 2023 trb_0 = le64toh(trb->trb_0); 2024 trb_2 = le32toh(trb->trb_2); 2025 trb_3 = le32toh(trb->trb_3); 2026 2027 if (trb_0 == sc->sc_command_addr) { 2028 sc->sc_resultpending = false; 2029 2030 sc->sc_result_trb.trb_0 = trb_0; 2031 sc->sc_result_trb.trb_2 = trb_2; 2032 sc->sc_result_trb.trb_3 = trb_3; 2033 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2034 XHCI_TRB_ERROR_SUCCESS) { 2035 DPRINTFN(1, "command completion " 2036 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 2037 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 2038 } 2039 cv_signal(&sc->sc_command_cv); 2040 } else { 2041 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 2042 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 2043 trb_2, trb_3); 2044 } 2045 } 2046 2047 /* 2048 * Process events. 2049 * called from xhci_softintr 2050 */ 2051 static void 2052 xhci_handle_event(struct xhci_softc * const sc, 2053 const struct xhci_trb * const trb) 2054 { 2055 uint64_t trb_0; 2056 uint32_t trb_2, trb_3; 2057 2058 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2059 2060 trb_0 = le64toh(trb->trb_0); 2061 trb_2 = le32toh(trb->trb_2); 2062 trb_3 = le32toh(trb->trb_3); 2063 2064 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2065 trb, trb_0, trb_2, trb_3); 2066 2067 /* 2068 * 4.11.3.1, 6.4.2.1 2069 * TRB Pointer is invalid for these completion codes. 2070 */ 2071 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2072 case XHCI_TRB_ERROR_RING_UNDERRUN: 2073 case XHCI_TRB_ERROR_RING_OVERRUN: 2074 case XHCI_TRB_ERROR_VF_RING_FULL: 2075 return; 2076 default: 2077 if (trb_0 == 0) { 2078 return; 2079 } 2080 break; 2081 } 2082 2083 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2084 case XHCI_TRB_EVENT_TRANSFER: 2085 xhci_event_transfer(sc, trb); 2086 break; 2087 case XHCI_TRB_EVENT_CMD_COMPLETE: 2088 xhci_event_cmd(sc, trb); 2089 break; 2090 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2091 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2092 break; 2093 default: 2094 break; 2095 } 2096 } 2097 2098 static void 2099 xhci_softintr(void *v) 2100 { 2101 struct usbd_bus * const bus = v; 2102 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2103 struct xhci_ring * const er = &sc->sc_er; 2104 struct xhci_trb *trb; 2105 int i, j, k; 2106 2107 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2108 2109 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2110 2111 i = er->xr_ep; 2112 j = er->xr_cs; 2113 2114 DPRINTFN(16, "er: xr_ep %d xr_cs %d", i, j, 0, 0); 2115 2116 while (1) { 2117 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2118 BUS_DMASYNC_POSTREAD); 2119 trb = &er->xr_trb[i]; 2120 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2121 2122 if (j != k) 2123 break; 2124 2125 xhci_handle_event(sc, trb); 2126 2127 i++; 2128 if (i == er->xr_ntrb) { 2129 i = 0; 2130 j ^= 1; 2131 } 2132 } 2133 2134 er->xr_ep = i; 2135 er->xr_cs = j; 2136 2137 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2138 XHCI_ERDP_LO_BUSY); 2139 2140 DPRINTFN(16, "ends", 0, 0, 0, 0); 2141 2142 return; 2143 } 2144 2145 static void 2146 xhci_poll(struct usbd_bus *bus) 2147 { 2148 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2149 2150 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2151 2152 mutex_spin_enter(&sc->sc_intr_lock); 2153 xhci_intr1(sc); 2154 mutex_spin_exit(&sc->sc_intr_lock); 2155 2156 return; 2157 } 2158 2159 static struct usbd_xfer * 2160 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2161 { 2162 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2163 struct usbd_xfer *xfer; 2164 2165 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2166 2167 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 2168 if (xfer != NULL) { 2169 memset(xfer, 0, sizeof(struct xhci_xfer)); 2170 #ifdef DIAGNOSTIC 2171 xfer->ux_state = XFER_BUSY; 2172 #endif 2173 } 2174 2175 return xfer; 2176 } 2177 2178 static void 2179 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2180 { 2181 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2182 2183 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2184 2185 #ifdef DIAGNOSTIC 2186 if (xfer->ux_state != XFER_BUSY) { 2187 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 2188 xfer, xfer->ux_state, 0, 0); 2189 } 2190 xfer->ux_state = XFER_FREE; 2191 #endif 2192 pool_cache_put(sc->sc_xferpool, xfer); 2193 } 2194 2195 static void 2196 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2197 { 2198 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2199 2200 *lock = &sc->sc_lock; 2201 } 2202 2203 extern uint32_t usb_cookie_no; 2204 2205 /* 2206 * xHCI 4.3 2207 * Called when uhub_explore finds a new device (via usbd_new_device). 2208 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2209 * This function does: 2210 * Allocate and construct dev structure of default endpoint (ep0). 2211 * Allocate and open pipe of ep0. 2212 * Enable slot and initialize slot context. 2213 * Set Address. 2214 * Read initial device descriptor. 2215 * Determine initial MaxPacketSize (mps) by speed. 2216 * Read full device descriptor. 2217 * Register this device. 2218 * Finally state of device transitions ADDRESSED. 2219 */ 2220 static usbd_status 2221 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2222 int speed, int port, struct usbd_port *up) 2223 { 2224 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2225 struct usbd_device *dev; 2226 usbd_status err; 2227 usb_device_descriptor_t *dd; 2228 struct xhci_slot *xs; 2229 uint32_t *cp; 2230 2231 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2232 DPRINTFN(4, "port %u depth %u speed %u up %p", port, depth, speed, up); 2233 2234 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2235 if (dev == NULL) 2236 return USBD_NOMEM; 2237 2238 dev->ud_bus = bus; 2239 dev->ud_quirks = &usbd_no_quirk; 2240 dev->ud_addr = 0; 2241 dev->ud_ddesc.bMaxPacketSize = 0; 2242 dev->ud_depth = depth; 2243 dev->ud_powersrc = up; 2244 dev->ud_myhub = up->up_parent; 2245 dev->ud_speed = speed; 2246 dev->ud_langid = USBD_NOLANG; 2247 dev->ud_cookie.cookie = ++usb_cookie_no; 2248 2249 /* Set up default endpoint handle. */ 2250 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2251 /* doesn't matter, just don't let it uninitialized */ 2252 dev->ud_ep0.ue_toggle = 0; 2253 2254 /* Set up default endpoint descriptor. */ 2255 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2256 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2257 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2258 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2259 dev->ud_ep0desc.bInterval = 0; 2260 2261 /* 4.3, 4.8.2.1 */ 2262 switch (speed) { 2263 case USB_SPEED_SUPER: 2264 case USB_SPEED_SUPER_PLUS: 2265 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2266 break; 2267 case USB_SPEED_FULL: 2268 /* XXX using 64 as initial mps of ep0 in FS */ 2269 case USB_SPEED_HIGH: 2270 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2271 break; 2272 case USB_SPEED_LOW: 2273 default: 2274 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2275 break; 2276 } 2277 2278 up->up_dev = dev; 2279 2280 /* Establish the default pipe. */ 2281 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2282 &dev->ud_pipe0); 2283 if (err) { 2284 goto bad; 2285 } 2286 2287 dd = &dev->ud_ddesc; 2288 2289 if (depth == 0 && port == 0) { 2290 KASSERT(bus->ub_devices[USB_ROOTHUB_INDEX] == NULL); 2291 bus->ub_devices[USB_ROOTHUB_INDEX] = dev; 2292 err = usbd_get_initial_ddesc(dev, dd); 2293 if (err) { 2294 DPRINTFN(1, "get_initial_ddesc %u", err, 0, 0, 0); 2295 goto bad; 2296 } 2297 2298 err = usbd_reload_device_desc(dev); 2299 if (err) { 2300 DPRINTFN(1, "reload desc %u", err, 0, 0, 0); 2301 goto bad; 2302 } 2303 } else { 2304 uint8_t slot = 0; 2305 2306 /* 4.3.2 */ 2307 err = xhci_enable_slot(sc, &slot); 2308 if (err) { 2309 DPRINTFN(1, "enable slot %u", err, 0, 0, 0); 2310 goto bad; 2311 } 2312 2313 xs = &sc->sc_slots[slot]; 2314 dev->ud_hcpriv = xs; 2315 2316 /* 4.3.3 initialize slot structure */ 2317 err = xhci_init_slot(dev, slot); 2318 if (err) { 2319 DPRINTFN(1, "init slot %u", err, 0, 0, 0); 2320 dev->ud_hcpriv = NULL; 2321 /* 2322 * We have to disable_slot here because 2323 * xs->xs_idx == 0 when xhci_init_slot fails, 2324 * in that case usbd_remove_dev won't work. 2325 */ 2326 mutex_enter(&sc->sc_lock); 2327 xhci_disable_slot(sc, slot); 2328 mutex_exit(&sc->sc_lock); 2329 goto bad; 2330 } 2331 2332 /* 4.3.4 Address Assignment */ 2333 err = xhci_set_address(dev, slot, false); 2334 if (err) { 2335 DPRINTFN(1, "set address w/o bsr %u", err, 0, 0, 0); 2336 goto bad; 2337 } 2338 2339 /* Allow device time to set new address */ 2340 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2341 2342 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2343 //hexdump("slot context", cp, sc->sc_ctxsz); 2344 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3])); 2345 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2346 /* 2347 * XXX ensure we know when the hardware does something 2348 * we can't yet cope with 2349 */ 2350 KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr); 2351 dev->ud_addr = addr; 2352 2353 KASSERTMSG(bus->ub_devices[usb_addr2dindex(dev->ud_addr)] == NULL, 2354 "addr %d already allocated", dev->ud_addr); 2355 /* 2356 * The root hub is given its own slot 2357 */ 2358 bus->ub_devices[usb_addr2dindex(dev->ud_addr)] = dev; 2359 2360 err = usbd_get_initial_ddesc(dev, dd); 2361 if (err) { 2362 DPRINTFN(1, "get_initial_ddesc %u", err, 0, 0, 0); 2363 goto bad; 2364 } 2365 2366 /* 4.8.2.1 */ 2367 if (USB_IS_SS(speed)) { 2368 if (dd->bMaxPacketSize != 9) { 2369 printf("%s: invalid mps 2^%u for SS ep0," 2370 " using 512\n", 2371 device_xname(sc->sc_dev), 2372 dd->bMaxPacketSize); 2373 dd->bMaxPacketSize = 9; 2374 } 2375 USETW(dev->ud_ep0desc.wMaxPacketSize, 2376 (1 << dd->bMaxPacketSize)); 2377 } else 2378 USETW(dev->ud_ep0desc.wMaxPacketSize, 2379 dd->bMaxPacketSize); 2380 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2381 err = xhci_update_ep0_mps(sc, xs, 2382 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2383 if (err) { 2384 DPRINTFN(1, "update mps of ep0 %u", err, 0, 0, 0); 2385 goto bad; 2386 } 2387 2388 err = usbd_reload_device_desc(dev); 2389 if (err) { 2390 DPRINTFN(1, "reload desc %u", err, 0, 0, 0); 2391 goto bad; 2392 } 2393 } 2394 2395 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2396 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2397 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2398 dd->bDeviceClass, dd->bDeviceSubClass, 2399 dd->bDeviceProtocol, 0); 2400 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2401 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2402 dev->ud_speed); 2403 2404 usbd_get_device_strings(dev); 2405 2406 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2407 2408 if (depth == 0 && port == 0) { 2409 usbd_attach_roothub(parent, dev); 2410 DPRINTFN(1, "root hub %p", dev, 0, 0, 0); 2411 return USBD_NORMAL_COMPLETION; 2412 } 2413 2414 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2415 bad: 2416 if (err != USBD_NORMAL_COMPLETION) { 2417 usbd_remove_device(dev, up); 2418 } 2419 2420 return err; 2421 } 2422 2423 static usbd_status 2424 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2425 size_t ntrb, size_t align) 2426 { 2427 usbd_status err; 2428 size_t size = ntrb * XHCI_TRB_SIZE; 2429 2430 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2431 2432 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2433 if (err) 2434 return err; 2435 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2436 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2437 xr->xr_trb = xhci_ring_trbv(xr, 0); 2438 xr->xr_ntrb = ntrb; 2439 xr->is_halted = false; 2440 xhci_host_dequeue(xr); 2441 2442 return USBD_NORMAL_COMPLETION; 2443 } 2444 2445 static void 2446 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2447 { 2448 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2449 mutex_destroy(&xr->xr_lock); 2450 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2451 } 2452 2453 static void 2454 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2455 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2456 { 2457 size_t i; 2458 u_int ri; 2459 u_int cs; 2460 uint64_t parameter; 2461 uint32_t status; 2462 uint32_t control; 2463 2464 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2465 2466 KASSERTMSG(ntrbs <= XHCI_XFER_NTRB, "ntrbs %zu", ntrbs); 2467 for (i = 0; i < ntrbs; i++) { 2468 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2469 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2470 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2471 KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2472 XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3); 2473 } 2474 2475 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2476 2477 ri = xr->xr_ep; 2478 cs = xr->xr_cs; 2479 2480 /* 2481 * Although the xhci hardware can do scatter/gather dma from 2482 * arbitrary sized buffers, there is a non-obvious restriction 2483 * that a LINK trb is only allowed at the end of a burst of 2484 * transfers - which might be 16kB. 2485 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2486 * The simple solution is not to allow a LINK trb in the middle 2487 * of anything - as here. 2488 * XXX: (dsl) There are xhci controllers out there (eg some made by 2489 * ASMedia) that seem to lock up if they process a LINK trb but 2490 * cannot process the linked-to trb yet. 2491 * The code should write the 'cycle' bit on the link trb AFTER 2492 * adding the other trb. 2493 */ 2494 u_int firstep = xr->xr_ep; 2495 u_int firstcs = xr->xr_cs; 2496 2497 for (i = 0; i < ntrbs; ) { 2498 u_int oldri = ri; 2499 u_int oldcs = cs; 2500 2501 if (ri >= (xr->xr_ntrb - 1)) { 2502 /* Put Link TD at the end of ring */ 2503 parameter = xhci_ring_trbp(xr, 0); 2504 status = 0; 2505 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2506 XHCI_TRB_3_TC_BIT; 2507 xr->xr_cookies[ri] = NULL; 2508 xr->xr_ep = 0; 2509 xr->xr_cs ^= 1; 2510 ri = xr->xr_ep; 2511 cs = xr->xr_cs; 2512 } else { 2513 parameter = trbs[i].trb_0; 2514 status = trbs[i].trb_2; 2515 control = trbs[i].trb_3; 2516 2517 xr->xr_cookies[ri] = cookie; 2518 ri++; 2519 i++; 2520 } 2521 /* 2522 * If this is a first TRB, mark it invalid to prevent 2523 * xHC from running it immediately. 2524 */ 2525 if (oldri == firstep) { 2526 if (oldcs) { 2527 control &= ~XHCI_TRB_3_CYCLE_BIT; 2528 } else { 2529 control |= XHCI_TRB_3_CYCLE_BIT; 2530 } 2531 } else { 2532 if (oldcs) { 2533 control |= XHCI_TRB_3_CYCLE_BIT; 2534 } else { 2535 control &= ~XHCI_TRB_3_CYCLE_BIT; 2536 } 2537 } 2538 xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control); 2539 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri, 2540 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2541 } 2542 2543 /* Now invert cycle bit of first TRB */ 2544 if (firstcs) { 2545 xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 2546 } else { 2547 xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 2548 } 2549 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep, 2550 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2551 2552 xr->xr_ep = ri; 2553 xr->xr_cs = cs; 2554 2555 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2556 } 2557 2558 /* 2559 * Stop execution commands, purge all commands on command ring, and 2560 * rewind dequeue pointer. 2561 */ 2562 static void 2563 xhci_abort_command(struct xhci_softc *sc) 2564 { 2565 struct xhci_ring * const cr = &sc->sc_cr; 2566 uint64_t crcr; 2567 int i; 2568 2569 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2570 DPRINTFN(14, "command %#"PRIx64" timeout, aborting", 2571 sc->sc_command_addr, 0, 0, 0); 2572 2573 mutex_enter(&cr->xr_lock); 2574 2575 /* 4.6.1.2 Aborting a Command */ 2576 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2577 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2578 2579 for (i = 0; i < 500; i++) { 2580 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2581 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2582 break; 2583 usb_delay_ms(&sc->sc_bus, 1); 2584 } 2585 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2586 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2587 /* reset HC here? */ 2588 } 2589 2590 /* reset command ring dequeue pointer */ 2591 cr->xr_ep = 0; 2592 cr->xr_cs = 1; 2593 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2594 2595 mutex_exit(&cr->xr_lock); 2596 } 2597 2598 /* 2599 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2600 * Command completion is notified by cv_signal from xhci_event_cmd() 2601 * (called from xhci_softint), or timed-out. 2602 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2603 * then do_command examines it. 2604 */ 2605 static usbd_status 2606 xhci_do_command_locked(struct xhci_softc * const sc, 2607 struct xhci_trb * const trb, int timeout) 2608 { 2609 struct xhci_ring * const cr = &sc->sc_cr; 2610 usbd_status err; 2611 2612 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2613 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2614 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2615 2616 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2617 KASSERT(mutex_owned(&sc->sc_lock)); 2618 2619 while (sc->sc_command_addr != 0) 2620 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 2621 2622 /* 2623 * If enqueue pointer points at last of ring, it's Link TRB, 2624 * command TRB will be stored in 0th TRB. 2625 */ 2626 if (cr->xr_ep == cr->xr_ntrb - 1) 2627 sc->sc_command_addr = xhci_ring_trbp(cr, 0); 2628 else 2629 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2630 2631 sc->sc_resultpending = true; 2632 2633 mutex_enter(&cr->xr_lock); 2634 xhci_ring_put(sc, cr, NULL, trb, 1); 2635 mutex_exit(&cr->xr_lock); 2636 2637 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2638 2639 while (sc->sc_resultpending) { 2640 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2641 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2642 xhci_abort_command(sc); 2643 err = USBD_TIMEOUT; 2644 goto timedout; 2645 } 2646 } 2647 2648 trb->trb_0 = sc->sc_result_trb.trb_0; 2649 trb->trb_2 = sc->sc_result_trb.trb_2; 2650 trb->trb_3 = sc->sc_result_trb.trb_3; 2651 2652 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2653 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2654 2655 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2656 case XHCI_TRB_ERROR_SUCCESS: 2657 err = USBD_NORMAL_COMPLETION; 2658 break; 2659 default: 2660 case 192 ... 223: 2661 err = USBD_IOERROR; 2662 break; 2663 case 224 ... 255: 2664 err = USBD_NORMAL_COMPLETION; 2665 break; 2666 } 2667 2668 timedout: 2669 sc->sc_resultpending = false; 2670 sc->sc_command_addr = 0; 2671 cv_broadcast(&sc->sc_cmdbusy_cv); 2672 2673 return err; 2674 } 2675 2676 static usbd_status 2677 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2678 int timeout) 2679 { 2680 2681 mutex_enter(&sc->sc_lock); 2682 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2683 mutex_exit(&sc->sc_lock); 2684 2685 return ret; 2686 } 2687 2688 static usbd_status 2689 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2690 { 2691 struct xhci_trb trb; 2692 usbd_status err; 2693 2694 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2695 2696 trb.trb_0 = 0; 2697 trb.trb_2 = 0; 2698 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2699 2700 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2701 if (err != USBD_NORMAL_COMPLETION) { 2702 return err; 2703 } 2704 2705 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2706 2707 return err; 2708 } 2709 2710 /* 2711 * xHCI 4.6.4 2712 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2713 * All endpoints in the slot should be stopped. 2714 * Should be called with sc_lock held. 2715 */ 2716 static usbd_status 2717 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2718 { 2719 struct xhci_trb trb; 2720 struct xhci_slot *xs; 2721 usbd_status err; 2722 2723 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2724 2725 if (sc->sc_dying) 2726 return USBD_IOERROR; 2727 2728 trb.trb_0 = 0; 2729 trb.trb_2 = 0; 2730 trb.trb_3 = htole32( 2731 XHCI_TRB_3_SLOT_SET(slot) | 2732 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2733 2734 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2735 2736 if (!err) { 2737 xs = &sc->sc_slots[slot]; 2738 if (xs->xs_idx != 0) { 2739 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2740 xhci_set_dcba(sc, 0, slot); 2741 memset(xs, 0, sizeof(*xs)); 2742 } 2743 } 2744 2745 return err; 2746 } 2747 2748 /* 2749 * Set address of device and transition slot state from ENABLED to ADDRESSED 2750 * if Block Setaddress Request (BSR) is false. 2751 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2752 * see xHCI 1.1 4.5.3, 3.3.4 2753 * Should be called without sc_lock held. 2754 */ 2755 static usbd_status 2756 xhci_address_device(struct xhci_softc * const sc, 2757 uint64_t icp, uint8_t slot_id, bool bsr) 2758 { 2759 struct xhci_trb trb; 2760 usbd_status err; 2761 2762 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2763 2764 trb.trb_0 = icp; 2765 trb.trb_2 = 0; 2766 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2767 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2768 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2769 2770 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2771 2772 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2773 err = USBD_NO_ADDR; 2774 2775 return err; 2776 } 2777 2778 static usbd_status 2779 xhci_update_ep0_mps(struct xhci_softc * const sc, 2780 struct xhci_slot * const xs, u_int mps) 2781 { 2782 struct xhci_trb trb; 2783 usbd_status err; 2784 uint32_t * cp; 2785 2786 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2787 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2788 2789 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2790 cp[0] = htole32(0); 2791 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2792 2793 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2794 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2795 2796 /* sync input contexts before they are read from memory */ 2797 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2798 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2799 sc->sc_ctxsz * 4); 2800 2801 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2802 trb.trb_2 = 0; 2803 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2804 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2805 2806 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2807 return err; 2808 } 2809 2810 static void 2811 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2812 { 2813 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2814 2815 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2816 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2817 &dcbaa[si], dcba, si, 0); 2818 2819 dcbaa[si] = htole64(dcba); 2820 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2821 BUS_DMASYNC_PREWRITE); 2822 } 2823 2824 /* 2825 * Allocate device and input context DMA buffer, and 2826 * TRB DMA buffer for each endpoint. 2827 */ 2828 static usbd_status 2829 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2830 { 2831 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2832 struct xhci_slot *xs; 2833 usbd_status err; 2834 u_int dci; 2835 2836 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2837 DPRINTFN(4, "slot %u", slot, 0, 0, 0); 2838 2839 xs = &sc->sc_slots[slot]; 2840 2841 /* allocate contexts */ 2842 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2843 &xs->xs_dc_dma); 2844 if (err) 2845 return err; 2846 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2847 2848 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2849 &xs->xs_ic_dma); 2850 if (err) 2851 goto bad1; 2852 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2853 2854 for (dci = 0; dci < 32; dci++) { 2855 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2856 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2857 if (dci == XHCI_DCI_SLOT) 2858 continue; 2859 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2860 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2861 if (err) { 2862 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2863 goto bad2; 2864 } 2865 } 2866 2867 bad2: 2868 if (err == USBD_NORMAL_COMPLETION) { 2869 xs->xs_idx = slot; 2870 } else { 2871 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2872 } 2873 2874 return err; 2875 2876 bad1: 2877 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2878 xs->xs_idx = 0; 2879 return err; 2880 } 2881 2882 static void 2883 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2884 int end_dci) 2885 { 2886 u_int dci; 2887 2888 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2889 DPRINTFN(4, "slot %u start %u end %u", xs->xs_idx, start_dci, end_dci, 2890 0); 2891 2892 for (dci = start_dci; dci < end_dci; dci++) { 2893 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2894 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2895 } 2896 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2897 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2898 xs->xs_idx = 0; 2899 } 2900 2901 /* 2902 * Setup slot context, set Device Context Base Address, and issue 2903 * Set Address Device command. 2904 */ 2905 static usbd_status 2906 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 2907 { 2908 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2909 struct xhci_slot *xs; 2910 usbd_status err; 2911 2912 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2913 DPRINTFN(4, "slot %u bsr %u", slot, bsr, 0, 0); 2914 2915 xs = &sc->sc_slots[slot]; 2916 2917 xhci_setup_ctx(dev->ud_pipe0); 2918 2919 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2920 sc->sc_ctxsz * 3); 2921 2922 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2923 2924 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 2925 2926 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2927 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2928 sc->sc_ctxsz * 2); 2929 2930 return err; 2931 } 2932 2933 /* 2934 * 4.8.2, 6.2.3.2 2935 * construct slot/endpoint context parameters and do syncmem 2936 */ 2937 static void 2938 xhci_setup_ctx(struct usbd_pipe *pipe) 2939 { 2940 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2941 struct usbd_device *dev = pipe->up_dev; 2942 struct xhci_slot * const xs = dev->ud_hcpriv; 2943 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2944 const u_int dci = xhci_ep_get_dci(ed); 2945 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2946 uint32_t *cp; 2947 uint16_t mps = UGETW(ed->wMaxPacketSize); 2948 uint8_t speed = dev->ud_speed; 2949 uint8_t ival = ed->bInterval; 2950 2951 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2952 DPRINTFN(4, "pipe %p: slot %u dci %u speed %u", pipe, xs->xs_idx, dci, 2953 speed); 2954 2955 /* set up initial input control context */ 2956 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2957 cp[0] = htole32(0); 2958 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 2959 if (dci == XHCI_DCI_EP_CONTROL) 2960 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2961 cp[7] = htole32(0); 2962 2963 /* set up input slot context */ 2964 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2965 cp[0] = 2966 XHCI_SCTX_0_CTX_NUM_SET(dci) | 2967 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 2968 cp[1] = 0; 2969 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2970 cp[3] = 0; 2971 xhci_setup_route(pipe, cp); 2972 xhci_setup_tthub(pipe, cp); 2973 2974 cp[0] = htole32(cp[0]); 2975 cp[1] = htole32(cp[1]); 2976 cp[2] = htole32(cp[2]); 2977 cp[3] = htole32(cp[3]); 2978 2979 /* set up input endpoint context */ 2980 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 2981 cp[0] = 2982 XHCI_EPCTX_0_EPSTATE_SET(0) | 2983 XHCI_EPCTX_0_MULT_SET(0) | 2984 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2985 XHCI_EPCTX_0_LSA_SET(0) | 2986 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 2987 cp[1] = 2988 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 2989 XHCI_EPCTX_1_HID_SET(0) | 2990 XHCI_EPCTX_1_MAXB_SET(0); 2991 2992 if (xfertype != UE_ISOCHRONOUS) 2993 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 2994 2995 if (xfertype == UE_CONTROL) 2996 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 2997 else if (USB_IS_SS(speed)) 2998 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 2999 else 3000 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 3001 3002 xhci_setup_maxburst(pipe, cp); 3003 3004 switch (xfertype) { 3005 case UE_CONTROL: 3006 break; 3007 case UE_BULK: 3008 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 3009 break; 3010 case UE_INTERRUPT: 3011 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3012 ival = pipe->up_interval; 3013 3014 ival = xhci_bival2ival(ival, speed); 3015 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3016 break; 3017 case UE_ISOCHRONOUS: 3018 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3019 ival = pipe->up_interval; 3020 3021 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 3022 if (speed == USB_SPEED_FULL) 3023 ival += 3; /* 1ms -> 125us */ 3024 ival--; 3025 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3026 break; 3027 default: 3028 break; 3029 } 3030 DPRINTFN(4, "setting ival %u MaxBurst %#x", 3031 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 3032 3033 /* rewind TR dequeue pointer in xHC */ 3034 /* can't use xhci_ep_get_dci() yet? */ 3035 *(uint64_t *)(&cp[2]) = htole64( 3036 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 3037 XHCI_EPCTX_2_DCS_SET(1)); 3038 3039 cp[0] = htole32(cp[0]); 3040 cp[1] = htole32(cp[1]); 3041 cp[4] = htole32(cp[4]); 3042 3043 /* rewind TR dequeue pointer in driver */ 3044 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 3045 mutex_enter(&xr->xr_lock); 3046 xhci_host_dequeue(xr); 3047 mutex_exit(&xr->xr_lock); 3048 3049 /* sync input contexts before they are read from memory */ 3050 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3051 } 3052 3053 /* 3054 * Setup route string and roothub port of given device for slot context 3055 */ 3056 static void 3057 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 3058 { 3059 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3060 struct usbd_device *dev = pipe->up_dev; 3061 struct usbd_port *up = dev->ud_powersrc; 3062 struct usbd_device *hub; 3063 struct usbd_device *adev; 3064 uint8_t rhport = 0; 3065 uint32_t route = 0; 3066 3067 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3068 3069 /* Locate root hub port and Determine route string */ 3070 /* 4.3.3 route string does not include roothub port */ 3071 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 3072 uint32_t dep; 3073 3074 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 3075 hub, hub->ud_depth, hub->ud_powersrc, 3076 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 3077 3078 if (hub->ud_powersrc == NULL) 3079 break; 3080 dep = hub->ud_depth; 3081 if (dep == 0) 3082 break; 3083 rhport = hub->ud_powersrc->up_portno; 3084 if (dep > USB_HUB_MAX_DEPTH) 3085 continue; 3086 3087 route |= 3088 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 3089 << ((dep - 1) * 4); 3090 } 3091 route = route >> 4; 3092 size_t bn = hub == sc->sc_bus.ub_roothub ? 0 : 1; 3093 3094 /* Locate port on upstream high speed hub */ 3095 for (adev = dev, hub = up->up_parent; 3096 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 3097 adev = hub, hub = hub->ud_myhub) 3098 ; 3099 if (hub) { 3100 int p; 3101 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 3102 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 3103 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 3104 goto found; 3105 } 3106 } 3107 panic("%s: cannot find HS port", __func__); 3108 found: 3109 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 3110 } else { 3111 dev->ud_myhsport = NULL; 3112 } 3113 3114 const size_t ctlrport = xhci_rhport2ctlrport(sc, bn, rhport); 3115 3116 DPRINTFN(4, "rhport %u ctlrport %u Route %05x hub %p", rhport, 3117 ctlrport, route, hub); 3118 3119 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 3120 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(ctlrport); 3121 } 3122 3123 /* 3124 * Setup whether device is hub, whether device uses MTT, and 3125 * TT informations if it uses MTT. 3126 */ 3127 static void 3128 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 3129 { 3130 struct usbd_device *dev = pipe->up_dev; 3131 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 3132 uint32_t speed = dev->ud_speed; 3133 uint8_t tthubslot, ttportnum; 3134 bool ishub; 3135 bool usemtt; 3136 3137 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3138 3139 /* 3140 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 3141 * tthubslot: 3142 * This is the slot ID of parent HS hub 3143 * if LS/FS device is connected && connected through HS hub. 3144 * This is 0 if device is not LS/FS device || 3145 * parent hub is not HS hub || 3146 * attached to root hub. 3147 * ttportnum: 3148 * This is the downstream facing port of parent HS hub 3149 * if LS/FS device is connected. 3150 * This is 0 if device is not LS/FS device || 3151 * parent hub is not HS hub || 3152 * attached to root hub. 3153 */ 3154 if (dev->ud_myhsport != NULL && 3155 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3156 (dev->ud_myhub != NULL && 3157 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3158 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 3159 ttportnum = dev->ud_myhsport->up_portno; 3160 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 3161 } else { 3162 ttportnum = 0; 3163 tthubslot = 0; 3164 } 3165 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 3166 dev->ud_myhsport, ttportnum, tthubslot, 0); 3167 3168 /* ishub is valid after reading UDESC_DEVICE */ 3169 ishub = (dd->bDeviceClass == UDCLASS_HUB); 3170 3171 /* dev->ud_hub is valid after reading UDESC_HUB */ 3172 if (ishub && dev->ud_hub) { 3173 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 3174 uint8_t ttt = 3175 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 3176 3177 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 3178 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 3179 DPRINTFN(4, "nports=%d ttt=%d", hd->bNbrPorts, ttt, 0, 0); 3180 } 3181 3182 #define IS_TTHUB(dd) \ 3183 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 3184 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 3185 3186 /* 3187 * MTT flag is set if 3188 * 1. this is HS hub && MTT is enabled 3189 * or 3190 * 2. this is not hub && this is LS or FS device && 3191 * MTT of parent HS hub (and its parent, too) is enabled 3192 */ 3193 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 3194 usemtt = true; 3195 else if (!ishub && 3196 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 3197 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3198 (dev->ud_myhub != NULL && 3199 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3200 dev->ud_myhsport != NULL && 3201 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 3202 usemtt = true; 3203 else 3204 usemtt = false; 3205 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 3206 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 3207 3208 #undef IS_TTHUB 3209 3210 cp[0] |= 3211 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 3212 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 3213 cp[2] |= 3214 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 3215 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 3216 } 3217 3218 /* set up params for periodic endpoint */ 3219 static void 3220 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 3221 { 3222 struct usbd_device *dev = pipe->up_dev; 3223 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3224 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3225 usbd_desc_iter_t iter; 3226 const usb_cdc_descriptor_t *cdcd; 3227 uint32_t maxb = 0; 3228 uint16_t mps = UGETW(ed->wMaxPacketSize); 3229 uint8_t speed = dev->ud_speed; 3230 uint8_t ep; 3231 3232 /* config desc is NULL when opening ep0 */ 3233 if (dev == NULL || dev->ud_cdesc == NULL) 3234 goto no_cdcd; 3235 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 3236 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 3237 if (cdcd == NULL) 3238 goto no_cdcd; 3239 usb_desc_iter_init(dev, &iter); 3240 iter.cur = (const void *)cdcd; 3241 3242 /* find endpoint_ss_comp desc for ep of this pipe */ 3243 for (ep = 0;;) { 3244 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 3245 if (cdcd == NULL) 3246 break; 3247 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 3248 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 3249 bEndpointAddress; 3250 if (UE_GET_ADDR(ep) == 3251 UE_GET_ADDR(ed->bEndpointAddress)) { 3252 cdcd = (const usb_cdc_descriptor_t *) 3253 usb_desc_iter_next(&iter); 3254 break; 3255 } 3256 ep = 0; 3257 } 3258 } 3259 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 3260 const usb_endpoint_ss_comp_descriptor_t * esscd = 3261 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3262 maxb = esscd->bMaxBurst; 3263 } 3264 3265 no_cdcd: 3266 /* 6.2.3.4, 4.8.2.4 */ 3267 if (USB_IS_SS(speed)) { 3268 /* USB 3.1 9.6.6 */ 3269 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3270 /* USB 3.1 9.6.7 */ 3271 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3272 #ifdef notyet 3273 if (xfertype == UE_ISOCHRONOUS) { 3274 } 3275 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3276 /* use ESIT */ 3277 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3278 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3279 3280 /* XXX if LEC = 1, set ESIT instead */ 3281 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3282 } else { 3283 /* use ival */ 3284 } 3285 #endif 3286 } else { 3287 /* USB 2.0 9.6.6 */ 3288 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3289 3290 /* 6.2.3.4 */ 3291 if (speed == USB_SPEED_HIGH && 3292 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3293 maxb = UE_GET_TRANS(mps); 3294 } else { 3295 /* LS/FS or HS CTRL or HS BULK */ 3296 maxb = 0; 3297 } 3298 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3299 } 3300 } 3301 3302 /* 3303 * Convert endpoint bInterval value to endpoint context interval value 3304 * for Interrupt pipe. 3305 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3306 */ 3307 static uint32_t 3308 xhci_bival2ival(uint32_t ival, uint32_t speed) 3309 { 3310 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3311 int i; 3312 3313 /* 3314 * round ival down to "the nearest base 2 multiple of 3315 * bInterval * 8". 3316 * bInterval is at most 255 as its type is uByte. 3317 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3318 */ 3319 for (i = 10; i > 0; i--) { 3320 if ((ival * 8) >= (1 << i)) 3321 break; 3322 } 3323 ival = i; 3324 } else { 3325 /* Interval = bInterval-1 for SS/HS */ 3326 ival--; 3327 } 3328 3329 return ival; 3330 } 3331 3332 /* ----- */ 3333 3334 static void 3335 xhci_noop(struct usbd_pipe *pipe) 3336 { 3337 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3338 } 3339 3340 /* 3341 * Process root hub request. 3342 */ 3343 static int 3344 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3345 void *buf, int buflen) 3346 { 3347 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3348 usb_port_status_t ps; 3349 int l, totlen = 0; 3350 uint16_t len, value, index; 3351 int port, i; 3352 uint32_t v; 3353 3354 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3355 3356 if (sc->sc_dying) 3357 return -1; 3358 3359 size_t bn = bus == &sc->sc_bus ? 0 : 1; 3360 3361 len = UGETW(req->wLength); 3362 value = UGETW(req->wValue); 3363 index = UGETW(req->wIndex); 3364 3365 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 3366 req->bmRequestType | (req->bRequest << 8), value, index, len); 3367 3368 #define C(x,y) ((x) | ((y) << 8)) 3369 switch (C(req->bRequest, req->bmRequestType)) { 3370 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3371 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 3372 if (len == 0) 3373 break; 3374 switch (value) { 3375 case C(0, UDESC_DEVICE): { 3376 usb_device_descriptor_t devd; 3377 totlen = min(buflen, sizeof(devd)); 3378 memcpy(&devd, buf, totlen); 3379 USETW(devd.idVendor, sc->sc_id_vendor); 3380 memcpy(buf, &devd, totlen); 3381 break; 3382 } 3383 #define sd ((usb_string_descriptor_t *)buf) 3384 case C(1, UDESC_STRING): 3385 /* Vendor */ 3386 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3387 break; 3388 case C(2, UDESC_STRING): 3389 /* Product */ 3390 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3391 break; 3392 #undef sd 3393 default: 3394 /* default from usbroothub */ 3395 return buflen; 3396 } 3397 break; 3398 3399 /* Hub requests */ 3400 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3401 break; 3402 /* Clear Port Feature request */ 3403 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): { 3404 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3405 3406 DPRINTFN(4, "UR_CLEAR_PORT_FEAT bp=%d feat=%d bus=%d cp=%d", 3407 index, value, bn, cp); 3408 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3409 return -1; 3410 } 3411 port = XHCI_PORTSC(cp); 3412 v = xhci_op_read_4(sc, port); 3413 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3414 v &= ~XHCI_PS_CLEAR; 3415 switch (value) { 3416 case UHF_PORT_ENABLE: 3417 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3418 break; 3419 case UHF_PORT_SUSPEND: 3420 return -1; 3421 case UHF_PORT_POWER: 3422 break; 3423 case UHF_PORT_TEST: 3424 case UHF_PORT_INDICATOR: 3425 return -1; 3426 case UHF_C_PORT_CONNECTION: 3427 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3428 break; 3429 case UHF_C_PORT_ENABLE: 3430 case UHF_C_PORT_SUSPEND: 3431 case UHF_C_PORT_OVER_CURRENT: 3432 return -1; 3433 case UHF_C_BH_PORT_RESET: 3434 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3435 break; 3436 case UHF_C_PORT_RESET: 3437 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3438 break; 3439 case UHF_C_PORT_LINK_STATE: 3440 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3441 break; 3442 case UHF_C_PORT_CONFIG_ERROR: 3443 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3444 break; 3445 default: 3446 return -1; 3447 } 3448 break; 3449 } 3450 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3451 if (len == 0) 3452 break; 3453 if ((value & 0xff) != 0) { 3454 return -1; 3455 } 3456 usb_hub_descriptor_t hubd; 3457 3458 totlen = min(buflen, sizeof(hubd)); 3459 memcpy(&hubd, buf, totlen); 3460 hubd.bNbrPorts = sc->sc_rhportcount[bn]; 3461 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3462 hubd.bPwrOn2PwrGood = 200; 3463 for (i = 0, l = sc->sc_rhportcount[bn]; l > 0; i++, l -= 8) { 3464 /* XXX can't find out? */ 3465 hubd.DeviceRemovable[i++] = 0; 3466 } 3467 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3468 totlen = min(totlen, hubd.bDescLength); 3469 memcpy(buf, &hubd, totlen); 3470 break; 3471 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3472 if (len != 4) { 3473 return -1; 3474 } 3475 memset(buf, 0, len); /* ? XXX */ 3476 totlen = len; 3477 break; 3478 /* Get Port Status request */ 3479 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): { 3480 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3481 3482 DPRINTFN(8, "get port status bn=%d i=%d cp=%zu", bn, index, cp, 3483 0); 3484 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3485 return -1; 3486 } 3487 if (len != 4) { 3488 return -1; 3489 } 3490 v = xhci_op_read_4(sc, XHCI_PORTSC(cp)); 3491 DPRINTFN(4, "getrhportsc %d %08x", cp, v, 0, 0); 3492 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3493 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3494 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3495 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3496 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3497 if (v & XHCI_PS_PR) i |= UPS_RESET; 3498 if (v & XHCI_PS_PP) { 3499 if (i & UPS_OTHER_SPEED) 3500 i |= UPS_PORT_POWER_SS; 3501 else 3502 i |= UPS_PORT_POWER; 3503 } 3504 if (i & UPS_OTHER_SPEED) 3505 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3506 if (sc->sc_vendor_port_status) 3507 i = sc->sc_vendor_port_status(sc, v, i); 3508 USETW(ps.wPortStatus, i); 3509 i = 0; 3510 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3511 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3512 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3513 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3514 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3515 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3516 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3517 USETW(ps.wPortChange, i); 3518 totlen = min(len, sizeof(ps)); 3519 memcpy(buf, &ps, totlen); 3520 break; 3521 } 3522 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3523 return -1; 3524 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3525 break; 3526 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3527 break; 3528 /* Set Port Feature request */ 3529 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3530 int optval = (index >> 8) & 0xff; 3531 index &= 0xff; 3532 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3533 return -1; 3534 } 3535 3536 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3537 3538 port = XHCI_PORTSC(cp); 3539 v = xhci_op_read_4(sc, port); 3540 DPRINTFN(4, "index %d cp %d portsc=0x%08x", index, cp, v, 0); 3541 v &= ~XHCI_PS_CLEAR; 3542 switch (value) { 3543 case UHF_PORT_ENABLE: 3544 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3545 break; 3546 case UHF_PORT_SUSPEND: 3547 /* XXX suspend */ 3548 break; 3549 case UHF_PORT_RESET: 3550 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3551 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3552 /* Wait for reset to complete. */ 3553 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3554 if (sc->sc_dying) { 3555 return -1; 3556 } 3557 v = xhci_op_read_4(sc, port); 3558 if (v & XHCI_PS_PR) { 3559 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3560 usb_delay_ms(&sc->sc_bus, 10); 3561 /* XXX */ 3562 } 3563 break; 3564 case UHF_PORT_POWER: 3565 /* XXX power control */ 3566 break; 3567 /* XXX more */ 3568 case UHF_C_PORT_RESET: 3569 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3570 break; 3571 case UHF_PORT_U1_TIMEOUT: 3572 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3573 return -1; 3574 } 3575 port = XHCI_PORTPMSC(cp); 3576 v = xhci_op_read_4(sc, port); 3577 DPRINTFN(4, "index %d cp %d portpmsc=0x%08x", index, cp, v, 0); 3578 v &= ~XHCI_PM3_U1TO_SET(0xff); 3579 v |= XHCI_PM3_U1TO_SET(optval); 3580 xhci_op_write_4(sc, port, v); 3581 break; 3582 case UHF_PORT_U2_TIMEOUT: 3583 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3584 return -1; 3585 } 3586 port = XHCI_PORTPMSC(cp); 3587 v = xhci_op_read_4(sc, port); 3588 DPRINTFN(4, "index %d cp %d portpmsc=0x%08x", index, cp, v, 0); 3589 v &= ~XHCI_PM3_U2TO_SET(0xff); 3590 v |= XHCI_PM3_U2TO_SET(optval); 3591 xhci_op_write_4(sc, port, v); 3592 break; 3593 default: 3594 return -1; 3595 } 3596 } 3597 break; 3598 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3599 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3600 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3601 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3602 break; 3603 default: 3604 /* default from usbroothub */ 3605 return buflen; 3606 } 3607 3608 return totlen; 3609 } 3610 3611 /* root hub interrupt */ 3612 3613 static usbd_status 3614 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3615 { 3616 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3617 usbd_status err; 3618 3619 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3620 3621 /* Insert last in queue. */ 3622 mutex_enter(&sc->sc_lock); 3623 err = usb_insert_transfer(xfer); 3624 mutex_exit(&sc->sc_lock); 3625 if (err) 3626 return err; 3627 3628 /* Pipe isn't running, start first */ 3629 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3630 } 3631 3632 /* Wait for roothub port status/change */ 3633 static usbd_status 3634 xhci_root_intr_start(struct usbd_xfer *xfer) 3635 { 3636 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3637 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3638 3639 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3640 3641 if (sc->sc_dying) 3642 return USBD_IOERROR; 3643 3644 mutex_enter(&sc->sc_lock); 3645 sc->sc_intrxfer[bn] = xfer; 3646 mutex_exit(&sc->sc_lock); 3647 3648 return USBD_IN_PROGRESS; 3649 } 3650 3651 static void 3652 xhci_root_intr_abort(struct usbd_xfer *xfer) 3653 { 3654 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3655 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3656 3657 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3658 3659 KASSERT(mutex_owned(&sc->sc_lock)); 3660 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3661 3662 sc->sc_intrxfer[bn] = NULL; 3663 3664 xfer->ux_status = USBD_CANCELLED; 3665 usb_transfer_complete(xfer); 3666 } 3667 3668 static void 3669 xhci_root_intr_close(struct usbd_pipe *pipe) 3670 { 3671 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3672 const struct usbd_xfer *xfer = pipe->up_intrxfer; 3673 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3674 3675 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3676 3677 KASSERT(mutex_owned(&sc->sc_lock)); 3678 3679 sc->sc_intrxfer[bn] = NULL; 3680 } 3681 3682 static void 3683 xhci_root_intr_done(struct usbd_xfer *xfer) 3684 { 3685 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3686 3687 } 3688 3689 /* -------------- */ 3690 /* device control */ 3691 3692 static usbd_status 3693 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3694 { 3695 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3696 usbd_status err; 3697 3698 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3699 3700 /* Insert last in queue. */ 3701 mutex_enter(&sc->sc_lock); 3702 err = usb_insert_transfer(xfer); 3703 mutex_exit(&sc->sc_lock); 3704 if (err) 3705 return err; 3706 3707 /* Pipe isn't running, start first */ 3708 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3709 } 3710 3711 static usbd_status 3712 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3713 { 3714 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3715 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3716 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3717 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3718 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3719 usb_device_request_t * const req = &xfer->ux_request; 3720 const int isread = usbd_xfer_isread(xfer); 3721 const uint32_t len = UGETW(req->wLength); 3722 usb_dma_t * const dma = &xfer->ux_dmabuf; 3723 uint64_t parameter; 3724 uint32_t status; 3725 uint32_t control; 3726 u_int i; 3727 3728 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3729 DPRINTFN(12, "req: %04x %04x %04x %04x", 3730 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3731 UGETW(req->wIndex), UGETW(req->wLength)); 3732 3733 /* we rely on the bottom bits for extra info */ 3734 KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx", 3735 (uintptr_t) xfer); 3736 3737 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3738 3739 i = 0; 3740 3741 /* setup phase */ 3742 memcpy(¶meter, req, sizeof(parameter)); 3743 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3744 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3745 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3746 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3747 XHCI_TRB_3_IDT_BIT; 3748 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3749 3750 if (len != 0) { 3751 /* data phase */ 3752 parameter = DMAADDR(dma, 0); 3753 KASSERTMSG(len <= 0x10000, "len %d", len); 3754 status = XHCI_TRB_2_IRQ_SET(0) | 3755 XHCI_TRB_2_TDSZ_SET(1) | 3756 XHCI_TRB_2_BYTES_SET(len); 3757 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3758 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3759 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3760 XHCI_TRB_3_IOC_BIT; 3761 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3762 } 3763 3764 parameter = 0; 3765 status = XHCI_TRB_2_IRQ_SET(0); 3766 /* the status stage has inverted direction */ 3767 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3768 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3769 XHCI_TRB_3_IOC_BIT; 3770 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3771 3772 mutex_enter(&tr->xr_lock); 3773 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3774 mutex_exit(&tr->xr_lock); 3775 3776 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3777 3778 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3779 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3780 xhci_timeout, xfer); 3781 } 3782 3783 return USBD_IN_PROGRESS; 3784 } 3785 3786 static void 3787 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3788 { 3789 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3790 usb_device_request_t *req = &xfer->ux_request; 3791 int len = UGETW(req->wLength); 3792 int rd = req->bmRequestType & UT_READ; 3793 3794 if (len) 3795 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3796 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3797 } 3798 3799 static void 3800 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3801 { 3802 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3803 3804 xhci_abort_xfer(xfer, USBD_CANCELLED); 3805 } 3806 3807 static void 3808 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3809 { 3810 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3811 3812 xhci_close_pipe(pipe); 3813 } 3814 3815 /* ------------------ */ 3816 /* device isochronous */ 3817 3818 /* ----------- */ 3819 /* device bulk */ 3820 3821 static usbd_status 3822 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3823 { 3824 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3825 usbd_status err; 3826 3827 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3828 3829 /* Insert last in queue. */ 3830 mutex_enter(&sc->sc_lock); 3831 err = usb_insert_transfer(xfer); 3832 mutex_exit(&sc->sc_lock); 3833 if (err) 3834 return err; 3835 3836 /* 3837 * Pipe isn't running (otherwise err would be USBD_INPROG), 3838 * so start it first. 3839 */ 3840 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3841 } 3842 3843 static usbd_status 3844 xhci_device_bulk_start(struct usbd_xfer *xfer) 3845 { 3846 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3847 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3848 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3849 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3850 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3851 const uint32_t len = xfer->ux_length; 3852 usb_dma_t * const dma = &xfer->ux_dmabuf; 3853 uint64_t parameter; 3854 uint32_t status; 3855 uint32_t control; 3856 u_int i = 0; 3857 3858 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3859 3860 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3861 3862 if (sc->sc_dying) 3863 return USBD_IOERROR; 3864 3865 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3866 3867 parameter = DMAADDR(dma, 0); 3868 /* 3869 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3870 * If the user supplied buffer crosses such a boundary then 2 3871 * (or more) TRB should be used. 3872 * If multiple TRB are used the td_size field must be set correctly. 3873 * For v1.0 devices (like ivy bridge) this is the number of usb data 3874 * blocks needed to complete the transfer. 3875 * Setting it to 1 in the last TRB causes an extra zero-length 3876 * data block be sent. 3877 * The earlier documentation differs, I don't know how it behaves. 3878 */ 3879 KASSERTMSG(len <= 0x10000, "len %d", len); 3880 status = XHCI_TRB_2_IRQ_SET(0) | 3881 XHCI_TRB_2_TDSZ_SET(1) | 3882 XHCI_TRB_2_BYTES_SET(len); 3883 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3884 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3885 XHCI_TRB_3_IOC_BIT; 3886 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3887 3888 mutex_enter(&tr->xr_lock); 3889 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3890 mutex_exit(&tr->xr_lock); 3891 3892 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3893 3894 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3895 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3896 xhci_timeout, xfer); 3897 } 3898 3899 return USBD_IN_PROGRESS; 3900 } 3901 3902 static void 3903 xhci_device_bulk_done(struct usbd_xfer *xfer) 3904 { 3905 #ifdef USB_DEBUG 3906 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3907 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3908 #endif 3909 const int isread = usbd_xfer_isread(xfer); 3910 3911 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3912 3913 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3914 3915 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3916 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3917 } 3918 3919 static void 3920 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3921 { 3922 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3923 3924 xhci_abort_xfer(xfer, USBD_CANCELLED); 3925 } 3926 3927 static void 3928 xhci_device_bulk_close(struct usbd_pipe *pipe) 3929 { 3930 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3931 3932 xhci_close_pipe(pipe); 3933 } 3934 3935 /* ---------------- */ 3936 /* device interrupt */ 3937 3938 static usbd_status 3939 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3940 { 3941 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3942 usbd_status err; 3943 3944 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3945 3946 /* Insert last in queue. */ 3947 mutex_enter(&sc->sc_lock); 3948 err = usb_insert_transfer(xfer); 3949 mutex_exit(&sc->sc_lock); 3950 if (err) 3951 return err; 3952 3953 /* 3954 * Pipe isn't running (otherwise err would be USBD_INPROG), 3955 * so start it first. 3956 */ 3957 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3958 } 3959 3960 static usbd_status 3961 xhci_device_intr_start(struct usbd_xfer *xfer) 3962 { 3963 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3964 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3965 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3966 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3967 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3968 const uint32_t len = xfer->ux_length; 3969 usb_dma_t * const dma = &xfer->ux_dmabuf; 3970 uint64_t parameter; 3971 uint32_t status; 3972 uint32_t control; 3973 u_int i = 0; 3974 3975 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3976 3977 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3978 3979 if (sc->sc_dying) 3980 return USBD_IOERROR; 3981 3982 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3983 3984 parameter = DMAADDR(dma, 0); 3985 KASSERTMSG(len <= 0x10000, "len %d", len); 3986 status = XHCI_TRB_2_IRQ_SET(0) | 3987 XHCI_TRB_2_TDSZ_SET(1) | 3988 XHCI_TRB_2_BYTES_SET(len); 3989 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3990 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3991 XHCI_TRB_3_IOC_BIT; 3992 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3993 3994 mutex_enter(&tr->xr_lock); 3995 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3996 mutex_exit(&tr->xr_lock); 3997 3998 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3999 4000 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4001 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4002 xhci_timeout, xfer); 4003 } 4004 4005 return USBD_IN_PROGRESS; 4006 } 4007 4008 static void 4009 xhci_device_intr_done(struct usbd_xfer *xfer) 4010 { 4011 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4012 #ifdef USB_DEBUG 4013 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4014 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4015 #endif 4016 const int isread = usbd_xfer_isread(xfer); 4017 4018 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4019 4020 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 4021 4022 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4023 4024 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4025 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4026 } 4027 4028 static void 4029 xhci_device_intr_abort(struct usbd_xfer *xfer) 4030 { 4031 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4032 4033 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4034 4035 KASSERT(mutex_owned(&sc->sc_lock)); 4036 DPRINTFN(15, "%p", xfer, 0, 0, 0); 4037 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4038 xhci_abort_xfer(xfer, USBD_CANCELLED); 4039 } 4040 4041 static void 4042 xhci_device_intr_close(struct usbd_pipe *pipe) 4043 { 4044 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 4045 4046 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4047 DPRINTFN(15, "%p", pipe, 0, 0, 0); 4048 4049 xhci_close_pipe(pipe); 4050 } 4051 4052 /* ------------ */ 4053 4054 static void 4055 xhci_timeout(void *addr) 4056 { 4057 struct xhci_xfer * const xx = addr; 4058 struct usbd_xfer * const xfer = &xx->xx_xfer; 4059 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4060 4061 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4062 4063 if (sc->sc_dying) { 4064 return; 4065 } 4066 4067 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 4068 USB_TASKQ_MPSAFE); 4069 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 4070 USB_TASKQ_HC); 4071 } 4072 4073 static void 4074 xhci_timeout_task(void *addr) 4075 { 4076 struct usbd_xfer * const xfer = addr; 4077 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4078 4079 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4080 4081 mutex_enter(&sc->sc_lock); 4082 xhci_abort_xfer(xfer, USBD_TIMEOUT); 4083 mutex_exit(&sc->sc_lock); 4084 } 4085
Indexes created Mon Sep 22 21:09:42 GMT 2025