xhci.c revision 1.72.2.14
1 /* $NetBSD: xhci.c,v 1.72.2.14 2023/01/23 12:10:12 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.72.2.14 2023/01/23 12:10:12 martin Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static void xhci_host_dequeue(struct xhci_ring * const); 146 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 147 148 static usbd_status xhci_do_command(struct xhci_softc * const, 149 struct xhci_trb * const, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 153 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 154 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 155 static usbd_status xhci_enable_slot(struct xhci_softc * const, 156 uint8_t * const); 157 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 158 static usbd_status xhci_address_device(struct xhci_softc * const, 159 uint64_t, uint8_t, bool); 160 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 161 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 162 struct xhci_slot * const, u_int); 163 static usbd_status xhci_ring_init(struct xhci_softc * const, 164 struct xhci_ring * const, size_t, size_t); 165 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 166 167 static void xhci_setup_ctx(struct usbd_pipe *); 168 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 169 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 170 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 171 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 172 173 static void xhci_noop(struct usbd_pipe *); 174 175 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 176 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 177 static void xhci_root_intr_abort(struct usbd_xfer *); 178 static void xhci_root_intr_close(struct usbd_pipe *); 179 static void xhci_root_intr_done(struct usbd_xfer *); 180 181 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 182 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 183 static void xhci_device_ctrl_abort(struct usbd_xfer *); 184 static void xhci_device_ctrl_close(struct usbd_pipe *); 185 static void xhci_device_ctrl_done(struct usbd_xfer *); 186 187 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 188 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 189 static void xhci_device_intr_abort(struct usbd_xfer *); 190 static void xhci_device_intr_close(struct usbd_pipe *); 191 static void xhci_device_intr_done(struct usbd_xfer *); 192 193 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 194 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 195 static void xhci_device_bulk_abort(struct usbd_xfer *); 196 static void xhci_device_bulk_close(struct usbd_pipe *); 197 static void xhci_device_bulk_done(struct usbd_xfer *); 198 199 static void xhci_timeout(void *); 200 static void xhci_timeout_task(void *); 201 202 static const struct usbd_bus_methods xhci_bus_methods = { 203 .ubm_open = xhci_open, 204 .ubm_softint = xhci_softintr, 205 .ubm_dopoll = xhci_poll, 206 .ubm_allocx = xhci_allocx, 207 .ubm_freex = xhci_freex, 208 .ubm_getlock = xhci_get_lock, 209 .ubm_newdev = xhci_new_device, 210 .ubm_rhctrl = xhci_roothub_ctrl, 211 }; 212 213 static const struct usbd_pipe_methods xhci_root_intr_methods = { 214 .upm_transfer = xhci_root_intr_transfer, 215 .upm_start = xhci_root_intr_start, 216 .upm_abort = xhci_root_intr_abort, 217 .upm_close = xhci_root_intr_close, 218 .upm_cleartoggle = xhci_noop, 219 .upm_done = xhci_root_intr_done, 220 }; 221 222 223 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 224 .upm_transfer = xhci_device_ctrl_transfer, 225 .upm_start = xhci_device_ctrl_start, 226 .upm_abort = xhci_device_ctrl_abort, 227 .upm_close = xhci_device_ctrl_close, 228 .upm_cleartoggle = xhci_noop, 229 .upm_done = xhci_device_ctrl_done, 230 }; 231 232 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 233 .upm_cleartoggle = xhci_noop, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 237 .upm_transfer = xhci_device_bulk_transfer, 238 .upm_start = xhci_device_bulk_start, 239 .upm_abort = xhci_device_bulk_abort, 240 .upm_close = xhci_device_bulk_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_bulk_done, 243 }; 244 245 static const struct usbd_pipe_methods xhci_device_intr_methods = { 246 .upm_transfer = xhci_device_intr_transfer, 247 .upm_start = xhci_device_intr_start, 248 .upm_abort = xhci_device_intr_abort, 249 .upm_close = xhci_device_intr_close, 250 .upm_cleartoggle = xhci_noop, 251 .upm_done = xhci_device_intr_done, 252 }; 253 254 static inline uint32_t 255 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 256 { 257 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 258 } 259 260 static inline uint32_t 261 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 262 { 263 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 264 } 265 266 static inline void 267 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 268 uint32_t value) 269 { 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 271 } 272 273 #if 0 /* unused */ 274 static inline void 275 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 276 uint32_t value) 277 { 278 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 279 } 280 #endif /* unused */ 281 282 static inline uint32_t 283 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 284 { 285 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 286 } 287 288 static inline uint32_t 289 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 290 { 291 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 292 } 293 294 static inline void 295 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 296 uint32_t value) 297 { 298 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 299 } 300 301 static inline uint64_t 302 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 303 { 304 uint64_t value; 305 306 if (sc->sc_ac64) { 307 #ifdef XHCI_USE_BUS_SPACE_8 308 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 309 #else 310 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 311 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 312 offset + 4) << 32; 313 #endif 314 } else { 315 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 316 } 317 318 return value; 319 } 320 321 static inline void 322 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 336 } 337 } 338 339 static inline uint32_t 340 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 341 { 342 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 343 } 344 345 static inline void 346 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 347 uint32_t value) 348 { 349 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 350 } 351 352 #if 0 /* unused */ 353 static inline uint64_t 354 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 355 { 356 uint64_t value; 357 358 if (sc->sc_ac64) { 359 #ifdef XHCI_USE_BUS_SPACE_8 360 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 361 #else 362 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 363 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 364 offset + 4) << 32; 365 #endif 366 } else { 367 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 368 } 369 370 return value; 371 } 372 #endif /* unused */ 373 374 static inline void 375 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 376 uint64_t value) 377 { 378 if (sc->sc_ac64) { 379 #ifdef XHCI_USE_BUS_SPACE_8 380 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 381 #else 382 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 383 (value >> 0) & 0xffffffff); 384 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 385 (value >> 32) & 0xffffffff); 386 #endif 387 } else { 388 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 389 } 390 } 391 392 #if 0 /* unused */ 393 static inline uint32_t 394 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 395 { 396 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 397 } 398 #endif /* unused */ 399 400 static inline void 401 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 402 uint32_t value) 403 { 404 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 405 } 406 407 /* --- */ 408 409 static inline uint8_t 410 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 411 { 412 u_int eptype = 0; 413 414 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 415 case UE_CONTROL: 416 eptype = 0x0; 417 break; 418 case UE_ISOCHRONOUS: 419 eptype = 0x1; 420 break; 421 case UE_BULK: 422 eptype = 0x2; 423 break; 424 case UE_INTERRUPT: 425 eptype = 0x3; 426 break; 427 } 428 429 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 430 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 431 return eptype | 0x4; 432 else 433 return eptype; 434 } 435 436 static u_int 437 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 438 { 439 /* xHCI 1.0 section 4.5.1 */ 440 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 441 u_int in = 0; 442 443 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 444 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 445 in = 1; 446 447 return epaddr * 2 + in; 448 } 449 450 static inline u_int 451 xhci_dci_to_ici(const u_int i) 452 { 453 return i + 1; 454 } 455 456 static inline void * 457 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 458 const u_int dci) 459 { 460 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 461 } 462 463 #if 0 /* unused */ 464 static inline bus_addr_t 465 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 466 const u_int dci) 467 { 468 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 469 } 470 #endif /* unused */ 471 472 static inline void * 473 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline bus_addr_t 480 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 481 const u_int ici) 482 { 483 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 484 } 485 486 static inline struct xhci_trb * 487 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 488 { 489 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 490 } 491 492 static inline bus_addr_t 493 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 494 { 495 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 496 } 497 498 static inline void 499 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 500 uint32_t control) 501 { 502 trb->trb_0 = htole64(parameter); 503 trb->trb_2 = htole32(status); 504 trb->trb_3 = htole32(control); 505 } 506 507 static int 508 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 509 { 510 /* base address of TRBs */ 511 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 512 513 /* trb_0 range sanity check */ 514 if (trb_0 == 0 || trb_0 < trbp || 515 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 516 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 517 return 1; 518 } 519 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 520 return 0; 521 } 522 523 static unsigned int 524 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 525 u_int dci) 526 { 527 uint32_t *cp; 528 529 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 530 cp = xhci_slot_get_dcv(sc, xs, dci); 531 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 532 } 533 534 static inline unsigned int 535 xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport) 536 { 537 const unsigned int port = ctlrport - 1; 538 const uint8_t bit = __BIT(port % NBBY); 539 540 return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit); 541 } 542 543 /* 544 * Return the roothub port for a controller port. Both are 1..n. 545 */ 546 static inline unsigned int 547 xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport) 548 { 549 550 return sc->sc_ctlrportmap[ctrlport - 1]; 551 } 552 553 /* 554 * Return the controller port for a bus roothub port. Both are 1..n. 555 */ 556 static inline unsigned int 557 xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn, 558 unsigned int rhport) 559 { 560 561 return sc->sc_rhportmap[bn][rhport - 1]; 562 } 563 564 /* --- */ 565 566 void 567 xhci_childdet(device_t self, device_t child) 568 { 569 struct xhci_softc * const sc = device_private(self); 570 571 KASSERT(sc->sc_child == child); 572 if (child == sc->sc_child) 573 sc->sc_child = NULL; 574 } 575 576 int 577 xhci_detach(struct xhci_softc *sc, int flags) 578 { 579 int rv = 0; 580 581 if (sc->sc_child2 != NULL) { 582 rv = config_detach(sc->sc_child2, flags); 583 if (rv != 0) 584 return rv; 585 KASSERT(sc->sc_child2 == NULL); 586 } 587 588 if (sc->sc_child != NULL) { 589 rv = config_detach(sc->sc_child, flags); 590 if (rv != 0) 591 return rv; 592 KASSERT(sc->sc_child == NULL); 593 } 594 595 /* XXX unconfigure/free slots */ 596 597 /* verify: */ 598 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 599 xhci_op_write_4(sc, XHCI_USBCMD, 0); 600 /* do we need to wait for stop? */ 601 602 xhci_op_write_8(sc, XHCI_CRCR, 0); 603 xhci_ring_free(sc, &sc->sc_cr); 604 cv_destroy(&sc->sc_command_cv); 605 cv_destroy(&sc->sc_cmdbusy_cv); 606 607 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 608 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 609 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 610 xhci_ring_free(sc, &sc->sc_er); 611 612 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 613 614 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 615 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 616 617 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 618 619 kmem_free(sc->sc_ctlrportbus, 620 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY)); 621 kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int)); 622 623 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 624 kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int)); 625 } 626 627 mutex_destroy(&sc->sc_lock); 628 mutex_destroy(&sc->sc_intr_lock); 629 630 pool_cache_destroy(sc->sc_xferpool); 631 632 return rv; 633 } 634 635 int 636 xhci_activate(device_t self, enum devact act) 637 { 638 struct xhci_softc * const sc = device_private(self); 639 640 switch (act) { 641 case DVACT_DEACTIVATE: 642 sc->sc_dying = true; 643 return 0; 644 default: 645 return EOPNOTSUPP; 646 } 647 } 648 649 bool 650 xhci_suspend(device_t dv, const pmf_qual_t *qual) 651 { 652 return false; 653 } 654 655 bool 656 xhci_resume(device_t dv, const pmf_qual_t *qual) 657 { 658 return false; 659 } 660 661 bool 662 xhci_shutdown(device_t self, int flags) 663 { 664 return false; 665 } 666 667 static int 668 xhci_hc_reset(struct xhci_softc * const sc) 669 { 670 uint32_t usbcmd, usbsts; 671 int i; 672 673 /* Check controller not ready */ 674 for (i = 0; i < XHCI_WAIT_CNR; i++) { 675 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 676 if ((usbsts & XHCI_STS_CNR) == 0) 677 break; 678 usb_delay_ms(&sc->sc_bus, 1); 679 } 680 if (i >= XHCI_WAIT_CNR) { 681 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 682 return EIO; 683 } 684 685 /* Halt controller */ 686 usbcmd = 0; 687 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 688 usb_delay_ms(&sc->sc_bus, 1); 689 690 /* Reset controller */ 691 usbcmd = XHCI_CMD_HCRST; 692 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 693 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 694 /* 695 * Wait 1ms first. Existing Intel xHCI requies 1ms delay to 696 * prevent system hang (Errata). 697 */ 698 usb_delay_ms(&sc->sc_bus, 1); 699 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 700 if ((usbcmd & XHCI_CMD_HCRST) == 0) 701 break; 702 } 703 if (i >= XHCI_WAIT_HCRST) { 704 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 705 return EIO; 706 } 707 708 /* Check controller not ready */ 709 for (i = 0; i < XHCI_WAIT_CNR; i++) { 710 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 711 if ((usbsts & XHCI_STS_CNR) == 0) 712 break; 713 usb_delay_ms(&sc->sc_bus, 1); 714 } 715 if (i >= XHCI_WAIT_CNR) { 716 aprint_error_dev(sc->sc_dev, 717 "controller not ready timeout after reset\n"); 718 return EIO; 719 } 720 721 return 0; 722 } 723 724 725 static void 726 hexdump(const char *msg, const void *base, size_t len) 727 { 728 #if 0 729 size_t cnt; 730 const uint32_t *p; 731 extern paddr_t vtophys(vaddr_t); 732 733 p = base; 734 cnt = 0; 735 736 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 737 (void *)vtophys((vaddr_t)base)); 738 739 while (cnt < len) { 740 if (cnt % 16 == 0) 741 printf("%p: ", p); 742 else if (cnt % 8 == 0) 743 printf(" |"); 744 printf(" %08x", *p++); 745 cnt += 4; 746 if (cnt % 16 == 0) 747 printf("\n"); 748 } 749 if (cnt % 16 != 0) 750 printf("\n"); 751 #endif 752 } 753 754 /* 7.2 xHCI Support Protocol Capability */ 755 static void 756 xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp) 757 { 758 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 759 760 /* XXX Cache this lot */ 761 762 const uint32_t w0 = xhci_read_4(sc, ecp); 763 const uint32_t w4 = xhci_read_4(sc, ecp + 4); 764 const uint32_t w8 = xhci_read_4(sc, ecp + 8); 765 const uint32_t wc = xhci_read_4(sc, ecp + 0xc); 766 767 aprint_debug_dev(sc->sc_dev, 768 " SP: %08x %08x %08x %08x\n", w0, w4, w8, wc); 769 770 if (w4 != XHCI_XECP_USBID) 771 return; 772 773 const int major = XHCI_XECP_SP_W0_MAJOR(w0); 774 const int minor = XHCI_XECP_SP_W0_MINOR(w0); 775 const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8); 776 const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8); 777 778 const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16)); 779 switch (mm) { 780 case 0x0200: 781 case 0x0300: 782 case 0x0301: 783 case 0x0310: 784 case 0x0320: 785 aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n", 786 major == 3 ? "ss" : "hs", cpo, cpo + cpc - 1); 787 if (major == 3) 788 sc->sc_usb3nports += cpo + cpc - 1; 789 else 790 sc->sc_usb2nports += cpo + cpc - 1; 791 break; 792 default: 793 aprint_debug_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n", 794 major, minor); 795 return; 796 } 797 798 const size_t bus = (major == 3) ? 0 : 1; 799 800 /* Index arrays with 0..n-1 where ports are numbered 1..n */ 801 for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) { 802 if (sc->sc_ctlrportmap[cp] != 0) { 803 aprint_error_dev(sc->sc_dev, "contoller port %zu " 804 "already assigned", cp); 805 continue; 806 } 807 808 sc->sc_ctlrportbus[cp / NBBY] |= 809 bus == 0 ? 0 : __BIT(cp % NBBY); 810 811 const size_t rhp = sc->sc_rhportcount[bus]++; 812 813 KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0, 814 "bus %zu rhp %zu is %d", bus, rhp, 815 sc->sc_rhportmap[bus][rhp]); 816 817 sc->sc_rhportmap[bus][rhp] = cp + 1; 818 sc->sc_ctlrportmap[cp] = rhp + 1; 819 } 820 } 821 822 /* Process extended capabilities */ 823 static void 824 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 825 { 826 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 827 828 bus_size_t ecp = XHCI_HCC_XECP(hcc) * 4; 829 while (ecp != 0) { 830 uint32_t ecr = xhci_read_4(sc, ecp); 831 aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr); 832 switch (XHCI_XECP_ID(ecr)) { 833 case XHCI_ID_PROTOCOLS: { 834 xhci_id_protocols(sc, ecp); 835 break; 836 } 837 case XHCI_ID_USB_LEGACY: { 838 uint8_t bios_sem; 839 840 /* Take host controller ownership from BIOS */ 841 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 842 if (bios_sem) { 843 /* sets xHCI to be owned by OS */ 844 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 845 aprint_debug_dev(sc->sc_dev, 846 "waiting for BIOS to give up control\n"); 847 for (int i = 0; i < 5000; i++) { 848 bios_sem = xhci_read_1(sc, ecp + 849 XHCI_XECP_BIOS_SEM); 850 if (bios_sem == 0) 851 break; 852 DELAY(1000); 853 } 854 if (bios_sem) { 855 aprint_error_dev(sc->sc_dev, 856 "timed out waiting for BIOS\n"); 857 } 858 } 859 break; 860 } 861 default: 862 break; 863 } 864 ecr = xhci_read_4(sc, ecp); 865 if (XHCI_XECP_NEXT(ecr) == 0) { 866 ecp = 0; 867 } else { 868 ecp += XHCI_XECP_NEXT(ecr) * 4; 869 } 870 } 871 } 872 873 #define XHCI_HCCPREV1_BITS \ 874 "\177\020" /* New bitmask */ \ 875 "f\020\020XECP\0" \ 876 "f\014\4MAXPSA\0" \ 877 "b\013CFC\0" \ 878 "b\012SEC\0" \ 879 "b\011SBD\0" \ 880 "b\010FSE\0" \ 881 "b\7NSS\0" \ 882 "b\6LTC\0" \ 883 "b\5LHRC\0" \ 884 "b\4PIND\0" \ 885 "b\3PPC\0" \ 886 "b\2CZC\0" \ 887 "b\1BNC\0" \ 888 "b\0AC64\0" \ 889 "\0" 890 #define XHCI_HCCV1_x_BITS \ 891 "\177\020" /* New bitmask */ \ 892 "f\020\020XECP\0" \ 893 "f\014\4MAXPSA\0" \ 894 "b\013CFC\0" \ 895 "b\012SEC\0" \ 896 "b\011SPC\0" \ 897 "b\010PAE\0" \ 898 "b\7NSS\0" \ 899 "b\6LTC\0" \ 900 "b\5LHRC\0" \ 901 "b\4PIND\0" \ 902 "b\3PPC\0" \ 903 "b\2CSZ\0" \ 904 "b\1BNC\0" \ 905 "b\0AC64\0" \ 906 "\0" 907 908 #define XHCI_HCC2_BITS \ 909 "\177\020" /* New bitmask */ \ 910 "b\7ETC_TSC\0" \ 911 "b\6ETC\0" \ 912 "b\5CIC\0" \ 913 "b\4LEC\0" \ 914 "b\3CTC\0" \ 915 "b\2FSC\0" \ 916 "b\1CMC\0" \ 917 "b\0U3C\0" \ 918 "\0" 919 920 int 921 xhci_init(struct xhci_softc *sc) 922 { 923 bus_size_t bsz; 924 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff, hcc2; 925 uint32_t pagesize, config; 926 int i = 0; 927 uint16_t hciversion; 928 uint8_t caplength; 929 930 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 931 932 /* Set up the bus struct for the usb 3 and usb 2 buses */ 933 sc->sc_bus.ub_methods = &xhci_bus_methods; 934 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 935 sc->sc_bus.ub_usedma = true; 936 sc->sc_bus.ub_hcpriv = sc; 937 938 sc->sc_bus2.ub_methods = &xhci_bus_methods; 939 sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe); 940 sc->sc_bus2.ub_revision = USBREV_2_0; 941 sc->sc_bus2.ub_usedma = true; 942 sc->sc_bus2.ub_hcpriv = sc; 943 sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag; 944 945 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 946 caplength = XHCI_CAP_CAPLENGTH(cap); 947 hciversion = XHCI_CAP_HCIVERSION(cap); 948 949 if (hciversion < XHCI_HCIVERSION_0_96 || 950 hciversion >= 0x0200) { 951 aprint_normal_dev(sc->sc_dev, 952 "xHCI version %x.%x not known to be supported\n", 953 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 954 } else { 955 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 956 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 957 } 958 959 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 960 &sc->sc_cbh) != 0) { 961 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 962 return ENOMEM; 963 } 964 965 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 966 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 967 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 968 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 969 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 970 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 971 aprint_debug_dev(sc->sc_dev, 972 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 973 974 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 975 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 976 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 977 978 char sbuf[128]; 979 if (hciversion < XHCI_HCIVERSION_1_0) 980 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 981 else 982 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 983 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 984 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 985 if (hciversion >= XHCI_HCIVERSION_1_1) { 986 hcc2 = xhci_cap_read_4(sc, XHCI_HCCPARAMS2); 987 snprintb(sbuf, sizeof(sbuf), XHCI_HCC2_BITS, hcc2); 988 aprint_debug_dev(sc->sc_dev, "hcc2=%s\n", sbuf); 989 } 990 991 /* default all ports to bus 0, i.e. usb 3 */ 992 sc->sc_ctlrportbus = kmem_zalloc( 993 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP); 994 sc->sc_ctlrportmap = 995 kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 996 997 /* controller port to bus roothub port map */ 998 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 999 sc->sc_rhportmap[j] = 1000 kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 1001 } 1002 1003 /* 1004 * Process all Extended Capabilities 1005 */ 1006 xhci_ecp(sc, hcc); 1007 1008 bsz = XHCI_PORTSC(sc->sc_maxports); 1009 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 1010 &sc->sc_obh) != 0) { 1011 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 1012 return ENOMEM; 1013 } 1014 1015 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 1016 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 1017 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 1018 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 1019 return ENOMEM; 1020 } 1021 1022 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 1023 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 1024 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 1025 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 1026 return ENOMEM; 1027 } 1028 1029 int rv; 1030 rv = xhci_hc_reset(sc); 1031 if (rv != 0) { 1032 return rv; 1033 } 1034 1035 if (sc->sc_vendor_init) 1036 sc->sc_vendor_init(sc); 1037 1038 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 1039 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 1040 pagesize = ffs(pagesize); 1041 if (pagesize == 0) { 1042 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 1043 return EIO; 1044 } 1045 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 1046 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 1047 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 1048 (uint32_t)sc->sc_maxslots); 1049 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 1050 1051 usbd_status err; 1052 1053 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 1054 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 1055 if (sc->sc_maxspbuf != 0) { 1056 err = usb_allocmem(&sc->sc_bus, 1057 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 1058 &sc->sc_spbufarray_dma); 1059 if (err) { 1060 aprint_error_dev(sc->sc_dev, 1061 "spbufarray init fail, err %d\n", err); 1062 return ENOMEM; 1063 } 1064 1065 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 1066 sc->sc_maxspbuf, KM_SLEEP); 1067 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 1068 for (i = 0; i < sc->sc_maxspbuf; i++) { 1069 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 1070 /* allocate contexts */ 1071 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 1072 sc->sc_pgsz, dma); 1073 if (err) { 1074 aprint_error_dev(sc->sc_dev, 1075 "spbufarray_dma init fail, err %d\n", err); 1076 rv = ENOMEM; 1077 goto bad1; 1078 } 1079 spbufarray[i] = htole64(DMAADDR(dma, 0)); 1080 usb_syncmem(dma, 0, sc->sc_pgsz, 1081 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1082 } 1083 1084 usb_syncmem(&sc->sc_spbufarray_dma, 0, 1085 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 1086 } 1087 1088 config = xhci_op_read_4(sc, XHCI_CONFIG); 1089 config &= ~0xFF; 1090 config |= sc->sc_maxslots & 0xFF; 1091 xhci_op_write_4(sc, XHCI_CONFIG, config); 1092 1093 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 1094 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 1095 if (err) { 1096 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 1097 err); 1098 rv = ENOMEM; 1099 goto bad1; 1100 } 1101 1102 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 1103 XHCI_EVENT_RING_SEGMENTS_ALIGN); 1104 if (err) { 1105 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 1106 err); 1107 rv = ENOMEM; 1108 goto bad2; 1109 } 1110 1111 usb_dma_t *dma; 1112 size_t size; 1113 size_t align; 1114 1115 dma = &sc->sc_eventst_dma; 1116 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 1117 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 1118 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 1119 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 1120 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1121 if (err) { 1122 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 1123 err); 1124 rv = ENOMEM; 1125 goto bad3; 1126 } 1127 1128 memset(KERNADDR(dma, 0), 0, size); 1129 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1130 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 1131 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 1132 KERNADDR(&sc->sc_eventst_dma, 0), 1133 sc->sc_eventst_dma.udma_block->size); 1134 1135 dma = &sc->sc_dcbaa_dma; 1136 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 1137 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 1138 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 1139 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1140 if (err) { 1141 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1142 rv = ENOMEM; 1143 goto bad4; 1144 } 1145 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 1146 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1147 KERNADDR(&sc->sc_dcbaa_dma, 0), 1148 sc->sc_dcbaa_dma.udma_block->size); 1149 1150 memset(KERNADDR(dma, 0), 0, size); 1151 if (sc->sc_maxspbuf != 0) { 1152 /* 1153 * DCBA entry 0 hold the scratchbuf array pointer. 1154 */ 1155 *(uint64_t *)KERNADDR(dma, 0) = 1156 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1157 } 1158 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1159 1160 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1161 KM_SLEEP); 1162 if (sc->sc_slots == NULL) { 1163 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1164 rv = ENOMEM; 1165 goto bad; 1166 } 1167 1168 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1169 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1170 if (sc->sc_xferpool == NULL) { 1171 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1172 err); 1173 rv = ENOMEM; 1174 goto bad; 1175 } 1176 1177 cv_init(&sc->sc_command_cv, "xhcicmd"); 1178 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1179 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1180 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1181 1182 struct xhci_erste *erst; 1183 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1184 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1185 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1186 erst[0].erste_3 = htole32(0); 1187 usb_syncmem(&sc->sc_eventst_dma, 0, 1188 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1189 1190 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1191 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1192 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1193 XHCI_ERDP_LO_BUSY); 1194 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1195 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1196 sc->sc_cr.xr_cs); 1197 1198 #if 0 1199 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1200 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1201 #endif 1202 1203 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1204 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1205 /* Intel xhci needs interrupt rate moderated. */ 1206 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1207 else 1208 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1209 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 1210 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1211 1212 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 1213 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1214 xhci_op_read_4(sc, XHCI_USBCMD)); 1215 1216 return 0; 1217 1218 bad: 1219 if (sc->sc_xferpool) { 1220 pool_cache_destroy(sc->sc_xferpool); 1221 sc->sc_xferpool = NULL; 1222 } 1223 1224 if (sc->sc_slots) { 1225 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1226 sc->sc_maxslots); 1227 sc->sc_slots = NULL; 1228 } 1229 1230 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1231 bad4: 1232 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1233 bad3: 1234 xhci_ring_free(sc, &sc->sc_er); 1235 bad2: 1236 xhci_ring_free(sc, &sc->sc_cr); 1237 i = sc->sc_maxspbuf; 1238 bad1: 1239 for (int j = 0; j < i; j++) 1240 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1241 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1242 1243 return rv; 1244 } 1245 1246 static inline bool 1247 xhci_polling_p(struct xhci_softc * const sc) 1248 { 1249 return sc->sc_bus.ub_usepolling || sc->sc_bus2.ub_usepolling; 1250 } 1251 1252 int 1253 xhci_intr(void *v) 1254 { 1255 struct xhci_softc * const sc = v; 1256 int ret = 0; 1257 1258 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1259 1260 if (sc == NULL) 1261 return 0; 1262 1263 mutex_spin_enter(&sc->sc_intr_lock); 1264 1265 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1266 goto done; 1267 1268 /* If we get an interrupt while polling, then just ignore it. */ 1269 if (xhci_polling_p(sc)) { 1270 #ifdef DIAGNOSTIC 1271 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1272 #endif 1273 goto done; 1274 } 1275 1276 ret = xhci_intr1(sc); 1277 if (ret) { 1278 KASSERT(sc->sc_child || sc->sc_child2); 1279 1280 /* 1281 * One of child busses could be already detached. It doesn't 1282 * matter on which of the two the softintr is scheduled. 1283 */ 1284 if (sc->sc_child) 1285 usb_schedsoftintr(&sc->sc_bus); 1286 else 1287 usb_schedsoftintr(&sc->sc_bus2); 1288 } 1289 done: 1290 mutex_spin_exit(&sc->sc_intr_lock); 1291 return ret; 1292 } 1293 1294 int 1295 xhci_intr1(struct xhci_softc * const sc) 1296 { 1297 uint32_t usbsts; 1298 uint32_t iman; 1299 1300 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1301 1302 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1303 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1304 if ((usbsts & (XHCI_STS_HSE | XHCI_STS_EINT | XHCI_STS_PCD | 1305 XHCI_STS_HCE)) == 0) { 1306 DPRINTFN(16, "ignored intr not for %s", 1307 device_xname(sc->sc_dev), 0, 0, 0); 1308 return 0; 1309 } 1310 1311 /* 1312 * Clear EINT and other transient flags, to not misenterpret 1313 * next shared interrupt. Also, to avoid race, EINT must be cleared 1314 * before XHCI_IMAN_INTR_PEND is cleared. 1315 */ 1316 xhci_op_write_4(sc, XHCI_USBSTS, usbsts & XHCI_STS_RSVDP0); 1317 1318 #ifdef XHCI_DEBUG 1319 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1320 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1321 #endif 1322 1323 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1324 DPRINTFN(16, "IMAN0 %08jx", iman, 0, 0, 0); 1325 iman |= XHCI_IMAN_INTR_PEND; 1326 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1327 1328 #ifdef XHCI_DEBUG 1329 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1330 DPRINTFN(16, "IMAN0 %08jx", iman, 0, 0, 0); 1331 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1332 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1333 #endif 1334 1335 return 1; 1336 } 1337 1338 /* 1339 * 3 port speed types used in USB stack 1340 * 1341 * usbdi speed 1342 * definition: USB_SPEED_* in usb.h 1343 * They are used in struct usbd_device in USB stack. 1344 * ioctl interface uses these values too. 1345 * port_status speed 1346 * definition: UPS_*_SPEED in usb.h 1347 * They are used in usb_port_status_t and valid only for USB 2.0. 1348 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1349 * of usb_port_status_ext_t indicates port speed. 1350 * Note that some 3.0 values overlap with 2.0 values. 1351 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1352 * means UPS_LOW_SPEED in HS.) 1353 * port status returned from hub also uses these values. 1354 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1355 * or more. 1356 * xspeed: 1357 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1358 * They are used in only slot context and PORTSC reg of xhci. 1359 * The difference between usbdi speed and xspeed is 1360 * that FS and LS values are swapped. 1361 */ 1362 1363 /* convert usbdi speed to xspeed */ 1364 static int 1365 xhci_speed2xspeed(int speed) 1366 { 1367 switch (speed) { 1368 case USB_SPEED_LOW: return 2; 1369 case USB_SPEED_FULL: return 1; 1370 default: return speed; 1371 } 1372 } 1373 1374 #if 0 1375 /* convert xspeed to usbdi speed */ 1376 static int 1377 xhci_xspeed2speed(int xspeed) 1378 { 1379 switch (xspeed) { 1380 case 1: return USB_SPEED_FULL; 1381 case 2: return USB_SPEED_LOW; 1382 default: return xspeed; 1383 } 1384 } 1385 #endif 1386 1387 /* convert xspeed to port status speed */ 1388 static int 1389 xhci_xspeed2psspeed(int xspeed) 1390 { 1391 switch (xspeed) { 1392 case 0: return 0; 1393 case 1: return UPS_FULL_SPEED; 1394 case 2: return UPS_LOW_SPEED; 1395 case 3: return UPS_HIGH_SPEED; 1396 default: return UPS_OTHER_SPEED; 1397 } 1398 } 1399 1400 /* 1401 * Construct input contexts and issue TRB to open pipe. 1402 */ 1403 static usbd_status 1404 xhci_configure_endpoint(struct usbd_pipe *pipe) 1405 { 1406 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1407 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1408 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1409 struct xhci_trb trb; 1410 usbd_status err; 1411 1412 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1413 DPRINTFN(4, "slot %ju dci %ju epaddr 0x%02jx attr 0x%02jx", 1414 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1415 pipe->up_endpoint->ue_edesc->bmAttributes); 1416 1417 /* XXX ensure input context is available? */ 1418 1419 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1420 1421 /* set up context */ 1422 xhci_setup_ctx(pipe); 1423 1424 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1425 sc->sc_ctxsz * 1); 1426 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1427 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1428 1429 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1430 trb.trb_2 = 0; 1431 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1432 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1433 1434 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1435 1436 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1437 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1438 sc->sc_ctxsz * 1); 1439 1440 return err; 1441 } 1442 1443 #if 0 1444 static usbd_status 1445 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1446 { 1447 #ifdef USB_DEBUG 1448 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1449 #endif 1450 1451 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1452 DPRINTFN(4, "slot %ju", xs->xs_idx, 0, 0, 0); 1453 1454 return USBD_NORMAL_COMPLETION; 1455 } 1456 #endif 1457 1458 /* 4.6.8, 6.4.3.7 */ 1459 static usbd_status 1460 xhci_reset_endpoint_locked(struct usbd_pipe *pipe) 1461 { 1462 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1463 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1464 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1465 struct xhci_trb trb; 1466 usbd_status err; 1467 1468 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1469 DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1470 1471 KASSERT(mutex_owned(&sc->sc_lock)); 1472 1473 trb.trb_0 = 0; 1474 trb.trb_2 = 0; 1475 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1476 XHCI_TRB_3_EP_SET(dci) | 1477 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1478 1479 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1480 1481 return err; 1482 } 1483 1484 static usbd_status 1485 xhci_reset_endpoint(struct usbd_pipe *pipe) 1486 { 1487 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1488 1489 mutex_enter(&sc->sc_lock); 1490 usbd_status ret = xhci_reset_endpoint_locked(pipe); 1491 mutex_exit(&sc->sc_lock); 1492 1493 return ret; 1494 } 1495 1496 /* 1497 * 4.6.9, 6.4.3.8 1498 * Stop execution of TDs on xfer ring. 1499 * Should be called with sc_lock held. 1500 */ 1501 static usbd_status 1502 xhci_stop_endpoint(struct usbd_pipe *pipe) 1503 { 1504 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1505 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1506 struct xhci_trb trb; 1507 usbd_status err; 1508 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1509 1510 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1511 DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1512 1513 KASSERT(mutex_owned(&sc->sc_lock)); 1514 1515 trb.trb_0 = 0; 1516 trb.trb_2 = 0; 1517 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1518 XHCI_TRB_3_EP_SET(dci) | 1519 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1520 1521 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1522 1523 return err; 1524 } 1525 1526 /* 1527 * Set TR Dequeue Pointer. 1528 * xHCI 1.1 4.6.10 6.4.3.9 1529 * Purge all of the TRBs on ring and reinitialize ring. 1530 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1531 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1532 * error will be generated. 1533 */ 1534 static usbd_status 1535 xhci_set_dequeue_locked(struct usbd_pipe *pipe) 1536 { 1537 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1538 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1539 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1540 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1541 struct xhci_trb trb; 1542 usbd_status err; 1543 1544 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1545 DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1546 1547 KASSERT(mutex_owned(&sc->sc_lock)); 1548 1549 xhci_host_dequeue(xr); 1550 1551 /* set DCS */ 1552 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1553 trb.trb_2 = 0; 1554 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1555 XHCI_TRB_3_EP_SET(dci) | 1556 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1557 1558 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1559 1560 return err; 1561 } 1562 1563 static usbd_status 1564 xhci_set_dequeue(struct usbd_pipe *pipe) 1565 { 1566 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1567 1568 mutex_enter(&sc->sc_lock); 1569 usbd_status ret = xhci_set_dequeue_locked(pipe); 1570 mutex_exit(&sc->sc_lock); 1571 1572 return ret; 1573 } 1574 1575 /* 1576 * Open new pipe: called from usbd_setup_pipe_flags. 1577 * Fills methods of pipe. 1578 * If pipe is not for ep0, calls configure_endpoint. 1579 */ 1580 static usbd_status 1581 xhci_open(struct usbd_pipe *pipe) 1582 { 1583 struct usbd_device * const dev = pipe->up_dev; 1584 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1585 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1586 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1587 1588 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1589 DPRINTFN(1, "addr %jd depth %jd port %jd speed %jd", dev->ud_addr, 1590 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1591 DPRINTFN(1, " dci %ju type 0x%02jx epaddr 0x%02jx attr 0x%02jx", 1592 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1593 ed->bmAttributes); 1594 DPRINTFN(1, " mps %ju ival %ju", UGETW(ed->wMaxPacketSize), 1595 ed->bInterval, 0, 0); 1596 1597 if (sc->sc_dying) 1598 return USBD_IOERROR; 1599 1600 /* Root Hub */ 1601 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1602 switch (ed->bEndpointAddress) { 1603 case USB_CONTROL_ENDPOINT: 1604 pipe->up_methods = &roothub_ctrl_methods; 1605 break; 1606 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1607 pipe->up_methods = &xhci_root_intr_methods; 1608 break; 1609 default: 1610 pipe->up_methods = NULL; 1611 DPRINTFN(0, "bad bEndpointAddress 0x%02jx", 1612 ed->bEndpointAddress, 0, 0, 0); 1613 return USBD_INVAL; 1614 } 1615 return USBD_NORMAL_COMPLETION; 1616 } 1617 1618 switch (xfertype) { 1619 case UE_CONTROL: 1620 pipe->up_methods = &xhci_device_ctrl_methods; 1621 break; 1622 case UE_ISOCHRONOUS: 1623 pipe->up_methods = &xhci_device_isoc_methods; 1624 return USBD_INVAL; 1625 break; 1626 case UE_BULK: 1627 pipe->up_methods = &xhci_device_bulk_methods; 1628 break; 1629 case UE_INTERRUPT: 1630 pipe->up_methods = &xhci_device_intr_methods; 1631 break; 1632 default: 1633 return USBD_IOERROR; 1634 break; 1635 } 1636 1637 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1638 return xhci_configure_endpoint(pipe); 1639 1640 return USBD_NORMAL_COMPLETION; 1641 } 1642 1643 /* 1644 * Closes pipe, called from usbd_kill_pipe via close methods. 1645 * If the endpoint to be closed is ep0, disable_slot. 1646 * Should be called with sc_lock held. 1647 */ 1648 static void 1649 xhci_close_pipe(struct usbd_pipe *pipe) 1650 { 1651 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1652 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1653 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1654 const u_int dci = xhci_ep_get_dci(ed); 1655 struct xhci_trb trb; 1656 uint32_t *cp; 1657 1658 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1659 1660 if (sc->sc_dying) 1661 return; 1662 1663 /* xs is uninitialized before xhci_init_slot */ 1664 if (xs == NULL || xs->xs_idx == 0) 1665 return; 1666 1667 DPRINTFN(4, "pipe %#jx slot %ju dci %ju", (uintptr_t)pipe, xs->xs_idx, 1668 dci, 0); 1669 1670 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1671 KASSERT(mutex_owned(&sc->sc_lock)); 1672 1673 if (pipe->up_dev->ud_depth == 0) 1674 return; 1675 1676 if (dci == XHCI_DCI_EP_CONTROL) { 1677 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1678 xhci_disable_slot(sc, xs->xs_idx); 1679 return; 1680 } 1681 1682 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED) 1683 (void)xhci_stop_endpoint(pipe); 1684 1685 /* 1686 * set appropriate bit to be dropped. 1687 * don't set DC bit to 1, otherwise all endpoints 1688 * would be deconfigured. 1689 */ 1690 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1691 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1692 cp[1] = htole32(0); 1693 1694 /* XXX should be most significant one, not dci? */ 1695 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1696 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1697 1698 /* configure ep context performs an implicit dequeue */ 1699 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 1700 1701 /* sync input contexts before they are read from memory */ 1702 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1703 1704 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1705 trb.trb_2 = 0; 1706 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1707 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1708 1709 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1710 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1711 } 1712 1713 /* 1714 * Abort transfer. 1715 * Should be called with sc_lock held. 1716 */ 1717 static void 1718 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1719 { 1720 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1721 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1722 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1723 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1724 1725 KASSERTMSG((status == USBD_CANCELLED || status == USBD_TIMEOUT), 1726 "invalid status for abort: %d", (int)status); 1727 1728 DPRINTFN(4, "xfer %#jx pipe %#jx status %jd", 1729 (uintptr_t)xfer, (uintptr_t)xfer->ux_pipe, status, 0); 1730 1731 KASSERT(mutex_owned(&sc->sc_lock)); 1732 ASSERT_SLEEPABLE(); 1733 1734 if (status == USBD_CANCELLED) { 1735 /* 1736 * We are synchronously aborting. Try to stop the 1737 * callout and task, but if we can't, wait for them to 1738 * complete. 1739 */ 1740 callout_halt(&xfer->ux_callout, &sc->sc_lock); 1741 usb_rem_task_wait(xfer->ux_pipe->up_dev, &xfer->ux_aborttask, 1742 USB_TASKQ_HC, &sc->sc_lock); 1743 } else { 1744 /* Otherwise, we are timing out. */ 1745 KASSERT(status == USBD_TIMEOUT); 1746 } 1747 1748 /* 1749 * The xfer cannot have been cancelled already. It is the 1750 * responsibility of the caller of usbd_abort_pipe not to try 1751 * to abort a pipe multiple times, whether concurrently or 1752 * sequentially. 1753 */ 1754 KASSERT(xfer->ux_status != USBD_CANCELLED); 1755 1756 /* Only the timeout, which runs only once, can time it out. */ 1757 KASSERT(xfer->ux_status != USBD_TIMEOUT); 1758 1759 /* If anyone else beat us, we're done. */ 1760 if (xfer->ux_status != USBD_IN_PROGRESS) 1761 return; 1762 1763 /* We beat everyone else. Claim the status. */ 1764 xfer->ux_status = status; 1765 1766 /* 1767 * If we're dying, skip the hardware action and just notify the 1768 * software that we're done. 1769 */ 1770 if (sc->sc_dying) { 1771 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 1772 xfer->ux_status, 0, 0); 1773 goto dying; 1774 } 1775 1776 /* 1777 * HC Step 1: Stop execution of TD on the ring. 1778 */ 1779 switch (xhci_get_epstate(sc, xs, dci)) { 1780 case XHCI_EPSTATE_HALTED: 1781 (void)xhci_reset_endpoint_locked(xfer->ux_pipe); 1782 break; 1783 case XHCI_EPSTATE_STOPPED: 1784 break; 1785 default: 1786 (void)xhci_stop_endpoint(xfer->ux_pipe); 1787 break; 1788 } 1789 #ifdef DIAGNOSTIC 1790 uint32_t epst = xhci_get_epstate(sc, xs, dci); 1791 if (epst != XHCI_EPSTATE_STOPPED) 1792 DPRINTFN(4, "dci %ju not stopped %ju", dci, epst, 0, 0); 1793 #endif 1794 1795 /* 1796 * HC Step 2: Remove any vestiges of the xfer from the ring. 1797 */ 1798 xhci_set_dequeue_locked(xfer->ux_pipe); 1799 1800 /* 1801 * Final Step: Notify completion to waiting xfers. 1802 */ 1803 dying: 1804 usb_transfer_complete(xfer); 1805 DPRINTFN(14, "end", 0, 0, 0, 0); 1806 1807 KASSERT(mutex_owned(&sc->sc_lock)); 1808 } 1809 1810 static void 1811 xhci_host_dequeue(struct xhci_ring * const xr) 1812 { 1813 /* When dequeueing the controller, update our struct copy too */ 1814 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1815 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1816 BUS_DMASYNC_PREWRITE); 1817 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1818 1819 xr->xr_ep = 0; 1820 xr->xr_cs = 1; 1821 } 1822 1823 /* 1824 * Recover STALLed endpoint. 1825 * xHCI 1.1 sect 4.10.2.1 1826 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1827 * all transfers on transfer ring. 1828 * These are done in thread context asynchronously. 1829 */ 1830 static void 1831 xhci_clear_endpoint_stall_async_task(void *cookie) 1832 { 1833 struct usbd_xfer * const xfer = cookie; 1834 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1835 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1836 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1837 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1838 1839 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1840 DPRINTFN(4, "xfer %#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, 1841 dci, 0); 1842 1843 xhci_reset_endpoint(xfer->ux_pipe); 1844 xhci_set_dequeue(xfer->ux_pipe); 1845 1846 mutex_enter(&sc->sc_lock); 1847 tr->is_halted = false; 1848 usb_transfer_complete(xfer); 1849 mutex_exit(&sc->sc_lock); 1850 DPRINTFN(4, "ends", 0, 0, 0, 0); 1851 } 1852 1853 static usbd_status 1854 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1855 { 1856 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1857 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1858 1859 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1860 DPRINTFN(4, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 1861 1862 if (sc->sc_dying) { 1863 return USBD_IOERROR; 1864 } 1865 1866 usb_init_task(&xp->xp_async_task, 1867 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1868 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1869 DPRINTFN(4, "ends", 0, 0, 0, 0); 1870 1871 return USBD_NORMAL_COMPLETION; 1872 } 1873 1874 /* Process roothub port status/change events and notify to uhub_intr. */ 1875 static void 1876 xhci_rhpsc(struct xhci_softc * const sc, u_int ctlrport) 1877 { 1878 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1879 DPRINTFN(4, "xhci%jd: port %ju status change", device_unit(sc->sc_dev), 1880 ctlrport, 0, 0); 1881 1882 if (ctlrport > sc->sc_maxports) 1883 return; 1884 1885 const size_t bn = xhci_ctlrport2bus(sc, ctlrport); 1886 const size_t rhp = xhci_ctlrport2rhport(sc, ctlrport); 1887 struct usbd_xfer * const xfer = sc->sc_intrxfer[bn]; 1888 1889 DPRINTFN(4, "xhci%jd: bus %jd bp %ju xfer %#jx status change", 1890 device_unit(sc->sc_dev), bn, rhp, (uintptr_t)xfer); 1891 1892 if (xfer == NULL) 1893 return; 1894 1895 uint8_t *p = xfer->ux_buf; 1896 memset(p, 0, xfer->ux_length); 1897 p[rhp / NBBY] |= 1 << (rhp % NBBY); 1898 xfer->ux_actlen = xfer->ux_length; 1899 xfer->ux_status = USBD_NORMAL_COMPLETION; 1900 usb_transfer_complete(xfer); 1901 } 1902 1903 /* Process Transfer Events */ 1904 static void 1905 xhci_event_transfer(struct xhci_softc * const sc, 1906 const struct xhci_trb * const trb) 1907 { 1908 uint64_t trb_0; 1909 uint32_t trb_2, trb_3; 1910 uint8_t trbcode; 1911 u_int slot, dci; 1912 struct xhci_slot *xs; 1913 struct xhci_ring *xr; 1914 struct xhci_xfer *xx; 1915 struct usbd_xfer *xfer; 1916 usbd_status err; 1917 1918 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1919 1920 trb_0 = le64toh(trb->trb_0); 1921 trb_2 = le32toh(trb->trb_2); 1922 trb_3 = le32toh(trb->trb_3); 1923 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1924 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1925 dci = XHCI_TRB_3_EP_GET(trb_3); 1926 xs = &sc->sc_slots[slot]; 1927 xr = &xs->xs_ep[dci].xe_tr; 1928 1929 /* sanity check */ 1930 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1931 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1932 1933 int idx = 0; 1934 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1935 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1936 DPRINTFN(0, "invalid trb_0 0x%jx", trb_0, 0, 0, 0); 1937 return; 1938 } 1939 xx = xr->xr_cookies[idx]; 1940 1941 /* clear cookie of consumed TRB */ 1942 xr->xr_cookies[idx] = NULL; 1943 1944 /* 1945 * xx is NULL if pipe is opened but xfer is not started. 1946 * It happens when stopping idle pipe. 1947 */ 1948 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1949 DPRINTFN(1, "Ignore #%ju: cookie %#jx cc %ju dci %ju", 1950 idx, (uintptr_t)xx, trbcode, dci); 1951 DPRINTFN(1, " orig TRB %jx type %ju", trb_0, 1952 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1953 0, 0); 1954 return; 1955 } 1956 } else { 1957 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1958 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1959 } 1960 /* XXX this may not happen */ 1961 if (xx == NULL) { 1962 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1963 return; 1964 } 1965 xfer = &xx->xx_xfer; 1966 /* XXX this may happen when detaching */ 1967 if (xfer == NULL) { 1968 DPRINTFN(1, "xx(%#jx)->xx_xfer is NULL trb_0 %#jx", 1969 (uintptr_t)xx, trb_0, 0, 0); 1970 return; 1971 } 1972 DPRINTFN(14, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 1973 /* XXX I dunno why this happens */ 1974 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1975 1976 if (!xfer->ux_pipe->up_repeat && 1977 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1978 DPRINTFN(1, "xfer(%#jx)->pipe not queued", (uintptr_t)xfer, 1979 0, 0, 0); 1980 return; 1981 } 1982 1983 /* 4.11.5.2 Event Data TRB */ 1984 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1985 DPRINTFN(14, "transfer Event Data: 0x%016jx 0x%08jx" 1986 " %02jx", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1987 if ((trb_0 & 0x3) == 0x3) { 1988 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1989 } 1990 } 1991 1992 switch (trbcode) { 1993 case XHCI_TRB_ERROR_SHORT_PKT: 1994 case XHCI_TRB_ERROR_SUCCESS: 1995 /* 1996 * A ctrl transfer can generate two events if it has a Data 1997 * stage. A short data stage can be OK and should not 1998 * complete the transfer as the status stage needs to be 1999 * performed. 2000 * 2001 * Note: Data and Status stage events point at same xfer. 2002 * ux_actlen and ux_dmabuf will be passed to 2003 * usb_transfer_complete after the Status stage event. 2004 * 2005 * It can be distingished which stage generates the event: 2006 * + by checking least 3 bits of trb_0 if ED==1. 2007 * (see xhci_device_ctrl_start). 2008 * + by checking the type of original TRB if ED==0. 2009 * 2010 * In addition, intr, bulk, and isoc transfer currently 2011 * consists of single TD, so the "skip" is not needed. 2012 * ctrl xfer uses EVENT_DATA, and others do not. 2013 * Thus driver can switch the flow by checking ED bit. 2014 */ 2015 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 2016 if (xfer->ux_actlen == 0) 2017 xfer->ux_actlen = xfer->ux_length - 2018 XHCI_TRB_2_REM_GET(trb_2); 2019 if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)) 2020 == XHCI_TRB_TYPE_DATA_STAGE) { 2021 return; 2022 } 2023 } else if ((trb_0 & 0x3) == 0x3) { 2024 return; 2025 } 2026 err = USBD_NORMAL_COMPLETION; 2027 break; 2028 case XHCI_TRB_ERROR_STOPPED: 2029 case XHCI_TRB_ERROR_LENGTH: 2030 case XHCI_TRB_ERROR_STOPPED_SHORT: 2031 /* 2032 * don't complete the transfer being aborted 2033 * as abort_xfer does instead. 2034 */ 2035 if (xfer->ux_status == USBD_CANCELLED || 2036 xfer->ux_status == USBD_TIMEOUT) { 2037 DPRINTFN(14, "ignore aborting xfer %#jx", 2038 (uintptr_t)xfer, 0, 0, 0); 2039 return; 2040 } 2041 err = USBD_CANCELLED; 2042 break; 2043 case XHCI_TRB_ERROR_STALL: 2044 case XHCI_TRB_ERROR_BABBLE: 2045 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 2046 xr->is_halted = true; 2047 /* 2048 * Stalled endpoints can be recoverd by issuing 2049 * command TRB TYPE_RESET_EP on xHCI instead of 2050 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 2051 * on the endpoint. However, this function may be 2052 * called from softint context (e.g. from umass), 2053 * in that case driver gets KASSERT in cv_timedwait 2054 * in xhci_do_command. 2055 * To avoid this, this runs reset_endpoint and 2056 * usb_transfer_complete in usb task thread 2057 * asynchronously (and then umass issues clear 2058 * UF_ENDPOINT_HALT). 2059 */ 2060 2061 /* Override the status. */ 2062 xfer->ux_status = USBD_STALLED; 2063 2064 /* 2065 * Cancel the timeout and the task, which have not yet 2066 * run. If they have already fired, at worst they are 2067 * waiting for the lock. They will see that the xfer 2068 * is no longer in progress and give up. 2069 */ 2070 callout_stop(&xfer->ux_callout); 2071 usb_rem_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask); 2072 2073 xhci_clear_endpoint_stall_async(xfer); 2074 return; 2075 default: 2076 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 2077 err = USBD_IOERROR; 2078 break; 2079 } 2080 2081 /* 2082 * If software has completed it, either by cancellation 2083 * or timeout, drop it on the floor. 2084 */ 2085 if (xfer->ux_status != USBD_IN_PROGRESS) { 2086 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 2087 xfer->ux_status == USBD_TIMEOUT), 2088 "xfer %p status %x", xfer, xfer->ux_status); 2089 return;; 2090 } 2091 2092 /* Otherwise, set the status. */ 2093 xfer->ux_status = err; 2094 2095 /* 2096 * Cancel the timeout and the task, which have not yet 2097 * run. If they have already fired, at worst they are 2098 * waiting for the lock. They will see that the xfer 2099 * is no longer in progress and give up. 2100 */ 2101 callout_stop(&xfer->ux_callout); 2102 usb_rem_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask); 2103 2104 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0 || 2105 (trb_0 & 0x3) == 0x0) { 2106 usb_transfer_complete(xfer); 2107 } 2108 } 2109 2110 /* Process Command complete events */ 2111 static void 2112 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 2113 { 2114 uint64_t trb_0; 2115 uint32_t trb_2, trb_3; 2116 2117 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2118 2119 KASSERT(mutex_owned(&sc->sc_lock)); 2120 2121 trb_0 = le64toh(trb->trb_0); 2122 trb_2 = le32toh(trb->trb_2); 2123 trb_3 = le32toh(trb->trb_3); 2124 2125 if (trb_0 == sc->sc_command_addr) { 2126 sc->sc_resultpending = false; 2127 2128 sc->sc_result_trb.trb_0 = trb_0; 2129 sc->sc_result_trb.trb_2 = trb_2; 2130 sc->sc_result_trb.trb_3 = trb_3; 2131 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2132 XHCI_TRB_ERROR_SUCCESS) { 2133 DPRINTFN(1, "command completion " 2134 "failure: 0x%016jx 0x%08jx 0x%08jx", 2135 trb_0, trb_2, trb_3, 0); 2136 } 2137 cv_signal(&sc->sc_command_cv); 2138 } else { 2139 DPRINTFN(1, "spurious event: %#jx 0x%016jx " 2140 "0x%08jx 0x%08jx", (uintptr_t)trb, trb_0, trb_2, trb_3); 2141 } 2142 } 2143 2144 /* 2145 * Process events. 2146 * called from xhci_softintr 2147 */ 2148 static void 2149 xhci_handle_event(struct xhci_softc * const sc, 2150 const struct xhci_trb * const trb) 2151 { 2152 uint64_t trb_0; 2153 uint32_t trb_2, trb_3; 2154 2155 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2156 2157 trb_0 = le64toh(trb->trb_0); 2158 trb_2 = le32toh(trb->trb_2); 2159 trb_3 = le32toh(trb->trb_3); 2160 2161 DPRINTFN(14, "event: %#jx 0x%016jx 0x%08jx 0x%08jx", 2162 (uintptr_t)trb, trb_0, trb_2, trb_3); 2163 2164 /* 2165 * 4.11.3.1, 6.4.2.1 2166 * TRB Pointer is invalid for these completion codes. 2167 */ 2168 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2169 case XHCI_TRB_ERROR_RING_UNDERRUN: 2170 case XHCI_TRB_ERROR_RING_OVERRUN: 2171 case XHCI_TRB_ERROR_VF_RING_FULL: 2172 return; 2173 default: 2174 if (trb_0 == 0) { 2175 return; 2176 } 2177 break; 2178 } 2179 2180 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2181 case XHCI_TRB_EVENT_TRANSFER: 2182 xhci_event_transfer(sc, trb); 2183 break; 2184 case XHCI_TRB_EVENT_CMD_COMPLETE: 2185 xhci_event_cmd(sc, trb); 2186 break; 2187 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2188 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2189 break; 2190 default: 2191 break; 2192 } 2193 } 2194 2195 static void 2196 xhci_softintr(void *v) 2197 { 2198 struct usbd_bus * const bus = v; 2199 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2200 struct xhci_ring * const er = &sc->sc_er; 2201 struct xhci_trb *trb; 2202 int i, j, k; 2203 2204 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2205 2206 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 2207 2208 i = er->xr_ep; 2209 j = er->xr_cs; 2210 2211 DPRINTFN(16, "er: xr_ep %jd xr_cs %jd", i, j, 0, 0); 2212 2213 while (1) { 2214 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2215 BUS_DMASYNC_POSTREAD); 2216 trb = &er->xr_trb[i]; 2217 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2218 2219 if (j != k) 2220 break; 2221 2222 xhci_handle_event(sc, trb); 2223 2224 i++; 2225 if (i == er->xr_ntrb) { 2226 i = 0; 2227 j ^= 1; 2228 } 2229 } 2230 2231 er->xr_ep = i; 2232 er->xr_cs = j; 2233 2234 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2235 XHCI_ERDP_LO_BUSY); 2236 2237 DPRINTFN(16, "ends", 0, 0, 0, 0); 2238 2239 return; 2240 } 2241 2242 static void 2243 xhci_poll(struct usbd_bus *bus) 2244 { 2245 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2246 2247 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2248 2249 mutex_spin_enter(&sc->sc_intr_lock); 2250 int ret = xhci_intr1(sc); 2251 if (ret) { 2252 xhci_softintr(bus); 2253 } 2254 mutex_spin_exit(&sc->sc_intr_lock); 2255 2256 return; 2257 } 2258 2259 static struct usbd_xfer * 2260 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2261 { 2262 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2263 struct usbd_xfer *xfer; 2264 2265 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2266 2267 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 2268 if (xfer != NULL) { 2269 memset(xfer, 0, sizeof(struct xhci_xfer)); 2270 usb_init_task(&xfer->ux_aborttask, xhci_timeout_task, xfer, 2271 USB_TASKQ_MPSAFE); 2272 #ifdef DIAGNOSTIC 2273 xfer->ux_state = XFER_BUSY; 2274 #endif 2275 } 2276 2277 return xfer; 2278 } 2279 2280 static void 2281 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2282 { 2283 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2284 2285 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2286 2287 #ifdef DIAGNOSTIC 2288 if (xfer->ux_state != XFER_BUSY) { 2289 DPRINTFN(0, "xfer=%#jx not busy, 0x%08jx", 2290 (uintptr_t)xfer, xfer->ux_state, 0, 0); 2291 } 2292 xfer->ux_state = XFER_FREE; 2293 #endif 2294 pool_cache_put(sc->sc_xferpool, xfer); 2295 } 2296 2297 static void 2298 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2299 { 2300 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2301 2302 *lock = &sc->sc_lock; 2303 } 2304 2305 extern uint32_t usb_cookie_no; 2306 2307 /* 2308 * xHCI 4.3 2309 * Called when uhub_explore finds a new device (via usbd_new_device). 2310 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2311 * This function does: 2312 * Allocate and construct dev structure of default endpoint (ep0). 2313 * Allocate and open pipe of ep0. 2314 * Enable slot and initialize slot context. 2315 * Set Address. 2316 * Read initial device descriptor. 2317 * Determine initial MaxPacketSize (mps) by speed. 2318 * Read full device descriptor. 2319 * Register this device. 2320 * Finally state of device transitions ADDRESSED. 2321 */ 2322 static usbd_status 2323 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2324 int speed, int port, struct usbd_port *up) 2325 { 2326 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2327 struct usbd_device *dev; 2328 usbd_status err; 2329 usb_device_descriptor_t *dd; 2330 struct xhci_slot *xs; 2331 uint32_t *cp; 2332 2333 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2334 DPRINTFN(4, "port %ju depth %ju speed %ju up %#jx", 2335 port, depth, speed, (uintptr_t)up); 2336 2337 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2338 dev->ud_bus = bus; 2339 dev->ud_quirks = &usbd_no_quirk; 2340 dev->ud_addr = 0; 2341 dev->ud_ddesc.bMaxPacketSize = 0; 2342 dev->ud_depth = depth; 2343 dev->ud_powersrc = up; 2344 dev->ud_myhub = up->up_parent; 2345 dev->ud_speed = speed; 2346 dev->ud_langid = USBD_NOLANG; 2347 dev->ud_cookie.cookie = ++usb_cookie_no; 2348 2349 /* Set up default endpoint handle. */ 2350 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2351 /* doesn't matter, just don't let it uninitialized */ 2352 dev->ud_ep0.ue_toggle = 0; 2353 2354 /* Set up default endpoint descriptor. */ 2355 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2356 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2357 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2358 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2359 dev->ud_ep0desc.bInterval = 0; 2360 2361 /* 4.3, 4.8.2.1 */ 2362 switch (speed) { 2363 case USB_SPEED_SUPER: 2364 case USB_SPEED_SUPER_PLUS: 2365 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2366 break; 2367 case USB_SPEED_FULL: 2368 /* XXX using 64 as initial mps of ep0 in FS */ 2369 case USB_SPEED_HIGH: 2370 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2371 break; 2372 case USB_SPEED_LOW: 2373 default: 2374 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2375 break; 2376 } 2377 2378 up->up_dev = dev; 2379 2380 /* Establish the default pipe. */ 2381 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2382 &dev->ud_pipe0); 2383 if (err) { 2384 goto bad; 2385 } 2386 2387 dd = &dev->ud_ddesc; 2388 2389 if (depth == 0 && port == 0) { 2390 KASSERT(bus->ub_devices[USB_ROOTHUB_INDEX] == NULL); 2391 bus->ub_devices[USB_ROOTHUB_INDEX] = dev; 2392 err = usbd_get_initial_ddesc(dev, dd); 2393 if (err) { 2394 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2395 goto bad; 2396 } 2397 2398 err = usbd_reload_device_desc(dev); 2399 if (err) { 2400 DPRINTFN(1, "reload desc %ju", err, 0, 0, 0); 2401 goto bad; 2402 } 2403 } else { 2404 uint8_t slot = 0; 2405 2406 /* 4.3.2 */ 2407 err = xhci_enable_slot(sc, &slot); 2408 if (err) { 2409 DPRINTFN(1, "enable slot %ju", err, 0, 0, 0); 2410 goto bad; 2411 } 2412 2413 xs = &sc->sc_slots[slot]; 2414 dev->ud_hcpriv = xs; 2415 2416 /* 4.3.3 initialize slot structure */ 2417 err = xhci_init_slot(dev, slot); 2418 if (err) { 2419 DPRINTFN(1, "init slot %ju", err, 0, 0, 0); 2420 dev->ud_hcpriv = NULL; 2421 /* 2422 * We have to disable_slot here because 2423 * xs->xs_idx == 0 when xhci_init_slot fails, 2424 * in that case usbd_remove_dev won't work. 2425 */ 2426 mutex_enter(&sc->sc_lock); 2427 xhci_disable_slot(sc, slot); 2428 mutex_exit(&sc->sc_lock); 2429 goto bad; 2430 } 2431 2432 /* 4.3.4 Address Assignment */ 2433 err = xhci_set_address(dev, slot, false); 2434 if (err) { 2435 DPRINTFN(1, "set address w/o bsr %ju", err, 0, 0, 0); 2436 goto bad; 2437 } 2438 2439 /* Allow device time to set new address */ 2440 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2441 2442 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2443 //hexdump("slot context", cp, sc->sc_ctxsz); 2444 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3])); 2445 DPRINTFN(4, "device address %ju", addr, 0, 0, 0); 2446 /* 2447 * XXX ensure we know when the hardware does something 2448 * we can't yet cope with 2449 */ 2450 KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr); 2451 dev->ud_addr = addr; 2452 2453 KASSERTMSG(bus->ub_devices[usb_addr2dindex(dev->ud_addr)] == NULL, 2454 "addr %d already allocated", dev->ud_addr); 2455 /* 2456 * The root hub is given its own slot 2457 */ 2458 bus->ub_devices[usb_addr2dindex(dev->ud_addr)] = dev; 2459 2460 err = usbd_get_initial_ddesc(dev, dd); 2461 if (err) { 2462 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2463 goto bad; 2464 } 2465 2466 /* 4.8.2.1 */ 2467 if (USB_IS_SS(speed)) { 2468 if (dd->bMaxPacketSize != 9) { 2469 printf("%s: invalid mps 2^%u for SS ep0," 2470 " using 512\n", 2471 device_xname(sc->sc_dev), 2472 dd->bMaxPacketSize); 2473 dd->bMaxPacketSize = 9; 2474 } 2475 USETW(dev->ud_ep0desc.wMaxPacketSize, 2476 (1 << dd->bMaxPacketSize)); 2477 } else 2478 USETW(dev->ud_ep0desc.wMaxPacketSize, 2479 dd->bMaxPacketSize); 2480 DPRINTFN(4, "bMaxPacketSize %ju", dd->bMaxPacketSize, 0, 0, 0); 2481 err = xhci_update_ep0_mps(sc, xs, 2482 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2483 if (err) { 2484 DPRINTFN(1, "update mps of ep0 %ju", err, 0, 0, 0); 2485 goto bad; 2486 } 2487 2488 err = usbd_reload_device_desc(dev); 2489 if (err) { 2490 DPRINTFN(1, "reload desc %ju", err, 0, 0, 0); 2491 goto bad; 2492 } 2493 } 2494 2495 DPRINTFN(1, "adding unit addr=%jd, rev=%02jx,", 2496 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2497 DPRINTFN(1, " class=%jd, subclass=%jd, protocol=%jd,", 2498 dd->bDeviceClass, dd->bDeviceSubClass, 2499 dd->bDeviceProtocol, 0); 2500 DPRINTFN(1, " mps=%jd, len=%jd, noconf=%jd, speed=%jd", 2501 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2502 dev->ud_speed); 2503 2504 usbd_get_device_strings(dev); 2505 2506 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2507 2508 if (depth == 0 && port == 0) { 2509 usbd_attach_roothub(parent, dev); 2510 DPRINTFN(1, "root hub %#jx", (uintptr_t)dev, 0, 0, 0); 2511 return USBD_NORMAL_COMPLETION; 2512 } 2513 2514 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2515 bad: 2516 if (err != USBD_NORMAL_COMPLETION) { 2517 usbd_remove_device(dev, up); 2518 } 2519 2520 return err; 2521 } 2522 2523 static usbd_status 2524 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2525 size_t ntrb, size_t align) 2526 { 2527 usbd_status err; 2528 size_t size = ntrb * XHCI_TRB_SIZE; 2529 2530 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2531 2532 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2533 if (err) 2534 return err; 2535 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2536 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2537 xr->xr_trb = xhci_ring_trbv(xr, 0); 2538 xr->xr_ntrb = ntrb; 2539 xr->is_halted = false; 2540 xhci_host_dequeue(xr); 2541 2542 return USBD_NORMAL_COMPLETION; 2543 } 2544 2545 static void 2546 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2547 { 2548 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2549 mutex_destroy(&xr->xr_lock); 2550 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2551 } 2552 2553 static void 2554 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2555 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2556 { 2557 size_t i; 2558 u_int ri; 2559 u_int cs; 2560 uint64_t parameter; 2561 uint32_t status; 2562 uint32_t control; 2563 2564 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2565 2566 KASSERTMSG(ntrbs <= XHCI_XFER_NTRB, "ntrbs %zu", ntrbs); 2567 for (i = 0; i < ntrbs; i++) { 2568 DPRINTFN(12, "xr %#jx trbs %#jx num %ju", (uintptr_t)xr, 2569 (uintptr_t)trbs, i, 0); 2570 DPRINTFN(12, " %016jx %08jx %08jx", 2571 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2572 KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2573 XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3); 2574 } 2575 2576 DPRINTFN(12, "%#jx xr_ep 0x%jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep, 2577 xr->xr_cs, 0); 2578 2579 ri = xr->xr_ep; 2580 cs = xr->xr_cs; 2581 2582 /* 2583 * Although the xhci hardware can do scatter/gather dma from 2584 * arbitrary sized buffers, there is a non-obvious restriction 2585 * that a LINK trb is only allowed at the end of a burst of 2586 * transfers - which might be 16kB. 2587 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2588 * The simple solution is not to allow a LINK trb in the middle 2589 * of anything - as here. 2590 * XXX: (dsl) There are xhci controllers out there (eg some made by 2591 * ASMedia) that seem to lock up if they process a LINK trb but 2592 * cannot process the linked-to trb yet. 2593 * The code should write the 'cycle' bit on the link trb AFTER 2594 * adding the other trb. 2595 */ 2596 u_int firstep = xr->xr_ep; 2597 u_int firstcs = xr->xr_cs; 2598 2599 for (i = 0; i < ntrbs; ) { 2600 u_int oldri = ri; 2601 u_int oldcs = cs; 2602 2603 if (ri >= (xr->xr_ntrb - 1)) { 2604 /* Put Link TD at the end of ring */ 2605 parameter = xhci_ring_trbp(xr, 0); 2606 status = 0; 2607 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2608 XHCI_TRB_3_TC_BIT; 2609 xr->xr_cookies[ri] = NULL; 2610 xr->xr_ep = 0; 2611 xr->xr_cs ^= 1; 2612 ri = xr->xr_ep; 2613 cs = xr->xr_cs; 2614 } else { 2615 parameter = trbs[i].trb_0; 2616 status = trbs[i].trb_2; 2617 control = trbs[i].trb_3; 2618 2619 xr->xr_cookies[ri] = cookie; 2620 ri++; 2621 i++; 2622 } 2623 /* 2624 * If this is a first TRB, mark it invalid to prevent 2625 * xHC from running it immediately. 2626 */ 2627 if (oldri == firstep) { 2628 if (oldcs) { 2629 control &= ~XHCI_TRB_3_CYCLE_BIT; 2630 } else { 2631 control |= XHCI_TRB_3_CYCLE_BIT; 2632 } 2633 } else { 2634 if (oldcs) { 2635 control |= XHCI_TRB_3_CYCLE_BIT; 2636 } else { 2637 control &= ~XHCI_TRB_3_CYCLE_BIT; 2638 } 2639 } 2640 xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control); 2641 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri, 2642 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2643 } 2644 2645 /* Now invert cycle bit of first TRB */ 2646 if (firstcs) { 2647 xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 2648 } else { 2649 xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 2650 } 2651 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep, 2652 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2653 2654 xr->xr_ep = ri; 2655 xr->xr_cs = cs; 2656 2657 DPRINTFN(12, "%#jx xr_ep 0x%jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep, 2658 xr->xr_cs, 0); 2659 } 2660 2661 /* 2662 * Stop execution commands, purge all commands on command ring, and 2663 * rewind dequeue pointer. 2664 */ 2665 static void 2666 xhci_abort_command(struct xhci_softc *sc) 2667 { 2668 struct xhci_ring * const cr = &sc->sc_cr; 2669 uint64_t crcr; 2670 int i; 2671 2672 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2673 DPRINTFN(14, "command %#jx timeout, aborting", 2674 sc->sc_command_addr, 0, 0, 0); 2675 2676 mutex_enter(&cr->xr_lock); 2677 2678 /* 4.6.1.2 Aborting a Command */ 2679 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2680 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2681 2682 for (i = 0; i < 500; i++) { 2683 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2684 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2685 break; 2686 usb_delay_ms(&sc->sc_bus, 1); 2687 } 2688 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2689 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2690 /* reset HC here? */ 2691 } 2692 2693 /* reset command ring dequeue pointer */ 2694 cr->xr_ep = 0; 2695 cr->xr_cs = 1; 2696 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2697 2698 mutex_exit(&cr->xr_lock); 2699 } 2700 2701 /* 2702 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2703 * Command completion is notified by cv_signal from xhci_event_cmd() 2704 * (called from xhci_softint), or timed-out. 2705 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2706 * then do_command examines it. 2707 */ 2708 static usbd_status 2709 xhci_do_command_locked(struct xhci_softc * const sc, 2710 struct xhci_trb * const trb, int timeout) 2711 { 2712 struct xhci_ring * const cr = &sc->sc_cr; 2713 usbd_status err; 2714 2715 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2716 DPRINTFN(12, "input: 0x%016jx 0x%08jx 0x%08jx", 2717 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2718 2719 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2720 KASSERT(mutex_owned(&sc->sc_lock)); 2721 2722 while (sc->sc_command_addr != 0) 2723 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 2724 2725 /* 2726 * If enqueue pointer points at last of ring, it's Link TRB, 2727 * command TRB will be stored in 0th TRB. 2728 */ 2729 if (cr->xr_ep == cr->xr_ntrb - 1) 2730 sc->sc_command_addr = xhci_ring_trbp(cr, 0); 2731 else 2732 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2733 2734 sc->sc_resultpending = true; 2735 2736 mutex_enter(&cr->xr_lock); 2737 xhci_ring_put(sc, cr, NULL, trb, 1); 2738 mutex_exit(&cr->xr_lock); 2739 2740 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2741 2742 while (sc->sc_resultpending) { 2743 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2744 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2745 xhci_abort_command(sc); 2746 err = USBD_TIMEOUT; 2747 goto timedout; 2748 } 2749 } 2750 2751 trb->trb_0 = sc->sc_result_trb.trb_0; 2752 trb->trb_2 = sc->sc_result_trb.trb_2; 2753 trb->trb_3 = sc->sc_result_trb.trb_3; 2754 2755 DPRINTFN(12, "output: 0x%016jx 0x%08jx 0x%08jx", 2756 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2757 2758 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2759 case XHCI_TRB_ERROR_SUCCESS: 2760 err = USBD_NORMAL_COMPLETION; 2761 break; 2762 default: 2763 case 192 ... 223: 2764 err = USBD_IOERROR; 2765 break; 2766 case 224 ... 255: 2767 err = USBD_NORMAL_COMPLETION; 2768 break; 2769 } 2770 2771 timedout: 2772 sc->sc_resultpending = false; 2773 sc->sc_command_addr = 0; 2774 cv_broadcast(&sc->sc_cmdbusy_cv); 2775 2776 return err; 2777 } 2778 2779 static usbd_status 2780 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2781 int timeout) 2782 { 2783 2784 mutex_enter(&sc->sc_lock); 2785 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2786 mutex_exit(&sc->sc_lock); 2787 2788 return ret; 2789 } 2790 2791 static usbd_status 2792 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2793 { 2794 struct xhci_trb trb; 2795 usbd_status err; 2796 2797 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2798 2799 trb.trb_0 = 0; 2800 trb.trb_2 = 0; 2801 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2802 2803 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2804 if (err != USBD_NORMAL_COMPLETION) { 2805 return err; 2806 } 2807 2808 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2809 2810 return err; 2811 } 2812 2813 /* 2814 * xHCI 4.6.4 2815 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2816 * All endpoints in the slot should be stopped. 2817 * Should be called with sc_lock held. 2818 */ 2819 static usbd_status 2820 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2821 { 2822 struct xhci_trb trb; 2823 struct xhci_slot *xs; 2824 usbd_status err; 2825 2826 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2827 2828 if (sc->sc_dying) 2829 return USBD_IOERROR; 2830 2831 trb.trb_0 = 0; 2832 trb.trb_2 = 0; 2833 trb.trb_3 = htole32( 2834 XHCI_TRB_3_SLOT_SET(slot) | 2835 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2836 2837 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2838 2839 if (!err) { 2840 xs = &sc->sc_slots[slot]; 2841 if (xs->xs_idx != 0) { 2842 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2843 xhci_set_dcba(sc, 0, slot); 2844 memset(xs, 0, sizeof(*xs)); 2845 } 2846 } 2847 2848 return err; 2849 } 2850 2851 /* 2852 * Set address of device and transition slot state from ENABLED to ADDRESSED 2853 * if Block Setaddress Request (BSR) is false. 2854 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2855 * see xHCI 1.1 4.5.3, 3.3.4 2856 * Should be called without sc_lock held. 2857 */ 2858 static usbd_status 2859 xhci_address_device(struct xhci_softc * const sc, 2860 uint64_t icp, uint8_t slot_id, bool bsr) 2861 { 2862 struct xhci_trb trb; 2863 usbd_status err; 2864 2865 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2866 2867 trb.trb_0 = icp; 2868 trb.trb_2 = 0; 2869 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2870 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2871 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2872 2873 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2874 2875 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2876 err = USBD_NO_ADDR; 2877 2878 return err; 2879 } 2880 2881 static usbd_status 2882 xhci_update_ep0_mps(struct xhci_softc * const sc, 2883 struct xhci_slot * const xs, u_int mps) 2884 { 2885 struct xhci_trb trb; 2886 usbd_status err; 2887 uint32_t * cp; 2888 2889 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2890 DPRINTFN(4, "slot %ju mps %ju", xs->xs_idx, mps, 0, 0); 2891 2892 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2893 cp[0] = htole32(0); 2894 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2895 2896 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2897 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2898 2899 /* sync input contexts before they are read from memory */ 2900 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2901 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2902 sc->sc_ctxsz * 4); 2903 2904 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2905 trb.trb_2 = 0; 2906 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2907 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2908 2909 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2910 return err; 2911 } 2912 2913 static void 2914 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2915 { 2916 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2917 2918 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2919 DPRINTFN(4, "dcbaa %#jx dc %016jx slot %jd", 2920 (uintptr_t)&dcbaa[si], dcba, si, 0); 2921 2922 dcbaa[si] = htole64(dcba); 2923 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2924 BUS_DMASYNC_PREWRITE); 2925 } 2926 2927 /* 2928 * Allocate device and input context DMA buffer, and 2929 * TRB DMA buffer for each endpoint. 2930 */ 2931 static usbd_status 2932 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2933 { 2934 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2935 struct xhci_slot *xs; 2936 usbd_status err; 2937 u_int dci; 2938 2939 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2940 DPRINTFN(4, "slot %ju", slot, 0, 0, 0); 2941 2942 xs = &sc->sc_slots[slot]; 2943 2944 /* allocate contexts */ 2945 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2946 &xs->xs_dc_dma); 2947 if (err) 2948 return err; 2949 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2950 2951 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2952 &xs->xs_ic_dma); 2953 if (err) 2954 goto bad1; 2955 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2956 2957 for (dci = 0; dci < 32; dci++) { 2958 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2959 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2960 if (dci == XHCI_DCI_SLOT) 2961 continue; 2962 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2963 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2964 if (err) { 2965 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2966 goto bad2; 2967 } 2968 } 2969 2970 bad2: 2971 if (err == USBD_NORMAL_COMPLETION) { 2972 xs->xs_idx = slot; 2973 } else { 2974 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2975 } 2976 2977 return err; 2978 2979 bad1: 2980 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2981 xs->xs_idx = 0; 2982 return err; 2983 } 2984 2985 static void 2986 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2987 int end_dci) 2988 { 2989 u_int dci; 2990 2991 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2992 DPRINTFN(4, "slot %ju start %ju end %ju", xs->xs_idx, start_dci, 2993 end_dci, 0); 2994 2995 for (dci = start_dci; dci < end_dci; dci++) { 2996 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2997 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2998 } 2999 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 3000 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 3001 xs->xs_idx = 0; 3002 } 3003 3004 /* 3005 * Setup slot context, set Device Context Base Address, and issue 3006 * Set Address Device command. 3007 */ 3008 static usbd_status 3009 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 3010 { 3011 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 3012 struct xhci_slot *xs; 3013 usbd_status err; 3014 3015 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3016 DPRINTFN(4, "slot %ju bsr %ju", slot, bsr, 0, 0); 3017 3018 xs = &sc->sc_slots[slot]; 3019 3020 xhci_setup_ctx(dev->ud_pipe0); 3021 3022 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 3023 sc->sc_ctxsz * 3); 3024 3025 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 3026 3027 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 3028 3029 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 3030 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 3031 sc->sc_ctxsz * 2); 3032 3033 return err; 3034 } 3035 3036 /* 3037 * 4.8.2, 6.2.3.2 3038 * construct slot/endpoint context parameters and do syncmem 3039 */ 3040 static void 3041 xhci_setup_ctx(struct usbd_pipe *pipe) 3042 { 3043 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3044 struct usbd_device *dev = pipe->up_dev; 3045 struct xhci_slot * const xs = dev->ud_hcpriv; 3046 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3047 const u_int dci = xhci_ep_get_dci(ed); 3048 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3049 uint32_t *cp; 3050 uint16_t mps = UGETW(ed->wMaxPacketSize); 3051 uint8_t speed = dev->ud_speed; 3052 uint8_t ival = ed->bInterval; 3053 3054 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3055 DPRINTFN(4, "pipe %#jx: slot %ju dci %ju speed %ju", 3056 (uintptr_t)pipe, xs->xs_idx, dci, speed); 3057 3058 /* set up initial input control context */ 3059 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 3060 cp[0] = htole32(0); 3061 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 3062 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 3063 cp[7] = htole32(0); 3064 3065 /* set up input slot context */ 3066 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 3067 cp[0] = 3068 XHCI_SCTX_0_CTX_NUM_SET(dci) | 3069 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 3070 cp[1] = 0; 3071 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 3072 cp[3] = 0; 3073 xhci_setup_route(pipe, cp); 3074 xhci_setup_tthub(pipe, cp); 3075 3076 cp[0] = htole32(cp[0]); 3077 cp[1] = htole32(cp[1]); 3078 cp[2] = htole32(cp[2]); 3079 cp[3] = htole32(cp[3]); 3080 3081 /* set up input endpoint context */ 3082 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 3083 cp[0] = 3084 XHCI_EPCTX_0_EPSTATE_SET(0) | 3085 XHCI_EPCTX_0_MULT_SET(0) | 3086 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 3087 XHCI_EPCTX_0_LSA_SET(0) | 3088 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 3089 cp[1] = 3090 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 3091 XHCI_EPCTX_1_HID_SET(0) | 3092 XHCI_EPCTX_1_MAXB_SET(0); 3093 3094 if (xfertype != UE_ISOCHRONOUS) 3095 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 3096 3097 if (xfertype == UE_CONTROL) 3098 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 3099 else if (USB_IS_SS(speed)) 3100 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 3101 else 3102 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 3103 3104 xhci_setup_maxburst(pipe, cp); 3105 3106 switch (xfertype) { 3107 case UE_CONTROL: 3108 break; 3109 case UE_BULK: 3110 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 3111 break; 3112 case UE_INTERRUPT: 3113 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3114 ival = pipe->up_interval; 3115 3116 ival = xhci_bival2ival(ival, speed); 3117 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3118 break; 3119 case UE_ISOCHRONOUS: 3120 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3121 ival = pipe->up_interval; 3122 3123 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 3124 if (speed == USB_SPEED_FULL) 3125 ival += 3; /* 1ms -> 125us */ 3126 ival--; 3127 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3128 break; 3129 default: 3130 break; 3131 } 3132 DPRINTFN(4, "setting ival %ju MaxBurst %#jx", 3133 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 3134 3135 /* rewind TR dequeue pointer in xHC */ 3136 /* can't use xhci_ep_get_dci() yet? */ 3137 *(uint64_t *)(&cp[2]) = htole64( 3138 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 3139 XHCI_EPCTX_2_DCS_SET(1)); 3140 3141 cp[0] = htole32(cp[0]); 3142 cp[1] = htole32(cp[1]); 3143 cp[4] = htole32(cp[4]); 3144 3145 /* rewind TR dequeue pointer in driver */ 3146 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 3147 mutex_enter(&xr->xr_lock); 3148 xhci_host_dequeue(xr); 3149 mutex_exit(&xr->xr_lock); 3150 3151 /* sync input contexts before they are read from memory */ 3152 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3153 } 3154 3155 /* 3156 * Setup route string and roothub port of given device for slot context 3157 */ 3158 static void 3159 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 3160 { 3161 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3162 struct usbd_device *dev = pipe->up_dev; 3163 struct usbd_port *up = dev->ud_powersrc; 3164 struct usbd_device *hub; 3165 struct usbd_device *adev; 3166 uint8_t rhport = 0; 3167 uint32_t route = 0; 3168 3169 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3170 3171 /* Locate root hub port and Determine route string */ 3172 /* 4.3.3 route string does not include roothub port */ 3173 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 3174 uint32_t dep; 3175 3176 DPRINTFN(4, "hub %#jx depth %jd upport %jp upportno %jd", 3177 (uintptr_t)hub, hub->ud_depth, (uintptr_t)hub->ud_powersrc, 3178 hub->ud_powersrc ? (uintptr_t)hub->ud_powersrc->up_portno : 3179 -1); 3180 3181 if (hub->ud_powersrc == NULL) 3182 break; 3183 dep = hub->ud_depth; 3184 if (dep == 0) 3185 break; 3186 rhport = hub->ud_powersrc->up_portno; 3187 if (dep > USB_HUB_MAX_DEPTH) 3188 continue; 3189 3190 route |= 3191 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 3192 << ((dep - 1) * 4); 3193 } 3194 route = route >> 4; 3195 size_t bn = hub == sc->sc_bus.ub_roothub ? 0 : 1; 3196 3197 /* Locate port on upstream high speed hub */ 3198 for (adev = dev, hub = up->up_parent; 3199 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 3200 adev = hub, hub = hub->ud_myhub) 3201 ; 3202 if (hub) { 3203 int p; 3204 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 3205 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 3206 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 3207 goto found; 3208 } 3209 } 3210 panic("%s: cannot find HS port", __func__); 3211 found: 3212 DPRINTFN(4, "high speed port %jd", p, 0, 0, 0); 3213 } else { 3214 dev->ud_myhsport = NULL; 3215 } 3216 3217 const size_t ctlrport = xhci_rhport2ctlrport(sc, bn, rhport); 3218 3219 DPRINTFN(4, "rhport %ju ctlrport %ju Route %05jx hub %#jx", rhport, 3220 ctlrport, route, (uintptr_t)hub); 3221 3222 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 3223 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(ctlrport); 3224 } 3225 3226 /* 3227 * Setup whether device is hub, whether device uses MTT, and 3228 * TT informations if it uses MTT. 3229 */ 3230 static void 3231 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 3232 { 3233 struct usbd_device *dev = pipe->up_dev; 3234 struct usbd_port *myhsport = dev->ud_myhsport; 3235 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 3236 uint32_t speed = dev->ud_speed; 3237 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 3238 uint8_t tthubslot, ttportnum; 3239 bool ishub; 3240 bool usemtt; 3241 3242 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3243 3244 /* 3245 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 3246 * tthubslot: 3247 * This is the slot ID of parent HS hub 3248 * if LS/FS device is connected && connected through HS hub. 3249 * This is 0 if device is not LS/FS device || 3250 * parent hub is not HS hub || 3251 * attached to root hub. 3252 * ttportnum: 3253 * This is the downstream facing port of parent HS hub 3254 * if LS/FS device is connected. 3255 * This is 0 if device is not LS/FS device || 3256 * parent hub is not HS hub || 3257 * attached to root hub. 3258 */ 3259 if (myhsport && 3260 myhsport->up_parent->ud_addr != rhaddr && 3261 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 3262 ttportnum = myhsport->up_portno; 3263 tthubslot = myhsport->up_parent->ud_addr; 3264 } else { 3265 ttportnum = 0; 3266 tthubslot = 0; 3267 } 3268 DPRINTFN(4, "myhsport %#jx ttportnum=%jd tthubslot=%jd", 3269 (uintptr_t)myhsport, ttportnum, tthubslot, 0); 3270 3271 /* ishub is valid after reading UDESC_DEVICE */ 3272 ishub = (dd->bDeviceClass == UDCLASS_HUB); 3273 3274 /* dev->ud_hub is valid after reading UDESC_HUB */ 3275 if (ishub && dev->ud_hub) { 3276 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 3277 uint8_t ttt = 3278 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 3279 3280 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 3281 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 3282 DPRINTFN(4, "nports=%jd ttt=%jd", hd->bNbrPorts, ttt, 0, 0); 3283 } 3284 3285 #define IS_MTTHUB(dd) \ 3286 ((dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 3287 3288 /* 3289 * MTT flag is set if 3290 * 1. this is HS hub && MTTs are supported and enabled; or 3291 * 2. this is LS or FS device && there is a parent HS hub where MTTs 3292 * are supported and enabled. 3293 * 3294 * XXX enabled is not tested yet 3295 */ 3296 if (ishub && speed == USB_SPEED_HIGH && IS_MTTHUB(dd)) 3297 usemtt = true; 3298 else if ((speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 3299 myhsport && 3300 myhsport->up_parent->ud_addr != rhaddr && 3301 IS_MTTHUB(&myhsport->up_parent->ud_ddesc)) 3302 usemtt = true; 3303 else 3304 usemtt = false; 3305 DPRINTFN(4, "class %ju proto %ju ishub %jd usemtt %jd", 3306 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 3307 3308 #undef IS_MTTHUB 3309 3310 cp[0] |= 3311 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 3312 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 3313 cp[2] |= 3314 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 3315 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 3316 } 3317 3318 /* set up params for periodic endpoint */ 3319 static void 3320 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 3321 { 3322 struct usbd_device *dev = pipe->up_dev; 3323 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3324 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3325 usbd_desc_iter_t iter; 3326 const usb_cdc_descriptor_t *cdcd; 3327 uint32_t maxb = 0; 3328 uint16_t mps = UGETW(ed->wMaxPacketSize); 3329 uint8_t speed = dev->ud_speed; 3330 uint8_t ep; 3331 3332 /* config desc is NULL when opening ep0 */ 3333 if (dev == NULL || dev->ud_cdesc == NULL) 3334 goto no_cdcd; 3335 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 3336 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 3337 if (cdcd == NULL) 3338 goto no_cdcd; 3339 usb_desc_iter_init(dev, &iter); 3340 iter.cur = (const void *)cdcd; 3341 3342 /* find endpoint_ss_comp desc for ep of this pipe */ 3343 for (ep = 0;;) { 3344 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 3345 if (cdcd == NULL) 3346 break; 3347 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 3348 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 3349 bEndpointAddress; 3350 if (UE_GET_ADDR(ep) == 3351 UE_GET_ADDR(ed->bEndpointAddress)) { 3352 cdcd = (const usb_cdc_descriptor_t *) 3353 usb_desc_iter_next(&iter); 3354 break; 3355 } 3356 ep = 0; 3357 } 3358 } 3359 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 3360 const usb_endpoint_ss_comp_descriptor_t * esscd = 3361 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3362 maxb = esscd->bMaxBurst; 3363 } 3364 3365 no_cdcd: 3366 /* 6.2.3.4, 4.8.2.4 */ 3367 if (USB_IS_SS(speed)) { 3368 /* USB 3.1 9.6.6 */ 3369 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3370 /* USB 3.1 9.6.7 */ 3371 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3372 #ifdef notyet 3373 if (xfertype == UE_ISOCHRONOUS) { 3374 } 3375 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3376 /* use ESIT */ 3377 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3378 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3379 3380 /* XXX if LEC = 1, set ESIT instead */ 3381 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3382 } else { 3383 /* use ival */ 3384 } 3385 #endif 3386 } else { 3387 /* USB 2.0 9.6.6 */ 3388 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3389 3390 /* 6.2.3.4 */ 3391 if (speed == USB_SPEED_HIGH && 3392 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3393 maxb = UE_GET_TRANS(mps); 3394 } else { 3395 /* LS/FS or HS CTRL or HS BULK */ 3396 maxb = 0; 3397 } 3398 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3399 } 3400 } 3401 3402 /* 3403 * Convert endpoint bInterval value to endpoint context interval value 3404 * for Interrupt pipe. 3405 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3406 */ 3407 static uint32_t 3408 xhci_bival2ival(uint32_t ival, uint32_t speed) 3409 { 3410 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3411 int i; 3412 3413 /* 3414 * round ival down to "the nearest base 2 multiple of 3415 * bInterval * 8". 3416 * bInterval is at most 255 as its type is uByte. 3417 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3418 */ 3419 for (i = 10; i > 0; i--) { 3420 if ((ival * 8) >= (1 << i)) 3421 break; 3422 } 3423 ival = i; 3424 } else { 3425 /* Interval = bInterval-1 for SS/HS */ 3426 ival--; 3427 } 3428 3429 return ival; 3430 } 3431 3432 /* ----- */ 3433 3434 static void 3435 xhci_noop(struct usbd_pipe *pipe) 3436 { 3437 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3438 } 3439 3440 /* 3441 * Process root hub request. 3442 */ 3443 static int 3444 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3445 void *buf, int buflen) 3446 { 3447 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3448 usb_port_status_t ps; 3449 int l, totlen = 0; 3450 uint16_t len, value, index; 3451 int port, i; 3452 uint32_t v; 3453 3454 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3455 3456 if (sc->sc_dying) 3457 return -1; 3458 3459 size_t bn = bus == &sc->sc_bus ? 0 : 1; 3460 3461 len = UGETW(req->wLength); 3462 value = UGETW(req->wValue); 3463 index = UGETW(req->wIndex); 3464 3465 DPRINTFN(12, "rhreq: %04jx %04jx %04jx %04jx", 3466 req->bmRequestType | (req->bRequest << 8), value, index, len); 3467 3468 #define C(x,y) ((x) | ((y) << 8)) 3469 switch (C(req->bRequest, req->bmRequestType)) { 3470 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3471 DPRINTFN(8, "getdesc: wValue=0x%04jx", value, 0, 0, 0); 3472 if (len == 0) 3473 break; 3474 switch (value) { 3475 case C(0, UDESC_DEVICE): { 3476 usb_device_descriptor_t devd; 3477 totlen = min(buflen, sizeof(devd)); 3478 memcpy(&devd, buf, totlen); 3479 USETW(devd.idVendor, sc->sc_id_vendor); 3480 memcpy(buf, &devd, totlen); 3481 break; 3482 } 3483 #define sd ((usb_string_descriptor_t *)buf) 3484 case C(1, UDESC_STRING): 3485 /* Vendor */ 3486 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3487 break; 3488 case C(2, UDESC_STRING): 3489 /* Product */ 3490 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3491 break; 3492 #undef sd 3493 default: 3494 /* default from usbroothub */ 3495 return buflen; 3496 } 3497 break; 3498 3499 /* Hub requests */ 3500 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3501 break; 3502 /* Clear Port Feature request */ 3503 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): { 3504 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3505 3506 DPRINTFN(4, "UR_CLEAR_PORT_FEAT bp=%jd feat=%jd bus=%jd cp=%jd", 3507 index, value, bn, cp); 3508 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3509 return -1; 3510 } 3511 port = XHCI_PORTSC(cp); 3512 v = xhci_op_read_4(sc, port); 3513 DPRINTFN(4, "portsc=0x%08jx", v, 0, 0, 0); 3514 v &= ~XHCI_PS_CLEAR; 3515 switch (value) { 3516 case UHF_PORT_ENABLE: 3517 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3518 break; 3519 case UHF_PORT_SUSPEND: 3520 return -1; 3521 case UHF_PORT_POWER: 3522 break; 3523 case UHF_PORT_TEST: 3524 case UHF_PORT_INDICATOR: 3525 return -1; 3526 case UHF_C_PORT_CONNECTION: 3527 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3528 break; 3529 case UHF_C_PORT_ENABLE: 3530 case UHF_C_PORT_SUSPEND: 3531 case UHF_C_PORT_OVER_CURRENT: 3532 return -1; 3533 case UHF_C_BH_PORT_RESET: 3534 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3535 break; 3536 case UHF_C_PORT_RESET: 3537 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3538 break; 3539 case UHF_C_PORT_LINK_STATE: 3540 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3541 break; 3542 case UHF_C_PORT_CONFIG_ERROR: 3543 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3544 break; 3545 default: 3546 return -1; 3547 } 3548 break; 3549 } 3550 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3551 if (len == 0) 3552 break; 3553 if ((value & 0xff) != 0) { 3554 return -1; 3555 } 3556 usb_hub_descriptor_t hubd; 3557 3558 totlen = min(buflen, sizeof(hubd)); 3559 memcpy(&hubd, buf, totlen); 3560 hubd.bNbrPorts = sc->sc_rhportcount[bn]; 3561 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3562 hubd.bPwrOn2PwrGood = 200; 3563 for (i = 0, l = sc->sc_rhportcount[bn]; l > 0; i++, l -= 8) { 3564 /* XXX can't find out? */ 3565 hubd.DeviceRemovable[i++] = 0; 3566 } 3567 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3568 totlen = min(totlen, hubd.bDescLength); 3569 memcpy(buf, &hubd, totlen); 3570 break; 3571 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3572 if (len != 4) { 3573 return -1; 3574 } 3575 memset(buf, 0, len); /* ? XXX */ 3576 totlen = len; 3577 break; 3578 /* Get Port Status request */ 3579 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): { 3580 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3581 3582 DPRINTFN(8, "get port status bn=%jd i=%jd cp=%ju", 3583 bn, index, cp, 0); 3584 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3585 return -1; 3586 } 3587 if (len != 4) { 3588 return -1; 3589 } 3590 v = xhci_op_read_4(sc, XHCI_PORTSC(cp)); 3591 DPRINTFN(4, "getrhportsc %jd %08jx", cp, v, 0, 0); 3592 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3593 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3594 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3595 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3596 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3597 if (v & XHCI_PS_PR) i |= UPS_RESET; 3598 if (v & XHCI_PS_PP) { 3599 if (i & UPS_OTHER_SPEED) 3600 i |= UPS_PORT_POWER_SS; 3601 else 3602 i |= UPS_PORT_POWER; 3603 } 3604 if (i & UPS_OTHER_SPEED) 3605 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3606 if (sc->sc_vendor_port_status) 3607 i = sc->sc_vendor_port_status(sc, v, i); 3608 USETW(ps.wPortStatus, i); 3609 i = 0; 3610 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3611 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3612 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3613 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3614 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3615 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3616 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3617 USETW(ps.wPortChange, i); 3618 totlen = min(len, sizeof(ps)); 3619 memcpy(buf, &ps, totlen); 3620 break; 3621 } 3622 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3623 return -1; 3624 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3625 break; 3626 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3627 break; 3628 /* Set Port Feature request */ 3629 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3630 int optval = (index >> 8) & 0xff; 3631 index &= 0xff; 3632 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3633 return -1; 3634 } 3635 3636 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3637 3638 port = XHCI_PORTSC(cp); 3639 v = xhci_op_read_4(sc, port); 3640 DPRINTFN(4, "index %jd cp %jd portsc=0x%08jx", index, cp, v, 0); 3641 v &= ~XHCI_PS_CLEAR; 3642 switch (value) { 3643 case UHF_PORT_ENABLE: 3644 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3645 break; 3646 case UHF_PORT_SUSPEND: 3647 /* XXX suspend */ 3648 break; 3649 case UHF_PORT_RESET: 3650 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3651 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3652 /* Wait for reset to complete. */ 3653 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3654 if (sc->sc_dying) { 3655 return -1; 3656 } 3657 v = xhci_op_read_4(sc, port); 3658 if (v & XHCI_PS_PR) { 3659 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3660 usb_delay_ms(&sc->sc_bus, 10); 3661 /* XXX */ 3662 } 3663 break; 3664 case UHF_PORT_POWER: 3665 /* XXX power control */ 3666 break; 3667 /* XXX more */ 3668 case UHF_C_PORT_RESET: 3669 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3670 break; 3671 case UHF_PORT_U1_TIMEOUT: 3672 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3673 return -1; 3674 } 3675 port = XHCI_PORTPMSC(cp); 3676 v = xhci_op_read_4(sc, port); 3677 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 3678 index, cp, v, 0); 3679 v &= ~XHCI_PM3_U1TO_SET(0xff); 3680 v |= XHCI_PM3_U1TO_SET(optval); 3681 xhci_op_write_4(sc, port, v); 3682 break; 3683 case UHF_PORT_U2_TIMEOUT: 3684 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3685 return -1; 3686 } 3687 port = XHCI_PORTPMSC(cp); 3688 v = xhci_op_read_4(sc, port); 3689 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 3690 index, cp, v, 0); 3691 v &= ~XHCI_PM3_U2TO_SET(0xff); 3692 v |= XHCI_PM3_U2TO_SET(optval); 3693 xhci_op_write_4(sc, port, v); 3694 break; 3695 default: 3696 return -1; 3697 } 3698 } 3699 break; 3700 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3701 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3702 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3703 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3704 break; 3705 default: 3706 /* default from usbroothub */ 3707 return buflen; 3708 } 3709 3710 return totlen; 3711 } 3712 3713 /* root hub interrupt */ 3714 3715 static usbd_status 3716 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3717 { 3718 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3719 usbd_status err; 3720 3721 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3722 3723 /* Insert last in queue. */ 3724 mutex_enter(&sc->sc_lock); 3725 err = usb_insert_transfer(xfer); 3726 mutex_exit(&sc->sc_lock); 3727 if (err) 3728 return err; 3729 3730 /* Pipe isn't running, start first */ 3731 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3732 } 3733 3734 /* Wait for roothub port status/change */ 3735 static usbd_status 3736 xhci_root_intr_start(struct usbd_xfer *xfer) 3737 { 3738 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3739 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3740 const bool polling = xhci_polling_p(sc); 3741 3742 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3743 3744 if (sc->sc_dying) 3745 return USBD_IOERROR; 3746 3747 if (!polling) 3748 mutex_enter(&sc->sc_lock); 3749 sc->sc_intrxfer[bn] = xfer; 3750 if (!polling) 3751 mutex_exit(&sc->sc_lock); 3752 3753 return USBD_IN_PROGRESS; 3754 } 3755 3756 static void 3757 xhci_root_intr_abort(struct usbd_xfer *xfer) 3758 { 3759 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3760 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3761 3762 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3763 3764 KASSERT(mutex_owned(&sc->sc_lock)); 3765 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3766 3767 sc->sc_intrxfer[bn] = NULL; 3768 3769 xfer->ux_status = USBD_CANCELLED; 3770 usb_transfer_complete(xfer); 3771 } 3772 3773 static void 3774 xhci_root_intr_close(struct usbd_pipe *pipe) 3775 { 3776 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3777 const struct usbd_xfer *xfer = pipe->up_intrxfer; 3778 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3779 3780 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3781 3782 KASSERT(mutex_owned(&sc->sc_lock)); 3783 3784 sc->sc_intrxfer[bn] = NULL; 3785 } 3786 3787 static void 3788 xhci_root_intr_done(struct usbd_xfer *xfer) 3789 { 3790 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3791 3792 } 3793 3794 /* -------------- */ 3795 /* device control */ 3796 3797 static usbd_status 3798 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3799 { 3800 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3801 usbd_status err; 3802 3803 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3804 3805 /* Insert last in queue. */ 3806 mutex_enter(&sc->sc_lock); 3807 err = usb_insert_transfer(xfer); 3808 mutex_exit(&sc->sc_lock); 3809 if (err) 3810 return err; 3811 3812 /* Pipe isn't running, start first */ 3813 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3814 } 3815 3816 static usbd_status 3817 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3818 { 3819 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3820 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3821 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3822 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3823 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3824 usb_device_request_t * const req = &xfer->ux_request; 3825 const int isread = usbd_xfer_isread(xfer); 3826 const uint32_t len = UGETW(req->wLength); 3827 usb_dma_t * const dma = &xfer->ux_dmabuf; 3828 uint64_t parameter; 3829 uint32_t status; 3830 uint32_t control; 3831 u_int i; 3832 const bool polling = xhci_polling_p(sc); 3833 3834 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3835 DPRINTFN(12, "req: %04jx %04jx %04jx %04jx", 3836 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3837 UGETW(req->wIndex), UGETW(req->wLength)); 3838 3839 /* we rely on the bottom bits for extra info */ 3840 KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx", 3841 (uintptr_t) xfer); 3842 3843 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3844 3845 i = 0; 3846 3847 /* setup phase */ 3848 memcpy(¶meter, req, sizeof(parameter)); 3849 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3850 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3851 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3852 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3853 XHCI_TRB_3_IDT_BIT; 3854 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3855 3856 if (len != 0) { 3857 /* data phase */ 3858 parameter = DMAADDR(dma, 0); 3859 KASSERTMSG(len <= 0x10000, "len %d", len); 3860 status = XHCI_TRB_2_IRQ_SET(0) | 3861 XHCI_TRB_2_TDSZ_SET(0) | 3862 XHCI_TRB_2_BYTES_SET(len); 3863 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3864 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3865 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3866 XHCI_TRB_3_IOC_BIT; 3867 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3868 } 3869 3870 parameter = 0; 3871 status = XHCI_TRB_2_IRQ_SET(0); 3872 /* the status stage has inverted direction */ 3873 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3874 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3875 XHCI_TRB_3_IOC_BIT; 3876 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3877 xfer->ux_status = USBD_IN_PROGRESS; 3878 3879 if (!polling) 3880 mutex_enter(&tr->xr_lock); 3881 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3882 if (!polling) 3883 mutex_exit(&tr->xr_lock); 3884 3885 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3886 3887 if (xfer->ux_timeout && !xhci_polling_p(sc)) { 3888 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3889 xhci_timeout, xfer); 3890 } 3891 3892 return USBD_IN_PROGRESS; 3893 } 3894 3895 static void 3896 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3897 { 3898 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3899 usb_device_request_t *req = &xfer->ux_request; 3900 int len = UGETW(req->wLength); 3901 int rd = req->bmRequestType & UT_READ; 3902 3903 if (len) 3904 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3905 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3906 } 3907 3908 static void 3909 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3910 { 3911 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3912 3913 xhci_abort_xfer(xfer, USBD_CANCELLED); 3914 } 3915 3916 static void 3917 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3918 { 3919 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3920 3921 xhci_close_pipe(pipe); 3922 } 3923 3924 /* ------------------ */ 3925 /* device isochronous */ 3926 3927 /* ----------- */ 3928 /* device bulk */ 3929 3930 static usbd_status 3931 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3932 { 3933 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3934 usbd_status err; 3935 3936 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3937 3938 /* Insert last in queue. */ 3939 mutex_enter(&sc->sc_lock); 3940 err = usb_insert_transfer(xfer); 3941 mutex_exit(&sc->sc_lock); 3942 if (err) 3943 return err; 3944 3945 /* 3946 * Pipe isn't running (otherwise err would be USBD_INPROG), 3947 * so start it first. 3948 */ 3949 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3950 } 3951 3952 static usbd_status 3953 xhci_device_bulk_start(struct usbd_xfer *xfer) 3954 { 3955 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3956 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3957 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3958 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3959 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3960 const uint32_t len = xfer->ux_length; 3961 usb_dma_t * const dma = &xfer->ux_dmabuf; 3962 uint64_t parameter; 3963 uint32_t status; 3964 uint32_t control; 3965 u_int i = 0; 3966 const bool polling = xhci_polling_p(sc); 3967 3968 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3969 3970 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 3971 0); 3972 3973 if (sc->sc_dying) 3974 return USBD_IOERROR; 3975 3976 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3977 3978 parameter = DMAADDR(dma, 0); 3979 /* 3980 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3981 * If the user supplied buffer crosses such a boundary then 2 3982 * (or more) TRB should be used. 3983 * If multiple TRB are used the td_size field must be set correctly. 3984 * For v1.0 devices (like ivy bridge) this is the number of usb data 3985 * blocks needed to complete the transfer. 3986 * Setting it to 1 in the last TRB causes an extra zero-length 3987 * data block be sent. 3988 * The earlier documentation differs, I don't know how it behaves. 3989 */ 3990 KASSERTMSG(len <= 0x10000, "len %d", len); 3991 status = XHCI_TRB_2_IRQ_SET(0) | 3992 XHCI_TRB_2_TDSZ_SET(0) | 3993 XHCI_TRB_2_BYTES_SET(len); 3994 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3995 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3996 XHCI_TRB_3_IOC_BIT; 3997 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3998 xfer->ux_status = USBD_IN_PROGRESS; 3999 4000 if (!polling) 4001 mutex_enter(&tr->xr_lock); 4002 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 4003 if (!polling) 4004 mutex_exit(&tr->xr_lock); 4005 4006 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4007 4008 if (xfer->ux_timeout && !polling) { 4009 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4010 xhci_timeout, xfer); 4011 } 4012 4013 return USBD_IN_PROGRESS; 4014 } 4015 4016 static void 4017 xhci_device_bulk_done(struct usbd_xfer *xfer) 4018 { 4019 #ifdef USB_DEBUG 4020 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4021 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4022 #endif 4023 const int isread = usbd_xfer_isread(xfer); 4024 4025 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4026 4027 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 4028 0); 4029 4030 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4031 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4032 } 4033 4034 static void 4035 xhci_device_bulk_abort(struct usbd_xfer *xfer) 4036 { 4037 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4038 4039 xhci_abort_xfer(xfer, USBD_CANCELLED); 4040 } 4041 4042 static void 4043 xhci_device_bulk_close(struct usbd_pipe *pipe) 4044 { 4045 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4046 4047 xhci_close_pipe(pipe); 4048 } 4049 4050 /* ---------------- */ 4051 /* device interrupt */ 4052 4053 static usbd_status 4054 xhci_device_intr_transfer(struct usbd_xfer *xfer) 4055 { 4056 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4057 usbd_status err; 4058 4059 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4060 4061 /* Insert last in queue. */ 4062 mutex_enter(&sc->sc_lock); 4063 err = usb_insert_transfer(xfer); 4064 mutex_exit(&sc->sc_lock); 4065 if (err) 4066 return err; 4067 4068 /* 4069 * Pipe isn't running (otherwise err would be USBD_INPROG), 4070 * so start it first. 4071 */ 4072 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4073 } 4074 4075 static usbd_status 4076 xhci_device_intr_start(struct usbd_xfer *xfer) 4077 { 4078 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4079 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4080 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4081 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 4082 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 4083 const uint32_t len = xfer->ux_length; 4084 const bool polling = xhci_polling_p(sc); 4085 usb_dma_t * const dma = &xfer->ux_dmabuf; 4086 uint64_t parameter; 4087 uint32_t status; 4088 uint32_t control; 4089 u_int i = 0; 4090 4091 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4092 4093 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 4094 0); 4095 4096 if (sc->sc_dying) 4097 return USBD_IOERROR; 4098 4099 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 4100 4101 parameter = DMAADDR(dma, 0); 4102 KASSERTMSG(len <= 0x10000, "len %d", len); 4103 status = XHCI_TRB_2_IRQ_SET(0) | 4104 XHCI_TRB_2_TDSZ_SET(0) | 4105 XHCI_TRB_2_BYTES_SET(len); 4106 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 4107 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 4108 XHCI_TRB_3_IOC_BIT; 4109 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 4110 xfer->ux_status = USBD_IN_PROGRESS; 4111 4112 if (!polling) 4113 mutex_enter(&tr->xr_lock); 4114 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 4115 if (!polling) 4116 mutex_exit(&tr->xr_lock); 4117 4118 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4119 4120 if (xfer->ux_timeout && !xhci_polling_p(sc)) { 4121 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4122 xhci_timeout, xfer); 4123 } 4124 4125 return USBD_IN_PROGRESS; 4126 } 4127 4128 static void 4129 xhci_device_intr_done(struct usbd_xfer *xfer) 4130 { 4131 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4132 #ifdef USB_DEBUG 4133 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4134 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4135 #endif 4136 const int isread = usbd_xfer_isread(xfer); 4137 4138 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4139 4140 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 4141 0); 4142 4143 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 4144 4145 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4146 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4147 } 4148 4149 static void 4150 xhci_device_intr_abort(struct usbd_xfer *xfer) 4151 { 4152 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4153 4154 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4155 4156 KASSERT(mutex_owned(&sc->sc_lock)); 4157 DPRINTFN(15, "%#jx", (uintptr_t)xfer, 0, 0, 0); 4158 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4159 xhci_abort_xfer(xfer, USBD_CANCELLED); 4160 } 4161 4162 static void 4163 xhci_device_intr_close(struct usbd_pipe *pipe) 4164 { 4165 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 4166 4167 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4168 DPRINTFN(15, "%#jx", (uintptr_t)pipe, 0, 0, 0); 4169 4170 xhci_close_pipe(pipe); 4171 } 4172 4173 /* ------------ */ 4174 4175 static void 4176 xhci_timeout(void *addr) 4177 { 4178 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4179 struct xhci_xfer * const xx = addr; 4180 struct usbd_xfer * const xfer = &xx->xx_xfer; 4181 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4182 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4183 4184 mutex_enter(&sc->sc_lock); 4185 if (!sc->sc_dying && xfer->ux_status == USBD_IN_PROGRESS) 4186 usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC); 4187 mutex_exit(&sc->sc_lock); 4188 } 4189 4190 static void 4191 xhci_timeout_task(void *addr) 4192 { 4193 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4194 struct usbd_xfer * const xfer = addr; 4195 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4196 4197 mutex_enter(&sc->sc_lock); 4198 xhci_abort_xfer(xfer, USBD_TIMEOUT); 4199 mutex_exit(&sc->sc_lock); 4200 } 4201
Indexes created Wed Oct 01 18:09:54 GMT 2025