xhci.c revision 1.72.2.7
1 /* $NetBSD: xhci.c,v 1.72.2.7 2018/08/25 11:29:52 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.72.2.7 2018/08/25 11:29:52 martin Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static void xhci_host_dequeue(struct xhci_ring * const); 146 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 147 148 static usbd_status xhci_do_command(struct xhci_softc * const, 149 struct xhci_trb * const, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 153 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 154 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 155 static usbd_status xhci_enable_slot(struct xhci_softc * const, 156 uint8_t * const); 157 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 158 static usbd_status xhci_address_device(struct xhci_softc * const, 159 uint64_t, uint8_t, bool); 160 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 161 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 162 struct xhci_slot * const, u_int); 163 static usbd_status xhci_ring_init(struct xhci_softc * const, 164 struct xhci_ring * const, size_t, size_t); 165 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 166 167 static void xhci_setup_ctx(struct usbd_pipe *); 168 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 169 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 170 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 171 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 172 173 static void xhci_noop(struct usbd_pipe *); 174 175 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 176 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 177 static void xhci_root_intr_abort(struct usbd_xfer *); 178 static void xhci_root_intr_close(struct usbd_pipe *); 179 static void xhci_root_intr_done(struct usbd_xfer *); 180 181 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 182 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 183 static void xhci_device_ctrl_abort(struct usbd_xfer *); 184 static void xhci_device_ctrl_close(struct usbd_pipe *); 185 static void xhci_device_ctrl_done(struct usbd_xfer *); 186 187 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 188 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 189 static void xhci_device_intr_abort(struct usbd_xfer *); 190 static void xhci_device_intr_close(struct usbd_pipe *); 191 static void xhci_device_intr_done(struct usbd_xfer *); 192 193 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 194 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 195 static void xhci_device_bulk_abort(struct usbd_xfer *); 196 static void xhci_device_bulk_close(struct usbd_pipe *); 197 static void xhci_device_bulk_done(struct usbd_xfer *); 198 199 static void xhci_timeout(void *); 200 static void xhci_timeout_task(void *); 201 202 static const struct usbd_bus_methods xhci_bus_methods = { 203 .ubm_open = xhci_open, 204 .ubm_softint = xhci_softintr, 205 .ubm_dopoll = xhci_poll, 206 .ubm_allocx = xhci_allocx, 207 .ubm_freex = xhci_freex, 208 .ubm_getlock = xhci_get_lock, 209 .ubm_newdev = xhci_new_device, 210 .ubm_rhctrl = xhci_roothub_ctrl, 211 }; 212 213 static const struct usbd_pipe_methods xhci_root_intr_methods = { 214 .upm_transfer = xhci_root_intr_transfer, 215 .upm_start = xhci_root_intr_start, 216 .upm_abort = xhci_root_intr_abort, 217 .upm_close = xhci_root_intr_close, 218 .upm_cleartoggle = xhci_noop, 219 .upm_done = xhci_root_intr_done, 220 }; 221 222 223 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 224 .upm_transfer = xhci_device_ctrl_transfer, 225 .upm_start = xhci_device_ctrl_start, 226 .upm_abort = xhci_device_ctrl_abort, 227 .upm_close = xhci_device_ctrl_close, 228 .upm_cleartoggle = xhci_noop, 229 .upm_done = xhci_device_ctrl_done, 230 }; 231 232 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 233 .upm_cleartoggle = xhci_noop, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 237 .upm_transfer = xhci_device_bulk_transfer, 238 .upm_start = xhci_device_bulk_start, 239 .upm_abort = xhci_device_bulk_abort, 240 .upm_close = xhci_device_bulk_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_bulk_done, 243 }; 244 245 static const struct usbd_pipe_methods xhci_device_intr_methods = { 246 .upm_transfer = xhci_device_intr_transfer, 247 .upm_start = xhci_device_intr_start, 248 .upm_abort = xhci_device_intr_abort, 249 .upm_close = xhci_device_intr_close, 250 .upm_cleartoggle = xhci_noop, 251 .upm_done = xhci_device_intr_done, 252 }; 253 254 static inline uint32_t 255 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 256 { 257 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 258 } 259 260 static inline uint32_t 261 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 262 { 263 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 264 } 265 266 static inline void 267 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 268 uint32_t value) 269 { 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 271 } 272 273 #if 0 /* unused */ 274 static inline void 275 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 276 uint32_t value) 277 { 278 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 279 } 280 #endif /* unused */ 281 282 static inline uint32_t 283 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 284 { 285 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 286 } 287 288 static inline uint32_t 289 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 290 { 291 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 292 } 293 294 static inline void 295 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 296 uint32_t value) 297 { 298 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 299 } 300 301 static inline uint64_t 302 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 303 { 304 uint64_t value; 305 306 if (sc->sc_ac64) { 307 #ifdef XHCI_USE_BUS_SPACE_8 308 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 309 #else 310 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 311 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 312 offset + 4) << 32; 313 #endif 314 } else { 315 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 316 } 317 318 return value; 319 } 320 321 static inline void 322 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 336 } 337 } 338 339 static inline uint32_t 340 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 341 { 342 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 343 } 344 345 static inline void 346 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 347 uint32_t value) 348 { 349 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 350 } 351 352 #if 0 /* unused */ 353 static inline uint64_t 354 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 355 { 356 uint64_t value; 357 358 if (sc->sc_ac64) { 359 #ifdef XHCI_USE_BUS_SPACE_8 360 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 361 #else 362 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 363 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 364 offset + 4) << 32; 365 #endif 366 } else { 367 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 368 } 369 370 return value; 371 } 372 #endif /* unused */ 373 374 static inline void 375 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 376 uint64_t value) 377 { 378 if (sc->sc_ac64) { 379 #ifdef XHCI_USE_BUS_SPACE_8 380 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 381 #else 382 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 383 (value >> 0) & 0xffffffff); 384 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 385 (value >> 32) & 0xffffffff); 386 #endif 387 } else { 388 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 389 } 390 } 391 392 #if 0 /* unused */ 393 static inline uint32_t 394 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 395 { 396 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 397 } 398 #endif /* unused */ 399 400 static inline void 401 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 402 uint32_t value) 403 { 404 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 405 } 406 407 /* --- */ 408 409 static inline uint8_t 410 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 411 { 412 u_int eptype = 0; 413 414 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 415 case UE_CONTROL: 416 eptype = 0x0; 417 break; 418 case UE_ISOCHRONOUS: 419 eptype = 0x1; 420 break; 421 case UE_BULK: 422 eptype = 0x2; 423 break; 424 case UE_INTERRUPT: 425 eptype = 0x3; 426 break; 427 } 428 429 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 430 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 431 return eptype | 0x4; 432 else 433 return eptype; 434 } 435 436 static u_int 437 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 438 { 439 /* xHCI 1.0 section 4.5.1 */ 440 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 441 u_int in = 0; 442 443 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 444 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 445 in = 1; 446 447 return epaddr * 2 + in; 448 } 449 450 static inline u_int 451 xhci_dci_to_ici(const u_int i) 452 { 453 return i + 1; 454 } 455 456 static inline void * 457 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 458 const u_int dci) 459 { 460 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 461 } 462 463 #if 0 /* unused */ 464 static inline bus_addr_t 465 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 466 const u_int dci) 467 { 468 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 469 } 470 #endif /* unused */ 471 472 static inline void * 473 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline bus_addr_t 480 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 481 const u_int ici) 482 { 483 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 484 } 485 486 static inline struct xhci_trb * 487 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 488 { 489 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 490 } 491 492 static inline bus_addr_t 493 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 494 { 495 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 496 } 497 498 static inline void 499 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 500 uint32_t control) 501 { 502 trb->trb_0 = htole64(parameter); 503 trb->trb_2 = htole32(status); 504 trb->trb_3 = htole32(control); 505 } 506 507 static int 508 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 509 { 510 /* base address of TRBs */ 511 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 512 513 /* trb_0 range sanity check */ 514 if (trb_0 == 0 || trb_0 < trbp || 515 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 516 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 517 return 1; 518 } 519 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 520 return 0; 521 } 522 523 static unsigned int 524 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 525 u_int dci) 526 { 527 uint32_t *cp; 528 529 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 530 cp = xhci_slot_get_dcv(sc, xs, dci); 531 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 532 } 533 534 static inline unsigned int 535 xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport) 536 { 537 const unsigned int port = ctlrport - 1; 538 const uint8_t bit = __BIT(port % NBBY); 539 540 return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit); 541 } 542 543 /* 544 * Return the roothub port for a controller port. Both are 1..n. 545 */ 546 static inline unsigned int 547 xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport) 548 { 549 550 return sc->sc_ctlrportmap[ctrlport - 1]; 551 } 552 553 /* 554 * Return the controller port for a bus roothub port. Both are 1..n. 555 */ 556 static inline unsigned int 557 xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn, 558 unsigned int rhport) 559 { 560 561 return sc->sc_rhportmap[bn][rhport - 1]; 562 } 563 564 /* --- */ 565 566 void 567 xhci_childdet(device_t self, device_t child) 568 { 569 struct xhci_softc * const sc = device_private(self); 570 571 KASSERT(sc->sc_child == child); 572 if (child == sc->sc_child) 573 sc->sc_child = NULL; 574 } 575 576 int 577 xhci_detach(struct xhci_softc *sc, int flags) 578 { 579 int rv = 0; 580 581 if (sc->sc_child2 != NULL) { 582 rv = config_detach(sc->sc_child2, flags); 583 if (rv != 0) 584 return rv; 585 KASSERT(sc->sc_child2 == NULL); 586 } 587 588 if (sc->sc_child != NULL) { 589 rv = config_detach(sc->sc_child, flags); 590 if (rv != 0) 591 return rv; 592 KASSERT(sc->sc_child == NULL); 593 } 594 595 /* XXX unconfigure/free slots */ 596 597 /* verify: */ 598 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 599 xhci_op_write_4(sc, XHCI_USBCMD, 0); 600 /* do we need to wait for stop? */ 601 602 xhci_op_write_8(sc, XHCI_CRCR, 0); 603 xhci_ring_free(sc, &sc->sc_cr); 604 cv_destroy(&sc->sc_command_cv); 605 cv_destroy(&sc->sc_cmdbusy_cv); 606 607 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 608 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 609 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 610 xhci_ring_free(sc, &sc->sc_er); 611 612 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 613 614 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 615 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 616 617 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 618 619 kmem_free(sc->sc_ctlrportbus, 620 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY)); 621 kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int)); 622 623 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 624 kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int)); 625 } 626 627 mutex_destroy(&sc->sc_lock); 628 mutex_destroy(&sc->sc_intr_lock); 629 630 pool_cache_destroy(sc->sc_xferpool); 631 632 return rv; 633 } 634 635 int 636 xhci_activate(device_t self, enum devact act) 637 { 638 struct xhci_softc * const sc = device_private(self); 639 640 switch (act) { 641 case DVACT_DEACTIVATE: 642 sc->sc_dying = true; 643 return 0; 644 default: 645 return EOPNOTSUPP; 646 } 647 } 648 649 bool 650 xhci_suspend(device_t dv, const pmf_qual_t *qual) 651 { 652 return false; 653 } 654 655 bool 656 xhci_resume(device_t dv, const pmf_qual_t *qual) 657 { 658 return false; 659 } 660 661 bool 662 xhci_shutdown(device_t self, int flags) 663 { 664 return false; 665 } 666 667 static int 668 xhci_hc_reset(struct xhci_softc * const sc) 669 { 670 uint32_t usbcmd, usbsts; 671 int i; 672 673 /* Check controller not ready */ 674 for (i = 0; i < XHCI_WAIT_CNR; i++) { 675 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 676 if ((usbsts & XHCI_STS_CNR) == 0) 677 break; 678 usb_delay_ms(&sc->sc_bus, 1); 679 } 680 if (i >= XHCI_WAIT_CNR) { 681 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 682 return EIO; 683 } 684 685 /* Halt controller */ 686 usbcmd = 0; 687 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 688 usb_delay_ms(&sc->sc_bus, 1); 689 690 /* Reset controller */ 691 usbcmd = XHCI_CMD_HCRST; 692 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 693 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 694 /* 695 * Wait 1ms first. Existing Intel xHCI requies 1ms delay to 696 * prevent system hang (Errata). 697 */ 698 usb_delay_ms(&sc->sc_bus, 1); 699 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 700 if ((usbcmd & XHCI_CMD_HCRST) == 0) 701 break; 702 } 703 if (i >= XHCI_WAIT_HCRST) { 704 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 705 return EIO; 706 } 707 708 /* Check controller not ready */ 709 for (i = 0; i < XHCI_WAIT_CNR; i++) { 710 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 711 if ((usbsts & XHCI_STS_CNR) == 0) 712 break; 713 usb_delay_ms(&sc->sc_bus, 1); 714 } 715 if (i >= XHCI_WAIT_CNR) { 716 aprint_error_dev(sc->sc_dev, 717 "controller not ready timeout after reset\n"); 718 return EIO; 719 } 720 721 return 0; 722 } 723 724 725 static void 726 hexdump(const char *msg, const void *base, size_t len) 727 { 728 #if 0 729 size_t cnt; 730 const uint32_t *p; 731 extern paddr_t vtophys(vaddr_t); 732 733 p = base; 734 cnt = 0; 735 736 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 737 (void *)vtophys((vaddr_t)base)); 738 739 while (cnt < len) { 740 if (cnt % 16 == 0) 741 printf("%p: ", p); 742 else if (cnt % 8 == 0) 743 printf(" |"); 744 printf(" %08x", *p++); 745 cnt += 4; 746 if (cnt % 16 == 0) 747 printf("\n"); 748 } 749 if (cnt % 16 != 0) 750 printf("\n"); 751 #endif 752 } 753 754 /* 7.2 xHCI Support Protocol Capability */ 755 static void 756 xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp) 757 { 758 /* XXX Cache this lot */ 759 760 const uint32_t w0 = xhci_read_4(sc, ecp); 761 const uint32_t w4 = xhci_read_4(sc, ecp + 4); 762 const uint32_t w8 = xhci_read_4(sc, ecp + 8); 763 const uint32_t wc = xhci_read_4(sc, ecp + 0xc); 764 765 aprint_debug_dev(sc->sc_dev, 766 " SP: %08x %08x %08x %08x\n", w0, w4, w8, wc); 767 768 if (w4 != XHCI_XECP_USBID) 769 return; 770 771 const int major = XHCI_XECP_SP_W0_MAJOR(w0); 772 const int minor = XHCI_XECP_SP_W0_MINOR(w0); 773 const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8); 774 const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8); 775 776 const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16)); 777 switch (mm) { 778 case 0x0200: 779 case 0x0300: 780 case 0x0301: 781 aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n", 782 major == 3 ? "ss" : "hs", cpo, cpo + cpc -1); 783 break; 784 default: 785 aprint_debug_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n", 786 major, minor); 787 return; 788 } 789 790 const size_t bus = (major == 3) ? 0 : 1; 791 792 /* Index arrays with 0..n-1 where ports are numbered 1..n */ 793 for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) { 794 if (sc->sc_ctlrportmap[cp] != 0) { 795 aprint_error_dev(sc->sc_dev, "contoller port %zu " 796 "already assigned", cp); 797 continue; 798 } 799 800 sc->sc_ctlrportbus[cp / NBBY] |= 801 bus == 0 ? 0 : __BIT(cp % NBBY); 802 803 const size_t rhp = sc->sc_rhportcount[bus]++; 804 805 KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0, 806 "bus %zu rhp %zu is %d", bus, rhp, 807 sc->sc_rhportmap[bus][rhp]); 808 809 sc->sc_rhportmap[bus][rhp] = cp + 1; 810 sc->sc_ctlrportmap[cp] = rhp + 1; 811 } 812 } 813 814 /* Process extended capabilities */ 815 static void 816 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 817 { 818 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 819 820 bus_size_t ecp = XHCI_HCC_XECP(hcc) * 4; 821 while (ecp != 0) { 822 uint32_t ecr = xhci_read_4(sc, ecp); 823 aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr); 824 switch (XHCI_XECP_ID(ecr)) { 825 case XHCI_ID_PROTOCOLS: { 826 xhci_id_protocols(sc, ecp); 827 break; 828 } 829 case XHCI_ID_USB_LEGACY: { 830 uint8_t bios_sem; 831 832 /* Take host controller ownership from BIOS */ 833 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 834 if (bios_sem) { 835 /* sets xHCI to be owned by OS */ 836 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 837 aprint_debug_dev(sc->sc_dev, 838 "waiting for BIOS to give up control\n"); 839 for (int i = 0; i < 5000; i++) { 840 bios_sem = xhci_read_1(sc, ecp + 841 XHCI_XECP_BIOS_SEM); 842 if (bios_sem == 0) 843 break; 844 DELAY(1000); 845 } 846 if (bios_sem) { 847 aprint_error_dev(sc->sc_dev, 848 "timed out waiting for BIOS\n"); 849 } 850 } 851 break; 852 } 853 default: 854 break; 855 } 856 ecr = xhci_read_4(sc, ecp); 857 if (XHCI_XECP_NEXT(ecr) == 0) { 858 ecp = 0; 859 } else { 860 ecp += XHCI_XECP_NEXT(ecr) * 4; 861 } 862 } 863 } 864 865 #define XHCI_HCCPREV1_BITS \ 866 "\177\020" /* New bitmask */ \ 867 "f\020\020XECP\0" \ 868 "f\014\4MAXPSA\0" \ 869 "b\013CFC\0" \ 870 "b\012SEC\0" \ 871 "b\011SBD\0" \ 872 "b\010FSE\0" \ 873 "b\7NSS\0" \ 874 "b\6LTC\0" \ 875 "b\5LHRC\0" \ 876 "b\4PIND\0" \ 877 "b\3PPC\0" \ 878 "b\2CZC\0" \ 879 "b\1BNC\0" \ 880 "b\0AC64\0" \ 881 "\0" 882 #define XHCI_HCCV1_x_BITS \ 883 "\177\020" /* New bitmask */ \ 884 "f\020\020XECP\0" \ 885 "f\014\4MAXPSA\0" \ 886 "b\013CFC\0" \ 887 "b\012SEC\0" \ 888 "b\011SPC\0" \ 889 "b\010PAE\0" \ 890 "b\7NSS\0" \ 891 "b\6LTC\0" \ 892 "b\5LHRC\0" \ 893 "b\4PIND\0" \ 894 "b\3PPC\0" \ 895 "b\2CSZ\0" \ 896 "b\1BNC\0" \ 897 "b\0AC64\0" \ 898 "\0" 899 900 int 901 xhci_init(struct xhci_softc *sc) 902 { 903 bus_size_t bsz; 904 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 905 uint32_t pagesize, config; 906 int i = 0; 907 uint16_t hciversion; 908 uint8_t caplength; 909 910 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 911 912 /* Set up the bus struct for the usb 3 and usb 2 buses */ 913 sc->sc_bus.ub_methods = &xhci_bus_methods; 914 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 915 sc->sc_bus.ub_revision = USBREV_3_0; 916 sc->sc_bus.ub_usedma = true; 917 sc->sc_bus.ub_hcpriv = sc; 918 919 sc->sc_bus2.ub_methods = &xhci_bus_methods; 920 sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe); 921 sc->sc_bus2.ub_revision = USBREV_2_0; 922 sc->sc_bus2.ub_usedma = true; 923 sc->sc_bus2.ub_hcpriv = sc; 924 sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag; 925 926 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 927 caplength = XHCI_CAP_CAPLENGTH(cap); 928 hciversion = XHCI_CAP_HCIVERSION(cap); 929 930 if (hciversion < XHCI_HCIVERSION_0_96 || 931 hciversion > XHCI_HCIVERSION_1_0) { 932 aprint_normal_dev(sc->sc_dev, 933 "xHCI version %x.%x not known to be supported\n", 934 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 935 } else { 936 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 937 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 938 } 939 940 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 941 &sc->sc_cbh) != 0) { 942 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 943 return ENOMEM; 944 } 945 946 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 947 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 948 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 949 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 950 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 951 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 952 aprint_debug_dev(sc->sc_dev, 953 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 954 955 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 956 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 957 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 958 959 char sbuf[128]; 960 if (hciversion < XHCI_HCIVERSION_1_0) 961 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 962 else 963 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 964 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 965 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 966 967 /* default all ports to bus 0, i.e. usb 3 */ 968 sc->sc_ctlrportbus = kmem_zalloc( 969 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP); 970 sc->sc_ctlrportmap = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 971 972 /* controller port to bus roothub port map */ 973 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 974 sc->sc_rhportmap[j] = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 975 } 976 977 /* 978 * Process all Extended Capabilities 979 */ 980 xhci_ecp(sc, hcc); 981 982 bsz = XHCI_PORTSC(sc->sc_maxports); 983 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 984 &sc->sc_obh) != 0) { 985 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 986 return ENOMEM; 987 } 988 989 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 990 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 991 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 992 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 993 return ENOMEM; 994 } 995 996 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 997 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 998 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 999 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 1000 return ENOMEM; 1001 } 1002 1003 int rv; 1004 rv = xhci_hc_reset(sc); 1005 if (rv != 0) { 1006 return rv; 1007 } 1008 1009 if (sc->sc_vendor_init) 1010 sc->sc_vendor_init(sc); 1011 1012 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 1013 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 1014 pagesize = ffs(pagesize); 1015 if (pagesize == 0) { 1016 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 1017 return EIO; 1018 } 1019 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 1020 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 1021 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 1022 (uint32_t)sc->sc_maxslots); 1023 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 1024 1025 usbd_status err; 1026 1027 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 1028 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 1029 if (sc->sc_maxspbuf != 0) { 1030 err = usb_allocmem(&sc->sc_bus, 1031 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 1032 &sc->sc_spbufarray_dma); 1033 if (err) { 1034 aprint_error_dev(sc->sc_dev, 1035 "spbufarray init fail, err %d\n", err); 1036 return ENOMEM; 1037 } 1038 1039 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 1040 sc->sc_maxspbuf, KM_SLEEP); 1041 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 1042 for (i = 0; i < sc->sc_maxspbuf; i++) { 1043 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 1044 /* allocate contexts */ 1045 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 1046 sc->sc_pgsz, dma); 1047 if (err) { 1048 aprint_error_dev(sc->sc_dev, 1049 "spbufarray_dma init fail, err %d\n", err); 1050 rv = ENOMEM; 1051 goto bad1; 1052 } 1053 spbufarray[i] = htole64(DMAADDR(dma, 0)); 1054 usb_syncmem(dma, 0, sc->sc_pgsz, 1055 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1056 } 1057 1058 usb_syncmem(&sc->sc_spbufarray_dma, 0, 1059 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 1060 } 1061 1062 config = xhci_op_read_4(sc, XHCI_CONFIG); 1063 config &= ~0xFF; 1064 config |= sc->sc_maxslots & 0xFF; 1065 xhci_op_write_4(sc, XHCI_CONFIG, config); 1066 1067 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 1068 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 1069 if (err) { 1070 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 1071 err); 1072 rv = ENOMEM; 1073 goto bad1; 1074 } 1075 1076 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 1077 XHCI_EVENT_RING_SEGMENTS_ALIGN); 1078 if (err) { 1079 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 1080 err); 1081 rv = ENOMEM; 1082 goto bad2; 1083 } 1084 1085 usb_dma_t *dma; 1086 size_t size; 1087 size_t align; 1088 1089 dma = &sc->sc_eventst_dma; 1090 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 1091 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 1092 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 1093 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 1094 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1095 if (err) { 1096 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 1097 err); 1098 rv = ENOMEM; 1099 goto bad3; 1100 } 1101 1102 memset(KERNADDR(dma, 0), 0, size); 1103 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1104 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 1105 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 1106 KERNADDR(&sc->sc_eventst_dma, 0), 1107 sc->sc_eventst_dma.udma_block->size); 1108 1109 dma = &sc->sc_dcbaa_dma; 1110 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 1111 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 1112 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 1113 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1114 if (err) { 1115 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1116 rv = ENOMEM; 1117 goto bad4; 1118 } 1119 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 1120 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1121 KERNADDR(&sc->sc_dcbaa_dma, 0), 1122 sc->sc_dcbaa_dma.udma_block->size); 1123 1124 memset(KERNADDR(dma, 0), 0, size); 1125 if (sc->sc_maxspbuf != 0) { 1126 /* 1127 * DCBA entry 0 hold the scratchbuf array pointer. 1128 */ 1129 *(uint64_t *)KERNADDR(dma, 0) = 1130 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1131 } 1132 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1133 1134 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1135 KM_SLEEP); 1136 if (sc->sc_slots == NULL) { 1137 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1138 rv = ENOMEM; 1139 goto bad; 1140 } 1141 1142 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1143 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1144 if (sc->sc_xferpool == NULL) { 1145 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1146 err); 1147 rv = ENOMEM; 1148 goto bad; 1149 } 1150 1151 cv_init(&sc->sc_command_cv, "xhcicmd"); 1152 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1153 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1154 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1155 1156 struct xhci_erste *erst; 1157 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1158 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1159 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1160 erst[0].erste_3 = htole32(0); 1161 usb_syncmem(&sc->sc_eventst_dma, 0, 1162 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1163 1164 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1165 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1166 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1167 XHCI_ERDP_LO_BUSY); 1168 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1169 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1170 sc->sc_cr.xr_cs); 1171 1172 #if 0 1173 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1174 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1175 #endif 1176 1177 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 1178 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 1179 /* Intel xhci needs interrupt rate moderated. */ 1180 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 1181 else 1182 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 1183 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 1184 xhci_rt_read_4(sc, XHCI_IMOD(0))); 1185 1186 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 1187 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 1188 xhci_op_read_4(sc, XHCI_USBCMD)); 1189 1190 return 0; 1191 1192 bad: 1193 if (sc->sc_xferpool) { 1194 pool_cache_destroy(sc->sc_xferpool); 1195 sc->sc_xferpool = NULL; 1196 } 1197 1198 if (sc->sc_slots) { 1199 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1200 sc->sc_maxslots); 1201 sc->sc_slots = NULL; 1202 } 1203 1204 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1205 bad4: 1206 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1207 bad3: 1208 xhci_ring_free(sc, &sc->sc_er); 1209 bad2: 1210 xhci_ring_free(sc, &sc->sc_cr); 1211 i = sc->sc_maxspbuf; 1212 bad1: 1213 for (int j = 0; j < i; j++) 1214 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1215 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1216 1217 return rv; 1218 } 1219 1220 static inline bool 1221 xhci_polling_p(struct xhci_softc * const sc) 1222 { 1223 return sc->sc_bus.ub_usepolling || sc->sc_bus2.ub_usepolling; 1224 } 1225 1226 int 1227 xhci_intr(void *v) 1228 { 1229 struct xhci_softc * const sc = v; 1230 int ret = 0; 1231 1232 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1233 1234 if (sc == NULL) 1235 return 0; 1236 1237 mutex_spin_enter(&sc->sc_intr_lock); 1238 1239 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1240 goto done; 1241 1242 /* If we get an interrupt while polling, then just ignore it. */ 1243 if (xhci_polling_p(sc)) { 1244 #ifdef DIAGNOSTIC 1245 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1246 #endif 1247 goto done; 1248 } 1249 1250 ret = xhci_intr1(sc); 1251 if (ret) { 1252 KASSERT(sc->sc_child || sc->sc_child2); 1253 1254 /* 1255 * One of child busses could be already detached. It doesn't 1256 * matter on which of the two the softintr is scheduled. 1257 */ 1258 if (sc->sc_child) 1259 usb_schedsoftintr(&sc->sc_bus); 1260 else 1261 usb_schedsoftintr(&sc->sc_bus2); 1262 } 1263 done: 1264 mutex_spin_exit(&sc->sc_intr_lock); 1265 return ret; 1266 } 1267 1268 int 1269 xhci_intr1(struct xhci_softc * const sc) 1270 { 1271 uint32_t usbsts; 1272 uint32_t iman; 1273 1274 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1275 1276 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1277 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1278 if ((usbsts & (XHCI_STS_HSE | XHCI_STS_EINT | XHCI_STS_PCD | 1279 XHCI_STS_HCE)) == 0) { 1280 DPRINTFN(16, "ignored intr not for %s", 1281 device_xname(sc->sc_dev), 0, 0, 0); 1282 return 0; 1283 } 1284 1285 /* 1286 * Clear EINT and other transient flags, to not misenterpret 1287 * next shared interrupt. Also, to avoid race, EINT must be cleared 1288 * before XHCI_IMAN_INTR_PEND is cleared. 1289 */ 1290 xhci_op_write_4(sc, XHCI_USBSTS, usbsts & XHCI_STS_RSVDP0); 1291 1292 #ifdef XHCI_DEBUG 1293 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1294 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1295 #endif 1296 1297 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1298 DPRINTFN(16, "IMAN0 %08jx", iman, 0, 0, 0); 1299 iman |= XHCI_IMAN_INTR_PEND; 1300 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1301 1302 #ifdef XHCI_DEBUG 1303 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1304 DPRINTFN(16, "IMAN0 %08jx", iman, 0, 0, 0); 1305 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1306 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1307 #endif 1308 1309 return 1; 1310 } 1311 1312 /* 1313 * 3 port speed types used in USB stack 1314 * 1315 * usbdi speed 1316 * definition: USB_SPEED_* in usb.h 1317 * They are used in struct usbd_device in USB stack. 1318 * ioctl interface uses these values too. 1319 * port_status speed 1320 * definition: UPS_*_SPEED in usb.h 1321 * They are used in usb_port_status_t and valid only for USB 2.0. 1322 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1323 * of usb_port_status_ext_t indicates port speed. 1324 * Note that some 3.0 values overlap with 2.0 values. 1325 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1326 * means UPS_LOW_SPEED in HS.) 1327 * port status returned from hub also uses these values. 1328 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1329 * or more. 1330 * xspeed: 1331 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1332 * They are used in only slot context and PORTSC reg of xhci. 1333 * The difference between usbdi speed and xspeed is 1334 * that FS and LS values are swapped. 1335 */ 1336 1337 /* convert usbdi speed to xspeed */ 1338 static int 1339 xhci_speed2xspeed(int speed) 1340 { 1341 switch (speed) { 1342 case USB_SPEED_LOW: return 2; 1343 case USB_SPEED_FULL: return 1; 1344 default: return speed; 1345 } 1346 } 1347 1348 #if 0 1349 /* convert xspeed to usbdi speed */ 1350 static int 1351 xhci_xspeed2speed(int xspeed) 1352 { 1353 switch (xspeed) { 1354 case 1: return USB_SPEED_FULL; 1355 case 2: return USB_SPEED_LOW; 1356 default: return xspeed; 1357 } 1358 } 1359 #endif 1360 1361 /* convert xspeed to port status speed */ 1362 static int 1363 xhci_xspeed2psspeed(int xspeed) 1364 { 1365 switch (xspeed) { 1366 case 0: return 0; 1367 case 1: return UPS_FULL_SPEED; 1368 case 2: return UPS_LOW_SPEED; 1369 case 3: return UPS_HIGH_SPEED; 1370 default: return UPS_OTHER_SPEED; 1371 } 1372 } 1373 1374 /* 1375 * Construct input contexts and issue TRB to open pipe. 1376 */ 1377 static usbd_status 1378 xhci_configure_endpoint(struct usbd_pipe *pipe) 1379 { 1380 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1381 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1382 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1383 struct xhci_trb trb; 1384 usbd_status err; 1385 1386 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1387 DPRINTFN(4, "slot %ju dci %ju epaddr 0x%02jx attr 0x%02jx", 1388 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1389 pipe->up_endpoint->ue_edesc->bmAttributes); 1390 1391 /* XXX ensure input context is available? */ 1392 1393 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1394 1395 /* set up context */ 1396 xhci_setup_ctx(pipe); 1397 1398 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1399 sc->sc_ctxsz * 1); 1400 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1401 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1402 1403 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1404 trb.trb_2 = 0; 1405 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1406 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1407 1408 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1409 1410 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1411 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1412 sc->sc_ctxsz * 1); 1413 1414 return err; 1415 } 1416 1417 #if 0 1418 static usbd_status 1419 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1420 { 1421 #ifdef USB_DEBUG 1422 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1423 #endif 1424 1425 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1426 DPRINTFN(4, "slot %ju", xs->xs_idx, 0, 0, 0); 1427 1428 return USBD_NORMAL_COMPLETION; 1429 } 1430 #endif 1431 1432 /* 4.6.8, 6.4.3.7 */ 1433 static usbd_status 1434 xhci_reset_endpoint_locked(struct usbd_pipe *pipe) 1435 { 1436 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1437 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1438 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1439 struct xhci_trb trb; 1440 usbd_status err; 1441 1442 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1443 DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1444 1445 KASSERT(mutex_owned(&sc->sc_lock)); 1446 1447 trb.trb_0 = 0; 1448 trb.trb_2 = 0; 1449 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1450 XHCI_TRB_3_EP_SET(dci) | 1451 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1452 1453 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1454 1455 return err; 1456 } 1457 1458 static usbd_status 1459 xhci_reset_endpoint(struct usbd_pipe *pipe) 1460 { 1461 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1462 1463 mutex_enter(&sc->sc_lock); 1464 usbd_status ret = xhci_reset_endpoint_locked(pipe); 1465 mutex_exit(&sc->sc_lock); 1466 1467 return ret; 1468 } 1469 1470 /* 1471 * 4.6.9, 6.4.3.8 1472 * Stop execution of TDs on xfer ring. 1473 * Should be called with sc_lock held. 1474 */ 1475 static usbd_status 1476 xhci_stop_endpoint(struct usbd_pipe *pipe) 1477 { 1478 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1479 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1480 struct xhci_trb trb; 1481 usbd_status err; 1482 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1483 1484 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1485 DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1486 1487 KASSERT(mutex_owned(&sc->sc_lock)); 1488 1489 trb.trb_0 = 0; 1490 trb.trb_2 = 0; 1491 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1492 XHCI_TRB_3_EP_SET(dci) | 1493 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1494 1495 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1496 1497 return err; 1498 } 1499 1500 /* 1501 * Set TR Dequeue Pointer. 1502 * xHCI 1.1 4.6.10 6.4.3.9 1503 * Purge all of the TRBs on ring and reinitialize ring. 1504 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1505 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1506 * error will be generated. 1507 */ 1508 static usbd_status 1509 xhci_set_dequeue_locked(struct usbd_pipe *pipe) 1510 { 1511 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1512 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1513 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1514 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1515 struct xhci_trb trb; 1516 usbd_status err; 1517 1518 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1519 DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1520 1521 KASSERT(mutex_owned(&sc->sc_lock)); 1522 1523 xhci_host_dequeue(xr); 1524 1525 /* set DCS */ 1526 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1527 trb.trb_2 = 0; 1528 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1529 XHCI_TRB_3_EP_SET(dci) | 1530 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1531 1532 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1533 1534 return err; 1535 } 1536 1537 static usbd_status 1538 xhci_set_dequeue(struct usbd_pipe *pipe) 1539 { 1540 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1541 1542 mutex_enter(&sc->sc_lock); 1543 usbd_status ret = xhci_set_dequeue_locked(pipe); 1544 mutex_exit(&sc->sc_lock); 1545 1546 return ret; 1547 } 1548 1549 /* 1550 * Open new pipe: called from usbd_setup_pipe_flags. 1551 * Fills methods of pipe. 1552 * If pipe is not for ep0, calls configure_endpoint. 1553 */ 1554 static usbd_status 1555 xhci_open(struct usbd_pipe *pipe) 1556 { 1557 struct usbd_device * const dev = pipe->up_dev; 1558 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1559 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1560 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1561 1562 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1563 DPRINTFN(1, "addr %jd depth %jd port %jd speed %jd", dev->ud_addr, 1564 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1565 DPRINTFN(1, " dci %ju type 0x%02jx epaddr 0x%02jx attr 0x%02jx", 1566 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1567 ed->bmAttributes); 1568 DPRINTFN(1, " mps %ju ival %ju", UGETW(ed->wMaxPacketSize), 1569 ed->bInterval, 0, 0); 1570 1571 if (sc->sc_dying) 1572 return USBD_IOERROR; 1573 1574 /* Root Hub */ 1575 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1576 switch (ed->bEndpointAddress) { 1577 case USB_CONTROL_ENDPOINT: 1578 pipe->up_methods = &roothub_ctrl_methods; 1579 break; 1580 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1581 pipe->up_methods = &xhci_root_intr_methods; 1582 break; 1583 default: 1584 pipe->up_methods = NULL; 1585 DPRINTFN(0, "bad bEndpointAddress 0x%02jx", 1586 ed->bEndpointAddress, 0, 0, 0); 1587 return USBD_INVAL; 1588 } 1589 return USBD_NORMAL_COMPLETION; 1590 } 1591 1592 switch (xfertype) { 1593 case UE_CONTROL: 1594 pipe->up_methods = &xhci_device_ctrl_methods; 1595 break; 1596 case UE_ISOCHRONOUS: 1597 pipe->up_methods = &xhci_device_isoc_methods; 1598 return USBD_INVAL; 1599 break; 1600 case UE_BULK: 1601 pipe->up_methods = &xhci_device_bulk_methods; 1602 break; 1603 case UE_INTERRUPT: 1604 pipe->up_methods = &xhci_device_intr_methods; 1605 break; 1606 default: 1607 return USBD_IOERROR; 1608 break; 1609 } 1610 1611 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1612 return xhci_configure_endpoint(pipe); 1613 1614 return USBD_NORMAL_COMPLETION; 1615 } 1616 1617 /* 1618 * Closes pipe, called from usbd_kill_pipe via close methods. 1619 * If the endpoint to be closed is ep0, disable_slot. 1620 * Should be called with sc_lock held. 1621 */ 1622 static void 1623 xhci_close_pipe(struct usbd_pipe *pipe) 1624 { 1625 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1626 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1627 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1628 const u_int dci = xhci_ep_get_dci(ed); 1629 struct xhci_trb trb; 1630 uint32_t *cp; 1631 1632 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1633 1634 if (sc->sc_dying) 1635 return; 1636 1637 /* xs is uninitialized before xhci_init_slot */ 1638 if (xs == NULL || xs->xs_idx == 0) 1639 return; 1640 1641 DPRINTFN(4, "pipe %#jx slot %ju dci %ju", (uintptr_t)pipe, xs->xs_idx, 1642 dci, 0); 1643 1644 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1645 KASSERT(mutex_owned(&sc->sc_lock)); 1646 1647 if (pipe->up_dev->ud_depth == 0) 1648 return; 1649 1650 if (dci == XHCI_DCI_EP_CONTROL) { 1651 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1652 xhci_disable_slot(sc, xs->xs_idx); 1653 return; 1654 } 1655 1656 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED) 1657 (void)xhci_stop_endpoint(pipe); 1658 1659 /* 1660 * set appropriate bit to be dropped. 1661 * don't set DC bit to 1, otherwise all endpoints 1662 * would be deconfigured. 1663 */ 1664 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1665 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1666 cp[1] = htole32(0); 1667 1668 /* XXX should be most significant one, not dci? */ 1669 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1670 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1671 1672 /* configure ep context performs an implicit dequeue */ 1673 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 1674 1675 /* sync input contexts before they are read from memory */ 1676 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1677 1678 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1679 trb.trb_2 = 0; 1680 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1681 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1682 1683 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1684 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1685 } 1686 1687 /* 1688 * Abort transfer. 1689 * Should be called with sc_lock held. 1690 */ 1691 static void 1692 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1693 { 1694 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1695 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1696 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1697 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1698 1699 KASSERTMSG((status == USBD_CANCELLED || status == USBD_TIMEOUT), 1700 "invalid status for abort: %d", (int)status); 1701 1702 DPRINTFN(4, "xfer %#jx pipe %#jx status %jd", 1703 (uintptr_t)xfer, (uintptr_t)xfer->ux_pipe, status, 0); 1704 1705 KASSERT(mutex_owned(&sc->sc_lock)); 1706 ASSERT_SLEEPABLE(); 1707 1708 if (status == USBD_CANCELLED) { 1709 /* 1710 * We are synchronously aborting. Try to stop the 1711 * callout and task, but if we can't, wait for them to 1712 * complete. 1713 */ 1714 callout_halt(&xfer->ux_callout, &sc->sc_lock); 1715 usb_rem_task_wait(xfer->ux_pipe->up_dev, &xfer->ux_aborttask, 1716 USB_TASKQ_HC, &sc->sc_lock); 1717 } else { 1718 /* Otherwise, we are timing out. */ 1719 KASSERT(status == USBD_TIMEOUT); 1720 } 1721 1722 /* 1723 * The xfer cannot have been cancelled already. It is the 1724 * responsibility of the caller of usbd_abort_pipe not to try 1725 * to abort a pipe multiple times, whether concurrently or 1726 * sequentially. 1727 */ 1728 KASSERT(xfer->ux_status != USBD_CANCELLED); 1729 1730 /* Only the timeout, which runs only once, can time it out. */ 1731 KASSERT(xfer->ux_status != USBD_TIMEOUT); 1732 1733 /* If anyone else beat us, we're done. */ 1734 if (xfer->ux_status != USBD_IN_PROGRESS) 1735 return; 1736 1737 /* We beat everyone else. Claim the status. */ 1738 xfer->ux_status = status; 1739 1740 /* 1741 * If we're dying, skip the hardware action and just notify the 1742 * software that we're done. 1743 */ 1744 if (sc->sc_dying) { 1745 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 1746 xfer->ux_status, 0, 0); 1747 goto dying; 1748 } 1749 1750 /* 1751 * HC Step 1: Stop execution of TD on the ring. 1752 */ 1753 switch (xhci_get_epstate(sc, xs, dci)) { 1754 case XHCI_EPSTATE_HALTED: 1755 (void)xhci_reset_endpoint_locked(xfer->ux_pipe); 1756 break; 1757 case XHCI_EPSTATE_STOPPED: 1758 break; 1759 default: 1760 (void)xhci_stop_endpoint(xfer->ux_pipe); 1761 break; 1762 } 1763 #ifdef DIAGNOSTIC 1764 uint32_t epst = xhci_get_epstate(sc, xs, dci); 1765 if (epst != XHCI_EPSTATE_STOPPED) 1766 DPRINTFN(4, "dci %ju not stopped %ju", dci, epst, 0, 0); 1767 #endif 1768 1769 /* 1770 * HC Step 2: Remove any vestiges of the xfer from the ring. 1771 */ 1772 xhci_set_dequeue_locked(xfer->ux_pipe); 1773 1774 /* 1775 * Final Step: Notify completion to waiting xfers. 1776 */ 1777 dying: 1778 usb_transfer_complete(xfer); 1779 DPRINTFN(14, "end", 0, 0, 0, 0); 1780 1781 KASSERT(mutex_owned(&sc->sc_lock)); 1782 } 1783 1784 static void 1785 xhci_host_dequeue(struct xhci_ring * const xr) 1786 { 1787 /* When dequeueing the controller, update our struct copy too */ 1788 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1789 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1790 BUS_DMASYNC_PREWRITE); 1791 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1792 1793 xr->xr_ep = 0; 1794 xr->xr_cs = 1; 1795 } 1796 1797 /* 1798 * Recover STALLed endpoint. 1799 * xHCI 1.1 sect 4.10.2.1 1800 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1801 * all transfers on transfer ring. 1802 * These are done in thread context asynchronously. 1803 */ 1804 static void 1805 xhci_clear_endpoint_stall_async_task(void *cookie) 1806 { 1807 struct usbd_xfer * const xfer = cookie; 1808 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1809 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1810 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1811 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1812 1813 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1814 DPRINTFN(4, "xfer %#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, 1815 dci, 0); 1816 1817 xhci_reset_endpoint(xfer->ux_pipe); 1818 xhci_set_dequeue(xfer->ux_pipe); 1819 1820 mutex_enter(&sc->sc_lock); 1821 tr->is_halted = false; 1822 usb_transfer_complete(xfer); 1823 mutex_exit(&sc->sc_lock); 1824 DPRINTFN(4, "ends", 0, 0, 0, 0); 1825 } 1826 1827 static usbd_status 1828 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1829 { 1830 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1831 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1832 1833 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1834 DPRINTFN(4, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 1835 1836 if (sc->sc_dying) { 1837 return USBD_IOERROR; 1838 } 1839 1840 usb_init_task(&xp->xp_async_task, 1841 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1842 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1843 DPRINTFN(4, "ends", 0, 0, 0, 0); 1844 1845 return USBD_NORMAL_COMPLETION; 1846 } 1847 1848 /* Process roothub port status/change events and notify to uhub_intr. */ 1849 static void 1850 xhci_rhpsc(struct xhci_softc * const sc, u_int ctlrport) 1851 { 1852 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1853 DPRINTFN(4, "xhci%jd: port %ju status change", device_unit(sc->sc_dev), 1854 ctlrport, 0, 0); 1855 1856 if (ctlrport > sc->sc_maxports) 1857 return; 1858 1859 const size_t bn = xhci_ctlrport2bus(sc, ctlrport); 1860 const size_t rhp = xhci_ctlrport2rhport(sc, ctlrport); 1861 struct usbd_xfer * const xfer = sc->sc_intrxfer[bn]; 1862 1863 DPRINTFN(4, "xhci%jd: bus %jd bp %ju xfer %#jx status change", 1864 device_unit(sc->sc_dev), bn, rhp, (uintptr_t)xfer); 1865 1866 if (xfer == NULL) 1867 return; 1868 1869 uint8_t *p = xfer->ux_buf; 1870 memset(p, 0, xfer->ux_length); 1871 p[rhp / NBBY] |= 1 << (rhp % NBBY); 1872 xfer->ux_actlen = xfer->ux_length; 1873 xfer->ux_status = USBD_NORMAL_COMPLETION; 1874 usb_transfer_complete(xfer); 1875 } 1876 1877 /* Process Transfer Events */ 1878 static void 1879 xhci_event_transfer(struct xhci_softc * const sc, 1880 const struct xhci_trb * const trb) 1881 { 1882 uint64_t trb_0; 1883 uint32_t trb_2, trb_3; 1884 uint8_t trbcode; 1885 u_int slot, dci; 1886 struct xhci_slot *xs; 1887 struct xhci_ring *xr; 1888 struct xhci_xfer *xx; 1889 struct usbd_xfer *xfer; 1890 usbd_status err; 1891 1892 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1893 1894 trb_0 = le64toh(trb->trb_0); 1895 trb_2 = le32toh(trb->trb_2); 1896 trb_3 = le32toh(trb->trb_3); 1897 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1898 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1899 dci = XHCI_TRB_3_EP_GET(trb_3); 1900 xs = &sc->sc_slots[slot]; 1901 xr = &xs->xs_ep[dci].xe_tr; 1902 1903 /* sanity check */ 1904 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1905 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1906 1907 int idx = 0; 1908 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1909 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1910 DPRINTFN(0, "invalid trb_0 0x%jx", trb_0, 0, 0, 0); 1911 return; 1912 } 1913 xx = xr->xr_cookies[idx]; 1914 1915 /* clear cookie of consumed TRB */ 1916 xr->xr_cookies[idx] = NULL; 1917 1918 /* 1919 * xx is NULL if pipe is opened but xfer is not started. 1920 * It happens when stopping idle pipe. 1921 */ 1922 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1923 DPRINTFN(1, "Ignore #%ju: cookie %#jx cc %ju dci %ju", 1924 idx, (uintptr_t)xx, trbcode, dci); 1925 DPRINTFN(1, " orig TRB %jx type %ju", trb_0, 1926 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1927 0, 0); 1928 return; 1929 } 1930 } else { 1931 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1932 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1933 } 1934 /* XXX this may not happen */ 1935 if (xx == NULL) { 1936 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1937 return; 1938 } 1939 xfer = &xx->xx_xfer; 1940 /* XXX this may happen when detaching */ 1941 if (xfer == NULL) { 1942 DPRINTFN(1, "xx(%#jx)->xx_xfer is NULL trb_0 %#jx", 1943 (uintptr_t)xx, trb_0, 0, 0); 1944 return; 1945 } 1946 DPRINTFN(14, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 1947 /* XXX I dunno why this happens */ 1948 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1949 1950 if (!xfer->ux_pipe->up_repeat && 1951 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1952 DPRINTFN(1, "xfer(%#jx)->pipe not queued", (uintptr_t)xfer, 1953 0, 0, 0); 1954 return; 1955 } 1956 1957 /* 4.11.5.2 Event Data TRB */ 1958 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1959 DPRINTFN(14, "transfer Event Data: 0x%016jx 0x%08jx" 1960 " %02jx", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1961 if ((trb_0 & 0x3) == 0x3) { 1962 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1963 } 1964 } 1965 1966 switch (trbcode) { 1967 case XHCI_TRB_ERROR_SHORT_PKT: 1968 case XHCI_TRB_ERROR_SUCCESS: 1969 /* 1970 * A ctrl transfer can generate two events if it has a Data 1971 * stage. A short data stage can be OK and should not 1972 * complete the transfer as the status stage needs to be 1973 * performed. 1974 * 1975 * Note: Data and Status stage events point at same xfer. 1976 * ux_actlen and ux_dmabuf will be passed to 1977 * usb_transfer_complete after the Status stage event. 1978 * 1979 * It can be distingished which stage generates the event: 1980 * + by checking least 3 bits of trb_0 if ED==1. 1981 * (see xhci_device_ctrl_start). 1982 * + by checking the type of original TRB if ED==0. 1983 * 1984 * In addition, intr, bulk, and isoc transfer currently 1985 * consists of single TD, so the "skip" is not needed. 1986 * ctrl xfer uses EVENT_DATA, and others do not. 1987 * Thus driver can switch the flow by checking ED bit. 1988 */ 1989 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1990 if (xfer->ux_actlen == 0) 1991 xfer->ux_actlen = xfer->ux_length - 1992 XHCI_TRB_2_REM_GET(trb_2); 1993 if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)) 1994 == XHCI_TRB_TYPE_DATA_STAGE) { 1995 return; 1996 } 1997 } else if ((trb_0 & 0x3) == 0x3) { 1998 return; 1999 } 2000 err = USBD_NORMAL_COMPLETION; 2001 break; 2002 case XHCI_TRB_ERROR_STOPPED: 2003 case XHCI_TRB_ERROR_LENGTH: 2004 case XHCI_TRB_ERROR_STOPPED_SHORT: 2005 /* 2006 * don't complete the transfer being aborted 2007 * as abort_xfer does instead. 2008 */ 2009 if (xfer->ux_status == USBD_CANCELLED || 2010 xfer->ux_status == USBD_TIMEOUT) { 2011 DPRINTFN(14, "ignore aborting xfer %#jx", 2012 (uintptr_t)xfer, 0, 0, 0); 2013 return; 2014 } 2015 err = USBD_CANCELLED; 2016 break; 2017 case XHCI_TRB_ERROR_STALL: 2018 case XHCI_TRB_ERROR_BABBLE: 2019 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 2020 xr->is_halted = true; 2021 /* 2022 * Stalled endpoints can be recoverd by issuing 2023 * command TRB TYPE_RESET_EP on xHCI instead of 2024 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 2025 * on the endpoint. However, this function may be 2026 * called from softint context (e.g. from umass), 2027 * in that case driver gets KASSERT in cv_timedwait 2028 * in xhci_do_command. 2029 * To avoid this, this runs reset_endpoint and 2030 * usb_transfer_complete in usb task thread 2031 * asynchronously (and then umass issues clear 2032 * UF_ENDPOINT_HALT). 2033 */ 2034 2035 /* Override the status. */ 2036 xfer->ux_status = USBD_STALLED; 2037 2038 /* 2039 * Cancel the timeout and the task, which have not yet 2040 * run. If they have already fired, at worst they are 2041 * waiting for the lock. They will see that the xfer 2042 * is no longer in progress and give up. 2043 */ 2044 callout_stop(&xfer->ux_callout); 2045 usb_rem_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask); 2046 2047 xhci_clear_endpoint_stall_async(xfer); 2048 return; 2049 default: 2050 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 2051 err = USBD_IOERROR; 2052 break; 2053 } 2054 2055 /* 2056 * If software has completed it, either by cancellation 2057 * or timeout, drop it on the floor. 2058 */ 2059 if (xfer->ux_status != USBD_IN_PROGRESS) { 2060 KASSERTMSG((xfer->ux_status == USBD_CANCELLED || 2061 xfer->ux_status == USBD_TIMEOUT), 2062 "xfer %p status %x", xfer, xfer->ux_status); 2063 return;; 2064 } 2065 2066 /* Otherwise, set the status. */ 2067 xfer->ux_status = err; 2068 2069 /* 2070 * Cancel the timeout and the task, which have not yet 2071 * run. If they have already fired, at worst they are 2072 * waiting for the lock. They will see that the xfer 2073 * is no longer in progress and give up. 2074 */ 2075 callout_stop(&xfer->ux_callout); 2076 usb_rem_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask); 2077 2078 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0 || 2079 (trb_0 & 0x3) == 0x0) { 2080 usb_transfer_complete(xfer); 2081 } 2082 } 2083 2084 /* Process Command complete events */ 2085 static void 2086 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 2087 { 2088 uint64_t trb_0; 2089 uint32_t trb_2, trb_3; 2090 2091 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2092 2093 KASSERT(mutex_owned(&sc->sc_lock)); 2094 2095 trb_0 = le64toh(trb->trb_0); 2096 trb_2 = le32toh(trb->trb_2); 2097 trb_3 = le32toh(trb->trb_3); 2098 2099 if (trb_0 == sc->sc_command_addr) { 2100 sc->sc_resultpending = false; 2101 2102 sc->sc_result_trb.trb_0 = trb_0; 2103 sc->sc_result_trb.trb_2 = trb_2; 2104 sc->sc_result_trb.trb_3 = trb_3; 2105 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2106 XHCI_TRB_ERROR_SUCCESS) { 2107 DPRINTFN(1, "command completion " 2108 "failure: 0x%016jx 0x%08jx 0x%08jx", 2109 trb_0, trb_2, trb_3, 0); 2110 } 2111 cv_signal(&sc->sc_command_cv); 2112 } else { 2113 DPRINTFN(1, "spurious event: %#jx 0x%016jx " 2114 "0x%08jx 0x%08jx", (uintptr_t)trb, trb_0, trb_2, trb_3); 2115 } 2116 } 2117 2118 /* 2119 * Process events. 2120 * called from xhci_softintr 2121 */ 2122 static void 2123 xhci_handle_event(struct xhci_softc * const sc, 2124 const struct xhci_trb * const trb) 2125 { 2126 uint64_t trb_0; 2127 uint32_t trb_2, trb_3; 2128 2129 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2130 2131 trb_0 = le64toh(trb->trb_0); 2132 trb_2 = le32toh(trb->trb_2); 2133 trb_3 = le32toh(trb->trb_3); 2134 2135 DPRINTFN(14, "event: %#jx 0x%016jx 0x%08jx 0x%08jx", 2136 (uintptr_t)trb, trb_0, trb_2, trb_3); 2137 2138 /* 2139 * 4.11.3.1, 6.4.2.1 2140 * TRB Pointer is invalid for these completion codes. 2141 */ 2142 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2143 case XHCI_TRB_ERROR_RING_UNDERRUN: 2144 case XHCI_TRB_ERROR_RING_OVERRUN: 2145 case XHCI_TRB_ERROR_VF_RING_FULL: 2146 return; 2147 default: 2148 if (trb_0 == 0) { 2149 return; 2150 } 2151 break; 2152 } 2153 2154 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2155 case XHCI_TRB_EVENT_TRANSFER: 2156 xhci_event_transfer(sc, trb); 2157 break; 2158 case XHCI_TRB_EVENT_CMD_COMPLETE: 2159 xhci_event_cmd(sc, trb); 2160 break; 2161 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2162 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2163 break; 2164 default: 2165 break; 2166 } 2167 } 2168 2169 static void 2170 xhci_softintr(void *v) 2171 { 2172 struct usbd_bus * const bus = v; 2173 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2174 struct xhci_ring * const er = &sc->sc_er; 2175 struct xhci_trb *trb; 2176 int i, j, k; 2177 2178 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2179 2180 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 2181 2182 i = er->xr_ep; 2183 j = er->xr_cs; 2184 2185 DPRINTFN(16, "er: xr_ep %jd xr_cs %jd", i, j, 0, 0); 2186 2187 while (1) { 2188 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2189 BUS_DMASYNC_POSTREAD); 2190 trb = &er->xr_trb[i]; 2191 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2192 2193 if (j != k) 2194 break; 2195 2196 xhci_handle_event(sc, trb); 2197 2198 i++; 2199 if (i == er->xr_ntrb) { 2200 i = 0; 2201 j ^= 1; 2202 } 2203 } 2204 2205 er->xr_ep = i; 2206 er->xr_cs = j; 2207 2208 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2209 XHCI_ERDP_LO_BUSY); 2210 2211 DPRINTFN(16, "ends", 0, 0, 0, 0); 2212 2213 return; 2214 } 2215 2216 static void 2217 xhci_poll(struct usbd_bus *bus) 2218 { 2219 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2220 2221 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2222 2223 mutex_spin_enter(&sc->sc_intr_lock); 2224 int ret = xhci_intr1(sc); 2225 if (ret) { 2226 xhci_softintr(bus); 2227 } 2228 mutex_spin_exit(&sc->sc_intr_lock); 2229 2230 return; 2231 } 2232 2233 static struct usbd_xfer * 2234 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2235 { 2236 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2237 struct usbd_xfer *xfer; 2238 2239 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2240 2241 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 2242 if (xfer != NULL) { 2243 memset(xfer, 0, sizeof(struct xhci_xfer)); 2244 usb_init_task(&xfer->ux_aborttask, xhci_timeout_task, xfer, 2245 USB_TASKQ_MPSAFE); 2246 #ifdef DIAGNOSTIC 2247 xfer->ux_state = XFER_BUSY; 2248 #endif 2249 } 2250 2251 return xfer; 2252 } 2253 2254 static void 2255 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2256 { 2257 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2258 2259 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2260 2261 #ifdef DIAGNOSTIC 2262 if (xfer->ux_state != XFER_BUSY) { 2263 DPRINTFN(0, "xfer=%#jx not busy, 0x%08jx", 2264 (uintptr_t)xfer, xfer->ux_state, 0, 0); 2265 } 2266 xfer->ux_state = XFER_FREE; 2267 #endif 2268 pool_cache_put(sc->sc_xferpool, xfer); 2269 } 2270 2271 static void 2272 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2273 { 2274 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2275 2276 *lock = &sc->sc_lock; 2277 } 2278 2279 extern uint32_t usb_cookie_no; 2280 2281 /* 2282 * xHCI 4.3 2283 * Called when uhub_explore finds a new device (via usbd_new_device). 2284 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2285 * This function does: 2286 * Allocate and construct dev structure of default endpoint (ep0). 2287 * Allocate and open pipe of ep0. 2288 * Enable slot and initialize slot context. 2289 * Set Address. 2290 * Read initial device descriptor. 2291 * Determine initial MaxPacketSize (mps) by speed. 2292 * Read full device descriptor. 2293 * Register this device. 2294 * Finally state of device transitions ADDRESSED. 2295 */ 2296 static usbd_status 2297 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2298 int speed, int port, struct usbd_port *up) 2299 { 2300 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2301 struct usbd_device *dev; 2302 usbd_status err; 2303 usb_device_descriptor_t *dd; 2304 struct xhci_slot *xs; 2305 uint32_t *cp; 2306 2307 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2308 DPRINTFN(4, "port %ju depth %ju speed %ju up %#jx", 2309 port, depth, speed, (uintptr_t)up); 2310 2311 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2312 dev->ud_bus = bus; 2313 dev->ud_quirks = &usbd_no_quirk; 2314 dev->ud_addr = 0; 2315 dev->ud_ddesc.bMaxPacketSize = 0; 2316 dev->ud_depth = depth; 2317 dev->ud_powersrc = up; 2318 dev->ud_myhub = up->up_parent; 2319 dev->ud_speed = speed; 2320 dev->ud_langid = USBD_NOLANG; 2321 dev->ud_cookie.cookie = ++usb_cookie_no; 2322 2323 /* Set up default endpoint handle. */ 2324 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2325 /* doesn't matter, just don't let it uninitialized */ 2326 dev->ud_ep0.ue_toggle = 0; 2327 2328 /* Set up default endpoint descriptor. */ 2329 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2330 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2331 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2332 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2333 dev->ud_ep0desc.bInterval = 0; 2334 2335 /* 4.3, 4.8.2.1 */ 2336 switch (speed) { 2337 case USB_SPEED_SUPER: 2338 case USB_SPEED_SUPER_PLUS: 2339 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2340 break; 2341 case USB_SPEED_FULL: 2342 /* XXX using 64 as initial mps of ep0 in FS */ 2343 case USB_SPEED_HIGH: 2344 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2345 break; 2346 case USB_SPEED_LOW: 2347 default: 2348 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2349 break; 2350 } 2351 2352 up->up_dev = dev; 2353 2354 /* Establish the default pipe. */ 2355 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2356 &dev->ud_pipe0); 2357 if (err) { 2358 goto bad; 2359 } 2360 2361 dd = &dev->ud_ddesc; 2362 2363 if (depth == 0 && port == 0) { 2364 KASSERT(bus->ub_devices[USB_ROOTHUB_INDEX] == NULL); 2365 bus->ub_devices[USB_ROOTHUB_INDEX] = dev; 2366 err = usbd_get_initial_ddesc(dev, dd); 2367 if (err) { 2368 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2369 goto bad; 2370 } 2371 2372 err = usbd_reload_device_desc(dev); 2373 if (err) { 2374 DPRINTFN(1, "reload desc %ju", err, 0, 0, 0); 2375 goto bad; 2376 } 2377 } else { 2378 uint8_t slot = 0; 2379 2380 /* 4.3.2 */ 2381 err = xhci_enable_slot(sc, &slot); 2382 if (err) { 2383 DPRINTFN(1, "enable slot %ju", err, 0, 0, 0); 2384 goto bad; 2385 } 2386 2387 xs = &sc->sc_slots[slot]; 2388 dev->ud_hcpriv = xs; 2389 2390 /* 4.3.3 initialize slot structure */ 2391 err = xhci_init_slot(dev, slot); 2392 if (err) { 2393 DPRINTFN(1, "init slot %ju", err, 0, 0, 0); 2394 dev->ud_hcpriv = NULL; 2395 /* 2396 * We have to disable_slot here because 2397 * xs->xs_idx == 0 when xhci_init_slot fails, 2398 * in that case usbd_remove_dev won't work. 2399 */ 2400 mutex_enter(&sc->sc_lock); 2401 xhci_disable_slot(sc, slot); 2402 mutex_exit(&sc->sc_lock); 2403 goto bad; 2404 } 2405 2406 /* 4.3.4 Address Assignment */ 2407 err = xhci_set_address(dev, slot, false); 2408 if (err) { 2409 DPRINTFN(1, "set address w/o bsr %ju", err, 0, 0, 0); 2410 goto bad; 2411 } 2412 2413 /* Allow device time to set new address */ 2414 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2415 2416 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2417 //hexdump("slot context", cp, sc->sc_ctxsz); 2418 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3])); 2419 DPRINTFN(4, "device address %ju", addr, 0, 0, 0); 2420 /* 2421 * XXX ensure we know when the hardware does something 2422 * we can't yet cope with 2423 */ 2424 KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr); 2425 dev->ud_addr = addr; 2426 2427 KASSERTMSG(bus->ub_devices[usb_addr2dindex(dev->ud_addr)] == NULL, 2428 "addr %d already allocated", dev->ud_addr); 2429 /* 2430 * The root hub is given its own slot 2431 */ 2432 bus->ub_devices[usb_addr2dindex(dev->ud_addr)] = dev; 2433 2434 err = usbd_get_initial_ddesc(dev, dd); 2435 if (err) { 2436 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2437 goto bad; 2438 } 2439 2440 /* 4.8.2.1 */ 2441 if (USB_IS_SS(speed)) { 2442 if (dd->bMaxPacketSize != 9) { 2443 printf("%s: invalid mps 2^%u for SS ep0," 2444 " using 512\n", 2445 device_xname(sc->sc_dev), 2446 dd->bMaxPacketSize); 2447 dd->bMaxPacketSize = 9; 2448 } 2449 USETW(dev->ud_ep0desc.wMaxPacketSize, 2450 (1 << dd->bMaxPacketSize)); 2451 } else 2452 USETW(dev->ud_ep0desc.wMaxPacketSize, 2453 dd->bMaxPacketSize); 2454 DPRINTFN(4, "bMaxPacketSize %ju", dd->bMaxPacketSize, 0, 0, 0); 2455 err = xhci_update_ep0_mps(sc, xs, 2456 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2457 if (err) { 2458 DPRINTFN(1, "update mps of ep0 %ju", err, 0, 0, 0); 2459 goto bad; 2460 } 2461 2462 err = usbd_reload_device_desc(dev); 2463 if (err) { 2464 DPRINTFN(1, "reload desc %ju", err, 0, 0, 0); 2465 goto bad; 2466 } 2467 } 2468 2469 DPRINTFN(1, "adding unit addr=%jd, rev=%02jx,", 2470 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2471 DPRINTFN(1, " class=%jd, subclass=%jd, protocol=%jd,", 2472 dd->bDeviceClass, dd->bDeviceSubClass, 2473 dd->bDeviceProtocol, 0); 2474 DPRINTFN(1, " mps=%jd, len=%jd, noconf=%jd, speed=%jd", 2475 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2476 dev->ud_speed); 2477 2478 usbd_get_device_strings(dev); 2479 2480 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2481 2482 if (depth == 0 && port == 0) { 2483 usbd_attach_roothub(parent, dev); 2484 DPRINTFN(1, "root hub %#jx", (uintptr_t)dev, 0, 0, 0); 2485 return USBD_NORMAL_COMPLETION; 2486 } 2487 2488 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2489 bad: 2490 if (err != USBD_NORMAL_COMPLETION) { 2491 usbd_remove_device(dev, up); 2492 } 2493 2494 return err; 2495 } 2496 2497 static usbd_status 2498 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2499 size_t ntrb, size_t align) 2500 { 2501 usbd_status err; 2502 size_t size = ntrb * XHCI_TRB_SIZE; 2503 2504 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2505 2506 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2507 if (err) 2508 return err; 2509 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2510 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2511 xr->xr_trb = xhci_ring_trbv(xr, 0); 2512 xr->xr_ntrb = ntrb; 2513 xr->is_halted = false; 2514 xhci_host_dequeue(xr); 2515 2516 return USBD_NORMAL_COMPLETION; 2517 } 2518 2519 static void 2520 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2521 { 2522 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2523 mutex_destroy(&xr->xr_lock); 2524 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2525 } 2526 2527 static void 2528 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2529 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2530 { 2531 size_t i; 2532 u_int ri; 2533 u_int cs; 2534 uint64_t parameter; 2535 uint32_t status; 2536 uint32_t control; 2537 2538 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2539 2540 KASSERTMSG(ntrbs <= XHCI_XFER_NTRB, "ntrbs %zu", ntrbs); 2541 for (i = 0; i < ntrbs; i++) { 2542 DPRINTFN(12, "xr %#jx trbs %#jx num %ju", (uintptr_t)xr, 2543 (uintptr_t)trbs, i, 0); 2544 DPRINTFN(12, " %016jx %08jx %08jx", 2545 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2546 KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2547 XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3); 2548 } 2549 2550 DPRINTFN(12, "%#jx xr_ep 0x%jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep, 2551 xr->xr_cs, 0); 2552 2553 ri = xr->xr_ep; 2554 cs = xr->xr_cs; 2555 2556 /* 2557 * Although the xhci hardware can do scatter/gather dma from 2558 * arbitrary sized buffers, there is a non-obvious restriction 2559 * that a LINK trb is only allowed at the end of a burst of 2560 * transfers - which might be 16kB. 2561 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2562 * The simple solution is not to allow a LINK trb in the middle 2563 * of anything - as here. 2564 * XXX: (dsl) There are xhci controllers out there (eg some made by 2565 * ASMedia) that seem to lock up if they process a LINK trb but 2566 * cannot process the linked-to trb yet. 2567 * The code should write the 'cycle' bit on the link trb AFTER 2568 * adding the other trb. 2569 */ 2570 u_int firstep = xr->xr_ep; 2571 u_int firstcs = xr->xr_cs; 2572 2573 for (i = 0; i < ntrbs; ) { 2574 u_int oldri = ri; 2575 u_int oldcs = cs; 2576 2577 if (ri >= (xr->xr_ntrb - 1)) { 2578 /* Put Link TD at the end of ring */ 2579 parameter = xhci_ring_trbp(xr, 0); 2580 status = 0; 2581 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2582 XHCI_TRB_3_TC_BIT; 2583 xr->xr_cookies[ri] = NULL; 2584 xr->xr_ep = 0; 2585 xr->xr_cs ^= 1; 2586 ri = xr->xr_ep; 2587 cs = xr->xr_cs; 2588 } else { 2589 parameter = trbs[i].trb_0; 2590 status = trbs[i].trb_2; 2591 control = trbs[i].trb_3; 2592 2593 xr->xr_cookies[ri] = cookie; 2594 ri++; 2595 i++; 2596 } 2597 /* 2598 * If this is a first TRB, mark it invalid to prevent 2599 * xHC from running it immediately. 2600 */ 2601 if (oldri == firstep) { 2602 if (oldcs) { 2603 control &= ~XHCI_TRB_3_CYCLE_BIT; 2604 } else { 2605 control |= XHCI_TRB_3_CYCLE_BIT; 2606 } 2607 } else { 2608 if (oldcs) { 2609 control |= XHCI_TRB_3_CYCLE_BIT; 2610 } else { 2611 control &= ~XHCI_TRB_3_CYCLE_BIT; 2612 } 2613 } 2614 xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control); 2615 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri, 2616 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2617 } 2618 2619 /* Now invert cycle bit of first TRB */ 2620 if (firstcs) { 2621 xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 2622 } else { 2623 xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 2624 } 2625 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep, 2626 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2627 2628 xr->xr_ep = ri; 2629 xr->xr_cs = cs; 2630 2631 DPRINTFN(12, "%#jx xr_ep 0x%jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep, 2632 xr->xr_cs, 0); 2633 } 2634 2635 /* 2636 * Stop execution commands, purge all commands on command ring, and 2637 * rewind dequeue pointer. 2638 */ 2639 static void 2640 xhci_abort_command(struct xhci_softc *sc) 2641 { 2642 struct xhci_ring * const cr = &sc->sc_cr; 2643 uint64_t crcr; 2644 int i; 2645 2646 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2647 DPRINTFN(14, "command %#jx timeout, aborting", 2648 sc->sc_command_addr, 0, 0, 0); 2649 2650 mutex_enter(&cr->xr_lock); 2651 2652 /* 4.6.1.2 Aborting a Command */ 2653 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2654 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2655 2656 for (i = 0; i < 500; i++) { 2657 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2658 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2659 break; 2660 usb_delay_ms(&sc->sc_bus, 1); 2661 } 2662 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2663 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2664 /* reset HC here? */ 2665 } 2666 2667 /* reset command ring dequeue pointer */ 2668 cr->xr_ep = 0; 2669 cr->xr_cs = 1; 2670 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2671 2672 mutex_exit(&cr->xr_lock); 2673 } 2674 2675 /* 2676 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2677 * Command completion is notified by cv_signal from xhci_event_cmd() 2678 * (called from xhci_softint), or timed-out. 2679 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2680 * then do_command examines it. 2681 */ 2682 static usbd_status 2683 xhci_do_command_locked(struct xhci_softc * const sc, 2684 struct xhci_trb * const trb, int timeout) 2685 { 2686 struct xhci_ring * const cr = &sc->sc_cr; 2687 usbd_status err; 2688 2689 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2690 DPRINTFN(12, "input: 0x%016jx 0x%08jx 0x%08jx", 2691 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2692 2693 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2694 KASSERT(mutex_owned(&sc->sc_lock)); 2695 2696 while (sc->sc_command_addr != 0) 2697 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 2698 2699 /* 2700 * If enqueue pointer points at last of ring, it's Link TRB, 2701 * command TRB will be stored in 0th TRB. 2702 */ 2703 if (cr->xr_ep == cr->xr_ntrb - 1) 2704 sc->sc_command_addr = xhci_ring_trbp(cr, 0); 2705 else 2706 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2707 2708 sc->sc_resultpending = true; 2709 2710 mutex_enter(&cr->xr_lock); 2711 xhci_ring_put(sc, cr, NULL, trb, 1); 2712 mutex_exit(&cr->xr_lock); 2713 2714 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2715 2716 while (sc->sc_resultpending) { 2717 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2718 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2719 xhci_abort_command(sc); 2720 err = USBD_TIMEOUT; 2721 goto timedout; 2722 } 2723 } 2724 2725 trb->trb_0 = sc->sc_result_trb.trb_0; 2726 trb->trb_2 = sc->sc_result_trb.trb_2; 2727 trb->trb_3 = sc->sc_result_trb.trb_3; 2728 2729 DPRINTFN(12, "output: 0x%016jx 0x%08jx 0x%08jx", 2730 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2731 2732 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2733 case XHCI_TRB_ERROR_SUCCESS: 2734 err = USBD_NORMAL_COMPLETION; 2735 break; 2736 default: 2737 case 192 ... 223: 2738 err = USBD_IOERROR; 2739 break; 2740 case 224 ... 255: 2741 err = USBD_NORMAL_COMPLETION; 2742 break; 2743 } 2744 2745 timedout: 2746 sc->sc_resultpending = false; 2747 sc->sc_command_addr = 0; 2748 cv_broadcast(&sc->sc_cmdbusy_cv); 2749 2750 return err; 2751 } 2752 2753 static usbd_status 2754 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2755 int timeout) 2756 { 2757 2758 mutex_enter(&sc->sc_lock); 2759 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2760 mutex_exit(&sc->sc_lock); 2761 2762 return ret; 2763 } 2764 2765 static usbd_status 2766 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2767 { 2768 struct xhci_trb trb; 2769 usbd_status err; 2770 2771 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2772 2773 trb.trb_0 = 0; 2774 trb.trb_2 = 0; 2775 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2776 2777 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2778 if (err != USBD_NORMAL_COMPLETION) { 2779 return err; 2780 } 2781 2782 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2783 2784 return err; 2785 } 2786 2787 /* 2788 * xHCI 4.6.4 2789 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2790 * All endpoints in the slot should be stopped. 2791 * Should be called with sc_lock held. 2792 */ 2793 static usbd_status 2794 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2795 { 2796 struct xhci_trb trb; 2797 struct xhci_slot *xs; 2798 usbd_status err; 2799 2800 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2801 2802 if (sc->sc_dying) 2803 return USBD_IOERROR; 2804 2805 trb.trb_0 = 0; 2806 trb.trb_2 = 0; 2807 trb.trb_3 = htole32( 2808 XHCI_TRB_3_SLOT_SET(slot) | 2809 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2810 2811 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2812 2813 if (!err) { 2814 xs = &sc->sc_slots[slot]; 2815 if (xs->xs_idx != 0) { 2816 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2817 xhci_set_dcba(sc, 0, slot); 2818 memset(xs, 0, sizeof(*xs)); 2819 } 2820 } 2821 2822 return err; 2823 } 2824 2825 /* 2826 * Set address of device and transition slot state from ENABLED to ADDRESSED 2827 * if Block Setaddress Request (BSR) is false. 2828 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2829 * see xHCI 1.1 4.5.3, 3.3.4 2830 * Should be called without sc_lock held. 2831 */ 2832 static usbd_status 2833 xhci_address_device(struct xhci_softc * const sc, 2834 uint64_t icp, uint8_t slot_id, bool bsr) 2835 { 2836 struct xhci_trb trb; 2837 usbd_status err; 2838 2839 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2840 2841 trb.trb_0 = icp; 2842 trb.trb_2 = 0; 2843 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2844 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2845 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2846 2847 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2848 2849 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2850 err = USBD_NO_ADDR; 2851 2852 return err; 2853 } 2854 2855 static usbd_status 2856 xhci_update_ep0_mps(struct xhci_softc * const sc, 2857 struct xhci_slot * const xs, u_int mps) 2858 { 2859 struct xhci_trb trb; 2860 usbd_status err; 2861 uint32_t * cp; 2862 2863 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2864 DPRINTFN(4, "slot %ju mps %ju", xs->xs_idx, mps, 0, 0); 2865 2866 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2867 cp[0] = htole32(0); 2868 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2869 2870 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2871 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2872 2873 /* sync input contexts before they are read from memory */ 2874 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2875 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2876 sc->sc_ctxsz * 4); 2877 2878 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2879 trb.trb_2 = 0; 2880 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2881 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2882 2883 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2884 return err; 2885 } 2886 2887 static void 2888 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2889 { 2890 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2891 2892 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2893 DPRINTFN(4, "dcbaa %#jx dc %016jx slot %jd", 2894 (uintptr_t)&dcbaa[si], dcba, si, 0); 2895 2896 dcbaa[si] = htole64(dcba); 2897 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2898 BUS_DMASYNC_PREWRITE); 2899 } 2900 2901 /* 2902 * Allocate device and input context DMA buffer, and 2903 * TRB DMA buffer for each endpoint. 2904 */ 2905 static usbd_status 2906 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2907 { 2908 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2909 struct xhci_slot *xs; 2910 usbd_status err; 2911 u_int dci; 2912 2913 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2914 DPRINTFN(4, "slot %ju", slot, 0, 0, 0); 2915 2916 xs = &sc->sc_slots[slot]; 2917 2918 /* allocate contexts */ 2919 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2920 &xs->xs_dc_dma); 2921 if (err) 2922 return err; 2923 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2924 2925 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2926 &xs->xs_ic_dma); 2927 if (err) 2928 goto bad1; 2929 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2930 2931 for (dci = 0; dci < 32; dci++) { 2932 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2933 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2934 if (dci == XHCI_DCI_SLOT) 2935 continue; 2936 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2937 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2938 if (err) { 2939 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2940 goto bad2; 2941 } 2942 } 2943 2944 bad2: 2945 if (err == USBD_NORMAL_COMPLETION) { 2946 xs->xs_idx = slot; 2947 } else { 2948 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2949 } 2950 2951 return err; 2952 2953 bad1: 2954 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2955 xs->xs_idx = 0; 2956 return err; 2957 } 2958 2959 static void 2960 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2961 int end_dci) 2962 { 2963 u_int dci; 2964 2965 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2966 DPRINTFN(4, "slot %ju start %ju end %ju", xs->xs_idx, start_dci, 2967 end_dci, 0); 2968 2969 for (dci = start_dci; dci < end_dci; dci++) { 2970 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2971 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2972 } 2973 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2974 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2975 xs->xs_idx = 0; 2976 } 2977 2978 /* 2979 * Setup slot context, set Device Context Base Address, and issue 2980 * Set Address Device command. 2981 */ 2982 static usbd_status 2983 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 2984 { 2985 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2986 struct xhci_slot *xs; 2987 usbd_status err; 2988 2989 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2990 DPRINTFN(4, "slot %ju bsr %ju", slot, bsr, 0, 0); 2991 2992 xs = &sc->sc_slots[slot]; 2993 2994 xhci_setup_ctx(dev->ud_pipe0); 2995 2996 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2997 sc->sc_ctxsz * 3); 2998 2999 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 3000 3001 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 3002 3003 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 3004 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 3005 sc->sc_ctxsz * 2); 3006 3007 return err; 3008 } 3009 3010 /* 3011 * 4.8.2, 6.2.3.2 3012 * construct slot/endpoint context parameters and do syncmem 3013 */ 3014 static void 3015 xhci_setup_ctx(struct usbd_pipe *pipe) 3016 { 3017 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3018 struct usbd_device *dev = pipe->up_dev; 3019 struct xhci_slot * const xs = dev->ud_hcpriv; 3020 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3021 const u_int dci = xhci_ep_get_dci(ed); 3022 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3023 uint32_t *cp; 3024 uint16_t mps = UGETW(ed->wMaxPacketSize); 3025 uint8_t speed = dev->ud_speed; 3026 uint8_t ival = ed->bInterval; 3027 3028 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3029 DPRINTFN(4, "pipe %#jx: slot %ju dci %ju speed %ju", 3030 (uintptr_t)pipe, xs->xs_idx, dci, speed); 3031 3032 /* set up initial input control context */ 3033 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 3034 cp[0] = htole32(0); 3035 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 3036 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 3037 cp[7] = htole32(0); 3038 3039 /* set up input slot context */ 3040 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 3041 cp[0] = 3042 XHCI_SCTX_0_CTX_NUM_SET(dci) | 3043 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 3044 cp[1] = 0; 3045 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 3046 cp[3] = 0; 3047 xhci_setup_route(pipe, cp); 3048 xhci_setup_tthub(pipe, cp); 3049 3050 cp[0] = htole32(cp[0]); 3051 cp[1] = htole32(cp[1]); 3052 cp[2] = htole32(cp[2]); 3053 cp[3] = htole32(cp[3]); 3054 3055 /* set up input endpoint context */ 3056 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 3057 cp[0] = 3058 XHCI_EPCTX_0_EPSTATE_SET(0) | 3059 XHCI_EPCTX_0_MULT_SET(0) | 3060 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 3061 XHCI_EPCTX_0_LSA_SET(0) | 3062 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 3063 cp[1] = 3064 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 3065 XHCI_EPCTX_1_HID_SET(0) | 3066 XHCI_EPCTX_1_MAXB_SET(0); 3067 3068 if (xfertype != UE_ISOCHRONOUS) 3069 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 3070 3071 if (xfertype == UE_CONTROL) 3072 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 3073 else if (USB_IS_SS(speed)) 3074 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 3075 else 3076 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 3077 3078 xhci_setup_maxburst(pipe, cp); 3079 3080 switch (xfertype) { 3081 case UE_CONTROL: 3082 break; 3083 case UE_BULK: 3084 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 3085 break; 3086 case UE_INTERRUPT: 3087 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3088 ival = pipe->up_interval; 3089 3090 ival = xhci_bival2ival(ival, speed); 3091 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3092 break; 3093 case UE_ISOCHRONOUS: 3094 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3095 ival = pipe->up_interval; 3096 3097 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 3098 if (speed == USB_SPEED_FULL) 3099 ival += 3; /* 1ms -> 125us */ 3100 ival--; 3101 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3102 break; 3103 default: 3104 break; 3105 } 3106 DPRINTFN(4, "setting ival %ju MaxBurst %#jx", 3107 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 3108 3109 /* rewind TR dequeue pointer in xHC */ 3110 /* can't use xhci_ep_get_dci() yet? */ 3111 *(uint64_t *)(&cp[2]) = htole64( 3112 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 3113 XHCI_EPCTX_2_DCS_SET(1)); 3114 3115 cp[0] = htole32(cp[0]); 3116 cp[1] = htole32(cp[1]); 3117 cp[4] = htole32(cp[4]); 3118 3119 /* rewind TR dequeue pointer in driver */ 3120 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 3121 mutex_enter(&xr->xr_lock); 3122 xhci_host_dequeue(xr); 3123 mutex_exit(&xr->xr_lock); 3124 3125 /* sync input contexts before they are read from memory */ 3126 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3127 } 3128 3129 /* 3130 * Setup route string and roothub port of given device for slot context 3131 */ 3132 static void 3133 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 3134 { 3135 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3136 struct usbd_device *dev = pipe->up_dev; 3137 struct usbd_port *up = dev->ud_powersrc; 3138 struct usbd_device *hub; 3139 struct usbd_device *adev; 3140 uint8_t rhport = 0; 3141 uint32_t route = 0; 3142 3143 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3144 3145 /* Locate root hub port and Determine route string */ 3146 /* 4.3.3 route string does not include roothub port */ 3147 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 3148 uint32_t dep; 3149 3150 DPRINTFN(4, "hub %#jx depth %jd upport %jp upportno %jd", 3151 (uintptr_t)hub, hub->ud_depth, (uintptr_t)hub->ud_powersrc, 3152 hub->ud_powersrc ? (uintptr_t)hub->ud_powersrc->up_portno : 3153 -1); 3154 3155 if (hub->ud_powersrc == NULL) 3156 break; 3157 dep = hub->ud_depth; 3158 if (dep == 0) 3159 break; 3160 rhport = hub->ud_powersrc->up_portno; 3161 if (dep > USB_HUB_MAX_DEPTH) 3162 continue; 3163 3164 route |= 3165 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 3166 << ((dep - 1) * 4); 3167 } 3168 route = route >> 4; 3169 size_t bn = hub == sc->sc_bus.ub_roothub ? 0 : 1; 3170 3171 /* Locate port on upstream high speed hub */ 3172 for (adev = dev, hub = up->up_parent; 3173 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 3174 adev = hub, hub = hub->ud_myhub) 3175 ; 3176 if (hub) { 3177 int p; 3178 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 3179 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 3180 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 3181 goto found; 3182 } 3183 } 3184 panic("%s: cannot find HS port", __func__); 3185 found: 3186 DPRINTFN(4, "high speed port %jd", p, 0, 0, 0); 3187 } else { 3188 dev->ud_myhsport = NULL; 3189 } 3190 3191 const size_t ctlrport = xhci_rhport2ctlrport(sc, bn, rhport); 3192 3193 DPRINTFN(4, "rhport %ju ctlrport %ju Route %05jx hub %#jx", rhport, 3194 ctlrport, route, (uintptr_t)hub); 3195 3196 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 3197 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(ctlrport); 3198 } 3199 3200 /* 3201 * Setup whether device is hub, whether device uses MTT, and 3202 * TT informations if it uses MTT. 3203 */ 3204 static void 3205 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 3206 { 3207 struct usbd_device *dev = pipe->up_dev; 3208 struct usbd_port *myhsport = dev->ud_myhsport; 3209 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 3210 uint32_t speed = dev->ud_speed; 3211 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 3212 uint8_t tthubslot, ttportnum; 3213 bool ishub; 3214 bool usemtt; 3215 3216 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3217 3218 /* 3219 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 3220 * tthubslot: 3221 * This is the slot ID of parent HS hub 3222 * if LS/FS device is connected && connected through HS hub. 3223 * This is 0 if device is not LS/FS device || 3224 * parent hub is not HS hub || 3225 * attached to root hub. 3226 * ttportnum: 3227 * This is the downstream facing port of parent HS hub 3228 * if LS/FS device is connected. 3229 * This is 0 if device is not LS/FS device || 3230 * parent hub is not HS hub || 3231 * attached to root hub. 3232 */ 3233 if (myhsport && 3234 myhsport->up_parent->ud_addr != rhaddr && 3235 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 3236 ttportnum = myhsport->up_portno; 3237 tthubslot = myhsport->up_parent->ud_addr; 3238 } else { 3239 ttportnum = 0; 3240 tthubslot = 0; 3241 } 3242 DPRINTFN(4, "myhsport %#jx ttportnum=%jd tthubslot=%jd", 3243 (uintptr_t)myhsport, ttportnum, tthubslot, 0); 3244 3245 /* ishub is valid after reading UDESC_DEVICE */ 3246 ishub = (dd->bDeviceClass == UDCLASS_HUB); 3247 3248 /* dev->ud_hub is valid after reading UDESC_HUB */ 3249 if (ishub && dev->ud_hub) { 3250 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 3251 uint8_t ttt = 3252 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 3253 3254 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 3255 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 3256 DPRINTFN(4, "nports=%jd ttt=%jd", hd->bNbrPorts, ttt, 0, 0); 3257 } 3258 3259 #define IS_MTTHUB(dd) \ 3260 ((dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 3261 3262 /* 3263 * MTT flag is set if 3264 * 1. this is HS hub && MTTs are supported and enabled; or 3265 * 2. this is LS or FS device && there is a parent HS hub where MTTs 3266 * are supported and enabled. 3267 * 3268 * XXX enabled is not tested yet 3269 */ 3270 if (ishub && speed == USB_SPEED_HIGH && IS_MTTHUB(dd)) 3271 usemtt = true; 3272 else if ((speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 3273 myhsport && 3274 myhsport->up_parent->ud_addr != rhaddr && 3275 IS_MTTHUB(&myhsport->up_parent->ud_ddesc)) 3276 usemtt = true; 3277 else 3278 usemtt = false; 3279 DPRINTFN(4, "class %ju proto %ju ishub %jd usemtt %jd", 3280 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 3281 3282 #undef IS_MTTHUB 3283 3284 cp[0] |= 3285 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 3286 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 3287 cp[2] |= 3288 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 3289 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 3290 } 3291 3292 /* set up params for periodic endpoint */ 3293 static void 3294 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 3295 { 3296 struct usbd_device *dev = pipe->up_dev; 3297 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3298 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3299 usbd_desc_iter_t iter; 3300 const usb_cdc_descriptor_t *cdcd; 3301 uint32_t maxb = 0; 3302 uint16_t mps = UGETW(ed->wMaxPacketSize); 3303 uint8_t speed = dev->ud_speed; 3304 uint8_t ep; 3305 3306 /* config desc is NULL when opening ep0 */ 3307 if (dev == NULL || dev->ud_cdesc == NULL) 3308 goto no_cdcd; 3309 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 3310 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 3311 if (cdcd == NULL) 3312 goto no_cdcd; 3313 usb_desc_iter_init(dev, &iter); 3314 iter.cur = (const void *)cdcd; 3315 3316 /* find endpoint_ss_comp desc for ep of this pipe */ 3317 for (ep = 0;;) { 3318 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 3319 if (cdcd == NULL) 3320 break; 3321 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 3322 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 3323 bEndpointAddress; 3324 if (UE_GET_ADDR(ep) == 3325 UE_GET_ADDR(ed->bEndpointAddress)) { 3326 cdcd = (const usb_cdc_descriptor_t *) 3327 usb_desc_iter_next(&iter); 3328 break; 3329 } 3330 ep = 0; 3331 } 3332 } 3333 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 3334 const usb_endpoint_ss_comp_descriptor_t * esscd = 3335 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3336 maxb = esscd->bMaxBurst; 3337 } 3338 3339 no_cdcd: 3340 /* 6.2.3.4, 4.8.2.4 */ 3341 if (USB_IS_SS(speed)) { 3342 /* USB 3.1 9.6.6 */ 3343 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3344 /* USB 3.1 9.6.7 */ 3345 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3346 #ifdef notyet 3347 if (xfertype == UE_ISOCHRONOUS) { 3348 } 3349 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3350 /* use ESIT */ 3351 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3352 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3353 3354 /* XXX if LEC = 1, set ESIT instead */ 3355 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3356 } else { 3357 /* use ival */ 3358 } 3359 #endif 3360 } else { 3361 /* USB 2.0 9.6.6 */ 3362 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3363 3364 /* 6.2.3.4 */ 3365 if (speed == USB_SPEED_HIGH && 3366 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3367 maxb = UE_GET_TRANS(mps); 3368 } else { 3369 /* LS/FS or HS CTRL or HS BULK */ 3370 maxb = 0; 3371 } 3372 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3373 } 3374 } 3375 3376 /* 3377 * Convert endpoint bInterval value to endpoint context interval value 3378 * for Interrupt pipe. 3379 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3380 */ 3381 static uint32_t 3382 xhci_bival2ival(uint32_t ival, uint32_t speed) 3383 { 3384 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3385 int i; 3386 3387 /* 3388 * round ival down to "the nearest base 2 multiple of 3389 * bInterval * 8". 3390 * bInterval is at most 255 as its type is uByte. 3391 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3392 */ 3393 for (i = 10; i > 0; i--) { 3394 if ((ival * 8) >= (1 << i)) 3395 break; 3396 } 3397 ival = i; 3398 } else { 3399 /* Interval = bInterval-1 for SS/HS */ 3400 ival--; 3401 } 3402 3403 return ival; 3404 } 3405 3406 /* ----- */ 3407 3408 static void 3409 xhci_noop(struct usbd_pipe *pipe) 3410 { 3411 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3412 } 3413 3414 /* 3415 * Process root hub request. 3416 */ 3417 static int 3418 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3419 void *buf, int buflen) 3420 { 3421 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3422 usb_port_status_t ps; 3423 int l, totlen = 0; 3424 uint16_t len, value, index; 3425 int port, i; 3426 uint32_t v; 3427 3428 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3429 3430 if (sc->sc_dying) 3431 return -1; 3432 3433 size_t bn = bus == &sc->sc_bus ? 0 : 1; 3434 3435 len = UGETW(req->wLength); 3436 value = UGETW(req->wValue); 3437 index = UGETW(req->wIndex); 3438 3439 DPRINTFN(12, "rhreq: %04jx %04jx %04jx %04jx", 3440 req->bmRequestType | (req->bRequest << 8), value, index, len); 3441 3442 #define C(x,y) ((x) | ((y) << 8)) 3443 switch (C(req->bRequest, req->bmRequestType)) { 3444 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3445 DPRINTFN(8, "getdesc: wValue=0x%04jx", value, 0, 0, 0); 3446 if (len == 0) 3447 break; 3448 switch (value) { 3449 case C(0, UDESC_DEVICE): { 3450 usb_device_descriptor_t devd; 3451 totlen = min(buflen, sizeof(devd)); 3452 memcpy(&devd, buf, totlen); 3453 USETW(devd.idVendor, sc->sc_id_vendor); 3454 memcpy(buf, &devd, totlen); 3455 break; 3456 } 3457 #define sd ((usb_string_descriptor_t *)buf) 3458 case C(1, UDESC_STRING): 3459 /* Vendor */ 3460 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3461 break; 3462 case C(2, UDESC_STRING): 3463 /* Product */ 3464 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3465 break; 3466 #undef sd 3467 default: 3468 /* default from usbroothub */ 3469 return buflen; 3470 } 3471 break; 3472 3473 /* Hub requests */ 3474 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3475 break; 3476 /* Clear Port Feature request */ 3477 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): { 3478 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3479 3480 DPRINTFN(4, "UR_CLEAR_PORT_FEAT bp=%jd feat=%jd bus=%jd cp=%jd", 3481 index, value, bn, cp); 3482 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3483 return -1; 3484 } 3485 port = XHCI_PORTSC(cp); 3486 v = xhci_op_read_4(sc, port); 3487 DPRINTFN(4, "portsc=0x%08jx", v, 0, 0, 0); 3488 v &= ~XHCI_PS_CLEAR; 3489 switch (value) { 3490 case UHF_PORT_ENABLE: 3491 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3492 break; 3493 case UHF_PORT_SUSPEND: 3494 return -1; 3495 case UHF_PORT_POWER: 3496 break; 3497 case UHF_PORT_TEST: 3498 case UHF_PORT_INDICATOR: 3499 return -1; 3500 case UHF_C_PORT_CONNECTION: 3501 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3502 break; 3503 case UHF_C_PORT_ENABLE: 3504 case UHF_C_PORT_SUSPEND: 3505 case UHF_C_PORT_OVER_CURRENT: 3506 return -1; 3507 case UHF_C_BH_PORT_RESET: 3508 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3509 break; 3510 case UHF_C_PORT_RESET: 3511 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3512 break; 3513 case UHF_C_PORT_LINK_STATE: 3514 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3515 break; 3516 case UHF_C_PORT_CONFIG_ERROR: 3517 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3518 break; 3519 default: 3520 return -1; 3521 } 3522 break; 3523 } 3524 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3525 if (len == 0) 3526 break; 3527 if ((value & 0xff) != 0) { 3528 return -1; 3529 } 3530 usb_hub_descriptor_t hubd; 3531 3532 totlen = min(buflen, sizeof(hubd)); 3533 memcpy(&hubd, buf, totlen); 3534 hubd.bNbrPorts = sc->sc_rhportcount[bn]; 3535 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3536 hubd.bPwrOn2PwrGood = 200; 3537 for (i = 0, l = sc->sc_rhportcount[bn]; l > 0; i++, l -= 8) { 3538 /* XXX can't find out? */ 3539 hubd.DeviceRemovable[i++] = 0; 3540 } 3541 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3542 totlen = min(totlen, hubd.bDescLength); 3543 memcpy(buf, &hubd, totlen); 3544 break; 3545 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3546 if (len != 4) { 3547 return -1; 3548 } 3549 memset(buf, 0, len); /* ? XXX */ 3550 totlen = len; 3551 break; 3552 /* Get Port Status request */ 3553 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): { 3554 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3555 3556 DPRINTFN(8, "get port status bn=%jd i=%jd cp=%ju", 3557 bn, index, cp, 0); 3558 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3559 return -1; 3560 } 3561 if (len != 4) { 3562 return -1; 3563 } 3564 v = xhci_op_read_4(sc, XHCI_PORTSC(cp)); 3565 DPRINTFN(4, "getrhportsc %jd %08jx", cp, v, 0, 0); 3566 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3567 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3568 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3569 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3570 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3571 if (v & XHCI_PS_PR) i |= UPS_RESET; 3572 if (v & XHCI_PS_PP) { 3573 if (i & UPS_OTHER_SPEED) 3574 i |= UPS_PORT_POWER_SS; 3575 else 3576 i |= UPS_PORT_POWER; 3577 } 3578 if (i & UPS_OTHER_SPEED) 3579 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3580 if (sc->sc_vendor_port_status) 3581 i = sc->sc_vendor_port_status(sc, v, i); 3582 USETW(ps.wPortStatus, i); 3583 i = 0; 3584 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3585 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3586 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3587 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3588 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3589 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3590 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3591 USETW(ps.wPortChange, i); 3592 totlen = min(len, sizeof(ps)); 3593 memcpy(buf, &ps, totlen); 3594 break; 3595 } 3596 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3597 return -1; 3598 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3599 break; 3600 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3601 break; 3602 /* Set Port Feature request */ 3603 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3604 int optval = (index >> 8) & 0xff; 3605 index &= 0xff; 3606 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3607 return -1; 3608 } 3609 3610 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3611 3612 port = XHCI_PORTSC(cp); 3613 v = xhci_op_read_4(sc, port); 3614 DPRINTFN(4, "index %jd cp %jd portsc=0x%08jx", index, cp, v, 0); 3615 v &= ~XHCI_PS_CLEAR; 3616 switch (value) { 3617 case UHF_PORT_ENABLE: 3618 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3619 break; 3620 case UHF_PORT_SUSPEND: 3621 /* XXX suspend */ 3622 break; 3623 case UHF_PORT_RESET: 3624 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3625 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3626 /* Wait for reset to complete. */ 3627 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3628 if (sc->sc_dying) { 3629 return -1; 3630 } 3631 v = xhci_op_read_4(sc, port); 3632 if (v & XHCI_PS_PR) { 3633 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3634 usb_delay_ms(&sc->sc_bus, 10); 3635 /* XXX */ 3636 } 3637 break; 3638 case UHF_PORT_POWER: 3639 /* XXX power control */ 3640 break; 3641 /* XXX more */ 3642 case UHF_C_PORT_RESET: 3643 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3644 break; 3645 case UHF_PORT_U1_TIMEOUT: 3646 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3647 return -1; 3648 } 3649 port = XHCI_PORTPMSC(cp); 3650 v = xhci_op_read_4(sc, port); 3651 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 3652 index, cp, v, 0); 3653 v &= ~XHCI_PM3_U1TO_SET(0xff); 3654 v |= XHCI_PM3_U1TO_SET(optval); 3655 xhci_op_write_4(sc, port, v); 3656 break; 3657 case UHF_PORT_U2_TIMEOUT: 3658 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3659 return -1; 3660 } 3661 port = XHCI_PORTPMSC(cp); 3662 v = xhci_op_read_4(sc, port); 3663 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 3664 index, cp, v, 0); 3665 v &= ~XHCI_PM3_U2TO_SET(0xff); 3666 v |= XHCI_PM3_U2TO_SET(optval); 3667 xhci_op_write_4(sc, port, v); 3668 break; 3669 default: 3670 return -1; 3671 } 3672 } 3673 break; 3674 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3675 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3676 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3677 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3678 break; 3679 default: 3680 /* default from usbroothub */ 3681 return buflen; 3682 } 3683 3684 return totlen; 3685 } 3686 3687 /* root hub interrupt */ 3688 3689 static usbd_status 3690 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3691 { 3692 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3693 usbd_status err; 3694 3695 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3696 3697 /* Insert last in queue. */ 3698 mutex_enter(&sc->sc_lock); 3699 err = usb_insert_transfer(xfer); 3700 mutex_exit(&sc->sc_lock); 3701 if (err) 3702 return err; 3703 3704 /* Pipe isn't running, start first */ 3705 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3706 } 3707 3708 /* Wait for roothub port status/change */ 3709 static usbd_status 3710 xhci_root_intr_start(struct usbd_xfer *xfer) 3711 { 3712 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3713 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3714 3715 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3716 3717 if (sc->sc_dying) 3718 return USBD_IOERROR; 3719 3720 mutex_enter(&sc->sc_lock); 3721 sc->sc_intrxfer[bn] = xfer; 3722 mutex_exit(&sc->sc_lock); 3723 3724 return USBD_IN_PROGRESS; 3725 } 3726 3727 static void 3728 xhci_root_intr_abort(struct usbd_xfer *xfer) 3729 { 3730 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3731 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3732 3733 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3734 3735 KASSERT(mutex_owned(&sc->sc_lock)); 3736 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3737 3738 sc->sc_intrxfer[bn] = NULL; 3739 3740 xfer->ux_status = USBD_CANCELLED; 3741 usb_transfer_complete(xfer); 3742 } 3743 3744 static void 3745 xhci_root_intr_close(struct usbd_pipe *pipe) 3746 { 3747 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3748 const struct usbd_xfer *xfer = pipe->up_intrxfer; 3749 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3750 3751 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3752 3753 KASSERT(mutex_owned(&sc->sc_lock)); 3754 3755 sc->sc_intrxfer[bn] = NULL; 3756 } 3757 3758 static void 3759 xhci_root_intr_done(struct usbd_xfer *xfer) 3760 { 3761 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3762 3763 } 3764 3765 /* -------------- */ 3766 /* device control */ 3767 3768 static usbd_status 3769 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3770 { 3771 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3772 usbd_status err; 3773 3774 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3775 3776 /* Insert last in queue. */ 3777 mutex_enter(&sc->sc_lock); 3778 err = usb_insert_transfer(xfer); 3779 mutex_exit(&sc->sc_lock); 3780 if (err) 3781 return err; 3782 3783 /* Pipe isn't running, start first */ 3784 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3785 } 3786 3787 static usbd_status 3788 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3789 { 3790 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3791 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3792 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3793 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3794 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3795 usb_device_request_t * const req = &xfer->ux_request; 3796 const int isread = usbd_xfer_isread(xfer); 3797 const uint32_t len = UGETW(req->wLength); 3798 usb_dma_t * const dma = &xfer->ux_dmabuf; 3799 uint64_t parameter; 3800 uint32_t status; 3801 uint32_t control; 3802 u_int i; 3803 3804 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3805 DPRINTFN(12, "req: %04jx %04jx %04jx %04jx", 3806 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3807 UGETW(req->wIndex), UGETW(req->wLength)); 3808 3809 /* we rely on the bottom bits for extra info */ 3810 KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx", 3811 (uintptr_t) xfer); 3812 3813 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3814 3815 i = 0; 3816 3817 /* setup phase */ 3818 memcpy(¶meter, req, sizeof(parameter)); 3819 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3820 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3821 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3822 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3823 XHCI_TRB_3_IDT_BIT; 3824 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3825 3826 if (len != 0) { 3827 /* data phase */ 3828 parameter = DMAADDR(dma, 0); 3829 KASSERTMSG(len <= 0x10000, "len %d", len); 3830 status = XHCI_TRB_2_IRQ_SET(0) | 3831 XHCI_TRB_2_TDSZ_SET(1) | 3832 XHCI_TRB_2_BYTES_SET(len); 3833 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3834 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3835 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3836 XHCI_TRB_3_IOC_BIT; 3837 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3838 } 3839 3840 parameter = 0; 3841 status = XHCI_TRB_2_IRQ_SET(0); 3842 /* the status stage has inverted direction */ 3843 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3844 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3845 XHCI_TRB_3_IOC_BIT; 3846 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3847 xfer->ux_status = USBD_IN_PROGRESS; 3848 3849 mutex_enter(&tr->xr_lock); 3850 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3851 mutex_exit(&tr->xr_lock); 3852 3853 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3854 3855 if (xfer->ux_timeout && !xhci_polling_p(sc)) { 3856 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3857 xhci_timeout, xfer); 3858 } 3859 3860 return USBD_IN_PROGRESS; 3861 } 3862 3863 static void 3864 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3865 { 3866 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3867 usb_device_request_t *req = &xfer->ux_request; 3868 int len = UGETW(req->wLength); 3869 int rd = req->bmRequestType & UT_READ; 3870 3871 if (len) 3872 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3873 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3874 } 3875 3876 static void 3877 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3878 { 3879 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3880 3881 xhci_abort_xfer(xfer, USBD_CANCELLED); 3882 } 3883 3884 static void 3885 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3886 { 3887 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3888 3889 xhci_close_pipe(pipe); 3890 } 3891 3892 /* ------------------ */ 3893 /* device isochronous */ 3894 3895 /* ----------- */ 3896 /* device bulk */ 3897 3898 static usbd_status 3899 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3900 { 3901 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3902 usbd_status err; 3903 3904 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3905 3906 /* Insert last in queue. */ 3907 mutex_enter(&sc->sc_lock); 3908 err = usb_insert_transfer(xfer); 3909 mutex_exit(&sc->sc_lock); 3910 if (err) 3911 return err; 3912 3913 /* 3914 * Pipe isn't running (otherwise err would be USBD_INPROG), 3915 * so start it first. 3916 */ 3917 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3918 } 3919 3920 static usbd_status 3921 xhci_device_bulk_start(struct usbd_xfer *xfer) 3922 { 3923 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3924 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3925 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3926 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3927 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3928 const uint32_t len = xfer->ux_length; 3929 usb_dma_t * const dma = &xfer->ux_dmabuf; 3930 uint64_t parameter; 3931 uint32_t status; 3932 uint32_t control; 3933 u_int i = 0; 3934 3935 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3936 3937 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 3938 0); 3939 3940 if (sc->sc_dying) 3941 return USBD_IOERROR; 3942 3943 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3944 3945 parameter = DMAADDR(dma, 0); 3946 /* 3947 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3948 * If the user supplied buffer crosses such a boundary then 2 3949 * (or more) TRB should be used. 3950 * If multiple TRB are used the td_size field must be set correctly. 3951 * For v1.0 devices (like ivy bridge) this is the number of usb data 3952 * blocks needed to complete the transfer. 3953 * Setting it to 1 in the last TRB causes an extra zero-length 3954 * data block be sent. 3955 * The earlier documentation differs, I don't know how it behaves. 3956 */ 3957 KASSERTMSG(len <= 0x10000, "len %d", len); 3958 status = XHCI_TRB_2_IRQ_SET(0) | 3959 XHCI_TRB_2_TDSZ_SET(1) | 3960 XHCI_TRB_2_BYTES_SET(len); 3961 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3962 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3963 XHCI_TRB_3_IOC_BIT; 3964 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3965 xfer->ux_status = USBD_IN_PROGRESS; 3966 3967 mutex_enter(&tr->xr_lock); 3968 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3969 mutex_exit(&tr->xr_lock); 3970 3971 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3972 3973 if (xfer->ux_timeout && !xhci_polling_p(sc)) { 3974 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3975 xhci_timeout, xfer); 3976 } 3977 3978 return USBD_IN_PROGRESS; 3979 } 3980 3981 static void 3982 xhci_device_bulk_done(struct usbd_xfer *xfer) 3983 { 3984 #ifdef USB_DEBUG 3985 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3986 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3987 #endif 3988 const int isread = usbd_xfer_isread(xfer); 3989 3990 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3991 3992 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 3993 0); 3994 3995 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3996 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3997 } 3998 3999 static void 4000 xhci_device_bulk_abort(struct usbd_xfer *xfer) 4001 { 4002 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4003 4004 xhci_abort_xfer(xfer, USBD_CANCELLED); 4005 } 4006 4007 static void 4008 xhci_device_bulk_close(struct usbd_pipe *pipe) 4009 { 4010 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4011 4012 xhci_close_pipe(pipe); 4013 } 4014 4015 /* ---------------- */ 4016 /* device interrupt */ 4017 4018 static usbd_status 4019 xhci_device_intr_transfer(struct usbd_xfer *xfer) 4020 { 4021 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4022 usbd_status err; 4023 4024 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4025 4026 /* Insert last in queue. */ 4027 mutex_enter(&sc->sc_lock); 4028 err = usb_insert_transfer(xfer); 4029 mutex_exit(&sc->sc_lock); 4030 if (err) 4031 return err; 4032 4033 /* 4034 * Pipe isn't running (otherwise err would be USBD_INPROG), 4035 * so start it first. 4036 */ 4037 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4038 } 4039 4040 static usbd_status 4041 xhci_device_intr_start(struct usbd_xfer *xfer) 4042 { 4043 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4044 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4045 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4046 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 4047 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 4048 const uint32_t len = xfer->ux_length; 4049 usb_dma_t * const dma = &xfer->ux_dmabuf; 4050 uint64_t parameter; 4051 uint32_t status; 4052 uint32_t control; 4053 u_int i = 0; 4054 4055 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4056 4057 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 4058 0); 4059 4060 if (sc->sc_dying) 4061 return USBD_IOERROR; 4062 4063 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 4064 4065 parameter = DMAADDR(dma, 0); 4066 KASSERTMSG(len <= 0x10000, "len %d", len); 4067 status = XHCI_TRB_2_IRQ_SET(0) | 4068 XHCI_TRB_2_TDSZ_SET(1) | 4069 XHCI_TRB_2_BYTES_SET(len); 4070 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 4071 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 4072 XHCI_TRB_3_IOC_BIT; 4073 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 4074 xfer->ux_status = USBD_IN_PROGRESS; 4075 4076 mutex_enter(&tr->xr_lock); 4077 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 4078 mutex_exit(&tr->xr_lock); 4079 4080 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4081 4082 if (xfer->ux_timeout && !xhci_polling_p(sc)) { 4083 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4084 xhci_timeout, xfer); 4085 } 4086 4087 return USBD_IN_PROGRESS; 4088 } 4089 4090 static void 4091 xhci_device_intr_done(struct usbd_xfer *xfer) 4092 { 4093 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4094 #ifdef USB_DEBUG 4095 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4096 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4097 #endif 4098 const int isread = usbd_xfer_isread(xfer); 4099 4100 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4101 4102 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 4103 0); 4104 4105 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 4106 4107 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4108 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4109 } 4110 4111 static void 4112 xhci_device_intr_abort(struct usbd_xfer *xfer) 4113 { 4114 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4115 4116 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4117 4118 KASSERT(mutex_owned(&sc->sc_lock)); 4119 DPRINTFN(15, "%#jx", (uintptr_t)xfer, 0, 0, 0); 4120 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4121 xhci_abort_xfer(xfer, USBD_CANCELLED); 4122 } 4123 4124 static void 4125 xhci_device_intr_close(struct usbd_pipe *pipe) 4126 { 4127 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 4128 4129 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4130 DPRINTFN(15, "%#jx", (uintptr_t)pipe, 0, 0, 0); 4131 4132 xhci_close_pipe(pipe); 4133 } 4134 4135 /* ------------ */ 4136 4137 static void 4138 xhci_timeout(void *addr) 4139 { 4140 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4141 struct xhci_xfer * const xx = addr; 4142 struct usbd_xfer * const xfer = &xx->xx_xfer; 4143 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4144 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4145 4146 mutex_enter(&sc->sc_lock); 4147 if (!sc->sc_dying && xfer->ux_status == USBD_IN_PROGRESS) 4148 usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC); 4149 mutex_exit(&sc->sc_lock); 4150 } 4151 4152 static void 4153 xhci_timeout_task(void *addr) 4154 { 4155 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4156 struct usbd_xfer * const xfer = addr; 4157 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4158 4159 mutex_enter(&sc->sc_lock); 4160 xhci_abort_xfer(xfer, USBD_TIMEOUT); 4161 mutex_exit(&sc->sc_lock); 4162 } 4163
Indexes created Wed Oct 01 18:09:54 GMT 2025