xhci.c revision 1.74
1 /* $NetBSD: xhci.c,v 1.74 2017/09/25 00:03:10 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.74 2017/09/25 00:03:10 jmcneill Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static void xhci_host_dequeue(struct xhci_ring * const); 146 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 147 148 static usbd_status xhci_do_command(struct xhci_softc * const, 149 struct xhci_trb * const, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 153 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 154 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 155 static usbd_status xhci_enable_slot(struct xhci_softc * const, 156 uint8_t * const); 157 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 158 static usbd_status xhci_address_device(struct xhci_softc * const, 159 uint64_t, uint8_t, bool); 160 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 161 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 162 struct xhci_slot * const, u_int); 163 static usbd_status xhci_ring_init(struct xhci_softc * const, 164 struct xhci_ring * const, size_t, size_t); 165 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 166 167 static void xhci_setup_ctx(struct usbd_pipe *); 168 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 169 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 170 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 171 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 172 173 static void xhci_noop(struct usbd_pipe *); 174 175 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 176 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 177 static void xhci_root_intr_abort(struct usbd_xfer *); 178 static void xhci_root_intr_close(struct usbd_pipe *); 179 static void xhci_root_intr_done(struct usbd_xfer *); 180 181 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 182 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 183 static void xhci_device_ctrl_abort(struct usbd_xfer *); 184 static void xhci_device_ctrl_close(struct usbd_pipe *); 185 static void xhci_device_ctrl_done(struct usbd_xfer *); 186 187 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 188 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 189 static void xhci_device_intr_abort(struct usbd_xfer *); 190 static void xhci_device_intr_close(struct usbd_pipe *); 191 static void xhci_device_intr_done(struct usbd_xfer *); 192 193 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 194 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 195 static void xhci_device_bulk_abort(struct usbd_xfer *); 196 static void xhci_device_bulk_close(struct usbd_pipe *); 197 static void xhci_device_bulk_done(struct usbd_xfer *); 198 199 static void xhci_timeout(void *); 200 static void xhci_timeout_task(void *); 201 202 static const struct usbd_bus_methods xhci_bus_methods = { 203 .ubm_open = xhci_open, 204 .ubm_softint = xhci_softintr, 205 .ubm_dopoll = xhci_poll, 206 .ubm_allocx = xhci_allocx, 207 .ubm_freex = xhci_freex, 208 .ubm_getlock = xhci_get_lock, 209 .ubm_newdev = xhci_new_device, 210 .ubm_rhctrl = xhci_roothub_ctrl, 211 }; 212 213 static const struct usbd_pipe_methods xhci_root_intr_methods = { 214 .upm_transfer = xhci_root_intr_transfer, 215 .upm_start = xhci_root_intr_start, 216 .upm_abort = xhci_root_intr_abort, 217 .upm_close = xhci_root_intr_close, 218 .upm_cleartoggle = xhci_noop, 219 .upm_done = xhci_root_intr_done, 220 }; 221 222 223 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 224 .upm_transfer = xhci_device_ctrl_transfer, 225 .upm_start = xhci_device_ctrl_start, 226 .upm_abort = xhci_device_ctrl_abort, 227 .upm_close = xhci_device_ctrl_close, 228 .upm_cleartoggle = xhci_noop, 229 .upm_done = xhci_device_ctrl_done, 230 }; 231 232 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 233 .upm_cleartoggle = xhci_noop, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 237 .upm_transfer = xhci_device_bulk_transfer, 238 .upm_start = xhci_device_bulk_start, 239 .upm_abort = xhci_device_bulk_abort, 240 .upm_close = xhci_device_bulk_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_bulk_done, 243 }; 244 245 static const struct usbd_pipe_methods xhci_device_intr_methods = { 246 .upm_transfer = xhci_device_intr_transfer, 247 .upm_start = xhci_device_intr_start, 248 .upm_abort = xhci_device_intr_abort, 249 .upm_close = xhci_device_intr_close, 250 .upm_cleartoggle = xhci_noop, 251 .upm_done = xhci_device_intr_done, 252 }; 253 254 static inline uint32_t 255 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 256 { 257 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 258 } 259 260 static inline uint32_t 261 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 262 { 263 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 264 } 265 266 static inline void 267 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 268 uint32_t value) 269 { 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 271 } 272 273 #if 0 /* unused */ 274 static inline void 275 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 276 uint32_t value) 277 { 278 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 279 } 280 #endif /* unused */ 281 282 static inline uint32_t 283 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 284 { 285 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 286 } 287 288 static inline uint32_t 289 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 290 { 291 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 292 } 293 294 static inline void 295 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 296 uint32_t value) 297 { 298 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 299 } 300 301 static inline uint64_t 302 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 303 { 304 uint64_t value; 305 306 if (sc->sc_ac64) { 307 #ifdef XHCI_USE_BUS_SPACE_8 308 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 309 #else 310 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 311 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 312 offset + 4) << 32; 313 #endif 314 } else { 315 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 316 } 317 318 return value; 319 } 320 321 static inline void 322 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 336 } 337 } 338 339 static inline uint32_t 340 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 341 { 342 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 343 } 344 345 static inline void 346 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 347 uint32_t value) 348 { 349 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 350 } 351 352 #if 0 /* unused */ 353 static inline uint64_t 354 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 355 { 356 uint64_t value; 357 358 if (sc->sc_ac64) { 359 #ifdef XHCI_USE_BUS_SPACE_8 360 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 361 #else 362 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 363 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 364 offset + 4) << 32; 365 #endif 366 } else { 367 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 368 } 369 370 return value; 371 } 372 #endif /* unused */ 373 374 static inline void 375 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 376 uint64_t value) 377 { 378 if (sc->sc_ac64) { 379 #ifdef XHCI_USE_BUS_SPACE_8 380 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 381 #else 382 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 383 (value >> 0) & 0xffffffff); 384 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 385 (value >> 32) & 0xffffffff); 386 #endif 387 } else { 388 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 389 } 390 } 391 392 #if 0 /* unused */ 393 static inline uint32_t 394 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 395 { 396 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 397 } 398 #endif /* unused */ 399 400 static inline void 401 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 402 uint32_t value) 403 { 404 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 405 } 406 407 /* --- */ 408 409 static inline uint8_t 410 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 411 { 412 u_int eptype = 0; 413 414 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 415 case UE_CONTROL: 416 eptype = 0x0; 417 break; 418 case UE_ISOCHRONOUS: 419 eptype = 0x1; 420 break; 421 case UE_BULK: 422 eptype = 0x2; 423 break; 424 case UE_INTERRUPT: 425 eptype = 0x3; 426 break; 427 } 428 429 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 430 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 431 return eptype | 0x4; 432 else 433 return eptype; 434 } 435 436 static u_int 437 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 438 { 439 /* xHCI 1.0 section 4.5.1 */ 440 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 441 u_int in = 0; 442 443 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 444 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 445 in = 1; 446 447 return epaddr * 2 + in; 448 } 449 450 static inline u_int 451 xhci_dci_to_ici(const u_int i) 452 { 453 return i + 1; 454 } 455 456 static inline void * 457 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 458 const u_int dci) 459 { 460 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 461 } 462 463 #if 0 /* unused */ 464 static inline bus_addr_t 465 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 466 const u_int dci) 467 { 468 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 469 } 470 #endif /* unused */ 471 472 static inline void * 473 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline bus_addr_t 480 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 481 const u_int ici) 482 { 483 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 484 } 485 486 static inline struct xhci_trb * 487 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 488 { 489 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 490 } 491 492 static inline bus_addr_t 493 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 494 { 495 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 496 } 497 498 static inline void 499 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 500 uint32_t control) 501 { 502 trb->trb_0 = htole64(parameter); 503 trb->trb_2 = htole32(status); 504 trb->trb_3 = htole32(control); 505 } 506 507 static int 508 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 509 { 510 /* base address of TRBs */ 511 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 512 513 /* trb_0 range sanity check */ 514 if (trb_0 == 0 || trb_0 < trbp || 515 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 516 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 517 return 1; 518 } 519 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 520 return 0; 521 } 522 523 static unsigned int 524 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 525 u_int dci) 526 { 527 uint32_t *cp; 528 529 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 530 cp = xhci_slot_get_dcv(sc, xs, dci); 531 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 532 } 533 534 static inline unsigned int 535 xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport) 536 { 537 const unsigned int port = ctlrport - 1; 538 const uint8_t bit = __BIT(port % NBBY); 539 540 return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit); 541 } 542 543 /* 544 * Return the roothub port for a controller port. Both are 1..n. 545 */ 546 static inline unsigned int 547 xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport) 548 { 549 550 return sc->sc_ctlrportmap[ctrlport - 1]; 551 } 552 553 /* 554 * Return the controller port for a bus roothub port. Both are 1..n. 555 */ 556 static inline unsigned int 557 xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn, 558 unsigned int rhport) 559 { 560 561 return sc->sc_rhportmap[bn][rhport - 1]; 562 } 563 564 /* --- */ 565 566 void 567 xhci_childdet(device_t self, device_t child) 568 { 569 struct xhci_softc * const sc = device_private(self); 570 571 KASSERT(sc->sc_child == child); 572 if (child == sc->sc_child) 573 sc->sc_child = NULL; 574 } 575 576 int 577 xhci_detach(struct xhci_softc *sc, int flags) 578 { 579 int rv = 0; 580 581 if (sc->sc_child2 != NULL) { 582 rv = config_detach(sc->sc_child2, flags); 583 if (rv != 0) 584 return rv; 585 } 586 587 if (sc->sc_child != NULL) { 588 rv = config_detach(sc->sc_child, flags); 589 if (rv != 0) 590 return rv; 591 } 592 593 /* XXX unconfigure/free slots */ 594 595 /* verify: */ 596 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 597 xhci_op_write_4(sc, XHCI_USBCMD, 0); 598 /* do we need to wait for stop? */ 599 600 xhci_op_write_8(sc, XHCI_CRCR, 0); 601 xhci_ring_free(sc, &sc->sc_cr); 602 cv_destroy(&sc->sc_command_cv); 603 cv_destroy(&sc->sc_cmdbusy_cv); 604 605 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 606 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 607 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 608 xhci_ring_free(sc, &sc->sc_er); 609 610 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 611 612 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 613 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 614 615 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 616 617 kmem_free(sc->sc_ctlrportbus, 618 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY)); 619 kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int)); 620 621 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 622 kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int)); 623 } 624 625 mutex_destroy(&sc->sc_lock); 626 mutex_destroy(&sc->sc_intr_lock); 627 628 pool_cache_destroy(sc->sc_xferpool); 629 630 return rv; 631 } 632 633 int 634 xhci_activate(device_t self, enum devact act) 635 { 636 struct xhci_softc * const sc = device_private(self); 637 638 switch (act) { 639 case DVACT_DEACTIVATE: 640 sc->sc_dying = true; 641 return 0; 642 default: 643 return EOPNOTSUPP; 644 } 645 } 646 647 bool 648 xhci_suspend(device_t dv, const pmf_qual_t *qual) 649 { 650 return false; 651 } 652 653 bool 654 xhci_resume(device_t dv, const pmf_qual_t *qual) 655 { 656 return false; 657 } 658 659 bool 660 xhci_shutdown(device_t self, int flags) 661 { 662 return false; 663 } 664 665 static int 666 xhci_hc_reset(struct xhci_softc * const sc) 667 { 668 uint32_t usbcmd, usbsts; 669 int i; 670 671 /* Check controller not ready */ 672 for (i = 0; i < XHCI_WAIT_CNR; i++) { 673 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 674 if ((usbsts & XHCI_STS_CNR) == 0) 675 break; 676 usb_delay_ms(&sc->sc_bus, 1); 677 } 678 if (i >= XHCI_WAIT_CNR) { 679 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 680 return EIO; 681 } 682 683 /* Halt controller */ 684 usbcmd = 0; 685 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 686 usb_delay_ms(&sc->sc_bus, 1); 687 688 /* Reset controller */ 689 usbcmd = XHCI_CMD_HCRST; 690 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 691 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 692 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 693 if ((usbcmd & XHCI_CMD_HCRST) == 0) 694 break; 695 usb_delay_ms(&sc->sc_bus, 1); 696 } 697 if (i >= XHCI_WAIT_HCRST) { 698 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 699 return EIO; 700 } 701 702 /* Check controller not ready */ 703 for (i = 0; i < XHCI_WAIT_CNR; i++) { 704 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 705 if ((usbsts & XHCI_STS_CNR) == 0) 706 break; 707 usb_delay_ms(&sc->sc_bus, 1); 708 } 709 if (i >= XHCI_WAIT_CNR) { 710 aprint_error_dev(sc->sc_dev, 711 "controller not ready timeout after reset\n"); 712 return EIO; 713 } 714 715 return 0; 716 } 717 718 719 static void 720 hexdump(const char *msg, const void *base, size_t len) 721 { 722 #if 0 723 size_t cnt; 724 const uint32_t *p; 725 extern paddr_t vtophys(vaddr_t); 726 727 p = base; 728 cnt = 0; 729 730 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 731 (void *)vtophys((vaddr_t)base)); 732 733 while (cnt < len) { 734 if (cnt % 16 == 0) 735 printf("%p: ", p); 736 else if (cnt % 8 == 0) 737 printf(" |"); 738 printf(" %08x", *p++); 739 cnt += 4; 740 if (cnt % 16 == 0) 741 printf("\n"); 742 } 743 if (cnt % 16 != 0) 744 printf("\n"); 745 #endif 746 } 747 748 /* 7.2 xHCI Support Protocol Capability */ 749 static void 750 xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp) 751 { 752 /* XXX Cache this lot */ 753 754 const uint32_t w0 = xhci_read_4(sc, ecp); 755 const uint32_t w4 = xhci_read_4(sc, ecp + 4); 756 const uint32_t w8 = xhci_read_4(sc, ecp + 8); 757 const uint32_t wc = xhci_read_4(sc, ecp + 0xc); 758 759 aprint_debug_dev(sc->sc_dev, 760 " SP: %08x %08x %08x %08x\n", w0, w4, w8, wc); 761 762 if (w4 != XHCI_XECP_USBID) 763 return; 764 765 const int major = XHCI_XECP_SP_W0_MAJOR(w0); 766 const int minor = XHCI_XECP_SP_W0_MINOR(w0); 767 const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8); 768 const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8); 769 770 const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16)); 771 switch (mm) { 772 case 0x0200: 773 case 0x0300: 774 case 0x0301: 775 aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n", 776 major == 3 ? "ss" : "hs", cpo, cpo + cpc -1); 777 break; 778 default: 779 aprint_debug_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n", 780 major, minor); 781 return; 782 } 783 784 const size_t bus = (major == 3) ? 0 : 1; 785 786 /* Index arrays with 0..n-1 where ports are numbered 1..n */ 787 for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) { 788 if (sc->sc_ctlrportmap[cp] != 0) { 789 aprint_error_dev(sc->sc_dev, "contoller port %zu " 790 "already assigned", cp); 791 continue; 792 } 793 794 sc->sc_ctlrportbus[cp / NBBY] |= 795 bus == 0 ? 0 : __BIT(cp % NBBY); 796 797 const size_t rhp = sc->sc_rhportcount[bus]++; 798 799 KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0, 800 "bus %zu rhp %zu is %d", bus, rhp, 801 sc->sc_rhportmap[bus][rhp]); 802 803 sc->sc_rhportmap[bus][rhp] = cp + 1; 804 sc->sc_ctlrportmap[cp] = rhp + 1; 805 } 806 } 807 808 /* Process extended capabilities */ 809 static void 810 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 811 { 812 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 813 814 bus_size_t ecp = XHCI_HCC_XECP(hcc) * 4; 815 while (ecp != 0) { 816 uint32_t ecr = xhci_read_4(sc, ecp); 817 aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr); 818 switch (XHCI_XECP_ID(ecr)) { 819 case XHCI_ID_PROTOCOLS: { 820 xhci_id_protocols(sc, ecp); 821 break; 822 } 823 case XHCI_ID_USB_LEGACY: { 824 uint8_t bios_sem; 825 826 /* Take host controller ownership from BIOS */ 827 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 828 if (bios_sem) { 829 /* sets xHCI to be owned by OS */ 830 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 831 aprint_debug_dev(sc->sc_dev, 832 "waiting for BIOS to give up control\n"); 833 for (int i = 0; i < 5000; i++) { 834 bios_sem = xhci_read_1(sc, ecp + 835 XHCI_XECP_BIOS_SEM); 836 if (bios_sem == 0) 837 break; 838 DELAY(1000); 839 } 840 if (bios_sem) { 841 aprint_error_dev(sc->sc_dev, 842 "timed out waiting for BIOS\n"); 843 } 844 } 845 break; 846 } 847 default: 848 break; 849 } 850 ecr = xhci_read_4(sc, ecp); 851 if (XHCI_XECP_NEXT(ecr) == 0) { 852 ecp = 0; 853 } else { 854 ecp += XHCI_XECP_NEXT(ecr) * 4; 855 } 856 } 857 } 858 859 #define XHCI_HCCPREV1_BITS \ 860 "\177\020" /* New bitmask */ \ 861 "f\020\020XECP\0" \ 862 "f\014\4MAXPSA\0" \ 863 "b\013CFC\0" \ 864 "b\012SEC\0" \ 865 "b\011SBD\0" \ 866 "b\010FSE\0" \ 867 "b\7NSS\0" \ 868 "b\6LTC\0" \ 869 "b\5LHRC\0" \ 870 "b\4PIND\0" \ 871 "b\3PPC\0" \ 872 "b\2CZC\0" \ 873 "b\1BNC\0" \ 874 "b\0AC64\0" \ 875 "\0" 876 #define XHCI_HCCV1_x_BITS \ 877 "\177\020" /* New bitmask */ \ 878 "f\020\020XECP\0" \ 879 "f\014\4MAXPSA\0" \ 880 "b\013CFC\0" \ 881 "b\012SEC\0" \ 882 "b\011SPC\0" \ 883 "b\010PAE\0" \ 884 "b\7NSS\0" \ 885 "b\6LTC\0" \ 886 "b\5LHRC\0" \ 887 "b\4PIND\0" \ 888 "b\3PPC\0" \ 889 "b\2CSZ\0" \ 890 "b\1BNC\0" \ 891 "b\0AC64\0" \ 892 "\0" 893 894 void 895 xhci_start(struct xhci_softc *sc) 896 { 897 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 898 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 899 /* Intel xhci needs interrupt rate moderated. */ 900 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 901 else 902 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 903 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 904 xhci_rt_read_4(sc, XHCI_IMOD(0))); 905 906 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 907 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 908 xhci_op_read_4(sc, XHCI_USBCMD)); 909 } 910 911 int 912 xhci_init(struct xhci_softc *sc) 913 { 914 bus_size_t bsz; 915 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 916 uint32_t pagesize, config; 917 int i = 0; 918 uint16_t hciversion; 919 uint8_t caplength; 920 921 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 922 923 /* Set up the bus struct for the usb 3 and usb 2 buses */ 924 sc->sc_bus.ub_methods = &xhci_bus_methods; 925 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 926 sc->sc_bus.ub_revision = USBREV_3_0; 927 sc->sc_bus.ub_usedma = true; 928 sc->sc_bus.ub_hcpriv = sc; 929 930 sc->sc_bus2.ub_methods = &xhci_bus_methods; 931 sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe); 932 sc->sc_bus2.ub_revision = USBREV_2_0; 933 sc->sc_bus2.ub_usedma = true; 934 sc->sc_bus2.ub_hcpriv = sc; 935 sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag; 936 937 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 938 caplength = XHCI_CAP_CAPLENGTH(cap); 939 hciversion = XHCI_CAP_HCIVERSION(cap); 940 941 if (hciversion < XHCI_HCIVERSION_0_96 || 942 hciversion > XHCI_HCIVERSION_1_0) { 943 aprint_normal_dev(sc->sc_dev, 944 "xHCI version %x.%x not known to be supported\n", 945 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 946 } else { 947 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 948 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 949 } 950 951 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 952 &sc->sc_cbh) != 0) { 953 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 954 return ENOMEM; 955 } 956 957 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 958 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 959 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 960 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 961 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 962 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 963 aprint_debug_dev(sc->sc_dev, 964 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 965 966 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 967 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 968 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 969 970 char sbuf[128]; 971 if (hciversion < XHCI_HCIVERSION_1_0) 972 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 973 else 974 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 975 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 976 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 977 978 /* default all ports to bus 0, i.e. usb 3 */ 979 sc->sc_ctlrportbus = kmem_zalloc( 980 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP); 981 sc->sc_ctlrportmap = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 982 983 /* controller port to bus roothub port map */ 984 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 985 sc->sc_rhportmap[j] = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 986 } 987 988 /* 989 * Process all Extended Capabilities 990 */ 991 xhci_ecp(sc, hcc); 992 993 bsz = XHCI_PORTSC(sc->sc_maxports); 994 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 995 &sc->sc_obh) != 0) { 996 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 997 return ENOMEM; 998 } 999 1000 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 1001 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 1002 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 1003 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 1004 return ENOMEM; 1005 } 1006 1007 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 1008 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 1009 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 1010 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 1011 return ENOMEM; 1012 } 1013 1014 int rv; 1015 rv = xhci_hc_reset(sc); 1016 if (rv != 0) { 1017 return rv; 1018 } 1019 1020 if (sc->sc_vendor_init) 1021 sc->sc_vendor_init(sc); 1022 1023 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 1024 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 1025 pagesize = ffs(pagesize); 1026 if (pagesize == 0) { 1027 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 1028 return EIO; 1029 } 1030 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 1031 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 1032 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 1033 (uint32_t)sc->sc_maxslots); 1034 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 1035 1036 usbd_status err; 1037 1038 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 1039 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 1040 if (sc->sc_maxspbuf != 0) { 1041 err = usb_allocmem(&sc->sc_bus, 1042 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 1043 &sc->sc_spbufarray_dma); 1044 if (err) { 1045 aprint_error_dev(sc->sc_dev, 1046 "spbufarray init fail, err %d\n", err); 1047 return ENOMEM; 1048 } 1049 1050 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 1051 sc->sc_maxspbuf, KM_SLEEP); 1052 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 1053 for (i = 0; i < sc->sc_maxspbuf; i++) { 1054 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 1055 /* allocate contexts */ 1056 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 1057 sc->sc_pgsz, dma); 1058 if (err) { 1059 aprint_error_dev(sc->sc_dev, 1060 "spbufarray_dma init fail, err %d\n", err); 1061 rv = ENOMEM; 1062 goto bad1; 1063 } 1064 spbufarray[i] = htole64(DMAADDR(dma, 0)); 1065 usb_syncmem(dma, 0, sc->sc_pgsz, 1066 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1067 } 1068 1069 usb_syncmem(&sc->sc_spbufarray_dma, 0, 1070 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 1071 } 1072 1073 config = xhci_op_read_4(sc, XHCI_CONFIG); 1074 config &= ~0xFF; 1075 config |= sc->sc_maxslots & 0xFF; 1076 xhci_op_write_4(sc, XHCI_CONFIG, config); 1077 1078 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 1079 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 1080 if (err) { 1081 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 1082 err); 1083 rv = ENOMEM; 1084 goto bad1; 1085 } 1086 1087 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 1088 XHCI_EVENT_RING_SEGMENTS_ALIGN); 1089 if (err) { 1090 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 1091 err); 1092 rv = ENOMEM; 1093 goto bad2; 1094 } 1095 1096 usb_dma_t *dma; 1097 size_t size; 1098 size_t align; 1099 1100 dma = &sc->sc_eventst_dma; 1101 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 1102 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 1103 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 1104 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 1105 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1106 if (err) { 1107 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 1108 err); 1109 rv = ENOMEM; 1110 goto bad3; 1111 } 1112 1113 memset(KERNADDR(dma, 0), 0, size); 1114 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1115 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 1116 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 1117 KERNADDR(&sc->sc_eventst_dma, 0), 1118 sc->sc_eventst_dma.udma_block->size); 1119 1120 dma = &sc->sc_dcbaa_dma; 1121 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 1122 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 1123 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 1124 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1125 if (err) { 1126 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1127 rv = ENOMEM; 1128 goto bad4; 1129 } 1130 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 1131 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1132 KERNADDR(&sc->sc_dcbaa_dma, 0), 1133 sc->sc_dcbaa_dma.udma_block->size); 1134 1135 memset(KERNADDR(dma, 0), 0, size); 1136 if (sc->sc_maxspbuf != 0) { 1137 /* 1138 * DCBA entry 0 hold the scratchbuf array pointer. 1139 */ 1140 *(uint64_t *)KERNADDR(dma, 0) = 1141 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1142 } 1143 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1144 1145 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1146 KM_SLEEP); 1147 if (sc->sc_slots == NULL) { 1148 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1149 rv = ENOMEM; 1150 goto bad; 1151 } 1152 1153 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1154 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1155 if (sc->sc_xferpool == NULL) { 1156 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1157 err); 1158 rv = ENOMEM; 1159 goto bad; 1160 } 1161 1162 cv_init(&sc->sc_command_cv, "xhcicmd"); 1163 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1164 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1165 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1166 1167 struct xhci_erste *erst; 1168 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1169 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1170 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1171 erst[0].erste_3 = htole32(0); 1172 usb_syncmem(&sc->sc_eventst_dma, 0, 1173 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1174 1175 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1176 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1177 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1178 XHCI_ERDP_LO_BUSY); 1179 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1180 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1181 sc->sc_cr.xr_cs); 1182 1183 #if 0 1184 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1185 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1186 #endif 1187 1188 if ((sc->sc_quirks & XHCI_DEFERRED_START) == 0) 1189 xhci_start(sc); 1190 1191 return 0; 1192 1193 bad: 1194 if (sc->sc_xferpool) { 1195 pool_cache_destroy(sc->sc_xferpool); 1196 sc->sc_xferpool = NULL; 1197 } 1198 1199 if (sc->sc_slots) { 1200 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1201 sc->sc_maxslots); 1202 sc->sc_slots = NULL; 1203 } 1204 1205 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1206 bad4: 1207 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1208 bad3: 1209 xhci_ring_free(sc, &sc->sc_er); 1210 bad2: 1211 xhci_ring_free(sc, &sc->sc_cr); 1212 i = sc->sc_maxspbuf; 1213 bad1: 1214 for (int j = 0; j < i; j++) 1215 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1216 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1217 1218 return rv; 1219 } 1220 1221 static inline bool 1222 xhci_polling_p(struct xhci_softc * const sc) 1223 { 1224 return sc->sc_bus.ub_usepolling || sc->sc_bus2.ub_usepolling; 1225 } 1226 1227 int 1228 xhci_intr(void *v) 1229 { 1230 struct xhci_softc * const sc = v; 1231 int ret = 0; 1232 1233 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1234 1235 if (sc == NULL) 1236 return 0; 1237 1238 mutex_spin_enter(&sc->sc_intr_lock); 1239 1240 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1241 goto done; 1242 1243 /* If we get an interrupt while polling, then just ignore it. */ 1244 if (xhci_polling_p(sc)) { 1245 #ifdef DIAGNOSTIC 1246 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1247 #endif 1248 goto done; 1249 } 1250 1251 ret = xhci_intr1(sc); 1252 if (ret) { 1253 usb_schedsoftintr(&sc->sc_bus); 1254 } 1255 done: 1256 mutex_spin_exit(&sc->sc_intr_lock); 1257 return ret; 1258 } 1259 1260 int 1261 xhci_intr1(struct xhci_softc * const sc) 1262 { 1263 uint32_t usbsts; 1264 uint32_t iman; 1265 1266 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1267 1268 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1269 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1270 #if 0 1271 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1272 return 0; 1273 } 1274 #endif 1275 xhci_op_write_4(sc, XHCI_USBSTS, 1276 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1277 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1278 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1279 1280 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1281 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1282 iman |= XHCI_IMAN_INTR_PEND; 1283 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1284 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1285 DPRINTFN(16, "IMAN0 %08x", iman, 0, 0, 0); 1286 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1287 DPRINTFN(16, "USBSTS %08x", usbsts, 0, 0, 0); 1288 1289 return 1; 1290 } 1291 1292 /* 1293 * 3 port speed types used in USB stack 1294 * 1295 * usbdi speed 1296 * definition: USB_SPEED_* in usb.h 1297 * They are used in struct usbd_device in USB stack. 1298 * ioctl interface uses these values too. 1299 * port_status speed 1300 * definition: UPS_*_SPEED in usb.h 1301 * They are used in usb_port_status_t and valid only for USB 2.0. 1302 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1303 * of usb_port_status_ext_t indicates port speed. 1304 * Note that some 3.0 values overlap with 2.0 values. 1305 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1306 * means UPS_LOW_SPEED in HS.) 1307 * port status returned from hub also uses these values. 1308 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1309 * or more. 1310 * xspeed: 1311 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1312 * They are used in only slot context and PORTSC reg of xhci. 1313 * The difference between usbdi speed and xspeed is 1314 * that FS and LS values are swapped. 1315 */ 1316 1317 /* convert usbdi speed to xspeed */ 1318 static int 1319 xhci_speed2xspeed(int speed) 1320 { 1321 switch (speed) { 1322 case USB_SPEED_LOW: return 2; 1323 case USB_SPEED_FULL: return 1; 1324 default: return speed; 1325 } 1326 } 1327 1328 #if 0 1329 /* convert xspeed to usbdi speed */ 1330 static int 1331 xhci_xspeed2speed(int xspeed) 1332 { 1333 switch (xspeed) { 1334 case 1: return USB_SPEED_FULL; 1335 case 2: return USB_SPEED_LOW; 1336 default: return xspeed; 1337 } 1338 } 1339 #endif 1340 1341 /* convert xspeed to port status speed */ 1342 static int 1343 xhci_xspeed2psspeed(int xspeed) 1344 { 1345 switch (xspeed) { 1346 case 0: return 0; 1347 case 1: return UPS_FULL_SPEED; 1348 case 2: return UPS_LOW_SPEED; 1349 case 3: return UPS_HIGH_SPEED; 1350 default: return UPS_OTHER_SPEED; 1351 } 1352 } 1353 1354 /* 1355 * Construct input contexts and issue TRB to open pipe. 1356 */ 1357 static usbd_status 1358 xhci_configure_endpoint(struct usbd_pipe *pipe) 1359 { 1360 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1361 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1362 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1363 struct xhci_trb trb; 1364 usbd_status err; 1365 1366 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1367 DPRINTFN(4, "slot %u dci %u epaddr 0x%02x attr 0x%02x", 1368 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1369 pipe->up_endpoint->ue_edesc->bmAttributes); 1370 1371 /* XXX ensure input context is available? */ 1372 1373 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1374 1375 /* set up context */ 1376 xhci_setup_ctx(pipe); 1377 1378 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1379 sc->sc_ctxsz * 1); 1380 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1381 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1382 1383 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1384 trb.trb_2 = 0; 1385 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1386 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1387 1388 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1389 1390 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1391 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1392 sc->sc_ctxsz * 1); 1393 1394 return err; 1395 } 1396 1397 #if 0 1398 static usbd_status 1399 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1400 { 1401 #ifdef USB_DEBUG 1402 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1403 #endif 1404 1405 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1406 DPRINTFN(4, "slot %u", xs->xs_idx, 0, 0, 0); 1407 1408 return USBD_NORMAL_COMPLETION; 1409 } 1410 #endif 1411 1412 /* 4.6.8, 6.4.3.7 */ 1413 static usbd_status 1414 xhci_reset_endpoint_locked(struct usbd_pipe *pipe) 1415 { 1416 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1417 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1418 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1419 struct xhci_trb trb; 1420 usbd_status err; 1421 1422 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1423 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1424 1425 KASSERT(mutex_owned(&sc->sc_lock)); 1426 1427 trb.trb_0 = 0; 1428 trb.trb_2 = 0; 1429 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1430 XHCI_TRB_3_EP_SET(dci) | 1431 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1432 1433 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1434 1435 return err; 1436 } 1437 1438 static usbd_status 1439 xhci_reset_endpoint(struct usbd_pipe *pipe) 1440 { 1441 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1442 1443 mutex_enter(&sc->sc_lock); 1444 usbd_status ret = xhci_reset_endpoint_locked(pipe); 1445 mutex_exit(&sc->sc_lock); 1446 1447 return ret; 1448 } 1449 1450 /* 1451 * 4.6.9, 6.4.3.8 1452 * Stop execution of TDs on xfer ring. 1453 * Should be called with sc_lock held. 1454 */ 1455 static usbd_status 1456 xhci_stop_endpoint(struct usbd_pipe *pipe) 1457 { 1458 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1459 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1460 struct xhci_trb trb; 1461 usbd_status err; 1462 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1463 1464 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1465 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1466 1467 KASSERT(mutex_owned(&sc->sc_lock)); 1468 1469 trb.trb_0 = 0; 1470 trb.trb_2 = 0; 1471 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1472 XHCI_TRB_3_EP_SET(dci) | 1473 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1474 1475 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1476 1477 return err; 1478 } 1479 1480 /* 1481 * Set TR Dequeue Pointer. 1482 * xHCI 1.1 4.6.10 6.4.3.9 1483 * Purge all of the TRBs on ring and reinitialize ring. 1484 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1485 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1486 * error will be generated. 1487 */ 1488 static usbd_status 1489 xhci_set_dequeue_locked(struct usbd_pipe *pipe) 1490 { 1491 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1492 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1493 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1494 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1495 struct xhci_trb trb; 1496 usbd_status err; 1497 1498 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1499 DPRINTFN(4, "slot %u dci %u", xs->xs_idx, dci, 0, 0); 1500 1501 KASSERT(mutex_owned(&sc->sc_lock)); 1502 1503 xhci_host_dequeue(xr); 1504 1505 /* set DCS */ 1506 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1507 trb.trb_2 = 0; 1508 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1509 XHCI_TRB_3_EP_SET(dci) | 1510 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1511 1512 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1513 1514 return err; 1515 } 1516 1517 static usbd_status 1518 xhci_set_dequeue(struct usbd_pipe *pipe) 1519 { 1520 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1521 1522 mutex_enter(&sc->sc_lock); 1523 usbd_status ret = xhci_set_dequeue_locked(pipe); 1524 mutex_exit(&sc->sc_lock); 1525 1526 return ret; 1527 } 1528 1529 /* 1530 * Open new pipe: called from usbd_setup_pipe_flags. 1531 * Fills methods of pipe. 1532 * If pipe is not for ep0, calls configure_endpoint. 1533 */ 1534 static usbd_status 1535 xhci_open(struct usbd_pipe *pipe) 1536 { 1537 struct usbd_device * const dev = pipe->up_dev; 1538 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1539 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1540 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1541 1542 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1543 DPRINTFN(1, "addr %d depth %d port %d speed %d", dev->ud_addr, 1544 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1545 DPRINTFN(1, " dci %u type 0x%02x epaddr 0x%02x attr 0x%02x", 1546 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1547 ed->bmAttributes); 1548 DPRINTFN(1, " mps %u ival %u", UGETW(ed->wMaxPacketSize), ed->bInterval, 1549 0, 0); 1550 1551 if (sc->sc_dying) 1552 return USBD_IOERROR; 1553 1554 /* Root Hub */ 1555 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1556 switch (ed->bEndpointAddress) { 1557 case USB_CONTROL_ENDPOINT: 1558 pipe->up_methods = &roothub_ctrl_methods; 1559 break; 1560 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1561 pipe->up_methods = &xhci_root_intr_methods; 1562 break; 1563 default: 1564 pipe->up_methods = NULL; 1565 DPRINTFN(0, "bad bEndpointAddress 0x%02x", 1566 ed->bEndpointAddress, 0, 0, 0); 1567 return USBD_INVAL; 1568 } 1569 return USBD_NORMAL_COMPLETION; 1570 } 1571 1572 switch (xfertype) { 1573 case UE_CONTROL: 1574 pipe->up_methods = &xhci_device_ctrl_methods; 1575 break; 1576 case UE_ISOCHRONOUS: 1577 pipe->up_methods = &xhci_device_isoc_methods; 1578 return USBD_INVAL; 1579 break; 1580 case UE_BULK: 1581 pipe->up_methods = &xhci_device_bulk_methods; 1582 break; 1583 case UE_INTERRUPT: 1584 pipe->up_methods = &xhci_device_intr_methods; 1585 break; 1586 default: 1587 return USBD_IOERROR; 1588 break; 1589 } 1590 1591 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1592 return xhci_configure_endpoint(pipe); 1593 1594 return USBD_NORMAL_COMPLETION; 1595 } 1596 1597 /* 1598 * Closes pipe, called from usbd_kill_pipe via close methods. 1599 * If the endpoint to be closed is ep0, disable_slot. 1600 * Should be called with sc_lock held. 1601 */ 1602 static void 1603 xhci_close_pipe(struct usbd_pipe *pipe) 1604 { 1605 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1606 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1607 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1608 const u_int dci = xhci_ep_get_dci(ed); 1609 struct xhci_trb trb; 1610 uint32_t *cp; 1611 1612 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1613 1614 if (sc->sc_dying) 1615 return; 1616 1617 /* xs is uninitialized before xhci_init_slot */ 1618 if (xs == NULL || xs->xs_idx == 0) 1619 return; 1620 1621 DPRINTFN(4, "pipe %p slot %u dci %u", pipe, xs->xs_idx, dci, 0); 1622 1623 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1624 KASSERT(mutex_owned(&sc->sc_lock)); 1625 1626 if (pipe->up_dev->ud_depth == 0) 1627 return; 1628 1629 if (dci == XHCI_DCI_EP_CONTROL) { 1630 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1631 xhci_disable_slot(sc, xs->xs_idx); 1632 return; 1633 } 1634 1635 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED) 1636 (void)xhci_stop_endpoint(pipe); 1637 1638 /* 1639 * set appropriate bit to be dropped. 1640 * don't set DC bit to 1, otherwise all endpoints 1641 * would be deconfigured. 1642 */ 1643 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1644 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1645 cp[1] = htole32(0); 1646 1647 /* XXX should be most significant one, not dci? */ 1648 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1649 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1650 1651 /* configure ep context performs an implicit dequeue */ 1652 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 1653 1654 /* sync input contexts before they are read from memory */ 1655 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1656 1657 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1658 trb.trb_2 = 0; 1659 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1660 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1661 1662 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1663 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1664 } 1665 1666 /* 1667 * Abort transfer. 1668 * Should be called with sc_lock held. 1669 */ 1670 static void 1671 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1672 { 1673 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1674 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1675 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1676 1677 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1678 DPRINTFN(4, "xfer %p pipe %p status %d", 1679 xfer, xfer->ux_pipe, status, 0); 1680 1681 KASSERT(mutex_owned(&sc->sc_lock)); 1682 1683 if (sc->sc_dying) { 1684 /* If we're dying, just do the software part. */ 1685 DPRINTFN(4, "xfer %p dying %u", xfer, xfer->ux_status, 0, 0); 1686 xfer->ux_status = status; 1687 callout_stop(&xfer->ux_callout); 1688 usb_transfer_complete(xfer); 1689 return; 1690 } 1691 1692 /* 1693 * If an abort is already in progress then just wait for it to 1694 * complete and return. 1695 */ 1696 if (xfer->ux_hcflags & UXFER_ABORTING) { 1697 DPRINTFN(4, "already aborting", 0, 0, 0, 0); 1698 #ifdef DIAGNOSTIC 1699 if (status == USBD_TIMEOUT) 1700 DPRINTFN(4, "TIMEOUT while aborting", 0, 0, 0, 0); 1701 #endif 1702 /* Override the status which might be USBD_TIMEOUT. */ 1703 xfer->ux_status = status; 1704 DPRINTFN(4, "xfer %p waiting for abort to finish", xfer, 0, 0, 1705 0); 1706 xfer->ux_hcflags |= UXFER_ABORTWAIT; 1707 while (xfer->ux_hcflags & UXFER_ABORTING) 1708 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 1709 return; 1710 } 1711 xfer->ux_hcflags |= UXFER_ABORTING; 1712 1713 /* 1714 * Step 1: Stop xfer timeout timer. 1715 */ 1716 xfer->ux_status = status; 1717 callout_stop(&xfer->ux_callout); 1718 1719 /* 1720 * Step 2: Stop execution of TD on the ring. 1721 */ 1722 switch (xhci_get_epstate(sc, xs, dci)) { 1723 case XHCI_EPSTATE_HALTED: 1724 (void)xhci_reset_endpoint_locked(xfer->ux_pipe); 1725 break; 1726 case XHCI_EPSTATE_STOPPED: 1727 break; 1728 default: 1729 (void)xhci_stop_endpoint(xfer->ux_pipe); 1730 break; 1731 } 1732 #ifdef DIAGNOSTIC 1733 uint32_t epst = xhci_get_epstate(sc, xs, dci); 1734 if (epst != XHCI_EPSTATE_STOPPED) 1735 DPRINTFN(4, "dci %u not stopped %u", dci, epst, 0, 0); 1736 #endif 1737 1738 /* 1739 * Step 3: Remove any vestiges of the xfer from the ring. 1740 */ 1741 xhci_set_dequeue_locked(xfer->ux_pipe); 1742 1743 /* 1744 * Step 4: Notify completion to waiting xfers. 1745 */ 1746 int wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 1747 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 1748 usb_transfer_complete(xfer); 1749 if (wake) { 1750 cv_broadcast(&xfer->ux_hccv); 1751 } 1752 DPRINTFN(14, "end", 0, 0, 0, 0); 1753 1754 KASSERT(mutex_owned(&sc->sc_lock)); 1755 } 1756 1757 static void 1758 xhci_host_dequeue(struct xhci_ring * const xr) 1759 { 1760 /* When dequeueing the controller, update our struct copy too */ 1761 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1762 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1763 BUS_DMASYNC_PREWRITE); 1764 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1765 1766 xr->xr_ep = 0; 1767 xr->xr_cs = 1; 1768 } 1769 1770 /* 1771 * Recover STALLed endpoint. 1772 * xHCI 1.1 sect 4.10.2.1 1773 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1774 * all transfers on transfer ring. 1775 * These are done in thread context asynchronously. 1776 */ 1777 static void 1778 xhci_clear_endpoint_stall_async_task(void *cookie) 1779 { 1780 struct usbd_xfer * const xfer = cookie; 1781 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1782 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1783 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1784 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1785 1786 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1787 DPRINTFN(4, "xfer %p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 1788 1789 xhci_reset_endpoint(xfer->ux_pipe); 1790 xhci_set_dequeue(xfer->ux_pipe); 1791 1792 mutex_enter(&sc->sc_lock); 1793 tr->is_halted = false; 1794 usb_transfer_complete(xfer); 1795 mutex_exit(&sc->sc_lock); 1796 DPRINTFN(4, "ends", 0, 0, 0, 0); 1797 } 1798 1799 static usbd_status 1800 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1801 { 1802 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1803 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1804 1805 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1806 DPRINTFN(4, "xfer %p", xfer, 0, 0, 0); 1807 1808 if (sc->sc_dying) { 1809 return USBD_IOERROR; 1810 } 1811 1812 usb_init_task(&xp->xp_async_task, 1813 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1814 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1815 DPRINTFN(4, "ends", 0, 0, 0, 0); 1816 1817 return USBD_NORMAL_COMPLETION; 1818 } 1819 1820 /* Process roothub port status/change events and notify to uhub_intr. */ 1821 static void 1822 xhci_rhpsc(struct xhci_softc * const sc, u_int ctlrport) 1823 { 1824 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1825 DPRINTFN(4, "xhci%d: port %u status change", device_unit(sc->sc_dev), 1826 ctlrport, 0, 0); 1827 1828 if (ctlrport > sc->sc_maxports) 1829 return; 1830 1831 const size_t bn = xhci_ctlrport2bus(sc, ctlrport); 1832 const size_t rhp = xhci_ctlrport2rhport(sc, ctlrport); 1833 struct usbd_xfer * const xfer = sc->sc_intrxfer[bn]; 1834 1835 DPRINTFN(4, "xhci%d: bus %d bp %u xfer %p status change", 1836 device_unit(sc->sc_dev), bn, rhp, xfer); 1837 1838 if (xfer == NULL) 1839 return; 1840 1841 uint8_t *p = xfer->ux_buf; 1842 memset(p, 0, xfer->ux_length); 1843 p[rhp / NBBY] |= 1 << (rhp % NBBY); 1844 xfer->ux_actlen = xfer->ux_length; 1845 xfer->ux_status = USBD_NORMAL_COMPLETION; 1846 usb_transfer_complete(xfer); 1847 } 1848 1849 /* Process Transfer Events */ 1850 static void 1851 xhci_event_transfer(struct xhci_softc * const sc, 1852 const struct xhci_trb * const trb) 1853 { 1854 uint64_t trb_0; 1855 uint32_t trb_2, trb_3; 1856 uint8_t trbcode; 1857 u_int slot, dci; 1858 struct xhci_slot *xs; 1859 struct xhci_ring *xr; 1860 struct xhci_xfer *xx; 1861 struct usbd_xfer *xfer; 1862 usbd_status err; 1863 1864 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1865 1866 trb_0 = le64toh(trb->trb_0); 1867 trb_2 = le32toh(trb->trb_2); 1868 trb_3 = le32toh(trb->trb_3); 1869 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1870 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1871 dci = XHCI_TRB_3_EP_GET(trb_3); 1872 xs = &sc->sc_slots[slot]; 1873 xr = &xs->xs_ep[dci].xe_tr; 1874 1875 /* sanity check */ 1876 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1877 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1878 1879 int idx = 0; 1880 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1881 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1882 DPRINTFN(0, "invalid trb_0 0x%"PRIx64, trb_0, 0, 0, 0); 1883 return; 1884 } 1885 xx = xr->xr_cookies[idx]; 1886 1887 /* clear cookie of consumed TRB */ 1888 xr->xr_cookies[idx] = NULL; 1889 1890 /* 1891 * xx is NULL if pipe is opened but xfer is not started. 1892 * It happens when stopping idle pipe. 1893 */ 1894 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1895 DPRINTFN(1, "Ignore #%u: cookie %p cc %u dci %u", 1896 idx, xx, trbcode, dci); 1897 DPRINTFN(1, " orig TRB %"PRIx64" type %u", trb_0, 1898 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1899 0, 0); 1900 return; 1901 } 1902 } else { 1903 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1904 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1905 } 1906 /* XXX this may not happen */ 1907 if (xx == NULL) { 1908 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1909 return; 1910 } 1911 xfer = &xx->xx_xfer; 1912 /* XXX this may happen when detaching */ 1913 if (xfer == NULL) { 1914 DPRINTFN(1, "xx(%p)->xx_xfer is NULL trb_0 %#"PRIx64, 1915 xx, trb_0, 0, 0); 1916 return; 1917 } 1918 DPRINTFN(14, "xfer %p", xfer, 0, 0, 0); 1919 /* XXX I dunno why this happens */ 1920 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1921 1922 if (!xfer->ux_pipe->up_repeat && 1923 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1924 DPRINTFN(1, "xfer(%p)->pipe not queued", xfer, 0, 0, 0); 1925 return; 1926 } 1927 1928 /* 4.11.5.2 Event Data TRB */ 1929 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1930 DPRINTFN(14, "transfer Event Data: 0x%016"PRIx64" 0x%08"PRIx32 1931 " %02x", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1932 if ((trb_0 & 0x3) == 0x3) { 1933 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1934 } 1935 } 1936 1937 switch (trbcode) { 1938 case XHCI_TRB_ERROR_SHORT_PKT: 1939 case XHCI_TRB_ERROR_SUCCESS: 1940 /* 1941 * A ctrl transfer can generate two events if it has a Data 1942 * stage. A short data stage can be OK and should not 1943 * complete the transfer as the status stage needs to be 1944 * performed. 1945 * 1946 * Note: Data and Status stage events point at same xfer. 1947 * ux_actlen and ux_dmabuf will be passed to 1948 * usb_transfer_complete after the Status stage event. 1949 * 1950 * It can be distingished which stage generates the event: 1951 * + by checking least 3 bits of trb_0 if ED==1. 1952 * (see xhci_device_ctrl_start). 1953 * + by checking the type of original TRB if ED==0. 1954 * 1955 * In addition, intr, bulk, and isoc transfer currently 1956 * consists of single TD, so the "skip" is not needed. 1957 * ctrl xfer uses EVENT_DATA, and others do not. 1958 * Thus driver can switch the flow by checking ED bit. 1959 */ 1960 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1961 if (xfer->ux_actlen == 0) 1962 xfer->ux_actlen = xfer->ux_length - 1963 XHCI_TRB_2_REM_GET(trb_2); 1964 if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)) 1965 == XHCI_TRB_TYPE_DATA_STAGE) { 1966 return; 1967 } 1968 } else if ((trb_0 & 0x3) == 0x3) { 1969 return; 1970 } 1971 err = USBD_NORMAL_COMPLETION; 1972 break; 1973 case XHCI_TRB_ERROR_STOPPED: 1974 case XHCI_TRB_ERROR_LENGTH: 1975 case XHCI_TRB_ERROR_STOPPED_SHORT: 1976 /* 1977 * don't complete the transfer being aborted 1978 * as abort_xfer does instead. 1979 */ 1980 if (xfer->ux_hcflags & UXFER_ABORTING) { 1981 DPRINTFN(14, "ignore aborting xfer %p", xfer, 0, 0, 0); 1982 return; 1983 } 1984 err = USBD_CANCELLED; 1985 break; 1986 case XHCI_TRB_ERROR_STALL: 1987 case XHCI_TRB_ERROR_BABBLE: 1988 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 1989 xr->is_halted = true; 1990 err = USBD_STALLED; 1991 /* 1992 * Stalled endpoints can be recoverd by issuing 1993 * command TRB TYPE_RESET_EP on xHCI instead of 1994 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1995 * on the endpoint. However, this function may be 1996 * called from softint context (e.g. from umass), 1997 * in that case driver gets KASSERT in cv_timedwait 1998 * in xhci_do_command. 1999 * To avoid this, this runs reset_endpoint and 2000 * usb_transfer_complete in usb task thread 2001 * asynchronously (and then umass issues clear 2002 * UF_ENDPOINT_HALT). 2003 */ 2004 xfer->ux_status = err; 2005 callout_stop(&xfer->ux_callout); 2006 xhci_clear_endpoint_stall_async(xfer); 2007 return; 2008 default: 2009 DPRINTFN(1, "ERR %u slot %u dci %u", trbcode, slot, dci, 0); 2010 err = USBD_IOERROR; 2011 break; 2012 } 2013 xfer->ux_status = err; 2014 2015 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 2016 if ((trb_0 & 0x3) == 0x0) { 2017 callout_stop(&xfer->ux_callout); 2018 usb_transfer_complete(xfer); 2019 } 2020 } else { 2021 callout_stop(&xfer->ux_callout); 2022 usb_transfer_complete(xfer); 2023 } 2024 } 2025 2026 /* Process Command complete events */ 2027 static void 2028 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 2029 { 2030 uint64_t trb_0; 2031 uint32_t trb_2, trb_3; 2032 2033 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2034 2035 KASSERT(mutex_owned(&sc->sc_lock)); 2036 2037 trb_0 = le64toh(trb->trb_0); 2038 trb_2 = le32toh(trb->trb_2); 2039 trb_3 = le32toh(trb->trb_3); 2040 2041 if (trb_0 == sc->sc_command_addr) { 2042 sc->sc_resultpending = false; 2043 2044 sc->sc_result_trb.trb_0 = trb_0; 2045 sc->sc_result_trb.trb_2 = trb_2; 2046 sc->sc_result_trb.trb_3 = trb_3; 2047 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2048 XHCI_TRB_ERROR_SUCCESS) { 2049 DPRINTFN(1, "command completion " 2050 "failure: 0x%016"PRIx64" 0x%08"PRIx32" " 2051 "0x%08"PRIx32, trb_0, trb_2, trb_3, 0); 2052 } 2053 cv_signal(&sc->sc_command_cv); 2054 } else { 2055 DPRINTFN(1, "spurious event: %p 0x%016"PRIx64" " 2056 "0x%08"PRIx32" 0x%08"PRIx32, trb, trb_0, 2057 trb_2, trb_3); 2058 } 2059 } 2060 2061 /* 2062 * Process events. 2063 * called from xhci_softintr 2064 */ 2065 static void 2066 xhci_handle_event(struct xhci_softc * const sc, 2067 const struct xhci_trb * const trb) 2068 { 2069 uint64_t trb_0; 2070 uint32_t trb_2, trb_3; 2071 2072 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2073 2074 trb_0 = le64toh(trb->trb_0); 2075 trb_2 = le32toh(trb->trb_2); 2076 trb_3 = le32toh(trb->trb_3); 2077 2078 DPRINTFN(14, "event: %p 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2079 trb, trb_0, trb_2, trb_3); 2080 2081 /* 2082 * 4.11.3.1, 6.4.2.1 2083 * TRB Pointer is invalid for these completion codes. 2084 */ 2085 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2086 case XHCI_TRB_ERROR_RING_UNDERRUN: 2087 case XHCI_TRB_ERROR_RING_OVERRUN: 2088 case XHCI_TRB_ERROR_VF_RING_FULL: 2089 return; 2090 default: 2091 if (trb_0 == 0) { 2092 return; 2093 } 2094 break; 2095 } 2096 2097 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2098 case XHCI_TRB_EVENT_TRANSFER: 2099 xhci_event_transfer(sc, trb); 2100 break; 2101 case XHCI_TRB_EVENT_CMD_COMPLETE: 2102 xhci_event_cmd(sc, trb); 2103 break; 2104 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2105 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2106 break; 2107 default: 2108 break; 2109 } 2110 } 2111 2112 static void 2113 xhci_softintr(void *v) 2114 { 2115 struct usbd_bus * const bus = v; 2116 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2117 struct xhci_ring * const er = &sc->sc_er; 2118 struct xhci_trb *trb; 2119 int i, j, k; 2120 2121 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2122 2123 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 2124 2125 i = er->xr_ep; 2126 j = er->xr_cs; 2127 2128 DPRINTFN(16, "er: xr_ep %d xr_cs %d", i, j, 0, 0); 2129 2130 while (1) { 2131 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2132 BUS_DMASYNC_POSTREAD); 2133 trb = &er->xr_trb[i]; 2134 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2135 2136 if (j != k) 2137 break; 2138 2139 xhci_handle_event(sc, trb); 2140 2141 i++; 2142 if (i == er->xr_ntrb) { 2143 i = 0; 2144 j ^= 1; 2145 } 2146 } 2147 2148 er->xr_ep = i; 2149 er->xr_cs = j; 2150 2151 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2152 XHCI_ERDP_LO_BUSY); 2153 2154 DPRINTFN(16, "ends", 0, 0, 0, 0); 2155 2156 return; 2157 } 2158 2159 static void 2160 xhci_poll(struct usbd_bus *bus) 2161 { 2162 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2163 2164 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2165 2166 mutex_spin_enter(&sc->sc_intr_lock); 2167 int ret = xhci_intr1(sc); 2168 if (ret) { 2169 xhci_softintr(bus); 2170 } 2171 mutex_spin_exit(&sc->sc_intr_lock); 2172 2173 return; 2174 } 2175 2176 static struct usbd_xfer * 2177 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2178 { 2179 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2180 struct usbd_xfer *xfer; 2181 2182 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2183 2184 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 2185 if (xfer != NULL) { 2186 memset(xfer, 0, sizeof(struct xhci_xfer)); 2187 #ifdef DIAGNOSTIC 2188 xfer->ux_state = XFER_BUSY; 2189 #endif 2190 } 2191 2192 return xfer; 2193 } 2194 2195 static void 2196 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2197 { 2198 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2199 2200 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2201 2202 #ifdef DIAGNOSTIC 2203 if (xfer->ux_state != XFER_BUSY) { 2204 DPRINTFN(0, "xfer=%p not busy, 0x%08x", 2205 xfer, xfer->ux_state, 0, 0); 2206 } 2207 xfer->ux_state = XFER_FREE; 2208 #endif 2209 pool_cache_put(sc->sc_xferpool, xfer); 2210 } 2211 2212 static void 2213 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2214 { 2215 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2216 2217 *lock = &sc->sc_lock; 2218 } 2219 2220 extern uint32_t usb_cookie_no; 2221 2222 /* 2223 * xHCI 4.3 2224 * Called when uhub_explore finds a new device (via usbd_new_device). 2225 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2226 * This function does: 2227 * Allocate and construct dev structure of default endpoint (ep0). 2228 * Allocate and open pipe of ep0. 2229 * Enable slot and initialize slot context. 2230 * Set Address. 2231 * Read initial device descriptor. 2232 * Determine initial MaxPacketSize (mps) by speed. 2233 * Read full device descriptor. 2234 * Register this device. 2235 * Finally state of device transitions ADDRESSED. 2236 */ 2237 static usbd_status 2238 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2239 int speed, int port, struct usbd_port *up) 2240 { 2241 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2242 struct usbd_device *dev; 2243 usbd_status err; 2244 usb_device_descriptor_t *dd; 2245 struct xhci_slot *xs; 2246 uint32_t *cp; 2247 2248 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2249 DPRINTFN(4, "port %u depth %u speed %u up %p", port, depth, speed, up); 2250 2251 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2252 dev->ud_bus = bus; 2253 dev->ud_quirks = &usbd_no_quirk; 2254 dev->ud_addr = 0; 2255 dev->ud_ddesc.bMaxPacketSize = 0; 2256 dev->ud_depth = depth; 2257 dev->ud_powersrc = up; 2258 dev->ud_myhub = up->up_parent; 2259 dev->ud_speed = speed; 2260 dev->ud_langid = USBD_NOLANG; 2261 dev->ud_cookie.cookie = ++usb_cookie_no; 2262 2263 /* Set up default endpoint handle. */ 2264 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2265 /* doesn't matter, just don't let it uninitialized */ 2266 dev->ud_ep0.ue_toggle = 0; 2267 2268 /* Set up default endpoint descriptor. */ 2269 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2270 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2271 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2272 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2273 dev->ud_ep0desc.bInterval = 0; 2274 2275 /* 4.3, 4.8.2.1 */ 2276 switch (speed) { 2277 case USB_SPEED_SUPER: 2278 case USB_SPEED_SUPER_PLUS: 2279 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2280 break; 2281 case USB_SPEED_FULL: 2282 /* XXX using 64 as initial mps of ep0 in FS */ 2283 case USB_SPEED_HIGH: 2284 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2285 break; 2286 case USB_SPEED_LOW: 2287 default: 2288 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2289 break; 2290 } 2291 2292 up->up_dev = dev; 2293 2294 /* Establish the default pipe. */ 2295 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2296 &dev->ud_pipe0); 2297 if (err) { 2298 goto bad; 2299 } 2300 2301 dd = &dev->ud_ddesc; 2302 2303 if (depth == 0 && port == 0) { 2304 KASSERT(bus->ub_devices[USB_ROOTHUB_INDEX] == NULL); 2305 bus->ub_devices[USB_ROOTHUB_INDEX] = dev; 2306 err = usbd_get_initial_ddesc(dev, dd); 2307 if (err) { 2308 DPRINTFN(1, "get_initial_ddesc %u", err, 0, 0, 0); 2309 goto bad; 2310 } 2311 2312 err = usbd_reload_device_desc(dev); 2313 if (err) { 2314 DPRINTFN(1, "reload desc %u", err, 0, 0, 0); 2315 goto bad; 2316 } 2317 } else { 2318 uint8_t slot = 0; 2319 2320 /* 4.3.2 */ 2321 err = xhci_enable_slot(sc, &slot); 2322 if (err) { 2323 DPRINTFN(1, "enable slot %u", err, 0, 0, 0); 2324 goto bad; 2325 } 2326 2327 xs = &sc->sc_slots[slot]; 2328 dev->ud_hcpriv = xs; 2329 2330 /* 4.3.3 initialize slot structure */ 2331 err = xhci_init_slot(dev, slot); 2332 if (err) { 2333 DPRINTFN(1, "init slot %u", err, 0, 0, 0); 2334 dev->ud_hcpriv = NULL; 2335 /* 2336 * We have to disable_slot here because 2337 * xs->xs_idx == 0 when xhci_init_slot fails, 2338 * in that case usbd_remove_dev won't work. 2339 */ 2340 mutex_enter(&sc->sc_lock); 2341 xhci_disable_slot(sc, slot); 2342 mutex_exit(&sc->sc_lock); 2343 goto bad; 2344 } 2345 2346 /* 4.3.4 Address Assignment */ 2347 err = xhci_set_address(dev, slot, false); 2348 if (err) { 2349 DPRINTFN(1, "set address w/o bsr %u", err, 0, 0, 0); 2350 goto bad; 2351 } 2352 2353 /* Allow device time to set new address */ 2354 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2355 2356 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2357 //hexdump("slot context", cp, sc->sc_ctxsz); 2358 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3])); 2359 DPRINTFN(4, "device address %u", addr, 0, 0, 0); 2360 /* 2361 * XXX ensure we know when the hardware does something 2362 * we can't yet cope with 2363 */ 2364 KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr); 2365 dev->ud_addr = addr; 2366 2367 KASSERTMSG(bus->ub_devices[usb_addr2dindex(dev->ud_addr)] == NULL, 2368 "addr %d already allocated", dev->ud_addr); 2369 /* 2370 * The root hub is given its own slot 2371 */ 2372 bus->ub_devices[usb_addr2dindex(dev->ud_addr)] = dev; 2373 2374 err = usbd_get_initial_ddesc(dev, dd); 2375 if (err) { 2376 DPRINTFN(1, "get_initial_ddesc %u", err, 0, 0, 0); 2377 goto bad; 2378 } 2379 2380 /* 4.8.2.1 */ 2381 if (USB_IS_SS(speed)) { 2382 if (dd->bMaxPacketSize != 9) { 2383 printf("%s: invalid mps 2^%u for SS ep0," 2384 " using 512\n", 2385 device_xname(sc->sc_dev), 2386 dd->bMaxPacketSize); 2387 dd->bMaxPacketSize = 9; 2388 } 2389 USETW(dev->ud_ep0desc.wMaxPacketSize, 2390 (1 << dd->bMaxPacketSize)); 2391 } else 2392 USETW(dev->ud_ep0desc.wMaxPacketSize, 2393 dd->bMaxPacketSize); 2394 DPRINTFN(4, "bMaxPacketSize %u", dd->bMaxPacketSize, 0, 0, 0); 2395 err = xhci_update_ep0_mps(sc, xs, 2396 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2397 if (err) { 2398 DPRINTFN(1, "update mps of ep0 %u", err, 0, 0, 0); 2399 goto bad; 2400 } 2401 2402 err = usbd_reload_device_desc(dev); 2403 if (err) { 2404 DPRINTFN(1, "reload desc %u", err, 0, 0, 0); 2405 goto bad; 2406 } 2407 } 2408 2409 DPRINTFN(1, "adding unit addr=%d, rev=%02x,", 2410 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2411 DPRINTFN(1, " class=%d, subclass=%d, protocol=%d,", 2412 dd->bDeviceClass, dd->bDeviceSubClass, 2413 dd->bDeviceProtocol, 0); 2414 DPRINTFN(1, " mps=%d, len=%d, noconf=%d, speed=%d", 2415 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2416 dev->ud_speed); 2417 2418 usbd_get_device_strings(dev); 2419 2420 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2421 2422 if (depth == 0 && port == 0) { 2423 usbd_attach_roothub(parent, dev); 2424 DPRINTFN(1, "root hub %p", dev, 0, 0, 0); 2425 return USBD_NORMAL_COMPLETION; 2426 } 2427 2428 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2429 bad: 2430 if (err != USBD_NORMAL_COMPLETION) { 2431 usbd_remove_device(dev, up); 2432 } 2433 2434 return err; 2435 } 2436 2437 static usbd_status 2438 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2439 size_t ntrb, size_t align) 2440 { 2441 usbd_status err; 2442 size_t size = ntrb * XHCI_TRB_SIZE; 2443 2444 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2445 2446 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2447 if (err) 2448 return err; 2449 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2450 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2451 xr->xr_trb = xhci_ring_trbv(xr, 0); 2452 xr->xr_ntrb = ntrb; 2453 xr->is_halted = false; 2454 xhci_host_dequeue(xr); 2455 2456 return USBD_NORMAL_COMPLETION; 2457 } 2458 2459 static void 2460 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2461 { 2462 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2463 mutex_destroy(&xr->xr_lock); 2464 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2465 } 2466 2467 static void 2468 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2469 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2470 { 2471 size_t i; 2472 u_int ri; 2473 u_int cs; 2474 uint64_t parameter; 2475 uint32_t status; 2476 uint32_t control; 2477 2478 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2479 2480 KASSERTMSG(ntrbs <= XHCI_XFER_NTRB, "ntrbs %zu", ntrbs); 2481 for (i = 0; i < ntrbs; i++) { 2482 DPRINTFN(12, "xr %p trbs %p num %zu", xr, trbs, i, 0); 2483 DPRINTFN(12, " %016"PRIx64" %08"PRIx32" %08"PRIx32, 2484 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2485 KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2486 XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3); 2487 } 2488 2489 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2490 2491 ri = xr->xr_ep; 2492 cs = xr->xr_cs; 2493 2494 /* 2495 * Although the xhci hardware can do scatter/gather dma from 2496 * arbitrary sized buffers, there is a non-obvious restriction 2497 * that a LINK trb is only allowed at the end of a burst of 2498 * transfers - which might be 16kB. 2499 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2500 * The simple solution is not to allow a LINK trb in the middle 2501 * of anything - as here. 2502 * XXX: (dsl) There are xhci controllers out there (eg some made by 2503 * ASMedia) that seem to lock up if they process a LINK trb but 2504 * cannot process the linked-to trb yet. 2505 * The code should write the 'cycle' bit on the link trb AFTER 2506 * adding the other trb. 2507 */ 2508 u_int firstep = xr->xr_ep; 2509 u_int firstcs = xr->xr_cs; 2510 2511 for (i = 0; i < ntrbs; ) { 2512 u_int oldri = ri; 2513 u_int oldcs = cs; 2514 2515 if (ri >= (xr->xr_ntrb - 1)) { 2516 /* Put Link TD at the end of ring */ 2517 parameter = xhci_ring_trbp(xr, 0); 2518 status = 0; 2519 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2520 XHCI_TRB_3_TC_BIT; 2521 xr->xr_cookies[ri] = NULL; 2522 xr->xr_ep = 0; 2523 xr->xr_cs ^= 1; 2524 ri = xr->xr_ep; 2525 cs = xr->xr_cs; 2526 } else { 2527 parameter = trbs[i].trb_0; 2528 status = trbs[i].trb_2; 2529 control = trbs[i].trb_3; 2530 2531 xr->xr_cookies[ri] = cookie; 2532 ri++; 2533 i++; 2534 } 2535 /* 2536 * If this is a first TRB, mark it invalid to prevent 2537 * xHC from running it immediately. 2538 */ 2539 if (oldri == firstep) { 2540 if (oldcs) { 2541 control &= ~XHCI_TRB_3_CYCLE_BIT; 2542 } else { 2543 control |= XHCI_TRB_3_CYCLE_BIT; 2544 } 2545 } else { 2546 if (oldcs) { 2547 control |= XHCI_TRB_3_CYCLE_BIT; 2548 } else { 2549 control &= ~XHCI_TRB_3_CYCLE_BIT; 2550 } 2551 } 2552 xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control); 2553 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri, 2554 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2555 } 2556 2557 /* Now invert cycle bit of first TRB */ 2558 if (firstcs) { 2559 xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 2560 } else { 2561 xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 2562 } 2563 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep, 2564 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2565 2566 xr->xr_ep = ri; 2567 xr->xr_cs = cs; 2568 2569 DPRINTFN(12, "%p xr_ep 0x%x xr_cs %u", xr, xr->xr_ep, xr->xr_cs, 0); 2570 } 2571 2572 /* 2573 * Stop execution commands, purge all commands on command ring, and 2574 * rewind dequeue pointer. 2575 */ 2576 static void 2577 xhci_abort_command(struct xhci_softc *sc) 2578 { 2579 struct xhci_ring * const cr = &sc->sc_cr; 2580 uint64_t crcr; 2581 int i; 2582 2583 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2584 DPRINTFN(14, "command %#"PRIx64" timeout, aborting", 2585 sc->sc_command_addr, 0, 0, 0); 2586 2587 mutex_enter(&cr->xr_lock); 2588 2589 /* 4.6.1.2 Aborting a Command */ 2590 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2591 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2592 2593 for (i = 0; i < 500; i++) { 2594 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2595 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2596 break; 2597 usb_delay_ms(&sc->sc_bus, 1); 2598 } 2599 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2600 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2601 /* reset HC here? */ 2602 } 2603 2604 /* reset command ring dequeue pointer */ 2605 cr->xr_ep = 0; 2606 cr->xr_cs = 1; 2607 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2608 2609 mutex_exit(&cr->xr_lock); 2610 } 2611 2612 /* 2613 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2614 * Command completion is notified by cv_signal from xhci_event_cmd() 2615 * (called from xhci_softint), or timed-out. 2616 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2617 * then do_command examines it. 2618 */ 2619 static usbd_status 2620 xhci_do_command_locked(struct xhci_softc * const sc, 2621 struct xhci_trb * const trb, int timeout) 2622 { 2623 struct xhci_ring * const cr = &sc->sc_cr; 2624 usbd_status err; 2625 2626 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2627 DPRINTFN(12, "input: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32, 2628 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2629 2630 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2631 KASSERT(mutex_owned(&sc->sc_lock)); 2632 2633 while (sc->sc_command_addr != 0) 2634 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 2635 2636 /* 2637 * If enqueue pointer points at last of ring, it's Link TRB, 2638 * command TRB will be stored in 0th TRB. 2639 */ 2640 if (cr->xr_ep == cr->xr_ntrb - 1) 2641 sc->sc_command_addr = xhci_ring_trbp(cr, 0); 2642 else 2643 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2644 2645 sc->sc_resultpending = true; 2646 2647 mutex_enter(&cr->xr_lock); 2648 xhci_ring_put(sc, cr, NULL, trb, 1); 2649 mutex_exit(&cr->xr_lock); 2650 2651 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2652 2653 while (sc->sc_resultpending) { 2654 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2655 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2656 xhci_abort_command(sc); 2657 err = USBD_TIMEOUT; 2658 goto timedout; 2659 } 2660 } 2661 2662 trb->trb_0 = sc->sc_result_trb.trb_0; 2663 trb->trb_2 = sc->sc_result_trb.trb_2; 2664 trb->trb_3 = sc->sc_result_trb.trb_3; 2665 2666 DPRINTFN(12, "output: 0x%016"PRIx64" 0x%08"PRIx32" 0x%08"PRIx32"", 2667 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2668 2669 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2670 case XHCI_TRB_ERROR_SUCCESS: 2671 err = USBD_NORMAL_COMPLETION; 2672 break; 2673 default: 2674 case 192 ... 223: 2675 err = USBD_IOERROR; 2676 break; 2677 case 224 ... 255: 2678 err = USBD_NORMAL_COMPLETION; 2679 break; 2680 } 2681 2682 timedout: 2683 sc->sc_resultpending = false; 2684 sc->sc_command_addr = 0; 2685 cv_broadcast(&sc->sc_cmdbusy_cv); 2686 2687 return err; 2688 } 2689 2690 static usbd_status 2691 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2692 int timeout) 2693 { 2694 2695 mutex_enter(&sc->sc_lock); 2696 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2697 mutex_exit(&sc->sc_lock); 2698 2699 return ret; 2700 } 2701 2702 static usbd_status 2703 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2704 { 2705 struct xhci_trb trb; 2706 usbd_status err; 2707 2708 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2709 2710 trb.trb_0 = 0; 2711 trb.trb_2 = 0; 2712 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2713 2714 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2715 if (err != USBD_NORMAL_COMPLETION) { 2716 return err; 2717 } 2718 2719 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2720 2721 return err; 2722 } 2723 2724 /* 2725 * xHCI 4.6.4 2726 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2727 * All endpoints in the slot should be stopped. 2728 * Should be called with sc_lock held. 2729 */ 2730 static usbd_status 2731 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2732 { 2733 struct xhci_trb trb; 2734 struct xhci_slot *xs; 2735 usbd_status err; 2736 2737 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2738 2739 if (sc->sc_dying) 2740 return USBD_IOERROR; 2741 2742 trb.trb_0 = 0; 2743 trb.trb_2 = 0; 2744 trb.trb_3 = htole32( 2745 XHCI_TRB_3_SLOT_SET(slot) | 2746 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2747 2748 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2749 2750 if (!err) { 2751 xs = &sc->sc_slots[slot]; 2752 if (xs->xs_idx != 0) { 2753 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2754 xhci_set_dcba(sc, 0, slot); 2755 memset(xs, 0, sizeof(*xs)); 2756 } 2757 } 2758 2759 return err; 2760 } 2761 2762 /* 2763 * Set address of device and transition slot state from ENABLED to ADDRESSED 2764 * if Block Setaddress Request (BSR) is false. 2765 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2766 * see xHCI 1.1 4.5.3, 3.3.4 2767 * Should be called without sc_lock held. 2768 */ 2769 static usbd_status 2770 xhci_address_device(struct xhci_softc * const sc, 2771 uint64_t icp, uint8_t slot_id, bool bsr) 2772 { 2773 struct xhci_trb trb; 2774 usbd_status err; 2775 2776 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2777 2778 trb.trb_0 = icp; 2779 trb.trb_2 = 0; 2780 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2781 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2782 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2783 2784 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2785 2786 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2787 err = USBD_NO_ADDR; 2788 2789 return err; 2790 } 2791 2792 static usbd_status 2793 xhci_update_ep0_mps(struct xhci_softc * const sc, 2794 struct xhci_slot * const xs, u_int mps) 2795 { 2796 struct xhci_trb trb; 2797 usbd_status err; 2798 uint32_t * cp; 2799 2800 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2801 DPRINTFN(4, "slot %u mps %u", xs->xs_idx, mps, 0, 0); 2802 2803 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2804 cp[0] = htole32(0); 2805 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2806 2807 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2808 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2809 2810 /* sync input contexts before they are read from memory */ 2811 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2812 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2813 sc->sc_ctxsz * 4); 2814 2815 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2816 trb.trb_2 = 0; 2817 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2818 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2819 2820 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2821 return err; 2822 } 2823 2824 static void 2825 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2826 { 2827 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2828 2829 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2830 DPRINTFN(4, "dcbaa %p dc %016"PRIx64" slot %d", 2831 &dcbaa[si], dcba, si, 0); 2832 2833 dcbaa[si] = htole64(dcba); 2834 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2835 BUS_DMASYNC_PREWRITE); 2836 } 2837 2838 /* 2839 * Allocate device and input context DMA buffer, and 2840 * TRB DMA buffer for each endpoint. 2841 */ 2842 static usbd_status 2843 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2844 { 2845 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2846 struct xhci_slot *xs; 2847 usbd_status err; 2848 u_int dci; 2849 2850 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2851 DPRINTFN(4, "slot %u", slot, 0, 0, 0); 2852 2853 xs = &sc->sc_slots[slot]; 2854 2855 /* allocate contexts */ 2856 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2857 &xs->xs_dc_dma); 2858 if (err) 2859 return err; 2860 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2861 2862 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2863 &xs->xs_ic_dma); 2864 if (err) 2865 goto bad1; 2866 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2867 2868 for (dci = 0; dci < 32; dci++) { 2869 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2870 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2871 if (dci == XHCI_DCI_SLOT) 2872 continue; 2873 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2874 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2875 if (err) { 2876 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2877 goto bad2; 2878 } 2879 } 2880 2881 bad2: 2882 if (err == USBD_NORMAL_COMPLETION) { 2883 xs->xs_idx = slot; 2884 } else { 2885 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2886 } 2887 2888 return err; 2889 2890 bad1: 2891 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2892 xs->xs_idx = 0; 2893 return err; 2894 } 2895 2896 static void 2897 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2898 int end_dci) 2899 { 2900 u_int dci; 2901 2902 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2903 DPRINTFN(4, "slot %u start %u end %u", xs->xs_idx, start_dci, end_dci, 2904 0); 2905 2906 for (dci = start_dci; dci < end_dci; dci++) { 2907 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2908 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2909 } 2910 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2911 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2912 xs->xs_idx = 0; 2913 } 2914 2915 /* 2916 * Setup slot context, set Device Context Base Address, and issue 2917 * Set Address Device command. 2918 */ 2919 static usbd_status 2920 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 2921 { 2922 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2923 struct xhci_slot *xs; 2924 usbd_status err; 2925 2926 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2927 DPRINTFN(4, "slot %u bsr %u", slot, bsr, 0, 0); 2928 2929 xs = &sc->sc_slots[slot]; 2930 2931 xhci_setup_ctx(dev->ud_pipe0); 2932 2933 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2934 sc->sc_ctxsz * 3); 2935 2936 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2937 2938 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 2939 2940 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2941 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2942 sc->sc_ctxsz * 2); 2943 2944 return err; 2945 } 2946 2947 /* 2948 * 4.8.2, 6.2.3.2 2949 * construct slot/endpoint context parameters and do syncmem 2950 */ 2951 static void 2952 xhci_setup_ctx(struct usbd_pipe *pipe) 2953 { 2954 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2955 struct usbd_device *dev = pipe->up_dev; 2956 struct xhci_slot * const xs = dev->ud_hcpriv; 2957 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2958 const u_int dci = xhci_ep_get_dci(ed); 2959 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2960 uint32_t *cp; 2961 uint16_t mps = UGETW(ed->wMaxPacketSize); 2962 uint8_t speed = dev->ud_speed; 2963 uint8_t ival = ed->bInterval; 2964 2965 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2966 DPRINTFN(4, "pipe %p: slot %u dci %u speed %u", pipe, xs->xs_idx, dci, 2967 speed); 2968 2969 /* set up initial input control context */ 2970 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2971 cp[0] = htole32(0); 2972 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 2973 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2974 cp[7] = htole32(0); 2975 2976 /* set up input slot context */ 2977 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2978 cp[0] = 2979 XHCI_SCTX_0_CTX_NUM_SET(dci) | 2980 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 2981 cp[1] = 0; 2982 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2983 cp[3] = 0; 2984 xhci_setup_route(pipe, cp); 2985 xhci_setup_tthub(pipe, cp); 2986 2987 cp[0] = htole32(cp[0]); 2988 cp[1] = htole32(cp[1]); 2989 cp[2] = htole32(cp[2]); 2990 cp[3] = htole32(cp[3]); 2991 2992 /* set up input endpoint context */ 2993 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 2994 cp[0] = 2995 XHCI_EPCTX_0_EPSTATE_SET(0) | 2996 XHCI_EPCTX_0_MULT_SET(0) | 2997 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2998 XHCI_EPCTX_0_LSA_SET(0) | 2999 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 3000 cp[1] = 3001 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 3002 XHCI_EPCTX_1_HID_SET(0) | 3003 XHCI_EPCTX_1_MAXB_SET(0); 3004 3005 if (xfertype != UE_ISOCHRONOUS) 3006 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 3007 3008 if (xfertype == UE_CONTROL) 3009 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 3010 else if (USB_IS_SS(speed)) 3011 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 3012 else 3013 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 3014 3015 xhci_setup_maxburst(pipe, cp); 3016 3017 switch (xfertype) { 3018 case UE_CONTROL: 3019 break; 3020 case UE_BULK: 3021 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 3022 break; 3023 case UE_INTERRUPT: 3024 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3025 ival = pipe->up_interval; 3026 3027 ival = xhci_bival2ival(ival, speed); 3028 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3029 break; 3030 case UE_ISOCHRONOUS: 3031 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3032 ival = pipe->up_interval; 3033 3034 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 3035 if (speed == USB_SPEED_FULL) 3036 ival += 3; /* 1ms -> 125us */ 3037 ival--; 3038 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3039 break; 3040 default: 3041 break; 3042 } 3043 DPRINTFN(4, "setting ival %u MaxBurst %#x", 3044 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 3045 3046 /* rewind TR dequeue pointer in xHC */ 3047 /* can't use xhci_ep_get_dci() yet? */ 3048 *(uint64_t *)(&cp[2]) = htole64( 3049 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 3050 XHCI_EPCTX_2_DCS_SET(1)); 3051 3052 cp[0] = htole32(cp[0]); 3053 cp[1] = htole32(cp[1]); 3054 cp[4] = htole32(cp[4]); 3055 3056 /* rewind TR dequeue pointer in driver */ 3057 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 3058 mutex_enter(&xr->xr_lock); 3059 xhci_host_dequeue(xr); 3060 mutex_exit(&xr->xr_lock); 3061 3062 /* sync input contexts before they are read from memory */ 3063 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3064 } 3065 3066 /* 3067 * Setup route string and roothub port of given device for slot context 3068 */ 3069 static void 3070 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 3071 { 3072 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3073 struct usbd_device *dev = pipe->up_dev; 3074 struct usbd_port *up = dev->ud_powersrc; 3075 struct usbd_device *hub; 3076 struct usbd_device *adev; 3077 uint8_t rhport = 0; 3078 uint32_t route = 0; 3079 3080 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3081 3082 /* Locate root hub port and Determine route string */ 3083 /* 4.3.3 route string does not include roothub port */ 3084 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 3085 uint32_t dep; 3086 3087 DPRINTFN(4, "hub %p depth %d upport %p upportno %d", 3088 hub, hub->ud_depth, hub->ud_powersrc, 3089 hub->ud_powersrc ? hub->ud_powersrc->up_portno : -1); 3090 3091 if (hub->ud_powersrc == NULL) 3092 break; 3093 dep = hub->ud_depth; 3094 if (dep == 0) 3095 break; 3096 rhport = hub->ud_powersrc->up_portno; 3097 if (dep > USB_HUB_MAX_DEPTH) 3098 continue; 3099 3100 route |= 3101 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 3102 << ((dep - 1) * 4); 3103 } 3104 route = route >> 4; 3105 size_t bn = hub == sc->sc_bus.ub_roothub ? 0 : 1; 3106 3107 /* Locate port on upstream high speed hub */ 3108 for (adev = dev, hub = up->up_parent; 3109 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 3110 adev = hub, hub = hub->ud_myhub) 3111 ; 3112 if (hub) { 3113 int p; 3114 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 3115 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 3116 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 3117 goto found; 3118 } 3119 } 3120 panic("%s: cannot find HS port", __func__); 3121 found: 3122 DPRINTFN(4, "high speed port %d", p, 0, 0, 0); 3123 } else { 3124 dev->ud_myhsport = NULL; 3125 } 3126 3127 const size_t ctlrport = xhci_rhport2ctlrport(sc, bn, rhport); 3128 3129 DPRINTFN(4, "rhport %u ctlrport %u Route %05x hub %p", rhport, 3130 ctlrport, route, hub); 3131 3132 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 3133 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(ctlrport); 3134 } 3135 3136 /* 3137 * Setup whether device is hub, whether device uses MTT, and 3138 * TT informations if it uses MTT. 3139 */ 3140 static void 3141 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 3142 { 3143 struct usbd_device *dev = pipe->up_dev; 3144 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 3145 uint32_t speed = dev->ud_speed; 3146 uint8_t tthubslot, ttportnum; 3147 bool ishub; 3148 bool usemtt; 3149 3150 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3151 3152 /* 3153 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 3154 * tthubslot: 3155 * This is the slot ID of parent HS hub 3156 * if LS/FS device is connected && connected through HS hub. 3157 * This is 0 if device is not LS/FS device || 3158 * parent hub is not HS hub || 3159 * attached to root hub. 3160 * ttportnum: 3161 * This is the downstream facing port of parent HS hub 3162 * if LS/FS device is connected. 3163 * This is 0 if device is not LS/FS device || 3164 * parent hub is not HS hub || 3165 * attached to root hub. 3166 */ 3167 if (dev->ud_myhsport != NULL && 3168 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3169 (dev->ud_myhub != NULL && 3170 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3171 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 3172 ttportnum = dev->ud_myhsport->up_portno; 3173 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 3174 } else { 3175 ttportnum = 0; 3176 tthubslot = 0; 3177 } 3178 DPRINTFN(4, "myhsport %p ttportnum=%d tthubslot=%d", 3179 dev->ud_myhsport, ttportnum, tthubslot, 0); 3180 3181 /* ishub is valid after reading UDESC_DEVICE */ 3182 ishub = (dd->bDeviceClass == UDCLASS_HUB); 3183 3184 /* dev->ud_hub is valid after reading UDESC_HUB */ 3185 if (ishub && dev->ud_hub) { 3186 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 3187 uint8_t ttt = 3188 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 3189 3190 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 3191 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 3192 DPRINTFN(4, "nports=%d ttt=%d", hd->bNbrPorts, ttt, 0, 0); 3193 } 3194 3195 #define IS_TTHUB(dd) \ 3196 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 3197 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 3198 3199 /* 3200 * MTT flag is set if 3201 * 1. this is HS hub && MTT is enabled 3202 * or 3203 * 2. this is not hub && this is LS or FS device && 3204 * MTT of parent HS hub (and its parent, too) is enabled 3205 */ 3206 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 3207 usemtt = true; 3208 else if (!ishub && 3209 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 3210 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3211 (dev->ud_myhub != NULL && 3212 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3213 dev->ud_myhsport != NULL && 3214 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 3215 usemtt = true; 3216 else 3217 usemtt = false; 3218 DPRINTFN(4, "class %u proto %u ishub %d usemtt %d", 3219 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 3220 3221 #undef IS_TTHUB 3222 3223 cp[0] |= 3224 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 3225 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 3226 cp[2] |= 3227 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 3228 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 3229 } 3230 3231 /* set up params for periodic endpoint */ 3232 static void 3233 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 3234 { 3235 struct usbd_device *dev = pipe->up_dev; 3236 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3237 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3238 usbd_desc_iter_t iter; 3239 const usb_cdc_descriptor_t *cdcd; 3240 uint32_t maxb = 0; 3241 uint16_t mps = UGETW(ed->wMaxPacketSize); 3242 uint8_t speed = dev->ud_speed; 3243 uint8_t ep; 3244 3245 /* config desc is NULL when opening ep0 */ 3246 if (dev == NULL || dev->ud_cdesc == NULL) 3247 goto no_cdcd; 3248 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 3249 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 3250 if (cdcd == NULL) 3251 goto no_cdcd; 3252 usb_desc_iter_init(dev, &iter); 3253 iter.cur = (const void *)cdcd; 3254 3255 /* find endpoint_ss_comp desc for ep of this pipe */ 3256 for (ep = 0;;) { 3257 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 3258 if (cdcd == NULL) 3259 break; 3260 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 3261 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 3262 bEndpointAddress; 3263 if (UE_GET_ADDR(ep) == 3264 UE_GET_ADDR(ed->bEndpointAddress)) { 3265 cdcd = (const usb_cdc_descriptor_t *) 3266 usb_desc_iter_next(&iter); 3267 break; 3268 } 3269 ep = 0; 3270 } 3271 } 3272 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 3273 const usb_endpoint_ss_comp_descriptor_t * esscd = 3274 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3275 maxb = esscd->bMaxBurst; 3276 } 3277 3278 no_cdcd: 3279 /* 6.2.3.4, 4.8.2.4 */ 3280 if (USB_IS_SS(speed)) { 3281 /* USB 3.1 9.6.6 */ 3282 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3283 /* USB 3.1 9.6.7 */ 3284 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3285 #ifdef notyet 3286 if (xfertype == UE_ISOCHRONOUS) { 3287 } 3288 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3289 /* use ESIT */ 3290 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3291 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3292 3293 /* XXX if LEC = 1, set ESIT instead */ 3294 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3295 } else { 3296 /* use ival */ 3297 } 3298 #endif 3299 } else { 3300 /* USB 2.0 9.6.6 */ 3301 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3302 3303 /* 6.2.3.4 */ 3304 if (speed == USB_SPEED_HIGH && 3305 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3306 maxb = UE_GET_TRANS(mps); 3307 } else { 3308 /* LS/FS or HS CTRL or HS BULK */ 3309 maxb = 0; 3310 } 3311 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3312 } 3313 } 3314 3315 /* 3316 * Convert endpoint bInterval value to endpoint context interval value 3317 * for Interrupt pipe. 3318 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3319 */ 3320 static uint32_t 3321 xhci_bival2ival(uint32_t ival, uint32_t speed) 3322 { 3323 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3324 int i; 3325 3326 /* 3327 * round ival down to "the nearest base 2 multiple of 3328 * bInterval * 8". 3329 * bInterval is at most 255 as its type is uByte. 3330 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3331 */ 3332 for (i = 10; i > 0; i--) { 3333 if ((ival * 8) >= (1 << i)) 3334 break; 3335 } 3336 ival = i; 3337 } else { 3338 /* Interval = bInterval-1 for SS/HS */ 3339 ival--; 3340 } 3341 3342 return ival; 3343 } 3344 3345 /* ----- */ 3346 3347 static void 3348 xhci_noop(struct usbd_pipe *pipe) 3349 { 3350 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3351 } 3352 3353 /* 3354 * Process root hub request. 3355 */ 3356 static int 3357 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3358 void *buf, int buflen) 3359 { 3360 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3361 usb_port_status_t ps; 3362 int l, totlen = 0; 3363 uint16_t len, value, index; 3364 int port, i; 3365 uint32_t v; 3366 3367 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3368 3369 if (sc->sc_dying) 3370 return -1; 3371 3372 size_t bn = bus == &sc->sc_bus ? 0 : 1; 3373 3374 len = UGETW(req->wLength); 3375 value = UGETW(req->wValue); 3376 index = UGETW(req->wIndex); 3377 3378 DPRINTFN(12, "rhreq: %04x %04x %04x %04x", 3379 req->bmRequestType | (req->bRequest << 8), value, index, len); 3380 3381 #define C(x,y) ((x) | ((y) << 8)) 3382 switch (C(req->bRequest, req->bmRequestType)) { 3383 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3384 DPRINTFN(8, "getdesc: wValue=0x%04x", value, 0, 0, 0); 3385 if (len == 0) 3386 break; 3387 switch (value) { 3388 case C(0, UDESC_DEVICE): { 3389 usb_device_descriptor_t devd; 3390 totlen = min(buflen, sizeof(devd)); 3391 memcpy(&devd, buf, totlen); 3392 USETW(devd.idVendor, sc->sc_id_vendor); 3393 memcpy(buf, &devd, totlen); 3394 break; 3395 } 3396 #define sd ((usb_string_descriptor_t *)buf) 3397 case C(1, UDESC_STRING): 3398 /* Vendor */ 3399 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3400 break; 3401 case C(2, UDESC_STRING): 3402 /* Product */ 3403 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3404 break; 3405 #undef sd 3406 default: 3407 /* default from usbroothub */ 3408 return buflen; 3409 } 3410 break; 3411 3412 /* Hub requests */ 3413 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3414 break; 3415 /* Clear Port Feature request */ 3416 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): { 3417 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3418 3419 DPRINTFN(4, "UR_CLEAR_PORT_FEAT bp=%d feat=%d bus=%d cp=%d", 3420 index, value, bn, cp); 3421 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3422 return -1; 3423 } 3424 port = XHCI_PORTSC(cp); 3425 v = xhci_op_read_4(sc, port); 3426 DPRINTFN(4, "portsc=0x%08x", v, 0, 0, 0); 3427 v &= ~XHCI_PS_CLEAR; 3428 switch (value) { 3429 case UHF_PORT_ENABLE: 3430 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3431 break; 3432 case UHF_PORT_SUSPEND: 3433 return -1; 3434 case UHF_PORT_POWER: 3435 break; 3436 case UHF_PORT_TEST: 3437 case UHF_PORT_INDICATOR: 3438 return -1; 3439 case UHF_C_PORT_CONNECTION: 3440 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3441 break; 3442 case UHF_C_PORT_ENABLE: 3443 case UHF_C_PORT_SUSPEND: 3444 case UHF_C_PORT_OVER_CURRENT: 3445 return -1; 3446 case UHF_C_BH_PORT_RESET: 3447 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3448 break; 3449 case UHF_C_PORT_RESET: 3450 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3451 break; 3452 case UHF_C_PORT_LINK_STATE: 3453 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3454 break; 3455 case UHF_C_PORT_CONFIG_ERROR: 3456 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3457 break; 3458 default: 3459 return -1; 3460 } 3461 break; 3462 } 3463 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3464 if (len == 0) 3465 break; 3466 if ((value & 0xff) != 0) { 3467 return -1; 3468 } 3469 usb_hub_descriptor_t hubd; 3470 3471 totlen = min(buflen, sizeof(hubd)); 3472 memcpy(&hubd, buf, totlen); 3473 hubd.bNbrPorts = sc->sc_rhportcount[bn]; 3474 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3475 hubd.bPwrOn2PwrGood = 200; 3476 for (i = 0, l = sc->sc_rhportcount[bn]; l > 0; i++, l -= 8) { 3477 /* XXX can't find out? */ 3478 hubd.DeviceRemovable[i++] = 0; 3479 } 3480 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3481 totlen = min(totlen, hubd.bDescLength); 3482 memcpy(buf, &hubd, totlen); 3483 break; 3484 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3485 if (len != 4) { 3486 return -1; 3487 } 3488 memset(buf, 0, len); /* ? XXX */ 3489 totlen = len; 3490 break; 3491 /* Get Port Status request */ 3492 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): { 3493 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3494 3495 DPRINTFN(8, "get port status bn=%d i=%d cp=%zu", bn, index, cp, 3496 0); 3497 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3498 return -1; 3499 } 3500 if (len != 4) { 3501 return -1; 3502 } 3503 v = xhci_op_read_4(sc, XHCI_PORTSC(cp)); 3504 DPRINTFN(4, "getrhportsc %d %08x", cp, v, 0, 0); 3505 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3506 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3507 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3508 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3509 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3510 if (v & XHCI_PS_PR) i |= UPS_RESET; 3511 if (v & XHCI_PS_PP) { 3512 if (i & UPS_OTHER_SPEED) 3513 i |= UPS_PORT_POWER_SS; 3514 else 3515 i |= UPS_PORT_POWER; 3516 } 3517 if (i & UPS_OTHER_SPEED) 3518 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3519 if (sc->sc_vendor_port_status) 3520 i = sc->sc_vendor_port_status(sc, v, i); 3521 USETW(ps.wPortStatus, i); 3522 i = 0; 3523 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3524 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3525 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3526 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3527 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3528 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3529 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3530 USETW(ps.wPortChange, i); 3531 totlen = min(len, sizeof(ps)); 3532 memcpy(buf, &ps, totlen); 3533 break; 3534 } 3535 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3536 return -1; 3537 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3538 break; 3539 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3540 break; 3541 /* Set Port Feature request */ 3542 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3543 int optval = (index >> 8) & 0xff; 3544 index &= 0xff; 3545 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3546 return -1; 3547 } 3548 3549 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3550 3551 port = XHCI_PORTSC(cp); 3552 v = xhci_op_read_4(sc, port); 3553 DPRINTFN(4, "index %d cp %d portsc=0x%08x", index, cp, v, 0); 3554 v &= ~XHCI_PS_CLEAR; 3555 switch (value) { 3556 case UHF_PORT_ENABLE: 3557 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3558 break; 3559 case UHF_PORT_SUSPEND: 3560 /* XXX suspend */ 3561 break; 3562 case UHF_PORT_RESET: 3563 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3564 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3565 /* Wait for reset to complete. */ 3566 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3567 if (sc->sc_dying) { 3568 return -1; 3569 } 3570 v = xhci_op_read_4(sc, port); 3571 if (v & XHCI_PS_PR) { 3572 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3573 usb_delay_ms(&sc->sc_bus, 10); 3574 /* XXX */ 3575 } 3576 break; 3577 case UHF_PORT_POWER: 3578 /* XXX power control */ 3579 break; 3580 /* XXX more */ 3581 case UHF_C_PORT_RESET: 3582 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3583 break; 3584 case UHF_PORT_U1_TIMEOUT: 3585 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3586 return -1; 3587 } 3588 port = XHCI_PORTPMSC(cp); 3589 v = xhci_op_read_4(sc, port); 3590 DPRINTFN(4, "index %d cp %d portpmsc=0x%08x", index, cp, v, 0); 3591 v &= ~XHCI_PM3_U1TO_SET(0xff); 3592 v |= XHCI_PM3_U1TO_SET(optval); 3593 xhci_op_write_4(sc, port, v); 3594 break; 3595 case UHF_PORT_U2_TIMEOUT: 3596 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3597 return -1; 3598 } 3599 port = XHCI_PORTPMSC(cp); 3600 v = xhci_op_read_4(sc, port); 3601 DPRINTFN(4, "index %d cp %d portpmsc=0x%08x", index, cp, v, 0); 3602 v &= ~XHCI_PM3_U2TO_SET(0xff); 3603 v |= XHCI_PM3_U2TO_SET(optval); 3604 xhci_op_write_4(sc, port, v); 3605 break; 3606 default: 3607 return -1; 3608 } 3609 } 3610 break; 3611 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3612 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3613 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3614 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3615 break; 3616 default: 3617 /* default from usbroothub */ 3618 return buflen; 3619 } 3620 3621 return totlen; 3622 } 3623 3624 /* root hub interrupt */ 3625 3626 static usbd_status 3627 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3628 { 3629 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3630 usbd_status err; 3631 3632 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3633 3634 /* Insert last in queue. */ 3635 mutex_enter(&sc->sc_lock); 3636 err = usb_insert_transfer(xfer); 3637 mutex_exit(&sc->sc_lock); 3638 if (err) 3639 return err; 3640 3641 /* Pipe isn't running, start first */ 3642 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3643 } 3644 3645 /* Wait for roothub port status/change */ 3646 static usbd_status 3647 xhci_root_intr_start(struct usbd_xfer *xfer) 3648 { 3649 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3650 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3651 3652 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3653 3654 if (sc->sc_dying) 3655 return USBD_IOERROR; 3656 3657 mutex_enter(&sc->sc_lock); 3658 sc->sc_intrxfer[bn] = xfer; 3659 mutex_exit(&sc->sc_lock); 3660 3661 return USBD_IN_PROGRESS; 3662 } 3663 3664 static void 3665 xhci_root_intr_abort(struct usbd_xfer *xfer) 3666 { 3667 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3668 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3669 3670 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3671 3672 KASSERT(mutex_owned(&sc->sc_lock)); 3673 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3674 3675 sc->sc_intrxfer[bn] = NULL; 3676 3677 xfer->ux_status = USBD_CANCELLED; 3678 usb_transfer_complete(xfer); 3679 } 3680 3681 static void 3682 xhci_root_intr_close(struct usbd_pipe *pipe) 3683 { 3684 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3685 const struct usbd_xfer *xfer = pipe->up_intrxfer; 3686 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3687 3688 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3689 3690 KASSERT(mutex_owned(&sc->sc_lock)); 3691 3692 sc->sc_intrxfer[bn] = NULL; 3693 } 3694 3695 static void 3696 xhci_root_intr_done(struct usbd_xfer *xfer) 3697 { 3698 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3699 3700 } 3701 3702 /* -------------- */ 3703 /* device control */ 3704 3705 static usbd_status 3706 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3707 { 3708 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3709 usbd_status err; 3710 3711 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3712 3713 /* Insert last in queue. */ 3714 mutex_enter(&sc->sc_lock); 3715 err = usb_insert_transfer(xfer); 3716 mutex_exit(&sc->sc_lock); 3717 if (err) 3718 return err; 3719 3720 /* Pipe isn't running, start first */ 3721 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3722 } 3723 3724 static usbd_status 3725 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3726 { 3727 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3728 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3729 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3730 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3731 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3732 usb_device_request_t * const req = &xfer->ux_request; 3733 const int isread = usbd_xfer_isread(xfer); 3734 const uint32_t len = UGETW(req->wLength); 3735 usb_dma_t * const dma = &xfer->ux_dmabuf; 3736 uint64_t parameter; 3737 uint32_t status; 3738 uint32_t control; 3739 u_int i; 3740 3741 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3742 DPRINTFN(12, "req: %04x %04x %04x %04x", 3743 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3744 UGETW(req->wIndex), UGETW(req->wLength)); 3745 3746 /* we rely on the bottom bits for extra info */ 3747 KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx", 3748 (uintptr_t) xfer); 3749 3750 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3751 3752 i = 0; 3753 3754 /* setup phase */ 3755 memcpy(¶meter, req, sizeof(parameter)); 3756 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3757 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3758 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3759 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3760 XHCI_TRB_3_IDT_BIT; 3761 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3762 3763 if (len != 0) { 3764 /* data phase */ 3765 parameter = DMAADDR(dma, 0); 3766 KASSERTMSG(len <= 0x10000, "len %d", len); 3767 status = XHCI_TRB_2_IRQ_SET(0) | 3768 XHCI_TRB_2_TDSZ_SET(1) | 3769 XHCI_TRB_2_BYTES_SET(len); 3770 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3771 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3772 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3773 XHCI_TRB_3_IOC_BIT; 3774 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3775 } 3776 3777 parameter = 0; 3778 status = XHCI_TRB_2_IRQ_SET(0); 3779 /* the status stage has inverted direction */ 3780 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3781 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3782 XHCI_TRB_3_IOC_BIT; 3783 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3784 3785 mutex_enter(&tr->xr_lock); 3786 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3787 mutex_exit(&tr->xr_lock); 3788 3789 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3790 3791 if (xfer->ux_timeout && !xhci_polling_p(sc)) { 3792 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3793 xhci_timeout, xfer); 3794 } 3795 3796 return USBD_IN_PROGRESS; 3797 } 3798 3799 static void 3800 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3801 { 3802 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3803 usb_device_request_t *req = &xfer->ux_request; 3804 int len = UGETW(req->wLength); 3805 int rd = req->bmRequestType & UT_READ; 3806 3807 if (len) 3808 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3809 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3810 } 3811 3812 static void 3813 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3814 { 3815 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3816 3817 xhci_abort_xfer(xfer, USBD_CANCELLED); 3818 } 3819 3820 static void 3821 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3822 { 3823 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3824 3825 xhci_close_pipe(pipe); 3826 } 3827 3828 /* ------------------ */ 3829 /* device isochronous */ 3830 3831 /* ----------- */ 3832 /* device bulk */ 3833 3834 static usbd_status 3835 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3836 { 3837 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3838 usbd_status err; 3839 3840 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3841 3842 /* Insert last in queue. */ 3843 mutex_enter(&sc->sc_lock); 3844 err = usb_insert_transfer(xfer); 3845 mutex_exit(&sc->sc_lock); 3846 if (err) 3847 return err; 3848 3849 /* 3850 * Pipe isn't running (otherwise err would be USBD_INPROG), 3851 * so start it first. 3852 */ 3853 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3854 } 3855 3856 static usbd_status 3857 xhci_device_bulk_start(struct usbd_xfer *xfer) 3858 { 3859 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3860 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3861 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3862 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3863 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3864 const uint32_t len = xfer->ux_length; 3865 usb_dma_t * const dma = &xfer->ux_dmabuf; 3866 uint64_t parameter; 3867 uint32_t status; 3868 uint32_t control; 3869 u_int i = 0; 3870 3871 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3872 3873 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3874 3875 if (sc->sc_dying) 3876 return USBD_IOERROR; 3877 3878 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3879 3880 parameter = DMAADDR(dma, 0); 3881 /* 3882 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3883 * If the user supplied buffer crosses such a boundary then 2 3884 * (or more) TRB should be used. 3885 * If multiple TRB are used the td_size field must be set correctly. 3886 * For v1.0 devices (like ivy bridge) this is the number of usb data 3887 * blocks needed to complete the transfer. 3888 * Setting it to 1 in the last TRB causes an extra zero-length 3889 * data block be sent. 3890 * The earlier documentation differs, I don't know how it behaves. 3891 */ 3892 KASSERTMSG(len <= 0x10000, "len %d", len); 3893 status = XHCI_TRB_2_IRQ_SET(0) | 3894 XHCI_TRB_2_TDSZ_SET(1) | 3895 XHCI_TRB_2_BYTES_SET(len); 3896 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3897 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3898 XHCI_TRB_3_IOC_BIT; 3899 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3900 3901 mutex_enter(&tr->xr_lock); 3902 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3903 mutex_exit(&tr->xr_lock); 3904 3905 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3906 3907 if (xfer->ux_timeout && !xhci_polling_p(sc)) { 3908 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3909 xhci_timeout, xfer); 3910 } 3911 3912 return USBD_IN_PROGRESS; 3913 } 3914 3915 static void 3916 xhci_device_bulk_done(struct usbd_xfer *xfer) 3917 { 3918 #ifdef USB_DEBUG 3919 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3920 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3921 #endif 3922 const int isread = usbd_xfer_isread(xfer); 3923 3924 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3925 3926 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3927 3928 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3929 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3930 } 3931 3932 static void 3933 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3934 { 3935 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3936 3937 xhci_abort_xfer(xfer, USBD_CANCELLED); 3938 } 3939 3940 static void 3941 xhci_device_bulk_close(struct usbd_pipe *pipe) 3942 { 3943 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3944 3945 xhci_close_pipe(pipe); 3946 } 3947 3948 /* ---------------- */ 3949 /* device interrupt */ 3950 3951 static usbd_status 3952 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3953 { 3954 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3955 usbd_status err; 3956 3957 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3958 3959 /* Insert last in queue. */ 3960 mutex_enter(&sc->sc_lock); 3961 err = usb_insert_transfer(xfer); 3962 mutex_exit(&sc->sc_lock); 3963 if (err) 3964 return err; 3965 3966 /* 3967 * Pipe isn't running (otherwise err would be USBD_INPROG), 3968 * so start it first. 3969 */ 3970 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3971 } 3972 3973 static usbd_status 3974 xhci_device_intr_start(struct usbd_xfer *xfer) 3975 { 3976 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3977 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3978 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3979 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3980 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3981 const uint32_t len = xfer->ux_length; 3982 usb_dma_t * const dma = &xfer->ux_dmabuf; 3983 uint64_t parameter; 3984 uint32_t status; 3985 uint32_t control; 3986 u_int i = 0; 3987 3988 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3989 3990 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 3991 3992 if (sc->sc_dying) 3993 return USBD_IOERROR; 3994 3995 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3996 3997 parameter = DMAADDR(dma, 0); 3998 KASSERTMSG(len <= 0x10000, "len %d", len); 3999 status = XHCI_TRB_2_IRQ_SET(0) | 4000 XHCI_TRB_2_TDSZ_SET(1) | 4001 XHCI_TRB_2_BYTES_SET(len); 4002 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 4003 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 4004 XHCI_TRB_3_IOC_BIT; 4005 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 4006 4007 mutex_enter(&tr->xr_lock); 4008 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 4009 mutex_exit(&tr->xr_lock); 4010 4011 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4012 4013 if (xfer->ux_timeout && !xhci_polling_p(sc)) { 4014 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4015 xhci_timeout, xfer); 4016 } 4017 4018 return USBD_IN_PROGRESS; 4019 } 4020 4021 static void 4022 xhci_device_intr_done(struct usbd_xfer *xfer) 4023 { 4024 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4025 #ifdef USB_DEBUG 4026 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4027 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4028 #endif 4029 const int isread = usbd_xfer_isread(xfer); 4030 4031 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4032 4033 DPRINTFN(15, "%p slot %u dci %u", xfer, xs->xs_idx, dci, 0); 4034 4035 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 4036 4037 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4038 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4039 } 4040 4041 static void 4042 xhci_device_intr_abort(struct usbd_xfer *xfer) 4043 { 4044 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4045 4046 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4047 4048 KASSERT(mutex_owned(&sc->sc_lock)); 4049 DPRINTFN(15, "%p", xfer, 0, 0, 0); 4050 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4051 xhci_abort_xfer(xfer, USBD_CANCELLED); 4052 } 4053 4054 static void 4055 xhci_device_intr_close(struct usbd_pipe *pipe) 4056 { 4057 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 4058 4059 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4060 DPRINTFN(15, "%p", pipe, 0, 0, 0); 4061 4062 xhci_close_pipe(pipe); 4063 } 4064 4065 /* ------------ */ 4066 4067 static void 4068 xhci_timeout(void *addr) 4069 { 4070 struct xhci_xfer * const xx = addr; 4071 struct usbd_xfer * const xfer = &xx->xx_xfer; 4072 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4073 4074 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4075 4076 if (sc->sc_dying) { 4077 return; 4078 } 4079 4080 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 4081 USB_TASKQ_MPSAFE); 4082 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 4083 USB_TASKQ_HC); 4084 } 4085 4086 static void 4087 xhci_timeout_task(void *addr) 4088 { 4089 struct usbd_xfer * const xfer = addr; 4090 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4091 4092 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4093 4094 mutex_enter(&sc->sc_lock); 4095 xhci_abort_xfer(xfer, USBD_TIMEOUT); 4096 mutex_exit(&sc->sc_lock); 4097 } 4098
Indexes created Thu Sep 25 16:09:42 GMT 2025