xhci.c revision 1.75
1 /* $NetBSD: xhci.c,v 1.75 2017/10/28 00:37:13 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.75 2017/10/28 00:37:13 pgoyette Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 static int xhcidebug = 0; 77 78 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 79 { 80 int err; 81 const struct sysctlnode *rnode; 82 const struct sysctlnode *cnode; 83 84 err = sysctl_createv(clog, 0, NULL, &rnode, 85 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 86 SYSCTL_DESCR("xhci global controls"), 87 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 88 89 if (err) 90 goto fail; 91 92 /* control debugging printfs */ 93 err = sysctl_createv(clog, 0, &rnode, &cnode, 94 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 95 "debug", SYSCTL_DESCR("Enable debugging output"), 96 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 97 if (err) 98 goto fail; 99 100 return; 101 fail: 102 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 103 } 104 105 #endif /* !XHCI_DEBUG */ 106 #endif /* USB_DEBUG */ 107 108 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 109 #define XHCIHIST_FUNC() USBHIST_FUNC() 110 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 111 112 #define XHCI_DCI_SLOT 0 113 #define XHCI_DCI_EP_CONTROL 1 114 115 #define XHCI_ICI_INPUT_CONTROL 0 116 117 struct xhci_pipe { 118 struct usbd_pipe xp_pipe; 119 struct usb_task xp_async_task; 120 }; 121 122 #define XHCI_COMMAND_RING_TRBS 256 123 #define XHCI_EVENT_RING_TRBS 256 124 #define XHCI_EVENT_RING_SEGMENTS 1 125 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 126 127 static usbd_status xhci_open(struct usbd_pipe *); 128 static void xhci_close_pipe(struct usbd_pipe *); 129 static int xhci_intr1(struct xhci_softc * const); 130 static void xhci_softintr(void *); 131 static void xhci_poll(struct usbd_bus *); 132 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 133 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 134 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 135 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 136 struct usbd_port *); 137 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 138 void *, int); 139 140 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 141 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 142 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 143 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 144 145 static void xhci_host_dequeue(struct xhci_ring * const); 146 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 147 148 static usbd_status xhci_do_command(struct xhci_softc * const, 149 struct xhci_trb * const, int); 150 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 151 struct xhci_trb * const, int); 152 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 153 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 154 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 155 static usbd_status xhci_enable_slot(struct xhci_softc * const, 156 uint8_t * const); 157 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 158 static usbd_status xhci_address_device(struct xhci_softc * const, 159 uint64_t, uint8_t, bool); 160 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 161 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 162 struct xhci_slot * const, u_int); 163 static usbd_status xhci_ring_init(struct xhci_softc * const, 164 struct xhci_ring * const, size_t, size_t); 165 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 166 167 static void xhci_setup_ctx(struct usbd_pipe *); 168 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 169 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 170 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 171 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 172 173 static void xhci_noop(struct usbd_pipe *); 174 175 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 176 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 177 static void xhci_root_intr_abort(struct usbd_xfer *); 178 static void xhci_root_intr_close(struct usbd_pipe *); 179 static void xhci_root_intr_done(struct usbd_xfer *); 180 181 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 182 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 183 static void xhci_device_ctrl_abort(struct usbd_xfer *); 184 static void xhci_device_ctrl_close(struct usbd_pipe *); 185 static void xhci_device_ctrl_done(struct usbd_xfer *); 186 187 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 188 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 189 static void xhci_device_intr_abort(struct usbd_xfer *); 190 static void xhci_device_intr_close(struct usbd_pipe *); 191 static void xhci_device_intr_done(struct usbd_xfer *); 192 193 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 194 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 195 static void xhci_device_bulk_abort(struct usbd_xfer *); 196 static void xhci_device_bulk_close(struct usbd_pipe *); 197 static void xhci_device_bulk_done(struct usbd_xfer *); 198 199 static void xhci_timeout(void *); 200 static void xhci_timeout_task(void *); 201 202 static const struct usbd_bus_methods xhci_bus_methods = { 203 .ubm_open = xhci_open, 204 .ubm_softint = xhci_softintr, 205 .ubm_dopoll = xhci_poll, 206 .ubm_allocx = xhci_allocx, 207 .ubm_freex = xhci_freex, 208 .ubm_getlock = xhci_get_lock, 209 .ubm_newdev = xhci_new_device, 210 .ubm_rhctrl = xhci_roothub_ctrl, 211 }; 212 213 static const struct usbd_pipe_methods xhci_root_intr_methods = { 214 .upm_transfer = xhci_root_intr_transfer, 215 .upm_start = xhci_root_intr_start, 216 .upm_abort = xhci_root_intr_abort, 217 .upm_close = xhci_root_intr_close, 218 .upm_cleartoggle = xhci_noop, 219 .upm_done = xhci_root_intr_done, 220 }; 221 222 223 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 224 .upm_transfer = xhci_device_ctrl_transfer, 225 .upm_start = xhci_device_ctrl_start, 226 .upm_abort = xhci_device_ctrl_abort, 227 .upm_close = xhci_device_ctrl_close, 228 .upm_cleartoggle = xhci_noop, 229 .upm_done = xhci_device_ctrl_done, 230 }; 231 232 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 233 .upm_cleartoggle = xhci_noop, 234 }; 235 236 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 237 .upm_transfer = xhci_device_bulk_transfer, 238 .upm_start = xhci_device_bulk_start, 239 .upm_abort = xhci_device_bulk_abort, 240 .upm_close = xhci_device_bulk_close, 241 .upm_cleartoggle = xhci_noop, 242 .upm_done = xhci_device_bulk_done, 243 }; 244 245 static const struct usbd_pipe_methods xhci_device_intr_methods = { 246 .upm_transfer = xhci_device_intr_transfer, 247 .upm_start = xhci_device_intr_start, 248 .upm_abort = xhci_device_intr_abort, 249 .upm_close = xhci_device_intr_close, 250 .upm_cleartoggle = xhci_noop, 251 .upm_done = xhci_device_intr_done, 252 }; 253 254 static inline uint32_t 255 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 256 { 257 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 258 } 259 260 static inline uint32_t 261 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 262 { 263 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 264 } 265 266 static inline void 267 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 268 uint32_t value) 269 { 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 271 } 272 273 #if 0 /* unused */ 274 static inline void 275 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 276 uint32_t value) 277 { 278 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 279 } 280 #endif /* unused */ 281 282 static inline uint32_t 283 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 284 { 285 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 286 } 287 288 static inline uint32_t 289 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 290 { 291 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 292 } 293 294 static inline void 295 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 296 uint32_t value) 297 { 298 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 299 } 300 301 static inline uint64_t 302 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 303 { 304 uint64_t value; 305 306 if (sc->sc_ac64) { 307 #ifdef XHCI_USE_BUS_SPACE_8 308 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 309 #else 310 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 311 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 312 offset + 4) << 32; 313 #endif 314 } else { 315 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 316 } 317 318 return value; 319 } 320 321 static inline void 322 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 323 uint64_t value) 324 { 325 if (sc->sc_ac64) { 326 #ifdef XHCI_USE_BUS_SPACE_8 327 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 328 #else 329 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 330 (value >> 0) & 0xffffffff); 331 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 332 (value >> 32) & 0xffffffff); 333 #endif 334 } else { 335 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 336 } 337 } 338 339 static inline uint32_t 340 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 341 { 342 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 343 } 344 345 static inline void 346 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 347 uint32_t value) 348 { 349 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 350 } 351 352 #if 0 /* unused */ 353 static inline uint64_t 354 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 355 { 356 uint64_t value; 357 358 if (sc->sc_ac64) { 359 #ifdef XHCI_USE_BUS_SPACE_8 360 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 361 #else 362 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 363 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 364 offset + 4) << 32; 365 #endif 366 } else { 367 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 368 } 369 370 return value; 371 } 372 #endif /* unused */ 373 374 static inline void 375 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 376 uint64_t value) 377 { 378 if (sc->sc_ac64) { 379 #ifdef XHCI_USE_BUS_SPACE_8 380 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 381 #else 382 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 383 (value >> 0) & 0xffffffff); 384 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 385 (value >> 32) & 0xffffffff); 386 #endif 387 } else { 388 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 389 } 390 } 391 392 #if 0 /* unused */ 393 static inline uint32_t 394 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 395 { 396 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 397 } 398 #endif /* unused */ 399 400 static inline void 401 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 402 uint32_t value) 403 { 404 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 405 } 406 407 /* --- */ 408 409 static inline uint8_t 410 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 411 { 412 u_int eptype = 0; 413 414 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 415 case UE_CONTROL: 416 eptype = 0x0; 417 break; 418 case UE_ISOCHRONOUS: 419 eptype = 0x1; 420 break; 421 case UE_BULK: 422 eptype = 0x2; 423 break; 424 case UE_INTERRUPT: 425 eptype = 0x3; 426 break; 427 } 428 429 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 430 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 431 return eptype | 0x4; 432 else 433 return eptype; 434 } 435 436 static u_int 437 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 438 { 439 /* xHCI 1.0 section 4.5.1 */ 440 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 441 u_int in = 0; 442 443 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 444 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 445 in = 1; 446 447 return epaddr * 2 + in; 448 } 449 450 static inline u_int 451 xhci_dci_to_ici(const u_int i) 452 { 453 return i + 1; 454 } 455 456 static inline void * 457 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 458 const u_int dci) 459 { 460 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 461 } 462 463 #if 0 /* unused */ 464 static inline bus_addr_t 465 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 466 const u_int dci) 467 { 468 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 469 } 470 #endif /* unused */ 471 472 static inline void * 473 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 474 const u_int ici) 475 { 476 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 477 } 478 479 static inline bus_addr_t 480 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 481 const u_int ici) 482 { 483 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 484 } 485 486 static inline struct xhci_trb * 487 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 488 { 489 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 490 } 491 492 static inline bus_addr_t 493 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 494 { 495 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 496 } 497 498 static inline void 499 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 500 uint32_t control) 501 { 502 trb->trb_0 = htole64(parameter); 503 trb->trb_2 = htole32(status); 504 trb->trb_3 = htole32(control); 505 } 506 507 static int 508 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 509 { 510 /* base address of TRBs */ 511 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 512 513 /* trb_0 range sanity check */ 514 if (trb_0 == 0 || trb_0 < trbp || 515 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 516 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 517 return 1; 518 } 519 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 520 return 0; 521 } 522 523 static unsigned int 524 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 525 u_int dci) 526 { 527 uint32_t *cp; 528 529 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 530 cp = xhci_slot_get_dcv(sc, xs, dci); 531 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 532 } 533 534 static inline unsigned int 535 xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport) 536 { 537 const unsigned int port = ctlrport - 1; 538 const uint8_t bit = __BIT(port % NBBY); 539 540 return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit); 541 } 542 543 /* 544 * Return the roothub port for a controller port. Both are 1..n. 545 */ 546 static inline unsigned int 547 xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport) 548 { 549 550 return sc->sc_ctlrportmap[ctrlport - 1]; 551 } 552 553 /* 554 * Return the controller port for a bus roothub port. Both are 1..n. 555 */ 556 static inline unsigned int 557 xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn, 558 unsigned int rhport) 559 { 560 561 return sc->sc_rhportmap[bn][rhport - 1]; 562 } 563 564 /* --- */ 565 566 void 567 xhci_childdet(device_t self, device_t child) 568 { 569 struct xhci_softc * const sc = device_private(self); 570 571 KASSERT(sc->sc_child == child); 572 if (child == sc->sc_child) 573 sc->sc_child = NULL; 574 } 575 576 int 577 xhci_detach(struct xhci_softc *sc, int flags) 578 { 579 int rv = 0; 580 581 if (sc->sc_child2 != NULL) { 582 rv = config_detach(sc->sc_child2, flags); 583 if (rv != 0) 584 return rv; 585 } 586 587 if (sc->sc_child != NULL) { 588 rv = config_detach(sc->sc_child, flags); 589 if (rv != 0) 590 return rv; 591 } 592 593 /* XXX unconfigure/free slots */ 594 595 /* verify: */ 596 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 597 xhci_op_write_4(sc, XHCI_USBCMD, 0); 598 /* do we need to wait for stop? */ 599 600 xhci_op_write_8(sc, XHCI_CRCR, 0); 601 xhci_ring_free(sc, &sc->sc_cr); 602 cv_destroy(&sc->sc_command_cv); 603 cv_destroy(&sc->sc_cmdbusy_cv); 604 605 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 606 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 607 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 608 xhci_ring_free(sc, &sc->sc_er); 609 610 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 611 612 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 613 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 614 615 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 616 617 kmem_free(sc->sc_ctlrportbus, 618 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY)); 619 kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int)); 620 621 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 622 kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int)); 623 } 624 625 mutex_destroy(&sc->sc_lock); 626 mutex_destroy(&sc->sc_intr_lock); 627 628 pool_cache_destroy(sc->sc_xferpool); 629 630 return rv; 631 } 632 633 int 634 xhci_activate(device_t self, enum devact act) 635 { 636 struct xhci_softc * const sc = device_private(self); 637 638 switch (act) { 639 case DVACT_DEACTIVATE: 640 sc->sc_dying = true; 641 return 0; 642 default: 643 return EOPNOTSUPP; 644 } 645 } 646 647 bool 648 xhci_suspend(device_t dv, const pmf_qual_t *qual) 649 { 650 return false; 651 } 652 653 bool 654 xhci_resume(device_t dv, const pmf_qual_t *qual) 655 { 656 return false; 657 } 658 659 bool 660 xhci_shutdown(device_t self, int flags) 661 { 662 return false; 663 } 664 665 static int 666 xhci_hc_reset(struct xhci_softc * const sc) 667 { 668 uint32_t usbcmd, usbsts; 669 int i; 670 671 /* Check controller not ready */ 672 for (i = 0; i < XHCI_WAIT_CNR; i++) { 673 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 674 if ((usbsts & XHCI_STS_CNR) == 0) 675 break; 676 usb_delay_ms(&sc->sc_bus, 1); 677 } 678 if (i >= XHCI_WAIT_CNR) { 679 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 680 return EIO; 681 } 682 683 /* Halt controller */ 684 usbcmd = 0; 685 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 686 usb_delay_ms(&sc->sc_bus, 1); 687 688 /* Reset controller */ 689 usbcmd = XHCI_CMD_HCRST; 690 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 691 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 692 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 693 if ((usbcmd & XHCI_CMD_HCRST) == 0) 694 break; 695 usb_delay_ms(&sc->sc_bus, 1); 696 } 697 if (i >= XHCI_WAIT_HCRST) { 698 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 699 return EIO; 700 } 701 702 /* Check controller not ready */ 703 for (i = 0; i < XHCI_WAIT_CNR; i++) { 704 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 705 if ((usbsts & XHCI_STS_CNR) == 0) 706 break; 707 usb_delay_ms(&sc->sc_bus, 1); 708 } 709 if (i >= XHCI_WAIT_CNR) { 710 aprint_error_dev(sc->sc_dev, 711 "controller not ready timeout after reset\n"); 712 return EIO; 713 } 714 715 return 0; 716 } 717 718 719 static void 720 hexdump(const char *msg, const void *base, size_t len) 721 { 722 #if 0 723 size_t cnt; 724 const uint32_t *p; 725 extern paddr_t vtophys(vaddr_t); 726 727 p = base; 728 cnt = 0; 729 730 printf("*** %s (%zu bytes @ %p %p)\n", msg, len, base, 731 (void *)vtophys((vaddr_t)base)); 732 733 while (cnt < len) { 734 if (cnt % 16 == 0) 735 printf("%p: ", p); 736 else if (cnt % 8 == 0) 737 printf(" |"); 738 printf(" %08x", *p++); 739 cnt += 4; 740 if (cnt % 16 == 0) 741 printf("\n"); 742 } 743 if (cnt % 16 != 0) 744 printf("\n"); 745 #endif 746 } 747 748 /* 7.2 xHCI Support Protocol Capability */ 749 static void 750 xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp) 751 { 752 /* XXX Cache this lot */ 753 754 const uint32_t w0 = xhci_read_4(sc, ecp); 755 const uint32_t w4 = xhci_read_4(sc, ecp + 4); 756 const uint32_t w8 = xhci_read_4(sc, ecp + 8); 757 const uint32_t wc = xhci_read_4(sc, ecp + 0xc); 758 759 aprint_debug_dev(sc->sc_dev, 760 " SP: %08x %08x %08x %08x\n", w0, w4, w8, wc); 761 762 if (w4 != XHCI_XECP_USBID) 763 return; 764 765 const int major = XHCI_XECP_SP_W0_MAJOR(w0); 766 const int minor = XHCI_XECP_SP_W0_MINOR(w0); 767 const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8); 768 const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8); 769 770 const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16)); 771 switch (mm) { 772 case 0x0200: 773 case 0x0300: 774 case 0x0301: 775 aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n", 776 major == 3 ? "ss" : "hs", cpo, cpo + cpc -1); 777 break; 778 default: 779 aprint_debug_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n", 780 major, minor); 781 return; 782 } 783 784 const size_t bus = (major == 3) ? 0 : 1; 785 786 /* Index arrays with 0..n-1 where ports are numbered 1..n */ 787 for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) { 788 if (sc->sc_ctlrportmap[cp] != 0) { 789 aprint_error_dev(sc->sc_dev, "contoller port %zu " 790 "already assigned", cp); 791 continue; 792 } 793 794 sc->sc_ctlrportbus[cp / NBBY] |= 795 bus == 0 ? 0 : __BIT(cp % NBBY); 796 797 const size_t rhp = sc->sc_rhportcount[bus]++; 798 799 KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0, 800 "bus %zu rhp %zu is %d", bus, rhp, 801 sc->sc_rhportmap[bus][rhp]); 802 803 sc->sc_rhportmap[bus][rhp] = cp + 1; 804 sc->sc_ctlrportmap[cp] = rhp + 1; 805 } 806 } 807 808 /* Process extended capabilities */ 809 static void 810 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 811 { 812 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 813 814 bus_size_t ecp = XHCI_HCC_XECP(hcc) * 4; 815 while (ecp != 0) { 816 uint32_t ecr = xhci_read_4(sc, ecp); 817 aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr); 818 switch (XHCI_XECP_ID(ecr)) { 819 case XHCI_ID_PROTOCOLS: { 820 xhci_id_protocols(sc, ecp); 821 break; 822 } 823 case XHCI_ID_USB_LEGACY: { 824 uint8_t bios_sem; 825 826 /* Take host controller ownership from BIOS */ 827 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 828 if (bios_sem) { 829 /* sets xHCI to be owned by OS */ 830 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 831 aprint_debug_dev(sc->sc_dev, 832 "waiting for BIOS to give up control\n"); 833 for (int i = 0; i < 5000; i++) { 834 bios_sem = xhci_read_1(sc, ecp + 835 XHCI_XECP_BIOS_SEM); 836 if (bios_sem == 0) 837 break; 838 DELAY(1000); 839 } 840 if (bios_sem) { 841 aprint_error_dev(sc->sc_dev, 842 "timed out waiting for BIOS\n"); 843 } 844 } 845 break; 846 } 847 default: 848 break; 849 } 850 ecr = xhci_read_4(sc, ecp); 851 if (XHCI_XECP_NEXT(ecr) == 0) { 852 ecp = 0; 853 } else { 854 ecp += XHCI_XECP_NEXT(ecr) * 4; 855 } 856 } 857 } 858 859 #define XHCI_HCCPREV1_BITS \ 860 "\177\020" /* New bitmask */ \ 861 "f\020\020XECP\0" \ 862 "f\014\4MAXPSA\0" \ 863 "b\013CFC\0" \ 864 "b\012SEC\0" \ 865 "b\011SBD\0" \ 866 "b\010FSE\0" \ 867 "b\7NSS\0" \ 868 "b\6LTC\0" \ 869 "b\5LHRC\0" \ 870 "b\4PIND\0" \ 871 "b\3PPC\0" \ 872 "b\2CZC\0" \ 873 "b\1BNC\0" \ 874 "b\0AC64\0" \ 875 "\0" 876 #define XHCI_HCCV1_x_BITS \ 877 "\177\020" /* New bitmask */ \ 878 "f\020\020XECP\0" \ 879 "f\014\4MAXPSA\0" \ 880 "b\013CFC\0" \ 881 "b\012SEC\0" \ 882 "b\011SPC\0" \ 883 "b\010PAE\0" \ 884 "b\7NSS\0" \ 885 "b\6LTC\0" \ 886 "b\5LHRC\0" \ 887 "b\4PIND\0" \ 888 "b\3PPC\0" \ 889 "b\2CSZ\0" \ 890 "b\1BNC\0" \ 891 "b\0AC64\0" \ 892 "\0" 893 894 void 895 xhci_start(struct xhci_softc *sc) 896 { 897 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 898 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 899 /* Intel xhci needs interrupt rate moderated. */ 900 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 901 else 902 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 903 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 904 xhci_rt_read_4(sc, XHCI_IMOD(0))); 905 906 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 907 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 908 xhci_op_read_4(sc, XHCI_USBCMD)); 909 } 910 911 int 912 xhci_init(struct xhci_softc *sc) 913 { 914 bus_size_t bsz; 915 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 916 uint32_t pagesize, config; 917 int i = 0; 918 uint16_t hciversion; 919 uint8_t caplength; 920 921 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 922 923 /* Set up the bus struct for the usb 3 and usb 2 buses */ 924 sc->sc_bus.ub_methods = &xhci_bus_methods; 925 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 926 sc->sc_bus.ub_revision = USBREV_3_0; 927 sc->sc_bus.ub_usedma = true; 928 sc->sc_bus.ub_hcpriv = sc; 929 930 sc->sc_bus2.ub_methods = &xhci_bus_methods; 931 sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe); 932 sc->sc_bus2.ub_revision = USBREV_2_0; 933 sc->sc_bus2.ub_usedma = true; 934 sc->sc_bus2.ub_hcpriv = sc; 935 sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag; 936 937 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 938 caplength = XHCI_CAP_CAPLENGTH(cap); 939 hciversion = XHCI_CAP_HCIVERSION(cap); 940 941 if (hciversion < XHCI_HCIVERSION_0_96 || 942 hciversion > XHCI_HCIVERSION_1_0) { 943 aprint_normal_dev(sc->sc_dev, 944 "xHCI version %x.%x not known to be supported\n", 945 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 946 } else { 947 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 948 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 949 } 950 951 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 952 &sc->sc_cbh) != 0) { 953 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 954 return ENOMEM; 955 } 956 957 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 958 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 959 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 960 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 961 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 962 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 963 aprint_debug_dev(sc->sc_dev, 964 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 965 966 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 967 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 968 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 969 970 char sbuf[128]; 971 if (hciversion < XHCI_HCIVERSION_1_0) 972 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 973 else 974 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 975 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 976 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 977 978 /* default all ports to bus 0, i.e. usb 3 */ 979 sc->sc_ctlrportbus = kmem_zalloc( 980 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP); 981 sc->sc_ctlrportmap = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 982 983 /* controller port to bus roothub port map */ 984 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 985 sc->sc_rhportmap[j] = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 986 } 987 988 /* 989 * Process all Extended Capabilities 990 */ 991 xhci_ecp(sc, hcc); 992 993 bsz = XHCI_PORTSC(sc->sc_maxports); 994 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 995 &sc->sc_obh) != 0) { 996 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 997 return ENOMEM; 998 } 999 1000 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 1001 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 1002 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 1003 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 1004 return ENOMEM; 1005 } 1006 1007 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 1008 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 1009 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 1010 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 1011 return ENOMEM; 1012 } 1013 1014 int rv; 1015 rv = xhci_hc_reset(sc); 1016 if (rv != 0) { 1017 return rv; 1018 } 1019 1020 if (sc->sc_vendor_init) 1021 sc->sc_vendor_init(sc); 1022 1023 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 1024 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 1025 pagesize = ffs(pagesize); 1026 if (pagesize == 0) { 1027 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 1028 return EIO; 1029 } 1030 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 1031 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 1032 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 1033 (uint32_t)sc->sc_maxslots); 1034 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 1035 1036 usbd_status err; 1037 1038 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 1039 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 1040 if (sc->sc_maxspbuf != 0) { 1041 err = usb_allocmem(&sc->sc_bus, 1042 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 1043 &sc->sc_spbufarray_dma); 1044 if (err) { 1045 aprint_error_dev(sc->sc_dev, 1046 "spbufarray init fail, err %d\n", err); 1047 return ENOMEM; 1048 } 1049 1050 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 1051 sc->sc_maxspbuf, KM_SLEEP); 1052 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 1053 for (i = 0; i < sc->sc_maxspbuf; i++) { 1054 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 1055 /* allocate contexts */ 1056 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 1057 sc->sc_pgsz, dma); 1058 if (err) { 1059 aprint_error_dev(sc->sc_dev, 1060 "spbufarray_dma init fail, err %d\n", err); 1061 rv = ENOMEM; 1062 goto bad1; 1063 } 1064 spbufarray[i] = htole64(DMAADDR(dma, 0)); 1065 usb_syncmem(dma, 0, sc->sc_pgsz, 1066 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1067 } 1068 1069 usb_syncmem(&sc->sc_spbufarray_dma, 0, 1070 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 1071 } 1072 1073 config = xhci_op_read_4(sc, XHCI_CONFIG); 1074 config &= ~0xFF; 1075 config |= sc->sc_maxslots & 0xFF; 1076 xhci_op_write_4(sc, XHCI_CONFIG, config); 1077 1078 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 1079 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 1080 if (err) { 1081 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 1082 err); 1083 rv = ENOMEM; 1084 goto bad1; 1085 } 1086 1087 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 1088 XHCI_EVENT_RING_SEGMENTS_ALIGN); 1089 if (err) { 1090 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 1091 err); 1092 rv = ENOMEM; 1093 goto bad2; 1094 } 1095 1096 usb_dma_t *dma; 1097 size_t size; 1098 size_t align; 1099 1100 dma = &sc->sc_eventst_dma; 1101 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 1102 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 1103 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 1104 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 1105 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1106 if (err) { 1107 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 1108 err); 1109 rv = ENOMEM; 1110 goto bad3; 1111 } 1112 1113 memset(KERNADDR(dma, 0), 0, size); 1114 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1115 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 1116 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 1117 KERNADDR(&sc->sc_eventst_dma, 0), 1118 sc->sc_eventst_dma.udma_block->size); 1119 1120 dma = &sc->sc_dcbaa_dma; 1121 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 1122 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 1123 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 1124 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1125 if (err) { 1126 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1127 rv = ENOMEM; 1128 goto bad4; 1129 } 1130 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 1131 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1132 KERNADDR(&sc->sc_dcbaa_dma, 0), 1133 sc->sc_dcbaa_dma.udma_block->size); 1134 1135 memset(KERNADDR(dma, 0), 0, size); 1136 if (sc->sc_maxspbuf != 0) { 1137 /* 1138 * DCBA entry 0 hold the scratchbuf array pointer. 1139 */ 1140 *(uint64_t *)KERNADDR(dma, 0) = 1141 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1142 } 1143 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1144 1145 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1146 KM_SLEEP); 1147 if (sc->sc_slots == NULL) { 1148 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1149 rv = ENOMEM; 1150 goto bad; 1151 } 1152 1153 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1154 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1155 if (sc->sc_xferpool == NULL) { 1156 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1157 err); 1158 rv = ENOMEM; 1159 goto bad; 1160 } 1161 1162 cv_init(&sc->sc_command_cv, "xhcicmd"); 1163 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1164 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1165 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1166 1167 struct xhci_erste *erst; 1168 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1169 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1170 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1171 erst[0].erste_3 = htole32(0); 1172 usb_syncmem(&sc->sc_eventst_dma, 0, 1173 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1174 1175 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1176 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1177 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1178 XHCI_ERDP_LO_BUSY); 1179 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1180 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1181 sc->sc_cr.xr_cs); 1182 1183 #if 0 1184 hexdump("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1185 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1186 #endif 1187 1188 if ((sc->sc_quirks & XHCI_DEFERRED_START) == 0) 1189 xhci_start(sc); 1190 1191 return 0; 1192 1193 bad: 1194 if (sc->sc_xferpool) { 1195 pool_cache_destroy(sc->sc_xferpool); 1196 sc->sc_xferpool = NULL; 1197 } 1198 1199 if (sc->sc_slots) { 1200 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1201 sc->sc_maxslots); 1202 sc->sc_slots = NULL; 1203 } 1204 1205 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1206 bad4: 1207 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1208 bad3: 1209 xhci_ring_free(sc, &sc->sc_er); 1210 bad2: 1211 xhci_ring_free(sc, &sc->sc_cr); 1212 i = sc->sc_maxspbuf; 1213 bad1: 1214 for (int j = 0; j < i; j++) 1215 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1216 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1217 1218 return rv; 1219 } 1220 1221 static inline bool 1222 xhci_polling_p(struct xhci_softc * const sc) 1223 { 1224 return sc->sc_bus.ub_usepolling || sc->sc_bus2.ub_usepolling; 1225 } 1226 1227 int 1228 xhci_intr(void *v) 1229 { 1230 struct xhci_softc * const sc = v; 1231 int ret = 0; 1232 1233 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1234 1235 if (sc == NULL) 1236 return 0; 1237 1238 mutex_spin_enter(&sc->sc_intr_lock); 1239 1240 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1241 goto done; 1242 1243 /* If we get an interrupt while polling, then just ignore it. */ 1244 if (xhci_polling_p(sc)) { 1245 #ifdef DIAGNOSTIC 1246 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1247 #endif 1248 goto done; 1249 } 1250 1251 ret = xhci_intr1(sc); 1252 if (ret) { 1253 usb_schedsoftintr(&sc->sc_bus); 1254 } 1255 done: 1256 mutex_spin_exit(&sc->sc_intr_lock); 1257 return ret; 1258 } 1259 1260 int 1261 xhci_intr1(struct xhci_softc * const sc) 1262 { 1263 uint32_t usbsts; 1264 uint32_t iman; 1265 1266 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1267 1268 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1269 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1270 #if 0 1271 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1272 return 0; 1273 } 1274 #endif 1275 xhci_op_write_4(sc, XHCI_USBSTS, 1276 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1277 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1278 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1279 1280 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1281 DPRINTFN(16, "IMAN0 %08jx", iman, 0, 0, 0); 1282 iman |= XHCI_IMAN_INTR_PEND; 1283 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1284 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1285 DPRINTFN(16, "IMAN0 %08jx", iman, 0, 0, 0); 1286 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1287 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1288 1289 return 1; 1290 } 1291 1292 /* 1293 * 3 port speed types used in USB stack 1294 * 1295 * usbdi speed 1296 * definition: USB_SPEED_* in usb.h 1297 * They are used in struct usbd_device in USB stack. 1298 * ioctl interface uses these values too. 1299 * port_status speed 1300 * definition: UPS_*_SPEED in usb.h 1301 * They are used in usb_port_status_t and valid only for USB 2.0. 1302 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1303 * of usb_port_status_ext_t indicates port speed. 1304 * Note that some 3.0 values overlap with 2.0 values. 1305 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1306 * means UPS_LOW_SPEED in HS.) 1307 * port status returned from hub also uses these values. 1308 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1309 * or more. 1310 * xspeed: 1311 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1312 * They are used in only slot context and PORTSC reg of xhci. 1313 * The difference between usbdi speed and xspeed is 1314 * that FS and LS values are swapped. 1315 */ 1316 1317 /* convert usbdi speed to xspeed */ 1318 static int 1319 xhci_speed2xspeed(int speed) 1320 { 1321 switch (speed) { 1322 case USB_SPEED_LOW: return 2; 1323 case USB_SPEED_FULL: return 1; 1324 default: return speed; 1325 } 1326 } 1327 1328 #if 0 1329 /* convert xspeed to usbdi speed */ 1330 static int 1331 xhci_xspeed2speed(int xspeed) 1332 { 1333 switch (xspeed) { 1334 case 1: return USB_SPEED_FULL; 1335 case 2: return USB_SPEED_LOW; 1336 default: return xspeed; 1337 } 1338 } 1339 #endif 1340 1341 /* convert xspeed to port status speed */ 1342 static int 1343 xhci_xspeed2psspeed(int xspeed) 1344 { 1345 switch (xspeed) { 1346 case 0: return 0; 1347 case 1: return UPS_FULL_SPEED; 1348 case 2: return UPS_LOW_SPEED; 1349 case 3: return UPS_HIGH_SPEED; 1350 default: return UPS_OTHER_SPEED; 1351 } 1352 } 1353 1354 /* 1355 * Construct input contexts and issue TRB to open pipe. 1356 */ 1357 static usbd_status 1358 xhci_configure_endpoint(struct usbd_pipe *pipe) 1359 { 1360 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1361 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1362 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1363 struct xhci_trb trb; 1364 usbd_status err; 1365 1366 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1367 DPRINTFN(4, "slot %ju dci %ju epaddr 0x%02jx attr 0x%02jx", 1368 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1369 pipe->up_endpoint->ue_edesc->bmAttributes); 1370 1371 /* XXX ensure input context is available? */ 1372 1373 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1374 1375 /* set up context */ 1376 xhci_setup_ctx(pipe); 1377 1378 hexdump("input control context", xhci_slot_get_icv(sc, xs, 0), 1379 sc->sc_ctxsz * 1); 1380 hexdump("input endpoint context", xhci_slot_get_icv(sc, xs, 1381 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1382 1383 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1384 trb.trb_2 = 0; 1385 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1386 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1387 1388 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1389 1390 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1391 hexdump("output context", xhci_slot_get_dcv(sc, xs, dci), 1392 sc->sc_ctxsz * 1); 1393 1394 return err; 1395 } 1396 1397 #if 0 1398 static usbd_status 1399 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1400 { 1401 #ifdef USB_DEBUG 1402 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1403 #endif 1404 1405 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1406 DPRINTFN(4, "slot %ju", xs->xs_idx, 0, 0, 0); 1407 1408 return USBD_NORMAL_COMPLETION; 1409 } 1410 #endif 1411 1412 /* 4.6.8, 6.4.3.7 */ 1413 static usbd_status 1414 xhci_reset_endpoint_locked(struct usbd_pipe *pipe) 1415 { 1416 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1417 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1418 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1419 struct xhci_trb trb; 1420 usbd_status err; 1421 1422 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1423 DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1424 1425 KASSERT(mutex_owned(&sc->sc_lock)); 1426 1427 trb.trb_0 = 0; 1428 trb.trb_2 = 0; 1429 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1430 XHCI_TRB_3_EP_SET(dci) | 1431 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1432 1433 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1434 1435 return err; 1436 } 1437 1438 static usbd_status 1439 xhci_reset_endpoint(struct usbd_pipe *pipe) 1440 { 1441 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1442 1443 mutex_enter(&sc->sc_lock); 1444 usbd_status ret = xhci_reset_endpoint_locked(pipe); 1445 mutex_exit(&sc->sc_lock); 1446 1447 return ret; 1448 } 1449 1450 /* 1451 * 4.6.9, 6.4.3.8 1452 * Stop execution of TDs on xfer ring. 1453 * Should be called with sc_lock held. 1454 */ 1455 static usbd_status 1456 xhci_stop_endpoint(struct usbd_pipe *pipe) 1457 { 1458 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1459 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1460 struct xhci_trb trb; 1461 usbd_status err; 1462 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1463 1464 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1465 DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1466 1467 KASSERT(mutex_owned(&sc->sc_lock)); 1468 1469 trb.trb_0 = 0; 1470 trb.trb_2 = 0; 1471 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1472 XHCI_TRB_3_EP_SET(dci) | 1473 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1474 1475 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1476 1477 return err; 1478 } 1479 1480 /* 1481 * Set TR Dequeue Pointer. 1482 * xHCI 1.1 4.6.10 6.4.3.9 1483 * Purge all of the TRBs on ring and reinitialize ring. 1484 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1485 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1486 * error will be generated. 1487 */ 1488 static usbd_status 1489 xhci_set_dequeue_locked(struct usbd_pipe *pipe) 1490 { 1491 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1492 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1493 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1494 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1495 struct xhci_trb trb; 1496 usbd_status err; 1497 1498 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1499 DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1500 1501 KASSERT(mutex_owned(&sc->sc_lock)); 1502 1503 xhci_host_dequeue(xr); 1504 1505 /* set DCS */ 1506 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1507 trb.trb_2 = 0; 1508 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1509 XHCI_TRB_3_EP_SET(dci) | 1510 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1511 1512 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1513 1514 return err; 1515 } 1516 1517 static usbd_status 1518 xhci_set_dequeue(struct usbd_pipe *pipe) 1519 { 1520 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1521 1522 mutex_enter(&sc->sc_lock); 1523 usbd_status ret = xhci_set_dequeue_locked(pipe); 1524 mutex_exit(&sc->sc_lock); 1525 1526 return ret; 1527 } 1528 1529 /* 1530 * Open new pipe: called from usbd_setup_pipe_flags. 1531 * Fills methods of pipe. 1532 * If pipe is not for ep0, calls configure_endpoint. 1533 */ 1534 static usbd_status 1535 xhci_open(struct usbd_pipe *pipe) 1536 { 1537 struct usbd_device * const dev = pipe->up_dev; 1538 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1539 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1540 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1541 1542 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1543 DPRINTFN(1, "addr %jd depth %jd port %jd speed %jd", dev->ud_addr, 1544 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1545 DPRINTFN(1, " dci %ju type 0x%02jx epaddr 0x%02jx attr 0x%02jx", 1546 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1547 ed->bmAttributes); 1548 DPRINTFN(1, " mps %ju ival %ju", UGETW(ed->wMaxPacketSize), 1549 ed->bInterval, 0, 0); 1550 1551 if (sc->sc_dying) 1552 return USBD_IOERROR; 1553 1554 /* Root Hub */ 1555 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1556 switch (ed->bEndpointAddress) { 1557 case USB_CONTROL_ENDPOINT: 1558 pipe->up_methods = &roothub_ctrl_methods; 1559 break; 1560 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1561 pipe->up_methods = &xhci_root_intr_methods; 1562 break; 1563 default: 1564 pipe->up_methods = NULL; 1565 DPRINTFN(0, "bad bEndpointAddress 0x%02jx", 1566 ed->bEndpointAddress, 0, 0, 0); 1567 return USBD_INVAL; 1568 } 1569 return USBD_NORMAL_COMPLETION; 1570 } 1571 1572 switch (xfertype) { 1573 case UE_CONTROL: 1574 pipe->up_methods = &xhci_device_ctrl_methods; 1575 break; 1576 case UE_ISOCHRONOUS: 1577 pipe->up_methods = &xhci_device_isoc_methods; 1578 return USBD_INVAL; 1579 break; 1580 case UE_BULK: 1581 pipe->up_methods = &xhci_device_bulk_methods; 1582 break; 1583 case UE_INTERRUPT: 1584 pipe->up_methods = &xhci_device_intr_methods; 1585 break; 1586 default: 1587 return USBD_IOERROR; 1588 break; 1589 } 1590 1591 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1592 return xhci_configure_endpoint(pipe); 1593 1594 return USBD_NORMAL_COMPLETION; 1595 } 1596 1597 /* 1598 * Closes pipe, called from usbd_kill_pipe via close methods. 1599 * If the endpoint to be closed is ep0, disable_slot. 1600 * Should be called with sc_lock held. 1601 */ 1602 static void 1603 xhci_close_pipe(struct usbd_pipe *pipe) 1604 { 1605 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1606 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1607 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1608 const u_int dci = xhci_ep_get_dci(ed); 1609 struct xhci_trb trb; 1610 uint32_t *cp; 1611 1612 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1613 1614 if (sc->sc_dying) 1615 return; 1616 1617 /* xs is uninitialized before xhci_init_slot */ 1618 if (xs == NULL || xs->xs_idx == 0) 1619 return; 1620 1621 DPRINTFN(4, "pipe %#jx slot %ju dci %ju", (uintptr_t)pipe, xs->xs_idx, 1622 dci, 0); 1623 1624 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1625 KASSERT(mutex_owned(&sc->sc_lock)); 1626 1627 if (pipe->up_dev->ud_depth == 0) 1628 return; 1629 1630 if (dci == XHCI_DCI_EP_CONTROL) { 1631 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1632 xhci_disable_slot(sc, xs->xs_idx); 1633 return; 1634 } 1635 1636 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED) 1637 (void)xhci_stop_endpoint(pipe); 1638 1639 /* 1640 * set appropriate bit to be dropped. 1641 * don't set DC bit to 1, otherwise all endpoints 1642 * would be deconfigured. 1643 */ 1644 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1645 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1646 cp[1] = htole32(0); 1647 1648 /* XXX should be most significant one, not dci? */ 1649 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1650 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1651 1652 /* configure ep context performs an implicit dequeue */ 1653 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 1654 1655 /* sync input contexts before they are read from memory */ 1656 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1657 1658 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1659 trb.trb_2 = 0; 1660 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1661 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1662 1663 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1664 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1665 } 1666 1667 /* 1668 * Abort transfer. 1669 * Should be called with sc_lock held. 1670 */ 1671 static void 1672 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1673 { 1674 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1675 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1676 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1677 1678 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1679 DPRINTFN(4, "xfer %#jx pipe %#jx status %jd", 1680 (uintptr_t)xfer, (uintptr_t)xfer->ux_pipe, status, 0); 1681 1682 KASSERT(mutex_owned(&sc->sc_lock)); 1683 1684 if (sc->sc_dying) { 1685 /* If we're dying, just do the software part. */ 1686 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 1687 xfer->ux_status, 0, 0); 1688 xfer->ux_status = status; 1689 callout_stop(&xfer->ux_callout); 1690 usb_transfer_complete(xfer); 1691 return; 1692 } 1693 1694 /* 1695 * If an abort is already in progress then just wait for it to 1696 * complete and return. 1697 */ 1698 if (xfer->ux_hcflags & UXFER_ABORTING) { 1699 DPRINTFN(4, "already aborting", 0, 0, 0, 0); 1700 #ifdef DIAGNOSTIC 1701 if (status == USBD_TIMEOUT) 1702 DPRINTFN(4, "TIMEOUT while aborting", 0, 0, 0, 0); 1703 #endif 1704 /* Override the status which might be USBD_TIMEOUT. */ 1705 xfer->ux_status = status; 1706 DPRINTFN(4, "xfer %#jx waiting for abort to finish", 1707 (uintptr_t)xfer, 0, 0, 0); 1708 xfer->ux_hcflags |= UXFER_ABORTWAIT; 1709 while (xfer->ux_hcflags & UXFER_ABORTING) 1710 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 1711 return; 1712 } 1713 xfer->ux_hcflags |= UXFER_ABORTING; 1714 1715 /* 1716 * Step 1: Stop xfer timeout timer. 1717 */ 1718 xfer->ux_status = status; 1719 callout_stop(&xfer->ux_callout); 1720 1721 /* 1722 * Step 2: Stop execution of TD on the ring. 1723 */ 1724 switch (xhci_get_epstate(sc, xs, dci)) { 1725 case XHCI_EPSTATE_HALTED: 1726 (void)xhci_reset_endpoint_locked(xfer->ux_pipe); 1727 break; 1728 case XHCI_EPSTATE_STOPPED: 1729 break; 1730 default: 1731 (void)xhci_stop_endpoint(xfer->ux_pipe); 1732 break; 1733 } 1734 #ifdef DIAGNOSTIC 1735 uint32_t epst = xhci_get_epstate(sc, xs, dci); 1736 if (epst != XHCI_EPSTATE_STOPPED) 1737 DPRINTFN(4, "dci %ju not stopped %ju", dci, epst, 0, 0); 1738 #endif 1739 1740 /* 1741 * Step 3: Remove any vestiges of the xfer from the ring. 1742 */ 1743 xhci_set_dequeue_locked(xfer->ux_pipe); 1744 1745 /* 1746 * Step 4: Notify completion to waiting xfers. 1747 */ 1748 int wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 1749 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 1750 usb_transfer_complete(xfer); 1751 if (wake) { 1752 cv_broadcast(&xfer->ux_hccv); 1753 } 1754 DPRINTFN(14, "end", 0, 0, 0, 0); 1755 1756 KASSERT(mutex_owned(&sc->sc_lock)); 1757 } 1758 1759 static void 1760 xhci_host_dequeue(struct xhci_ring * const xr) 1761 { 1762 /* When dequeueing the controller, update our struct copy too */ 1763 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1764 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1765 BUS_DMASYNC_PREWRITE); 1766 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1767 1768 xr->xr_ep = 0; 1769 xr->xr_cs = 1; 1770 } 1771 1772 /* 1773 * Recover STALLed endpoint. 1774 * xHCI 1.1 sect 4.10.2.1 1775 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1776 * all transfers on transfer ring. 1777 * These are done in thread context asynchronously. 1778 */ 1779 static void 1780 xhci_clear_endpoint_stall_async_task(void *cookie) 1781 { 1782 struct usbd_xfer * const xfer = cookie; 1783 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1784 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1785 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1786 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1787 1788 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1789 DPRINTFN(4, "xfer %#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, 1790 dci, 0); 1791 1792 xhci_reset_endpoint(xfer->ux_pipe); 1793 xhci_set_dequeue(xfer->ux_pipe); 1794 1795 mutex_enter(&sc->sc_lock); 1796 tr->is_halted = false; 1797 usb_transfer_complete(xfer); 1798 mutex_exit(&sc->sc_lock); 1799 DPRINTFN(4, "ends", 0, 0, 0, 0); 1800 } 1801 1802 static usbd_status 1803 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1804 { 1805 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1806 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1807 1808 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1809 DPRINTFN(4, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 1810 1811 if (sc->sc_dying) { 1812 return USBD_IOERROR; 1813 } 1814 1815 usb_init_task(&xp->xp_async_task, 1816 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1817 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1818 DPRINTFN(4, "ends", 0, 0, 0, 0); 1819 1820 return USBD_NORMAL_COMPLETION; 1821 } 1822 1823 /* Process roothub port status/change events and notify to uhub_intr. */ 1824 static void 1825 xhci_rhpsc(struct xhci_softc * const sc, u_int ctlrport) 1826 { 1827 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1828 DPRINTFN(4, "xhci%jd: port %ju status change", device_unit(sc->sc_dev), 1829 ctlrport, 0, 0); 1830 1831 if (ctlrport > sc->sc_maxports) 1832 return; 1833 1834 const size_t bn = xhci_ctlrport2bus(sc, ctlrport); 1835 const size_t rhp = xhci_ctlrport2rhport(sc, ctlrport); 1836 struct usbd_xfer * const xfer = sc->sc_intrxfer[bn]; 1837 1838 DPRINTFN(4, "xhci%jd: bus %jd bp %ju xfer %#jx status change", 1839 device_unit(sc->sc_dev), bn, rhp, (uintptr_t)xfer); 1840 1841 if (xfer == NULL) 1842 return; 1843 1844 uint8_t *p = xfer->ux_buf; 1845 memset(p, 0, xfer->ux_length); 1846 p[rhp / NBBY] |= 1 << (rhp % NBBY); 1847 xfer->ux_actlen = xfer->ux_length; 1848 xfer->ux_status = USBD_NORMAL_COMPLETION; 1849 usb_transfer_complete(xfer); 1850 } 1851 1852 /* Process Transfer Events */ 1853 static void 1854 xhci_event_transfer(struct xhci_softc * const sc, 1855 const struct xhci_trb * const trb) 1856 { 1857 uint64_t trb_0; 1858 uint32_t trb_2, trb_3; 1859 uint8_t trbcode; 1860 u_int slot, dci; 1861 struct xhci_slot *xs; 1862 struct xhci_ring *xr; 1863 struct xhci_xfer *xx; 1864 struct usbd_xfer *xfer; 1865 usbd_status err; 1866 1867 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1868 1869 trb_0 = le64toh(trb->trb_0); 1870 trb_2 = le32toh(trb->trb_2); 1871 trb_3 = le32toh(trb->trb_3); 1872 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1873 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1874 dci = XHCI_TRB_3_EP_GET(trb_3); 1875 xs = &sc->sc_slots[slot]; 1876 xr = &xs->xs_ep[dci].xe_tr; 1877 1878 /* sanity check */ 1879 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1880 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1881 1882 int idx = 0; 1883 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1884 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1885 DPRINTFN(0, "invalid trb_0 0x%jx", trb_0, 0, 0, 0); 1886 return; 1887 } 1888 xx = xr->xr_cookies[idx]; 1889 1890 /* clear cookie of consumed TRB */ 1891 xr->xr_cookies[idx] = NULL; 1892 1893 /* 1894 * xx is NULL if pipe is opened but xfer is not started. 1895 * It happens when stopping idle pipe. 1896 */ 1897 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1898 DPRINTFN(1, "Ignore #%ju: cookie %#jx cc %ju dci %ju", 1899 idx, (uintptr_t)xx, trbcode, dci); 1900 DPRINTFN(1, " orig TRB %jx type %ju", trb_0, 1901 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1902 0, 0); 1903 return; 1904 } 1905 } else { 1906 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1907 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1908 } 1909 /* XXX this may not happen */ 1910 if (xx == NULL) { 1911 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1912 return; 1913 } 1914 xfer = &xx->xx_xfer; 1915 /* XXX this may happen when detaching */ 1916 if (xfer == NULL) { 1917 DPRINTFN(1, "xx(%#jx)->xx_xfer is NULL trb_0 %#jx", 1918 (uintptr_t)xx, trb_0, 0, 0); 1919 return; 1920 } 1921 DPRINTFN(14, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 1922 /* XXX I dunno why this happens */ 1923 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1924 1925 if (!xfer->ux_pipe->up_repeat && 1926 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1927 DPRINTFN(1, "xfer(%#jx)->pipe not queued", (uintptr_t)xfer, 1928 0, 0, 0); 1929 return; 1930 } 1931 1932 /* 4.11.5.2 Event Data TRB */ 1933 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1934 DPRINTFN(14, "transfer Event Data: 0x%016jx 0x%08jx" 1935 " %02jx", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1936 if ((trb_0 & 0x3) == 0x3) { 1937 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1938 } 1939 } 1940 1941 switch (trbcode) { 1942 case XHCI_TRB_ERROR_SHORT_PKT: 1943 case XHCI_TRB_ERROR_SUCCESS: 1944 /* 1945 * A ctrl transfer can generate two events if it has a Data 1946 * stage. A short data stage can be OK and should not 1947 * complete the transfer as the status stage needs to be 1948 * performed. 1949 * 1950 * Note: Data and Status stage events point at same xfer. 1951 * ux_actlen and ux_dmabuf will be passed to 1952 * usb_transfer_complete after the Status stage event. 1953 * 1954 * It can be distingished which stage generates the event: 1955 * + by checking least 3 bits of trb_0 if ED==1. 1956 * (see xhci_device_ctrl_start). 1957 * + by checking the type of original TRB if ED==0. 1958 * 1959 * In addition, intr, bulk, and isoc transfer currently 1960 * consists of single TD, so the "skip" is not needed. 1961 * ctrl xfer uses EVENT_DATA, and others do not. 1962 * Thus driver can switch the flow by checking ED bit. 1963 */ 1964 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1965 if (xfer->ux_actlen == 0) 1966 xfer->ux_actlen = xfer->ux_length - 1967 XHCI_TRB_2_REM_GET(trb_2); 1968 if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)) 1969 == XHCI_TRB_TYPE_DATA_STAGE) { 1970 return; 1971 } 1972 } else if ((trb_0 & 0x3) == 0x3) { 1973 return; 1974 } 1975 err = USBD_NORMAL_COMPLETION; 1976 break; 1977 case XHCI_TRB_ERROR_STOPPED: 1978 case XHCI_TRB_ERROR_LENGTH: 1979 case XHCI_TRB_ERROR_STOPPED_SHORT: 1980 /* 1981 * don't complete the transfer being aborted 1982 * as abort_xfer does instead. 1983 */ 1984 if (xfer->ux_hcflags & UXFER_ABORTING) { 1985 DPRINTFN(14, "ignore aborting xfer %#jx", 1986 (uintptr_t)xfer, 0, 0, 0); 1987 return; 1988 } 1989 err = USBD_CANCELLED; 1990 break; 1991 case XHCI_TRB_ERROR_STALL: 1992 case XHCI_TRB_ERROR_BABBLE: 1993 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 1994 xr->is_halted = true; 1995 err = USBD_STALLED; 1996 /* 1997 * Stalled endpoints can be recoverd by issuing 1998 * command TRB TYPE_RESET_EP on xHCI instead of 1999 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 2000 * on the endpoint. However, this function may be 2001 * called from softint context (e.g. from umass), 2002 * in that case driver gets KASSERT in cv_timedwait 2003 * in xhci_do_command. 2004 * To avoid this, this runs reset_endpoint and 2005 * usb_transfer_complete in usb task thread 2006 * asynchronously (and then umass issues clear 2007 * UF_ENDPOINT_HALT). 2008 */ 2009 xfer->ux_status = err; 2010 callout_stop(&xfer->ux_callout); 2011 xhci_clear_endpoint_stall_async(xfer); 2012 return; 2013 default: 2014 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 2015 err = USBD_IOERROR; 2016 break; 2017 } 2018 xfer->ux_status = err; 2019 2020 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 2021 if ((trb_0 & 0x3) == 0x0) { 2022 callout_stop(&xfer->ux_callout); 2023 usb_transfer_complete(xfer); 2024 } 2025 } else { 2026 callout_stop(&xfer->ux_callout); 2027 usb_transfer_complete(xfer); 2028 } 2029 } 2030 2031 /* Process Command complete events */ 2032 static void 2033 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 2034 { 2035 uint64_t trb_0; 2036 uint32_t trb_2, trb_3; 2037 2038 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2039 2040 KASSERT(mutex_owned(&sc->sc_lock)); 2041 2042 trb_0 = le64toh(trb->trb_0); 2043 trb_2 = le32toh(trb->trb_2); 2044 trb_3 = le32toh(trb->trb_3); 2045 2046 if (trb_0 == sc->sc_command_addr) { 2047 sc->sc_resultpending = false; 2048 2049 sc->sc_result_trb.trb_0 = trb_0; 2050 sc->sc_result_trb.trb_2 = trb_2; 2051 sc->sc_result_trb.trb_3 = trb_3; 2052 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2053 XHCI_TRB_ERROR_SUCCESS) { 2054 DPRINTFN(1, "command completion " 2055 "failure: 0x%016jx 0x%08jx 0x%08jx", 2056 trb_0, trb_2, trb_3, 0); 2057 } 2058 cv_signal(&sc->sc_command_cv); 2059 } else { 2060 DPRINTFN(1, "spurious event: %#jx 0x%016jx " 2061 "0x%08jx 0x%08jx", (uintptr_t)trb, trb_0, trb_2, trb_3); 2062 } 2063 } 2064 2065 /* 2066 * Process events. 2067 * called from xhci_softintr 2068 */ 2069 static void 2070 xhci_handle_event(struct xhci_softc * const sc, 2071 const struct xhci_trb * const trb) 2072 { 2073 uint64_t trb_0; 2074 uint32_t trb_2, trb_3; 2075 2076 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2077 2078 trb_0 = le64toh(trb->trb_0); 2079 trb_2 = le32toh(trb->trb_2); 2080 trb_3 = le32toh(trb->trb_3); 2081 2082 DPRINTFN(14, "event: %#jx 0x%016jx 0x%08jx 0x%08jx", 2083 (uintptr_t)trb, trb_0, trb_2, trb_3); 2084 2085 /* 2086 * 4.11.3.1, 6.4.2.1 2087 * TRB Pointer is invalid for these completion codes. 2088 */ 2089 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2090 case XHCI_TRB_ERROR_RING_UNDERRUN: 2091 case XHCI_TRB_ERROR_RING_OVERRUN: 2092 case XHCI_TRB_ERROR_VF_RING_FULL: 2093 return; 2094 default: 2095 if (trb_0 == 0) { 2096 return; 2097 } 2098 break; 2099 } 2100 2101 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2102 case XHCI_TRB_EVENT_TRANSFER: 2103 xhci_event_transfer(sc, trb); 2104 break; 2105 case XHCI_TRB_EVENT_CMD_COMPLETE: 2106 xhci_event_cmd(sc, trb); 2107 break; 2108 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2109 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2110 break; 2111 default: 2112 break; 2113 } 2114 } 2115 2116 static void 2117 xhci_softintr(void *v) 2118 { 2119 struct usbd_bus * const bus = v; 2120 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2121 struct xhci_ring * const er = &sc->sc_er; 2122 struct xhci_trb *trb; 2123 int i, j, k; 2124 2125 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2126 2127 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 2128 2129 i = er->xr_ep; 2130 j = er->xr_cs; 2131 2132 DPRINTFN(16, "er: xr_ep %jd xr_cs %jd", i, j, 0, 0); 2133 2134 while (1) { 2135 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2136 BUS_DMASYNC_POSTREAD); 2137 trb = &er->xr_trb[i]; 2138 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2139 2140 if (j != k) 2141 break; 2142 2143 xhci_handle_event(sc, trb); 2144 2145 i++; 2146 if (i == er->xr_ntrb) { 2147 i = 0; 2148 j ^= 1; 2149 } 2150 } 2151 2152 er->xr_ep = i; 2153 er->xr_cs = j; 2154 2155 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2156 XHCI_ERDP_LO_BUSY); 2157 2158 DPRINTFN(16, "ends", 0, 0, 0, 0); 2159 2160 return; 2161 } 2162 2163 static void 2164 xhci_poll(struct usbd_bus *bus) 2165 { 2166 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2167 2168 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2169 2170 mutex_spin_enter(&sc->sc_intr_lock); 2171 int ret = xhci_intr1(sc); 2172 if (ret) { 2173 xhci_softintr(bus); 2174 } 2175 mutex_spin_exit(&sc->sc_intr_lock); 2176 2177 return; 2178 } 2179 2180 static struct usbd_xfer * 2181 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2182 { 2183 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2184 struct usbd_xfer *xfer; 2185 2186 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2187 2188 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 2189 if (xfer != NULL) { 2190 memset(xfer, 0, sizeof(struct xhci_xfer)); 2191 #ifdef DIAGNOSTIC 2192 xfer->ux_state = XFER_BUSY; 2193 #endif 2194 } 2195 2196 return xfer; 2197 } 2198 2199 static void 2200 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2201 { 2202 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2203 2204 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2205 2206 #ifdef DIAGNOSTIC 2207 if (xfer->ux_state != XFER_BUSY) { 2208 DPRINTFN(0, "xfer=%#jx not busy, 0x%08jx", 2209 (uintptr_t)xfer, xfer->ux_state, 0, 0); 2210 } 2211 xfer->ux_state = XFER_FREE; 2212 #endif 2213 pool_cache_put(sc->sc_xferpool, xfer); 2214 } 2215 2216 static void 2217 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2218 { 2219 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2220 2221 *lock = &sc->sc_lock; 2222 } 2223 2224 extern uint32_t usb_cookie_no; 2225 2226 /* 2227 * xHCI 4.3 2228 * Called when uhub_explore finds a new device (via usbd_new_device). 2229 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2230 * This function does: 2231 * Allocate and construct dev structure of default endpoint (ep0). 2232 * Allocate and open pipe of ep0. 2233 * Enable slot and initialize slot context. 2234 * Set Address. 2235 * Read initial device descriptor. 2236 * Determine initial MaxPacketSize (mps) by speed. 2237 * Read full device descriptor. 2238 * Register this device. 2239 * Finally state of device transitions ADDRESSED. 2240 */ 2241 static usbd_status 2242 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2243 int speed, int port, struct usbd_port *up) 2244 { 2245 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2246 struct usbd_device *dev; 2247 usbd_status err; 2248 usb_device_descriptor_t *dd; 2249 struct xhci_slot *xs; 2250 uint32_t *cp; 2251 2252 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2253 DPRINTFN(4, "port %ju depth %ju speed %ju up %#jx", 2254 port, depth, speed, (uintptr_t)up); 2255 2256 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2257 dev->ud_bus = bus; 2258 dev->ud_quirks = &usbd_no_quirk; 2259 dev->ud_addr = 0; 2260 dev->ud_ddesc.bMaxPacketSize = 0; 2261 dev->ud_depth = depth; 2262 dev->ud_powersrc = up; 2263 dev->ud_myhub = up->up_parent; 2264 dev->ud_speed = speed; 2265 dev->ud_langid = USBD_NOLANG; 2266 dev->ud_cookie.cookie = ++usb_cookie_no; 2267 2268 /* Set up default endpoint handle. */ 2269 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2270 /* doesn't matter, just don't let it uninitialized */ 2271 dev->ud_ep0.ue_toggle = 0; 2272 2273 /* Set up default endpoint descriptor. */ 2274 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2275 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2276 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2277 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2278 dev->ud_ep0desc.bInterval = 0; 2279 2280 /* 4.3, 4.8.2.1 */ 2281 switch (speed) { 2282 case USB_SPEED_SUPER: 2283 case USB_SPEED_SUPER_PLUS: 2284 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2285 break; 2286 case USB_SPEED_FULL: 2287 /* XXX using 64 as initial mps of ep0 in FS */ 2288 case USB_SPEED_HIGH: 2289 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2290 break; 2291 case USB_SPEED_LOW: 2292 default: 2293 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2294 break; 2295 } 2296 2297 up->up_dev = dev; 2298 2299 /* Establish the default pipe. */ 2300 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2301 &dev->ud_pipe0); 2302 if (err) { 2303 goto bad; 2304 } 2305 2306 dd = &dev->ud_ddesc; 2307 2308 if (depth == 0 && port == 0) { 2309 KASSERT(bus->ub_devices[USB_ROOTHUB_INDEX] == NULL); 2310 bus->ub_devices[USB_ROOTHUB_INDEX] = dev; 2311 err = usbd_get_initial_ddesc(dev, dd); 2312 if (err) { 2313 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2314 goto bad; 2315 } 2316 2317 err = usbd_reload_device_desc(dev); 2318 if (err) { 2319 DPRINTFN(1, "reload desc %ju", err, 0, 0, 0); 2320 goto bad; 2321 } 2322 } else { 2323 uint8_t slot = 0; 2324 2325 /* 4.3.2 */ 2326 err = xhci_enable_slot(sc, &slot); 2327 if (err) { 2328 DPRINTFN(1, "enable slot %ju", err, 0, 0, 0); 2329 goto bad; 2330 } 2331 2332 xs = &sc->sc_slots[slot]; 2333 dev->ud_hcpriv = xs; 2334 2335 /* 4.3.3 initialize slot structure */ 2336 err = xhci_init_slot(dev, slot); 2337 if (err) { 2338 DPRINTFN(1, "init slot %ju", err, 0, 0, 0); 2339 dev->ud_hcpriv = NULL; 2340 /* 2341 * We have to disable_slot here because 2342 * xs->xs_idx == 0 when xhci_init_slot fails, 2343 * in that case usbd_remove_dev won't work. 2344 */ 2345 mutex_enter(&sc->sc_lock); 2346 xhci_disable_slot(sc, slot); 2347 mutex_exit(&sc->sc_lock); 2348 goto bad; 2349 } 2350 2351 /* 4.3.4 Address Assignment */ 2352 err = xhci_set_address(dev, slot, false); 2353 if (err) { 2354 DPRINTFN(1, "set address w/o bsr %ju", err, 0, 0, 0); 2355 goto bad; 2356 } 2357 2358 /* Allow device time to set new address */ 2359 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2360 2361 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2362 //hexdump("slot context", cp, sc->sc_ctxsz); 2363 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3])); 2364 DPRINTFN(4, "device address %ju", addr, 0, 0, 0); 2365 /* 2366 * XXX ensure we know when the hardware does something 2367 * we can't yet cope with 2368 */ 2369 KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr); 2370 dev->ud_addr = addr; 2371 2372 KASSERTMSG(bus->ub_devices[usb_addr2dindex(dev->ud_addr)] == NULL, 2373 "addr %d already allocated", dev->ud_addr); 2374 /* 2375 * The root hub is given its own slot 2376 */ 2377 bus->ub_devices[usb_addr2dindex(dev->ud_addr)] = dev; 2378 2379 err = usbd_get_initial_ddesc(dev, dd); 2380 if (err) { 2381 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2382 goto bad; 2383 } 2384 2385 /* 4.8.2.1 */ 2386 if (USB_IS_SS(speed)) { 2387 if (dd->bMaxPacketSize != 9) { 2388 printf("%s: invalid mps 2^%u for SS ep0," 2389 " using 512\n", 2390 device_xname(sc->sc_dev), 2391 dd->bMaxPacketSize); 2392 dd->bMaxPacketSize = 9; 2393 } 2394 USETW(dev->ud_ep0desc.wMaxPacketSize, 2395 (1 << dd->bMaxPacketSize)); 2396 } else 2397 USETW(dev->ud_ep0desc.wMaxPacketSize, 2398 dd->bMaxPacketSize); 2399 DPRINTFN(4, "bMaxPacketSize %ju", dd->bMaxPacketSize, 0, 0, 0); 2400 err = xhci_update_ep0_mps(sc, xs, 2401 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2402 if (err) { 2403 DPRINTFN(1, "update mps of ep0 %ju", err, 0, 0, 0); 2404 goto bad; 2405 } 2406 2407 err = usbd_reload_device_desc(dev); 2408 if (err) { 2409 DPRINTFN(1, "reload desc %ju", err, 0, 0, 0); 2410 goto bad; 2411 } 2412 } 2413 2414 DPRINTFN(1, "adding unit addr=%jd, rev=%02jx,", 2415 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2416 DPRINTFN(1, " class=%jd, subclass=%jd, protocol=%jd,", 2417 dd->bDeviceClass, dd->bDeviceSubClass, 2418 dd->bDeviceProtocol, 0); 2419 DPRINTFN(1, " mps=%jd, len=%jd, noconf=%jd, speed=%jd", 2420 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2421 dev->ud_speed); 2422 2423 usbd_get_device_strings(dev); 2424 2425 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2426 2427 if (depth == 0 && port == 0) { 2428 usbd_attach_roothub(parent, dev); 2429 DPRINTFN(1, "root hub %#jx", (uintptr_t)dev, 0, 0, 0); 2430 return USBD_NORMAL_COMPLETION; 2431 } 2432 2433 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2434 bad: 2435 if (err != USBD_NORMAL_COMPLETION) { 2436 usbd_remove_device(dev, up); 2437 } 2438 2439 return err; 2440 } 2441 2442 static usbd_status 2443 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2444 size_t ntrb, size_t align) 2445 { 2446 usbd_status err; 2447 size_t size = ntrb * XHCI_TRB_SIZE; 2448 2449 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2450 2451 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2452 if (err) 2453 return err; 2454 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2455 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2456 xr->xr_trb = xhci_ring_trbv(xr, 0); 2457 xr->xr_ntrb = ntrb; 2458 xr->is_halted = false; 2459 xhci_host_dequeue(xr); 2460 2461 return USBD_NORMAL_COMPLETION; 2462 } 2463 2464 static void 2465 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2466 { 2467 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2468 mutex_destroy(&xr->xr_lock); 2469 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2470 } 2471 2472 static void 2473 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2474 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2475 { 2476 size_t i; 2477 u_int ri; 2478 u_int cs; 2479 uint64_t parameter; 2480 uint32_t status; 2481 uint32_t control; 2482 2483 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2484 2485 KASSERTMSG(ntrbs <= XHCI_XFER_NTRB, "ntrbs %zu", ntrbs); 2486 for (i = 0; i < ntrbs; i++) { 2487 DPRINTFN(12, "xr %#jx trbs %#jx num %ju", (uintptr_t)xr, 2488 (uintptr_t)trbs, i, 0); 2489 DPRINTFN(12, " %016jx %08jx %08jx", 2490 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2491 KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2492 XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3); 2493 } 2494 2495 DPRINTFN(12, "%#jx xr_ep 0x%jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep, 2496 xr->xr_cs, 0); 2497 2498 ri = xr->xr_ep; 2499 cs = xr->xr_cs; 2500 2501 /* 2502 * Although the xhci hardware can do scatter/gather dma from 2503 * arbitrary sized buffers, there is a non-obvious restriction 2504 * that a LINK trb is only allowed at the end of a burst of 2505 * transfers - which might be 16kB. 2506 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2507 * The simple solution is not to allow a LINK trb in the middle 2508 * of anything - as here. 2509 * XXX: (dsl) There are xhci controllers out there (eg some made by 2510 * ASMedia) that seem to lock up if they process a LINK trb but 2511 * cannot process the linked-to trb yet. 2512 * The code should write the 'cycle' bit on the link trb AFTER 2513 * adding the other trb. 2514 */ 2515 u_int firstep = xr->xr_ep; 2516 u_int firstcs = xr->xr_cs; 2517 2518 for (i = 0; i < ntrbs; ) { 2519 u_int oldri = ri; 2520 u_int oldcs = cs; 2521 2522 if (ri >= (xr->xr_ntrb - 1)) { 2523 /* Put Link TD at the end of ring */ 2524 parameter = xhci_ring_trbp(xr, 0); 2525 status = 0; 2526 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2527 XHCI_TRB_3_TC_BIT; 2528 xr->xr_cookies[ri] = NULL; 2529 xr->xr_ep = 0; 2530 xr->xr_cs ^= 1; 2531 ri = xr->xr_ep; 2532 cs = xr->xr_cs; 2533 } else { 2534 parameter = trbs[i].trb_0; 2535 status = trbs[i].trb_2; 2536 control = trbs[i].trb_3; 2537 2538 xr->xr_cookies[ri] = cookie; 2539 ri++; 2540 i++; 2541 } 2542 /* 2543 * If this is a first TRB, mark it invalid to prevent 2544 * xHC from running it immediately. 2545 */ 2546 if (oldri == firstep) { 2547 if (oldcs) { 2548 control &= ~XHCI_TRB_3_CYCLE_BIT; 2549 } else { 2550 control |= XHCI_TRB_3_CYCLE_BIT; 2551 } 2552 } else { 2553 if (oldcs) { 2554 control |= XHCI_TRB_3_CYCLE_BIT; 2555 } else { 2556 control &= ~XHCI_TRB_3_CYCLE_BIT; 2557 } 2558 } 2559 xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control); 2560 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri, 2561 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2562 } 2563 2564 /* Now invert cycle bit of first TRB */ 2565 if (firstcs) { 2566 xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 2567 } else { 2568 xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 2569 } 2570 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep, 2571 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2572 2573 xr->xr_ep = ri; 2574 xr->xr_cs = cs; 2575 2576 DPRINTFN(12, "%#jx xr_ep 0x%jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep, 2577 xr->xr_cs, 0); 2578 } 2579 2580 /* 2581 * Stop execution commands, purge all commands on command ring, and 2582 * rewind dequeue pointer. 2583 */ 2584 static void 2585 xhci_abort_command(struct xhci_softc *sc) 2586 { 2587 struct xhci_ring * const cr = &sc->sc_cr; 2588 uint64_t crcr; 2589 int i; 2590 2591 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2592 DPRINTFN(14, "command %#jx timeout, aborting", 2593 sc->sc_command_addr, 0, 0, 0); 2594 2595 mutex_enter(&cr->xr_lock); 2596 2597 /* 4.6.1.2 Aborting a Command */ 2598 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2599 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2600 2601 for (i = 0; i < 500; i++) { 2602 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2603 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2604 break; 2605 usb_delay_ms(&sc->sc_bus, 1); 2606 } 2607 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2608 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2609 /* reset HC here? */ 2610 } 2611 2612 /* reset command ring dequeue pointer */ 2613 cr->xr_ep = 0; 2614 cr->xr_cs = 1; 2615 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2616 2617 mutex_exit(&cr->xr_lock); 2618 } 2619 2620 /* 2621 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2622 * Command completion is notified by cv_signal from xhci_event_cmd() 2623 * (called from xhci_softint), or timed-out. 2624 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2625 * then do_command examines it. 2626 */ 2627 static usbd_status 2628 xhci_do_command_locked(struct xhci_softc * const sc, 2629 struct xhci_trb * const trb, int timeout) 2630 { 2631 struct xhci_ring * const cr = &sc->sc_cr; 2632 usbd_status err; 2633 2634 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2635 DPRINTFN(12, "input: 0x%016jx 0x%08jx 0x%08jx", 2636 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2637 2638 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2639 KASSERT(mutex_owned(&sc->sc_lock)); 2640 2641 while (sc->sc_command_addr != 0) 2642 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 2643 2644 /* 2645 * If enqueue pointer points at last of ring, it's Link TRB, 2646 * command TRB will be stored in 0th TRB. 2647 */ 2648 if (cr->xr_ep == cr->xr_ntrb - 1) 2649 sc->sc_command_addr = xhci_ring_trbp(cr, 0); 2650 else 2651 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2652 2653 sc->sc_resultpending = true; 2654 2655 mutex_enter(&cr->xr_lock); 2656 xhci_ring_put(sc, cr, NULL, trb, 1); 2657 mutex_exit(&cr->xr_lock); 2658 2659 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2660 2661 while (sc->sc_resultpending) { 2662 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2663 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2664 xhci_abort_command(sc); 2665 err = USBD_TIMEOUT; 2666 goto timedout; 2667 } 2668 } 2669 2670 trb->trb_0 = sc->sc_result_trb.trb_0; 2671 trb->trb_2 = sc->sc_result_trb.trb_2; 2672 trb->trb_3 = sc->sc_result_trb.trb_3; 2673 2674 DPRINTFN(12, "output: 0x%016jx 0x%08jx 0x%08jx", 2675 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2676 2677 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2678 case XHCI_TRB_ERROR_SUCCESS: 2679 err = USBD_NORMAL_COMPLETION; 2680 break; 2681 default: 2682 case 192 ... 223: 2683 err = USBD_IOERROR; 2684 break; 2685 case 224 ... 255: 2686 err = USBD_NORMAL_COMPLETION; 2687 break; 2688 } 2689 2690 timedout: 2691 sc->sc_resultpending = false; 2692 sc->sc_command_addr = 0; 2693 cv_broadcast(&sc->sc_cmdbusy_cv); 2694 2695 return err; 2696 } 2697 2698 static usbd_status 2699 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2700 int timeout) 2701 { 2702 2703 mutex_enter(&sc->sc_lock); 2704 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2705 mutex_exit(&sc->sc_lock); 2706 2707 return ret; 2708 } 2709 2710 static usbd_status 2711 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2712 { 2713 struct xhci_trb trb; 2714 usbd_status err; 2715 2716 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2717 2718 trb.trb_0 = 0; 2719 trb.trb_2 = 0; 2720 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2721 2722 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2723 if (err != USBD_NORMAL_COMPLETION) { 2724 return err; 2725 } 2726 2727 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2728 2729 return err; 2730 } 2731 2732 /* 2733 * xHCI 4.6.4 2734 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2735 * All endpoints in the slot should be stopped. 2736 * Should be called with sc_lock held. 2737 */ 2738 static usbd_status 2739 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2740 { 2741 struct xhci_trb trb; 2742 struct xhci_slot *xs; 2743 usbd_status err; 2744 2745 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2746 2747 if (sc->sc_dying) 2748 return USBD_IOERROR; 2749 2750 trb.trb_0 = 0; 2751 trb.trb_2 = 0; 2752 trb.trb_3 = htole32( 2753 XHCI_TRB_3_SLOT_SET(slot) | 2754 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2755 2756 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2757 2758 if (!err) { 2759 xs = &sc->sc_slots[slot]; 2760 if (xs->xs_idx != 0) { 2761 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2762 xhci_set_dcba(sc, 0, slot); 2763 memset(xs, 0, sizeof(*xs)); 2764 } 2765 } 2766 2767 return err; 2768 } 2769 2770 /* 2771 * Set address of device and transition slot state from ENABLED to ADDRESSED 2772 * if Block Setaddress Request (BSR) is false. 2773 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2774 * see xHCI 1.1 4.5.3, 3.3.4 2775 * Should be called without sc_lock held. 2776 */ 2777 static usbd_status 2778 xhci_address_device(struct xhci_softc * const sc, 2779 uint64_t icp, uint8_t slot_id, bool bsr) 2780 { 2781 struct xhci_trb trb; 2782 usbd_status err; 2783 2784 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2785 2786 trb.trb_0 = icp; 2787 trb.trb_2 = 0; 2788 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2789 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2790 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2791 2792 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2793 2794 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2795 err = USBD_NO_ADDR; 2796 2797 return err; 2798 } 2799 2800 static usbd_status 2801 xhci_update_ep0_mps(struct xhci_softc * const sc, 2802 struct xhci_slot * const xs, u_int mps) 2803 { 2804 struct xhci_trb trb; 2805 usbd_status err; 2806 uint32_t * cp; 2807 2808 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2809 DPRINTFN(4, "slot %ju mps %ju", xs->xs_idx, mps, 0, 0); 2810 2811 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2812 cp[0] = htole32(0); 2813 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2814 2815 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2816 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2817 2818 /* sync input contexts before they are read from memory */ 2819 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2820 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2821 sc->sc_ctxsz * 4); 2822 2823 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2824 trb.trb_2 = 0; 2825 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2826 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2827 2828 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2829 return err; 2830 } 2831 2832 static void 2833 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2834 { 2835 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2836 2837 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2838 DPRINTFN(4, "dcbaa %#jx dc %016jx slot %jd", 2839 (uintptr_t)&dcbaa[si], dcba, si, 0); 2840 2841 dcbaa[si] = htole64(dcba); 2842 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2843 BUS_DMASYNC_PREWRITE); 2844 } 2845 2846 /* 2847 * Allocate device and input context DMA buffer, and 2848 * TRB DMA buffer for each endpoint. 2849 */ 2850 static usbd_status 2851 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2852 { 2853 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2854 struct xhci_slot *xs; 2855 usbd_status err; 2856 u_int dci; 2857 2858 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2859 DPRINTFN(4, "slot %ju", slot, 0, 0, 0); 2860 2861 xs = &sc->sc_slots[slot]; 2862 2863 /* allocate contexts */ 2864 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2865 &xs->xs_dc_dma); 2866 if (err) 2867 return err; 2868 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2869 2870 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2871 &xs->xs_ic_dma); 2872 if (err) 2873 goto bad1; 2874 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2875 2876 for (dci = 0; dci < 32; dci++) { 2877 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2878 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2879 if (dci == XHCI_DCI_SLOT) 2880 continue; 2881 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2882 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2883 if (err) { 2884 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2885 goto bad2; 2886 } 2887 } 2888 2889 bad2: 2890 if (err == USBD_NORMAL_COMPLETION) { 2891 xs->xs_idx = slot; 2892 } else { 2893 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2894 } 2895 2896 return err; 2897 2898 bad1: 2899 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2900 xs->xs_idx = 0; 2901 return err; 2902 } 2903 2904 static void 2905 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2906 int end_dci) 2907 { 2908 u_int dci; 2909 2910 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2911 DPRINTFN(4, "slot %ju start %ju end %ju", xs->xs_idx, start_dci, 2912 end_dci, 0); 2913 2914 for (dci = start_dci; dci < end_dci; dci++) { 2915 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2916 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2917 } 2918 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2919 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2920 xs->xs_idx = 0; 2921 } 2922 2923 /* 2924 * Setup slot context, set Device Context Base Address, and issue 2925 * Set Address Device command. 2926 */ 2927 static usbd_status 2928 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 2929 { 2930 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2931 struct xhci_slot *xs; 2932 usbd_status err; 2933 2934 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2935 DPRINTFN(4, "slot %ju bsr %ju", slot, bsr, 0, 0); 2936 2937 xs = &sc->sc_slots[slot]; 2938 2939 xhci_setup_ctx(dev->ud_pipe0); 2940 2941 hexdump("input context", xhci_slot_get_icv(sc, xs, 0), 2942 sc->sc_ctxsz * 3); 2943 2944 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2945 2946 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 2947 2948 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2949 hexdump("output context", xhci_slot_get_dcv(sc, xs, 0), 2950 sc->sc_ctxsz * 2); 2951 2952 return err; 2953 } 2954 2955 /* 2956 * 4.8.2, 6.2.3.2 2957 * construct slot/endpoint context parameters and do syncmem 2958 */ 2959 static void 2960 xhci_setup_ctx(struct usbd_pipe *pipe) 2961 { 2962 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2963 struct usbd_device *dev = pipe->up_dev; 2964 struct xhci_slot * const xs = dev->ud_hcpriv; 2965 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2966 const u_int dci = xhci_ep_get_dci(ed); 2967 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2968 uint32_t *cp; 2969 uint16_t mps = UGETW(ed->wMaxPacketSize); 2970 uint8_t speed = dev->ud_speed; 2971 uint8_t ival = ed->bInterval; 2972 2973 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2974 DPRINTFN(4, "pipe %#jx: slot %ju dci %ju speed %ju", 2975 (uintptr_t)pipe, xs->xs_idx, dci, speed); 2976 2977 /* set up initial input control context */ 2978 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2979 cp[0] = htole32(0); 2980 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 2981 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2982 cp[7] = htole32(0); 2983 2984 /* set up input slot context */ 2985 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2986 cp[0] = 2987 XHCI_SCTX_0_CTX_NUM_SET(dci) | 2988 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 2989 cp[1] = 0; 2990 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2991 cp[3] = 0; 2992 xhci_setup_route(pipe, cp); 2993 xhci_setup_tthub(pipe, cp); 2994 2995 cp[0] = htole32(cp[0]); 2996 cp[1] = htole32(cp[1]); 2997 cp[2] = htole32(cp[2]); 2998 cp[3] = htole32(cp[3]); 2999 3000 /* set up input endpoint context */ 3001 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 3002 cp[0] = 3003 XHCI_EPCTX_0_EPSTATE_SET(0) | 3004 XHCI_EPCTX_0_MULT_SET(0) | 3005 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 3006 XHCI_EPCTX_0_LSA_SET(0) | 3007 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 3008 cp[1] = 3009 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 3010 XHCI_EPCTX_1_HID_SET(0) | 3011 XHCI_EPCTX_1_MAXB_SET(0); 3012 3013 if (xfertype != UE_ISOCHRONOUS) 3014 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 3015 3016 if (xfertype == UE_CONTROL) 3017 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 3018 else if (USB_IS_SS(speed)) 3019 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 3020 else 3021 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 3022 3023 xhci_setup_maxburst(pipe, cp); 3024 3025 switch (xfertype) { 3026 case UE_CONTROL: 3027 break; 3028 case UE_BULK: 3029 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 3030 break; 3031 case UE_INTERRUPT: 3032 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3033 ival = pipe->up_interval; 3034 3035 ival = xhci_bival2ival(ival, speed); 3036 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3037 break; 3038 case UE_ISOCHRONOUS: 3039 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3040 ival = pipe->up_interval; 3041 3042 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 3043 if (speed == USB_SPEED_FULL) 3044 ival += 3; /* 1ms -> 125us */ 3045 ival--; 3046 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3047 break; 3048 default: 3049 break; 3050 } 3051 DPRINTFN(4, "setting ival %ju MaxBurst %#jx", 3052 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 3053 3054 /* rewind TR dequeue pointer in xHC */ 3055 /* can't use xhci_ep_get_dci() yet? */ 3056 *(uint64_t *)(&cp[2]) = htole64( 3057 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 3058 XHCI_EPCTX_2_DCS_SET(1)); 3059 3060 cp[0] = htole32(cp[0]); 3061 cp[1] = htole32(cp[1]); 3062 cp[4] = htole32(cp[4]); 3063 3064 /* rewind TR dequeue pointer in driver */ 3065 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 3066 mutex_enter(&xr->xr_lock); 3067 xhci_host_dequeue(xr); 3068 mutex_exit(&xr->xr_lock); 3069 3070 /* sync input contexts before they are read from memory */ 3071 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3072 } 3073 3074 /* 3075 * Setup route string and roothub port of given device for slot context 3076 */ 3077 static void 3078 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 3079 { 3080 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3081 struct usbd_device *dev = pipe->up_dev; 3082 struct usbd_port *up = dev->ud_powersrc; 3083 struct usbd_device *hub; 3084 struct usbd_device *adev; 3085 uint8_t rhport = 0; 3086 uint32_t route = 0; 3087 3088 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3089 3090 /* Locate root hub port and Determine route string */ 3091 /* 4.3.3 route string does not include roothub port */ 3092 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 3093 uint32_t dep; 3094 3095 DPRINTFN(4, "hub %#jx depth %jd upport %jp upportno %jd", 3096 (uintptr_t)hub, hub->ud_depth, (uintptr_t)hub->ud_powersrc, 3097 hub->ud_powersrc ? (uintptr_t)hub->ud_powersrc->up_portno : 3098 -1); 3099 3100 if (hub->ud_powersrc == NULL) 3101 break; 3102 dep = hub->ud_depth; 3103 if (dep == 0) 3104 break; 3105 rhport = hub->ud_powersrc->up_portno; 3106 if (dep > USB_HUB_MAX_DEPTH) 3107 continue; 3108 3109 route |= 3110 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 3111 << ((dep - 1) * 4); 3112 } 3113 route = route >> 4; 3114 size_t bn = hub == sc->sc_bus.ub_roothub ? 0 : 1; 3115 3116 /* Locate port on upstream high speed hub */ 3117 for (adev = dev, hub = up->up_parent; 3118 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 3119 adev = hub, hub = hub->ud_myhub) 3120 ; 3121 if (hub) { 3122 int p; 3123 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 3124 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 3125 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 3126 goto found; 3127 } 3128 } 3129 panic("%s: cannot find HS port", __func__); 3130 found: 3131 DPRINTFN(4, "high speed port %jd", p, 0, 0, 0); 3132 } else { 3133 dev->ud_myhsport = NULL; 3134 } 3135 3136 const size_t ctlrport = xhci_rhport2ctlrport(sc, bn, rhport); 3137 3138 DPRINTFN(4, "rhport %ju ctlrport %ju Route %05jx hub %#jx", rhport, 3139 ctlrport, route, (uintptr_t)hub); 3140 3141 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 3142 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(ctlrport); 3143 } 3144 3145 /* 3146 * Setup whether device is hub, whether device uses MTT, and 3147 * TT informations if it uses MTT. 3148 */ 3149 static void 3150 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 3151 { 3152 struct usbd_device *dev = pipe->up_dev; 3153 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 3154 uint32_t speed = dev->ud_speed; 3155 uint8_t tthubslot, ttportnum; 3156 bool ishub; 3157 bool usemtt; 3158 3159 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3160 3161 /* 3162 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 3163 * tthubslot: 3164 * This is the slot ID of parent HS hub 3165 * if LS/FS device is connected && connected through HS hub. 3166 * This is 0 if device is not LS/FS device || 3167 * parent hub is not HS hub || 3168 * attached to root hub. 3169 * ttportnum: 3170 * This is the downstream facing port of parent HS hub 3171 * if LS/FS device is connected. 3172 * This is 0 if device is not LS/FS device || 3173 * parent hub is not HS hub || 3174 * attached to root hub. 3175 */ 3176 if (dev->ud_myhsport != NULL && 3177 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3178 (dev->ud_myhub != NULL && 3179 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3180 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 3181 ttportnum = dev->ud_myhsport->up_portno; 3182 tthubslot = dev->ud_myhsport->up_parent->ud_addr; 3183 } else { 3184 ttportnum = 0; 3185 tthubslot = 0; 3186 } 3187 DPRINTFN(4, "myhsport %#jx ttportnum=%jd tthubslot=%jd", 3188 (uintptr_t)dev->ud_myhsport, ttportnum, tthubslot, 0); 3189 3190 /* ishub is valid after reading UDESC_DEVICE */ 3191 ishub = (dd->bDeviceClass == UDCLASS_HUB); 3192 3193 /* dev->ud_hub is valid after reading UDESC_HUB */ 3194 if (ishub && dev->ud_hub) { 3195 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 3196 uint8_t ttt = 3197 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 3198 3199 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 3200 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 3201 DPRINTFN(4, "nports=%jd ttt=%jd", hd->bNbrPorts, ttt, 0, 0); 3202 } 3203 3204 #define IS_TTHUB(dd) \ 3205 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 3206 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 3207 3208 /* 3209 * MTT flag is set if 3210 * 1. this is HS hub && MTT is enabled 3211 * or 3212 * 2. this is not hub && this is LS or FS device && 3213 * MTT of parent HS hub (and its parent, too) is enabled 3214 */ 3215 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 3216 usemtt = true; 3217 else if (!ishub && 3218 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 3219 dev->ud_myhub != NULL && dev->ud_myhub->ud_depth != 0 && 3220 (dev->ud_myhub != NULL && 3221 dev->ud_myhub->ud_speed == USB_SPEED_HIGH) && 3222 dev->ud_myhsport != NULL && 3223 IS_TTHUB(&dev->ud_myhsport->up_parent->ud_ddesc)) 3224 usemtt = true; 3225 else 3226 usemtt = false; 3227 DPRINTFN(4, "class %ju proto %ju ishub %jd usemtt %jd", 3228 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 3229 3230 #undef IS_TTHUB 3231 3232 cp[0] |= 3233 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 3234 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 3235 cp[2] |= 3236 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 3237 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 3238 } 3239 3240 /* set up params for periodic endpoint */ 3241 static void 3242 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 3243 { 3244 struct usbd_device *dev = pipe->up_dev; 3245 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3246 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3247 usbd_desc_iter_t iter; 3248 const usb_cdc_descriptor_t *cdcd; 3249 uint32_t maxb = 0; 3250 uint16_t mps = UGETW(ed->wMaxPacketSize); 3251 uint8_t speed = dev->ud_speed; 3252 uint8_t ep; 3253 3254 /* config desc is NULL when opening ep0 */ 3255 if (dev == NULL || dev->ud_cdesc == NULL) 3256 goto no_cdcd; 3257 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 3258 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 3259 if (cdcd == NULL) 3260 goto no_cdcd; 3261 usb_desc_iter_init(dev, &iter); 3262 iter.cur = (const void *)cdcd; 3263 3264 /* find endpoint_ss_comp desc for ep of this pipe */ 3265 for (ep = 0;;) { 3266 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 3267 if (cdcd == NULL) 3268 break; 3269 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 3270 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 3271 bEndpointAddress; 3272 if (UE_GET_ADDR(ep) == 3273 UE_GET_ADDR(ed->bEndpointAddress)) { 3274 cdcd = (const usb_cdc_descriptor_t *) 3275 usb_desc_iter_next(&iter); 3276 break; 3277 } 3278 ep = 0; 3279 } 3280 } 3281 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 3282 const usb_endpoint_ss_comp_descriptor_t * esscd = 3283 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3284 maxb = esscd->bMaxBurst; 3285 } 3286 3287 no_cdcd: 3288 /* 6.2.3.4, 4.8.2.4 */ 3289 if (USB_IS_SS(speed)) { 3290 /* USB 3.1 9.6.6 */ 3291 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3292 /* USB 3.1 9.6.7 */ 3293 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3294 #ifdef notyet 3295 if (xfertype == UE_ISOCHRONOUS) { 3296 } 3297 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3298 /* use ESIT */ 3299 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3300 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3301 3302 /* XXX if LEC = 1, set ESIT instead */ 3303 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3304 } else { 3305 /* use ival */ 3306 } 3307 #endif 3308 } else { 3309 /* USB 2.0 9.6.6 */ 3310 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3311 3312 /* 6.2.3.4 */ 3313 if (speed == USB_SPEED_HIGH && 3314 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3315 maxb = UE_GET_TRANS(mps); 3316 } else { 3317 /* LS/FS or HS CTRL or HS BULK */ 3318 maxb = 0; 3319 } 3320 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3321 } 3322 } 3323 3324 /* 3325 * Convert endpoint bInterval value to endpoint context interval value 3326 * for Interrupt pipe. 3327 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3328 */ 3329 static uint32_t 3330 xhci_bival2ival(uint32_t ival, uint32_t speed) 3331 { 3332 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3333 int i; 3334 3335 /* 3336 * round ival down to "the nearest base 2 multiple of 3337 * bInterval * 8". 3338 * bInterval is at most 255 as its type is uByte. 3339 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3340 */ 3341 for (i = 10; i > 0; i--) { 3342 if ((ival * 8) >= (1 << i)) 3343 break; 3344 } 3345 ival = i; 3346 } else { 3347 /* Interval = bInterval-1 for SS/HS */ 3348 ival--; 3349 } 3350 3351 return ival; 3352 } 3353 3354 /* ----- */ 3355 3356 static void 3357 xhci_noop(struct usbd_pipe *pipe) 3358 { 3359 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3360 } 3361 3362 /* 3363 * Process root hub request. 3364 */ 3365 static int 3366 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3367 void *buf, int buflen) 3368 { 3369 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3370 usb_port_status_t ps; 3371 int l, totlen = 0; 3372 uint16_t len, value, index; 3373 int port, i; 3374 uint32_t v; 3375 3376 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3377 3378 if (sc->sc_dying) 3379 return -1; 3380 3381 size_t bn = bus == &sc->sc_bus ? 0 : 1; 3382 3383 len = UGETW(req->wLength); 3384 value = UGETW(req->wValue); 3385 index = UGETW(req->wIndex); 3386 3387 DPRINTFN(12, "rhreq: %04jx %04jx %04jx %04jx", 3388 req->bmRequestType | (req->bRequest << 8), value, index, len); 3389 3390 #define C(x,y) ((x) | ((y) << 8)) 3391 switch (C(req->bRequest, req->bmRequestType)) { 3392 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3393 DPRINTFN(8, "getdesc: wValue=0x%04jx", value, 0, 0, 0); 3394 if (len == 0) 3395 break; 3396 switch (value) { 3397 case C(0, UDESC_DEVICE): { 3398 usb_device_descriptor_t devd; 3399 totlen = min(buflen, sizeof(devd)); 3400 memcpy(&devd, buf, totlen); 3401 USETW(devd.idVendor, sc->sc_id_vendor); 3402 memcpy(buf, &devd, totlen); 3403 break; 3404 } 3405 #define sd ((usb_string_descriptor_t *)buf) 3406 case C(1, UDESC_STRING): 3407 /* Vendor */ 3408 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3409 break; 3410 case C(2, UDESC_STRING): 3411 /* Product */ 3412 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3413 break; 3414 #undef sd 3415 default: 3416 /* default from usbroothub */ 3417 return buflen; 3418 } 3419 break; 3420 3421 /* Hub requests */ 3422 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3423 break; 3424 /* Clear Port Feature request */ 3425 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): { 3426 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3427 3428 DPRINTFN(4, "UR_CLEAR_PORT_FEAT bp=%jd feat=%jd bus=%jd cp=%jd", 3429 index, value, bn, cp); 3430 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3431 return -1; 3432 } 3433 port = XHCI_PORTSC(cp); 3434 v = xhci_op_read_4(sc, port); 3435 DPRINTFN(4, "portsc=0x%08jx", v, 0, 0, 0); 3436 v &= ~XHCI_PS_CLEAR; 3437 switch (value) { 3438 case UHF_PORT_ENABLE: 3439 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3440 break; 3441 case UHF_PORT_SUSPEND: 3442 return -1; 3443 case UHF_PORT_POWER: 3444 break; 3445 case UHF_PORT_TEST: 3446 case UHF_PORT_INDICATOR: 3447 return -1; 3448 case UHF_C_PORT_CONNECTION: 3449 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3450 break; 3451 case UHF_C_PORT_ENABLE: 3452 case UHF_C_PORT_SUSPEND: 3453 case UHF_C_PORT_OVER_CURRENT: 3454 return -1; 3455 case UHF_C_BH_PORT_RESET: 3456 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3457 break; 3458 case UHF_C_PORT_RESET: 3459 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3460 break; 3461 case UHF_C_PORT_LINK_STATE: 3462 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3463 break; 3464 case UHF_C_PORT_CONFIG_ERROR: 3465 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3466 break; 3467 default: 3468 return -1; 3469 } 3470 break; 3471 } 3472 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3473 if (len == 0) 3474 break; 3475 if ((value & 0xff) != 0) { 3476 return -1; 3477 } 3478 usb_hub_descriptor_t hubd; 3479 3480 totlen = min(buflen, sizeof(hubd)); 3481 memcpy(&hubd, buf, totlen); 3482 hubd.bNbrPorts = sc->sc_rhportcount[bn]; 3483 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3484 hubd.bPwrOn2PwrGood = 200; 3485 for (i = 0, l = sc->sc_rhportcount[bn]; l > 0; i++, l -= 8) { 3486 /* XXX can't find out? */ 3487 hubd.DeviceRemovable[i++] = 0; 3488 } 3489 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3490 totlen = min(totlen, hubd.bDescLength); 3491 memcpy(buf, &hubd, totlen); 3492 break; 3493 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3494 if (len != 4) { 3495 return -1; 3496 } 3497 memset(buf, 0, len); /* ? XXX */ 3498 totlen = len; 3499 break; 3500 /* Get Port Status request */ 3501 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): { 3502 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3503 3504 DPRINTFN(8, "get port status bn=%jd i=%jd cp=%ju", 3505 bn, index, cp, 0); 3506 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3507 return -1; 3508 } 3509 if (len != 4) { 3510 return -1; 3511 } 3512 v = xhci_op_read_4(sc, XHCI_PORTSC(cp)); 3513 DPRINTFN(4, "getrhportsc %jd %08jx", cp, v, 0, 0); 3514 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3515 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3516 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3517 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3518 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3519 if (v & XHCI_PS_PR) i |= UPS_RESET; 3520 if (v & XHCI_PS_PP) { 3521 if (i & UPS_OTHER_SPEED) 3522 i |= UPS_PORT_POWER_SS; 3523 else 3524 i |= UPS_PORT_POWER; 3525 } 3526 if (i & UPS_OTHER_SPEED) 3527 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3528 if (sc->sc_vendor_port_status) 3529 i = sc->sc_vendor_port_status(sc, v, i); 3530 USETW(ps.wPortStatus, i); 3531 i = 0; 3532 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3533 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3534 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3535 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3536 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3537 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3538 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3539 USETW(ps.wPortChange, i); 3540 totlen = min(len, sizeof(ps)); 3541 memcpy(buf, &ps, totlen); 3542 break; 3543 } 3544 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3545 return -1; 3546 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3547 break; 3548 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3549 break; 3550 /* Set Port Feature request */ 3551 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3552 int optval = (index >> 8) & 0xff; 3553 index &= 0xff; 3554 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3555 return -1; 3556 } 3557 3558 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3559 3560 port = XHCI_PORTSC(cp); 3561 v = xhci_op_read_4(sc, port); 3562 DPRINTFN(4, "index %jd cp %jd portsc=0x%08jx", index, cp, v, 0); 3563 v &= ~XHCI_PS_CLEAR; 3564 switch (value) { 3565 case UHF_PORT_ENABLE: 3566 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3567 break; 3568 case UHF_PORT_SUSPEND: 3569 /* XXX suspend */ 3570 break; 3571 case UHF_PORT_RESET: 3572 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3573 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3574 /* Wait for reset to complete. */ 3575 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3576 if (sc->sc_dying) { 3577 return -1; 3578 } 3579 v = xhci_op_read_4(sc, port); 3580 if (v & XHCI_PS_PR) { 3581 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3582 usb_delay_ms(&sc->sc_bus, 10); 3583 /* XXX */ 3584 } 3585 break; 3586 case UHF_PORT_POWER: 3587 /* XXX power control */ 3588 break; 3589 /* XXX more */ 3590 case UHF_C_PORT_RESET: 3591 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3592 break; 3593 case UHF_PORT_U1_TIMEOUT: 3594 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3595 return -1; 3596 } 3597 port = XHCI_PORTPMSC(cp); 3598 v = xhci_op_read_4(sc, port); 3599 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 3600 index, cp, v, 0); 3601 v &= ~XHCI_PM3_U1TO_SET(0xff); 3602 v |= XHCI_PM3_U1TO_SET(optval); 3603 xhci_op_write_4(sc, port, v); 3604 break; 3605 case UHF_PORT_U2_TIMEOUT: 3606 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3607 return -1; 3608 } 3609 port = XHCI_PORTPMSC(cp); 3610 v = xhci_op_read_4(sc, port); 3611 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 3612 index, cp, v, 0); 3613 v &= ~XHCI_PM3_U2TO_SET(0xff); 3614 v |= XHCI_PM3_U2TO_SET(optval); 3615 xhci_op_write_4(sc, port, v); 3616 break; 3617 default: 3618 return -1; 3619 } 3620 } 3621 break; 3622 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3623 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3624 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3625 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3626 break; 3627 default: 3628 /* default from usbroothub */ 3629 return buflen; 3630 } 3631 3632 return totlen; 3633 } 3634 3635 /* root hub interrupt */ 3636 3637 static usbd_status 3638 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3639 { 3640 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3641 usbd_status err; 3642 3643 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3644 3645 /* Insert last in queue. */ 3646 mutex_enter(&sc->sc_lock); 3647 err = usb_insert_transfer(xfer); 3648 mutex_exit(&sc->sc_lock); 3649 if (err) 3650 return err; 3651 3652 /* Pipe isn't running, start first */ 3653 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3654 } 3655 3656 /* Wait for roothub port status/change */ 3657 static usbd_status 3658 xhci_root_intr_start(struct usbd_xfer *xfer) 3659 { 3660 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3661 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3662 3663 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3664 3665 if (sc->sc_dying) 3666 return USBD_IOERROR; 3667 3668 mutex_enter(&sc->sc_lock); 3669 sc->sc_intrxfer[bn] = xfer; 3670 mutex_exit(&sc->sc_lock); 3671 3672 return USBD_IN_PROGRESS; 3673 } 3674 3675 static void 3676 xhci_root_intr_abort(struct usbd_xfer *xfer) 3677 { 3678 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3679 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3680 3681 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3682 3683 KASSERT(mutex_owned(&sc->sc_lock)); 3684 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3685 3686 sc->sc_intrxfer[bn] = NULL; 3687 3688 xfer->ux_status = USBD_CANCELLED; 3689 usb_transfer_complete(xfer); 3690 } 3691 3692 static void 3693 xhci_root_intr_close(struct usbd_pipe *pipe) 3694 { 3695 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3696 const struct usbd_xfer *xfer = pipe->up_intrxfer; 3697 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3698 3699 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3700 3701 KASSERT(mutex_owned(&sc->sc_lock)); 3702 3703 sc->sc_intrxfer[bn] = NULL; 3704 } 3705 3706 static void 3707 xhci_root_intr_done(struct usbd_xfer *xfer) 3708 { 3709 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3710 3711 } 3712 3713 /* -------------- */ 3714 /* device control */ 3715 3716 static usbd_status 3717 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3718 { 3719 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3720 usbd_status err; 3721 3722 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3723 3724 /* Insert last in queue. */ 3725 mutex_enter(&sc->sc_lock); 3726 err = usb_insert_transfer(xfer); 3727 mutex_exit(&sc->sc_lock); 3728 if (err) 3729 return err; 3730 3731 /* Pipe isn't running, start first */ 3732 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3733 } 3734 3735 static usbd_status 3736 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3737 { 3738 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3739 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3740 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3741 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3742 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3743 usb_device_request_t * const req = &xfer->ux_request; 3744 const int isread = usbd_xfer_isread(xfer); 3745 const uint32_t len = UGETW(req->wLength); 3746 usb_dma_t * const dma = &xfer->ux_dmabuf; 3747 uint64_t parameter; 3748 uint32_t status; 3749 uint32_t control; 3750 u_int i; 3751 3752 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3753 DPRINTFN(12, "req: %04jx %04jx %04jx %04jx", 3754 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3755 UGETW(req->wIndex), UGETW(req->wLength)); 3756 3757 /* we rely on the bottom bits for extra info */ 3758 KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx", 3759 (uintptr_t) xfer); 3760 3761 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3762 3763 i = 0; 3764 3765 /* setup phase */ 3766 memcpy(¶meter, req, sizeof(parameter)); 3767 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3768 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3769 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3770 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3771 XHCI_TRB_3_IDT_BIT; 3772 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3773 3774 if (len != 0) { 3775 /* data phase */ 3776 parameter = DMAADDR(dma, 0); 3777 KASSERTMSG(len <= 0x10000, "len %d", len); 3778 status = XHCI_TRB_2_IRQ_SET(0) | 3779 XHCI_TRB_2_TDSZ_SET(1) | 3780 XHCI_TRB_2_BYTES_SET(len); 3781 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3782 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3783 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3784 XHCI_TRB_3_IOC_BIT; 3785 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3786 } 3787 3788 parameter = 0; 3789 status = XHCI_TRB_2_IRQ_SET(0); 3790 /* the status stage has inverted direction */ 3791 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3792 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3793 XHCI_TRB_3_IOC_BIT; 3794 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3795 3796 mutex_enter(&tr->xr_lock); 3797 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3798 mutex_exit(&tr->xr_lock); 3799 3800 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3801 3802 if (xfer->ux_timeout && !xhci_polling_p(sc)) { 3803 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3804 xhci_timeout, xfer); 3805 } 3806 3807 return USBD_IN_PROGRESS; 3808 } 3809 3810 static void 3811 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3812 { 3813 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3814 usb_device_request_t *req = &xfer->ux_request; 3815 int len = UGETW(req->wLength); 3816 int rd = req->bmRequestType & UT_READ; 3817 3818 if (len) 3819 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3820 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3821 } 3822 3823 static void 3824 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3825 { 3826 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3827 3828 xhci_abort_xfer(xfer, USBD_CANCELLED); 3829 } 3830 3831 static void 3832 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3833 { 3834 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3835 3836 xhci_close_pipe(pipe); 3837 } 3838 3839 /* ------------------ */ 3840 /* device isochronous */ 3841 3842 /* ----------- */ 3843 /* device bulk */ 3844 3845 static usbd_status 3846 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3847 { 3848 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3849 usbd_status err; 3850 3851 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3852 3853 /* Insert last in queue. */ 3854 mutex_enter(&sc->sc_lock); 3855 err = usb_insert_transfer(xfer); 3856 mutex_exit(&sc->sc_lock); 3857 if (err) 3858 return err; 3859 3860 /* 3861 * Pipe isn't running (otherwise err would be USBD_INPROG), 3862 * so start it first. 3863 */ 3864 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3865 } 3866 3867 static usbd_status 3868 xhci_device_bulk_start(struct usbd_xfer *xfer) 3869 { 3870 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3871 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3872 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3873 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3874 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3875 const uint32_t len = xfer->ux_length; 3876 usb_dma_t * const dma = &xfer->ux_dmabuf; 3877 uint64_t parameter; 3878 uint32_t status; 3879 uint32_t control; 3880 u_int i = 0; 3881 3882 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3883 3884 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 3885 0); 3886 3887 if (sc->sc_dying) 3888 return USBD_IOERROR; 3889 3890 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3891 3892 parameter = DMAADDR(dma, 0); 3893 /* 3894 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3895 * If the user supplied buffer crosses such a boundary then 2 3896 * (or more) TRB should be used. 3897 * If multiple TRB are used the td_size field must be set correctly. 3898 * For v1.0 devices (like ivy bridge) this is the number of usb data 3899 * blocks needed to complete the transfer. 3900 * Setting it to 1 in the last TRB causes an extra zero-length 3901 * data block be sent. 3902 * The earlier documentation differs, I don't know how it behaves. 3903 */ 3904 KASSERTMSG(len <= 0x10000, "len %d", len); 3905 status = XHCI_TRB_2_IRQ_SET(0) | 3906 XHCI_TRB_2_TDSZ_SET(1) | 3907 XHCI_TRB_2_BYTES_SET(len); 3908 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3909 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3910 XHCI_TRB_3_IOC_BIT; 3911 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3912 3913 mutex_enter(&tr->xr_lock); 3914 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3915 mutex_exit(&tr->xr_lock); 3916 3917 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3918 3919 if (xfer->ux_timeout && !xhci_polling_p(sc)) { 3920 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3921 xhci_timeout, xfer); 3922 } 3923 3924 return USBD_IN_PROGRESS; 3925 } 3926 3927 static void 3928 xhci_device_bulk_done(struct usbd_xfer *xfer) 3929 { 3930 #ifdef USB_DEBUG 3931 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3932 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3933 #endif 3934 const int isread = usbd_xfer_isread(xfer); 3935 3936 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3937 3938 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 3939 0); 3940 3941 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3942 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3943 } 3944 3945 static void 3946 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3947 { 3948 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3949 3950 xhci_abort_xfer(xfer, USBD_CANCELLED); 3951 } 3952 3953 static void 3954 xhci_device_bulk_close(struct usbd_pipe *pipe) 3955 { 3956 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3957 3958 xhci_close_pipe(pipe); 3959 } 3960 3961 /* ---------------- */ 3962 /* device interrupt */ 3963 3964 static usbd_status 3965 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3966 { 3967 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3968 usbd_status err; 3969 3970 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3971 3972 /* Insert last in queue. */ 3973 mutex_enter(&sc->sc_lock); 3974 err = usb_insert_transfer(xfer); 3975 mutex_exit(&sc->sc_lock); 3976 if (err) 3977 return err; 3978 3979 /* 3980 * Pipe isn't running (otherwise err would be USBD_INPROG), 3981 * so start it first. 3982 */ 3983 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3984 } 3985 3986 static usbd_status 3987 xhci_device_intr_start(struct usbd_xfer *xfer) 3988 { 3989 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3990 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3991 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3992 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3993 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3994 const uint32_t len = xfer->ux_length; 3995 usb_dma_t * const dma = &xfer->ux_dmabuf; 3996 uint64_t parameter; 3997 uint32_t status; 3998 uint32_t control; 3999 u_int i = 0; 4000 4001 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4002 4003 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 4004 0); 4005 4006 if (sc->sc_dying) 4007 return USBD_IOERROR; 4008 4009 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 4010 4011 parameter = DMAADDR(dma, 0); 4012 KASSERTMSG(len <= 0x10000, "len %d", len); 4013 status = XHCI_TRB_2_IRQ_SET(0) | 4014 XHCI_TRB_2_TDSZ_SET(1) | 4015 XHCI_TRB_2_BYTES_SET(len); 4016 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 4017 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 4018 XHCI_TRB_3_IOC_BIT; 4019 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 4020 4021 mutex_enter(&tr->xr_lock); 4022 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 4023 mutex_exit(&tr->xr_lock); 4024 4025 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4026 4027 if (xfer->ux_timeout && !xhci_polling_p(sc)) { 4028 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4029 xhci_timeout, xfer); 4030 } 4031 4032 return USBD_IN_PROGRESS; 4033 } 4034 4035 static void 4036 xhci_device_intr_done(struct usbd_xfer *xfer) 4037 { 4038 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4039 #ifdef USB_DEBUG 4040 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4041 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4042 #endif 4043 const int isread = usbd_xfer_isread(xfer); 4044 4045 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4046 4047 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 4048 0); 4049 4050 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 4051 4052 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4053 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4054 } 4055 4056 static void 4057 xhci_device_intr_abort(struct usbd_xfer *xfer) 4058 { 4059 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4060 4061 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4062 4063 KASSERT(mutex_owned(&sc->sc_lock)); 4064 DPRINTFN(15, "%#jx", (uintptr_t)xfer, 0, 0, 0); 4065 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4066 xhci_abort_xfer(xfer, USBD_CANCELLED); 4067 } 4068 4069 static void 4070 xhci_device_intr_close(struct usbd_pipe *pipe) 4071 { 4072 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 4073 4074 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4075 DPRINTFN(15, "%#jx", (uintptr_t)pipe, 0, 0, 0); 4076 4077 xhci_close_pipe(pipe); 4078 } 4079 4080 /* ------------ */ 4081 4082 static void 4083 xhci_timeout(void *addr) 4084 { 4085 struct xhci_xfer * const xx = addr; 4086 struct usbd_xfer * const xfer = &xx->xx_xfer; 4087 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4088 4089 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4090 4091 if (sc->sc_dying) { 4092 return; 4093 } 4094 4095 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 4096 USB_TASKQ_MPSAFE); 4097 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 4098 USB_TASKQ_HC); 4099 } 4100 4101 static void 4102 xhci_timeout_task(void *addr) 4103 { 4104 struct usbd_xfer * const xfer = addr; 4105 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4106 4107 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4108 4109 mutex_enter(&sc->sc_lock); 4110 xhci_abort_xfer(xfer, USBD_TIMEOUT); 4111 mutex_exit(&sc->sc_lock); 4112 } 4113
Indexes created Tue Sep 23 14:10:03 GMT 2025