xhci.c revision 1.79
1 /* $NetBSD: xhci.c,v 1.79 2017/12/08 21:51:07 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.79 2017/12/08 21:51:07 christos Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 #define HEXDUMP(a, b, c) \ 77 do { \ 78 if (xhcidebug > 0) \ 79 hexdump(a, b, c); \ 80 } while (/*CONSTCOND*/0) 81 static int xhcidebug = 0; 82 83 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 84 { 85 int err; 86 const struct sysctlnode *rnode; 87 const struct sysctlnode *cnode; 88 89 err = sysctl_createv(clog, 0, NULL, &rnode, 90 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 91 SYSCTL_DESCR("xhci global controls"), 92 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 93 94 if (err) 95 goto fail; 96 97 /* control debugging printfs */ 98 err = sysctl_createv(clog, 0, &rnode, &cnode, 99 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 100 "debug", SYSCTL_DESCR("Enable debugging output"), 101 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 102 if (err) 103 goto fail; 104 105 return; 106 fail: 107 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 108 } 109 110 #endif /* !XHCI_DEBUG */ 111 #endif /* USB_DEBUG */ 112 113 #ifndef HEXDUMP 114 #define HEXDUMP(a, b, c) 115 #endif 116 117 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 118 #define XHCIHIST_FUNC() USBHIST_FUNC() 119 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 120 121 #define XHCI_DCI_SLOT 0 122 #define XHCI_DCI_EP_CONTROL 1 123 124 #define XHCI_ICI_INPUT_CONTROL 0 125 126 struct xhci_pipe { 127 struct usbd_pipe xp_pipe; 128 struct usb_task xp_async_task; 129 }; 130 131 #define XHCI_COMMAND_RING_TRBS 256 132 #define XHCI_EVENT_RING_TRBS 256 133 #define XHCI_EVENT_RING_SEGMENTS 1 134 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 135 136 static usbd_status xhci_open(struct usbd_pipe *); 137 static void xhci_close_pipe(struct usbd_pipe *); 138 static int xhci_intr1(struct xhci_softc * const); 139 static void xhci_softintr(void *); 140 static void xhci_poll(struct usbd_bus *); 141 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 142 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 143 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 144 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 145 struct usbd_port *); 146 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 147 void *, int); 148 149 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 150 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 151 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 152 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 153 154 static void xhci_host_dequeue(struct xhci_ring * const); 155 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 156 157 static usbd_status xhci_do_command(struct xhci_softc * const, 158 struct xhci_trb * const, int); 159 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 160 struct xhci_trb * const, int); 161 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 162 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 163 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 164 static usbd_status xhci_enable_slot(struct xhci_softc * const, 165 uint8_t * const); 166 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 167 static usbd_status xhci_address_device(struct xhci_softc * const, 168 uint64_t, uint8_t, bool); 169 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 170 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 171 struct xhci_slot * const, u_int); 172 static usbd_status xhci_ring_init(struct xhci_softc * const, 173 struct xhci_ring * const, size_t, size_t); 174 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 175 176 static void xhci_setup_ctx(struct usbd_pipe *); 177 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 178 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 179 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 180 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 181 182 static void xhci_noop(struct usbd_pipe *); 183 184 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 185 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 186 static void xhci_root_intr_abort(struct usbd_xfer *); 187 static void xhci_root_intr_close(struct usbd_pipe *); 188 static void xhci_root_intr_done(struct usbd_xfer *); 189 190 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 191 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 192 static void xhci_device_ctrl_abort(struct usbd_xfer *); 193 static void xhci_device_ctrl_close(struct usbd_pipe *); 194 static void xhci_device_ctrl_done(struct usbd_xfer *); 195 196 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 197 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 198 static void xhci_device_intr_abort(struct usbd_xfer *); 199 static void xhci_device_intr_close(struct usbd_pipe *); 200 static void xhci_device_intr_done(struct usbd_xfer *); 201 202 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 203 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 204 static void xhci_device_bulk_abort(struct usbd_xfer *); 205 static void xhci_device_bulk_close(struct usbd_pipe *); 206 static void xhci_device_bulk_done(struct usbd_xfer *); 207 208 static void xhci_timeout(void *); 209 static void xhci_timeout_task(void *); 210 211 static const struct usbd_bus_methods xhci_bus_methods = { 212 .ubm_open = xhci_open, 213 .ubm_softint = xhci_softintr, 214 .ubm_dopoll = xhci_poll, 215 .ubm_allocx = xhci_allocx, 216 .ubm_freex = xhci_freex, 217 .ubm_getlock = xhci_get_lock, 218 .ubm_newdev = xhci_new_device, 219 .ubm_rhctrl = xhci_roothub_ctrl, 220 }; 221 222 static const struct usbd_pipe_methods xhci_root_intr_methods = { 223 .upm_transfer = xhci_root_intr_transfer, 224 .upm_start = xhci_root_intr_start, 225 .upm_abort = xhci_root_intr_abort, 226 .upm_close = xhci_root_intr_close, 227 .upm_cleartoggle = xhci_noop, 228 .upm_done = xhci_root_intr_done, 229 }; 230 231 232 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 233 .upm_transfer = xhci_device_ctrl_transfer, 234 .upm_start = xhci_device_ctrl_start, 235 .upm_abort = xhci_device_ctrl_abort, 236 .upm_close = xhci_device_ctrl_close, 237 .upm_cleartoggle = xhci_noop, 238 .upm_done = xhci_device_ctrl_done, 239 }; 240 241 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 242 .upm_cleartoggle = xhci_noop, 243 }; 244 245 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 246 .upm_transfer = xhci_device_bulk_transfer, 247 .upm_start = xhci_device_bulk_start, 248 .upm_abort = xhci_device_bulk_abort, 249 .upm_close = xhci_device_bulk_close, 250 .upm_cleartoggle = xhci_noop, 251 .upm_done = xhci_device_bulk_done, 252 }; 253 254 static const struct usbd_pipe_methods xhci_device_intr_methods = { 255 .upm_transfer = xhci_device_intr_transfer, 256 .upm_start = xhci_device_intr_start, 257 .upm_abort = xhci_device_intr_abort, 258 .upm_close = xhci_device_intr_close, 259 .upm_cleartoggle = xhci_noop, 260 .upm_done = xhci_device_intr_done, 261 }; 262 263 static inline uint32_t 264 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 265 { 266 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 267 } 268 269 static inline uint32_t 270 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 271 { 272 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 273 } 274 275 static inline void 276 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 277 uint32_t value) 278 { 279 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 280 } 281 282 #if 0 /* unused */ 283 static inline void 284 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 285 uint32_t value) 286 { 287 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 288 } 289 #endif /* unused */ 290 291 static inline uint32_t 292 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 293 { 294 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 295 } 296 297 static inline uint32_t 298 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 299 { 300 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 301 } 302 303 static inline void 304 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 305 uint32_t value) 306 { 307 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 308 } 309 310 static inline uint64_t 311 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 312 { 313 uint64_t value; 314 315 if (sc->sc_ac64) { 316 #ifdef XHCI_USE_BUS_SPACE_8 317 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 318 #else 319 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 320 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 321 offset + 4) << 32; 322 #endif 323 } else { 324 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 325 } 326 327 return value; 328 } 329 330 static inline void 331 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 332 uint64_t value) 333 { 334 if (sc->sc_ac64) { 335 #ifdef XHCI_USE_BUS_SPACE_8 336 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 337 #else 338 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 339 (value >> 0) & 0xffffffff); 340 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 341 (value >> 32) & 0xffffffff); 342 #endif 343 } else { 344 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 345 } 346 } 347 348 static inline uint32_t 349 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 350 { 351 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 352 } 353 354 static inline void 355 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 356 uint32_t value) 357 { 358 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 359 } 360 361 #if 0 /* unused */ 362 static inline uint64_t 363 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 364 { 365 uint64_t value; 366 367 if (sc->sc_ac64) { 368 #ifdef XHCI_USE_BUS_SPACE_8 369 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 370 #else 371 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 372 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 373 offset + 4) << 32; 374 #endif 375 } else { 376 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 377 } 378 379 return value; 380 } 381 #endif /* unused */ 382 383 static inline void 384 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 385 uint64_t value) 386 { 387 if (sc->sc_ac64) { 388 #ifdef XHCI_USE_BUS_SPACE_8 389 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 390 #else 391 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 392 (value >> 0) & 0xffffffff); 393 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 394 (value >> 32) & 0xffffffff); 395 #endif 396 } else { 397 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 398 } 399 } 400 401 #if 0 /* unused */ 402 static inline uint32_t 403 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 404 { 405 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 406 } 407 #endif /* unused */ 408 409 static inline void 410 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 411 uint32_t value) 412 { 413 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 414 } 415 416 /* --- */ 417 418 static inline uint8_t 419 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 420 { 421 u_int eptype = 0; 422 423 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 424 case UE_CONTROL: 425 eptype = 0x0; 426 break; 427 case UE_ISOCHRONOUS: 428 eptype = 0x1; 429 break; 430 case UE_BULK: 431 eptype = 0x2; 432 break; 433 case UE_INTERRUPT: 434 eptype = 0x3; 435 break; 436 } 437 438 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 439 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 440 return eptype | 0x4; 441 else 442 return eptype; 443 } 444 445 static u_int 446 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 447 { 448 /* xHCI 1.0 section 4.5.1 */ 449 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 450 u_int in = 0; 451 452 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 453 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 454 in = 1; 455 456 return epaddr * 2 + in; 457 } 458 459 static inline u_int 460 xhci_dci_to_ici(const u_int i) 461 { 462 return i + 1; 463 } 464 465 static inline void * 466 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 467 const u_int dci) 468 { 469 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 470 } 471 472 #if 0 /* unused */ 473 static inline bus_addr_t 474 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 475 const u_int dci) 476 { 477 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 478 } 479 #endif /* unused */ 480 481 static inline void * 482 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 483 const u_int ici) 484 { 485 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 486 } 487 488 static inline bus_addr_t 489 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 490 const u_int ici) 491 { 492 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 493 } 494 495 static inline struct xhci_trb * 496 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 497 { 498 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 499 } 500 501 static inline bus_addr_t 502 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 503 { 504 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 505 } 506 507 static inline void 508 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 509 uint32_t control) 510 { 511 trb->trb_0 = htole64(parameter); 512 trb->trb_2 = htole32(status); 513 trb->trb_3 = htole32(control); 514 } 515 516 static int 517 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 518 { 519 /* base address of TRBs */ 520 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 521 522 /* trb_0 range sanity check */ 523 if (trb_0 == 0 || trb_0 < trbp || 524 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 525 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 526 return 1; 527 } 528 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 529 return 0; 530 } 531 532 static unsigned int 533 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 534 u_int dci) 535 { 536 uint32_t *cp; 537 538 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 539 cp = xhci_slot_get_dcv(sc, xs, dci); 540 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 541 } 542 543 static inline unsigned int 544 xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport) 545 { 546 const unsigned int port = ctlrport - 1; 547 const uint8_t bit = __BIT(port % NBBY); 548 549 return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit); 550 } 551 552 /* 553 * Return the roothub port for a controller port. Both are 1..n. 554 */ 555 static inline unsigned int 556 xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport) 557 { 558 559 return sc->sc_ctlrportmap[ctrlport - 1]; 560 } 561 562 /* 563 * Return the controller port for a bus roothub port. Both are 1..n. 564 */ 565 static inline unsigned int 566 xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn, 567 unsigned int rhport) 568 { 569 570 return sc->sc_rhportmap[bn][rhport - 1]; 571 } 572 573 /* --- */ 574 575 void 576 xhci_childdet(device_t self, device_t child) 577 { 578 struct xhci_softc * const sc = device_private(self); 579 580 KASSERT(sc->sc_child == child); 581 if (child == sc->sc_child) 582 sc->sc_child = NULL; 583 } 584 585 int 586 xhci_detach(struct xhci_softc *sc, int flags) 587 { 588 int rv = 0; 589 590 if (sc->sc_child2 != NULL) { 591 rv = config_detach(sc->sc_child2, flags); 592 if (rv != 0) 593 return rv; 594 } 595 596 if (sc->sc_child != NULL) { 597 rv = config_detach(sc->sc_child, flags); 598 if (rv != 0) 599 return rv; 600 } 601 602 /* XXX unconfigure/free slots */ 603 604 /* verify: */ 605 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 606 xhci_op_write_4(sc, XHCI_USBCMD, 0); 607 /* do we need to wait for stop? */ 608 609 xhci_op_write_8(sc, XHCI_CRCR, 0); 610 xhci_ring_free(sc, &sc->sc_cr); 611 cv_destroy(&sc->sc_command_cv); 612 cv_destroy(&sc->sc_cmdbusy_cv); 613 614 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 615 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 616 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 617 xhci_ring_free(sc, &sc->sc_er); 618 619 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 620 621 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 622 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 623 624 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 625 626 kmem_free(sc->sc_ctlrportbus, 627 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY)); 628 kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int)); 629 630 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 631 kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int)); 632 } 633 634 mutex_destroy(&sc->sc_lock); 635 mutex_destroy(&sc->sc_intr_lock); 636 637 pool_cache_destroy(sc->sc_xferpool); 638 639 return rv; 640 } 641 642 int 643 xhci_activate(device_t self, enum devact act) 644 { 645 struct xhci_softc * const sc = device_private(self); 646 647 switch (act) { 648 case DVACT_DEACTIVATE: 649 sc->sc_dying = true; 650 return 0; 651 default: 652 return EOPNOTSUPP; 653 } 654 } 655 656 bool 657 xhci_suspend(device_t dv, const pmf_qual_t *qual) 658 { 659 return false; 660 } 661 662 bool 663 xhci_resume(device_t dv, const pmf_qual_t *qual) 664 { 665 return false; 666 } 667 668 bool 669 xhci_shutdown(device_t self, int flags) 670 { 671 return false; 672 } 673 674 static int 675 xhci_hc_reset(struct xhci_softc * const sc) 676 { 677 uint32_t usbcmd, usbsts; 678 int i; 679 680 /* Check controller not ready */ 681 for (i = 0; i < XHCI_WAIT_CNR; i++) { 682 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 683 if ((usbsts & XHCI_STS_CNR) == 0) 684 break; 685 usb_delay_ms(&sc->sc_bus, 1); 686 } 687 if (i >= XHCI_WAIT_CNR) { 688 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 689 return EIO; 690 } 691 692 /* Halt controller */ 693 usbcmd = 0; 694 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 695 usb_delay_ms(&sc->sc_bus, 1); 696 697 /* Reset controller */ 698 usbcmd = XHCI_CMD_HCRST; 699 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 700 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 701 /* 702 * Wait 1ms first. Existing Intel xHCI requies 1ms delay to 703 * prevent system hang (Errata). 704 */ 705 usb_delay_ms(&sc->sc_bus, 1); 706 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 707 if ((usbcmd & XHCI_CMD_HCRST) == 0) 708 break; 709 } 710 if (i >= XHCI_WAIT_HCRST) { 711 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 712 return EIO; 713 } 714 715 /* Check controller not ready */ 716 for (i = 0; i < XHCI_WAIT_CNR; i++) { 717 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 718 if ((usbsts & XHCI_STS_CNR) == 0) 719 break; 720 usb_delay_ms(&sc->sc_bus, 1); 721 } 722 if (i >= XHCI_WAIT_CNR) { 723 aprint_error_dev(sc->sc_dev, 724 "controller not ready timeout after reset\n"); 725 return EIO; 726 } 727 728 return 0; 729 } 730 731 732 /* 7.2 xHCI Support Protocol Capability */ 733 static void 734 xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp) 735 { 736 /* XXX Cache this lot */ 737 738 const uint32_t w0 = xhci_read_4(sc, ecp); 739 const uint32_t w4 = xhci_read_4(sc, ecp + 4); 740 const uint32_t w8 = xhci_read_4(sc, ecp + 8); 741 const uint32_t wc = xhci_read_4(sc, ecp + 0xc); 742 743 aprint_debug_dev(sc->sc_dev, 744 " SP: %08x %08x %08x %08x\n", w0, w4, w8, wc); 745 746 if (w4 != XHCI_XECP_USBID) 747 return; 748 749 const int major = XHCI_XECP_SP_W0_MAJOR(w0); 750 const int minor = XHCI_XECP_SP_W0_MINOR(w0); 751 const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8); 752 const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8); 753 754 const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16)); 755 switch (mm) { 756 case 0x0200: 757 case 0x0300: 758 case 0x0301: 759 aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n", 760 major == 3 ? "ss" : "hs", cpo, cpo + cpc -1); 761 break; 762 default: 763 aprint_debug_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n", 764 major, minor); 765 return; 766 } 767 768 const size_t bus = (major == 3) ? 0 : 1; 769 770 /* Index arrays with 0..n-1 where ports are numbered 1..n */ 771 for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) { 772 if (sc->sc_ctlrportmap[cp] != 0) { 773 aprint_error_dev(sc->sc_dev, "contoller port %zu " 774 "already assigned", cp); 775 continue; 776 } 777 778 sc->sc_ctlrportbus[cp / NBBY] |= 779 bus == 0 ? 0 : __BIT(cp % NBBY); 780 781 const size_t rhp = sc->sc_rhportcount[bus]++; 782 783 KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0, 784 "bus %zu rhp %zu is %d", bus, rhp, 785 sc->sc_rhportmap[bus][rhp]); 786 787 sc->sc_rhportmap[bus][rhp] = cp + 1; 788 sc->sc_ctlrportmap[cp] = rhp + 1; 789 } 790 } 791 792 /* Process extended capabilities */ 793 static void 794 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 795 { 796 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 797 798 bus_size_t ecp = XHCI_HCC_XECP(hcc) * 4; 799 while (ecp != 0) { 800 uint32_t ecr = xhci_read_4(sc, ecp); 801 aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr); 802 switch (XHCI_XECP_ID(ecr)) { 803 case XHCI_ID_PROTOCOLS: { 804 xhci_id_protocols(sc, ecp); 805 break; 806 } 807 case XHCI_ID_USB_LEGACY: { 808 uint8_t bios_sem; 809 810 /* Take host controller ownership from BIOS */ 811 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 812 if (bios_sem) { 813 /* sets xHCI to be owned by OS */ 814 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 815 aprint_debug_dev(sc->sc_dev, 816 "waiting for BIOS to give up control\n"); 817 for (int i = 0; i < 5000; i++) { 818 bios_sem = xhci_read_1(sc, ecp + 819 XHCI_XECP_BIOS_SEM); 820 if (bios_sem == 0) 821 break; 822 DELAY(1000); 823 } 824 if (bios_sem) { 825 aprint_error_dev(sc->sc_dev, 826 "timed out waiting for BIOS\n"); 827 } 828 } 829 break; 830 } 831 default: 832 break; 833 } 834 ecr = xhci_read_4(sc, ecp); 835 if (XHCI_XECP_NEXT(ecr) == 0) { 836 ecp = 0; 837 } else { 838 ecp += XHCI_XECP_NEXT(ecr) * 4; 839 } 840 } 841 } 842 843 #define XHCI_HCCPREV1_BITS \ 844 "\177\020" /* New bitmask */ \ 845 "f\020\020XECP\0" \ 846 "f\014\4MAXPSA\0" \ 847 "b\013CFC\0" \ 848 "b\012SEC\0" \ 849 "b\011SBD\0" \ 850 "b\010FSE\0" \ 851 "b\7NSS\0" \ 852 "b\6LTC\0" \ 853 "b\5LHRC\0" \ 854 "b\4PIND\0" \ 855 "b\3PPC\0" \ 856 "b\2CZC\0" \ 857 "b\1BNC\0" \ 858 "b\0AC64\0" \ 859 "\0" 860 #define XHCI_HCCV1_x_BITS \ 861 "\177\020" /* New bitmask */ \ 862 "f\020\020XECP\0" \ 863 "f\014\4MAXPSA\0" \ 864 "b\013CFC\0" \ 865 "b\012SEC\0" \ 866 "b\011SPC\0" \ 867 "b\010PAE\0" \ 868 "b\7NSS\0" \ 869 "b\6LTC\0" \ 870 "b\5LHRC\0" \ 871 "b\4PIND\0" \ 872 "b\3PPC\0" \ 873 "b\2CSZ\0" \ 874 "b\1BNC\0" \ 875 "b\0AC64\0" \ 876 "\0" 877 878 void 879 xhci_start(struct xhci_softc *sc) 880 { 881 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 882 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 883 /* Intel xhci needs interrupt rate moderated. */ 884 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 885 else 886 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 887 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 888 xhci_rt_read_4(sc, XHCI_IMOD(0))); 889 890 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 891 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 892 xhci_op_read_4(sc, XHCI_USBCMD)); 893 } 894 895 int 896 xhci_init(struct xhci_softc *sc) 897 { 898 bus_size_t bsz; 899 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 900 uint32_t pagesize, config; 901 int i = 0; 902 uint16_t hciversion; 903 uint8_t caplength; 904 905 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 906 907 /* Set up the bus struct for the usb 3 and usb 2 buses */ 908 sc->sc_bus.ub_methods = &xhci_bus_methods; 909 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 910 sc->sc_bus.ub_revision = USBREV_3_0; 911 sc->sc_bus.ub_usedma = true; 912 sc->sc_bus.ub_hcpriv = sc; 913 914 sc->sc_bus2.ub_methods = &xhci_bus_methods; 915 sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe); 916 sc->sc_bus2.ub_revision = USBREV_2_0; 917 sc->sc_bus2.ub_usedma = true; 918 sc->sc_bus2.ub_hcpriv = sc; 919 sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag; 920 921 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 922 caplength = XHCI_CAP_CAPLENGTH(cap); 923 hciversion = XHCI_CAP_HCIVERSION(cap); 924 925 if (hciversion < XHCI_HCIVERSION_0_96 || 926 hciversion > XHCI_HCIVERSION_1_0) { 927 aprint_normal_dev(sc->sc_dev, 928 "xHCI version %x.%x not known to be supported\n", 929 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 930 } else { 931 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 932 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 933 } 934 935 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 936 &sc->sc_cbh) != 0) { 937 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 938 return ENOMEM; 939 } 940 941 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 942 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 943 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 944 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 945 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 946 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 947 aprint_debug_dev(sc->sc_dev, 948 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 949 950 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 951 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 952 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 953 954 char sbuf[128]; 955 if (hciversion < XHCI_HCIVERSION_1_0) 956 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 957 else 958 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 959 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 960 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 961 962 /* default all ports to bus 0, i.e. usb 3 */ 963 sc->sc_ctlrportbus = kmem_zalloc( 964 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP); 965 sc->sc_ctlrportmap = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 966 967 /* controller port to bus roothub port map */ 968 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 969 sc->sc_rhportmap[j] = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 970 } 971 972 /* 973 * Process all Extended Capabilities 974 */ 975 xhci_ecp(sc, hcc); 976 977 bsz = XHCI_PORTSC(sc->sc_maxports); 978 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 979 &sc->sc_obh) != 0) { 980 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 981 return ENOMEM; 982 } 983 984 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 985 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 986 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 987 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 988 return ENOMEM; 989 } 990 991 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 992 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 993 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 994 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 995 return ENOMEM; 996 } 997 998 int rv; 999 rv = xhci_hc_reset(sc); 1000 if (rv != 0) { 1001 return rv; 1002 } 1003 1004 if (sc->sc_vendor_init) 1005 sc->sc_vendor_init(sc); 1006 1007 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 1008 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 1009 pagesize = ffs(pagesize); 1010 if (pagesize == 0) { 1011 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 1012 return EIO; 1013 } 1014 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 1015 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 1016 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 1017 (uint32_t)sc->sc_maxslots); 1018 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 1019 1020 usbd_status err; 1021 1022 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 1023 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 1024 if (sc->sc_maxspbuf != 0) { 1025 err = usb_allocmem(&sc->sc_bus, 1026 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 1027 &sc->sc_spbufarray_dma); 1028 if (err) { 1029 aprint_error_dev(sc->sc_dev, 1030 "spbufarray init fail, err %d\n", err); 1031 return ENOMEM; 1032 } 1033 1034 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 1035 sc->sc_maxspbuf, KM_SLEEP); 1036 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 1037 for (i = 0; i < sc->sc_maxspbuf; i++) { 1038 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 1039 /* allocate contexts */ 1040 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 1041 sc->sc_pgsz, dma); 1042 if (err) { 1043 aprint_error_dev(sc->sc_dev, 1044 "spbufarray_dma init fail, err %d\n", err); 1045 rv = ENOMEM; 1046 goto bad1; 1047 } 1048 spbufarray[i] = htole64(DMAADDR(dma, 0)); 1049 usb_syncmem(dma, 0, sc->sc_pgsz, 1050 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1051 } 1052 1053 usb_syncmem(&sc->sc_spbufarray_dma, 0, 1054 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 1055 } 1056 1057 config = xhci_op_read_4(sc, XHCI_CONFIG); 1058 config &= ~0xFF; 1059 config |= sc->sc_maxslots & 0xFF; 1060 xhci_op_write_4(sc, XHCI_CONFIG, config); 1061 1062 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 1063 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 1064 if (err) { 1065 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 1066 err); 1067 rv = ENOMEM; 1068 goto bad1; 1069 } 1070 1071 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 1072 XHCI_EVENT_RING_SEGMENTS_ALIGN); 1073 if (err) { 1074 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 1075 err); 1076 rv = ENOMEM; 1077 goto bad2; 1078 } 1079 1080 usb_dma_t *dma; 1081 size_t size; 1082 size_t align; 1083 1084 dma = &sc->sc_eventst_dma; 1085 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 1086 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 1087 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 1088 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 1089 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1090 if (err) { 1091 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 1092 err); 1093 rv = ENOMEM; 1094 goto bad3; 1095 } 1096 1097 memset(KERNADDR(dma, 0), 0, size); 1098 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1099 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 1100 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 1101 KERNADDR(&sc->sc_eventst_dma, 0), 1102 sc->sc_eventst_dma.udma_block->size); 1103 1104 dma = &sc->sc_dcbaa_dma; 1105 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 1106 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 1107 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 1108 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1109 if (err) { 1110 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1111 rv = ENOMEM; 1112 goto bad4; 1113 } 1114 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 1115 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1116 KERNADDR(&sc->sc_dcbaa_dma, 0), 1117 sc->sc_dcbaa_dma.udma_block->size); 1118 1119 memset(KERNADDR(dma, 0), 0, size); 1120 if (sc->sc_maxspbuf != 0) { 1121 /* 1122 * DCBA entry 0 hold the scratchbuf array pointer. 1123 */ 1124 *(uint64_t *)KERNADDR(dma, 0) = 1125 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1126 } 1127 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1128 1129 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1130 KM_SLEEP); 1131 if (sc->sc_slots == NULL) { 1132 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1133 rv = ENOMEM; 1134 goto bad; 1135 } 1136 1137 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1138 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1139 if (sc->sc_xferpool == NULL) { 1140 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1141 err); 1142 rv = ENOMEM; 1143 goto bad; 1144 } 1145 1146 cv_init(&sc->sc_command_cv, "xhcicmd"); 1147 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1148 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1149 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1150 1151 struct xhci_erste *erst; 1152 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1153 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1154 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1155 erst[0].erste_3 = htole32(0); 1156 usb_syncmem(&sc->sc_eventst_dma, 0, 1157 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1158 1159 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1160 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1161 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1162 XHCI_ERDP_LO_BUSY); 1163 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1164 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1165 sc->sc_cr.xr_cs); 1166 1167 HEXDUMP("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1168 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1169 1170 if ((sc->sc_quirks & XHCI_DEFERRED_START) == 0) 1171 xhci_start(sc); 1172 1173 return 0; 1174 1175 bad: 1176 if (sc->sc_xferpool) { 1177 pool_cache_destroy(sc->sc_xferpool); 1178 sc->sc_xferpool = NULL; 1179 } 1180 1181 if (sc->sc_slots) { 1182 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1183 sc->sc_maxslots); 1184 sc->sc_slots = NULL; 1185 } 1186 1187 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1188 bad4: 1189 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1190 bad3: 1191 xhci_ring_free(sc, &sc->sc_er); 1192 bad2: 1193 xhci_ring_free(sc, &sc->sc_cr); 1194 i = sc->sc_maxspbuf; 1195 bad1: 1196 for (int j = 0; j < i; j++) 1197 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1198 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1199 1200 return rv; 1201 } 1202 1203 static inline bool 1204 xhci_polling_p(struct xhci_softc * const sc) 1205 { 1206 return sc->sc_bus.ub_usepolling || sc->sc_bus2.ub_usepolling; 1207 } 1208 1209 int 1210 xhci_intr(void *v) 1211 { 1212 struct xhci_softc * const sc = v; 1213 int ret = 0; 1214 1215 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1216 1217 if (sc == NULL) 1218 return 0; 1219 1220 mutex_spin_enter(&sc->sc_intr_lock); 1221 1222 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1223 goto done; 1224 1225 /* If we get an interrupt while polling, then just ignore it. */ 1226 if (xhci_polling_p(sc)) { 1227 #ifdef DIAGNOSTIC 1228 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1229 #endif 1230 goto done; 1231 } 1232 1233 ret = xhci_intr1(sc); 1234 if (ret) { 1235 usb_schedsoftintr(&sc->sc_bus); 1236 } 1237 done: 1238 mutex_spin_exit(&sc->sc_intr_lock); 1239 return ret; 1240 } 1241 1242 int 1243 xhci_intr1(struct xhci_softc * const sc) 1244 { 1245 uint32_t usbsts; 1246 uint32_t iman; 1247 1248 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1249 1250 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1251 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1252 #if 0 1253 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1254 return 0; 1255 } 1256 #endif 1257 xhci_op_write_4(sc, XHCI_USBSTS, 1258 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1259 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1260 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1261 1262 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1263 DPRINTFN(16, "IMAN0 %08jx", iman, 0, 0, 0); 1264 iman |= XHCI_IMAN_INTR_PEND; 1265 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1266 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1267 DPRINTFN(16, "IMAN0 %08jx", iman, 0, 0, 0); 1268 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1269 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1270 1271 return 1; 1272 } 1273 1274 /* 1275 * 3 port speed types used in USB stack 1276 * 1277 * usbdi speed 1278 * definition: USB_SPEED_* in usb.h 1279 * They are used in struct usbd_device in USB stack. 1280 * ioctl interface uses these values too. 1281 * port_status speed 1282 * definition: UPS_*_SPEED in usb.h 1283 * They are used in usb_port_status_t and valid only for USB 2.0. 1284 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1285 * of usb_port_status_ext_t indicates port speed. 1286 * Note that some 3.0 values overlap with 2.0 values. 1287 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1288 * means UPS_LOW_SPEED in HS.) 1289 * port status returned from hub also uses these values. 1290 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1291 * or more. 1292 * xspeed: 1293 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1294 * They are used in only slot context and PORTSC reg of xhci. 1295 * The difference between usbdi speed and xspeed is 1296 * that FS and LS values are swapped. 1297 */ 1298 1299 /* convert usbdi speed to xspeed */ 1300 static int 1301 xhci_speed2xspeed(int speed) 1302 { 1303 switch (speed) { 1304 case USB_SPEED_LOW: return 2; 1305 case USB_SPEED_FULL: return 1; 1306 default: return speed; 1307 } 1308 } 1309 1310 #if 0 1311 /* convert xspeed to usbdi speed */ 1312 static int 1313 xhci_xspeed2speed(int xspeed) 1314 { 1315 switch (xspeed) { 1316 case 1: return USB_SPEED_FULL; 1317 case 2: return USB_SPEED_LOW; 1318 default: return xspeed; 1319 } 1320 } 1321 #endif 1322 1323 /* convert xspeed to port status speed */ 1324 static int 1325 xhci_xspeed2psspeed(int xspeed) 1326 { 1327 switch (xspeed) { 1328 case 0: return 0; 1329 case 1: return UPS_FULL_SPEED; 1330 case 2: return UPS_LOW_SPEED; 1331 case 3: return UPS_HIGH_SPEED; 1332 default: return UPS_OTHER_SPEED; 1333 } 1334 } 1335 1336 /* 1337 * Construct input contexts and issue TRB to open pipe. 1338 */ 1339 static usbd_status 1340 xhci_configure_endpoint(struct usbd_pipe *pipe) 1341 { 1342 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1343 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1344 #ifdef XHCI_DEBUG 1345 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1346 #endif 1347 struct xhci_trb trb; 1348 usbd_status err; 1349 1350 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1351 DPRINTFN(4, "slot %ju dci %ju epaddr 0x%02jx attr 0x%02jx", 1352 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1353 pipe->up_endpoint->ue_edesc->bmAttributes); 1354 1355 /* XXX ensure input context is available? */ 1356 1357 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1358 1359 /* set up context */ 1360 xhci_setup_ctx(pipe); 1361 1362 HEXDUMP("input control context", xhci_slot_get_icv(sc, xs, 0), 1363 sc->sc_ctxsz * 1); 1364 HEXDUMP("input endpoint context", xhci_slot_get_icv(sc, xs, 1365 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1366 1367 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1368 trb.trb_2 = 0; 1369 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1370 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1371 1372 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1373 1374 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1375 HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, dci), 1376 sc->sc_ctxsz * 1); 1377 1378 return err; 1379 } 1380 1381 #if 0 1382 static usbd_status 1383 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1384 { 1385 #ifdef USB_DEBUG 1386 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1387 #endif 1388 1389 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1390 DPRINTFN(4, "slot %ju", xs->xs_idx, 0, 0, 0); 1391 1392 return USBD_NORMAL_COMPLETION; 1393 } 1394 #endif 1395 1396 /* 4.6.8, 6.4.3.7 */ 1397 static usbd_status 1398 xhci_reset_endpoint_locked(struct usbd_pipe *pipe) 1399 { 1400 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1401 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1402 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1403 struct xhci_trb trb; 1404 usbd_status err; 1405 1406 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1407 DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1408 1409 KASSERT(mutex_owned(&sc->sc_lock)); 1410 1411 trb.trb_0 = 0; 1412 trb.trb_2 = 0; 1413 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1414 XHCI_TRB_3_EP_SET(dci) | 1415 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1416 1417 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1418 1419 return err; 1420 } 1421 1422 static usbd_status 1423 xhci_reset_endpoint(struct usbd_pipe *pipe) 1424 { 1425 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1426 1427 mutex_enter(&sc->sc_lock); 1428 usbd_status ret = xhci_reset_endpoint_locked(pipe); 1429 mutex_exit(&sc->sc_lock); 1430 1431 return ret; 1432 } 1433 1434 /* 1435 * 4.6.9, 6.4.3.8 1436 * Stop execution of TDs on xfer ring. 1437 * Should be called with sc_lock held. 1438 */ 1439 static usbd_status 1440 xhci_stop_endpoint(struct usbd_pipe *pipe) 1441 { 1442 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1443 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1444 struct xhci_trb trb; 1445 usbd_status err; 1446 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1447 1448 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1449 DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1450 1451 KASSERT(mutex_owned(&sc->sc_lock)); 1452 1453 trb.trb_0 = 0; 1454 trb.trb_2 = 0; 1455 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1456 XHCI_TRB_3_EP_SET(dci) | 1457 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1458 1459 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1460 1461 return err; 1462 } 1463 1464 /* 1465 * Set TR Dequeue Pointer. 1466 * xHCI 1.1 4.6.10 6.4.3.9 1467 * Purge all of the TRBs on ring and reinitialize ring. 1468 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1469 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1470 * error will be generated. 1471 */ 1472 static usbd_status 1473 xhci_set_dequeue_locked(struct usbd_pipe *pipe) 1474 { 1475 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1476 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1477 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1478 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1479 struct xhci_trb trb; 1480 usbd_status err; 1481 1482 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1483 DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1484 1485 KASSERT(mutex_owned(&sc->sc_lock)); 1486 1487 xhci_host_dequeue(xr); 1488 1489 /* set DCS */ 1490 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1491 trb.trb_2 = 0; 1492 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1493 XHCI_TRB_3_EP_SET(dci) | 1494 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1495 1496 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1497 1498 return err; 1499 } 1500 1501 static usbd_status 1502 xhci_set_dequeue(struct usbd_pipe *pipe) 1503 { 1504 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1505 1506 mutex_enter(&sc->sc_lock); 1507 usbd_status ret = xhci_set_dequeue_locked(pipe); 1508 mutex_exit(&sc->sc_lock); 1509 1510 return ret; 1511 } 1512 1513 /* 1514 * Open new pipe: called from usbd_setup_pipe_flags. 1515 * Fills methods of pipe. 1516 * If pipe is not for ep0, calls configure_endpoint. 1517 */ 1518 static usbd_status 1519 xhci_open(struct usbd_pipe *pipe) 1520 { 1521 struct usbd_device * const dev = pipe->up_dev; 1522 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1523 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1524 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1525 1526 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1527 DPRINTFN(1, "addr %jd depth %jd port %jd speed %jd", dev->ud_addr, 1528 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1529 DPRINTFN(1, " dci %ju type 0x%02jx epaddr 0x%02jx attr 0x%02jx", 1530 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1531 ed->bmAttributes); 1532 DPRINTFN(1, " mps %ju ival %ju", UGETW(ed->wMaxPacketSize), 1533 ed->bInterval, 0, 0); 1534 1535 if (sc->sc_dying) 1536 return USBD_IOERROR; 1537 1538 /* Root Hub */ 1539 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1540 switch (ed->bEndpointAddress) { 1541 case USB_CONTROL_ENDPOINT: 1542 pipe->up_methods = &roothub_ctrl_methods; 1543 break; 1544 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1545 pipe->up_methods = &xhci_root_intr_methods; 1546 break; 1547 default: 1548 pipe->up_methods = NULL; 1549 DPRINTFN(0, "bad bEndpointAddress 0x%02jx", 1550 ed->bEndpointAddress, 0, 0, 0); 1551 return USBD_INVAL; 1552 } 1553 return USBD_NORMAL_COMPLETION; 1554 } 1555 1556 switch (xfertype) { 1557 case UE_CONTROL: 1558 pipe->up_methods = &xhci_device_ctrl_methods; 1559 break; 1560 case UE_ISOCHRONOUS: 1561 pipe->up_methods = &xhci_device_isoc_methods; 1562 return USBD_INVAL; 1563 break; 1564 case UE_BULK: 1565 pipe->up_methods = &xhci_device_bulk_methods; 1566 break; 1567 case UE_INTERRUPT: 1568 pipe->up_methods = &xhci_device_intr_methods; 1569 break; 1570 default: 1571 return USBD_IOERROR; 1572 break; 1573 } 1574 1575 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1576 return xhci_configure_endpoint(pipe); 1577 1578 return USBD_NORMAL_COMPLETION; 1579 } 1580 1581 /* 1582 * Closes pipe, called from usbd_kill_pipe via close methods. 1583 * If the endpoint to be closed is ep0, disable_slot. 1584 * Should be called with sc_lock held. 1585 */ 1586 static void 1587 xhci_close_pipe(struct usbd_pipe *pipe) 1588 { 1589 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1590 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1591 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1592 const u_int dci = xhci_ep_get_dci(ed); 1593 struct xhci_trb trb; 1594 uint32_t *cp; 1595 1596 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1597 1598 if (sc->sc_dying) 1599 return; 1600 1601 /* xs is uninitialized before xhci_init_slot */ 1602 if (xs == NULL || xs->xs_idx == 0) 1603 return; 1604 1605 DPRINTFN(4, "pipe %#jx slot %ju dci %ju", (uintptr_t)pipe, xs->xs_idx, 1606 dci, 0); 1607 1608 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1609 KASSERT(mutex_owned(&sc->sc_lock)); 1610 1611 if (pipe->up_dev->ud_depth == 0) 1612 return; 1613 1614 if (dci == XHCI_DCI_EP_CONTROL) { 1615 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1616 xhci_disable_slot(sc, xs->xs_idx); 1617 return; 1618 } 1619 1620 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED) 1621 (void)xhci_stop_endpoint(pipe); 1622 1623 /* 1624 * set appropriate bit to be dropped. 1625 * don't set DC bit to 1, otherwise all endpoints 1626 * would be deconfigured. 1627 */ 1628 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1629 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1630 cp[1] = htole32(0); 1631 1632 /* XXX should be most significant one, not dci? */ 1633 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1634 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1635 1636 /* configure ep context performs an implicit dequeue */ 1637 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 1638 1639 /* sync input contexts before they are read from memory */ 1640 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1641 1642 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1643 trb.trb_2 = 0; 1644 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1645 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1646 1647 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1648 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1649 } 1650 1651 /* 1652 * Abort transfer. 1653 * Should be called with sc_lock held. 1654 */ 1655 static void 1656 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1657 { 1658 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1659 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1660 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1661 1662 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1663 DPRINTFN(4, "xfer %#jx pipe %#jx status %jd", 1664 (uintptr_t)xfer, (uintptr_t)xfer->ux_pipe, status, 0); 1665 1666 KASSERT(mutex_owned(&sc->sc_lock)); 1667 1668 if (sc->sc_dying) { 1669 /* If we're dying, just do the software part. */ 1670 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 1671 xfer->ux_status, 0, 0); 1672 xfer->ux_status = status; 1673 callout_stop(&xfer->ux_callout); 1674 usb_transfer_complete(xfer); 1675 return; 1676 } 1677 1678 /* 1679 * If an abort is already in progress then just wait for it to 1680 * complete and return. 1681 */ 1682 if (xfer->ux_hcflags & UXFER_ABORTING) { 1683 DPRINTFN(4, "already aborting", 0, 0, 0, 0); 1684 #ifdef DIAGNOSTIC 1685 if (status == USBD_TIMEOUT) 1686 DPRINTFN(4, "TIMEOUT while aborting", 0, 0, 0, 0); 1687 #endif 1688 /* Override the status which might be USBD_TIMEOUT. */ 1689 xfer->ux_status = status; 1690 DPRINTFN(4, "xfer %#jx waiting for abort to finish", 1691 (uintptr_t)xfer, 0, 0, 0); 1692 xfer->ux_hcflags |= UXFER_ABORTWAIT; 1693 while (xfer->ux_hcflags & UXFER_ABORTING) 1694 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 1695 return; 1696 } 1697 xfer->ux_hcflags |= UXFER_ABORTING; 1698 1699 /* 1700 * Step 1: Stop xfer timeout timer. 1701 */ 1702 xfer->ux_status = status; 1703 callout_stop(&xfer->ux_callout); 1704 1705 /* 1706 * Step 2: Stop execution of TD on the ring. 1707 */ 1708 switch (xhci_get_epstate(sc, xs, dci)) { 1709 case XHCI_EPSTATE_HALTED: 1710 (void)xhci_reset_endpoint_locked(xfer->ux_pipe); 1711 break; 1712 case XHCI_EPSTATE_STOPPED: 1713 break; 1714 default: 1715 (void)xhci_stop_endpoint(xfer->ux_pipe); 1716 break; 1717 } 1718 #ifdef DIAGNOSTIC 1719 uint32_t epst = xhci_get_epstate(sc, xs, dci); 1720 if (epst != XHCI_EPSTATE_STOPPED) 1721 DPRINTFN(4, "dci %ju not stopped %ju", dci, epst, 0, 0); 1722 #endif 1723 1724 /* 1725 * Step 3: Remove any vestiges of the xfer from the ring. 1726 */ 1727 xhci_set_dequeue_locked(xfer->ux_pipe); 1728 1729 /* 1730 * Step 4: Notify completion to waiting xfers. 1731 */ 1732 int wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 1733 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 1734 usb_transfer_complete(xfer); 1735 if (wake) { 1736 cv_broadcast(&xfer->ux_hccv); 1737 } 1738 DPRINTFN(14, "end", 0, 0, 0, 0); 1739 1740 KASSERT(mutex_owned(&sc->sc_lock)); 1741 } 1742 1743 static void 1744 xhci_host_dequeue(struct xhci_ring * const xr) 1745 { 1746 /* When dequeueing the controller, update our struct copy too */ 1747 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1748 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1749 BUS_DMASYNC_PREWRITE); 1750 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1751 1752 xr->xr_ep = 0; 1753 xr->xr_cs = 1; 1754 } 1755 1756 /* 1757 * Recover STALLed endpoint. 1758 * xHCI 1.1 sect 4.10.2.1 1759 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1760 * all transfers on transfer ring. 1761 * These are done in thread context asynchronously. 1762 */ 1763 static void 1764 xhci_clear_endpoint_stall_async_task(void *cookie) 1765 { 1766 struct usbd_xfer * const xfer = cookie; 1767 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1768 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1769 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1770 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1771 1772 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1773 DPRINTFN(4, "xfer %#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, 1774 dci, 0); 1775 1776 xhci_reset_endpoint(xfer->ux_pipe); 1777 xhci_set_dequeue(xfer->ux_pipe); 1778 1779 mutex_enter(&sc->sc_lock); 1780 tr->is_halted = false; 1781 usb_transfer_complete(xfer); 1782 mutex_exit(&sc->sc_lock); 1783 DPRINTFN(4, "ends", 0, 0, 0, 0); 1784 } 1785 1786 static usbd_status 1787 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1788 { 1789 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1790 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1791 1792 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1793 DPRINTFN(4, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 1794 1795 if (sc->sc_dying) { 1796 return USBD_IOERROR; 1797 } 1798 1799 usb_init_task(&xp->xp_async_task, 1800 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1801 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1802 DPRINTFN(4, "ends", 0, 0, 0, 0); 1803 1804 return USBD_NORMAL_COMPLETION; 1805 } 1806 1807 /* Process roothub port status/change events and notify to uhub_intr. */ 1808 static void 1809 xhci_rhpsc(struct xhci_softc * const sc, u_int ctlrport) 1810 { 1811 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1812 DPRINTFN(4, "xhci%jd: port %ju status change", device_unit(sc->sc_dev), 1813 ctlrport, 0, 0); 1814 1815 if (ctlrport > sc->sc_maxports) 1816 return; 1817 1818 const size_t bn = xhci_ctlrport2bus(sc, ctlrport); 1819 const size_t rhp = xhci_ctlrport2rhport(sc, ctlrport); 1820 struct usbd_xfer * const xfer = sc->sc_intrxfer[bn]; 1821 1822 DPRINTFN(4, "xhci%jd: bus %jd bp %ju xfer %#jx status change", 1823 device_unit(sc->sc_dev), bn, rhp, (uintptr_t)xfer); 1824 1825 if (xfer == NULL) 1826 return; 1827 1828 uint8_t *p = xfer->ux_buf; 1829 memset(p, 0, xfer->ux_length); 1830 p[rhp / NBBY] |= 1 << (rhp % NBBY); 1831 xfer->ux_actlen = xfer->ux_length; 1832 xfer->ux_status = USBD_NORMAL_COMPLETION; 1833 usb_transfer_complete(xfer); 1834 } 1835 1836 /* Process Transfer Events */ 1837 static void 1838 xhci_event_transfer(struct xhci_softc * const sc, 1839 const struct xhci_trb * const trb) 1840 { 1841 uint64_t trb_0; 1842 uint32_t trb_2, trb_3; 1843 uint8_t trbcode; 1844 u_int slot, dci; 1845 struct xhci_slot *xs; 1846 struct xhci_ring *xr; 1847 struct xhci_xfer *xx; 1848 struct usbd_xfer *xfer; 1849 usbd_status err; 1850 1851 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1852 1853 trb_0 = le64toh(trb->trb_0); 1854 trb_2 = le32toh(trb->trb_2); 1855 trb_3 = le32toh(trb->trb_3); 1856 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1857 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1858 dci = XHCI_TRB_3_EP_GET(trb_3); 1859 xs = &sc->sc_slots[slot]; 1860 xr = &xs->xs_ep[dci].xe_tr; 1861 1862 /* sanity check */ 1863 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1864 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1865 1866 int idx = 0; 1867 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1868 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1869 DPRINTFN(0, "invalid trb_0 0x%jx", trb_0, 0, 0, 0); 1870 return; 1871 } 1872 xx = xr->xr_cookies[idx]; 1873 1874 /* clear cookie of consumed TRB */ 1875 xr->xr_cookies[idx] = NULL; 1876 1877 /* 1878 * xx is NULL if pipe is opened but xfer is not started. 1879 * It happens when stopping idle pipe. 1880 */ 1881 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1882 DPRINTFN(1, "Ignore #%ju: cookie %#jx cc %ju dci %ju", 1883 idx, (uintptr_t)xx, trbcode, dci); 1884 DPRINTFN(1, " orig TRB %jx type %ju", trb_0, 1885 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1886 0, 0); 1887 return; 1888 } 1889 } else { 1890 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1891 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1892 } 1893 /* XXX this may not happen */ 1894 if (xx == NULL) { 1895 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1896 return; 1897 } 1898 xfer = &xx->xx_xfer; 1899 /* XXX this may happen when detaching */ 1900 if (xfer == NULL) { 1901 DPRINTFN(1, "xx(%#jx)->xx_xfer is NULL trb_0 %#jx", 1902 (uintptr_t)xx, trb_0, 0, 0); 1903 return; 1904 } 1905 DPRINTFN(14, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 1906 /* XXX I dunno why this happens */ 1907 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1908 1909 if (!xfer->ux_pipe->up_repeat && 1910 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1911 DPRINTFN(1, "xfer(%#jx)->pipe not queued", (uintptr_t)xfer, 1912 0, 0, 0); 1913 return; 1914 } 1915 1916 /* 4.11.5.2 Event Data TRB */ 1917 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1918 DPRINTFN(14, "transfer Event Data: 0x%016jx 0x%08jx" 1919 " %02jx", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1920 if ((trb_0 & 0x3) == 0x3) { 1921 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1922 } 1923 } 1924 1925 switch (trbcode) { 1926 case XHCI_TRB_ERROR_SHORT_PKT: 1927 case XHCI_TRB_ERROR_SUCCESS: 1928 /* 1929 * A ctrl transfer can generate two events if it has a Data 1930 * stage. A short data stage can be OK and should not 1931 * complete the transfer as the status stage needs to be 1932 * performed. 1933 * 1934 * Note: Data and Status stage events point at same xfer. 1935 * ux_actlen and ux_dmabuf will be passed to 1936 * usb_transfer_complete after the Status stage event. 1937 * 1938 * It can be distingished which stage generates the event: 1939 * + by checking least 3 bits of trb_0 if ED==1. 1940 * (see xhci_device_ctrl_start). 1941 * + by checking the type of original TRB if ED==0. 1942 * 1943 * In addition, intr, bulk, and isoc transfer currently 1944 * consists of single TD, so the "skip" is not needed. 1945 * ctrl xfer uses EVENT_DATA, and others do not. 1946 * Thus driver can switch the flow by checking ED bit. 1947 */ 1948 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1949 if (xfer->ux_actlen == 0) 1950 xfer->ux_actlen = xfer->ux_length - 1951 XHCI_TRB_2_REM_GET(trb_2); 1952 if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)) 1953 == XHCI_TRB_TYPE_DATA_STAGE) { 1954 return; 1955 } 1956 } else if ((trb_0 & 0x3) == 0x3) { 1957 return; 1958 } 1959 err = USBD_NORMAL_COMPLETION; 1960 break; 1961 case XHCI_TRB_ERROR_STOPPED: 1962 case XHCI_TRB_ERROR_LENGTH: 1963 case XHCI_TRB_ERROR_STOPPED_SHORT: 1964 /* 1965 * don't complete the transfer being aborted 1966 * as abort_xfer does instead. 1967 */ 1968 if (xfer->ux_hcflags & UXFER_ABORTING) { 1969 DPRINTFN(14, "ignore aborting xfer %#jx", 1970 (uintptr_t)xfer, 0, 0, 0); 1971 return; 1972 } 1973 err = USBD_CANCELLED; 1974 break; 1975 case XHCI_TRB_ERROR_STALL: 1976 case XHCI_TRB_ERROR_BABBLE: 1977 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 1978 xr->is_halted = true; 1979 err = USBD_STALLED; 1980 /* 1981 * Stalled endpoints can be recoverd by issuing 1982 * command TRB TYPE_RESET_EP on xHCI instead of 1983 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1984 * on the endpoint. However, this function may be 1985 * called from softint context (e.g. from umass), 1986 * in that case driver gets KASSERT in cv_timedwait 1987 * in xhci_do_command. 1988 * To avoid this, this runs reset_endpoint and 1989 * usb_transfer_complete in usb task thread 1990 * asynchronously (and then umass issues clear 1991 * UF_ENDPOINT_HALT). 1992 */ 1993 xfer->ux_status = err; 1994 callout_stop(&xfer->ux_callout); 1995 xhci_clear_endpoint_stall_async(xfer); 1996 return; 1997 default: 1998 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 1999 err = USBD_IOERROR; 2000 break; 2001 } 2002 xfer->ux_status = err; 2003 2004 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 2005 if ((trb_0 & 0x3) == 0x0) { 2006 callout_stop(&xfer->ux_callout); 2007 usb_transfer_complete(xfer); 2008 } 2009 } else { 2010 callout_stop(&xfer->ux_callout); 2011 usb_transfer_complete(xfer); 2012 } 2013 } 2014 2015 /* Process Command complete events */ 2016 static void 2017 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 2018 { 2019 uint64_t trb_0; 2020 uint32_t trb_2, trb_3; 2021 2022 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2023 2024 KASSERT(mutex_owned(&sc->sc_lock)); 2025 2026 trb_0 = le64toh(trb->trb_0); 2027 trb_2 = le32toh(trb->trb_2); 2028 trb_3 = le32toh(trb->trb_3); 2029 2030 if (trb_0 == sc->sc_command_addr) { 2031 sc->sc_resultpending = false; 2032 2033 sc->sc_result_trb.trb_0 = trb_0; 2034 sc->sc_result_trb.trb_2 = trb_2; 2035 sc->sc_result_trb.trb_3 = trb_3; 2036 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2037 XHCI_TRB_ERROR_SUCCESS) { 2038 DPRINTFN(1, "command completion " 2039 "failure: 0x%016jx 0x%08jx 0x%08jx", 2040 trb_0, trb_2, trb_3, 0); 2041 } 2042 cv_signal(&sc->sc_command_cv); 2043 } else { 2044 DPRINTFN(1, "spurious event: %#jx 0x%016jx " 2045 "0x%08jx 0x%08jx", (uintptr_t)trb, trb_0, trb_2, trb_3); 2046 } 2047 } 2048 2049 /* 2050 * Process events. 2051 * called from xhci_softintr 2052 */ 2053 static void 2054 xhci_handle_event(struct xhci_softc * const sc, 2055 const struct xhci_trb * const trb) 2056 { 2057 uint64_t trb_0; 2058 uint32_t trb_2, trb_3; 2059 2060 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2061 2062 trb_0 = le64toh(trb->trb_0); 2063 trb_2 = le32toh(trb->trb_2); 2064 trb_3 = le32toh(trb->trb_3); 2065 2066 DPRINTFN(14, "event: %#jx 0x%016jx 0x%08jx 0x%08jx", 2067 (uintptr_t)trb, trb_0, trb_2, trb_3); 2068 2069 /* 2070 * 4.11.3.1, 6.4.2.1 2071 * TRB Pointer is invalid for these completion codes. 2072 */ 2073 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2074 case XHCI_TRB_ERROR_RING_UNDERRUN: 2075 case XHCI_TRB_ERROR_RING_OVERRUN: 2076 case XHCI_TRB_ERROR_VF_RING_FULL: 2077 return; 2078 default: 2079 if (trb_0 == 0) { 2080 return; 2081 } 2082 break; 2083 } 2084 2085 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2086 case XHCI_TRB_EVENT_TRANSFER: 2087 xhci_event_transfer(sc, trb); 2088 break; 2089 case XHCI_TRB_EVENT_CMD_COMPLETE: 2090 xhci_event_cmd(sc, trb); 2091 break; 2092 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2093 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2094 break; 2095 default: 2096 break; 2097 } 2098 } 2099 2100 static void 2101 xhci_softintr(void *v) 2102 { 2103 struct usbd_bus * const bus = v; 2104 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2105 struct xhci_ring * const er = &sc->sc_er; 2106 struct xhci_trb *trb; 2107 int i, j, k; 2108 2109 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2110 2111 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 2112 2113 i = er->xr_ep; 2114 j = er->xr_cs; 2115 2116 DPRINTFN(16, "er: xr_ep %jd xr_cs %jd", i, j, 0, 0); 2117 2118 while (1) { 2119 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2120 BUS_DMASYNC_POSTREAD); 2121 trb = &er->xr_trb[i]; 2122 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2123 2124 if (j != k) 2125 break; 2126 2127 xhci_handle_event(sc, trb); 2128 2129 i++; 2130 if (i == er->xr_ntrb) { 2131 i = 0; 2132 j ^= 1; 2133 } 2134 } 2135 2136 er->xr_ep = i; 2137 er->xr_cs = j; 2138 2139 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2140 XHCI_ERDP_LO_BUSY); 2141 2142 DPRINTFN(16, "ends", 0, 0, 0, 0); 2143 2144 return; 2145 } 2146 2147 static void 2148 xhci_poll(struct usbd_bus *bus) 2149 { 2150 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2151 2152 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2153 2154 mutex_spin_enter(&sc->sc_intr_lock); 2155 int ret = xhci_intr1(sc); 2156 if (ret) { 2157 xhci_softintr(bus); 2158 } 2159 mutex_spin_exit(&sc->sc_intr_lock); 2160 2161 return; 2162 } 2163 2164 static struct usbd_xfer * 2165 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2166 { 2167 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2168 struct usbd_xfer *xfer; 2169 2170 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2171 2172 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 2173 if (xfer != NULL) { 2174 memset(xfer, 0, sizeof(struct xhci_xfer)); 2175 #ifdef DIAGNOSTIC 2176 xfer->ux_state = XFER_BUSY; 2177 #endif 2178 } 2179 2180 return xfer; 2181 } 2182 2183 static void 2184 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2185 { 2186 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2187 2188 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2189 2190 #ifdef DIAGNOSTIC 2191 if (xfer->ux_state != XFER_BUSY) { 2192 DPRINTFN(0, "xfer=%#jx not busy, 0x%08jx", 2193 (uintptr_t)xfer, xfer->ux_state, 0, 0); 2194 } 2195 xfer->ux_state = XFER_FREE; 2196 #endif 2197 pool_cache_put(sc->sc_xferpool, xfer); 2198 } 2199 2200 static void 2201 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2202 { 2203 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2204 2205 *lock = &sc->sc_lock; 2206 } 2207 2208 extern uint32_t usb_cookie_no; 2209 2210 /* 2211 * xHCI 4.3 2212 * Called when uhub_explore finds a new device (via usbd_new_device). 2213 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2214 * This function does: 2215 * Allocate and construct dev structure of default endpoint (ep0). 2216 * Allocate and open pipe of ep0. 2217 * Enable slot and initialize slot context. 2218 * Set Address. 2219 * Read initial device descriptor. 2220 * Determine initial MaxPacketSize (mps) by speed. 2221 * Read full device descriptor. 2222 * Register this device. 2223 * Finally state of device transitions ADDRESSED. 2224 */ 2225 static usbd_status 2226 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2227 int speed, int port, struct usbd_port *up) 2228 { 2229 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2230 struct usbd_device *dev; 2231 usbd_status err; 2232 usb_device_descriptor_t *dd; 2233 struct xhci_slot *xs; 2234 uint32_t *cp; 2235 2236 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2237 DPRINTFN(4, "port %ju depth %ju speed %ju up %#jx", 2238 port, depth, speed, (uintptr_t)up); 2239 2240 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2241 dev->ud_bus = bus; 2242 dev->ud_quirks = &usbd_no_quirk; 2243 dev->ud_addr = 0; 2244 dev->ud_ddesc.bMaxPacketSize = 0; 2245 dev->ud_depth = depth; 2246 dev->ud_powersrc = up; 2247 dev->ud_myhub = up->up_parent; 2248 dev->ud_speed = speed; 2249 dev->ud_langid = USBD_NOLANG; 2250 dev->ud_cookie.cookie = ++usb_cookie_no; 2251 2252 /* Set up default endpoint handle. */ 2253 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2254 /* doesn't matter, just don't let it uninitialized */ 2255 dev->ud_ep0.ue_toggle = 0; 2256 2257 /* Set up default endpoint descriptor. */ 2258 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2259 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2260 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2261 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2262 dev->ud_ep0desc.bInterval = 0; 2263 2264 /* 4.3, 4.8.2.1 */ 2265 switch (speed) { 2266 case USB_SPEED_SUPER: 2267 case USB_SPEED_SUPER_PLUS: 2268 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2269 break; 2270 case USB_SPEED_FULL: 2271 /* XXX using 64 as initial mps of ep0 in FS */ 2272 case USB_SPEED_HIGH: 2273 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2274 break; 2275 case USB_SPEED_LOW: 2276 default: 2277 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2278 break; 2279 } 2280 2281 up->up_dev = dev; 2282 2283 /* Establish the default pipe. */ 2284 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2285 &dev->ud_pipe0); 2286 if (err) { 2287 goto bad; 2288 } 2289 2290 dd = &dev->ud_ddesc; 2291 2292 if (depth == 0 && port == 0) { 2293 KASSERT(bus->ub_devices[USB_ROOTHUB_INDEX] == NULL); 2294 bus->ub_devices[USB_ROOTHUB_INDEX] = dev; 2295 err = usbd_get_initial_ddesc(dev, dd); 2296 if (err) { 2297 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2298 goto bad; 2299 } 2300 2301 err = usbd_reload_device_desc(dev); 2302 if (err) { 2303 DPRINTFN(1, "reload desc %ju", err, 0, 0, 0); 2304 goto bad; 2305 } 2306 } else { 2307 uint8_t slot = 0; 2308 2309 /* 4.3.2 */ 2310 err = xhci_enable_slot(sc, &slot); 2311 if (err) { 2312 DPRINTFN(1, "enable slot %ju", err, 0, 0, 0); 2313 goto bad; 2314 } 2315 2316 xs = &sc->sc_slots[slot]; 2317 dev->ud_hcpriv = xs; 2318 2319 /* 4.3.3 initialize slot structure */ 2320 err = xhci_init_slot(dev, slot); 2321 if (err) { 2322 DPRINTFN(1, "init slot %ju", err, 0, 0, 0); 2323 dev->ud_hcpriv = NULL; 2324 /* 2325 * We have to disable_slot here because 2326 * xs->xs_idx == 0 when xhci_init_slot fails, 2327 * in that case usbd_remove_dev won't work. 2328 */ 2329 mutex_enter(&sc->sc_lock); 2330 xhci_disable_slot(sc, slot); 2331 mutex_exit(&sc->sc_lock); 2332 goto bad; 2333 } 2334 2335 /* 4.3.4 Address Assignment */ 2336 err = xhci_set_address(dev, slot, false); 2337 if (err) { 2338 DPRINTFN(1, "set address w/o bsr %ju", err, 0, 0, 0); 2339 goto bad; 2340 } 2341 2342 /* Allow device time to set new address */ 2343 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2344 2345 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2346 HEXDUMP("slot context", cp, sc->sc_ctxsz); 2347 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3])); 2348 DPRINTFN(4, "device address %ju", addr, 0, 0, 0); 2349 /* 2350 * XXX ensure we know when the hardware does something 2351 * we can't yet cope with 2352 */ 2353 KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr); 2354 dev->ud_addr = addr; 2355 2356 KASSERTMSG(bus->ub_devices[usb_addr2dindex(dev->ud_addr)] == NULL, 2357 "addr %d already allocated", dev->ud_addr); 2358 /* 2359 * The root hub is given its own slot 2360 */ 2361 bus->ub_devices[usb_addr2dindex(dev->ud_addr)] = dev; 2362 2363 err = usbd_get_initial_ddesc(dev, dd); 2364 if (err) { 2365 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2366 goto bad; 2367 } 2368 2369 /* 4.8.2.1 */ 2370 if (USB_IS_SS(speed)) { 2371 if (dd->bMaxPacketSize != 9) { 2372 printf("%s: invalid mps 2^%u for SS ep0," 2373 " using 512\n", 2374 device_xname(sc->sc_dev), 2375 dd->bMaxPacketSize); 2376 dd->bMaxPacketSize = 9; 2377 } 2378 USETW(dev->ud_ep0desc.wMaxPacketSize, 2379 (1 << dd->bMaxPacketSize)); 2380 } else 2381 USETW(dev->ud_ep0desc.wMaxPacketSize, 2382 dd->bMaxPacketSize); 2383 DPRINTFN(4, "bMaxPacketSize %ju", dd->bMaxPacketSize, 0, 0, 0); 2384 err = xhci_update_ep0_mps(sc, xs, 2385 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2386 if (err) { 2387 DPRINTFN(1, "update mps of ep0 %ju", err, 0, 0, 0); 2388 goto bad; 2389 } 2390 2391 err = usbd_reload_device_desc(dev); 2392 if (err) { 2393 DPRINTFN(1, "reload desc %ju", err, 0, 0, 0); 2394 goto bad; 2395 } 2396 } 2397 2398 DPRINTFN(1, "adding unit addr=%jd, rev=%02jx,", 2399 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2400 DPRINTFN(1, " class=%jd, subclass=%jd, protocol=%jd,", 2401 dd->bDeviceClass, dd->bDeviceSubClass, 2402 dd->bDeviceProtocol, 0); 2403 DPRINTFN(1, " mps=%jd, len=%jd, noconf=%jd, speed=%jd", 2404 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2405 dev->ud_speed); 2406 2407 usbd_get_device_strings(dev); 2408 2409 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2410 2411 if (depth == 0 && port == 0) { 2412 usbd_attach_roothub(parent, dev); 2413 DPRINTFN(1, "root hub %#jx", (uintptr_t)dev, 0, 0, 0); 2414 return USBD_NORMAL_COMPLETION; 2415 } 2416 2417 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2418 bad: 2419 if (err != USBD_NORMAL_COMPLETION) { 2420 usbd_remove_device(dev, up); 2421 } 2422 2423 return err; 2424 } 2425 2426 static usbd_status 2427 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2428 size_t ntrb, size_t align) 2429 { 2430 usbd_status err; 2431 size_t size = ntrb * XHCI_TRB_SIZE; 2432 2433 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2434 2435 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2436 if (err) 2437 return err; 2438 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2439 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2440 xr->xr_trb = xhci_ring_trbv(xr, 0); 2441 xr->xr_ntrb = ntrb; 2442 xr->is_halted = false; 2443 xhci_host_dequeue(xr); 2444 2445 return USBD_NORMAL_COMPLETION; 2446 } 2447 2448 static void 2449 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2450 { 2451 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2452 mutex_destroy(&xr->xr_lock); 2453 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2454 } 2455 2456 static void 2457 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2458 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2459 { 2460 size_t i; 2461 u_int ri; 2462 u_int cs; 2463 uint64_t parameter; 2464 uint32_t status; 2465 uint32_t control; 2466 2467 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2468 2469 KASSERTMSG(ntrbs <= XHCI_XFER_NTRB, "ntrbs %zu", ntrbs); 2470 for (i = 0; i < ntrbs; i++) { 2471 DPRINTFN(12, "xr %#jx trbs %#jx num %ju", (uintptr_t)xr, 2472 (uintptr_t)trbs, i, 0); 2473 DPRINTFN(12, " %016jx %08jx %08jx", 2474 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2475 KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2476 XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3); 2477 } 2478 2479 DPRINTFN(12, "%#jx xr_ep 0x%jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep, 2480 xr->xr_cs, 0); 2481 2482 ri = xr->xr_ep; 2483 cs = xr->xr_cs; 2484 2485 /* 2486 * Although the xhci hardware can do scatter/gather dma from 2487 * arbitrary sized buffers, there is a non-obvious restriction 2488 * that a LINK trb is only allowed at the end of a burst of 2489 * transfers - which might be 16kB. 2490 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2491 * The simple solution is not to allow a LINK trb in the middle 2492 * of anything - as here. 2493 * XXX: (dsl) There are xhci controllers out there (eg some made by 2494 * ASMedia) that seem to lock up if they process a LINK trb but 2495 * cannot process the linked-to trb yet. 2496 * The code should write the 'cycle' bit on the link trb AFTER 2497 * adding the other trb. 2498 */ 2499 u_int firstep = xr->xr_ep; 2500 u_int firstcs = xr->xr_cs; 2501 2502 for (i = 0; i < ntrbs; ) { 2503 u_int oldri = ri; 2504 u_int oldcs = cs; 2505 2506 if (ri >= (xr->xr_ntrb - 1)) { 2507 /* Put Link TD at the end of ring */ 2508 parameter = xhci_ring_trbp(xr, 0); 2509 status = 0; 2510 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2511 XHCI_TRB_3_TC_BIT; 2512 xr->xr_cookies[ri] = NULL; 2513 xr->xr_ep = 0; 2514 xr->xr_cs ^= 1; 2515 ri = xr->xr_ep; 2516 cs = xr->xr_cs; 2517 } else { 2518 parameter = trbs[i].trb_0; 2519 status = trbs[i].trb_2; 2520 control = trbs[i].trb_3; 2521 2522 xr->xr_cookies[ri] = cookie; 2523 ri++; 2524 i++; 2525 } 2526 /* 2527 * If this is a first TRB, mark it invalid to prevent 2528 * xHC from running it immediately. 2529 */ 2530 if (oldri == firstep) { 2531 if (oldcs) { 2532 control &= ~XHCI_TRB_3_CYCLE_BIT; 2533 } else { 2534 control |= XHCI_TRB_3_CYCLE_BIT; 2535 } 2536 } else { 2537 if (oldcs) { 2538 control |= XHCI_TRB_3_CYCLE_BIT; 2539 } else { 2540 control &= ~XHCI_TRB_3_CYCLE_BIT; 2541 } 2542 } 2543 xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control); 2544 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri, 2545 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2546 } 2547 2548 /* Now invert cycle bit of first TRB */ 2549 if (firstcs) { 2550 xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 2551 } else { 2552 xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 2553 } 2554 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep, 2555 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2556 2557 xr->xr_ep = ri; 2558 xr->xr_cs = cs; 2559 2560 DPRINTFN(12, "%#jx xr_ep 0x%jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep, 2561 xr->xr_cs, 0); 2562 } 2563 2564 /* 2565 * Stop execution commands, purge all commands on command ring, and 2566 * rewind dequeue pointer. 2567 */ 2568 static void 2569 xhci_abort_command(struct xhci_softc *sc) 2570 { 2571 struct xhci_ring * const cr = &sc->sc_cr; 2572 uint64_t crcr; 2573 int i; 2574 2575 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2576 DPRINTFN(14, "command %#jx timeout, aborting", 2577 sc->sc_command_addr, 0, 0, 0); 2578 2579 mutex_enter(&cr->xr_lock); 2580 2581 /* 4.6.1.2 Aborting a Command */ 2582 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2583 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2584 2585 for (i = 0; i < 500; i++) { 2586 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2587 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2588 break; 2589 usb_delay_ms(&sc->sc_bus, 1); 2590 } 2591 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2592 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2593 /* reset HC here? */ 2594 } 2595 2596 /* reset command ring dequeue pointer */ 2597 cr->xr_ep = 0; 2598 cr->xr_cs = 1; 2599 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2600 2601 mutex_exit(&cr->xr_lock); 2602 } 2603 2604 /* 2605 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2606 * Command completion is notified by cv_signal from xhci_event_cmd() 2607 * (called from xhci_softint), or timed-out. 2608 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2609 * then do_command examines it. 2610 */ 2611 static usbd_status 2612 xhci_do_command_locked(struct xhci_softc * const sc, 2613 struct xhci_trb * const trb, int timeout) 2614 { 2615 struct xhci_ring * const cr = &sc->sc_cr; 2616 usbd_status err; 2617 2618 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2619 DPRINTFN(12, "input: 0x%016jx 0x%08jx 0x%08jx", 2620 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2621 2622 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2623 KASSERT(mutex_owned(&sc->sc_lock)); 2624 2625 while (sc->sc_command_addr != 0) 2626 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 2627 2628 /* 2629 * If enqueue pointer points at last of ring, it's Link TRB, 2630 * command TRB will be stored in 0th TRB. 2631 */ 2632 if (cr->xr_ep == cr->xr_ntrb - 1) 2633 sc->sc_command_addr = xhci_ring_trbp(cr, 0); 2634 else 2635 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2636 2637 sc->sc_resultpending = true; 2638 2639 mutex_enter(&cr->xr_lock); 2640 xhci_ring_put(sc, cr, NULL, trb, 1); 2641 mutex_exit(&cr->xr_lock); 2642 2643 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2644 2645 while (sc->sc_resultpending) { 2646 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2647 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2648 xhci_abort_command(sc); 2649 err = USBD_TIMEOUT; 2650 goto timedout; 2651 } 2652 } 2653 2654 trb->trb_0 = sc->sc_result_trb.trb_0; 2655 trb->trb_2 = sc->sc_result_trb.trb_2; 2656 trb->trb_3 = sc->sc_result_trb.trb_3; 2657 2658 DPRINTFN(12, "output: 0x%016jx 0x%08jx 0x%08jx", 2659 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2660 2661 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2662 case XHCI_TRB_ERROR_SUCCESS: 2663 err = USBD_NORMAL_COMPLETION; 2664 break; 2665 default: 2666 case 192 ... 223: 2667 err = USBD_IOERROR; 2668 break; 2669 case 224 ... 255: 2670 err = USBD_NORMAL_COMPLETION; 2671 break; 2672 } 2673 2674 timedout: 2675 sc->sc_resultpending = false; 2676 sc->sc_command_addr = 0; 2677 cv_broadcast(&sc->sc_cmdbusy_cv); 2678 2679 return err; 2680 } 2681 2682 static usbd_status 2683 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2684 int timeout) 2685 { 2686 2687 mutex_enter(&sc->sc_lock); 2688 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2689 mutex_exit(&sc->sc_lock); 2690 2691 return ret; 2692 } 2693 2694 static usbd_status 2695 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2696 { 2697 struct xhci_trb trb; 2698 usbd_status err; 2699 2700 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2701 2702 trb.trb_0 = 0; 2703 trb.trb_2 = 0; 2704 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2705 2706 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2707 if (err != USBD_NORMAL_COMPLETION) { 2708 return err; 2709 } 2710 2711 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2712 2713 return err; 2714 } 2715 2716 /* 2717 * xHCI 4.6.4 2718 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2719 * All endpoints in the slot should be stopped. 2720 * Should be called with sc_lock held. 2721 */ 2722 static usbd_status 2723 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2724 { 2725 struct xhci_trb trb; 2726 struct xhci_slot *xs; 2727 usbd_status err; 2728 2729 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2730 2731 if (sc->sc_dying) 2732 return USBD_IOERROR; 2733 2734 trb.trb_0 = 0; 2735 trb.trb_2 = 0; 2736 trb.trb_3 = htole32( 2737 XHCI_TRB_3_SLOT_SET(slot) | 2738 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2739 2740 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2741 2742 if (!err) { 2743 xs = &sc->sc_slots[slot]; 2744 if (xs->xs_idx != 0) { 2745 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2746 xhci_set_dcba(sc, 0, slot); 2747 memset(xs, 0, sizeof(*xs)); 2748 } 2749 } 2750 2751 return err; 2752 } 2753 2754 /* 2755 * Set address of device and transition slot state from ENABLED to ADDRESSED 2756 * if Block Setaddress Request (BSR) is false. 2757 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2758 * see xHCI 1.1 4.5.3, 3.3.4 2759 * Should be called without sc_lock held. 2760 */ 2761 static usbd_status 2762 xhci_address_device(struct xhci_softc * const sc, 2763 uint64_t icp, uint8_t slot_id, bool bsr) 2764 { 2765 struct xhci_trb trb; 2766 usbd_status err; 2767 2768 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2769 2770 trb.trb_0 = icp; 2771 trb.trb_2 = 0; 2772 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2773 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2774 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2775 2776 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2777 2778 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2779 err = USBD_NO_ADDR; 2780 2781 return err; 2782 } 2783 2784 static usbd_status 2785 xhci_update_ep0_mps(struct xhci_softc * const sc, 2786 struct xhci_slot * const xs, u_int mps) 2787 { 2788 struct xhci_trb trb; 2789 usbd_status err; 2790 uint32_t * cp; 2791 2792 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2793 DPRINTFN(4, "slot %ju mps %ju", xs->xs_idx, mps, 0, 0); 2794 2795 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2796 cp[0] = htole32(0); 2797 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2798 2799 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2800 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2801 2802 /* sync input contexts before they are read from memory */ 2803 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2804 HEXDUMP("input context", xhci_slot_get_icv(sc, xs, 0), 2805 sc->sc_ctxsz * 4); 2806 2807 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2808 trb.trb_2 = 0; 2809 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2810 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2811 2812 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2813 return err; 2814 } 2815 2816 static void 2817 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2818 { 2819 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2820 2821 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2822 DPRINTFN(4, "dcbaa %#jx dc %016jx slot %jd", 2823 (uintptr_t)&dcbaa[si], dcba, si, 0); 2824 2825 dcbaa[si] = htole64(dcba); 2826 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2827 BUS_DMASYNC_PREWRITE); 2828 } 2829 2830 /* 2831 * Allocate device and input context DMA buffer, and 2832 * TRB DMA buffer for each endpoint. 2833 */ 2834 static usbd_status 2835 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2836 { 2837 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2838 struct xhci_slot *xs; 2839 usbd_status err; 2840 u_int dci; 2841 2842 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2843 DPRINTFN(4, "slot %ju", slot, 0, 0, 0); 2844 2845 xs = &sc->sc_slots[slot]; 2846 2847 /* allocate contexts */ 2848 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2849 &xs->xs_dc_dma); 2850 if (err) 2851 return err; 2852 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2853 2854 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2855 &xs->xs_ic_dma); 2856 if (err) 2857 goto bad1; 2858 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2859 2860 for (dci = 0; dci < 32; dci++) { 2861 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2862 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2863 if (dci == XHCI_DCI_SLOT) 2864 continue; 2865 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2866 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2867 if (err) { 2868 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2869 goto bad2; 2870 } 2871 } 2872 2873 bad2: 2874 if (err == USBD_NORMAL_COMPLETION) { 2875 xs->xs_idx = slot; 2876 } else { 2877 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2878 } 2879 2880 return err; 2881 2882 bad1: 2883 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2884 xs->xs_idx = 0; 2885 return err; 2886 } 2887 2888 static void 2889 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2890 int end_dci) 2891 { 2892 u_int dci; 2893 2894 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2895 DPRINTFN(4, "slot %ju start %ju end %ju", xs->xs_idx, start_dci, 2896 end_dci, 0); 2897 2898 for (dci = start_dci; dci < end_dci; dci++) { 2899 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2900 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2901 } 2902 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2903 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2904 xs->xs_idx = 0; 2905 } 2906 2907 /* 2908 * Setup slot context, set Device Context Base Address, and issue 2909 * Set Address Device command. 2910 */ 2911 static usbd_status 2912 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 2913 { 2914 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2915 struct xhci_slot *xs; 2916 usbd_status err; 2917 2918 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2919 DPRINTFN(4, "slot %ju bsr %ju", slot, bsr, 0, 0); 2920 2921 xs = &sc->sc_slots[slot]; 2922 2923 xhci_setup_ctx(dev->ud_pipe0); 2924 2925 HEXDUMP("input context", xhci_slot_get_icv(sc, xs, 0), 2926 sc->sc_ctxsz * 3); 2927 2928 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2929 2930 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 2931 2932 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2933 HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, 0), 2934 sc->sc_ctxsz * 2); 2935 2936 return err; 2937 } 2938 2939 /* 2940 * 4.8.2, 6.2.3.2 2941 * construct slot/endpoint context parameters and do syncmem 2942 */ 2943 static void 2944 xhci_setup_ctx(struct usbd_pipe *pipe) 2945 { 2946 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2947 struct usbd_device *dev = pipe->up_dev; 2948 struct xhci_slot * const xs = dev->ud_hcpriv; 2949 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2950 const u_int dci = xhci_ep_get_dci(ed); 2951 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2952 uint32_t *cp; 2953 uint16_t mps = UGETW(ed->wMaxPacketSize); 2954 uint8_t speed = dev->ud_speed; 2955 uint8_t ival = ed->bInterval; 2956 2957 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2958 DPRINTFN(4, "pipe %#jx: slot %ju dci %ju speed %ju", 2959 (uintptr_t)pipe, xs->xs_idx, dci, speed); 2960 2961 /* set up initial input control context */ 2962 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2963 cp[0] = htole32(0); 2964 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 2965 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2966 cp[7] = htole32(0); 2967 2968 /* set up input slot context */ 2969 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2970 cp[0] = 2971 XHCI_SCTX_0_CTX_NUM_SET(dci) | 2972 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 2973 cp[1] = 0; 2974 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2975 cp[3] = 0; 2976 xhci_setup_route(pipe, cp); 2977 xhci_setup_tthub(pipe, cp); 2978 2979 cp[0] = htole32(cp[0]); 2980 cp[1] = htole32(cp[1]); 2981 cp[2] = htole32(cp[2]); 2982 cp[3] = htole32(cp[3]); 2983 2984 /* set up input endpoint context */ 2985 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 2986 cp[0] = 2987 XHCI_EPCTX_0_EPSTATE_SET(0) | 2988 XHCI_EPCTX_0_MULT_SET(0) | 2989 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2990 XHCI_EPCTX_0_LSA_SET(0) | 2991 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 2992 cp[1] = 2993 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 2994 XHCI_EPCTX_1_HID_SET(0) | 2995 XHCI_EPCTX_1_MAXB_SET(0); 2996 2997 if (xfertype != UE_ISOCHRONOUS) 2998 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 2999 3000 if (xfertype == UE_CONTROL) 3001 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 3002 else if (USB_IS_SS(speed)) 3003 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 3004 else 3005 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 3006 3007 xhci_setup_maxburst(pipe, cp); 3008 3009 switch (xfertype) { 3010 case UE_CONTROL: 3011 break; 3012 case UE_BULK: 3013 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 3014 break; 3015 case UE_INTERRUPT: 3016 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3017 ival = pipe->up_interval; 3018 3019 ival = xhci_bival2ival(ival, speed); 3020 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3021 break; 3022 case UE_ISOCHRONOUS: 3023 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3024 ival = pipe->up_interval; 3025 3026 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 3027 if (speed == USB_SPEED_FULL) 3028 ival += 3; /* 1ms -> 125us */ 3029 ival--; 3030 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3031 break; 3032 default: 3033 break; 3034 } 3035 DPRINTFN(4, "setting ival %ju MaxBurst %#jx", 3036 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 3037 3038 /* rewind TR dequeue pointer in xHC */ 3039 /* can't use xhci_ep_get_dci() yet? */ 3040 *(uint64_t *)(&cp[2]) = htole64( 3041 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 3042 XHCI_EPCTX_2_DCS_SET(1)); 3043 3044 cp[0] = htole32(cp[0]); 3045 cp[1] = htole32(cp[1]); 3046 cp[4] = htole32(cp[4]); 3047 3048 /* rewind TR dequeue pointer in driver */ 3049 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 3050 mutex_enter(&xr->xr_lock); 3051 xhci_host_dequeue(xr); 3052 mutex_exit(&xr->xr_lock); 3053 3054 /* sync input contexts before they are read from memory */ 3055 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3056 } 3057 3058 /* 3059 * Setup route string and roothub port of given device for slot context 3060 */ 3061 static void 3062 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 3063 { 3064 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3065 struct usbd_device *dev = pipe->up_dev; 3066 struct usbd_port *up = dev->ud_powersrc; 3067 struct usbd_device *hub; 3068 struct usbd_device *adev; 3069 uint8_t rhport = 0; 3070 uint32_t route = 0; 3071 3072 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3073 3074 /* Locate root hub port and Determine route string */ 3075 /* 4.3.3 route string does not include roothub port */ 3076 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 3077 uint32_t dep; 3078 3079 DPRINTFN(4, "hub %#jx depth %jd upport %jp upportno %jd", 3080 (uintptr_t)hub, hub->ud_depth, (uintptr_t)hub->ud_powersrc, 3081 hub->ud_powersrc ? (uintptr_t)hub->ud_powersrc->up_portno : 3082 -1); 3083 3084 if (hub->ud_powersrc == NULL) 3085 break; 3086 dep = hub->ud_depth; 3087 if (dep == 0) 3088 break; 3089 rhport = hub->ud_powersrc->up_portno; 3090 if (dep > USB_HUB_MAX_DEPTH) 3091 continue; 3092 3093 route |= 3094 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 3095 << ((dep - 1) * 4); 3096 } 3097 route = route >> 4; 3098 size_t bn = hub == sc->sc_bus.ub_roothub ? 0 : 1; 3099 3100 /* Locate port on upstream high speed hub */ 3101 for (adev = dev, hub = up->up_parent; 3102 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 3103 adev = hub, hub = hub->ud_myhub) 3104 ; 3105 if (hub) { 3106 int p; 3107 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 3108 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 3109 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 3110 goto found; 3111 } 3112 } 3113 panic("%s: cannot find HS port", __func__); 3114 found: 3115 DPRINTFN(4, "high speed port %jd", p, 0, 0, 0); 3116 } else { 3117 dev->ud_myhsport = NULL; 3118 } 3119 3120 const size_t ctlrport = xhci_rhport2ctlrport(sc, bn, rhport); 3121 3122 DPRINTFN(4, "rhport %ju ctlrport %ju Route %05jx hub %#jx", rhport, 3123 ctlrport, route, (uintptr_t)hub); 3124 3125 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 3126 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(ctlrport); 3127 } 3128 3129 /* 3130 * Setup whether device is hub, whether device uses MTT, and 3131 * TT informations if it uses MTT. 3132 */ 3133 static void 3134 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 3135 { 3136 struct usbd_device *dev = pipe->up_dev; 3137 struct usbd_device *myhub = dev->ud_myhub; 3138 struct usbd_port *myhsport = dev->ud_myhsport; 3139 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 3140 uint32_t speed = dev->ud_speed; 3141 uint8_t tthubslot, ttportnum; 3142 bool ishub; 3143 bool usemtt; 3144 3145 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3146 3147 /* 3148 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 3149 * tthubslot: 3150 * This is the slot ID of parent HS hub 3151 * if LS/FS device is connected && connected through HS hub. 3152 * This is 0 if device is not LS/FS device || 3153 * parent hub is not HS hub || 3154 * attached to root hub. 3155 * ttportnum: 3156 * This is the downstream facing port of parent HS hub 3157 * if LS/FS device is connected. 3158 * This is 0 if device is not LS/FS device || 3159 * parent hub is not HS hub || 3160 * attached to root hub. 3161 */ 3162 if (myhsport && myhub && myhub->ud_depth && 3163 myhub->ud_speed == USB_SPEED_HIGH && 3164 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 3165 ttportnum = myhsport->up_portno; 3166 tthubslot = myhsport->up_parent->ud_addr; 3167 } else { 3168 ttportnum = 0; 3169 tthubslot = 0; 3170 } 3171 DPRINTFN(4, "myhsport %#jx ttportnum=%jd tthubslot=%jd", 3172 (uintptr_t)myhsport, ttportnum, tthubslot, 0); 3173 3174 /* ishub is valid after reading UDESC_DEVICE */ 3175 ishub = (dd->bDeviceClass == UDCLASS_HUB); 3176 3177 /* dev->ud_hub is valid after reading UDESC_HUB */ 3178 if (ishub && dev->ud_hub) { 3179 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 3180 uint8_t ttt = 3181 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 3182 3183 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 3184 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 3185 DPRINTFN(4, "nports=%jd ttt=%jd", hd->bNbrPorts, ttt, 0, 0); 3186 } 3187 3188 #define IS_TTHUB(dd) \ 3189 ((dd)->bDeviceProtocol == UDPROTO_HSHUBSTT || \ 3190 (dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 3191 3192 /* 3193 * MTT flag is set if 3194 * 1. this is HS hub && MTT is enabled 3195 * or 3196 * 2. this is not hub && this is LS or FS device && 3197 * MTT of parent HS hub (and its parent, too) is enabled 3198 */ 3199 if (ishub && speed == USB_SPEED_HIGH && IS_TTHUB(dd)) 3200 usemtt = true; 3201 else if (!ishub && (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 3202 myhub && myhub->ud_depth && myhub->ud_speed == USB_SPEED_HIGH && 3203 myhsport && IS_TTHUB(&myhsport->up_parent->ud_ddesc)) 3204 usemtt = true; 3205 else 3206 usemtt = false; 3207 DPRINTFN(4, "class %ju proto %ju ishub %jd usemtt %jd", 3208 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 3209 3210 #undef IS_TTHUB 3211 3212 cp[0] |= 3213 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 3214 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 3215 cp[2] |= 3216 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 3217 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 3218 } 3219 3220 /* set up params for periodic endpoint */ 3221 static void 3222 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 3223 { 3224 struct usbd_device *dev = pipe->up_dev; 3225 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3226 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3227 usbd_desc_iter_t iter; 3228 const usb_cdc_descriptor_t *cdcd; 3229 uint32_t maxb = 0; 3230 uint16_t mps = UGETW(ed->wMaxPacketSize); 3231 uint8_t speed = dev->ud_speed; 3232 uint8_t ep; 3233 3234 /* config desc is NULL when opening ep0 */ 3235 if (dev == NULL || dev->ud_cdesc == NULL) 3236 goto no_cdcd; 3237 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 3238 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 3239 if (cdcd == NULL) 3240 goto no_cdcd; 3241 usb_desc_iter_init(dev, &iter); 3242 iter.cur = (const void *)cdcd; 3243 3244 /* find endpoint_ss_comp desc for ep of this pipe */ 3245 for (ep = 0;;) { 3246 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 3247 if (cdcd == NULL) 3248 break; 3249 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 3250 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 3251 bEndpointAddress; 3252 if (UE_GET_ADDR(ep) == 3253 UE_GET_ADDR(ed->bEndpointAddress)) { 3254 cdcd = (const usb_cdc_descriptor_t *) 3255 usb_desc_iter_next(&iter); 3256 break; 3257 } 3258 ep = 0; 3259 } 3260 } 3261 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 3262 const usb_endpoint_ss_comp_descriptor_t * esscd = 3263 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3264 maxb = esscd->bMaxBurst; 3265 } 3266 3267 no_cdcd: 3268 /* 6.2.3.4, 4.8.2.4 */ 3269 if (USB_IS_SS(speed)) { 3270 /* USB 3.1 9.6.6 */ 3271 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3272 /* USB 3.1 9.6.7 */ 3273 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3274 #ifdef notyet 3275 if (xfertype == UE_ISOCHRONOUS) { 3276 } 3277 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3278 /* use ESIT */ 3279 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3280 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3281 3282 /* XXX if LEC = 1, set ESIT instead */ 3283 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3284 } else { 3285 /* use ival */ 3286 } 3287 #endif 3288 } else { 3289 /* USB 2.0 9.6.6 */ 3290 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3291 3292 /* 6.2.3.4 */ 3293 if (speed == USB_SPEED_HIGH && 3294 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3295 maxb = UE_GET_TRANS(mps); 3296 } else { 3297 /* LS/FS or HS CTRL or HS BULK */ 3298 maxb = 0; 3299 } 3300 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3301 } 3302 } 3303 3304 /* 3305 * Convert endpoint bInterval value to endpoint context interval value 3306 * for Interrupt pipe. 3307 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3308 */ 3309 static uint32_t 3310 xhci_bival2ival(uint32_t ival, uint32_t speed) 3311 { 3312 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3313 int i; 3314 3315 /* 3316 * round ival down to "the nearest base 2 multiple of 3317 * bInterval * 8". 3318 * bInterval is at most 255 as its type is uByte. 3319 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3320 */ 3321 for (i = 10; i > 0; i--) { 3322 if ((ival * 8) >= (1 << i)) 3323 break; 3324 } 3325 ival = i; 3326 } else { 3327 /* Interval = bInterval-1 for SS/HS */ 3328 ival--; 3329 } 3330 3331 return ival; 3332 } 3333 3334 /* ----- */ 3335 3336 static void 3337 xhci_noop(struct usbd_pipe *pipe) 3338 { 3339 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3340 } 3341 3342 /* 3343 * Process root hub request. 3344 */ 3345 static int 3346 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3347 void *buf, int buflen) 3348 { 3349 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3350 usb_port_status_t ps; 3351 int l, totlen = 0; 3352 uint16_t len, value, index; 3353 int port, i; 3354 uint32_t v; 3355 3356 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3357 3358 if (sc->sc_dying) 3359 return -1; 3360 3361 size_t bn = bus == &sc->sc_bus ? 0 : 1; 3362 3363 len = UGETW(req->wLength); 3364 value = UGETW(req->wValue); 3365 index = UGETW(req->wIndex); 3366 3367 DPRINTFN(12, "rhreq: %04jx %04jx %04jx %04jx", 3368 req->bmRequestType | (req->bRequest << 8), value, index, len); 3369 3370 #define C(x,y) ((x) | ((y) << 8)) 3371 switch (C(req->bRequest, req->bmRequestType)) { 3372 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3373 DPRINTFN(8, "getdesc: wValue=0x%04jx", value, 0, 0, 0); 3374 if (len == 0) 3375 break; 3376 switch (value) { 3377 case C(0, UDESC_DEVICE): { 3378 usb_device_descriptor_t devd; 3379 totlen = min(buflen, sizeof(devd)); 3380 memcpy(&devd, buf, totlen); 3381 USETW(devd.idVendor, sc->sc_id_vendor); 3382 memcpy(buf, &devd, totlen); 3383 break; 3384 } 3385 #define sd ((usb_string_descriptor_t *)buf) 3386 case C(1, UDESC_STRING): 3387 /* Vendor */ 3388 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3389 break; 3390 case C(2, UDESC_STRING): 3391 /* Product */ 3392 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3393 break; 3394 #undef sd 3395 default: 3396 /* default from usbroothub */ 3397 return buflen; 3398 } 3399 break; 3400 3401 /* Hub requests */ 3402 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3403 break; 3404 /* Clear Port Feature request */ 3405 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): { 3406 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3407 3408 DPRINTFN(4, "UR_CLEAR_PORT_FEAT bp=%jd feat=%jd bus=%jd cp=%jd", 3409 index, value, bn, cp); 3410 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3411 return -1; 3412 } 3413 port = XHCI_PORTSC(cp); 3414 v = xhci_op_read_4(sc, port); 3415 DPRINTFN(4, "portsc=0x%08jx", v, 0, 0, 0); 3416 v &= ~XHCI_PS_CLEAR; 3417 switch (value) { 3418 case UHF_PORT_ENABLE: 3419 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3420 break; 3421 case UHF_PORT_SUSPEND: 3422 return -1; 3423 case UHF_PORT_POWER: 3424 break; 3425 case UHF_PORT_TEST: 3426 case UHF_PORT_INDICATOR: 3427 return -1; 3428 case UHF_C_PORT_CONNECTION: 3429 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3430 break; 3431 case UHF_C_PORT_ENABLE: 3432 case UHF_C_PORT_SUSPEND: 3433 case UHF_C_PORT_OVER_CURRENT: 3434 return -1; 3435 case UHF_C_BH_PORT_RESET: 3436 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3437 break; 3438 case UHF_C_PORT_RESET: 3439 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3440 break; 3441 case UHF_C_PORT_LINK_STATE: 3442 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3443 break; 3444 case UHF_C_PORT_CONFIG_ERROR: 3445 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3446 break; 3447 default: 3448 return -1; 3449 } 3450 break; 3451 } 3452 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3453 if (len == 0) 3454 break; 3455 if ((value & 0xff) != 0) { 3456 return -1; 3457 } 3458 usb_hub_descriptor_t hubd; 3459 3460 totlen = min(buflen, sizeof(hubd)); 3461 memcpy(&hubd, buf, totlen); 3462 hubd.bNbrPorts = sc->sc_rhportcount[bn]; 3463 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3464 hubd.bPwrOn2PwrGood = 200; 3465 for (i = 0, l = sc->sc_rhportcount[bn]; l > 0; i++, l -= 8) { 3466 /* XXX can't find out? */ 3467 hubd.DeviceRemovable[i++] = 0; 3468 } 3469 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3470 totlen = min(totlen, hubd.bDescLength); 3471 memcpy(buf, &hubd, totlen); 3472 break; 3473 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3474 if (len != 4) { 3475 return -1; 3476 } 3477 memset(buf, 0, len); /* ? XXX */ 3478 totlen = len; 3479 break; 3480 /* Get Port Status request */ 3481 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): { 3482 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3483 3484 DPRINTFN(8, "get port status bn=%jd i=%jd cp=%ju", 3485 bn, index, cp, 0); 3486 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3487 return -1; 3488 } 3489 if (len != 4) { 3490 return -1; 3491 } 3492 v = xhci_op_read_4(sc, XHCI_PORTSC(cp)); 3493 DPRINTFN(4, "getrhportsc %jd %08jx", cp, v, 0, 0); 3494 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3495 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3496 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3497 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3498 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3499 if (v & XHCI_PS_PR) i |= UPS_RESET; 3500 if (v & XHCI_PS_PP) { 3501 if (i & UPS_OTHER_SPEED) 3502 i |= UPS_PORT_POWER_SS; 3503 else 3504 i |= UPS_PORT_POWER; 3505 } 3506 if (i & UPS_OTHER_SPEED) 3507 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3508 if (sc->sc_vendor_port_status) 3509 i = sc->sc_vendor_port_status(sc, v, i); 3510 USETW(ps.wPortStatus, i); 3511 i = 0; 3512 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3513 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3514 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3515 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3516 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3517 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3518 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3519 USETW(ps.wPortChange, i); 3520 totlen = min(len, sizeof(ps)); 3521 memcpy(buf, &ps, totlen); 3522 break; 3523 } 3524 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3525 return -1; 3526 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3527 break; 3528 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3529 break; 3530 /* Set Port Feature request */ 3531 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3532 int optval = (index >> 8) & 0xff; 3533 index &= 0xff; 3534 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3535 return -1; 3536 } 3537 3538 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3539 3540 port = XHCI_PORTSC(cp); 3541 v = xhci_op_read_4(sc, port); 3542 DPRINTFN(4, "index %jd cp %jd portsc=0x%08jx", index, cp, v, 0); 3543 v &= ~XHCI_PS_CLEAR; 3544 switch (value) { 3545 case UHF_PORT_ENABLE: 3546 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3547 break; 3548 case UHF_PORT_SUSPEND: 3549 /* XXX suspend */ 3550 break; 3551 case UHF_PORT_RESET: 3552 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3553 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3554 /* Wait for reset to complete. */ 3555 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3556 if (sc->sc_dying) { 3557 return -1; 3558 } 3559 v = xhci_op_read_4(sc, port); 3560 if (v & XHCI_PS_PR) { 3561 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3562 usb_delay_ms(&sc->sc_bus, 10); 3563 /* XXX */ 3564 } 3565 break; 3566 case UHF_PORT_POWER: 3567 /* XXX power control */ 3568 break; 3569 /* XXX more */ 3570 case UHF_C_PORT_RESET: 3571 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3572 break; 3573 case UHF_PORT_U1_TIMEOUT: 3574 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3575 return -1; 3576 } 3577 port = XHCI_PORTPMSC(cp); 3578 v = xhci_op_read_4(sc, port); 3579 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 3580 index, cp, v, 0); 3581 v &= ~XHCI_PM3_U1TO_SET(0xff); 3582 v |= XHCI_PM3_U1TO_SET(optval); 3583 xhci_op_write_4(sc, port, v); 3584 break; 3585 case UHF_PORT_U2_TIMEOUT: 3586 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3587 return -1; 3588 } 3589 port = XHCI_PORTPMSC(cp); 3590 v = xhci_op_read_4(sc, port); 3591 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 3592 index, cp, v, 0); 3593 v &= ~XHCI_PM3_U2TO_SET(0xff); 3594 v |= XHCI_PM3_U2TO_SET(optval); 3595 xhci_op_write_4(sc, port, v); 3596 break; 3597 default: 3598 return -1; 3599 } 3600 } 3601 break; 3602 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3603 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3604 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3605 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3606 break; 3607 default: 3608 /* default from usbroothub */ 3609 return buflen; 3610 } 3611 3612 return totlen; 3613 } 3614 3615 /* root hub interrupt */ 3616 3617 static usbd_status 3618 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3619 { 3620 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3621 usbd_status err; 3622 3623 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3624 3625 /* Insert last in queue. */ 3626 mutex_enter(&sc->sc_lock); 3627 err = usb_insert_transfer(xfer); 3628 mutex_exit(&sc->sc_lock); 3629 if (err) 3630 return err; 3631 3632 /* Pipe isn't running, start first */ 3633 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3634 } 3635 3636 /* Wait for roothub port status/change */ 3637 static usbd_status 3638 xhci_root_intr_start(struct usbd_xfer *xfer) 3639 { 3640 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3641 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3642 3643 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3644 3645 if (sc->sc_dying) 3646 return USBD_IOERROR; 3647 3648 mutex_enter(&sc->sc_lock); 3649 sc->sc_intrxfer[bn] = xfer; 3650 mutex_exit(&sc->sc_lock); 3651 3652 return USBD_IN_PROGRESS; 3653 } 3654 3655 static void 3656 xhci_root_intr_abort(struct usbd_xfer *xfer) 3657 { 3658 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3659 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3660 3661 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3662 3663 KASSERT(mutex_owned(&sc->sc_lock)); 3664 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3665 3666 sc->sc_intrxfer[bn] = NULL; 3667 3668 xfer->ux_status = USBD_CANCELLED; 3669 usb_transfer_complete(xfer); 3670 } 3671 3672 static void 3673 xhci_root_intr_close(struct usbd_pipe *pipe) 3674 { 3675 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3676 const struct usbd_xfer *xfer = pipe->up_intrxfer; 3677 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3678 3679 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3680 3681 KASSERT(mutex_owned(&sc->sc_lock)); 3682 3683 sc->sc_intrxfer[bn] = NULL; 3684 } 3685 3686 static void 3687 xhci_root_intr_done(struct usbd_xfer *xfer) 3688 { 3689 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3690 3691 } 3692 3693 /* -------------- */ 3694 /* device control */ 3695 3696 static usbd_status 3697 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3698 { 3699 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3700 usbd_status err; 3701 3702 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3703 3704 /* Insert last in queue. */ 3705 mutex_enter(&sc->sc_lock); 3706 err = usb_insert_transfer(xfer); 3707 mutex_exit(&sc->sc_lock); 3708 if (err) 3709 return err; 3710 3711 /* Pipe isn't running, start first */ 3712 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3713 } 3714 3715 static usbd_status 3716 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3717 { 3718 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3719 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3720 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3721 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3722 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3723 usb_device_request_t * const req = &xfer->ux_request; 3724 const int isread = usbd_xfer_isread(xfer); 3725 const uint32_t len = UGETW(req->wLength); 3726 usb_dma_t * const dma = &xfer->ux_dmabuf; 3727 uint64_t parameter; 3728 uint32_t status; 3729 uint32_t control; 3730 u_int i; 3731 3732 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3733 DPRINTFN(12, "req: %04jx %04jx %04jx %04jx", 3734 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3735 UGETW(req->wIndex), UGETW(req->wLength)); 3736 3737 /* we rely on the bottom bits for extra info */ 3738 KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx", 3739 (uintptr_t) xfer); 3740 3741 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3742 3743 i = 0; 3744 3745 /* setup phase */ 3746 memcpy(¶meter, req, sizeof(parameter)); 3747 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3748 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3749 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3750 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3751 XHCI_TRB_3_IDT_BIT; 3752 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3753 3754 if (len != 0) { 3755 /* data phase */ 3756 parameter = DMAADDR(dma, 0); 3757 KASSERTMSG(len <= 0x10000, "len %d", len); 3758 status = XHCI_TRB_2_IRQ_SET(0) | 3759 XHCI_TRB_2_TDSZ_SET(1) | 3760 XHCI_TRB_2_BYTES_SET(len); 3761 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3762 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3763 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3764 XHCI_TRB_3_IOC_BIT; 3765 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3766 } 3767 3768 parameter = 0; 3769 status = XHCI_TRB_2_IRQ_SET(0); 3770 /* the status stage has inverted direction */ 3771 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3772 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3773 XHCI_TRB_3_IOC_BIT; 3774 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3775 3776 mutex_enter(&tr->xr_lock); 3777 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3778 mutex_exit(&tr->xr_lock); 3779 3780 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3781 3782 if (xfer->ux_timeout && !xhci_polling_p(sc)) { 3783 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3784 xhci_timeout, xfer); 3785 } 3786 3787 return USBD_IN_PROGRESS; 3788 } 3789 3790 static void 3791 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3792 { 3793 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3794 usb_device_request_t *req = &xfer->ux_request; 3795 int len = UGETW(req->wLength); 3796 int rd = req->bmRequestType & UT_READ; 3797 3798 if (len) 3799 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3800 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3801 } 3802 3803 static void 3804 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3805 { 3806 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3807 3808 xhci_abort_xfer(xfer, USBD_CANCELLED); 3809 } 3810 3811 static void 3812 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3813 { 3814 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3815 3816 xhci_close_pipe(pipe); 3817 } 3818 3819 /* ------------------ */ 3820 /* device isochronous */ 3821 3822 /* ----------- */ 3823 /* device bulk */ 3824 3825 static usbd_status 3826 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3827 { 3828 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3829 usbd_status err; 3830 3831 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3832 3833 /* Insert last in queue. */ 3834 mutex_enter(&sc->sc_lock); 3835 err = usb_insert_transfer(xfer); 3836 mutex_exit(&sc->sc_lock); 3837 if (err) 3838 return err; 3839 3840 /* 3841 * Pipe isn't running (otherwise err would be USBD_INPROG), 3842 * so start it first. 3843 */ 3844 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3845 } 3846 3847 static usbd_status 3848 xhci_device_bulk_start(struct usbd_xfer *xfer) 3849 { 3850 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3851 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3852 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3853 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3854 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3855 const uint32_t len = xfer->ux_length; 3856 usb_dma_t * const dma = &xfer->ux_dmabuf; 3857 uint64_t parameter; 3858 uint32_t status; 3859 uint32_t control; 3860 u_int i = 0; 3861 3862 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3863 3864 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 3865 0); 3866 3867 if (sc->sc_dying) 3868 return USBD_IOERROR; 3869 3870 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3871 3872 parameter = DMAADDR(dma, 0); 3873 /* 3874 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3875 * If the user supplied buffer crosses such a boundary then 2 3876 * (or more) TRB should be used. 3877 * If multiple TRB are used the td_size field must be set correctly. 3878 * For v1.0 devices (like ivy bridge) this is the number of usb data 3879 * blocks needed to complete the transfer. 3880 * Setting it to 1 in the last TRB causes an extra zero-length 3881 * data block be sent. 3882 * The earlier documentation differs, I don't know how it behaves. 3883 */ 3884 KASSERTMSG(len <= 0x10000, "len %d", len); 3885 status = XHCI_TRB_2_IRQ_SET(0) | 3886 XHCI_TRB_2_TDSZ_SET(1) | 3887 XHCI_TRB_2_BYTES_SET(len); 3888 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3889 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3890 XHCI_TRB_3_IOC_BIT; 3891 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3892 3893 mutex_enter(&tr->xr_lock); 3894 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3895 mutex_exit(&tr->xr_lock); 3896 3897 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3898 3899 if (xfer->ux_timeout && !xhci_polling_p(sc)) { 3900 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3901 xhci_timeout, xfer); 3902 } 3903 3904 return USBD_IN_PROGRESS; 3905 } 3906 3907 static void 3908 xhci_device_bulk_done(struct usbd_xfer *xfer) 3909 { 3910 #ifdef USB_DEBUG 3911 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3912 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3913 #endif 3914 const int isread = usbd_xfer_isread(xfer); 3915 3916 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3917 3918 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 3919 0); 3920 3921 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3922 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3923 } 3924 3925 static void 3926 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3927 { 3928 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3929 3930 xhci_abort_xfer(xfer, USBD_CANCELLED); 3931 } 3932 3933 static void 3934 xhci_device_bulk_close(struct usbd_pipe *pipe) 3935 { 3936 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3937 3938 xhci_close_pipe(pipe); 3939 } 3940 3941 /* ---------------- */ 3942 /* device interrupt */ 3943 3944 static usbd_status 3945 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3946 { 3947 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3948 usbd_status err; 3949 3950 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3951 3952 /* Insert last in queue. */ 3953 mutex_enter(&sc->sc_lock); 3954 err = usb_insert_transfer(xfer); 3955 mutex_exit(&sc->sc_lock); 3956 if (err) 3957 return err; 3958 3959 /* 3960 * Pipe isn't running (otherwise err would be USBD_INPROG), 3961 * so start it first. 3962 */ 3963 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3964 } 3965 3966 static usbd_status 3967 xhci_device_intr_start(struct usbd_xfer *xfer) 3968 { 3969 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3970 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3971 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3972 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3973 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3974 const uint32_t len = xfer->ux_length; 3975 usb_dma_t * const dma = &xfer->ux_dmabuf; 3976 uint64_t parameter; 3977 uint32_t status; 3978 uint32_t control; 3979 u_int i = 0; 3980 3981 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3982 3983 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 3984 0); 3985 3986 if (sc->sc_dying) 3987 return USBD_IOERROR; 3988 3989 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3990 3991 parameter = DMAADDR(dma, 0); 3992 KASSERTMSG(len <= 0x10000, "len %d", len); 3993 status = XHCI_TRB_2_IRQ_SET(0) | 3994 XHCI_TRB_2_TDSZ_SET(1) | 3995 XHCI_TRB_2_BYTES_SET(len); 3996 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3997 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3998 XHCI_TRB_3_IOC_BIT; 3999 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 4000 4001 mutex_enter(&tr->xr_lock); 4002 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 4003 mutex_exit(&tr->xr_lock); 4004 4005 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4006 4007 if (xfer->ux_timeout && !xhci_polling_p(sc)) { 4008 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4009 xhci_timeout, xfer); 4010 } 4011 4012 return USBD_IN_PROGRESS; 4013 } 4014 4015 static void 4016 xhci_device_intr_done(struct usbd_xfer *xfer) 4017 { 4018 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4019 #ifdef USB_DEBUG 4020 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4021 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4022 #endif 4023 const int isread = usbd_xfer_isread(xfer); 4024 4025 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4026 4027 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 4028 0); 4029 4030 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 4031 4032 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4033 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4034 } 4035 4036 static void 4037 xhci_device_intr_abort(struct usbd_xfer *xfer) 4038 { 4039 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4040 4041 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4042 4043 KASSERT(mutex_owned(&sc->sc_lock)); 4044 DPRINTFN(15, "%#jx", (uintptr_t)xfer, 0, 0, 0); 4045 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4046 xhci_abort_xfer(xfer, USBD_CANCELLED); 4047 } 4048 4049 static void 4050 xhci_device_intr_close(struct usbd_pipe *pipe) 4051 { 4052 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 4053 4054 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4055 DPRINTFN(15, "%#jx", (uintptr_t)pipe, 0, 0, 0); 4056 4057 xhci_close_pipe(pipe); 4058 } 4059 4060 /* ------------ */ 4061 4062 static void 4063 xhci_timeout(void *addr) 4064 { 4065 struct xhci_xfer * const xx = addr; 4066 struct usbd_xfer * const xfer = &xx->xx_xfer; 4067 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4068 4069 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4070 4071 if (sc->sc_dying) { 4072 return; 4073 } 4074 4075 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 4076 USB_TASKQ_MPSAFE); 4077 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 4078 USB_TASKQ_HC); 4079 } 4080 4081 static void 4082 xhci_timeout_task(void *addr) 4083 { 4084 struct usbd_xfer * const xfer = addr; 4085 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4086 4087 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4088 4089 mutex_enter(&sc->sc_lock); 4090 xhci_abort_xfer(xfer, USBD_TIMEOUT); 4091 mutex_exit(&sc->sc_lock); 4092 } 4093
Indexes created Tue Sep 23 02:09:52 GMT 2025