xhci.c revision 1.86
1 /* $NetBSD: xhci.c,v 1.86 2018/02/07 15:55:58 prlw1 Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.86 2018/02/07 15:55:58 prlw1 Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 #define HEXDUMP(a, b, c) \ 77 do { \ 78 if (xhcidebug > 0) \ 79 hexdump(printf, a, b, c); \ 80 } while (/*CONSTCOND*/0) 81 static int xhcidebug = 0; 82 83 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 84 { 85 int err; 86 const struct sysctlnode *rnode; 87 const struct sysctlnode *cnode; 88 89 err = sysctl_createv(clog, 0, NULL, &rnode, 90 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 91 SYSCTL_DESCR("xhci global controls"), 92 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 93 94 if (err) 95 goto fail; 96 97 /* control debugging printfs */ 98 err = sysctl_createv(clog, 0, &rnode, &cnode, 99 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 100 "debug", SYSCTL_DESCR("Enable debugging output"), 101 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 102 if (err) 103 goto fail; 104 105 return; 106 fail: 107 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 108 } 109 110 #endif /* !XHCI_DEBUG */ 111 #endif /* USB_DEBUG */ 112 113 #ifndef HEXDUMP 114 #define HEXDUMP(a, b, c) 115 #endif 116 117 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 118 #define XHCIHIST_FUNC() USBHIST_FUNC() 119 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 120 121 #define XHCI_DCI_SLOT 0 122 #define XHCI_DCI_EP_CONTROL 1 123 124 #define XHCI_ICI_INPUT_CONTROL 0 125 126 struct xhci_pipe { 127 struct usbd_pipe xp_pipe; 128 struct usb_task xp_async_task; 129 }; 130 131 #define XHCI_COMMAND_RING_TRBS 256 132 #define XHCI_EVENT_RING_TRBS 256 133 #define XHCI_EVENT_RING_SEGMENTS 1 134 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 135 136 static usbd_status xhci_open(struct usbd_pipe *); 137 static void xhci_close_pipe(struct usbd_pipe *); 138 static int xhci_intr1(struct xhci_softc * const); 139 static void xhci_softintr(void *); 140 static void xhci_poll(struct usbd_bus *); 141 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 142 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 143 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 144 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 145 struct usbd_port *); 146 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 147 void *, int); 148 149 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 150 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 151 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 152 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 153 154 static void xhci_host_dequeue(struct xhci_ring * const); 155 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 156 157 static usbd_status xhci_do_command(struct xhci_softc * const, 158 struct xhci_trb * const, int); 159 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 160 struct xhci_trb * const, int); 161 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 162 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 163 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 164 static usbd_status xhci_enable_slot(struct xhci_softc * const, 165 uint8_t * const); 166 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 167 static usbd_status xhci_address_device(struct xhci_softc * const, 168 uint64_t, uint8_t, bool); 169 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 170 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 171 struct xhci_slot * const, u_int); 172 static usbd_status xhci_ring_init(struct xhci_softc * const, 173 struct xhci_ring * const, size_t, size_t); 174 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 175 176 static void xhci_setup_ctx(struct usbd_pipe *); 177 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 178 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 179 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 180 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 181 182 static void xhci_noop(struct usbd_pipe *); 183 184 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 185 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 186 static void xhci_root_intr_abort(struct usbd_xfer *); 187 static void xhci_root_intr_close(struct usbd_pipe *); 188 static void xhci_root_intr_done(struct usbd_xfer *); 189 190 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 191 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 192 static void xhci_device_ctrl_abort(struct usbd_xfer *); 193 static void xhci_device_ctrl_close(struct usbd_pipe *); 194 static void xhci_device_ctrl_done(struct usbd_xfer *); 195 196 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 197 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 198 static void xhci_device_intr_abort(struct usbd_xfer *); 199 static void xhci_device_intr_close(struct usbd_pipe *); 200 static void xhci_device_intr_done(struct usbd_xfer *); 201 202 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 203 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 204 static void xhci_device_bulk_abort(struct usbd_xfer *); 205 static void xhci_device_bulk_close(struct usbd_pipe *); 206 static void xhci_device_bulk_done(struct usbd_xfer *); 207 208 static void xhci_timeout(void *); 209 static void xhci_timeout_task(void *); 210 211 static const struct usbd_bus_methods xhci_bus_methods = { 212 .ubm_open = xhci_open, 213 .ubm_softint = xhci_softintr, 214 .ubm_dopoll = xhci_poll, 215 .ubm_allocx = xhci_allocx, 216 .ubm_freex = xhci_freex, 217 .ubm_getlock = xhci_get_lock, 218 .ubm_newdev = xhci_new_device, 219 .ubm_rhctrl = xhci_roothub_ctrl, 220 }; 221 222 static const struct usbd_pipe_methods xhci_root_intr_methods = { 223 .upm_transfer = xhci_root_intr_transfer, 224 .upm_start = xhci_root_intr_start, 225 .upm_abort = xhci_root_intr_abort, 226 .upm_close = xhci_root_intr_close, 227 .upm_cleartoggle = xhci_noop, 228 .upm_done = xhci_root_intr_done, 229 }; 230 231 232 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 233 .upm_transfer = xhci_device_ctrl_transfer, 234 .upm_start = xhci_device_ctrl_start, 235 .upm_abort = xhci_device_ctrl_abort, 236 .upm_close = xhci_device_ctrl_close, 237 .upm_cleartoggle = xhci_noop, 238 .upm_done = xhci_device_ctrl_done, 239 }; 240 241 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 242 .upm_cleartoggle = xhci_noop, 243 }; 244 245 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 246 .upm_transfer = xhci_device_bulk_transfer, 247 .upm_start = xhci_device_bulk_start, 248 .upm_abort = xhci_device_bulk_abort, 249 .upm_close = xhci_device_bulk_close, 250 .upm_cleartoggle = xhci_noop, 251 .upm_done = xhci_device_bulk_done, 252 }; 253 254 static const struct usbd_pipe_methods xhci_device_intr_methods = { 255 .upm_transfer = xhci_device_intr_transfer, 256 .upm_start = xhci_device_intr_start, 257 .upm_abort = xhci_device_intr_abort, 258 .upm_close = xhci_device_intr_close, 259 .upm_cleartoggle = xhci_noop, 260 .upm_done = xhci_device_intr_done, 261 }; 262 263 static inline uint32_t 264 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 265 { 266 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 267 } 268 269 static inline uint32_t 270 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 271 { 272 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 273 } 274 275 static inline void 276 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 277 uint32_t value) 278 { 279 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 280 } 281 282 #if 0 /* unused */ 283 static inline void 284 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 285 uint32_t value) 286 { 287 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 288 } 289 #endif /* unused */ 290 291 static inline uint32_t 292 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 293 { 294 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 295 } 296 297 static inline uint32_t 298 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 299 { 300 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 301 } 302 303 static inline void 304 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 305 uint32_t value) 306 { 307 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 308 } 309 310 static inline uint64_t 311 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 312 { 313 uint64_t value; 314 315 if (sc->sc_ac64) { 316 #ifdef XHCI_USE_BUS_SPACE_8 317 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 318 #else 319 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 320 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 321 offset + 4) << 32; 322 #endif 323 } else { 324 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 325 } 326 327 return value; 328 } 329 330 static inline void 331 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 332 uint64_t value) 333 { 334 if (sc->sc_ac64) { 335 #ifdef XHCI_USE_BUS_SPACE_8 336 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 337 #else 338 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 339 (value >> 0) & 0xffffffff); 340 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 341 (value >> 32) & 0xffffffff); 342 #endif 343 } else { 344 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 345 } 346 } 347 348 static inline uint32_t 349 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 350 { 351 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 352 } 353 354 static inline void 355 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 356 uint32_t value) 357 { 358 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 359 } 360 361 #if 0 /* unused */ 362 static inline uint64_t 363 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 364 { 365 uint64_t value; 366 367 if (sc->sc_ac64) { 368 #ifdef XHCI_USE_BUS_SPACE_8 369 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 370 #else 371 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 372 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 373 offset + 4) << 32; 374 #endif 375 } else { 376 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 377 } 378 379 return value; 380 } 381 #endif /* unused */ 382 383 static inline void 384 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 385 uint64_t value) 386 { 387 if (sc->sc_ac64) { 388 #ifdef XHCI_USE_BUS_SPACE_8 389 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 390 #else 391 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 392 (value >> 0) & 0xffffffff); 393 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 394 (value >> 32) & 0xffffffff); 395 #endif 396 } else { 397 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 398 } 399 } 400 401 #if 0 /* unused */ 402 static inline uint32_t 403 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 404 { 405 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 406 } 407 #endif /* unused */ 408 409 static inline void 410 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 411 uint32_t value) 412 { 413 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 414 } 415 416 /* --- */ 417 418 static inline uint8_t 419 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 420 { 421 u_int eptype = 0; 422 423 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 424 case UE_CONTROL: 425 eptype = 0x0; 426 break; 427 case UE_ISOCHRONOUS: 428 eptype = 0x1; 429 break; 430 case UE_BULK: 431 eptype = 0x2; 432 break; 433 case UE_INTERRUPT: 434 eptype = 0x3; 435 break; 436 } 437 438 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 439 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 440 return eptype | 0x4; 441 else 442 return eptype; 443 } 444 445 static u_int 446 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 447 { 448 /* xHCI 1.0 section 4.5.1 */ 449 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 450 u_int in = 0; 451 452 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 453 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 454 in = 1; 455 456 return epaddr * 2 + in; 457 } 458 459 static inline u_int 460 xhci_dci_to_ici(const u_int i) 461 { 462 return i + 1; 463 } 464 465 static inline void * 466 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 467 const u_int dci) 468 { 469 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 470 } 471 472 #if 0 /* unused */ 473 static inline bus_addr_t 474 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 475 const u_int dci) 476 { 477 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 478 } 479 #endif /* unused */ 480 481 static inline void * 482 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 483 const u_int ici) 484 { 485 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 486 } 487 488 static inline bus_addr_t 489 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 490 const u_int ici) 491 { 492 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 493 } 494 495 static inline struct xhci_trb * 496 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 497 { 498 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 499 } 500 501 static inline bus_addr_t 502 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 503 { 504 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 505 } 506 507 static inline void 508 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 509 uint32_t control) 510 { 511 trb->trb_0 = htole64(parameter); 512 trb->trb_2 = htole32(status); 513 trb->trb_3 = htole32(control); 514 } 515 516 static int 517 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 518 { 519 /* base address of TRBs */ 520 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 521 522 /* trb_0 range sanity check */ 523 if (trb_0 == 0 || trb_0 < trbp || 524 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 525 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 526 return 1; 527 } 528 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 529 return 0; 530 } 531 532 static unsigned int 533 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 534 u_int dci) 535 { 536 uint32_t *cp; 537 538 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 539 cp = xhci_slot_get_dcv(sc, xs, dci); 540 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 541 } 542 543 static inline unsigned int 544 xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport) 545 { 546 const unsigned int port = ctlrport - 1; 547 const uint8_t bit = __BIT(port % NBBY); 548 549 return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit); 550 } 551 552 /* 553 * Return the roothub port for a controller port. Both are 1..n. 554 */ 555 static inline unsigned int 556 xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport) 557 { 558 559 return sc->sc_ctlrportmap[ctrlport - 1]; 560 } 561 562 /* 563 * Return the controller port for a bus roothub port. Both are 1..n. 564 */ 565 static inline unsigned int 566 xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn, 567 unsigned int rhport) 568 { 569 570 return sc->sc_rhportmap[bn][rhport - 1]; 571 } 572 573 /* --- */ 574 575 void 576 xhci_childdet(device_t self, device_t child) 577 { 578 struct xhci_softc * const sc = device_private(self); 579 580 KASSERT((sc->sc_child == child) || (sc->sc_child2 == child)); 581 if (child == sc->sc_child2) 582 sc->sc_child2 = NULL; 583 else if (child == sc->sc_child) 584 sc->sc_child = NULL; 585 } 586 587 int 588 xhci_detach(struct xhci_softc *sc, int flags) 589 { 590 int rv = 0; 591 592 if (sc->sc_child2 != NULL) { 593 rv = config_detach(sc->sc_child2, flags); 594 if (rv != 0) 595 return rv; 596 } 597 598 if (sc->sc_child != NULL) { 599 rv = config_detach(sc->sc_child, flags); 600 if (rv != 0) 601 return rv; 602 } 603 604 /* XXX unconfigure/free slots */ 605 606 /* verify: */ 607 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 608 xhci_op_write_4(sc, XHCI_USBCMD, 0); 609 /* do we need to wait for stop? */ 610 611 xhci_op_write_8(sc, XHCI_CRCR, 0); 612 xhci_ring_free(sc, &sc->sc_cr); 613 cv_destroy(&sc->sc_command_cv); 614 cv_destroy(&sc->sc_cmdbusy_cv); 615 616 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 617 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 618 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 619 xhci_ring_free(sc, &sc->sc_er); 620 621 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 622 623 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 624 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 625 626 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 627 628 kmem_free(sc->sc_ctlrportbus, 629 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY)); 630 kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int)); 631 632 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 633 kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int)); 634 } 635 636 mutex_destroy(&sc->sc_lock); 637 mutex_destroy(&sc->sc_intr_lock); 638 639 pool_cache_destroy(sc->sc_xferpool); 640 641 return rv; 642 } 643 644 int 645 xhci_activate(device_t self, enum devact act) 646 { 647 struct xhci_softc * const sc = device_private(self); 648 649 switch (act) { 650 case DVACT_DEACTIVATE: 651 sc->sc_dying = true; 652 return 0; 653 default: 654 return EOPNOTSUPP; 655 } 656 } 657 658 bool 659 xhci_suspend(device_t dv, const pmf_qual_t *qual) 660 { 661 return false; 662 } 663 664 bool 665 xhci_resume(device_t dv, const pmf_qual_t *qual) 666 { 667 return false; 668 } 669 670 bool 671 xhci_shutdown(device_t self, int flags) 672 { 673 return false; 674 } 675 676 static int 677 xhci_hc_reset(struct xhci_softc * const sc) 678 { 679 uint32_t usbcmd, usbsts; 680 int i; 681 682 /* Check controller not ready */ 683 for (i = 0; i < XHCI_WAIT_CNR; i++) { 684 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 685 if ((usbsts & XHCI_STS_CNR) == 0) 686 break; 687 usb_delay_ms(&sc->sc_bus, 1); 688 } 689 if (i >= XHCI_WAIT_CNR) { 690 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 691 return EIO; 692 } 693 694 /* Halt controller */ 695 usbcmd = 0; 696 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 697 usb_delay_ms(&sc->sc_bus, 1); 698 699 /* Reset controller */ 700 usbcmd = XHCI_CMD_HCRST; 701 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 702 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 703 /* 704 * Wait 1ms first. Existing Intel xHCI requies 1ms delay to 705 * prevent system hang (Errata). 706 */ 707 usb_delay_ms(&sc->sc_bus, 1); 708 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 709 if ((usbcmd & XHCI_CMD_HCRST) == 0) 710 break; 711 } 712 if (i >= XHCI_WAIT_HCRST) { 713 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 714 return EIO; 715 } 716 717 /* Check controller not ready */ 718 for (i = 0; i < XHCI_WAIT_CNR; i++) { 719 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 720 if ((usbsts & XHCI_STS_CNR) == 0) 721 break; 722 usb_delay_ms(&sc->sc_bus, 1); 723 } 724 if (i >= XHCI_WAIT_CNR) { 725 aprint_error_dev(sc->sc_dev, 726 "controller not ready timeout after reset\n"); 727 return EIO; 728 } 729 730 return 0; 731 } 732 733 734 /* 7.2 xHCI Support Protocol Capability */ 735 static void 736 xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp) 737 { 738 /* XXX Cache this lot */ 739 740 const uint32_t w0 = xhci_read_4(sc, ecp); 741 const uint32_t w4 = xhci_read_4(sc, ecp + 4); 742 const uint32_t w8 = xhci_read_4(sc, ecp + 8); 743 const uint32_t wc = xhci_read_4(sc, ecp + 0xc); 744 745 aprint_debug_dev(sc->sc_dev, 746 " SP: %08x %08x %08x %08x\n", w0, w4, w8, wc); 747 748 if (w4 != XHCI_XECP_USBID) 749 return; 750 751 const int major = XHCI_XECP_SP_W0_MAJOR(w0); 752 const int minor = XHCI_XECP_SP_W0_MINOR(w0); 753 const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8); 754 const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8); 755 756 const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16)); 757 switch (mm) { 758 case 0x0200: 759 case 0x0300: 760 case 0x0301: 761 aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n", 762 major == 3 ? "ss" : "hs", cpo, cpo + cpc -1); 763 break; 764 default: 765 aprint_debug_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n", 766 major, minor); 767 return; 768 } 769 770 const size_t bus = (major == 3) ? 0 : 1; 771 772 /* Index arrays with 0..n-1 where ports are numbered 1..n */ 773 for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) { 774 if (sc->sc_ctlrportmap[cp] != 0) { 775 aprint_error_dev(sc->sc_dev, "contoller port %zu " 776 "already assigned", cp); 777 continue; 778 } 779 780 sc->sc_ctlrportbus[cp / NBBY] |= 781 bus == 0 ? 0 : __BIT(cp % NBBY); 782 783 const size_t rhp = sc->sc_rhportcount[bus]++; 784 785 KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0, 786 "bus %zu rhp %zu is %d", bus, rhp, 787 sc->sc_rhportmap[bus][rhp]); 788 789 sc->sc_rhportmap[bus][rhp] = cp + 1; 790 sc->sc_ctlrportmap[cp] = rhp + 1; 791 } 792 } 793 794 /* Process extended capabilities */ 795 static void 796 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 797 { 798 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 799 800 bus_size_t ecp = XHCI_HCC_XECP(hcc) * 4; 801 while (ecp != 0) { 802 uint32_t ecr = xhci_read_4(sc, ecp); 803 aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr); 804 switch (XHCI_XECP_ID(ecr)) { 805 case XHCI_ID_PROTOCOLS: { 806 xhci_id_protocols(sc, ecp); 807 break; 808 } 809 case XHCI_ID_USB_LEGACY: { 810 uint8_t bios_sem; 811 812 /* Take host controller ownership from BIOS */ 813 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 814 if (bios_sem) { 815 /* sets xHCI to be owned by OS */ 816 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 817 aprint_debug_dev(sc->sc_dev, 818 "waiting for BIOS to give up control\n"); 819 for (int i = 0; i < 5000; i++) { 820 bios_sem = xhci_read_1(sc, ecp + 821 XHCI_XECP_BIOS_SEM); 822 if (bios_sem == 0) 823 break; 824 DELAY(1000); 825 } 826 if (bios_sem) { 827 aprint_error_dev(sc->sc_dev, 828 "timed out waiting for BIOS\n"); 829 } 830 } 831 break; 832 } 833 default: 834 break; 835 } 836 ecr = xhci_read_4(sc, ecp); 837 if (XHCI_XECP_NEXT(ecr) == 0) { 838 ecp = 0; 839 } else { 840 ecp += XHCI_XECP_NEXT(ecr) * 4; 841 } 842 } 843 } 844 845 #define XHCI_HCCPREV1_BITS \ 846 "\177\020" /* New bitmask */ \ 847 "f\020\020XECP\0" \ 848 "f\014\4MAXPSA\0" \ 849 "b\013CFC\0" \ 850 "b\012SEC\0" \ 851 "b\011SBD\0" \ 852 "b\010FSE\0" \ 853 "b\7NSS\0" \ 854 "b\6LTC\0" \ 855 "b\5LHRC\0" \ 856 "b\4PIND\0" \ 857 "b\3PPC\0" \ 858 "b\2CZC\0" \ 859 "b\1BNC\0" \ 860 "b\0AC64\0" \ 861 "\0" 862 #define XHCI_HCCV1_x_BITS \ 863 "\177\020" /* New bitmask */ \ 864 "f\020\020XECP\0" \ 865 "f\014\4MAXPSA\0" \ 866 "b\013CFC\0" \ 867 "b\012SEC\0" \ 868 "b\011SPC\0" \ 869 "b\010PAE\0" \ 870 "b\7NSS\0" \ 871 "b\6LTC\0" \ 872 "b\5LHRC\0" \ 873 "b\4PIND\0" \ 874 "b\3PPC\0" \ 875 "b\2CSZ\0" \ 876 "b\1BNC\0" \ 877 "b\0AC64\0" \ 878 "\0" 879 880 void 881 xhci_start(struct xhci_softc *sc) 882 { 883 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 884 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 885 /* Intel xhci needs interrupt rate moderated. */ 886 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 887 else 888 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 889 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 890 xhci_rt_read_4(sc, XHCI_IMOD(0))); 891 892 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 893 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 894 xhci_op_read_4(sc, XHCI_USBCMD)); 895 } 896 897 int 898 xhci_init(struct xhci_softc *sc) 899 { 900 bus_size_t bsz; 901 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 902 uint32_t pagesize, config; 903 int i = 0; 904 uint16_t hciversion; 905 uint8_t caplength; 906 907 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 908 909 /* Set up the bus struct for the usb 3 and usb 2 buses */ 910 sc->sc_bus.ub_methods = &xhci_bus_methods; 911 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 912 sc->sc_bus.ub_revision = USBREV_3_0; 913 sc->sc_bus.ub_usedma = true; 914 sc->sc_bus.ub_hcpriv = sc; 915 916 sc->sc_bus2.ub_methods = &xhci_bus_methods; 917 sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe); 918 sc->sc_bus2.ub_revision = USBREV_2_0; 919 sc->sc_bus2.ub_usedma = true; 920 sc->sc_bus2.ub_hcpriv = sc; 921 sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag; 922 923 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 924 caplength = XHCI_CAP_CAPLENGTH(cap); 925 hciversion = XHCI_CAP_HCIVERSION(cap); 926 927 if (hciversion < XHCI_HCIVERSION_0_96 || 928 hciversion > XHCI_HCIVERSION_1_0) { 929 aprint_normal_dev(sc->sc_dev, 930 "xHCI version %x.%x not known to be supported\n", 931 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 932 } else { 933 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 934 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 935 } 936 937 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 938 &sc->sc_cbh) != 0) { 939 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 940 return ENOMEM; 941 } 942 943 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 944 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 945 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 946 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 947 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 948 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 949 aprint_debug_dev(sc->sc_dev, 950 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 951 952 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 953 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 954 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 955 956 char sbuf[128]; 957 if (hciversion < XHCI_HCIVERSION_1_0) 958 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 959 else 960 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 961 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 962 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 963 964 /* default all ports to bus 0, i.e. usb 3 */ 965 sc->sc_ctlrportbus = kmem_zalloc( 966 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP); 967 sc->sc_ctlrportmap = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 968 969 /* controller port to bus roothub port map */ 970 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 971 sc->sc_rhportmap[j] = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 972 } 973 974 /* 975 * Process all Extended Capabilities 976 */ 977 xhci_ecp(sc, hcc); 978 979 bsz = XHCI_PORTSC(sc->sc_maxports); 980 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 981 &sc->sc_obh) != 0) { 982 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 983 return ENOMEM; 984 } 985 986 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 987 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 988 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 989 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 990 return ENOMEM; 991 } 992 993 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 994 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 995 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 996 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 997 return ENOMEM; 998 } 999 1000 int rv; 1001 rv = xhci_hc_reset(sc); 1002 if (rv != 0) { 1003 return rv; 1004 } 1005 1006 if (sc->sc_vendor_init) 1007 sc->sc_vendor_init(sc); 1008 1009 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 1010 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 1011 pagesize = ffs(pagesize); 1012 if (pagesize == 0) { 1013 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 1014 return EIO; 1015 } 1016 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 1017 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 1018 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 1019 (uint32_t)sc->sc_maxslots); 1020 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 1021 1022 usbd_status err; 1023 1024 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 1025 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 1026 if (sc->sc_maxspbuf != 0) { 1027 err = usb_allocmem(&sc->sc_bus, 1028 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 1029 &sc->sc_spbufarray_dma); 1030 if (err) { 1031 aprint_error_dev(sc->sc_dev, 1032 "spbufarray init fail, err %d\n", err); 1033 return ENOMEM; 1034 } 1035 1036 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 1037 sc->sc_maxspbuf, KM_SLEEP); 1038 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 1039 for (i = 0; i < sc->sc_maxspbuf; i++) { 1040 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 1041 /* allocate contexts */ 1042 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 1043 sc->sc_pgsz, dma); 1044 if (err) { 1045 aprint_error_dev(sc->sc_dev, 1046 "spbufarray_dma init fail, err %d\n", err); 1047 rv = ENOMEM; 1048 goto bad1; 1049 } 1050 spbufarray[i] = htole64(DMAADDR(dma, 0)); 1051 usb_syncmem(dma, 0, sc->sc_pgsz, 1052 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1053 } 1054 1055 usb_syncmem(&sc->sc_spbufarray_dma, 0, 1056 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 1057 } 1058 1059 config = xhci_op_read_4(sc, XHCI_CONFIG); 1060 config &= ~0xFF; 1061 config |= sc->sc_maxslots & 0xFF; 1062 xhci_op_write_4(sc, XHCI_CONFIG, config); 1063 1064 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 1065 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 1066 if (err) { 1067 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 1068 err); 1069 rv = ENOMEM; 1070 goto bad1; 1071 } 1072 1073 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 1074 XHCI_EVENT_RING_SEGMENTS_ALIGN); 1075 if (err) { 1076 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 1077 err); 1078 rv = ENOMEM; 1079 goto bad2; 1080 } 1081 1082 usb_dma_t *dma; 1083 size_t size; 1084 size_t align; 1085 1086 dma = &sc->sc_eventst_dma; 1087 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 1088 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 1089 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 1090 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 1091 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1092 if (err) { 1093 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 1094 err); 1095 rv = ENOMEM; 1096 goto bad3; 1097 } 1098 1099 memset(KERNADDR(dma, 0), 0, size); 1100 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1101 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 1102 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 1103 KERNADDR(&sc->sc_eventst_dma, 0), 1104 sc->sc_eventst_dma.udma_block->size); 1105 1106 dma = &sc->sc_dcbaa_dma; 1107 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 1108 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 1109 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 1110 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1111 if (err) { 1112 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1113 rv = ENOMEM; 1114 goto bad4; 1115 } 1116 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 1117 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1118 KERNADDR(&sc->sc_dcbaa_dma, 0), 1119 sc->sc_dcbaa_dma.udma_block->size); 1120 1121 memset(KERNADDR(dma, 0), 0, size); 1122 if (sc->sc_maxspbuf != 0) { 1123 /* 1124 * DCBA entry 0 hold the scratchbuf array pointer. 1125 */ 1126 *(uint64_t *)KERNADDR(dma, 0) = 1127 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1128 } 1129 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1130 1131 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1132 KM_SLEEP); 1133 if (sc->sc_slots == NULL) { 1134 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1135 rv = ENOMEM; 1136 goto bad; 1137 } 1138 1139 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1140 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1141 if (sc->sc_xferpool == NULL) { 1142 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1143 err); 1144 rv = ENOMEM; 1145 goto bad; 1146 } 1147 1148 cv_init(&sc->sc_command_cv, "xhcicmd"); 1149 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1150 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1151 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1152 1153 struct xhci_erste *erst; 1154 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1155 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1156 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1157 erst[0].erste_3 = htole32(0); 1158 usb_syncmem(&sc->sc_eventst_dma, 0, 1159 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1160 1161 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1162 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1163 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1164 XHCI_ERDP_LO_BUSY); 1165 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1166 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1167 sc->sc_cr.xr_cs); 1168 1169 HEXDUMP("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1170 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1171 1172 if ((sc->sc_quirks & XHCI_DEFERRED_START) == 0) 1173 xhci_start(sc); 1174 1175 return 0; 1176 1177 bad: 1178 if (sc->sc_xferpool) { 1179 pool_cache_destroy(sc->sc_xferpool); 1180 sc->sc_xferpool = NULL; 1181 } 1182 1183 if (sc->sc_slots) { 1184 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1185 sc->sc_maxslots); 1186 sc->sc_slots = NULL; 1187 } 1188 1189 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1190 bad4: 1191 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1192 bad3: 1193 xhci_ring_free(sc, &sc->sc_er); 1194 bad2: 1195 xhci_ring_free(sc, &sc->sc_cr); 1196 i = sc->sc_maxspbuf; 1197 bad1: 1198 for (int j = 0; j < i; j++) 1199 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1200 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1201 1202 return rv; 1203 } 1204 1205 static inline bool 1206 xhci_polling_p(struct xhci_softc * const sc) 1207 { 1208 return sc->sc_bus.ub_usepolling || sc->sc_bus2.ub_usepolling; 1209 } 1210 1211 int 1212 xhci_intr(void *v) 1213 { 1214 struct xhci_softc * const sc = v; 1215 int ret = 0; 1216 1217 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1218 1219 if (sc == NULL) 1220 return 0; 1221 1222 mutex_spin_enter(&sc->sc_intr_lock); 1223 1224 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1225 goto done; 1226 1227 /* If we get an interrupt while polling, then just ignore it. */ 1228 if (xhci_polling_p(sc)) { 1229 #ifdef DIAGNOSTIC 1230 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1231 #endif 1232 goto done; 1233 } 1234 1235 ret = xhci_intr1(sc); 1236 if (ret) { 1237 usb_schedsoftintr(&sc->sc_bus); 1238 } 1239 done: 1240 mutex_spin_exit(&sc->sc_intr_lock); 1241 return ret; 1242 } 1243 1244 int 1245 xhci_intr1(struct xhci_softc * const sc) 1246 { 1247 uint32_t usbsts; 1248 uint32_t iman; 1249 1250 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1251 1252 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1253 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1254 #if 0 1255 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1256 return 0; 1257 } 1258 #endif 1259 xhci_op_write_4(sc, XHCI_USBSTS, 1260 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1261 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1262 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1263 1264 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1265 DPRINTFN(16, "IMAN0 %08jx", iman, 0, 0, 0); 1266 iman |= XHCI_IMAN_INTR_PEND; 1267 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1268 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1269 DPRINTFN(16, "IMAN0 %08jx", iman, 0, 0, 0); 1270 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1271 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1272 1273 return 1; 1274 } 1275 1276 /* 1277 * 3 port speed types used in USB stack 1278 * 1279 * usbdi speed 1280 * definition: USB_SPEED_* in usb.h 1281 * They are used in struct usbd_device in USB stack. 1282 * ioctl interface uses these values too. 1283 * port_status speed 1284 * definition: UPS_*_SPEED in usb.h 1285 * They are used in usb_port_status_t and valid only for USB 2.0. 1286 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1287 * of usb_port_status_ext_t indicates port speed. 1288 * Note that some 3.0 values overlap with 2.0 values. 1289 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1290 * means UPS_LOW_SPEED in HS.) 1291 * port status returned from hub also uses these values. 1292 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1293 * or more. 1294 * xspeed: 1295 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1296 * They are used in only slot context and PORTSC reg of xhci. 1297 * The difference between usbdi speed and xspeed is 1298 * that FS and LS values are swapped. 1299 */ 1300 1301 /* convert usbdi speed to xspeed */ 1302 static int 1303 xhci_speed2xspeed(int speed) 1304 { 1305 switch (speed) { 1306 case USB_SPEED_LOW: return 2; 1307 case USB_SPEED_FULL: return 1; 1308 default: return speed; 1309 } 1310 } 1311 1312 #if 0 1313 /* convert xspeed to usbdi speed */ 1314 static int 1315 xhci_xspeed2speed(int xspeed) 1316 { 1317 switch (xspeed) { 1318 case 1: return USB_SPEED_FULL; 1319 case 2: return USB_SPEED_LOW; 1320 default: return xspeed; 1321 } 1322 } 1323 #endif 1324 1325 /* convert xspeed to port status speed */ 1326 static int 1327 xhci_xspeed2psspeed(int xspeed) 1328 { 1329 switch (xspeed) { 1330 case 0: return 0; 1331 case 1: return UPS_FULL_SPEED; 1332 case 2: return UPS_LOW_SPEED; 1333 case 3: return UPS_HIGH_SPEED; 1334 default: return UPS_OTHER_SPEED; 1335 } 1336 } 1337 1338 /* 1339 * Construct input contexts and issue TRB to open pipe. 1340 */ 1341 static usbd_status 1342 xhci_configure_endpoint(struct usbd_pipe *pipe) 1343 { 1344 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1345 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1346 #ifdef USB_DEBUG 1347 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1348 #endif 1349 struct xhci_trb trb; 1350 usbd_status err; 1351 1352 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1353 DPRINTFN(4, "slot %ju dci %ju epaddr 0x%02jx attr 0x%02jx", 1354 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1355 pipe->up_endpoint->ue_edesc->bmAttributes); 1356 1357 /* XXX ensure input context is available? */ 1358 1359 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1360 1361 /* set up context */ 1362 xhci_setup_ctx(pipe); 1363 1364 HEXDUMP("input control context", xhci_slot_get_icv(sc, xs, 0), 1365 sc->sc_ctxsz * 1); 1366 HEXDUMP("input endpoint context", xhci_slot_get_icv(sc, xs, 1367 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1368 1369 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1370 trb.trb_2 = 0; 1371 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1372 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1373 1374 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1375 1376 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1377 HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, dci), 1378 sc->sc_ctxsz * 1); 1379 1380 return err; 1381 } 1382 1383 #if 0 1384 static usbd_status 1385 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1386 { 1387 #ifdef USB_DEBUG 1388 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1389 #endif 1390 1391 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1392 DPRINTFN(4, "slot %ju", xs->xs_idx, 0, 0, 0); 1393 1394 return USBD_NORMAL_COMPLETION; 1395 } 1396 #endif 1397 1398 /* 4.6.8, 6.4.3.7 */ 1399 static usbd_status 1400 xhci_reset_endpoint_locked(struct usbd_pipe *pipe) 1401 { 1402 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1403 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1404 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1405 struct xhci_trb trb; 1406 usbd_status err; 1407 1408 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1409 DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1410 1411 KASSERT(mutex_owned(&sc->sc_lock)); 1412 1413 trb.trb_0 = 0; 1414 trb.trb_2 = 0; 1415 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1416 XHCI_TRB_3_EP_SET(dci) | 1417 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1418 1419 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1420 1421 return err; 1422 } 1423 1424 static usbd_status 1425 xhci_reset_endpoint(struct usbd_pipe *pipe) 1426 { 1427 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1428 1429 mutex_enter(&sc->sc_lock); 1430 usbd_status ret = xhci_reset_endpoint_locked(pipe); 1431 mutex_exit(&sc->sc_lock); 1432 1433 return ret; 1434 } 1435 1436 /* 1437 * 4.6.9, 6.4.3.8 1438 * Stop execution of TDs on xfer ring. 1439 * Should be called with sc_lock held. 1440 */ 1441 static usbd_status 1442 xhci_stop_endpoint(struct usbd_pipe *pipe) 1443 { 1444 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1445 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1446 struct xhci_trb trb; 1447 usbd_status err; 1448 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1449 1450 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1451 DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1452 1453 KASSERT(mutex_owned(&sc->sc_lock)); 1454 1455 trb.trb_0 = 0; 1456 trb.trb_2 = 0; 1457 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1458 XHCI_TRB_3_EP_SET(dci) | 1459 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1460 1461 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1462 1463 return err; 1464 } 1465 1466 /* 1467 * Set TR Dequeue Pointer. 1468 * xHCI 1.1 4.6.10 6.4.3.9 1469 * Purge all of the TRBs on ring and reinitialize ring. 1470 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1471 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1472 * error will be generated. 1473 */ 1474 static usbd_status 1475 xhci_set_dequeue_locked(struct usbd_pipe *pipe) 1476 { 1477 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1478 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1479 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1480 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1481 struct xhci_trb trb; 1482 usbd_status err; 1483 1484 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1485 DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1486 1487 KASSERT(mutex_owned(&sc->sc_lock)); 1488 1489 xhci_host_dequeue(xr); 1490 1491 /* set DCS */ 1492 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1493 trb.trb_2 = 0; 1494 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1495 XHCI_TRB_3_EP_SET(dci) | 1496 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1497 1498 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1499 1500 return err; 1501 } 1502 1503 static usbd_status 1504 xhci_set_dequeue(struct usbd_pipe *pipe) 1505 { 1506 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1507 1508 mutex_enter(&sc->sc_lock); 1509 usbd_status ret = xhci_set_dequeue_locked(pipe); 1510 mutex_exit(&sc->sc_lock); 1511 1512 return ret; 1513 } 1514 1515 /* 1516 * Open new pipe: called from usbd_setup_pipe_flags. 1517 * Fills methods of pipe. 1518 * If pipe is not for ep0, calls configure_endpoint. 1519 */ 1520 static usbd_status 1521 xhci_open(struct usbd_pipe *pipe) 1522 { 1523 struct usbd_device * const dev = pipe->up_dev; 1524 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1525 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1526 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1527 1528 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1529 DPRINTFN(1, "addr %jd depth %jd port %jd speed %jd", dev->ud_addr, 1530 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1531 DPRINTFN(1, " dci %ju type 0x%02jx epaddr 0x%02jx attr 0x%02jx", 1532 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1533 ed->bmAttributes); 1534 DPRINTFN(1, " mps %ju ival %ju", UGETW(ed->wMaxPacketSize), 1535 ed->bInterval, 0, 0); 1536 1537 if (sc->sc_dying) 1538 return USBD_IOERROR; 1539 1540 /* Root Hub */ 1541 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1542 switch (ed->bEndpointAddress) { 1543 case USB_CONTROL_ENDPOINT: 1544 pipe->up_methods = &roothub_ctrl_methods; 1545 break; 1546 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1547 pipe->up_methods = &xhci_root_intr_methods; 1548 break; 1549 default: 1550 pipe->up_methods = NULL; 1551 DPRINTFN(0, "bad bEndpointAddress 0x%02jx", 1552 ed->bEndpointAddress, 0, 0, 0); 1553 return USBD_INVAL; 1554 } 1555 return USBD_NORMAL_COMPLETION; 1556 } 1557 1558 switch (xfertype) { 1559 case UE_CONTROL: 1560 pipe->up_methods = &xhci_device_ctrl_methods; 1561 break; 1562 case UE_ISOCHRONOUS: 1563 pipe->up_methods = &xhci_device_isoc_methods; 1564 return USBD_INVAL; 1565 break; 1566 case UE_BULK: 1567 pipe->up_methods = &xhci_device_bulk_methods; 1568 break; 1569 case UE_INTERRUPT: 1570 pipe->up_methods = &xhci_device_intr_methods; 1571 break; 1572 default: 1573 return USBD_IOERROR; 1574 break; 1575 } 1576 1577 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1578 return xhci_configure_endpoint(pipe); 1579 1580 return USBD_NORMAL_COMPLETION; 1581 } 1582 1583 /* 1584 * Closes pipe, called from usbd_kill_pipe via close methods. 1585 * If the endpoint to be closed is ep0, disable_slot. 1586 * Should be called with sc_lock held. 1587 */ 1588 static void 1589 xhci_close_pipe(struct usbd_pipe *pipe) 1590 { 1591 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1592 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1593 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1594 const u_int dci = xhci_ep_get_dci(ed); 1595 struct xhci_trb trb; 1596 uint32_t *cp; 1597 1598 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1599 1600 if (sc->sc_dying) 1601 return; 1602 1603 /* xs is uninitialized before xhci_init_slot */ 1604 if (xs == NULL || xs->xs_idx == 0) 1605 return; 1606 1607 DPRINTFN(4, "pipe %#jx slot %ju dci %ju", (uintptr_t)pipe, xs->xs_idx, 1608 dci, 0); 1609 1610 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1611 KASSERT(mutex_owned(&sc->sc_lock)); 1612 1613 if (pipe->up_dev->ud_depth == 0) 1614 return; 1615 1616 if (dci == XHCI_DCI_EP_CONTROL) { 1617 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1618 xhci_disable_slot(sc, xs->xs_idx); 1619 return; 1620 } 1621 1622 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED) 1623 (void)xhci_stop_endpoint(pipe); 1624 1625 /* 1626 * set appropriate bit to be dropped. 1627 * don't set DC bit to 1, otherwise all endpoints 1628 * would be deconfigured. 1629 */ 1630 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1631 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1632 cp[1] = htole32(0); 1633 1634 /* XXX should be most significant one, not dci? */ 1635 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1636 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1637 1638 /* configure ep context performs an implicit dequeue */ 1639 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 1640 1641 /* sync input contexts before they are read from memory */ 1642 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1643 1644 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1645 trb.trb_2 = 0; 1646 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1647 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1648 1649 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1650 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1651 } 1652 1653 /* 1654 * Abort transfer. 1655 * Should be called with sc_lock held. 1656 */ 1657 static void 1658 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1659 { 1660 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1661 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1662 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1663 1664 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1665 DPRINTFN(4, "xfer %#jx pipe %#jx status %jd", 1666 (uintptr_t)xfer, (uintptr_t)xfer->ux_pipe, status, 0); 1667 1668 KASSERT(mutex_owned(&sc->sc_lock)); 1669 1670 if (sc->sc_dying) { 1671 /* If we're dying, just do the software part. */ 1672 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 1673 xfer->ux_status, 0, 0); 1674 xfer->ux_status = status; 1675 callout_stop(&xfer->ux_callout); 1676 usb_transfer_complete(xfer); 1677 return; 1678 } 1679 1680 /* 1681 * If an abort is already in progress then just wait for it to 1682 * complete and return. 1683 */ 1684 if (xfer->ux_hcflags & UXFER_ABORTING) { 1685 DPRINTFN(4, "already aborting", 0, 0, 0, 0); 1686 #ifdef DIAGNOSTIC 1687 if (status == USBD_TIMEOUT) 1688 DPRINTFN(4, "TIMEOUT while aborting", 0, 0, 0, 0); 1689 #endif 1690 /* Override the status which might be USBD_TIMEOUT. */ 1691 xfer->ux_status = status; 1692 DPRINTFN(4, "xfer %#jx waiting for abort to finish", 1693 (uintptr_t)xfer, 0, 0, 0); 1694 xfer->ux_hcflags |= UXFER_ABORTWAIT; 1695 while (xfer->ux_hcflags & UXFER_ABORTING) 1696 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 1697 return; 1698 } 1699 xfer->ux_hcflags |= UXFER_ABORTING; 1700 1701 /* 1702 * Step 1: Stop xfer timeout timer. 1703 */ 1704 xfer->ux_status = status; 1705 callout_stop(&xfer->ux_callout); 1706 1707 /* 1708 * Step 2: Stop execution of TD on the ring. 1709 */ 1710 switch (xhci_get_epstate(sc, xs, dci)) { 1711 case XHCI_EPSTATE_HALTED: 1712 (void)xhci_reset_endpoint_locked(xfer->ux_pipe); 1713 break; 1714 case XHCI_EPSTATE_STOPPED: 1715 break; 1716 default: 1717 (void)xhci_stop_endpoint(xfer->ux_pipe); 1718 break; 1719 } 1720 #ifdef DIAGNOSTIC 1721 uint32_t epst = xhci_get_epstate(sc, xs, dci); 1722 if (epst != XHCI_EPSTATE_STOPPED) 1723 DPRINTFN(4, "dci %ju not stopped %ju", dci, epst, 0, 0); 1724 #endif 1725 1726 /* 1727 * Step 3: Remove any vestiges of the xfer from the ring. 1728 */ 1729 xhci_set_dequeue_locked(xfer->ux_pipe); 1730 1731 /* 1732 * Step 4: Notify completion to waiting xfers. 1733 */ 1734 int wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 1735 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 1736 usb_transfer_complete(xfer); 1737 if (wake) { 1738 cv_broadcast(&xfer->ux_hccv); 1739 } 1740 DPRINTFN(14, "end", 0, 0, 0, 0); 1741 1742 KASSERT(mutex_owned(&sc->sc_lock)); 1743 } 1744 1745 static void 1746 xhci_host_dequeue(struct xhci_ring * const xr) 1747 { 1748 /* When dequeueing the controller, update our struct copy too */ 1749 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1750 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1751 BUS_DMASYNC_PREWRITE); 1752 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1753 1754 xr->xr_ep = 0; 1755 xr->xr_cs = 1; 1756 } 1757 1758 /* 1759 * Recover STALLed endpoint. 1760 * xHCI 1.1 sect 4.10.2.1 1761 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1762 * all transfers on transfer ring. 1763 * These are done in thread context asynchronously. 1764 */ 1765 static void 1766 xhci_clear_endpoint_stall_async_task(void *cookie) 1767 { 1768 struct usbd_xfer * const xfer = cookie; 1769 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1770 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1771 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1772 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1773 1774 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1775 DPRINTFN(4, "xfer %#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, 1776 dci, 0); 1777 1778 xhci_reset_endpoint(xfer->ux_pipe); 1779 xhci_set_dequeue(xfer->ux_pipe); 1780 1781 mutex_enter(&sc->sc_lock); 1782 tr->is_halted = false; 1783 usb_transfer_complete(xfer); 1784 mutex_exit(&sc->sc_lock); 1785 DPRINTFN(4, "ends", 0, 0, 0, 0); 1786 } 1787 1788 static usbd_status 1789 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1790 { 1791 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1792 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1793 1794 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1795 DPRINTFN(4, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 1796 1797 if (sc->sc_dying) { 1798 return USBD_IOERROR; 1799 } 1800 1801 usb_init_task(&xp->xp_async_task, 1802 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1803 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1804 DPRINTFN(4, "ends", 0, 0, 0, 0); 1805 1806 return USBD_NORMAL_COMPLETION; 1807 } 1808 1809 /* Process roothub port status/change events and notify to uhub_intr. */ 1810 static void 1811 xhci_rhpsc(struct xhci_softc * const sc, u_int ctlrport) 1812 { 1813 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1814 DPRINTFN(4, "xhci%jd: port %ju status change", device_unit(sc->sc_dev), 1815 ctlrport, 0, 0); 1816 1817 if (ctlrport > sc->sc_maxports) 1818 return; 1819 1820 const size_t bn = xhci_ctlrport2bus(sc, ctlrport); 1821 const size_t rhp = xhci_ctlrport2rhport(sc, ctlrport); 1822 struct usbd_xfer * const xfer = sc->sc_intrxfer[bn]; 1823 1824 DPRINTFN(4, "xhci%jd: bus %jd bp %ju xfer %#jx status change", 1825 device_unit(sc->sc_dev), bn, rhp, (uintptr_t)xfer); 1826 1827 if (xfer == NULL) 1828 return; 1829 1830 uint8_t *p = xfer->ux_buf; 1831 memset(p, 0, xfer->ux_length); 1832 p[rhp / NBBY] |= 1 << (rhp % NBBY); 1833 xfer->ux_actlen = xfer->ux_length; 1834 xfer->ux_status = USBD_NORMAL_COMPLETION; 1835 usb_transfer_complete(xfer); 1836 } 1837 1838 /* Process Transfer Events */ 1839 static void 1840 xhci_event_transfer(struct xhci_softc * const sc, 1841 const struct xhci_trb * const trb) 1842 { 1843 uint64_t trb_0; 1844 uint32_t trb_2, trb_3; 1845 uint8_t trbcode; 1846 u_int slot, dci; 1847 struct xhci_slot *xs; 1848 struct xhci_ring *xr; 1849 struct xhci_xfer *xx; 1850 struct usbd_xfer *xfer; 1851 usbd_status err; 1852 1853 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1854 1855 trb_0 = le64toh(trb->trb_0); 1856 trb_2 = le32toh(trb->trb_2); 1857 trb_3 = le32toh(trb->trb_3); 1858 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1859 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1860 dci = XHCI_TRB_3_EP_GET(trb_3); 1861 xs = &sc->sc_slots[slot]; 1862 xr = &xs->xs_ep[dci].xe_tr; 1863 1864 /* sanity check */ 1865 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1866 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1867 1868 int idx = 0; 1869 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1870 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1871 DPRINTFN(0, "invalid trb_0 0x%jx", trb_0, 0, 0, 0); 1872 return; 1873 } 1874 xx = xr->xr_cookies[idx]; 1875 1876 /* clear cookie of consumed TRB */ 1877 xr->xr_cookies[idx] = NULL; 1878 1879 /* 1880 * xx is NULL if pipe is opened but xfer is not started. 1881 * It happens when stopping idle pipe. 1882 */ 1883 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1884 DPRINTFN(1, "Ignore #%ju: cookie %#jx cc %ju dci %ju", 1885 idx, (uintptr_t)xx, trbcode, dci); 1886 DPRINTFN(1, " orig TRB %jx type %ju", trb_0, 1887 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1888 0, 0); 1889 return; 1890 } 1891 } else { 1892 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1893 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1894 } 1895 /* XXX this may not happen */ 1896 if (xx == NULL) { 1897 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1898 return; 1899 } 1900 xfer = &xx->xx_xfer; 1901 /* XXX this may happen when detaching */ 1902 if (xfer == NULL) { 1903 DPRINTFN(1, "xx(%#jx)->xx_xfer is NULL trb_0 %#jx", 1904 (uintptr_t)xx, trb_0, 0, 0); 1905 return; 1906 } 1907 DPRINTFN(14, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 1908 /* XXX I dunno why this happens */ 1909 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1910 1911 if (!xfer->ux_pipe->up_repeat && 1912 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1913 DPRINTFN(1, "xfer(%#jx)->pipe not queued", (uintptr_t)xfer, 1914 0, 0, 0); 1915 return; 1916 } 1917 1918 /* 4.11.5.2 Event Data TRB */ 1919 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1920 DPRINTFN(14, "transfer Event Data: 0x%016jx 0x%08jx" 1921 " %02jx", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1922 if ((trb_0 & 0x3) == 0x3) { 1923 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1924 } 1925 } 1926 1927 switch (trbcode) { 1928 case XHCI_TRB_ERROR_SHORT_PKT: 1929 case XHCI_TRB_ERROR_SUCCESS: 1930 /* 1931 * A ctrl transfer can generate two events if it has a Data 1932 * stage. A short data stage can be OK and should not 1933 * complete the transfer as the status stage needs to be 1934 * performed. 1935 * 1936 * Note: Data and Status stage events point at same xfer. 1937 * ux_actlen and ux_dmabuf will be passed to 1938 * usb_transfer_complete after the Status stage event. 1939 * 1940 * It can be distingished which stage generates the event: 1941 * + by checking least 3 bits of trb_0 if ED==1. 1942 * (see xhci_device_ctrl_start). 1943 * + by checking the type of original TRB if ED==0. 1944 * 1945 * In addition, intr, bulk, and isoc transfer currently 1946 * consists of single TD, so the "skip" is not needed. 1947 * ctrl xfer uses EVENT_DATA, and others do not. 1948 * Thus driver can switch the flow by checking ED bit. 1949 */ 1950 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1951 if (xfer->ux_actlen == 0) 1952 xfer->ux_actlen = xfer->ux_length - 1953 XHCI_TRB_2_REM_GET(trb_2); 1954 if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)) 1955 == XHCI_TRB_TYPE_DATA_STAGE) { 1956 return; 1957 } 1958 } else if ((trb_0 & 0x3) == 0x3) { 1959 return; 1960 } 1961 err = USBD_NORMAL_COMPLETION; 1962 break; 1963 case XHCI_TRB_ERROR_STOPPED: 1964 case XHCI_TRB_ERROR_LENGTH: 1965 case XHCI_TRB_ERROR_STOPPED_SHORT: 1966 /* 1967 * don't complete the transfer being aborted 1968 * as abort_xfer does instead. 1969 */ 1970 if (xfer->ux_hcflags & UXFER_ABORTING) { 1971 DPRINTFN(14, "ignore aborting xfer %#jx", 1972 (uintptr_t)xfer, 0, 0, 0); 1973 return; 1974 } 1975 err = USBD_CANCELLED; 1976 break; 1977 case XHCI_TRB_ERROR_STALL: 1978 case XHCI_TRB_ERROR_BABBLE: 1979 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 1980 xr->is_halted = true; 1981 err = USBD_STALLED; 1982 /* 1983 * Stalled endpoints can be recoverd by issuing 1984 * command TRB TYPE_RESET_EP on xHCI instead of 1985 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1986 * on the endpoint. However, this function may be 1987 * called from softint context (e.g. from umass), 1988 * in that case driver gets KASSERT in cv_timedwait 1989 * in xhci_do_command. 1990 * To avoid this, this runs reset_endpoint and 1991 * usb_transfer_complete in usb task thread 1992 * asynchronously (and then umass issues clear 1993 * UF_ENDPOINT_HALT). 1994 */ 1995 xfer->ux_status = err; 1996 callout_stop(&xfer->ux_callout); 1997 xhci_clear_endpoint_stall_async(xfer); 1998 return; 1999 default: 2000 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 2001 err = USBD_IOERROR; 2002 break; 2003 } 2004 xfer->ux_status = err; 2005 2006 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 2007 if ((trb_0 & 0x3) == 0x0) { 2008 callout_stop(&xfer->ux_callout); 2009 usb_transfer_complete(xfer); 2010 } 2011 } else { 2012 callout_stop(&xfer->ux_callout); 2013 usb_transfer_complete(xfer); 2014 } 2015 } 2016 2017 /* Process Command complete events */ 2018 static void 2019 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 2020 { 2021 uint64_t trb_0; 2022 uint32_t trb_2, trb_3; 2023 2024 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2025 2026 KASSERT(mutex_owned(&sc->sc_lock)); 2027 2028 trb_0 = le64toh(trb->trb_0); 2029 trb_2 = le32toh(trb->trb_2); 2030 trb_3 = le32toh(trb->trb_3); 2031 2032 if (trb_0 == sc->sc_command_addr) { 2033 sc->sc_resultpending = false; 2034 2035 sc->sc_result_trb.trb_0 = trb_0; 2036 sc->sc_result_trb.trb_2 = trb_2; 2037 sc->sc_result_trb.trb_3 = trb_3; 2038 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2039 XHCI_TRB_ERROR_SUCCESS) { 2040 DPRINTFN(1, "command completion " 2041 "failure: 0x%016jx 0x%08jx 0x%08jx", 2042 trb_0, trb_2, trb_3, 0); 2043 } 2044 cv_signal(&sc->sc_command_cv); 2045 } else { 2046 DPRINTFN(1, "spurious event: %#jx 0x%016jx " 2047 "0x%08jx 0x%08jx", (uintptr_t)trb, trb_0, trb_2, trb_3); 2048 } 2049 } 2050 2051 /* 2052 * Process events. 2053 * called from xhci_softintr 2054 */ 2055 static void 2056 xhci_handle_event(struct xhci_softc * const sc, 2057 const struct xhci_trb * const trb) 2058 { 2059 uint64_t trb_0; 2060 uint32_t trb_2, trb_3; 2061 2062 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2063 2064 trb_0 = le64toh(trb->trb_0); 2065 trb_2 = le32toh(trb->trb_2); 2066 trb_3 = le32toh(trb->trb_3); 2067 2068 DPRINTFN(14, "event: %#jx 0x%016jx 0x%08jx 0x%08jx", 2069 (uintptr_t)trb, trb_0, trb_2, trb_3); 2070 2071 /* 2072 * 4.11.3.1, 6.4.2.1 2073 * TRB Pointer is invalid for these completion codes. 2074 */ 2075 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2076 case XHCI_TRB_ERROR_RING_UNDERRUN: 2077 case XHCI_TRB_ERROR_RING_OVERRUN: 2078 case XHCI_TRB_ERROR_VF_RING_FULL: 2079 return; 2080 default: 2081 if (trb_0 == 0) { 2082 return; 2083 } 2084 break; 2085 } 2086 2087 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2088 case XHCI_TRB_EVENT_TRANSFER: 2089 xhci_event_transfer(sc, trb); 2090 break; 2091 case XHCI_TRB_EVENT_CMD_COMPLETE: 2092 xhci_event_cmd(sc, trb); 2093 break; 2094 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2095 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2096 break; 2097 default: 2098 break; 2099 } 2100 } 2101 2102 static void 2103 xhci_softintr(void *v) 2104 { 2105 struct usbd_bus * const bus = v; 2106 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2107 struct xhci_ring * const er = &sc->sc_er; 2108 struct xhci_trb *trb; 2109 int i, j, k; 2110 2111 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2112 2113 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 2114 2115 i = er->xr_ep; 2116 j = er->xr_cs; 2117 2118 DPRINTFN(16, "er: xr_ep %jd xr_cs %jd", i, j, 0, 0); 2119 2120 while (1) { 2121 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2122 BUS_DMASYNC_POSTREAD); 2123 trb = &er->xr_trb[i]; 2124 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2125 2126 if (j != k) 2127 break; 2128 2129 xhci_handle_event(sc, trb); 2130 2131 i++; 2132 if (i == er->xr_ntrb) { 2133 i = 0; 2134 j ^= 1; 2135 } 2136 } 2137 2138 er->xr_ep = i; 2139 er->xr_cs = j; 2140 2141 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2142 XHCI_ERDP_LO_BUSY); 2143 2144 DPRINTFN(16, "ends", 0, 0, 0, 0); 2145 2146 return; 2147 } 2148 2149 static void 2150 xhci_poll(struct usbd_bus *bus) 2151 { 2152 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2153 2154 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2155 2156 mutex_spin_enter(&sc->sc_intr_lock); 2157 int ret = xhci_intr1(sc); 2158 if (ret) { 2159 xhci_softintr(bus); 2160 } 2161 mutex_spin_exit(&sc->sc_intr_lock); 2162 2163 return; 2164 } 2165 2166 static struct usbd_xfer * 2167 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2168 { 2169 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2170 struct usbd_xfer *xfer; 2171 2172 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2173 2174 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 2175 if (xfer != NULL) { 2176 memset(xfer, 0, sizeof(struct xhci_xfer)); 2177 #ifdef DIAGNOSTIC 2178 xfer->ux_state = XFER_BUSY; 2179 #endif 2180 } 2181 2182 return xfer; 2183 } 2184 2185 static void 2186 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2187 { 2188 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2189 2190 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2191 2192 #ifdef DIAGNOSTIC 2193 if (xfer->ux_state != XFER_BUSY) { 2194 DPRINTFN(0, "xfer=%#jx not busy, 0x%08jx", 2195 (uintptr_t)xfer, xfer->ux_state, 0, 0); 2196 } 2197 xfer->ux_state = XFER_FREE; 2198 #endif 2199 pool_cache_put(sc->sc_xferpool, xfer); 2200 } 2201 2202 static void 2203 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2204 { 2205 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2206 2207 *lock = &sc->sc_lock; 2208 } 2209 2210 extern uint32_t usb_cookie_no; 2211 2212 /* 2213 * xHCI 4.3 2214 * Called when uhub_explore finds a new device (via usbd_new_device). 2215 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2216 * This function does: 2217 * Allocate and construct dev structure of default endpoint (ep0). 2218 * Allocate and open pipe of ep0. 2219 * Enable slot and initialize slot context. 2220 * Set Address. 2221 * Read initial device descriptor. 2222 * Determine initial MaxPacketSize (mps) by speed. 2223 * Read full device descriptor. 2224 * Register this device. 2225 * Finally state of device transitions ADDRESSED. 2226 */ 2227 static usbd_status 2228 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2229 int speed, int port, struct usbd_port *up) 2230 { 2231 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2232 struct usbd_device *dev; 2233 usbd_status err; 2234 usb_device_descriptor_t *dd; 2235 struct xhci_slot *xs; 2236 uint32_t *cp; 2237 2238 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2239 DPRINTFN(4, "port %ju depth %ju speed %ju up %#jx", 2240 port, depth, speed, (uintptr_t)up); 2241 2242 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2243 dev->ud_bus = bus; 2244 dev->ud_quirks = &usbd_no_quirk; 2245 dev->ud_addr = 0; 2246 dev->ud_ddesc.bMaxPacketSize = 0; 2247 dev->ud_depth = depth; 2248 dev->ud_powersrc = up; 2249 dev->ud_myhub = up->up_parent; 2250 dev->ud_speed = speed; 2251 dev->ud_langid = USBD_NOLANG; 2252 dev->ud_cookie.cookie = ++usb_cookie_no; 2253 2254 /* Set up default endpoint handle. */ 2255 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2256 /* doesn't matter, just don't let it uninitialized */ 2257 dev->ud_ep0.ue_toggle = 0; 2258 2259 /* Set up default endpoint descriptor. */ 2260 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2261 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2262 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2263 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2264 dev->ud_ep0desc.bInterval = 0; 2265 2266 /* 4.3, 4.8.2.1 */ 2267 switch (speed) { 2268 case USB_SPEED_SUPER: 2269 case USB_SPEED_SUPER_PLUS: 2270 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2271 break; 2272 case USB_SPEED_FULL: 2273 /* XXX using 64 as initial mps of ep0 in FS */ 2274 case USB_SPEED_HIGH: 2275 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2276 break; 2277 case USB_SPEED_LOW: 2278 default: 2279 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2280 break; 2281 } 2282 2283 up->up_dev = dev; 2284 2285 /* Establish the default pipe. */ 2286 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2287 &dev->ud_pipe0); 2288 if (err) { 2289 goto bad; 2290 } 2291 2292 dd = &dev->ud_ddesc; 2293 2294 if (depth == 0 && port == 0) { 2295 KASSERT(bus->ub_devices[USB_ROOTHUB_INDEX] == NULL); 2296 bus->ub_devices[USB_ROOTHUB_INDEX] = dev; 2297 err = usbd_get_initial_ddesc(dev, dd); 2298 if (err) { 2299 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2300 goto bad; 2301 } 2302 2303 err = usbd_reload_device_desc(dev); 2304 if (err) { 2305 DPRINTFN(1, "reload desc %ju", err, 0, 0, 0); 2306 goto bad; 2307 } 2308 } else { 2309 uint8_t slot = 0; 2310 2311 /* 4.3.2 */ 2312 err = xhci_enable_slot(sc, &slot); 2313 if (err) { 2314 DPRINTFN(1, "enable slot %ju", err, 0, 0, 0); 2315 goto bad; 2316 } 2317 2318 xs = &sc->sc_slots[slot]; 2319 dev->ud_hcpriv = xs; 2320 2321 /* 4.3.3 initialize slot structure */ 2322 err = xhci_init_slot(dev, slot); 2323 if (err) { 2324 DPRINTFN(1, "init slot %ju", err, 0, 0, 0); 2325 dev->ud_hcpriv = NULL; 2326 /* 2327 * We have to disable_slot here because 2328 * xs->xs_idx == 0 when xhci_init_slot fails, 2329 * in that case usbd_remove_dev won't work. 2330 */ 2331 mutex_enter(&sc->sc_lock); 2332 xhci_disable_slot(sc, slot); 2333 mutex_exit(&sc->sc_lock); 2334 goto bad; 2335 } 2336 2337 /* 4.3.4 Address Assignment */ 2338 err = xhci_set_address(dev, slot, false); 2339 if (err) { 2340 DPRINTFN(1, "set address w/o bsr %ju", err, 0, 0, 0); 2341 goto bad; 2342 } 2343 2344 /* Allow device time to set new address */ 2345 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2346 2347 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2348 HEXDUMP("slot context", cp, sc->sc_ctxsz); 2349 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3])); 2350 DPRINTFN(4, "device address %ju", addr, 0, 0, 0); 2351 /* 2352 * XXX ensure we know when the hardware does something 2353 * we can't yet cope with 2354 */ 2355 KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr); 2356 dev->ud_addr = addr; 2357 2358 KASSERTMSG(bus->ub_devices[usb_addr2dindex(dev->ud_addr)] == NULL, 2359 "addr %d already allocated", dev->ud_addr); 2360 /* 2361 * The root hub is given its own slot 2362 */ 2363 bus->ub_devices[usb_addr2dindex(dev->ud_addr)] = dev; 2364 2365 err = usbd_get_initial_ddesc(dev, dd); 2366 if (err) { 2367 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2368 goto bad; 2369 } 2370 2371 /* 4.8.2.1 */ 2372 if (USB_IS_SS(speed)) { 2373 if (dd->bMaxPacketSize != 9) { 2374 printf("%s: invalid mps 2^%u for SS ep0," 2375 " using 512\n", 2376 device_xname(sc->sc_dev), 2377 dd->bMaxPacketSize); 2378 dd->bMaxPacketSize = 9; 2379 } 2380 USETW(dev->ud_ep0desc.wMaxPacketSize, 2381 (1 << dd->bMaxPacketSize)); 2382 } else 2383 USETW(dev->ud_ep0desc.wMaxPacketSize, 2384 dd->bMaxPacketSize); 2385 DPRINTFN(4, "bMaxPacketSize %ju", dd->bMaxPacketSize, 0, 0, 0); 2386 err = xhci_update_ep0_mps(sc, xs, 2387 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2388 if (err) { 2389 DPRINTFN(1, "update mps of ep0 %ju", err, 0, 0, 0); 2390 goto bad; 2391 } 2392 2393 err = usbd_reload_device_desc(dev); 2394 if (err) { 2395 DPRINTFN(1, "reload desc %ju", err, 0, 0, 0); 2396 goto bad; 2397 } 2398 } 2399 2400 DPRINTFN(1, "adding unit addr=%jd, rev=%02jx,", 2401 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2402 DPRINTFN(1, " class=%jd, subclass=%jd, protocol=%jd,", 2403 dd->bDeviceClass, dd->bDeviceSubClass, 2404 dd->bDeviceProtocol, 0); 2405 DPRINTFN(1, " mps=%jd, len=%jd, noconf=%jd, speed=%jd", 2406 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2407 dev->ud_speed); 2408 2409 usbd_get_device_strings(dev); 2410 2411 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2412 2413 if (depth == 0 && port == 0) { 2414 usbd_attach_roothub(parent, dev); 2415 DPRINTFN(1, "root hub %#jx", (uintptr_t)dev, 0, 0, 0); 2416 return USBD_NORMAL_COMPLETION; 2417 } 2418 2419 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2420 bad: 2421 if (err != USBD_NORMAL_COMPLETION) { 2422 usbd_remove_device(dev, up); 2423 } 2424 2425 return err; 2426 } 2427 2428 static usbd_status 2429 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2430 size_t ntrb, size_t align) 2431 { 2432 usbd_status err; 2433 size_t size = ntrb * XHCI_TRB_SIZE; 2434 2435 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2436 2437 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2438 if (err) 2439 return err; 2440 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2441 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2442 xr->xr_trb = xhci_ring_trbv(xr, 0); 2443 xr->xr_ntrb = ntrb; 2444 xr->is_halted = false; 2445 xhci_host_dequeue(xr); 2446 2447 return USBD_NORMAL_COMPLETION; 2448 } 2449 2450 static void 2451 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2452 { 2453 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2454 mutex_destroy(&xr->xr_lock); 2455 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2456 } 2457 2458 static void 2459 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2460 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2461 { 2462 size_t i; 2463 u_int ri; 2464 u_int cs; 2465 uint64_t parameter; 2466 uint32_t status; 2467 uint32_t control; 2468 2469 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2470 2471 KASSERTMSG(ntrbs <= XHCI_XFER_NTRB, "ntrbs %zu", ntrbs); 2472 for (i = 0; i < ntrbs; i++) { 2473 DPRINTFN(12, "xr %#jx trbs %#jx num %ju", (uintptr_t)xr, 2474 (uintptr_t)trbs, i, 0); 2475 DPRINTFN(12, " %016jx %08jx %08jx", 2476 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2477 KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2478 XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3); 2479 } 2480 2481 DPRINTFN(12, "%#jx xr_ep 0x%jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep, 2482 xr->xr_cs, 0); 2483 2484 ri = xr->xr_ep; 2485 cs = xr->xr_cs; 2486 2487 /* 2488 * Although the xhci hardware can do scatter/gather dma from 2489 * arbitrary sized buffers, there is a non-obvious restriction 2490 * that a LINK trb is only allowed at the end of a burst of 2491 * transfers - which might be 16kB. 2492 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2493 * The simple solution is not to allow a LINK trb in the middle 2494 * of anything - as here. 2495 * XXX: (dsl) There are xhci controllers out there (eg some made by 2496 * ASMedia) that seem to lock up if they process a LINK trb but 2497 * cannot process the linked-to trb yet. 2498 * The code should write the 'cycle' bit on the link trb AFTER 2499 * adding the other trb. 2500 */ 2501 u_int firstep = xr->xr_ep; 2502 u_int firstcs = xr->xr_cs; 2503 2504 for (i = 0; i < ntrbs; ) { 2505 u_int oldri = ri; 2506 u_int oldcs = cs; 2507 2508 if (ri >= (xr->xr_ntrb - 1)) { 2509 /* Put Link TD at the end of ring */ 2510 parameter = xhci_ring_trbp(xr, 0); 2511 status = 0; 2512 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2513 XHCI_TRB_3_TC_BIT; 2514 xr->xr_cookies[ri] = NULL; 2515 xr->xr_ep = 0; 2516 xr->xr_cs ^= 1; 2517 ri = xr->xr_ep; 2518 cs = xr->xr_cs; 2519 } else { 2520 parameter = trbs[i].trb_0; 2521 status = trbs[i].trb_2; 2522 control = trbs[i].trb_3; 2523 2524 xr->xr_cookies[ri] = cookie; 2525 ri++; 2526 i++; 2527 } 2528 /* 2529 * If this is a first TRB, mark it invalid to prevent 2530 * xHC from running it immediately. 2531 */ 2532 if (oldri == firstep) { 2533 if (oldcs) { 2534 control &= ~XHCI_TRB_3_CYCLE_BIT; 2535 } else { 2536 control |= XHCI_TRB_3_CYCLE_BIT; 2537 } 2538 } else { 2539 if (oldcs) { 2540 control |= XHCI_TRB_3_CYCLE_BIT; 2541 } else { 2542 control &= ~XHCI_TRB_3_CYCLE_BIT; 2543 } 2544 } 2545 xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control); 2546 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri, 2547 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2548 } 2549 2550 /* Now invert cycle bit of first TRB */ 2551 if (firstcs) { 2552 xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 2553 } else { 2554 xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 2555 } 2556 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep, 2557 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2558 2559 xr->xr_ep = ri; 2560 xr->xr_cs = cs; 2561 2562 DPRINTFN(12, "%#jx xr_ep 0x%jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep, 2563 xr->xr_cs, 0); 2564 } 2565 2566 /* 2567 * Stop execution commands, purge all commands on command ring, and 2568 * rewind dequeue pointer. 2569 */ 2570 static void 2571 xhci_abort_command(struct xhci_softc *sc) 2572 { 2573 struct xhci_ring * const cr = &sc->sc_cr; 2574 uint64_t crcr; 2575 int i; 2576 2577 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2578 DPRINTFN(14, "command %#jx timeout, aborting", 2579 sc->sc_command_addr, 0, 0, 0); 2580 2581 mutex_enter(&cr->xr_lock); 2582 2583 /* 4.6.1.2 Aborting a Command */ 2584 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2585 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2586 2587 for (i = 0; i < 500; i++) { 2588 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2589 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2590 break; 2591 usb_delay_ms(&sc->sc_bus, 1); 2592 } 2593 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2594 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2595 /* reset HC here? */ 2596 } 2597 2598 /* reset command ring dequeue pointer */ 2599 cr->xr_ep = 0; 2600 cr->xr_cs = 1; 2601 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2602 2603 mutex_exit(&cr->xr_lock); 2604 } 2605 2606 /* 2607 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2608 * Command completion is notified by cv_signal from xhci_event_cmd() 2609 * (called from xhci_softint), or timed-out. 2610 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2611 * then do_command examines it. 2612 */ 2613 static usbd_status 2614 xhci_do_command_locked(struct xhci_softc * const sc, 2615 struct xhci_trb * const trb, int timeout) 2616 { 2617 struct xhci_ring * const cr = &sc->sc_cr; 2618 usbd_status err; 2619 2620 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2621 DPRINTFN(12, "input: 0x%016jx 0x%08jx 0x%08jx", 2622 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2623 2624 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2625 KASSERT(mutex_owned(&sc->sc_lock)); 2626 2627 while (sc->sc_command_addr != 0) 2628 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 2629 2630 /* 2631 * If enqueue pointer points at last of ring, it's Link TRB, 2632 * command TRB will be stored in 0th TRB. 2633 */ 2634 if (cr->xr_ep == cr->xr_ntrb - 1) 2635 sc->sc_command_addr = xhci_ring_trbp(cr, 0); 2636 else 2637 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2638 2639 sc->sc_resultpending = true; 2640 2641 mutex_enter(&cr->xr_lock); 2642 xhci_ring_put(sc, cr, NULL, trb, 1); 2643 mutex_exit(&cr->xr_lock); 2644 2645 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2646 2647 while (sc->sc_resultpending) { 2648 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2649 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2650 xhci_abort_command(sc); 2651 err = USBD_TIMEOUT; 2652 goto timedout; 2653 } 2654 } 2655 2656 trb->trb_0 = sc->sc_result_trb.trb_0; 2657 trb->trb_2 = sc->sc_result_trb.trb_2; 2658 trb->trb_3 = sc->sc_result_trb.trb_3; 2659 2660 DPRINTFN(12, "output: 0x%016jx 0x%08jx 0x%08jx", 2661 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2662 2663 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2664 case XHCI_TRB_ERROR_SUCCESS: 2665 err = USBD_NORMAL_COMPLETION; 2666 break; 2667 default: 2668 case 192 ... 223: 2669 err = USBD_IOERROR; 2670 break; 2671 case 224 ... 255: 2672 err = USBD_NORMAL_COMPLETION; 2673 break; 2674 } 2675 2676 timedout: 2677 sc->sc_resultpending = false; 2678 sc->sc_command_addr = 0; 2679 cv_broadcast(&sc->sc_cmdbusy_cv); 2680 2681 return err; 2682 } 2683 2684 static usbd_status 2685 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2686 int timeout) 2687 { 2688 2689 mutex_enter(&sc->sc_lock); 2690 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2691 mutex_exit(&sc->sc_lock); 2692 2693 return ret; 2694 } 2695 2696 static usbd_status 2697 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2698 { 2699 struct xhci_trb trb; 2700 usbd_status err; 2701 2702 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2703 2704 trb.trb_0 = 0; 2705 trb.trb_2 = 0; 2706 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2707 2708 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2709 if (err != USBD_NORMAL_COMPLETION) { 2710 return err; 2711 } 2712 2713 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2714 2715 return err; 2716 } 2717 2718 /* 2719 * xHCI 4.6.4 2720 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2721 * All endpoints in the slot should be stopped. 2722 * Should be called with sc_lock held. 2723 */ 2724 static usbd_status 2725 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2726 { 2727 struct xhci_trb trb; 2728 struct xhci_slot *xs; 2729 usbd_status err; 2730 2731 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2732 2733 if (sc->sc_dying) 2734 return USBD_IOERROR; 2735 2736 trb.trb_0 = 0; 2737 trb.trb_2 = 0; 2738 trb.trb_3 = htole32( 2739 XHCI_TRB_3_SLOT_SET(slot) | 2740 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2741 2742 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2743 2744 if (!err) { 2745 xs = &sc->sc_slots[slot]; 2746 if (xs->xs_idx != 0) { 2747 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2748 xhci_set_dcba(sc, 0, slot); 2749 memset(xs, 0, sizeof(*xs)); 2750 } 2751 } 2752 2753 return err; 2754 } 2755 2756 /* 2757 * Set address of device and transition slot state from ENABLED to ADDRESSED 2758 * if Block Setaddress Request (BSR) is false. 2759 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2760 * see xHCI 1.1 4.5.3, 3.3.4 2761 * Should be called without sc_lock held. 2762 */ 2763 static usbd_status 2764 xhci_address_device(struct xhci_softc * const sc, 2765 uint64_t icp, uint8_t slot_id, bool bsr) 2766 { 2767 struct xhci_trb trb; 2768 usbd_status err; 2769 2770 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2771 2772 trb.trb_0 = icp; 2773 trb.trb_2 = 0; 2774 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2775 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2776 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2777 2778 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2779 2780 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2781 err = USBD_NO_ADDR; 2782 2783 return err; 2784 } 2785 2786 static usbd_status 2787 xhci_update_ep0_mps(struct xhci_softc * const sc, 2788 struct xhci_slot * const xs, u_int mps) 2789 { 2790 struct xhci_trb trb; 2791 usbd_status err; 2792 uint32_t * cp; 2793 2794 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2795 DPRINTFN(4, "slot %ju mps %ju", xs->xs_idx, mps, 0, 0); 2796 2797 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2798 cp[0] = htole32(0); 2799 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2800 2801 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2802 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2803 2804 /* sync input contexts before they are read from memory */ 2805 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2806 HEXDUMP("input context", xhci_slot_get_icv(sc, xs, 0), 2807 sc->sc_ctxsz * 4); 2808 2809 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2810 trb.trb_2 = 0; 2811 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2812 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2813 2814 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2815 return err; 2816 } 2817 2818 static void 2819 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2820 { 2821 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2822 2823 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2824 DPRINTFN(4, "dcbaa %#jx dc %016jx slot %jd", 2825 (uintptr_t)&dcbaa[si], dcba, si, 0); 2826 2827 dcbaa[si] = htole64(dcba); 2828 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2829 BUS_DMASYNC_PREWRITE); 2830 } 2831 2832 /* 2833 * Allocate device and input context DMA buffer, and 2834 * TRB DMA buffer for each endpoint. 2835 */ 2836 static usbd_status 2837 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2838 { 2839 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2840 struct xhci_slot *xs; 2841 usbd_status err; 2842 u_int dci; 2843 2844 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2845 DPRINTFN(4, "slot %ju", slot, 0, 0, 0); 2846 2847 xs = &sc->sc_slots[slot]; 2848 2849 /* allocate contexts */ 2850 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2851 &xs->xs_dc_dma); 2852 if (err) 2853 return err; 2854 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2855 2856 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2857 &xs->xs_ic_dma); 2858 if (err) 2859 goto bad1; 2860 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2861 2862 for (dci = 0; dci < 32; dci++) { 2863 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2864 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2865 if (dci == XHCI_DCI_SLOT) 2866 continue; 2867 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2868 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2869 if (err) { 2870 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2871 goto bad2; 2872 } 2873 } 2874 2875 bad2: 2876 if (err == USBD_NORMAL_COMPLETION) { 2877 xs->xs_idx = slot; 2878 } else { 2879 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2880 } 2881 2882 return err; 2883 2884 bad1: 2885 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2886 xs->xs_idx = 0; 2887 return err; 2888 } 2889 2890 static void 2891 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2892 int end_dci) 2893 { 2894 u_int dci; 2895 2896 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2897 DPRINTFN(4, "slot %ju start %ju end %ju", xs->xs_idx, start_dci, 2898 end_dci, 0); 2899 2900 for (dci = start_dci; dci < end_dci; dci++) { 2901 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2902 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2903 } 2904 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2905 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2906 xs->xs_idx = 0; 2907 } 2908 2909 /* 2910 * Setup slot context, set Device Context Base Address, and issue 2911 * Set Address Device command. 2912 */ 2913 static usbd_status 2914 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 2915 { 2916 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2917 struct xhci_slot *xs; 2918 usbd_status err; 2919 2920 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2921 DPRINTFN(4, "slot %ju bsr %ju", slot, bsr, 0, 0); 2922 2923 xs = &sc->sc_slots[slot]; 2924 2925 xhci_setup_ctx(dev->ud_pipe0); 2926 2927 HEXDUMP("input context", xhci_slot_get_icv(sc, xs, 0), 2928 sc->sc_ctxsz * 3); 2929 2930 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2931 2932 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 2933 2934 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2935 HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, 0), 2936 sc->sc_ctxsz * 2); 2937 2938 return err; 2939 } 2940 2941 /* 2942 * 4.8.2, 6.2.3.2 2943 * construct slot/endpoint context parameters and do syncmem 2944 */ 2945 static void 2946 xhci_setup_ctx(struct usbd_pipe *pipe) 2947 { 2948 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2949 struct usbd_device *dev = pipe->up_dev; 2950 struct xhci_slot * const xs = dev->ud_hcpriv; 2951 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2952 const u_int dci = xhci_ep_get_dci(ed); 2953 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2954 uint32_t *cp; 2955 uint16_t mps = UGETW(ed->wMaxPacketSize); 2956 uint8_t speed = dev->ud_speed; 2957 uint8_t ival = ed->bInterval; 2958 2959 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2960 DPRINTFN(4, "pipe %#jx: slot %ju dci %ju speed %ju", 2961 (uintptr_t)pipe, xs->xs_idx, dci, speed); 2962 2963 /* set up initial input control context */ 2964 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2965 cp[0] = htole32(0); 2966 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 2967 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2968 cp[7] = htole32(0); 2969 2970 /* set up input slot context */ 2971 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2972 cp[0] = 2973 XHCI_SCTX_0_CTX_NUM_SET(dci) | 2974 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 2975 cp[1] = 0; 2976 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2977 cp[3] = 0; 2978 xhci_setup_route(pipe, cp); 2979 xhci_setup_tthub(pipe, cp); 2980 2981 cp[0] = htole32(cp[0]); 2982 cp[1] = htole32(cp[1]); 2983 cp[2] = htole32(cp[2]); 2984 cp[3] = htole32(cp[3]); 2985 2986 /* set up input endpoint context */ 2987 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 2988 cp[0] = 2989 XHCI_EPCTX_0_EPSTATE_SET(0) | 2990 XHCI_EPCTX_0_MULT_SET(0) | 2991 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2992 XHCI_EPCTX_0_LSA_SET(0) | 2993 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 2994 cp[1] = 2995 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 2996 XHCI_EPCTX_1_HID_SET(0) | 2997 XHCI_EPCTX_1_MAXB_SET(0); 2998 2999 if (xfertype != UE_ISOCHRONOUS) 3000 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 3001 3002 if (xfertype == UE_CONTROL) 3003 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 3004 else if (USB_IS_SS(speed)) 3005 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 3006 else 3007 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 3008 3009 xhci_setup_maxburst(pipe, cp); 3010 3011 switch (xfertype) { 3012 case UE_CONTROL: 3013 break; 3014 case UE_BULK: 3015 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 3016 break; 3017 case UE_INTERRUPT: 3018 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3019 ival = pipe->up_interval; 3020 3021 ival = xhci_bival2ival(ival, speed); 3022 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3023 break; 3024 case UE_ISOCHRONOUS: 3025 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3026 ival = pipe->up_interval; 3027 3028 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 3029 if (speed == USB_SPEED_FULL) 3030 ival += 3; /* 1ms -> 125us */ 3031 ival--; 3032 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3033 break; 3034 default: 3035 break; 3036 } 3037 DPRINTFN(4, "setting ival %ju MaxBurst %#jx", 3038 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 3039 3040 /* rewind TR dequeue pointer in xHC */ 3041 /* can't use xhci_ep_get_dci() yet? */ 3042 *(uint64_t *)(&cp[2]) = htole64( 3043 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 3044 XHCI_EPCTX_2_DCS_SET(1)); 3045 3046 cp[0] = htole32(cp[0]); 3047 cp[1] = htole32(cp[1]); 3048 cp[4] = htole32(cp[4]); 3049 3050 /* rewind TR dequeue pointer in driver */ 3051 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 3052 mutex_enter(&xr->xr_lock); 3053 xhci_host_dequeue(xr); 3054 mutex_exit(&xr->xr_lock); 3055 3056 /* sync input contexts before they are read from memory */ 3057 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3058 } 3059 3060 /* 3061 * Setup route string and roothub port of given device for slot context 3062 */ 3063 static void 3064 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 3065 { 3066 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3067 struct usbd_device *dev = pipe->up_dev; 3068 struct usbd_port *up = dev->ud_powersrc; 3069 struct usbd_device *hub; 3070 struct usbd_device *adev; 3071 uint8_t rhport = 0; 3072 uint32_t route = 0; 3073 3074 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3075 3076 /* Locate root hub port and Determine route string */ 3077 /* 4.3.3 route string does not include roothub port */ 3078 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 3079 uint32_t dep; 3080 3081 DPRINTFN(4, "hub %#jx depth %jd upport %jp upportno %jd", 3082 (uintptr_t)hub, hub->ud_depth, (uintptr_t)hub->ud_powersrc, 3083 hub->ud_powersrc ? (uintptr_t)hub->ud_powersrc->up_portno : 3084 -1); 3085 3086 if (hub->ud_powersrc == NULL) 3087 break; 3088 dep = hub->ud_depth; 3089 if (dep == 0) 3090 break; 3091 rhport = hub->ud_powersrc->up_portno; 3092 if (dep > USB_HUB_MAX_DEPTH) 3093 continue; 3094 3095 route |= 3096 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 3097 << ((dep - 1) * 4); 3098 } 3099 route = route >> 4; 3100 size_t bn = hub == sc->sc_bus.ub_roothub ? 0 : 1; 3101 3102 /* Locate port on upstream high speed hub */ 3103 for (adev = dev, hub = up->up_parent; 3104 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 3105 adev = hub, hub = hub->ud_myhub) 3106 ; 3107 if (hub) { 3108 int p; 3109 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 3110 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 3111 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 3112 goto found; 3113 } 3114 } 3115 panic("%s: cannot find HS port", __func__); 3116 found: 3117 DPRINTFN(4, "high speed port %jd", p, 0, 0, 0); 3118 } else { 3119 dev->ud_myhsport = NULL; 3120 } 3121 3122 const size_t ctlrport = xhci_rhport2ctlrport(sc, bn, rhport); 3123 3124 DPRINTFN(4, "rhport %ju ctlrport %ju Route %05jx hub %#jx", rhport, 3125 ctlrport, route, (uintptr_t)hub); 3126 3127 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 3128 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(ctlrport); 3129 } 3130 3131 /* 3132 * Setup whether device is hub, whether device uses MTT, and 3133 * TT informations if it uses MTT. 3134 */ 3135 static void 3136 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 3137 { 3138 struct usbd_device *dev = pipe->up_dev; 3139 struct usbd_port *myhsport = dev->ud_myhsport; 3140 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 3141 uint32_t speed = dev->ud_speed; 3142 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 3143 uint8_t tthubslot, ttportnum; 3144 bool ishub; 3145 bool usemtt; 3146 3147 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3148 3149 /* 3150 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 3151 * tthubslot: 3152 * This is the slot ID of parent HS hub 3153 * if LS/FS device is connected && connected through HS hub. 3154 * This is 0 if device is not LS/FS device || 3155 * parent hub is not HS hub || 3156 * attached to root hub. 3157 * ttportnum: 3158 * This is the downstream facing port of parent HS hub 3159 * if LS/FS device is connected. 3160 * This is 0 if device is not LS/FS device || 3161 * parent hub is not HS hub || 3162 * attached to root hub. 3163 */ 3164 if (myhsport && 3165 myhsport->up_parent->ud_addr != rhaddr && 3166 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 3167 ttportnum = myhsport->up_portno; 3168 tthubslot = myhsport->up_parent->ud_addr; 3169 } else { 3170 ttportnum = 0; 3171 tthubslot = 0; 3172 } 3173 DPRINTFN(4, "myhsport %#jx ttportnum=%jd tthubslot=%jd", 3174 (uintptr_t)myhsport, ttportnum, tthubslot, 0); 3175 3176 /* ishub is valid after reading UDESC_DEVICE */ 3177 ishub = (dd->bDeviceClass == UDCLASS_HUB); 3178 3179 /* dev->ud_hub is valid after reading UDESC_HUB */ 3180 if (ishub && dev->ud_hub) { 3181 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 3182 uint8_t ttt = 3183 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 3184 3185 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 3186 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 3187 DPRINTFN(4, "nports=%jd ttt=%jd", hd->bNbrPorts, ttt, 0, 0); 3188 } 3189 3190 #define IS_MTTHUB(dd) \ 3191 ((dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 3192 3193 /* 3194 * MTT flag is set if 3195 * 1. this is HS hub && MTTs are supported and enabled; or 3196 * 2. this is LS or FS device && there is a parent HS hub where MTTs 3197 * are supported and enabled. 3198 * 3199 * XXX enabled is not tested yet 3200 */ 3201 if (ishub && speed == USB_SPEED_HIGH && IS_MTTHUB(dd)) 3202 usemtt = true; 3203 else if ((speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 3204 myhsport && 3205 myhsport->up_parent->ud_addr != rhaddr && 3206 IS_MTTHUB(&myhsport->up_parent->ud_ddesc)) 3207 usemtt = true; 3208 else 3209 usemtt = false; 3210 DPRINTFN(4, "class %ju proto %ju ishub %jd usemtt %jd", 3211 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 3212 3213 #undef IS_MTTHUB 3214 3215 cp[0] |= 3216 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 3217 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 3218 cp[2] |= 3219 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 3220 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 3221 } 3222 3223 /* set up params for periodic endpoint */ 3224 static void 3225 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 3226 { 3227 struct usbd_device *dev = pipe->up_dev; 3228 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3229 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3230 usbd_desc_iter_t iter; 3231 const usb_cdc_descriptor_t *cdcd; 3232 uint32_t maxb = 0; 3233 uint16_t mps = UGETW(ed->wMaxPacketSize); 3234 uint8_t speed = dev->ud_speed; 3235 uint8_t ep; 3236 3237 /* config desc is NULL when opening ep0 */ 3238 if (dev == NULL || dev->ud_cdesc == NULL) 3239 goto no_cdcd; 3240 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 3241 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 3242 if (cdcd == NULL) 3243 goto no_cdcd; 3244 usb_desc_iter_init(dev, &iter); 3245 iter.cur = (const void *)cdcd; 3246 3247 /* find endpoint_ss_comp desc for ep of this pipe */ 3248 for (ep = 0;;) { 3249 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 3250 if (cdcd == NULL) 3251 break; 3252 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 3253 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 3254 bEndpointAddress; 3255 if (UE_GET_ADDR(ep) == 3256 UE_GET_ADDR(ed->bEndpointAddress)) { 3257 cdcd = (const usb_cdc_descriptor_t *) 3258 usb_desc_iter_next(&iter); 3259 break; 3260 } 3261 ep = 0; 3262 } 3263 } 3264 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 3265 const usb_endpoint_ss_comp_descriptor_t * esscd = 3266 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3267 maxb = esscd->bMaxBurst; 3268 } 3269 3270 no_cdcd: 3271 /* 6.2.3.4, 4.8.2.4 */ 3272 if (USB_IS_SS(speed)) { 3273 /* USB 3.1 9.6.6 */ 3274 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3275 /* USB 3.1 9.6.7 */ 3276 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3277 #ifdef notyet 3278 if (xfertype == UE_ISOCHRONOUS) { 3279 } 3280 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3281 /* use ESIT */ 3282 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3283 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3284 3285 /* XXX if LEC = 1, set ESIT instead */ 3286 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3287 } else { 3288 /* use ival */ 3289 } 3290 #endif 3291 } else { 3292 /* USB 2.0 9.6.6 */ 3293 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3294 3295 /* 6.2.3.4 */ 3296 if (speed == USB_SPEED_HIGH && 3297 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3298 maxb = UE_GET_TRANS(mps); 3299 } else { 3300 /* LS/FS or HS CTRL or HS BULK */ 3301 maxb = 0; 3302 } 3303 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3304 } 3305 } 3306 3307 /* 3308 * Convert endpoint bInterval value to endpoint context interval value 3309 * for Interrupt pipe. 3310 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3311 */ 3312 static uint32_t 3313 xhci_bival2ival(uint32_t ival, uint32_t speed) 3314 { 3315 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3316 int i; 3317 3318 /* 3319 * round ival down to "the nearest base 2 multiple of 3320 * bInterval * 8". 3321 * bInterval is at most 255 as its type is uByte. 3322 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3323 */ 3324 for (i = 10; i > 0; i--) { 3325 if ((ival * 8) >= (1 << i)) 3326 break; 3327 } 3328 ival = i; 3329 } else { 3330 /* Interval = bInterval-1 for SS/HS */ 3331 ival--; 3332 } 3333 3334 return ival; 3335 } 3336 3337 /* ----- */ 3338 3339 static void 3340 xhci_noop(struct usbd_pipe *pipe) 3341 { 3342 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3343 } 3344 3345 /* 3346 * Process root hub request. 3347 */ 3348 static int 3349 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3350 void *buf, int buflen) 3351 { 3352 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3353 usb_port_status_t ps; 3354 int l, totlen = 0; 3355 uint16_t len, value, index; 3356 int port, i; 3357 uint32_t v; 3358 3359 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3360 3361 if (sc->sc_dying) 3362 return -1; 3363 3364 size_t bn = bus == &sc->sc_bus ? 0 : 1; 3365 3366 len = UGETW(req->wLength); 3367 value = UGETW(req->wValue); 3368 index = UGETW(req->wIndex); 3369 3370 DPRINTFN(12, "rhreq: %04jx %04jx %04jx %04jx", 3371 req->bmRequestType | (req->bRequest << 8), value, index, len); 3372 3373 #define C(x,y) ((x) | ((y) << 8)) 3374 switch (C(req->bRequest, req->bmRequestType)) { 3375 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3376 DPRINTFN(8, "getdesc: wValue=0x%04jx", value, 0, 0, 0); 3377 if (len == 0) 3378 break; 3379 switch (value) { 3380 case C(0, UDESC_DEVICE): { 3381 usb_device_descriptor_t devd; 3382 totlen = min(buflen, sizeof(devd)); 3383 memcpy(&devd, buf, totlen); 3384 USETW(devd.idVendor, sc->sc_id_vendor); 3385 memcpy(buf, &devd, totlen); 3386 break; 3387 } 3388 #define sd ((usb_string_descriptor_t *)buf) 3389 case C(1, UDESC_STRING): 3390 /* Vendor */ 3391 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 3392 break; 3393 case C(2, UDESC_STRING): 3394 /* Product */ 3395 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3396 break; 3397 #undef sd 3398 default: 3399 /* default from usbroothub */ 3400 return buflen; 3401 } 3402 break; 3403 3404 /* Hub requests */ 3405 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3406 break; 3407 /* Clear Port Feature request */ 3408 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): { 3409 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3410 3411 DPRINTFN(4, "UR_CLEAR_PORT_FEAT bp=%jd feat=%jd bus=%jd cp=%jd", 3412 index, value, bn, cp); 3413 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3414 return -1; 3415 } 3416 port = XHCI_PORTSC(cp); 3417 v = xhci_op_read_4(sc, port); 3418 DPRINTFN(4, "portsc=0x%08jx", v, 0, 0, 0); 3419 v &= ~XHCI_PS_CLEAR; 3420 switch (value) { 3421 case UHF_PORT_ENABLE: 3422 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3423 break; 3424 case UHF_PORT_SUSPEND: 3425 return -1; 3426 case UHF_PORT_POWER: 3427 break; 3428 case UHF_PORT_TEST: 3429 case UHF_PORT_INDICATOR: 3430 return -1; 3431 case UHF_C_PORT_CONNECTION: 3432 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3433 break; 3434 case UHF_C_PORT_ENABLE: 3435 case UHF_C_PORT_SUSPEND: 3436 case UHF_C_PORT_OVER_CURRENT: 3437 return -1; 3438 case UHF_C_BH_PORT_RESET: 3439 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3440 break; 3441 case UHF_C_PORT_RESET: 3442 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3443 break; 3444 case UHF_C_PORT_LINK_STATE: 3445 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3446 break; 3447 case UHF_C_PORT_CONFIG_ERROR: 3448 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3449 break; 3450 default: 3451 return -1; 3452 } 3453 break; 3454 } 3455 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3456 if (len == 0) 3457 break; 3458 if ((value & 0xff) != 0) { 3459 return -1; 3460 } 3461 usb_hub_descriptor_t hubd; 3462 3463 totlen = min(buflen, sizeof(hubd)); 3464 memcpy(&hubd, buf, totlen); 3465 hubd.bNbrPorts = sc->sc_rhportcount[bn]; 3466 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3467 hubd.bPwrOn2PwrGood = 200; 3468 for (i = 0, l = sc->sc_rhportcount[bn]; l > 0; i++, l -= 8) { 3469 /* XXX can't find out? */ 3470 hubd.DeviceRemovable[i++] = 0; 3471 } 3472 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3473 totlen = min(totlen, hubd.bDescLength); 3474 memcpy(buf, &hubd, totlen); 3475 break; 3476 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3477 if (len != 4) { 3478 return -1; 3479 } 3480 memset(buf, 0, len); /* ? XXX */ 3481 totlen = len; 3482 break; 3483 /* Get Port Status request */ 3484 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): { 3485 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3486 3487 DPRINTFN(8, "get port status bn=%jd i=%jd cp=%ju", 3488 bn, index, cp, 0); 3489 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3490 return -1; 3491 } 3492 if (len != 4) { 3493 return -1; 3494 } 3495 v = xhci_op_read_4(sc, XHCI_PORTSC(cp)); 3496 DPRINTFN(4, "getrhportsc %jd %08jx", cp, v, 0, 0); 3497 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3498 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3499 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3500 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3501 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3502 if (v & XHCI_PS_PR) i |= UPS_RESET; 3503 if (v & XHCI_PS_PP) { 3504 if (i & UPS_OTHER_SPEED) 3505 i |= UPS_PORT_POWER_SS; 3506 else 3507 i |= UPS_PORT_POWER; 3508 } 3509 if (i & UPS_OTHER_SPEED) 3510 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3511 if (sc->sc_vendor_port_status) 3512 i = sc->sc_vendor_port_status(sc, v, i); 3513 USETW(ps.wPortStatus, i); 3514 i = 0; 3515 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3516 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3517 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3518 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3519 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3520 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3521 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3522 USETW(ps.wPortChange, i); 3523 totlen = min(len, sizeof(ps)); 3524 memcpy(buf, &ps, totlen); 3525 break; 3526 } 3527 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3528 return -1; 3529 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3530 break; 3531 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3532 break; 3533 /* Set Port Feature request */ 3534 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3535 int optval = (index >> 8) & 0xff; 3536 index &= 0xff; 3537 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3538 return -1; 3539 } 3540 3541 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3542 3543 port = XHCI_PORTSC(cp); 3544 v = xhci_op_read_4(sc, port); 3545 DPRINTFN(4, "index %jd cp %jd portsc=0x%08jx", index, cp, v, 0); 3546 v &= ~XHCI_PS_CLEAR; 3547 switch (value) { 3548 case UHF_PORT_ENABLE: 3549 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3550 break; 3551 case UHF_PORT_SUSPEND: 3552 /* XXX suspend */ 3553 break; 3554 case UHF_PORT_RESET: 3555 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3556 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3557 /* Wait for reset to complete. */ 3558 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3559 if (sc->sc_dying) { 3560 return -1; 3561 } 3562 v = xhci_op_read_4(sc, port); 3563 if (v & XHCI_PS_PR) { 3564 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3565 usb_delay_ms(&sc->sc_bus, 10); 3566 /* XXX */ 3567 } 3568 break; 3569 case UHF_PORT_POWER: 3570 /* XXX power control */ 3571 break; 3572 /* XXX more */ 3573 case UHF_C_PORT_RESET: 3574 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3575 break; 3576 case UHF_PORT_U1_TIMEOUT: 3577 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3578 return -1; 3579 } 3580 port = XHCI_PORTPMSC(cp); 3581 v = xhci_op_read_4(sc, port); 3582 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 3583 index, cp, v, 0); 3584 v &= ~XHCI_PM3_U1TO_SET(0xff); 3585 v |= XHCI_PM3_U1TO_SET(optval); 3586 xhci_op_write_4(sc, port, v); 3587 break; 3588 case UHF_PORT_U2_TIMEOUT: 3589 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3590 return -1; 3591 } 3592 port = XHCI_PORTPMSC(cp); 3593 v = xhci_op_read_4(sc, port); 3594 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 3595 index, cp, v, 0); 3596 v &= ~XHCI_PM3_U2TO_SET(0xff); 3597 v |= XHCI_PM3_U2TO_SET(optval); 3598 xhci_op_write_4(sc, port, v); 3599 break; 3600 default: 3601 return -1; 3602 } 3603 } 3604 break; 3605 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3606 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3607 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3608 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3609 break; 3610 default: 3611 /* default from usbroothub */ 3612 return buflen; 3613 } 3614 3615 return totlen; 3616 } 3617 3618 /* root hub interrupt */ 3619 3620 static usbd_status 3621 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3622 { 3623 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3624 usbd_status err; 3625 3626 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3627 3628 /* Insert last in queue. */ 3629 mutex_enter(&sc->sc_lock); 3630 err = usb_insert_transfer(xfer); 3631 mutex_exit(&sc->sc_lock); 3632 if (err) 3633 return err; 3634 3635 /* Pipe isn't running, start first */ 3636 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3637 } 3638 3639 /* Wait for roothub port status/change */ 3640 static usbd_status 3641 xhci_root_intr_start(struct usbd_xfer *xfer) 3642 { 3643 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3644 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3645 3646 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3647 3648 if (sc->sc_dying) 3649 return USBD_IOERROR; 3650 3651 mutex_enter(&sc->sc_lock); 3652 sc->sc_intrxfer[bn] = xfer; 3653 mutex_exit(&sc->sc_lock); 3654 3655 return USBD_IN_PROGRESS; 3656 } 3657 3658 static void 3659 xhci_root_intr_abort(struct usbd_xfer *xfer) 3660 { 3661 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3662 3663 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3664 3665 KASSERT(mutex_owned(&sc->sc_lock)); 3666 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3667 3668 xfer->ux_status = USBD_CANCELLED; 3669 usb_transfer_complete(xfer); 3670 } 3671 3672 static void 3673 xhci_root_intr_close(struct usbd_pipe *pipe) 3674 { 3675 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3676 const struct usbd_xfer *xfer = pipe->up_intrxfer; 3677 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3678 3679 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3680 3681 KASSERT(mutex_owned(&sc->sc_lock)); 3682 3683 sc->sc_intrxfer[bn] = NULL; 3684 } 3685 3686 static void 3687 xhci_root_intr_done(struct usbd_xfer *xfer) 3688 { 3689 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3690 3691 } 3692 3693 /* -------------- */ 3694 /* device control */ 3695 3696 static usbd_status 3697 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3698 { 3699 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3700 usbd_status err; 3701 3702 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3703 3704 /* Insert last in queue. */ 3705 mutex_enter(&sc->sc_lock); 3706 err = usb_insert_transfer(xfer); 3707 mutex_exit(&sc->sc_lock); 3708 if (err) 3709 return err; 3710 3711 /* Pipe isn't running, start first */ 3712 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3713 } 3714 3715 static usbd_status 3716 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3717 { 3718 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3719 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3720 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3721 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3722 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3723 usb_device_request_t * const req = &xfer->ux_request; 3724 const int isread = usbd_xfer_isread(xfer); 3725 const uint32_t len = UGETW(req->wLength); 3726 usb_dma_t * const dma = &xfer->ux_dmabuf; 3727 uint64_t parameter; 3728 uint32_t status; 3729 uint32_t control; 3730 u_int i; 3731 3732 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3733 DPRINTFN(12, "req: %04jx %04jx %04jx %04jx", 3734 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3735 UGETW(req->wIndex), UGETW(req->wLength)); 3736 3737 /* we rely on the bottom bits for extra info */ 3738 KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx", 3739 (uintptr_t) xfer); 3740 3741 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3742 3743 i = 0; 3744 3745 /* setup phase */ 3746 memcpy(¶meter, req, sizeof(parameter)); 3747 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3748 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3749 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3750 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3751 XHCI_TRB_3_IDT_BIT; 3752 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3753 3754 if (len != 0) { 3755 /* data phase */ 3756 parameter = DMAADDR(dma, 0); 3757 KASSERTMSG(len <= 0x10000, "len %d", len); 3758 status = XHCI_TRB_2_IRQ_SET(0) | 3759 XHCI_TRB_2_TDSZ_SET(1) | 3760 XHCI_TRB_2_BYTES_SET(len); 3761 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3762 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3763 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3764 XHCI_TRB_3_IOC_BIT; 3765 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3766 } 3767 3768 parameter = 0; 3769 status = XHCI_TRB_2_IRQ_SET(0); 3770 /* the status stage has inverted direction */ 3771 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3772 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3773 XHCI_TRB_3_IOC_BIT; 3774 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3775 3776 mutex_enter(&tr->xr_lock); 3777 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3778 mutex_exit(&tr->xr_lock); 3779 3780 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3781 3782 if (xfer->ux_timeout && !xhci_polling_p(sc)) { 3783 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3784 xhci_timeout, xfer); 3785 } 3786 3787 return USBD_IN_PROGRESS; 3788 } 3789 3790 static void 3791 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3792 { 3793 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3794 usb_device_request_t *req = &xfer->ux_request; 3795 int len = UGETW(req->wLength); 3796 int rd = req->bmRequestType & UT_READ; 3797 3798 if (len) 3799 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3800 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3801 } 3802 3803 static void 3804 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3805 { 3806 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3807 3808 xhci_abort_xfer(xfer, USBD_CANCELLED); 3809 } 3810 3811 static void 3812 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3813 { 3814 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3815 3816 xhci_close_pipe(pipe); 3817 } 3818 3819 /* ------------------ */ 3820 /* device isochronous */ 3821 3822 /* ----------- */ 3823 /* device bulk */ 3824 3825 static usbd_status 3826 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3827 { 3828 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3829 usbd_status err; 3830 3831 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3832 3833 /* Insert last in queue. */ 3834 mutex_enter(&sc->sc_lock); 3835 err = usb_insert_transfer(xfer); 3836 mutex_exit(&sc->sc_lock); 3837 if (err) 3838 return err; 3839 3840 /* 3841 * Pipe isn't running (otherwise err would be USBD_INPROG), 3842 * so start it first. 3843 */ 3844 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3845 } 3846 3847 static usbd_status 3848 xhci_device_bulk_start(struct usbd_xfer *xfer) 3849 { 3850 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3851 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3852 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3853 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3854 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3855 const uint32_t len = xfer->ux_length; 3856 usb_dma_t * const dma = &xfer->ux_dmabuf; 3857 uint64_t parameter; 3858 uint32_t status; 3859 uint32_t control; 3860 u_int i = 0; 3861 3862 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3863 3864 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 3865 0); 3866 3867 if (sc->sc_dying) 3868 return USBD_IOERROR; 3869 3870 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3871 3872 parameter = DMAADDR(dma, 0); 3873 /* 3874 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3875 * If the user supplied buffer crosses such a boundary then 2 3876 * (or more) TRB should be used. 3877 * If multiple TRB are used the td_size field must be set correctly. 3878 * For v1.0 devices (like ivy bridge) this is the number of usb data 3879 * blocks needed to complete the transfer. 3880 * Setting it to 1 in the last TRB causes an extra zero-length 3881 * data block be sent. 3882 * The earlier documentation differs, I don't know how it behaves. 3883 */ 3884 KASSERTMSG(len <= 0x10000, "len %d", len); 3885 status = XHCI_TRB_2_IRQ_SET(0) | 3886 XHCI_TRB_2_TDSZ_SET(1) | 3887 XHCI_TRB_2_BYTES_SET(len); 3888 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3889 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3890 XHCI_TRB_3_IOC_BIT; 3891 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3892 3893 mutex_enter(&tr->xr_lock); 3894 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3895 mutex_exit(&tr->xr_lock); 3896 3897 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3898 3899 if (xfer->ux_timeout && !xhci_polling_p(sc)) { 3900 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3901 xhci_timeout, xfer); 3902 } 3903 3904 return USBD_IN_PROGRESS; 3905 } 3906 3907 static void 3908 xhci_device_bulk_done(struct usbd_xfer *xfer) 3909 { 3910 #ifdef USB_DEBUG 3911 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3912 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3913 #endif 3914 const int isread = usbd_xfer_isread(xfer); 3915 3916 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3917 3918 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 3919 0); 3920 3921 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3922 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3923 } 3924 3925 static void 3926 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3927 { 3928 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3929 3930 xhci_abort_xfer(xfer, USBD_CANCELLED); 3931 } 3932 3933 static void 3934 xhci_device_bulk_close(struct usbd_pipe *pipe) 3935 { 3936 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3937 3938 xhci_close_pipe(pipe); 3939 } 3940 3941 /* ---------------- */ 3942 /* device interrupt */ 3943 3944 static usbd_status 3945 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3946 { 3947 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3948 usbd_status err; 3949 3950 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3951 3952 /* Insert last in queue. */ 3953 mutex_enter(&sc->sc_lock); 3954 err = usb_insert_transfer(xfer); 3955 mutex_exit(&sc->sc_lock); 3956 if (err) 3957 return err; 3958 3959 /* 3960 * Pipe isn't running (otherwise err would be USBD_INPROG), 3961 * so start it first. 3962 */ 3963 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3964 } 3965 3966 static usbd_status 3967 xhci_device_intr_start(struct usbd_xfer *xfer) 3968 { 3969 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3970 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3971 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3972 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3973 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3974 const uint32_t len = xfer->ux_length; 3975 usb_dma_t * const dma = &xfer->ux_dmabuf; 3976 uint64_t parameter; 3977 uint32_t status; 3978 uint32_t control; 3979 u_int i = 0; 3980 3981 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3982 3983 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 3984 0); 3985 3986 if (sc->sc_dying) 3987 return USBD_IOERROR; 3988 3989 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3990 3991 parameter = DMAADDR(dma, 0); 3992 KASSERTMSG(len <= 0x10000, "len %d", len); 3993 status = XHCI_TRB_2_IRQ_SET(0) | 3994 XHCI_TRB_2_TDSZ_SET(1) | 3995 XHCI_TRB_2_BYTES_SET(len); 3996 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3997 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3998 XHCI_TRB_3_IOC_BIT; 3999 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 4000 4001 mutex_enter(&tr->xr_lock); 4002 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 4003 mutex_exit(&tr->xr_lock); 4004 4005 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 4006 4007 if (xfer->ux_timeout && !xhci_polling_p(sc)) { 4008 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4009 xhci_timeout, xfer); 4010 } 4011 4012 return USBD_IN_PROGRESS; 4013 } 4014 4015 static void 4016 xhci_device_intr_done(struct usbd_xfer *xfer) 4017 { 4018 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4019 #ifdef USB_DEBUG 4020 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4021 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4022 #endif 4023 const int isread = usbd_xfer_isread(xfer); 4024 4025 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4026 4027 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 4028 0); 4029 4030 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 4031 4032 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4033 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4034 } 4035 4036 static void 4037 xhci_device_intr_abort(struct usbd_xfer *xfer) 4038 { 4039 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4040 4041 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4042 4043 KASSERT(mutex_owned(&sc->sc_lock)); 4044 DPRINTFN(15, "%#jx", (uintptr_t)xfer, 0, 0, 0); 4045 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4046 xhci_abort_xfer(xfer, USBD_CANCELLED); 4047 } 4048 4049 static void 4050 xhci_device_intr_close(struct usbd_pipe *pipe) 4051 { 4052 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 4053 4054 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4055 DPRINTFN(15, "%#jx", (uintptr_t)pipe, 0, 0, 0); 4056 4057 xhci_close_pipe(pipe); 4058 } 4059 4060 /* ------------ */ 4061 4062 static void 4063 xhci_timeout(void *addr) 4064 { 4065 struct xhci_xfer * const xx = addr; 4066 struct usbd_xfer * const xfer = &xx->xx_xfer; 4067 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4068 4069 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4070 4071 if (sc->sc_dying) { 4072 return; 4073 } 4074 4075 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 4076 USB_TASKQ_MPSAFE); 4077 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 4078 USB_TASKQ_HC); 4079 } 4080 4081 static void 4082 xhci_timeout_task(void *addr) 4083 { 4084 struct usbd_xfer * const xfer = addr; 4085 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4086 4087 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4088 4089 mutex_enter(&sc->sc_lock); 4090 xhci_abort_xfer(xfer, USBD_TIMEOUT); 4091 mutex_exit(&sc->sc_lock); 4092 } 4093
Indexes created Wed Sep 24 05:09:52 GMT 2025