xhci.c revision 1.86.2.2
1 /* $NetBSD: xhci.c,v 1.86.2.2 2018/04/22 07:20:26 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * USB rev 2.0 and rev 3.1 specification 31 * http://www.usb.org/developers/docs/ 32 * xHCI rev 1.1 specification 33 * http://www.intel.com/technology/usb/spec.htm 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: xhci.c,v 1.86.2.2 2018/04/22 07:20:26 pgoyette Exp $"); 38 39 #ifdef _KERNEL_OPT 40 #include "opt_usb.h" 41 #endif 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/kmem.h> 47 #include <sys/device.h> 48 #include <sys/select.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 #include <sys/bus.h> 54 #include <sys/cpu.h> 55 #include <sys/sysctl.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usbdi_util.h> 63 #include <dev/usb/usbhist.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/xhcireg.h> 68 #include <dev/usb/xhcivar.h> 69 #include <dev/usb/usbroothub.h> 70 71 72 #ifdef USB_DEBUG 73 #ifndef XHCI_DEBUG 74 #define xhcidebug 0 75 #else /* !XHCI_DEBUG */ 76 #define HEXDUMP(a, b, c) \ 77 do { \ 78 if (xhcidebug > 0) \ 79 hexdump(printf, a, b, c); \ 80 } while (/*CONSTCOND*/0) 81 static int xhcidebug = 0; 82 83 SYSCTL_SETUP(sysctl_hw_xhci_setup, "sysctl hw.xhci setup") 84 { 85 int err; 86 const struct sysctlnode *rnode; 87 const struct sysctlnode *cnode; 88 89 err = sysctl_createv(clog, 0, NULL, &rnode, 90 CTLFLAG_PERMANENT, CTLTYPE_NODE, "xhci", 91 SYSCTL_DESCR("xhci global controls"), 92 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 93 94 if (err) 95 goto fail; 96 97 /* control debugging printfs */ 98 err = sysctl_createv(clog, 0, &rnode, &cnode, 99 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 100 "debug", SYSCTL_DESCR("Enable debugging output"), 101 NULL, 0, &xhcidebug, sizeof(xhcidebug), CTL_CREATE, CTL_EOL); 102 if (err) 103 goto fail; 104 105 return; 106 fail: 107 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 108 } 109 110 #endif /* !XHCI_DEBUG */ 111 #endif /* USB_DEBUG */ 112 113 #ifndef HEXDUMP 114 #define HEXDUMP(a, b, c) 115 #endif 116 117 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(xhcidebug,N,FMT,A,B,C,D) 118 #define XHCIHIST_FUNC() USBHIST_FUNC() 119 #define XHCIHIST_CALLED(name) USBHIST_CALLED(xhcidebug) 120 121 #define XHCI_DCI_SLOT 0 122 #define XHCI_DCI_EP_CONTROL 1 123 124 #define XHCI_ICI_INPUT_CONTROL 0 125 126 struct xhci_pipe { 127 struct usbd_pipe xp_pipe; 128 struct usb_task xp_async_task; 129 }; 130 131 #define XHCI_COMMAND_RING_TRBS 256 132 #define XHCI_EVENT_RING_TRBS 256 133 #define XHCI_EVENT_RING_SEGMENTS 1 134 #define XHCI_TRB_3_ED_BIT XHCI_TRB_3_ISP_BIT 135 136 static usbd_status xhci_open(struct usbd_pipe *); 137 static void xhci_close_pipe(struct usbd_pipe *); 138 static int xhci_intr1(struct xhci_softc * const); 139 static void xhci_softintr(void *); 140 static void xhci_poll(struct usbd_bus *); 141 static struct usbd_xfer *xhci_allocx(struct usbd_bus *, unsigned int); 142 static void xhci_freex(struct usbd_bus *, struct usbd_xfer *); 143 static void xhci_get_lock(struct usbd_bus *, kmutex_t **); 144 static usbd_status xhci_new_device(device_t, struct usbd_bus *, int, int, int, 145 struct usbd_port *); 146 static int xhci_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 147 void *, int); 148 149 static usbd_status xhci_configure_endpoint(struct usbd_pipe *); 150 //static usbd_status xhci_unconfigure_endpoint(struct usbd_pipe *); 151 static usbd_status xhci_reset_endpoint(struct usbd_pipe *); 152 static usbd_status xhci_stop_endpoint(struct usbd_pipe *); 153 154 static void xhci_host_dequeue(struct xhci_ring * const); 155 static usbd_status xhci_set_dequeue(struct usbd_pipe *); 156 157 static usbd_status xhci_do_command(struct xhci_softc * const, 158 struct xhci_trb * const, int); 159 static usbd_status xhci_do_command_locked(struct xhci_softc * const, 160 struct xhci_trb * const, int); 161 static usbd_status xhci_init_slot(struct usbd_device *, uint32_t); 162 static void xhci_free_slot(struct xhci_softc *, struct xhci_slot *, int, int); 163 static usbd_status xhci_set_address(struct usbd_device *, uint32_t, bool); 164 static usbd_status xhci_enable_slot(struct xhci_softc * const, 165 uint8_t * const); 166 static usbd_status xhci_disable_slot(struct xhci_softc * const, uint8_t); 167 static usbd_status xhci_address_device(struct xhci_softc * const, 168 uint64_t, uint8_t, bool); 169 static void xhci_set_dcba(struct xhci_softc * const, uint64_t, int); 170 static usbd_status xhci_update_ep0_mps(struct xhci_softc * const, 171 struct xhci_slot * const, u_int); 172 static usbd_status xhci_ring_init(struct xhci_softc * const, 173 struct xhci_ring * const, size_t, size_t); 174 static void xhci_ring_free(struct xhci_softc * const, struct xhci_ring * const); 175 176 static void xhci_setup_ctx(struct usbd_pipe *); 177 static void xhci_setup_route(struct usbd_pipe *, uint32_t *); 178 static void xhci_setup_tthub(struct usbd_pipe *, uint32_t *); 179 static void xhci_setup_maxburst(struct usbd_pipe *, uint32_t *); 180 static uint32_t xhci_bival2ival(uint32_t, uint32_t); 181 182 static void xhci_noop(struct usbd_pipe *); 183 184 static usbd_status xhci_root_intr_transfer(struct usbd_xfer *); 185 static usbd_status xhci_root_intr_start(struct usbd_xfer *); 186 static void xhci_root_intr_abort(struct usbd_xfer *); 187 static void xhci_root_intr_close(struct usbd_pipe *); 188 static void xhci_root_intr_done(struct usbd_xfer *); 189 190 static usbd_status xhci_device_ctrl_transfer(struct usbd_xfer *); 191 static usbd_status xhci_device_ctrl_start(struct usbd_xfer *); 192 static void xhci_device_ctrl_abort(struct usbd_xfer *); 193 static void xhci_device_ctrl_close(struct usbd_pipe *); 194 static void xhci_device_ctrl_done(struct usbd_xfer *); 195 196 static usbd_status xhci_device_intr_transfer(struct usbd_xfer *); 197 static usbd_status xhci_device_intr_start(struct usbd_xfer *); 198 static void xhci_device_intr_abort(struct usbd_xfer *); 199 static void xhci_device_intr_close(struct usbd_pipe *); 200 static void xhci_device_intr_done(struct usbd_xfer *); 201 202 static usbd_status xhci_device_bulk_transfer(struct usbd_xfer *); 203 static usbd_status xhci_device_bulk_start(struct usbd_xfer *); 204 static void xhci_device_bulk_abort(struct usbd_xfer *); 205 static void xhci_device_bulk_close(struct usbd_pipe *); 206 static void xhci_device_bulk_done(struct usbd_xfer *); 207 208 static void xhci_timeout(void *); 209 static void xhci_timeout_task(void *); 210 211 static const struct usbd_bus_methods xhci_bus_methods = { 212 .ubm_open = xhci_open, 213 .ubm_softint = xhci_softintr, 214 .ubm_dopoll = xhci_poll, 215 .ubm_allocx = xhci_allocx, 216 .ubm_freex = xhci_freex, 217 .ubm_getlock = xhci_get_lock, 218 .ubm_newdev = xhci_new_device, 219 .ubm_rhctrl = xhci_roothub_ctrl, 220 }; 221 222 static const struct usbd_pipe_methods xhci_root_intr_methods = { 223 .upm_transfer = xhci_root_intr_transfer, 224 .upm_start = xhci_root_intr_start, 225 .upm_abort = xhci_root_intr_abort, 226 .upm_close = xhci_root_intr_close, 227 .upm_cleartoggle = xhci_noop, 228 .upm_done = xhci_root_intr_done, 229 }; 230 231 232 static const struct usbd_pipe_methods xhci_device_ctrl_methods = { 233 .upm_transfer = xhci_device_ctrl_transfer, 234 .upm_start = xhci_device_ctrl_start, 235 .upm_abort = xhci_device_ctrl_abort, 236 .upm_close = xhci_device_ctrl_close, 237 .upm_cleartoggle = xhci_noop, 238 .upm_done = xhci_device_ctrl_done, 239 }; 240 241 static const struct usbd_pipe_methods xhci_device_isoc_methods = { 242 .upm_cleartoggle = xhci_noop, 243 }; 244 245 static const struct usbd_pipe_methods xhci_device_bulk_methods = { 246 .upm_transfer = xhci_device_bulk_transfer, 247 .upm_start = xhci_device_bulk_start, 248 .upm_abort = xhci_device_bulk_abort, 249 .upm_close = xhci_device_bulk_close, 250 .upm_cleartoggle = xhci_noop, 251 .upm_done = xhci_device_bulk_done, 252 }; 253 254 static const struct usbd_pipe_methods xhci_device_intr_methods = { 255 .upm_transfer = xhci_device_intr_transfer, 256 .upm_start = xhci_device_intr_start, 257 .upm_abort = xhci_device_intr_abort, 258 .upm_close = xhci_device_intr_close, 259 .upm_cleartoggle = xhci_noop, 260 .upm_done = xhci_device_intr_done, 261 }; 262 263 static inline uint32_t 264 xhci_read_1(const struct xhci_softc * const sc, bus_size_t offset) 265 { 266 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 267 } 268 269 static inline uint32_t 270 xhci_read_4(const struct xhci_softc * const sc, bus_size_t offset) 271 { 272 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, offset); 273 } 274 275 static inline void 276 xhci_write_1(const struct xhci_softc * const sc, bus_size_t offset, 277 uint32_t value) 278 { 279 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value); 280 } 281 282 #if 0 /* unused */ 283 static inline void 284 xhci_write_4(const struct xhci_softc * const sc, bus_size_t offset, 285 uint32_t value) 286 { 287 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value); 288 } 289 #endif /* unused */ 290 291 static inline uint32_t 292 xhci_cap_read_4(const struct xhci_softc * const sc, bus_size_t offset) 293 { 294 return bus_space_read_4(sc->sc_iot, sc->sc_cbh, offset); 295 } 296 297 static inline uint32_t 298 xhci_op_read_4(const struct xhci_softc * const sc, bus_size_t offset) 299 { 300 return bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 301 } 302 303 static inline void 304 xhci_op_write_4(const struct xhci_softc * const sc, bus_size_t offset, 305 uint32_t value) 306 { 307 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 308 } 309 310 static inline uint64_t 311 xhci_op_read_8(const struct xhci_softc * const sc, bus_size_t offset) 312 { 313 uint64_t value; 314 315 if (sc->sc_ac64) { 316 #ifdef XHCI_USE_BUS_SPACE_8 317 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset); 318 #else 319 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 320 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh, 321 offset + 4) << 32; 322 #endif 323 } else { 324 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset); 325 } 326 327 return value; 328 } 329 330 static inline void 331 xhci_op_write_8(const struct xhci_softc * const sc, bus_size_t offset, 332 uint64_t value) 333 { 334 if (sc->sc_ac64) { 335 #ifdef XHCI_USE_BUS_SPACE_8 336 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value); 337 #else 338 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 0, 339 (value >> 0) & 0xffffffff); 340 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset + 4, 341 (value >> 32) & 0xffffffff); 342 #endif 343 } else { 344 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value); 345 } 346 } 347 348 static inline uint32_t 349 xhci_rt_read_4(const struct xhci_softc * const sc, bus_size_t offset) 350 { 351 return bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 352 } 353 354 static inline void 355 xhci_rt_write_4(const struct xhci_softc * const sc, bus_size_t offset, 356 uint32_t value) 357 { 358 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 359 } 360 361 #if 0 /* unused */ 362 static inline uint64_t 363 xhci_rt_read_8(const struct xhci_softc * const sc, bus_size_t offset) 364 { 365 uint64_t value; 366 367 if (sc->sc_ac64) { 368 #ifdef XHCI_USE_BUS_SPACE_8 369 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset); 370 #else 371 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 372 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh, 373 offset + 4) << 32; 374 #endif 375 } else { 376 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset); 377 } 378 379 return value; 380 } 381 #endif /* unused */ 382 383 static inline void 384 xhci_rt_write_8(const struct xhci_softc * const sc, bus_size_t offset, 385 uint64_t value) 386 { 387 if (sc->sc_ac64) { 388 #ifdef XHCI_USE_BUS_SPACE_8 389 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value); 390 #else 391 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 0, 392 (value >> 0) & 0xffffffff); 393 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset + 4, 394 (value >> 32) & 0xffffffff); 395 #endif 396 } else { 397 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value); 398 } 399 } 400 401 #if 0 /* unused */ 402 static inline uint32_t 403 xhci_db_read_4(const struct xhci_softc * const sc, bus_size_t offset) 404 { 405 return bus_space_read_4(sc->sc_iot, sc->sc_dbh, offset); 406 } 407 #endif /* unused */ 408 409 static inline void 410 xhci_db_write_4(const struct xhci_softc * const sc, bus_size_t offset, 411 uint32_t value) 412 { 413 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value); 414 } 415 416 /* --- */ 417 418 static inline uint8_t 419 xhci_ep_get_type(usb_endpoint_descriptor_t * const ed) 420 { 421 u_int eptype = 0; 422 423 switch (UE_GET_XFERTYPE(ed->bmAttributes)) { 424 case UE_CONTROL: 425 eptype = 0x0; 426 break; 427 case UE_ISOCHRONOUS: 428 eptype = 0x1; 429 break; 430 case UE_BULK: 431 eptype = 0x2; 432 break; 433 case UE_INTERRUPT: 434 eptype = 0x3; 435 break; 436 } 437 438 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 439 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 440 return eptype | 0x4; 441 else 442 return eptype; 443 } 444 445 static u_int 446 xhci_ep_get_dci(usb_endpoint_descriptor_t * const ed) 447 { 448 /* xHCI 1.0 section 4.5.1 */ 449 u_int epaddr = UE_GET_ADDR(ed->bEndpointAddress); 450 u_int in = 0; 451 452 if ((UE_GET_XFERTYPE(ed->bmAttributes) == UE_CONTROL) || 453 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)) 454 in = 1; 455 456 return epaddr * 2 + in; 457 } 458 459 static inline u_int 460 xhci_dci_to_ici(const u_int i) 461 { 462 return i + 1; 463 } 464 465 static inline void * 466 xhci_slot_get_dcv(struct xhci_softc * const sc, struct xhci_slot * const xs, 467 const u_int dci) 468 { 469 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 470 } 471 472 #if 0 /* unused */ 473 static inline bus_addr_t 474 xhci_slot_get_dcp(struct xhci_softc * const sc, struct xhci_slot * const xs, 475 const u_int dci) 476 { 477 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci); 478 } 479 #endif /* unused */ 480 481 static inline void * 482 xhci_slot_get_icv(struct xhci_softc * const sc, struct xhci_slot * const xs, 483 const u_int ici) 484 { 485 return KERNADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 486 } 487 488 static inline bus_addr_t 489 xhci_slot_get_icp(struct xhci_softc * const sc, struct xhci_slot * const xs, 490 const u_int ici) 491 { 492 return DMAADDR(&xs->xs_ic_dma, sc->sc_ctxsz * ici); 493 } 494 495 static inline struct xhci_trb * 496 xhci_ring_trbv(struct xhci_ring * const xr, u_int idx) 497 { 498 return KERNADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 499 } 500 501 static inline bus_addr_t 502 xhci_ring_trbp(struct xhci_ring * const xr, u_int idx) 503 { 504 return DMAADDR(&xr->xr_dma, XHCI_TRB_SIZE * idx); 505 } 506 507 static inline void 508 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status, 509 uint32_t control) 510 { 511 trb->trb_0 = htole64(parameter); 512 trb->trb_2 = htole32(status); 513 trb->trb_3 = htole32(control); 514 } 515 516 static int 517 xhci_trb_get_idx(struct xhci_ring *xr, uint64_t trb_0, int *idx) 518 { 519 /* base address of TRBs */ 520 bus_addr_t trbp = xhci_ring_trbp(xr, 0); 521 522 /* trb_0 range sanity check */ 523 if (trb_0 == 0 || trb_0 < trbp || 524 (trb_0 - trbp) % sizeof(struct xhci_trb) != 0 || 525 (trb_0 - trbp) / sizeof(struct xhci_trb) >= xr->xr_ntrb) { 526 return 1; 527 } 528 *idx = (trb_0 - trbp) / sizeof(struct xhci_trb); 529 return 0; 530 } 531 532 static unsigned int 533 xhci_get_epstate(struct xhci_softc * const sc, struct xhci_slot * const xs, 534 u_int dci) 535 { 536 uint32_t *cp; 537 538 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 539 cp = xhci_slot_get_dcv(sc, xs, dci); 540 return XHCI_EPCTX_0_EPSTATE_GET(le32toh(cp[0])); 541 } 542 543 static inline unsigned int 544 xhci_ctlrport2bus(struct xhci_softc * const sc, unsigned int ctlrport) 545 { 546 const unsigned int port = ctlrport - 1; 547 const uint8_t bit = __BIT(port % NBBY); 548 549 return __SHIFTOUT(sc->sc_ctlrportbus[port / NBBY], bit); 550 } 551 552 /* 553 * Return the roothub port for a controller port. Both are 1..n. 554 */ 555 static inline unsigned int 556 xhci_ctlrport2rhport(struct xhci_softc * const sc, unsigned int ctrlport) 557 { 558 559 return sc->sc_ctlrportmap[ctrlport - 1]; 560 } 561 562 /* 563 * Return the controller port for a bus roothub port. Both are 1..n. 564 */ 565 static inline unsigned int 566 xhci_rhport2ctlrport(struct xhci_softc * const sc, unsigned int bn, 567 unsigned int rhport) 568 { 569 570 return sc->sc_rhportmap[bn][rhport - 1]; 571 } 572 573 /* --- */ 574 575 void 576 xhci_childdet(device_t self, device_t child) 577 { 578 struct xhci_softc * const sc = device_private(self); 579 580 KASSERT((sc->sc_child == child) || (sc->sc_child2 == child)); 581 if (child == sc->sc_child2) 582 sc->sc_child2 = NULL; 583 else if (child == sc->sc_child) 584 sc->sc_child = NULL; 585 } 586 587 int 588 xhci_detach(struct xhci_softc *sc, int flags) 589 { 590 int rv = 0; 591 592 if (sc->sc_child2 != NULL) { 593 rv = config_detach(sc->sc_child2, flags); 594 if (rv != 0) 595 return rv; 596 KASSERT(sc->sc_child2 == NULL); 597 } 598 599 if (sc->sc_child != NULL) { 600 rv = config_detach(sc->sc_child, flags); 601 if (rv != 0) 602 return rv; 603 KASSERT(sc->sc_child == NULL); 604 } 605 606 /* XXX unconfigure/free slots */ 607 608 /* verify: */ 609 xhci_rt_write_4(sc, XHCI_IMAN(0), 0); 610 xhci_op_write_4(sc, XHCI_USBCMD, 0); 611 /* do we need to wait for stop? */ 612 613 xhci_op_write_8(sc, XHCI_CRCR, 0); 614 xhci_ring_free(sc, &sc->sc_cr); 615 cv_destroy(&sc->sc_command_cv); 616 cv_destroy(&sc->sc_cmdbusy_cv); 617 618 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), 0); 619 xhci_rt_write_8(sc, XHCI_ERSTBA(0), 0); 620 xhci_rt_write_8(sc, XHCI_ERDP(0), 0|XHCI_ERDP_LO_BUSY); 621 xhci_ring_free(sc, &sc->sc_er); 622 623 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 624 625 xhci_op_write_8(sc, XHCI_DCBAAP, 0); 626 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 627 628 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * sc->sc_maxslots); 629 630 kmem_free(sc->sc_ctlrportbus, 631 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY)); 632 kmem_free(sc->sc_ctlrportmap, sc->sc_maxports * sizeof(int)); 633 634 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 635 kmem_free(sc->sc_rhportmap[j], sc->sc_maxports * sizeof(int)); 636 } 637 638 mutex_destroy(&sc->sc_lock); 639 mutex_destroy(&sc->sc_intr_lock); 640 641 pool_cache_destroy(sc->sc_xferpool); 642 643 return rv; 644 } 645 646 int 647 xhci_activate(device_t self, enum devact act) 648 { 649 struct xhci_softc * const sc = device_private(self); 650 651 switch (act) { 652 case DVACT_DEACTIVATE: 653 sc->sc_dying = true; 654 return 0; 655 default: 656 return EOPNOTSUPP; 657 } 658 } 659 660 bool 661 xhci_suspend(device_t dv, const pmf_qual_t *qual) 662 { 663 return false; 664 } 665 666 bool 667 xhci_resume(device_t dv, const pmf_qual_t *qual) 668 { 669 return false; 670 } 671 672 bool 673 xhci_shutdown(device_t self, int flags) 674 { 675 return false; 676 } 677 678 static int 679 xhci_hc_reset(struct xhci_softc * const sc) 680 { 681 uint32_t usbcmd, usbsts; 682 int i; 683 684 /* Check controller not ready */ 685 for (i = 0; i < XHCI_WAIT_CNR; i++) { 686 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 687 if ((usbsts & XHCI_STS_CNR) == 0) 688 break; 689 usb_delay_ms(&sc->sc_bus, 1); 690 } 691 if (i >= XHCI_WAIT_CNR) { 692 aprint_error_dev(sc->sc_dev, "controller not ready timeout\n"); 693 return EIO; 694 } 695 696 /* Halt controller */ 697 usbcmd = 0; 698 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 699 usb_delay_ms(&sc->sc_bus, 1); 700 701 /* Reset controller */ 702 usbcmd = XHCI_CMD_HCRST; 703 xhci_op_write_4(sc, XHCI_USBCMD, usbcmd); 704 for (i = 0; i < XHCI_WAIT_HCRST; i++) { 705 /* 706 * Wait 1ms first. Existing Intel xHCI requies 1ms delay to 707 * prevent system hang (Errata). 708 */ 709 usb_delay_ms(&sc->sc_bus, 1); 710 usbcmd = xhci_op_read_4(sc, XHCI_USBCMD); 711 if ((usbcmd & XHCI_CMD_HCRST) == 0) 712 break; 713 } 714 if (i >= XHCI_WAIT_HCRST) { 715 aprint_error_dev(sc->sc_dev, "host controller reset timeout\n"); 716 return EIO; 717 } 718 719 /* Check controller not ready */ 720 for (i = 0; i < XHCI_WAIT_CNR; i++) { 721 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 722 if ((usbsts & XHCI_STS_CNR) == 0) 723 break; 724 usb_delay_ms(&sc->sc_bus, 1); 725 } 726 if (i >= XHCI_WAIT_CNR) { 727 aprint_error_dev(sc->sc_dev, 728 "controller not ready timeout after reset\n"); 729 return EIO; 730 } 731 732 return 0; 733 } 734 735 736 /* 7.2 xHCI Support Protocol Capability */ 737 static void 738 xhci_id_protocols(struct xhci_softc *sc, bus_size_t ecp) 739 { 740 /* XXX Cache this lot */ 741 742 const uint32_t w0 = xhci_read_4(sc, ecp); 743 const uint32_t w4 = xhci_read_4(sc, ecp + 4); 744 const uint32_t w8 = xhci_read_4(sc, ecp + 8); 745 const uint32_t wc = xhci_read_4(sc, ecp + 0xc); 746 747 aprint_debug_dev(sc->sc_dev, 748 " SP: %08x %08x %08x %08x\n", w0, w4, w8, wc); 749 750 if (w4 != XHCI_XECP_USBID) 751 return; 752 753 const int major = XHCI_XECP_SP_W0_MAJOR(w0); 754 const int minor = XHCI_XECP_SP_W0_MINOR(w0); 755 const uint8_t cpo = XHCI_XECP_SP_W8_CPO(w8); 756 const uint8_t cpc = XHCI_XECP_SP_W8_CPC(w8); 757 758 const uint16_t mm = __SHIFTOUT(w0, __BITS(31, 16)); 759 switch (mm) { 760 case 0x0200: 761 case 0x0300: 762 case 0x0301: 763 aprint_debug_dev(sc->sc_dev, " %s ports %d - %d\n", 764 major == 3 ? "ss" : "hs", cpo, cpo + cpc -1); 765 break; 766 default: 767 aprint_debug_dev(sc->sc_dev, " unknown major/minor (%d/%d)\n", 768 major, minor); 769 return; 770 } 771 772 const size_t bus = (major == 3) ? 0 : 1; 773 774 /* Index arrays with 0..n-1 where ports are numbered 1..n */ 775 for (size_t cp = cpo - 1; cp < cpo + cpc - 1; cp++) { 776 if (sc->sc_ctlrportmap[cp] != 0) { 777 aprint_error_dev(sc->sc_dev, "contoller port %zu " 778 "already assigned", cp); 779 continue; 780 } 781 782 sc->sc_ctlrportbus[cp / NBBY] |= 783 bus == 0 ? 0 : __BIT(cp % NBBY); 784 785 const size_t rhp = sc->sc_rhportcount[bus]++; 786 787 KASSERTMSG(sc->sc_rhportmap[bus][rhp] == 0, 788 "bus %zu rhp %zu is %d", bus, rhp, 789 sc->sc_rhportmap[bus][rhp]); 790 791 sc->sc_rhportmap[bus][rhp] = cp + 1; 792 sc->sc_ctlrportmap[cp] = rhp + 1; 793 } 794 } 795 796 /* Process extended capabilities */ 797 static void 798 xhci_ecp(struct xhci_softc *sc, uint32_t hcc) 799 { 800 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 801 802 bus_size_t ecp = XHCI_HCC_XECP(hcc) * 4; 803 while (ecp != 0) { 804 uint32_t ecr = xhci_read_4(sc, ecp); 805 aprint_debug_dev(sc->sc_dev, "ECR: 0x%08x\n", ecr); 806 switch (XHCI_XECP_ID(ecr)) { 807 case XHCI_ID_PROTOCOLS: { 808 xhci_id_protocols(sc, ecp); 809 break; 810 } 811 case XHCI_ID_USB_LEGACY: { 812 uint8_t bios_sem; 813 814 /* Take host controller ownership from BIOS */ 815 bios_sem = xhci_read_1(sc, ecp + XHCI_XECP_BIOS_SEM); 816 if (bios_sem) { 817 /* sets xHCI to be owned by OS */ 818 xhci_write_1(sc, ecp + XHCI_XECP_OS_SEM, 1); 819 aprint_debug_dev(sc->sc_dev, 820 "waiting for BIOS to give up control\n"); 821 for (int i = 0; i < 5000; i++) { 822 bios_sem = xhci_read_1(sc, ecp + 823 XHCI_XECP_BIOS_SEM); 824 if (bios_sem == 0) 825 break; 826 DELAY(1000); 827 } 828 if (bios_sem) { 829 aprint_error_dev(sc->sc_dev, 830 "timed out waiting for BIOS\n"); 831 } 832 } 833 break; 834 } 835 default: 836 break; 837 } 838 ecr = xhci_read_4(sc, ecp); 839 if (XHCI_XECP_NEXT(ecr) == 0) { 840 ecp = 0; 841 } else { 842 ecp += XHCI_XECP_NEXT(ecr) * 4; 843 } 844 } 845 } 846 847 #define XHCI_HCCPREV1_BITS \ 848 "\177\020" /* New bitmask */ \ 849 "f\020\020XECP\0" \ 850 "f\014\4MAXPSA\0" \ 851 "b\013CFC\0" \ 852 "b\012SEC\0" \ 853 "b\011SBD\0" \ 854 "b\010FSE\0" \ 855 "b\7NSS\0" \ 856 "b\6LTC\0" \ 857 "b\5LHRC\0" \ 858 "b\4PIND\0" \ 859 "b\3PPC\0" \ 860 "b\2CZC\0" \ 861 "b\1BNC\0" \ 862 "b\0AC64\0" \ 863 "\0" 864 #define XHCI_HCCV1_x_BITS \ 865 "\177\020" /* New bitmask */ \ 866 "f\020\020XECP\0" \ 867 "f\014\4MAXPSA\0" \ 868 "b\013CFC\0" \ 869 "b\012SEC\0" \ 870 "b\011SPC\0" \ 871 "b\010PAE\0" \ 872 "b\7NSS\0" \ 873 "b\6LTC\0" \ 874 "b\5LHRC\0" \ 875 "b\4PIND\0" \ 876 "b\3PPC\0" \ 877 "b\2CSZ\0" \ 878 "b\1BNC\0" \ 879 "b\0AC64\0" \ 880 "\0" 881 882 void 883 xhci_start(struct xhci_softc *sc) 884 { 885 xhci_rt_write_4(sc, XHCI_IMAN(0), XHCI_IMAN_INTR_ENA); 886 if ((sc->sc_quirks & XHCI_QUIRK_INTEL) != 0) 887 /* Intel xhci needs interrupt rate moderated. */ 888 xhci_rt_write_4(sc, XHCI_IMOD(0), XHCI_IMOD_DEFAULT_LP); 889 else 890 xhci_rt_write_4(sc, XHCI_IMOD(0), 0); 891 aprint_debug_dev(sc->sc_dev, "current IMOD %u\n", 892 xhci_rt_read_4(sc, XHCI_IMOD(0))); 893 894 xhci_op_write_4(sc, XHCI_USBCMD, XHCI_CMD_INTE|XHCI_CMD_RS); /* Go! */ 895 aprint_debug_dev(sc->sc_dev, "USBCMD %08"PRIx32"\n", 896 xhci_op_read_4(sc, XHCI_USBCMD)); 897 } 898 899 int 900 xhci_init(struct xhci_softc *sc) 901 { 902 bus_size_t bsz; 903 uint32_t cap, hcs1, hcs2, hcs3, hcc, dboff, rtsoff; 904 uint32_t pagesize, config; 905 int i = 0; 906 uint16_t hciversion; 907 uint8_t caplength; 908 909 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 910 911 /* Set up the bus struct for the usb 3 and usb 2 buses */ 912 sc->sc_bus.ub_methods = &xhci_bus_methods; 913 sc->sc_bus.ub_pipesize = sizeof(struct xhci_pipe); 914 sc->sc_bus.ub_revision = USBREV_3_0; 915 sc->sc_bus.ub_usedma = true; 916 sc->sc_bus.ub_hcpriv = sc; 917 918 sc->sc_bus2.ub_methods = &xhci_bus_methods; 919 sc->sc_bus2.ub_pipesize = sizeof(struct xhci_pipe); 920 sc->sc_bus2.ub_revision = USBREV_2_0; 921 sc->sc_bus2.ub_usedma = true; 922 sc->sc_bus2.ub_hcpriv = sc; 923 sc->sc_bus2.ub_dmatag = sc->sc_bus.ub_dmatag; 924 925 cap = xhci_read_4(sc, XHCI_CAPLENGTH); 926 caplength = XHCI_CAP_CAPLENGTH(cap); 927 hciversion = XHCI_CAP_HCIVERSION(cap); 928 929 if (hciversion < XHCI_HCIVERSION_0_96 || 930 hciversion > XHCI_HCIVERSION_1_0) { 931 aprint_normal_dev(sc->sc_dev, 932 "xHCI version %x.%x not known to be supported\n", 933 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 934 } else { 935 aprint_verbose_dev(sc->sc_dev, "xHCI version %x.%x\n", 936 (hciversion >> 8) & 0xff, (hciversion >> 0) & 0xff); 937 } 938 939 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0, caplength, 940 &sc->sc_cbh) != 0) { 941 aprint_error_dev(sc->sc_dev, "capability subregion failure\n"); 942 return ENOMEM; 943 } 944 945 hcs1 = xhci_cap_read_4(sc, XHCI_HCSPARAMS1); 946 sc->sc_maxslots = XHCI_HCS1_MAXSLOTS(hcs1); 947 sc->sc_maxintrs = XHCI_HCS1_MAXINTRS(hcs1); 948 sc->sc_maxports = XHCI_HCS1_MAXPORTS(hcs1); 949 hcs2 = xhci_cap_read_4(sc, XHCI_HCSPARAMS2); 950 hcs3 = xhci_cap_read_4(sc, XHCI_HCSPARAMS3); 951 aprint_debug_dev(sc->sc_dev, 952 "hcs1=%"PRIx32" hcs2=%"PRIx32" hcs3=%"PRIx32"\n", hcs1, hcs2, hcs3); 953 954 hcc = xhci_cap_read_4(sc, XHCI_HCCPARAMS); 955 sc->sc_ac64 = XHCI_HCC_AC64(hcc); 956 sc->sc_ctxsz = XHCI_HCC_CSZ(hcc) ? 64 : 32; 957 958 char sbuf[128]; 959 if (hciversion < XHCI_HCIVERSION_1_0) 960 snprintb(sbuf, sizeof(sbuf), XHCI_HCCPREV1_BITS, hcc); 961 else 962 snprintb(sbuf, sizeof(sbuf), XHCI_HCCV1_x_BITS, hcc); 963 aprint_debug_dev(sc->sc_dev, "hcc=%s\n", sbuf); 964 aprint_debug_dev(sc->sc_dev, "xECP %x\n", XHCI_HCC_XECP(hcc) * 4); 965 966 /* default all ports to bus 0, i.e. usb 3 */ 967 sc->sc_ctlrportbus = kmem_zalloc( 968 howmany(sc->sc_maxports * sizeof(uint8_t), NBBY), KM_SLEEP); 969 sc->sc_ctlrportmap = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 970 971 /* controller port to bus roothub port map */ 972 for (size_t j = 0; j < __arraycount(sc->sc_rhportmap); j++) { 973 sc->sc_rhportmap[j] = kmem_zalloc(sc->sc_maxports * sizeof(int), KM_SLEEP); 974 } 975 976 /* 977 * Process all Extended Capabilities 978 */ 979 xhci_ecp(sc, hcc); 980 981 bsz = XHCI_PORTSC(sc->sc_maxports); 982 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, caplength, bsz, 983 &sc->sc_obh) != 0) { 984 aprint_error_dev(sc->sc_dev, "operational subregion failure\n"); 985 return ENOMEM; 986 } 987 988 dboff = xhci_cap_read_4(sc, XHCI_DBOFF); 989 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, dboff, 990 sc->sc_maxslots * 4, &sc->sc_dbh) != 0) { 991 aprint_error_dev(sc->sc_dev, "doorbell subregion failure\n"); 992 return ENOMEM; 993 } 994 995 rtsoff = xhci_cap_read_4(sc, XHCI_RTSOFF); 996 if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, rtsoff, 997 sc->sc_maxintrs * 0x20, &sc->sc_rbh) != 0) { 998 aprint_error_dev(sc->sc_dev, "runtime subregion failure\n"); 999 return ENOMEM; 1000 } 1001 1002 int rv; 1003 rv = xhci_hc_reset(sc); 1004 if (rv != 0) { 1005 return rv; 1006 } 1007 1008 if (sc->sc_vendor_init) 1009 sc->sc_vendor_init(sc); 1010 1011 pagesize = xhci_op_read_4(sc, XHCI_PAGESIZE); 1012 aprint_debug_dev(sc->sc_dev, "PAGESIZE 0x%08x\n", pagesize); 1013 pagesize = ffs(pagesize); 1014 if (pagesize == 0) { 1015 aprint_error_dev(sc->sc_dev, "pagesize is 0\n"); 1016 return EIO; 1017 } 1018 sc->sc_pgsz = 1 << (12 + (pagesize - 1)); 1019 aprint_debug_dev(sc->sc_dev, "sc_pgsz 0x%08x\n", (uint32_t)sc->sc_pgsz); 1020 aprint_debug_dev(sc->sc_dev, "sc_maxslots 0x%08x\n", 1021 (uint32_t)sc->sc_maxslots); 1022 aprint_debug_dev(sc->sc_dev, "sc_maxports %d\n", sc->sc_maxports); 1023 1024 usbd_status err; 1025 1026 sc->sc_maxspbuf = XHCI_HCS2_MAXSPBUF(hcs2); 1027 aprint_debug_dev(sc->sc_dev, "sc_maxspbuf %d\n", sc->sc_maxspbuf); 1028 if (sc->sc_maxspbuf != 0) { 1029 err = usb_allocmem(&sc->sc_bus, 1030 sizeof(uint64_t) * sc->sc_maxspbuf, sizeof(uint64_t), 1031 &sc->sc_spbufarray_dma); 1032 if (err) { 1033 aprint_error_dev(sc->sc_dev, 1034 "spbufarray init fail, err %d\n", err); 1035 return ENOMEM; 1036 } 1037 1038 sc->sc_spbuf_dma = kmem_zalloc(sizeof(*sc->sc_spbuf_dma) * 1039 sc->sc_maxspbuf, KM_SLEEP); 1040 uint64_t *spbufarray = KERNADDR(&sc->sc_spbufarray_dma, 0); 1041 for (i = 0; i < sc->sc_maxspbuf; i++) { 1042 usb_dma_t * const dma = &sc->sc_spbuf_dma[i]; 1043 /* allocate contexts */ 1044 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, 1045 sc->sc_pgsz, dma); 1046 if (err) { 1047 aprint_error_dev(sc->sc_dev, 1048 "spbufarray_dma init fail, err %d\n", err); 1049 rv = ENOMEM; 1050 goto bad1; 1051 } 1052 spbufarray[i] = htole64(DMAADDR(dma, 0)); 1053 usb_syncmem(dma, 0, sc->sc_pgsz, 1054 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1055 } 1056 1057 usb_syncmem(&sc->sc_spbufarray_dma, 0, 1058 sizeof(uint64_t) * sc->sc_maxspbuf, BUS_DMASYNC_PREWRITE); 1059 } 1060 1061 config = xhci_op_read_4(sc, XHCI_CONFIG); 1062 config &= ~0xFF; 1063 config |= sc->sc_maxslots & 0xFF; 1064 xhci_op_write_4(sc, XHCI_CONFIG, config); 1065 1066 err = xhci_ring_init(sc, &sc->sc_cr, XHCI_COMMAND_RING_TRBS, 1067 XHCI_COMMAND_RING_SEGMENTS_ALIGN); 1068 if (err) { 1069 aprint_error_dev(sc->sc_dev, "command ring init fail, err %d\n", 1070 err); 1071 rv = ENOMEM; 1072 goto bad1; 1073 } 1074 1075 err = xhci_ring_init(sc, &sc->sc_er, XHCI_EVENT_RING_TRBS, 1076 XHCI_EVENT_RING_SEGMENTS_ALIGN); 1077 if (err) { 1078 aprint_error_dev(sc->sc_dev, "event ring init fail, err %d\n", 1079 err); 1080 rv = ENOMEM; 1081 goto bad2; 1082 } 1083 1084 usb_dma_t *dma; 1085 size_t size; 1086 size_t align; 1087 1088 dma = &sc->sc_eventst_dma; 1089 size = roundup2(XHCI_EVENT_RING_SEGMENTS * XHCI_ERSTE_SIZE, 1090 XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN); 1091 KASSERTMSG(size <= (512 * 1024), "eventst size %zu too large", size); 1092 align = XHCI_EVENT_RING_SEGMENT_TABLE_ALIGN; 1093 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1094 if (err) { 1095 aprint_error_dev(sc->sc_dev, "eventst init fail, err %d\n", 1096 err); 1097 rv = ENOMEM; 1098 goto bad3; 1099 } 1100 1101 memset(KERNADDR(dma, 0), 0, size); 1102 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1103 aprint_debug_dev(sc->sc_dev, "eventst: %016jx %p %zx\n", 1104 (uintmax_t)DMAADDR(&sc->sc_eventst_dma, 0), 1105 KERNADDR(&sc->sc_eventst_dma, 0), 1106 sc->sc_eventst_dma.udma_block->size); 1107 1108 dma = &sc->sc_dcbaa_dma; 1109 size = (1 + sc->sc_maxslots) * sizeof(uint64_t); 1110 KASSERTMSG(size <= 2048, "dcbaa size %zu too large", size); 1111 align = XHCI_DEVICE_CONTEXT_BASE_ADDRESS_ARRAY_ALIGN; 1112 err = usb_allocmem(&sc->sc_bus, size, align, dma); 1113 if (err) { 1114 aprint_error_dev(sc->sc_dev, "dcbaa init fail, err %d\n", err); 1115 rv = ENOMEM; 1116 goto bad4; 1117 } 1118 aprint_debug_dev(sc->sc_dev, "dcbaa: %016jx %p %zx\n", 1119 (uintmax_t)DMAADDR(&sc->sc_dcbaa_dma, 0), 1120 KERNADDR(&sc->sc_dcbaa_dma, 0), 1121 sc->sc_dcbaa_dma.udma_block->size); 1122 1123 memset(KERNADDR(dma, 0), 0, size); 1124 if (sc->sc_maxspbuf != 0) { 1125 /* 1126 * DCBA entry 0 hold the scratchbuf array pointer. 1127 */ 1128 *(uint64_t *)KERNADDR(dma, 0) = 1129 htole64(DMAADDR(&sc->sc_spbufarray_dma, 0)); 1130 } 1131 usb_syncmem(dma, 0, size, BUS_DMASYNC_PREWRITE); 1132 1133 sc->sc_slots = kmem_zalloc(sizeof(*sc->sc_slots) * sc->sc_maxslots, 1134 KM_SLEEP); 1135 if (sc->sc_slots == NULL) { 1136 aprint_error_dev(sc->sc_dev, "slots init fail, err %d\n", err); 1137 rv = ENOMEM; 1138 goto bad; 1139 } 1140 1141 sc->sc_xferpool = pool_cache_init(sizeof(struct xhci_xfer), 0, 0, 0, 1142 "xhcixfer", NULL, IPL_USB, NULL, NULL, NULL); 1143 if (sc->sc_xferpool == NULL) { 1144 aprint_error_dev(sc->sc_dev, "pool_cache init fail, err %d\n", 1145 err); 1146 rv = ENOMEM; 1147 goto bad; 1148 } 1149 1150 cv_init(&sc->sc_command_cv, "xhcicmd"); 1151 cv_init(&sc->sc_cmdbusy_cv, "xhcicmdq"); 1152 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 1153 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 1154 1155 struct xhci_erste *erst; 1156 erst = KERNADDR(&sc->sc_eventst_dma, 0); 1157 erst[0].erste_0 = htole64(xhci_ring_trbp(&sc->sc_er, 0)); 1158 erst[0].erste_2 = htole32(sc->sc_er.xr_ntrb); 1159 erst[0].erste_3 = htole32(0); 1160 usb_syncmem(&sc->sc_eventst_dma, 0, 1161 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS, BUS_DMASYNC_PREWRITE); 1162 1163 xhci_rt_write_4(sc, XHCI_ERSTSZ(0), XHCI_EVENT_RING_SEGMENTS); 1164 xhci_rt_write_8(sc, XHCI_ERSTBA(0), DMAADDR(&sc->sc_eventst_dma, 0)); 1165 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(&sc->sc_er, 0) | 1166 XHCI_ERDP_LO_BUSY); 1167 xhci_op_write_8(sc, XHCI_DCBAAP, DMAADDR(&sc->sc_dcbaa_dma, 0)); 1168 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(&sc->sc_cr, 0) | 1169 sc->sc_cr.xr_cs); 1170 1171 HEXDUMP("eventst", KERNADDR(&sc->sc_eventst_dma, 0), 1172 XHCI_ERSTE_SIZE * XHCI_EVENT_RING_SEGMENTS); 1173 1174 if ((sc->sc_quirks & XHCI_DEFERRED_START) == 0) 1175 xhci_start(sc); 1176 1177 return 0; 1178 1179 bad: 1180 if (sc->sc_xferpool) { 1181 pool_cache_destroy(sc->sc_xferpool); 1182 sc->sc_xferpool = NULL; 1183 } 1184 1185 if (sc->sc_slots) { 1186 kmem_free(sc->sc_slots, sizeof(*sc->sc_slots) * 1187 sc->sc_maxslots); 1188 sc->sc_slots = NULL; 1189 } 1190 1191 usb_freemem(&sc->sc_bus, &sc->sc_dcbaa_dma); 1192 bad4: 1193 usb_freemem(&sc->sc_bus, &sc->sc_eventst_dma); 1194 bad3: 1195 xhci_ring_free(sc, &sc->sc_er); 1196 bad2: 1197 xhci_ring_free(sc, &sc->sc_cr); 1198 i = sc->sc_maxspbuf; 1199 bad1: 1200 for (int j = 0; j < i; j++) 1201 usb_freemem(&sc->sc_bus, &sc->sc_spbuf_dma[j]); 1202 usb_freemem(&sc->sc_bus, &sc->sc_spbufarray_dma); 1203 1204 return rv; 1205 } 1206 1207 static inline bool 1208 xhci_polling_p(struct xhci_softc * const sc) 1209 { 1210 return sc->sc_bus.ub_usepolling || sc->sc_bus2.ub_usepolling; 1211 } 1212 1213 int 1214 xhci_intr(void *v) 1215 { 1216 struct xhci_softc * const sc = v; 1217 int ret = 0; 1218 1219 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1220 1221 if (sc == NULL) 1222 return 0; 1223 1224 mutex_spin_enter(&sc->sc_intr_lock); 1225 1226 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1227 goto done; 1228 1229 /* If we get an interrupt while polling, then just ignore it. */ 1230 if (xhci_polling_p(sc)) { 1231 #ifdef DIAGNOSTIC 1232 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1233 #endif 1234 goto done; 1235 } 1236 1237 ret = xhci_intr1(sc); 1238 if (ret) { 1239 usb_schedsoftintr(&sc->sc_bus); 1240 } 1241 done: 1242 mutex_spin_exit(&sc->sc_intr_lock); 1243 return ret; 1244 } 1245 1246 int 1247 xhci_intr1(struct xhci_softc * const sc) 1248 { 1249 uint32_t usbsts; 1250 uint32_t iman; 1251 1252 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1253 1254 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1255 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1256 #if 0 1257 if ((usbsts & (XHCI_STS_EINT|XHCI_STS_PCD)) == 0) { 1258 return 0; 1259 } 1260 #endif 1261 xhci_op_write_4(sc, XHCI_USBSTS, 1262 usbsts & (2|XHCI_STS_EINT|XHCI_STS_PCD)); /* XXX */ 1263 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1264 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1265 1266 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1267 DPRINTFN(16, "IMAN0 %08jx", iman, 0, 0, 0); 1268 iman |= XHCI_IMAN_INTR_PEND; 1269 xhci_rt_write_4(sc, XHCI_IMAN(0), iman); 1270 iman = xhci_rt_read_4(sc, XHCI_IMAN(0)); 1271 DPRINTFN(16, "IMAN0 %08jx", iman, 0, 0, 0); 1272 usbsts = xhci_op_read_4(sc, XHCI_USBSTS); 1273 DPRINTFN(16, "USBSTS %08jx", usbsts, 0, 0, 0); 1274 1275 return 1; 1276 } 1277 1278 /* 1279 * 3 port speed types used in USB stack 1280 * 1281 * usbdi speed 1282 * definition: USB_SPEED_* in usb.h 1283 * They are used in struct usbd_device in USB stack. 1284 * ioctl interface uses these values too. 1285 * port_status speed 1286 * definition: UPS_*_SPEED in usb.h 1287 * They are used in usb_port_status_t and valid only for USB 2.0. 1288 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus 1289 * of usb_port_status_ext_t indicates port speed. 1290 * Note that some 3.0 values overlap with 2.0 values. 1291 * (e.g. 0x200 means UPS_POER_POWER_SS in SS and 1292 * means UPS_LOW_SPEED in HS.) 1293 * port status returned from hub also uses these values. 1294 * On NetBSD UPS_OTHER_SPEED indicates port speed is super speed 1295 * or more. 1296 * xspeed: 1297 * definition: Protocol Speed ID (PSI) (xHCI 1.1 7.2.1) 1298 * They are used in only slot context and PORTSC reg of xhci. 1299 * The difference between usbdi speed and xspeed is 1300 * that FS and LS values are swapped. 1301 */ 1302 1303 /* convert usbdi speed to xspeed */ 1304 static int 1305 xhci_speed2xspeed(int speed) 1306 { 1307 switch (speed) { 1308 case USB_SPEED_LOW: return 2; 1309 case USB_SPEED_FULL: return 1; 1310 default: return speed; 1311 } 1312 } 1313 1314 #if 0 1315 /* convert xspeed to usbdi speed */ 1316 static int 1317 xhci_xspeed2speed(int xspeed) 1318 { 1319 switch (xspeed) { 1320 case 1: return USB_SPEED_FULL; 1321 case 2: return USB_SPEED_LOW; 1322 default: return xspeed; 1323 } 1324 } 1325 #endif 1326 1327 /* convert xspeed to port status speed */ 1328 static int 1329 xhci_xspeed2psspeed(int xspeed) 1330 { 1331 switch (xspeed) { 1332 case 0: return 0; 1333 case 1: return UPS_FULL_SPEED; 1334 case 2: return UPS_LOW_SPEED; 1335 case 3: return UPS_HIGH_SPEED; 1336 default: return UPS_OTHER_SPEED; 1337 } 1338 } 1339 1340 /* 1341 * Construct input contexts and issue TRB to open pipe. 1342 */ 1343 static usbd_status 1344 xhci_configure_endpoint(struct usbd_pipe *pipe) 1345 { 1346 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1347 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1348 #ifdef USB_DEBUG 1349 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1350 #endif 1351 struct xhci_trb trb; 1352 usbd_status err; 1353 1354 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1355 DPRINTFN(4, "slot %ju dci %ju epaddr 0x%02jx attr 0x%02jx", 1356 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress, 1357 pipe->up_endpoint->ue_edesc->bmAttributes); 1358 1359 /* XXX ensure input context is available? */ 1360 1361 memset(xhci_slot_get_icv(sc, xs, 0), 0, sc->sc_pgsz); 1362 1363 /* set up context */ 1364 xhci_setup_ctx(pipe); 1365 1366 HEXDUMP("input control context", xhci_slot_get_icv(sc, xs, 0), 1367 sc->sc_ctxsz * 1); 1368 HEXDUMP("input endpoint context", xhci_slot_get_icv(sc, xs, 1369 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1); 1370 1371 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1372 trb.trb_2 = 0; 1373 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1374 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1375 1376 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 1377 1378 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1379 HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, dci), 1380 sc->sc_ctxsz * 1); 1381 1382 return err; 1383 } 1384 1385 #if 0 1386 static usbd_status 1387 xhci_unconfigure_endpoint(struct usbd_pipe *pipe) 1388 { 1389 #ifdef USB_DEBUG 1390 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1391 #endif 1392 1393 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1394 DPRINTFN(4, "slot %ju", xs->xs_idx, 0, 0, 0); 1395 1396 return USBD_NORMAL_COMPLETION; 1397 } 1398 #endif 1399 1400 /* 4.6.8, 6.4.3.7 */ 1401 static usbd_status 1402 xhci_reset_endpoint_locked(struct usbd_pipe *pipe) 1403 { 1404 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1405 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1406 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1407 struct xhci_trb trb; 1408 usbd_status err; 1409 1410 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1411 DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1412 1413 KASSERT(mutex_owned(&sc->sc_lock)); 1414 1415 trb.trb_0 = 0; 1416 trb.trb_2 = 0; 1417 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1418 XHCI_TRB_3_EP_SET(dci) | 1419 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP); 1420 1421 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1422 1423 return err; 1424 } 1425 1426 static usbd_status 1427 xhci_reset_endpoint(struct usbd_pipe *pipe) 1428 { 1429 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1430 1431 mutex_enter(&sc->sc_lock); 1432 usbd_status ret = xhci_reset_endpoint_locked(pipe); 1433 mutex_exit(&sc->sc_lock); 1434 1435 return ret; 1436 } 1437 1438 /* 1439 * 4.6.9, 6.4.3.8 1440 * Stop execution of TDs on xfer ring. 1441 * Should be called with sc_lock held. 1442 */ 1443 static usbd_status 1444 xhci_stop_endpoint(struct usbd_pipe *pipe) 1445 { 1446 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1447 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1448 struct xhci_trb trb; 1449 usbd_status err; 1450 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1451 1452 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1453 DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1454 1455 KASSERT(mutex_owned(&sc->sc_lock)); 1456 1457 trb.trb_0 = 0; 1458 trb.trb_2 = 0; 1459 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1460 XHCI_TRB_3_EP_SET(dci) | 1461 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP); 1462 1463 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1464 1465 return err; 1466 } 1467 1468 /* 1469 * Set TR Dequeue Pointer. 1470 * xHCI 1.1 4.6.10 6.4.3.9 1471 * Purge all of the TRBs on ring and reinitialize ring. 1472 * Set TR dequeue Pointr to 0 and Cycle State to 1. 1473 * EPSTATE of endpoint must be ERROR or STOPPED, otherwise CONTEXT_STATE 1474 * error will be generated. 1475 */ 1476 static usbd_status 1477 xhci_set_dequeue_locked(struct usbd_pipe *pipe) 1478 { 1479 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1480 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1481 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc); 1482 struct xhci_ring * const xr = &xs->xs_ep[dci].xe_tr; 1483 struct xhci_trb trb; 1484 usbd_status err; 1485 1486 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1487 DPRINTFN(4, "slot %ju dci %ju", xs->xs_idx, dci, 0, 0); 1488 1489 KASSERT(mutex_owned(&sc->sc_lock)); 1490 1491 xhci_host_dequeue(xr); 1492 1493 /* set DCS */ 1494 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */ 1495 trb.trb_2 = 0; 1496 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1497 XHCI_TRB_3_EP_SET(dci) | 1498 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE); 1499 1500 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1501 1502 return err; 1503 } 1504 1505 static usbd_status 1506 xhci_set_dequeue(struct usbd_pipe *pipe) 1507 { 1508 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1509 1510 mutex_enter(&sc->sc_lock); 1511 usbd_status ret = xhci_set_dequeue_locked(pipe); 1512 mutex_exit(&sc->sc_lock); 1513 1514 return ret; 1515 } 1516 1517 /* 1518 * Open new pipe: called from usbd_setup_pipe_flags. 1519 * Fills methods of pipe. 1520 * If pipe is not for ep0, calls configure_endpoint. 1521 */ 1522 static usbd_status 1523 xhci_open(struct usbd_pipe *pipe) 1524 { 1525 struct usbd_device * const dev = pipe->up_dev; 1526 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 1527 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1528 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1529 1530 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1531 DPRINTFN(1, "addr %jd depth %jd port %jd speed %jd", dev->ud_addr, 1532 dev->ud_depth, dev->ud_powersrc->up_portno, dev->ud_speed); 1533 DPRINTFN(1, " dci %ju type 0x%02jx epaddr 0x%02jx attr 0x%02jx", 1534 xhci_ep_get_dci(ed), ed->bDescriptorType, ed->bEndpointAddress, 1535 ed->bmAttributes); 1536 DPRINTFN(1, " mps %ju ival %ju", UGETW(ed->wMaxPacketSize), 1537 ed->bInterval, 0, 0); 1538 1539 if (sc->sc_dying) 1540 return USBD_IOERROR; 1541 1542 /* Root Hub */ 1543 if (dev->ud_depth == 0 && dev->ud_powersrc->up_portno == 0) { 1544 switch (ed->bEndpointAddress) { 1545 case USB_CONTROL_ENDPOINT: 1546 pipe->up_methods = &roothub_ctrl_methods; 1547 break; 1548 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1549 pipe->up_methods = &xhci_root_intr_methods; 1550 break; 1551 default: 1552 pipe->up_methods = NULL; 1553 DPRINTFN(0, "bad bEndpointAddress 0x%02jx", 1554 ed->bEndpointAddress, 0, 0, 0); 1555 return USBD_INVAL; 1556 } 1557 return USBD_NORMAL_COMPLETION; 1558 } 1559 1560 switch (xfertype) { 1561 case UE_CONTROL: 1562 pipe->up_methods = &xhci_device_ctrl_methods; 1563 break; 1564 case UE_ISOCHRONOUS: 1565 pipe->up_methods = &xhci_device_isoc_methods; 1566 return USBD_INVAL; 1567 break; 1568 case UE_BULK: 1569 pipe->up_methods = &xhci_device_bulk_methods; 1570 break; 1571 case UE_INTERRUPT: 1572 pipe->up_methods = &xhci_device_intr_methods; 1573 break; 1574 default: 1575 return USBD_IOERROR; 1576 break; 1577 } 1578 1579 if (ed->bEndpointAddress != USB_CONTROL_ENDPOINT) 1580 return xhci_configure_endpoint(pipe); 1581 1582 return USBD_NORMAL_COMPLETION; 1583 } 1584 1585 /* 1586 * Closes pipe, called from usbd_kill_pipe via close methods. 1587 * If the endpoint to be closed is ep0, disable_slot. 1588 * Should be called with sc_lock held. 1589 */ 1590 static void 1591 xhci_close_pipe(struct usbd_pipe *pipe) 1592 { 1593 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 1594 struct xhci_slot * const xs = pipe->up_dev->ud_hcpriv; 1595 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 1596 const u_int dci = xhci_ep_get_dci(ed); 1597 struct xhci_trb trb; 1598 uint32_t *cp; 1599 1600 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1601 1602 if (sc->sc_dying) 1603 return; 1604 1605 /* xs is uninitialized before xhci_init_slot */ 1606 if (xs == NULL || xs->xs_idx == 0) 1607 return; 1608 1609 DPRINTFN(4, "pipe %#jx slot %ju dci %ju", (uintptr_t)pipe, xs->xs_idx, 1610 dci, 0); 1611 1612 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 1613 KASSERT(mutex_owned(&sc->sc_lock)); 1614 1615 if (pipe->up_dev->ud_depth == 0) 1616 return; 1617 1618 if (dci == XHCI_DCI_EP_CONTROL) { 1619 DPRINTFN(4, "closing ep0", 0, 0, 0, 0); 1620 xhci_disable_slot(sc, xs->xs_idx); 1621 return; 1622 } 1623 1624 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED) 1625 (void)xhci_stop_endpoint(pipe); 1626 1627 /* 1628 * set appropriate bit to be dropped. 1629 * don't set DC bit to 1, otherwise all endpoints 1630 * would be deconfigured. 1631 */ 1632 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 1633 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci)); 1634 cp[1] = htole32(0); 1635 1636 /* XXX should be most significant one, not dci? */ 1637 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 1638 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci)); 1639 1640 /* configure ep context performs an implicit dequeue */ 1641 xhci_host_dequeue(&xs->xs_ep[dci].xe_tr); 1642 1643 /* sync input contexts before they are read from memory */ 1644 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 1645 1646 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 1647 trb.trb_2 = 0; 1648 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 1649 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP); 1650 1651 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 1652 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 1653 } 1654 1655 /* 1656 * Abort transfer. 1657 * Should be called with sc_lock held. 1658 */ 1659 static void 1660 xhci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 1661 { 1662 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1663 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1664 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1665 1666 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1667 DPRINTFN(4, "xfer %#jx pipe %#jx status %jd", 1668 (uintptr_t)xfer, (uintptr_t)xfer->ux_pipe, status, 0); 1669 1670 KASSERT(mutex_owned(&sc->sc_lock)); 1671 1672 if (sc->sc_dying) { 1673 /* If we're dying, just do the software part. */ 1674 DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer, 1675 xfer->ux_status, 0, 0); 1676 xfer->ux_status = status; 1677 callout_stop(&xfer->ux_callout); 1678 usb_transfer_complete(xfer); 1679 return; 1680 } 1681 1682 /* 1683 * If an abort is already in progress then just wait for it to 1684 * complete and return. 1685 */ 1686 if (xfer->ux_hcflags & UXFER_ABORTING) { 1687 DPRINTFN(4, "already aborting", 0, 0, 0, 0); 1688 #ifdef DIAGNOSTIC 1689 if (status == USBD_TIMEOUT) 1690 DPRINTFN(4, "TIMEOUT while aborting", 0, 0, 0, 0); 1691 #endif 1692 /* Override the status which might be USBD_TIMEOUT. */ 1693 xfer->ux_status = status; 1694 DPRINTFN(4, "xfer %#jx waiting for abort to finish", 1695 (uintptr_t)xfer, 0, 0, 0); 1696 xfer->ux_hcflags |= UXFER_ABORTWAIT; 1697 while (xfer->ux_hcflags & UXFER_ABORTING) 1698 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 1699 return; 1700 } 1701 xfer->ux_hcflags |= UXFER_ABORTING; 1702 1703 /* 1704 * Step 1: Stop xfer timeout timer. 1705 */ 1706 xfer->ux_status = status; 1707 callout_stop(&xfer->ux_callout); 1708 1709 /* 1710 * Step 2: Stop execution of TD on the ring. 1711 */ 1712 switch (xhci_get_epstate(sc, xs, dci)) { 1713 case XHCI_EPSTATE_HALTED: 1714 (void)xhci_reset_endpoint_locked(xfer->ux_pipe); 1715 break; 1716 case XHCI_EPSTATE_STOPPED: 1717 break; 1718 default: 1719 (void)xhci_stop_endpoint(xfer->ux_pipe); 1720 break; 1721 } 1722 #ifdef DIAGNOSTIC 1723 uint32_t epst = xhci_get_epstate(sc, xs, dci); 1724 if (epst != XHCI_EPSTATE_STOPPED) 1725 DPRINTFN(4, "dci %ju not stopped %ju", dci, epst, 0, 0); 1726 #endif 1727 1728 /* 1729 * Step 3: Remove any vestiges of the xfer from the ring. 1730 */ 1731 xhci_set_dequeue_locked(xfer->ux_pipe); 1732 1733 /* 1734 * Step 4: Notify completion to waiting xfers. 1735 */ 1736 int wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 1737 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 1738 usb_transfer_complete(xfer); 1739 if (wake) { 1740 cv_broadcast(&xfer->ux_hccv); 1741 } 1742 DPRINTFN(14, "end", 0, 0, 0, 0); 1743 1744 KASSERT(mutex_owned(&sc->sc_lock)); 1745 } 1746 1747 static void 1748 xhci_host_dequeue(struct xhci_ring * const xr) 1749 { 1750 /* When dequeueing the controller, update our struct copy too */ 1751 memset(xr->xr_trb, 0, xr->xr_ntrb * XHCI_TRB_SIZE); 1752 usb_syncmem(&xr->xr_dma, 0, xr->xr_ntrb * XHCI_TRB_SIZE, 1753 BUS_DMASYNC_PREWRITE); 1754 memset(xr->xr_cookies, 0, xr->xr_ntrb * sizeof(*xr->xr_cookies)); 1755 1756 xr->xr_ep = 0; 1757 xr->xr_cs = 1; 1758 } 1759 1760 /* 1761 * Recover STALLed endpoint. 1762 * xHCI 1.1 sect 4.10.2.1 1763 * Issue RESET_EP to recover halt condition and SET_TR_DEQUEUE to remove 1764 * all transfers on transfer ring. 1765 * These are done in thread context asynchronously. 1766 */ 1767 static void 1768 xhci_clear_endpoint_stall_async_task(void *cookie) 1769 { 1770 struct usbd_xfer * const xfer = cookie; 1771 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1772 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 1773 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 1774 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 1775 1776 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1777 DPRINTFN(4, "xfer %#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, 1778 dci, 0); 1779 1780 xhci_reset_endpoint(xfer->ux_pipe); 1781 xhci_set_dequeue(xfer->ux_pipe); 1782 1783 mutex_enter(&sc->sc_lock); 1784 tr->is_halted = false; 1785 usb_transfer_complete(xfer); 1786 mutex_exit(&sc->sc_lock); 1787 DPRINTFN(4, "ends", 0, 0, 0, 0); 1788 } 1789 1790 static usbd_status 1791 xhci_clear_endpoint_stall_async(struct usbd_xfer *xfer) 1792 { 1793 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 1794 struct xhci_pipe * const xp = (struct xhci_pipe *)xfer->ux_pipe; 1795 1796 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1797 DPRINTFN(4, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 1798 1799 if (sc->sc_dying) { 1800 return USBD_IOERROR; 1801 } 1802 1803 usb_init_task(&xp->xp_async_task, 1804 xhci_clear_endpoint_stall_async_task, xfer, USB_TASKQ_MPSAFE); 1805 usb_add_task(xfer->ux_pipe->up_dev, &xp->xp_async_task, USB_TASKQ_HC); 1806 DPRINTFN(4, "ends", 0, 0, 0, 0); 1807 1808 return USBD_NORMAL_COMPLETION; 1809 } 1810 1811 /* Process roothub port status/change events and notify to uhub_intr. */ 1812 static void 1813 xhci_rhpsc(struct xhci_softc * const sc, u_int ctlrport) 1814 { 1815 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1816 DPRINTFN(4, "xhci%jd: port %ju status change", device_unit(sc->sc_dev), 1817 ctlrport, 0, 0); 1818 1819 if (ctlrport > sc->sc_maxports) 1820 return; 1821 1822 const size_t bn = xhci_ctlrport2bus(sc, ctlrport); 1823 const size_t rhp = xhci_ctlrport2rhport(sc, ctlrport); 1824 struct usbd_xfer * const xfer = sc->sc_intrxfer[bn]; 1825 1826 DPRINTFN(4, "xhci%jd: bus %jd bp %ju xfer %#jx status change", 1827 device_unit(sc->sc_dev), bn, rhp, (uintptr_t)xfer); 1828 1829 if (xfer == NULL) 1830 return; 1831 1832 uint8_t *p = xfer->ux_buf; 1833 memset(p, 0, xfer->ux_length); 1834 p[rhp / NBBY] |= 1 << (rhp % NBBY); 1835 xfer->ux_actlen = xfer->ux_length; 1836 xfer->ux_status = USBD_NORMAL_COMPLETION; 1837 usb_transfer_complete(xfer); 1838 } 1839 1840 /* Process Transfer Events */ 1841 static void 1842 xhci_event_transfer(struct xhci_softc * const sc, 1843 const struct xhci_trb * const trb) 1844 { 1845 uint64_t trb_0; 1846 uint32_t trb_2, trb_3; 1847 uint8_t trbcode; 1848 u_int slot, dci; 1849 struct xhci_slot *xs; 1850 struct xhci_ring *xr; 1851 struct xhci_xfer *xx; 1852 struct usbd_xfer *xfer; 1853 usbd_status err; 1854 1855 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 1856 1857 trb_0 = le64toh(trb->trb_0); 1858 trb_2 = le32toh(trb->trb_2); 1859 trb_3 = le32toh(trb->trb_3); 1860 trbcode = XHCI_TRB_2_ERROR_GET(trb_2); 1861 slot = XHCI_TRB_3_SLOT_GET(trb_3); 1862 dci = XHCI_TRB_3_EP_GET(trb_3); 1863 xs = &sc->sc_slots[slot]; 1864 xr = &xs->xs_ep[dci].xe_tr; 1865 1866 /* sanity check */ 1867 KASSERTMSG(xs->xs_idx != 0 && xs->xs_idx <= sc->sc_maxslots, 1868 "invalid xs_idx %u slot %u", xs->xs_idx, slot); 1869 1870 int idx = 0; 1871 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1872 if (xhci_trb_get_idx(xr, trb_0, &idx)) { 1873 DPRINTFN(0, "invalid trb_0 0x%jx", trb_0, 0, 0, 0); 1874 return; 1875 } 1876 xx = xr->xr_cookies[idx]; 1877 1878 /* clear cookie of consumed TRB */ 1879 xr->xr_cookies[idx] = NULL; 1880 1881 /* 1882 * xx is NULL if pipe is opened but xfer is not started. 1883 * It happens when stopping idle pipe. 1884 */ 1885 if (xx == NULL || trbcode == XHCI_TRB_ERROR_LENGTH) { 1886 DPRINTFN(1, "Ignore #%ju: cookie %#jx cc %ju dci %ju", 1887 idx, (uintptr_t)xx, trbcode, dci); 1888 DPRINTFN(1, " orig TRB %jx type %ju", trb_0, 1889 XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)), 1890 0, 0); 1891 return; 1892 } 1893 } else { 1894 /* When ED != 0, trb_0 is virtual addr of struct xhci_xfer. */ 1895 xx = (void *)(uintptr_t)(trb_0 & ~0x3); 1896 } 1897 /* XXX this may not happen */ 1898 if (xx == NULL) { 1899 DPRINTFN(1, "xfer done: xx is NULL", 0, 0, 0, 0); 1900 return; 1901 } 1902 xfer = &xx->xx_xfer; 1903 /* XXX this may happen when detaching */ 1904 if (xfer == NULL) { 1905 DPRINTFN(1, "xx(%#jx)->xx_xfer is NULL trb_0 %#jx", 1906 (uintptr_t)xx, trb_0, 0, 0); 1907 return; 1908 } 1909 DPRINTFN(14, "xfer %#jx", (uintptr_t)xfer, 0, 0, 0); 1910 /* XXX I dunno why this happens */ 1911 KASSERTMSG(xfer->ux_pipe != NULL, "xfer(%p)->ux_pipe is NULL", xfer); 1912 1913 if (!xfer->ux_pipe->up_repeat && 1914 SIMPLEQ_EMPTY(&xfer->ux_pipe->up_queue)) { 1915 DPRINTFN(1, "xfer(%#jx)->pipe not queued", (uintptr_t)xfer, 1916 0, 0, 0); 1917 return; 1918 } 1919 1920 /* 4.11.5.2 Event Data TRB */ 1921 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 1922 DPRINTFN(14, "transfer Event Data: 0x%016jx 0x%08jx" 1923 " %02jx", trb_0, XHCI_TRB_2_REM_GET(trb_2), trbcode, 0); 1924 if ((trb_0 & 0x3) == 0x3) { 1925 xfer->ux_actlen = XHCI_TRB_2_REM_GET(trb_2); 1926 } 1927 } 1928 1929 switch (trbcode) { 1930 case XHCI_TRB_ERROR_SHORT_PKT: 1931 case XHCI_TRB_ERROR_SUCCESS: 1932 /* 1933 * A ctrl transfer can generate two events if it has a Data 1934 * stage. A short data stage can be OK and should not 1935 * complete the transfer as the status stage needs to be 1936 * performed. 1937 * 1938 * Note: Data and Status stage events point at same xfer. 1939 * ux_actlen and ux_dmabuf will be passed to 1940 * usb_transfer_complete after the Status stage event. 1941 * 1942 * It can be distingished which stage generates the event: 1943 * + by checking least 3 bits of trb_0 if ED==1. 1944 * (see xhci_device_ctrl_start). 1945 * + by checking the type of original TRB if ED==0. 1946 * 1947 * In addition, intr, bulk, and isoc transfer currently 1948 * consists of single TD, so the "skip" is not needed. 1949 * ctrl xfer uses EVENT_DATA, and others do not. 1950 * Thus driver can switch the flow by checking ED bit. 1951 */ 1952 if ((trb_3 & XHCI_TRB_3_ED_BIT) == 0) { 1953 if (xfer->ux_actlen == 0) 1954 xfer->ux_actlen = xfer->ux_length - 1955 XHCI_TRB_2_REM_GET(trb_2); 1956 if (XHCI_TRB_3_TYPE_GET(le32toh(xr->xr_trb[idx].trb_3)) 1957 == XHCI_TRB_TYPE_DATA_STAGE) { 1958 return; 1959 } 1960 } else if ((trb_0 & 0x3) == 0x3) { 1961 return; 1962 } 1963 err = USBD_NORMAL_COMPLETION; 1964 break; 1965 case XHCI_TRB_ERROR_STOPPED: 1966 case XHCI_TRB_ERROR_LENGTH: 1967 case XHCI_TRB_ERROR_STOPPED_SHORT: 1968 /* 1969 * don't complete the transfer being aborted 1970 * as abort_xfer does instead. 1971 */ 1972 if (xfer->ux_hcflags & UXFER_ABORTING) { 1973 DPRINTFN(14, "ignore aborting xfer %#jx", 1974 (uintptr_t)xfer, 0, 0, 0); 1975 return; 1976 } 1977 err = USBD_CANCELLED; 1978 break; 1979 case XHCI_TRB_ERROR_STALL: 1980 case XHCI_TRB_ERROR_BABBLE: 1981 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 1982 xr->is_halted = true; 1983 err = USBD_STALLED; 1984 /* 1985 * Stalled endpoints can be recoverd by issuing 1986 * command TRB TYPE_RESET_EP on xHCI instead of 1987 * issuing request CLEAR_FEATURE UF_ENDPOINT_HALT 1988 * on the endpoint. However, this function may be 1989 * called from softint context (e.g. from umass), 1990 * in that case driver gets KASSERT in cv_timedwait 1991 * in xhci_do_command. 1992 * To avoid this, this runs reset_endpoint and 1993 * usb_transfer_complete in usb task thread 1994 * asynchronously (and then umass issues clear 1995 * UF_ENDPOINT_HALT). 1996 */ 1997 xfer->ux_status = err; 1998 callout_stop(&xfer->ux_callout); 1999 xhci_clear_endpoint_stall_async(xfer); 2000 return; 2001 default: 2002 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0); 2003 err = USBD_IOERROR; 2004 break; 2005 } 2006 xfer->ux_status = err; 2007 2008 if ((trb_3 & XHCI_TRB_3_ED_BIT) != 0) { 2009 if ((trb_0 & 0x3) == 0x0) { 2010 callout_stop(&xfer->ux_callout); 2011 usb_transfer_complete(xfer); 2012 } 2013 } else { 2014 callout_stop(&xfer->ux_callout); 2015 usb_transfer_complete(xfer); 2016 } 2017 } 2018 2019 /* Process Command complete events */ 2020 static void 2021 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb) 2022 { 2023 uint64_t trb_0; 2024 uint32_t trb_2, trb_3; 2025 2026 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2027 2028 KASSERT(mutex_owned(&sc->sc_lock)); 2029 2030 trb_0 = le64toh(trb->trb_0); 2031 trb_2 = le32toh(trb->trb_2); 2032 trb_3 = le32toh(trb->trb_3); 2033 2034 if (trb_0 == sc->sc_command_addr) { 2035 sc->sc_resultpending = false; 2036 2037 sc->sc_result_trb.trb_0 = trb_0; 2038 sc->sc_result_trb.trb_2 = trb_2; 2039 sc->sc_result_trb.trb_3 = trb_3; 2040 if (XHCI_TRB_2_ERROR_GET(trb_2) != 2041 XHCI_TRB_ERROR_SUCCESS) { 2042 DPRINTFN(1, "command completion " 2043 "failure: 0x%016jx 0x%08jx 0x%08jx", 2044 trb_0, trb_2, trb_3, 0); 2045 } 2046 cv_signal(&sc->sc_command_cv); 2047 } else { 2048 DPRINTFN(1, "spurious event: %#jx 0x%016jx " 2049 "0x%08jx 0x%08jx", (uintptr_t)trb, trb_0, trb_2, trb_3); 2050 } 2051 } 2052 2053 /* 2054 * Process events. 2055 * called from xhci_softintr 2056 */ 2057 static void 2058 xhci_handle_event(struct xhci_softc * const sc, 2059 const struct xhci_trb * const trb) 2060 { 2061 uint64_t trb_0; 2062 uint32_t trb_2, trb_3; 2063 2064 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2065 2066 trb_0 = le64toh(trb->trb_0); 2067 trb_2 = le32toh(trb->trb_2); 2068 trb_3 = le32toh(trb->trb_3); 2069 2070 DPRINTFN(14, "event: %#jx 0x%016jx 0x%08jx 0x%08jx", 2071 (uintptr_t)trb, trb_0, trb_2, trb_3); 2072 2073 /* 2074 * 4.11.3.1, 6.4.2.1 2075 * TRB Pointer is invalid for these completion codes. 2076 */ 2077 switch (XHCI_TRB_2_ERROR_GET(trb_2)) { 2078 case XHCI_TRB_ERROR_RING_UNDERRUN: 2079 case XHCI_TRB_ERROR_RING_OVERRUN: 2080 case XHCI_TRB_ERROR_VF_RING_FULL: 2081 return; 2082 default: 2083 if (trb_0 == 0) { 2084 return; 2085 } 2086 break; 2087 } 2088 2089 switch (XHCI_TRB_3_TYPE_GET(trb_3)) { 2090 case XHCI_TRB_EVENT_TRANSFER: 2091 xhci_event_transfer(sc, trb); 2092 break; 2093 case XHCI_TRB_EVENT_CMD_COMPLETE: 2094 xhci_event_cmd(sc, trb); 2095 break; 2096 case XHCI_TRB_EVENT_PORT_STS_CHANGE: 2097 xhci_rhpsc(sc, (uint32_t)((trb_0 >> 24) & 0xff)); 2098 break; 2099 default: 2100 break; 2101 } 2102 } 2103 2104 static void 2105 xhci_softintr(void *v) 2106 { 2107 struct usbd_bus * const bus = v; 2108 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2109 struct xhci_ring * const er = &sc->sc_er; 2110 struct xhci_trb *trb; 2111 int i, j, k; 2112 2113 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2114 2115 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 2116 2117 i = er->xr_ep; 2118 j = er->xr_cs; 2119 2120 DPRINTFN(16, "er: xr_ep %jd xr_cs %jd", i, j, 0, 0); 2121 2122 while (1) { 2123 usb_syncmem(&er->xr_dma, XHCI_TRB_SIZE * i, XHCI_TRB_SIZE, 2124 BUS_DMASYNC_POSTREAD); 2125 trb = &er->xr_trb[i]; 2126 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 2127 2128 if (j != k) 2129 break; 2130 2131 xhci_handle_event(sc, trb); 2132 2133 i++; 2134 if (i == er->xr_ntrb) { 2135 i = 0; 2136 j ^= 1; 2137 } 2138 } 2139 2140 er->xr_ep = i; 2141 er->xr_cs = j; 2142 2143 xhci_rt_write_8(sc, XHCI_ERDP(0), xhci_ring_trbp(er, er->xr_ep) | 2144 XHCI_ERDP_LO_BUSY); 2145 2146 DPRINTFN(16, "ends", 0, 0, 0, 0); 2147 2148 return; 2149 } 2150 2151 static void 2152 xhci_poll(struct usbd_bus *bus) 2153 { 2154 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2155 2156 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2157 2158 mutex_spin_enter(&sc->sc_intr_lock); 2159 int ret = xhci_intr1(sc); 2160 if (ret) { 2161 xhci_softintr(bus); 2162 } 2163 mutex_spin_exit(&sc->sc_intr_lock); 2164 2165 return; 2166 } 2167 2168 static struct usbd_xfer * 2169 xhci_allocx(struct usbd_bus *bus, unsigned int nframes) 2170 { 2171 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2172 struct usbd_xfer *xfer; 2173 2174 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2175 2176 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 2177 if (xfer != NULL) { 2178 memset(xfer, 0, sizeof(struct xhci_xfer)); 2179 #ifdef DIAGNOSTIC 2180 xfer->ux_state = XFER_BUSY; 2181 #endif 2182 } 2183 2184 return xfer; 2185 } 2186 2187 static void 2188 xhci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 2189 { 2190 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2191 2192 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2193 2194 #ifdef DIAGNOSTIC 2195 if (xfer->ux_state != XFER_BUSY) { 2196 DPRINTFN(0, "xfer=%#jx not busy, 0x%08jx", 2197 (uintptr_t)xfer, xfer->ux_state, 0, 0); 2198 } 2199 xfer->ux_state = XFER_FREE; 2200 #endif 2201 pool_cache_put(sc->sc_xferpool, xfer); 2202 } 2203 2204 static void 2205 xhci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 2206 { 2207 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2208 2209 *lock = &sc->sc_lock; 2210 } 2211 2212 extern uint32_t usb_cookie_no; 2213 2214 /* 2215 * xHCI 4.3 2216 * Called when uhub_explore finds a new device (via usbd_new_device). 2217 * Port initialization and speed detection (4.3.1) are already done in uhub.c. 2218 * This function does: 2219 * Allocate and construct dev structure of default endpoint (ep0). 2220 * Allocate and open pipe of ep0. 2221 * Enable slot and initialize slot context. 2222 * Set Address. 2223 * Read initial device descriptor. 2224 * Determine initial MaxPacketSize (mps) by speed. 2225 * Read full device descriptor. 2226 * Register this device. 2227 * Finally state of device transitions ADDRESSED. 2228 */ 2229 static usbd_status 2230 xhci_new_device(device_t parent, struct usbd_bus *bus, int depth, 2231 int speed, int port, struct usbd_port *up) 2232 { 2233 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 2234 struct usbd_device *dev; 2235 usbd_status err; 2236 usb_device_descriptor_t *dd; 2237 struct xhci_slot *xs; 2238 uint32_t *cp; 2239 2240 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2241 DPRINTFN(4, "port %ju depth %ju speed %ju up %#jx", 2242 port, depth, speed, (uintptr_t)up); 2243 2244 dev = kmem_zalloc(sizeof(*dev), KM_SLEEP); 2245 dev->ud_bus = bus; 2246 dev->ud_quirks = &usbd_no_quirk; 2247 dev->ud_addr = 0; 2248 dev->ud_ddesc.bMaxPacketSize = 0; 2249 dev->ud_depth = depth; 2250 dev->ud_powersrc = up; 2251 dev->ud_myhub = up->up_parent; 2252 dev->ud_speed = speed; 2253 dev->ud_langid = USBD_NOLANG; 2254 dev->ud_cookie.cookie = ++usb_cookie_no; 2255 2256 /* Set up default endpoint handle. */ 2257 dev->ud_ep0.ue_edesc = &dev->ud_ep0desc; 2258 /* doesn't matter, just don't let it uninitialized */ 2259 dev->ud_ep0.ue_toggle = 0; 2260 2261 /* Set up default endpoint descriptor. */ 2262 dev->ud_ep0desc.bLength = USB_ENDPOINT_DESCRIPTOR_SIZE; 2263 dev->ud_ep0desc.bDescriptorType = UDESC_ENDPOINT; 2264 dev->ud_ep0desc.bEndpointAddress = USB_CONTROL_ENDPOINT; 2265 dev->ud_ep0desc.bmAttributes = UE_CONTROL; 2266 dev->ud_ep0desc.bInterval = 0; 2267 2268 /* 4.3, 4.8.2.1 */ 2269 switch (speed) { 2270 case USB_SPEED_SUPER: 2271 case USB_SPEED_SUPER_PLUS: 2272 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_3_MAX_CTRL_PACKET); 2273 break; 2274 case USB_SPEED_FULL: 2275 /* XXX using 64 as initial mps of ep0 in FS */ 2276 case USB_SPEED_HIGH: 2277 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_2_MAX_CTRL_PACKET); 2278 break; 2279 case USB_SPEED_LOW: 2280 default: 2281 USETW(dev->ud_ep0desc.wMaxPacketSize, USB_MAX_IPACKET); 2282 break; 2283 } 2284 2285 up->up_dev = dev; 2286 2287 /* Establish the default pipe. */ 2288 err = usbd_setup_pipe(dev, 0, &dev->ud_ep0, USBD_DEFAULT_INTERVAL, 2289 &dev->ud_pipe0); 2290 if (err) { 2291 goto bad; 2292 } 2293 2294 dd = &dev->ud_ddesc; 2295 2296 if (depth == 0 && port == 0) { 2297 KASSERT(bus->ub_devices[USB_ROOTHUB_INDEX] == NULL); 2298 bus->ub_devices[USB_ROOTHUB_INDEX] = dev; 2299 err = usbd_get_initial_ddesc(dev, dd); 2300 if (err) { 2301 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2302 goto bad; 2303 } 2304 2305 err = usbd_reload_device_desc(dev); 2306 if (err) { 2307 DPRINTFN(1, "reload desc %ju", err, 0, 0, 0); 2308 goto bad; 2309 } 2310 } else { 2311 uint8_t slot = 0; 2312 2313 /* 4.3.2 */ 2314 err = xhci_enable_slot(sc, &slot); 2315 if (err) { 2316 DPRINTFN(1, "enable slot %ju", err, 0, 0, 0); 2317 goto bad; 2318 } 2319 2320 xs = &sc->sc_slots[slot]; 2321 dev->ud_hcpriv = xs; 2322 2323 /* 4.3.3 initialize slot structure */ 2324 err = xhci_init_slot(dev, slot); 2325 if (err) { 2326 DPRINTFN(1, "init slot %ju", err, 0, 0, 0); 2327 dev->ud_hcpriv = NULL; 2328 /* 2329 * We have to disable_slot here because 2330 * xs->xs_idx == 0 when xhci_init_slot fails, 2331 * in that case usbd_remove_dev won't work. 2332 */ 2333 mutex_enter(&sc->sc_lock); 2334 xhci_disable_slot(sc, slot); 2335 mutex_exit(&sc->sc_lock); 2336 goto bad; 2337 } 2338 2339 /* 4.3.4 Address Assignment */ 2340 err = xhci_set_address(dev, slot, false); 2341 if (err) { 2342 DPRINTFN(1, "set address w/o bsr %ju", err, 0, 0, 0); 2343 goto bad; 2344 } 2345 2346 /* Allow device time to set new address */ 2347 usbd_delay_ms(dev, USB_SET_ADDRESS_SETTLE); 2348 2349 cp = xhci_slot_get_dcv(sc, xs, XHCI_DCI_SLOT); 2350 HEXDUMP("slot context", cp, sc->sc_ctxsz); 2351 uint8_t addr = XHCI_SCTX_3_DEV_ADDR_GET(le32toh(cp[3])); 2352 DPRINTFN(4, "device address %ju", addr, 0, 0, 0); 2353 /* 2354 * XXX ensure we know when the hardware does something 2355 * we can't yet cope with 2356 */ 2357 KASSERTMSG(addr >= 1 && addr <= 127, "addr %d", addr); 2358 dev->ud_addr = addr; 2359 2360 KASSERTMSG(bus->ub_devices[usb_addr2dindex(dev->ud_addr)] == NULL, 2361 "addr %d already allocated", dev->ud_addr); 2362 /* 2363 * The root hub is given its own slot 2364 */ 2365 bus->ub_devices[usb_addr2dindex(dev->ud_addr)] = dev; 2366 2367 err = usbd_get_initial_ddesc(dev, dd); 2368 if (err) { 2369 DPRINTFN(1, "get_initial_ddesc %ju", err, 0, 0, 0); 2370 goto bad; 2371 } 2372 2373 /* 4.8.2.1 */ 2374 if (USB_IS_SS(speed)) { 2375 if (dd->bMaxPacketSize != 9) { 2376 printf("%s: invalid mps 2^%u for SS ep0," 2377 " using 512\n", 2378 device_xname(sc->sc_dev), 2379 dd->bMaxPacketSize); 2380 dd->bMaxPacketSize = 9; 2381 } 2382 USETW(dev->ud_ep0desc.wMaxPacketSize, 2383 (1 << dd->bMaxPacketSize)); 2384 } else 2385 USETW(dev->ud_ep0desc.wMaxPacketSize, 2386 dd->bMaxPacketSize); 2387 DPRINTFN(4, "bMaxPacketSize %ju", dd->bMaxPacketSize, 0, 0, 0); 2388 err = xhci_update_ep0_mps(sc, xs, 2389 UGETW(dev->ud_ep0desc.wMaxPacketSize)); 2390 if (err) { 2391 DPRINTFN(1, "update mps of ep0 %ju", err, 0, 0, 0); 2392 goto bad; 2393 } 2394 2395 err = usbd_reload_device_desc(dev); 2396 if (err) { 2397 DPRINTFN(1, "reload desc %ju", err, 0, 0, 0); 2398 goto bad; 2399 } 2400 } 2401 2402 DPRINTFN(1, "adding unit addr=%jd, rev=%02jx,", 2403 dev->ud_addr, UGETW(dd->bcdUSB), 0, 0); 2404 DPRINTFN(1, " class=%jd, subclass=%jd, protocol=%jd,", 2405 dd->bDeviceClass, dd->bDeviceSubClass, 2406 dd->bDeviceProtocol, 0); 2407 DPRINTFN(1, " mps=%jd, len=%jd, noconf=%jd, speed=%jd", 2408 dd->bMaxPacketSize, dd->bLength, dd->bNumConfigurations, 2409 dev->ud_speed); 2410 2411 usbd_get_device_strings(dev); 2412 2413 usbd_add_dev_event(USB_EVENT_DEVICE_ATTACH, dev); 2414 2415 if (depth == 0 && port == 0) { 2416 usbd_attach_roothub(parent, dev); 2417 DPRINTFN(1, "root hub %#jx", (uintptr_t)dev, 0, 0, 0); 2418 return USBD_NORMAL_COMPLETION; 2419 } 2420 2421 err = usbd_probe_and_attach(parent, dev, port, dev->ud_addr); 2422 bad: 2423 if (err != USBD_NORMAL_COMPLETION) { 2424 usbd_remove_device(dev, up); 2425 } 2426 2427 return err; 2428 } 2429 2430 static usbd_status 2431 xhci_ring_init(struct xhci_softc * const sc, struct xhci_ring * const xr, 2432 size_t ntrb, size_t align) 2433 { 2434 usbd_status err; 2435 size_t size = ntrb * XHCI_TRB_SIZE; 2436 2437 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2438 2439 err = usb_allocmem(&sc->sc_bus, size, align, &xr->xr_dma); 2440 if (err) 2441 return err; 2442 mutex_init(&xr->xr_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 2443 xr->xr_cookies = kmem_zalloc(sizeof(*xr->xr_cookies) * ntrb, KM_SLEEP); 2444 xr->xr_trb = xhci_ring_trbv(xr, 0); 2445 xr->xr_ntrb = ntrb; 2446 xr->is_halted = false; 2447 xhci_host_dequeue(xr); 2448 2449 return USBD_NORMAL_COMPLETION; 2450 } 2451 2452 static void 2453 xhci_ring_free(struct xhci_softc * const sc, struct xhci_ring * const xr) 2454 { 2455 usb_freemem(&sc->sc_bus, &xr->xr_dma); 2456 mutex_destroy(&xr->xr_lock); 2457 kmem_free(xr->xr_cookies, sizeof(*xr->xr_cookies) * xr->xr_ntrb); 2458 } 2459 2460 static void 2461 xhci_ring_put(struct xhci_softc * const sc, struct xhci_ring * const xr, 2462 void *cookie, struct xhci_trb * const trbs, size_t ntrbs) 2463 { 2464 size_t i; 2465 u_int ri; 2466 u_int cs; 2467 uint64_t parameter; 2468 uint32_t status; 2469 uint32_t control; 2470 2471 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2472 2473 KASSERTMSG(ntrbs <= XHCI_XFER_NTRB, "ntrbs %zu", ntrbs); 2474 for (i = 0; i < ntrbs; i++) { 2475 DPRINTFN(12, "xr %#jx trbs %#jx num %ju", (uintptr_t)xr, 2476 (uintptr_t)trbs, i, 0); 2477 DPRINTFN(12, " %016jx %08jx %08jx", 2478 trbs[i].trb_0, trbs[i].trb_2, trbs[i].trb_3, 0); 2479 KASSERTMSG(XHCI_TRB_3_TYPE_GET(trbs[i].trb_3) != 2480 XHCI_TRB_TYPE_LINK, "trbs[%zu].trb3 %#x", i, trbs[i].trb_3); 2481 } 2482 2483 DPRINTFN(12, "%#jx xr_ep 0x%jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep, 2484 xr->xr_cs, 0); 2485 2486 ri = xr->xr_ep; 2487 cs = xr->xr_cs; 2488 2489 /* 2490 * Although the xhci hardware can do scatter/gather dma from 2491 * arbitrary sized buffers, there is a non-obvious restriction 2492 * that a LINK trb is only allowed at the end of a burst of 2493 * transfers - which might be 16kB. 2494 * Arbitrary aligned LINK trb definitely fail on Ivy bridge. 2495 * The simple solution is not to allow a LINK trb in the middle 2496 * of anything - as here. 2497 * XXX: (dsl) There are xhci controllers out there (eg some made by 2498 * ASMedia) that seem to lock up if they process a LINK trb but 2499 * cannot process the linked-to trb yet. 2500 * The code should write the 'cycle' bit on the link trb AFTER 2501 * adding the other trb. 2502 */ 2503 u_int firstep = xr->xr_ep; 2504 u_int firstcs = xr->xr_cs; 2505 2506 for (i = 0; i < ntrbs; ) { 2507 u_int oldri = ri; 2508 u_int oldcs = cs; 2509 2510 if (ri >= (xr->xr_ntrb - 1)) { 2511 /* Put Link TD at the end of ring */ 2512 parameter = xhci_ring_trbp(xr, 0); 2513 status = 0; 2514 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 2515 XHCI_TRB_3_TC_BIT; 2516 xr->xr_cookies[ri] = NULL; 2517 xr->xr_ep = 0; 2518 xr->xr_cs ^= 1; 2519 ri = xr->xr_ep; 2520 cs = xr->xr_cs; 2521 } else { 2522 parameter = trbs[i].trb_0; 2523 status = trbs[i].trb_2; 2524 control = trbs[i].trb_3; 2525 2526 xr->xr_cookies[ri] = cookie; 2527 ri++; 2528 i++; 2529 } 2530 /* 2531 * If this is a first TRB, mark it invalid to prevent 2532 * xHC from running it immediately. 2533 */ 2534 if (oldri == firstep) { 2535 if (oldcs) { 2536 control &= ~XHCI_TRB_3_CYCLE_BIT; 2537 } else { 2538 control |= XHCI_TRB_3_CYCLE_BIT; 2539 } 2540 } else { 2541 if (oldcs) { 2542 control |= XHCI_TRB_3_CYCLE_BIT; 2543 } else { 2544 control &= ~XHCI_TRB_3_CYCLE_BIT; 2545 } 2546 } 2547 xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control); 2548 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * oldri, 2549 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2550 } 2551 2552 /* Now invert cycle bit of first TRB */ 2553 if (firstcs) { 2554 xr->xr_trb[firstep].trb_3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 2555 } else { 2556 xr->xr_trb[firstep].trb_3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 2557 } 2558 usb_syncmem(&xr->xr_dma, XHCI_TRB_SIZE * firstep, 2559 XHCI_TRB_SIZE * 1, BUS_DMASYNC_PREWRITE); 2560 2561 xr->xr_ep = ri; 2562 xr->xr_cs = cs; 2563 2564 DPRINTFN(12, "%#jx xr_ep 0x%jx xr_cs %ju", (uintptr_t)xr, xr->xr_ep, 2565 xr->xr_cs, 0); 2566 } 2567 2568 /* 2569 * Stop execution commands, purge all commands on command ring, and 2570 * rewind dequeue pointer. 2571 */ 2572 static void 2573 xhci_abort_command(struct xhci_softc *sc) 2574 { 2575 struct xhci_ring * const cr = &sc->sc_cr; 2576 uint64_t crcr; 2577 int i; 2578 2579 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2580 DPRINTFN(14, "command %#jx timeout, aborting", 2581 sc->sc_command_addr, 0, 0, 0); 2582 2583 mutex_enter(&cr->xr_lock); 2584 2585 /* 4.6.1.2 Aborting a Command */ 2586 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2587 xhci_op_write_8(sc, XHCI_CRCR, crcr | XHCI_CRCR_LO_CA); 2588 2589 for (i = 0; i < 500; i++) { 2590 crcr = xhci_op_read_8(sc, XHCI_CRCR); 2591 if ((crcr & XHCI_CRCR_LO_CRR) == 0) 2592 break; 2593 usb_delay_ms(&sc->sc_bus, 1); 2594 } 2595 if ((crcr & XHCI_CRCR_LO_CRR) != 0) { 2596 DPRINTFN(1, "Command Abort timeout", 0, 0, 0, 0); 2597 /* reset HC here? */ 2598 } 2599 2600 /* reset command ring dequeue pointer */ 2601 cr->xr_ep = 0; 2602 cr->xr_cs = 1; 2603 xhci_op_write_8(sc, XHCI_CRCR, xhci_ring_trbp(cr, 0) | cr->xr_cs); 2604 2605 mutex_exit(&cr->xr_lock); 2606 } 2607 2608 /* 2609 * Put a command on command ring, ring bell, set timer, and cv_timedwait. 2610 * Command completion is notified by cv_signal from xhci_event_cmd() 2611 * (called from xhci_softint), or timed-out. 2612 * The completion code is copied to sc->sc_result_trb in xhci_event_cmd(), 2613 * then do_command examines it. 2614 */ 2615 static usbd_status 2616 xhci_do_command_locked(struct xhci_softc * const sc, 2617 struct xhci_trb * const trb, int timeout) 2618 { 2619 struct xhci_ring * const cr = &sc->sc_cr; 2620 usbd_status err; 2621 2622 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2623 DPRINTFN(12, "input: 0x%016jx 0x%08jx 0x%08jx", 2624 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2625 2626 KASSERTMSG(!cpu_intr_p() && !cpu_softintr_p(), "called from intr ctx"); 2627 KASSERT(mutex_owned(&sc->sc_lock)); 2628 2629 while (sc->sc_command_addr != 0) 2630 cv_wait(&sc->sc_cmdbusy_cv, &sc->sc_lock); 2631 2632 /* 2633 * If enqueue pointer points at last of ring, it's Link TRB, 2634 * command TRB will be stored in 0th TRB. 2635 */ 2636 if (cr->xr_ep == cr->xr_ntrb - 1) 2637 sc->sc_command_addr = xhci_ring_trbp(cr, 0); 2638 else 2639 sc->sc_command_addr = xhci_ring_trbp(cr, cr->xr_ep); 2640 2641 sc->sc_resultpending = true; 2642 2643 mutex_enter(&cr->xr_lock); 2644 xhci_ring_put(sc, cr, NULL, trb, 1); 2645 mutex_exit(&cr->xr_lock); 2646 2647 xhci_db_write_4(sc, XHCI_DOORBELL(0), 0); 2648 2649 while (sc->sc_resultpending) { 2650 if (cv_timedwait(&sc->sc_command_cv, &sc->sc_lock, 2651 MAX(1, mstohz(timeout))) == EWOULDBLOCK) { 2652 xhci_abort_command(sc); 2653 err = USBD_TIMEOUT; 2654 goto timedout; 2655 } 2656 } 2657 2658 trb->trb_0 = sc->sc_result_trb.trb_0; 2659 trb->trb_2 = sc->sc_result_trb.trb_2; 2660 trb->trb_3 = sc->sc_result_trb.trb_3; 2661 2662 DPRINTFN(12, "output: 0x%016jx 0x%08jx 0x%08jx", 2663 trb->trb_0, trb->trb_2, trb->trb_3, 0); 2664 2665 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) { 2666 case XHCI_TRB_ERROR_SUCCESS: 2667 err = USBD_NORMAL_COMPLETION; 2668 break; 2669 default: 2670 case 192 ... 223: 2671 err = USBD_IOERROR; 2672 break; 2673 case 224 ... 255: 2674 err = USBD_NORMAL_COMPLETION; 2675 break; 2676 } 2677 2678 timedout: 2679 sc->sc_resultpending = false; 2680 sc->sc_command_addr = 0; 2681 cv_broadcast(&sc->sc_cmdbusy_cv); 2682 2683 return err; 2684 } 2685 2686 static usbd_status 2687 xhci_do_command(struct xhci_softc * const sc, struct xhci_trb * const trb, 2688 int timeout) 2689 { 2690 2691 mutex_enter(&sc->sc_lock); 2692 usbd_status ret = xhci_do_command_locked(sc, trb, timeout); 2693 mutex_exit(&sc->sc_lock); 2694 2695 return ret; 2696 } 2697 2698 static usbd_status 2699 xhci_enable_slot(struct xhci_softc * const sc, uint8_t * const slotp) 2700 { 2701 struct xhci_trb trb; 2702 usbd_status err; 2703 2704 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2705 2706 trb.trb_0 = 0; 2707 trb.trb_2 = 0; 2708 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT); 2709 2710 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2711 if (err != USBD_NORMAL_COMPLETION) { 2712 return err; 2713 } 2714 2715 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3); 2716 2717 return err; 2718 } 2719 2720 /* 2721 * xHCI 4.6.4 2722 * Deallocate ring and device/input context DMA buffers, and disable_slot. 2723 * All endpoints in the slot should be stopped. 2724 * Should be called with sc_lock held. 2725 */ 2726 static usbd_status 2727 xhci_disable_slot(struct xhci_softc * const sc, uint8_t slot) 2728 { 2729 struct xhci_trb trb; 2730 struct xhci_slot *xs; 2731 usbd_status err; 2732 2733 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2734 2735 if (sc->sc_dying) 2736 return USBD_IOERROR; 2737 2738 trb.trb_0 = 0; 2739 trb.trb_2 = 0; 2740 trb.trb_3 = htole32( 2741 XHCI_TRB_3_SLOT_SET(slot) | 2742 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT)); 2743 2744 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT); 2745 2746 if (!err) { 2747 xs = &sc->sc_slots[slot]; 2748 if (xs->xs_idx != 0) { 2749 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, 32); 2750 xhci_set_dcba(sc, 0, slot); 2751 memset(xs, 0, sizeof(*xs)); 2752 } 2753 } 2754 2755 return err; 2756 } 2757 2758 /* 2759 * Set address of device and transition slot state from ENABLED to ADDRESSED 2760 * if Block Setaddress Request (BSR) is false. 2761 * If BSR==true, transition slot state from ENABLED to DEFAULT. 2762 * see xHCI 1.1 4.5.3, 3.3.4 2763 * Should be called without sc_lock held. 2764 */ 2765 static usbd_status 2766 xhci_address_device(struct xhci_softc * const sc, 2767 uint64_t icp, uint8_t slot_id, bool bsr) 2768 { 2769 struct xhci_trb trb; 2770 usbd_status err; 2771 2772 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2773 2774 trb.trb_0 = icp; 2775 trb.trb_2 = 0; 2776 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) | 2777 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 2778 (bsr ? XHCI_TRB_3_BSR_BIT : 0); 2779 2780 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2781 2782 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS) 2783 err = USBD_NO_ADDR; 2784 2785 return err; 2786 } 2787 2788 static usbd_status 2789 xhci_update_ep0_mps(struct xhci_softc * const sc, 2790 struct xhci_slot * const xs, u_int mps) 2791 { 2792 struct xhci_trb trb; 2793 usbd_status err; 2794 uint32_t * cp; 2795 2796 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2797 DPRINTFN(4, "slot %ju mps %ju", xs->xs_idx, mps, 0, 0); 2798 2799 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2800 cp[0] = htole32(0); 2801 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_EP_CONTROL)); 2802 2803 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_EP_CONTROL)); 2804 cp[1] = htole32(XHCI_EPCTX_1_MAXP_SIZE_SET(mps)); 2805 2806 /* sync input contexts before they are read from memory */ 2807 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 2808 HEXDUMP("input context", xhci_slot_get_icv(sc, xs, 0), 2809 sc->sc_ctxsz * 4); 2810 2811 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0); 2812 trb.trb_2 = 0; 2813 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) | 2814 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX); 2815 2816 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT); 2817 return err; 2818 } 2819 2820 static void 2821 xhci_set_dcba(struct xhci_softc * const sc, uint64_t dcba, int si) 2822 { 2823 uint64_t * const dcbaa = KERNADDR(&sc->sc_dcbaa_dma, 0); 2824 2825 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2826 DPRINTFN(4, "dcbaa %#jx dc %016jx slot %jd", 2827 (uintptr_t)&dcbaa[si], dcba, si, 0); 2828 2829 dcbaa[si] = htole64(dcba); 2830 usb_syncmem(&sc->sc_dcbaa_dma, si * sizeof(uint64_t), sizeof(uint64_t), 2831 BUS_DMASYNC_PREWRITE); 2832 } 2833 2834 /* 2835 * Allocate device and input context DMA buffer, and 2836 * TRB DMA buffer for each endpoint. 2837 */ 2838 static usbd_status 2839 xhci_init_slot(struct usbd_device *dev, uint32_t slot) 2840 { 2841 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2842 struct xhci_slot *xs; 2843 usbd_status err; 2844 u_int dci; 2845 2846 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2847 DPRINTFN(4, "slot %ju", slot, 0, 0, 0); 2848 2849 xs = &sc->sc_slots[slot]; 2850 2851 /* allocate contexts */ 2852 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2853 &xs->xs_dc_dma); 2854 if (err) 2855 return err; 2856 memset(KERNADDR(&xs->xs_dc_dma, 0), 0, sc->sc_pgsz); 2857 2858 err = usb_allocmem(&sc->sc_bus, sc->sc_pgsz, sc->sc_pgsz, 2859 &xs->xs_ic_dma); 2860 if (err) 2861 goto bad1; 2862 memset(KERNADDR(&xs->xs_ic_dma, 0), 0, sc->sc_pgsz); 2863 2864 for (dci = 0; dci < 32; dci++) { 2865 //CTASSERT(sizeof(xs->xs_ep[dci]) == sizeof(struct xhci_endpoint)); 2866 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2867 if (dci == XHCI_DCI_SLOT) 2868 continue; 2869 err = xhci_ring_init(sc, &xs->xs_ep[dci].xe_tr, 2870 XHCI_TRANSFER_RING_TRBS, XHCI_TRB_ALIGN); 2871 if (err) { 2872 DPRINTFN(0, "ring init failure", 0, 0, 0, 0); 2873 goto bad2; 2874 } 2875 } 2876 2877 bad2: 2878 if (err == USBD_NORMAL_COMPLETION) { 2879 xs->xs_idx = slot; 2880 } else { 2881 xhci_free_slot(sc, xs, XHCI_DCI_SLOT + 1, dci); 2882 } 2883 2884 return err; 2885 2886 bad1: 2887 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2888 xs->xs_idx = 0; 2889 return err; 2890 } 2891 2892 static void 2893 xhci_free_slot(struct xhci_softc *sc, struct xhci_slot *xs, int start_dci, 2894 int end_dci) 2895 { 2896 u_int dci; 2897 2898 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2899 DPRINTFN(4, "slot %ju start %ju end %ju", xs->xs_idx, start_dci, 2900 end_dci, 0); 2901 2902 for (dci = start_dci; dci < end_dci; dci++) { 2903 xhci_ring_free(sc, &xs->xs_ep[dci].xe_tr); 2904 memset(&xs->xs_ep[dci], 0, sizeof(xs->xs_ep[dci])); 2905 } 2906 usb_freemem(&sc->sc_bus, &xs->xs_ic_dma); 2907 usb_freemem(&sc->sc_bus, &xs->xs_dc_dma); 2908 xs->xs_idx = 0; 2909 } 2910 2911 /* 2912 * Setup slot context, set Device Context Base Address, and issue 2913 * Set Address Device command. 2914 */ 2915 static usbd_status 2916 xhci_set_address(struct usbd_device *dev, uint32_t slot, bool bsr) 2917 { 2918 struct xhci_softc * const sc = XHCI_BUS2SC(dev->ud_bus); 2919 struct xhci_slot *xs; 2920 usbd_status err; 2921 2922 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2923 DPRINTFN(4, "slot %ju bsr %ju", slot, bsr, 0, 0); 2924 2925 xs = &sc->sc_slots[slot]; 2926 2927 xhci_setup_ctx(dev->ud_pipe0); 2928 2929 HEXDUMP("input context", xhci_slot_get_icv(sc, xs, 0), 2930 sc->sc_ctxsz * 3); 2931 2932 xhci_set_dcba(sc, DMAADDR(&xs->xs_dc_dma, 0), slot); 2933 2934 err = xhci_address_device(sc, xhci_slot_get_icp(sc, xs, 0), slot, bsr); 2935 2936 usb_syncmem(&xs->xs_dc_dma, 0, sc->sc_pgsz, BUS_DMASYNC_POSTREAD); 2937 HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, 0), 2938 sc->sc_ctxsz * 2); 2939 2940 return err; 2941 } 2942 2943 /* 2944 * 4.8.2, 6.2.3.2 2945 * construct slot/endpoint context parameters and do syncmem 2946 */ 2947 static void 2948 xhci_setup_ctx(struct usbd_pipe *pipe) 2949 { 2950 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 2951 struct usbd_device *dev = pipe->up_dev; 2952 struct xhci_slot * const xs = dev->ud_hcpriv; 2953 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 2954 const u_int dci = xhci_ep_get_dci(ed); 2955 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 2956 uint32_t *cp; 2957 uint16_t mps = UGETW(ed->wMaxPacketSize); 2958 uint8_t speed = dev->ud_speed; 2959 uint8_t ival = ed->bInterval; 2960 2961 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 2962 DPRINTFN(4, "pipe %#jx: slot %ju dci %ju speed %ju", 2963 (uintptr_t)pipe, xs->xs_idx, dci, speed); 2964 2965 /* set up initial input control context */ 2966 cp = xhci_slot_get_icv(sc, xs, XHCI_ICI_INPUT_CONTROL); 2967 cp[0] = htole32(0); 2968 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci)); 2969 cp[1] |= htole32(XHCI_INCTX_1_ADD_MASK(XHCI_DCI_SLOT)); 2970 cp[7] = htole32(0); 2971 2972 /* set up input slot context */ 2973 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(XHCI_DCI_SLOT)); 2974 cp[0] = 2975 XHCI_SCTX_0_CTX_NUM_SET(dci) | 2976 XHCI_SCTX_0_SPEED_SET(xhci_speed2xspeed(speed)); 2977 cp[1] = 0; 2978 cp[2] = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2979 cp[3] = 0; 2980 xhci_setup_route(pipe, cp); 2981 xhci_setup_tthub(pipe, cp); 2982 2983 cp[0] = htole32(cp[0]); 2984 cp[1] = htole32(cp[1]); 2985 cp[2] = htole32(cp[2]); 2986 cp[3] = htole32(cp[3]); 2987 2988 /* set up input endpoint context */ 2989 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci)); 2990 cp[0] = 2991 XHCI_EPCTX_0_EPSTATE_SET(0) | 2992 XHCI_EPCTX_0_MULT_SET(0) | 2993 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2994 XHCI_EPCTX_0_LSA_SET(0) | 2995 XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(0); 2996 cp[1] = 2997 XHCI_EPCTX_1_EPTYPE_SET(xhci_ep_get_type(ed)) | 2998 XHCI_EPCTX_1_HID_SET(0) | 2999 XHCI_EPCTX_1_MAXB_SET(0); 3000 3001 if (xfertype != UE_ISOCHRONOUS) 3002 cp[1] |= XHCI_EPCTX_1_CERR_SET(3); 3003 3004 if (xfertype == UE_CONTROL) 3005 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); /* 6.2.3 */ 3006 else if (USB_IS_SS(speed)) 3007 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(mps); 3008 else 3009 cp[4] = XHCI_EPCTX_4_AVG_TRB_LEN_SET(UE_GET_SIZE(mps)); 3010 3011 xhci_setup_maxburst(pipe, cp); 3012 3013 switch (xfertype) { 3014 case UE_CONTROL: 3015 break; 3016 case UE_BULK: 3017 /* XXX Set MaxPStreams, HID, and LSA if streams enabled */ 3018 break; 3019 case UE_INTERRUPT: 3020 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3021 ival = pipe->up_interval; 3022 3023 ival = xhci_bival2ival(ival, speed); 3024 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3025 break; 3026 case UE_ISOCHRONOUS: 3027 if (pipe->up_interval != USBD_DEFAULT_INTERVAL) 3028 ival = pipe->up_interval; 3029 3030 /* xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 */ 3031 if (speed == USB_SPEED_FULL) 3032 ival += 3; /* 1ms -> 125us */ 3033 ival--; 3034 cp[0] |= XHCI_EPCTX_0_IVAL_SET(ival); 3035 break; 3036 default: 3037 break; 3038 } 3039 DPRINTFN(4, "setting ival %ju MaxBurst %#jx", 3040 XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_1_MAXB_GET(cp[1]), 0, 0); 3041 3042 /* rewind TR dequeue pointer in xHC */ 3043 /* can't use xhci_ep_get_dci() yet? */ 3044 *(uint64_t *)(&cp[2]) = htole64( 3045 xhci_ring_trbp(&xs->xs_ep[dci].xe_tr, 0) | 3046 XHCI_EPCTX_2_DCS_SET(1)); 3047 3048 cp[0] = htole32(cp[0]); 3049 cp[1] = htole32(cp[1]); 3050 cp[4] = htole32(cp[4]); 3051 3052 /* rewind TR dequeue pointer in driver */ 3053 struct xhci_ring *xr = &xs->xs_ep[dci].xe_tr; 3054 mutex_enter(&xr->xr_lock); 3055 xhci_host_dequeue(xr); 3056 mutex_exit(&xr->xr_lock); 3057 3058 /* sync input contexts before they are read from memory */ 3059 usb_syncmem(&xs->xs_ic_dma, 0, sc->sc_pgsz, BUS_DMASYNC_PREWRITE); 3060 } 3061 3062 /* 3063 * Setup route string and roothub port of given device for slot context 3064 */ 3065 static void 3066 xhci_setup_route(struct usbd_pipe *pipe, uint32_t *cp) 3067 { 3068 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3069 struct usbd_device *dev = pipe->up_dev; 3070 struct usbd_port *up = dev->ud_powersrc; 3071 struct usbd_device *hub; 3072 struct usbd_device *adev; 3073 uint8_t rhport = 0; 3074 uint32_t route = 0; 3075 3076 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3077 3078 /* Locate root hub port and Determine route string */ 3079 /* 4.3.3 route string does not include roothub port */ 3080 for (hub = dev; hub != NULL; hub = hub->ud_myhub) { 3081 uint32_t dep; 3082 3083 DPRINTFN(4, "hub %#jx depth %jd upport %jp upportno %jd", 3084 (uintptr_t)hub, hub->ud_depth, (uintptr_t)hub->ud_powersrc, 3085 hub->ud_powersrc ? (uintptr_t)hub->ud_powersrc->up_portno : 3086 -1); 3087 3088 if (hub->ud_powersrc == NULL) 3089 break; 3090 dep = hub->ud_depth; 3091 if (dep == 0) 3092 break; 3093 rhport = hub->ud_powersrc->up_portno; 3094 if (dep > USB_HUB_MAX_DEPTH) 3095 continue; 3096 3097 route |= 3098 (rhport > UHD_SS_NPORTS_MAX ? UHD_SS_NPORTS_MAX : rhport) 3099 << ((dep - 1) * 4); 3100 } 3101 route = route >> 4; 3102 size_t bn = hub == sc->sc_bus.ub_roothub ? 0 : 1; 3103 3104 /* Locate port on upstream high speed hub */ 3105 for (adev = dev, hub = up->up_parent; 3106 hub != NULL && hub->ud_speed != USB_SPEED_HIGH; 3107 adev = hub, hub = hub->ud_myhub) 3108 ; 3109 if (hub) { 3110 int p; 3111 for (p = 0; p < hub->ud_hub->uh_hubdesc.bNbrPorts; p++) { 3112 if (hub->ud_hub->uh_ports[p].up_dev == adev) { 3113 dev->ud_myhsport = &hub->ud_hub->uh_ports[p]; 3114 goto found; 3115 } 3116 } 3117 panic("%s: cannot find HS port", __func__); 3118 found: 3119 DPRINTFN(4, "high speed port %jd", p, 0, 0, 0); 3120 } else { 3121 dev->ud_myhsport = NULL; 3122 } 3123 3124 const size_t ctlrport = xhci_rhport2ctlrport(sc, bn, rhport); 3125 3126 DPRINTFN(4, "rhport %ju ctlrport %ju Route %05jx hub %#jx", rhport, 3127 ctlrport, route, (uintptr_t)hub); 3128 3129 cp[0] |= XHCI_SCTX_0_ROUTE_SET(route); 3130 cp[1] |= XHCI_SCTX_1_RH_PORT_SET(ctlrport); 3131 } 3132 3133 /* 3134 * Setup whether device is hub, whether device uses MTT, and 3135 * TT informations if it uses MTT. 3136 */ 3137 static void 3138 xhci_setup_tthub(struct usbd_pipe *pipe, uint32_t *cp) 3139 { 3140 struct usbd_device *dev = pipe->up_dev; 3141 struct usbd_port *myhsport = dev->ud_myhsport; 3142 usb_device_descriptor_t * const dd = &dev->ud_ddesc; 3143 uint32_t speed = dev->ud_speed; 3144 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 3145 uint8_t tthubslot, ttportnum; 3146 bool ishub; 3147 bool usemtt; 3148 3149 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3150 3151 /* 3152 * 6.2.2, Table 57-60, 6.2.2.1, 6.2.2.2 3153 * tthubslot: 3154 * This is the slot ID of parent HS hub 3155 * if LS/FS device is connected && connected through HS hub. 3156 * This is 0 if device is not LS/FS device || 3157 * parent hub is not HS hub || 3158 * attached to root hub. 3159 * ttportnum: 3160 * This is the downstream facing port of parent HS hub 3161 * if LS/FS device is connected. 3162 * This is 0 if device is not LS/FS device || 3163 * parent hub is not HS hub || 3164 * attached to root hub. 3165 */ 3166 if (myhsport && 3167 myhsport->up_parent->ud_addr != rhaddr && 3168 (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL)) { 3169 ttportnum = myhsport->up_portno; 3170 tthubslot = myhsport->up_parent->ud_addr; 3171 } else { 3172 ttportnum = 0; 3173 tthubslot = 0; 3174 } 3175 DPRINTFN(4, "myhsport %#jx ttportnum=%jd tthubslot=%jd", 3176 (uintptr_t)myhsport, ttportnum, tthubslot, 0); 3177 3178 /* ishub is valid after reading UDESC_DEVICE */ 3179 ishub = (dd->bDeviceClass == UDCLASS_HUB); 3180 3181 /* dev->ud_hub is valid after reading UDESC_HUB */ 3182 if (ishub && dev->ud_hub) { 3183 usb_hub_descriptor_t *hd = &dev->ud_hub->uh_hubdesc; 3184 uint8_t ttt = 3185 __SHIFTOUT(UGETW(hd->wHubCharacteristics), UHD_TT_THINK); 3186 3187 cp[1] |= XHCI_SCTX_1_NUM_PORTS_SET(hd->bNbrPorts); 3188 cp[2] |= XHCI_SCTX_2_TT_THINK_TIME_SET(ttt); 3189 DPRINTFN(4, "nports=%jd ttt=%jd", hd->bNbrPorts, ttt, 0, 0); 3190 } 3191 3192 #define IS_MTTHUB(dd) \ 3193 ((dd)->bDeviceProtocol == UDPROTO_HSHUBMTT) 3194 3195 /* 3196 * MTT flag is set if 3197 * 1. this is HS hub && MTTs are supported and enabled; or 3198 * 2. this is LS or FS device && there is a parent HS hub where MTTs 3199 * are supported and enabled. 3200 * 3201 * XXX enabled is not tested yet 3202 */ 3203 if (ishub && speed == USB_SPEED_HIGH && IS_MTTHUB(dd)) 3204 usemtt = true; 3205 else if ((speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) && 3206 myhsport && 3207 myhsport->up_parent->ud_addr != rhaddr && 3208 IS_MTTHUB(&myhsport->up_parent->ud_ddesc)) 3209 usemtt = true; 3210 else 3211 usemtt = false; 3212 DPRINTFN(4, "class %ju proto %ju ishub %jd usemtt %jd", 3213 dd->bDeviceClass, dd->bDeviceProtocol, ishub, usemtt); 3214 3215 #undef IS_MTTHUB 3216 3217 cp[0] |= 3218 XHCI_SCTX_0_HUB_SET(ishub ? 1 : 0) | 3219 XHCI_SCTX_0_MTT_SET(usemtt ? 1 : 0); 3220 cp[2] |= 3221 XHCI_SCTX_2_TT_HUB_SID_SET(tthubslot) | 3222 XHCI_SCTX_2_TT_PORT_NUM_SET(ttportnum); 3223 } 3224 3225 /* set up params for periodic endpoint */ 3226 static void 3227 xhci_setup_maxburst(struct usbd_pipe *pipe, uint32_t *cp) 3228 { 3229 struct usbd_device *dev = pipe->up_dev; 3230 usb_endpoint_descriptor_t * const ed = pipe->up_endpoint->ue_edesc; 3231 const uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 3232 usbd_desc_iter_t iter; 3233 const usb_cdc_descriptor_t *cdcd; 3234 uint32_t maxb = 0; 3235 uint16_t mps = UGETW(ed->wMaxPacketSize); 3236 uint8_t speed = dev->ud_speed; 3237 uint8_t ep; 3238 3239 /* config desc is NULL when opening ep0 */ 3240 if (dev == NULL || dev->ud_cdesc == NULL) 3241 goto no_cdcd; 3242 cdcd = (const usb_cdc_descriptor_t *)usb_find_desc(dev, 3243 UDESC_INTERFACE, USBD_CDCSUBTYPE_ANY); 3244 if (cdcd == NULL) 3245 goto no_cdcd; 3246 usb_desc_iter_init(dev, &iter); 3247 iter.cur = (const void *)cdcd; 3248 3249 /* find endpoint_ss_comp desc for ep of this pipe */ 3250 for (ep = 0;;) { 3251 cdcd = (const usb_cdc_descriptor_t *)usb_desc_iter_next(&iter); 3252 if (cdcd == NULL) 3253 break; 3254 if (ep == 0 && cdcd->bDescriptorType == UDESC_ENDPOINT) { 3255 ep = ((const usb_endpoint_descriptor_t *)cdcd)-> 3256 bEndpointAddress; 3257 if (UE_GET_ADDR(ep) == 3258 UE_GET_ADDR(ed->bEndpointAddress)) { 3259 cdcd = (const usb_cdc_descriptor_t *) 3260 usb_desc_iter_next(&iter); 3261 break; 3262 } 3263 ep = 0; 3264 } 3265 } 3266 if (cdcd != NULL && cdcd->bDescriptorType == UDESC_ENDPOINT_SS_COMP) { 3267 const usb_endpoint_ss_comp_descriptor_t * esscd = 3268 (const usb_endpoint_ss_comp_descriptor_t *)cdcd; 3269 maxb = esscd->bMaxBurst; 3270 } 3271 3272 no_cdcd: 3273 /* 6.2.3.4, 4.8.2.4 */ 3274 if (USB_IS_SS(speed)) { 3275 /* USB 3.1 9.6.6 */ 3276 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(mps); 3277 /* USB 3.1 9.6.7 */ 3278 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3279 #ifdef notyet 3280 if (xfertype == UE_ISOCHRONOUS) { 3281 } 3282 if (XHCI_HCC2_LEC(sc->sc_hcc2) != 0) { 3283 /* use ESIT */ 3284 cp[4] |= XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x); 3285 cp[0] |= XHCI_EPCTX_0_MAX_ESIT_PAYLOAD_HI_SET(x); 3286 3287 /* XXX if LEC = 1, set ESIT instead */ 3288 cp[0] |= XHCI_EPCTX_0_MULT_SET(0); 3289 } else { 3290 /* use ival */ 3291 } 3292 #endif 3293 } else { 3294 /* USB 2.0 9.6.6 */ 3295 cp[1] |= XHCI_EPCTX_1_MAXP_SIZE_SET(UE_GET_SIZE(mps)); 3296 3297 /* 6.2.3.4 */ 3298 if (speed == USB_SPEED_HIGH && 3299 (xfertype == UE_ISOCHRONOUS || xfertype == UE_INTERRUPT)) { 3300 maxb = UE_GET_TRANS(mps); 3301 } else { 3302 /* LS/FS or HS CTRL or HS BULK */ 3303 maxb = 0; 3304 } 3305 cp[1] |= XHCI_EPCTX_1_MAXB_SET(maxb); 3306 } 3307 } 3308 3309 /* 3310 * Convert endpoint bInterval value to endpoint context interval value 3311 * for Interrupt pipe. 3312 * xHCI 6.2.3.6 Table 65, USB 2.0 9.6.6 3313 */ 3314 static uint32_t 3315 xhci_bival2ival(uint32_t ival, uint32_t speed) 3316 { 3317 if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) { 3318 int i; 3319 3320 /* 3321 * round ival down to "the nearest base 2 multiple of 3322 * bInterval * 8". 3323 * bInterval is at most 255 as its type is uByte. 3324 * 255(ms) = 2040(x 125us) < 2^11, so start with 10. 3325 */ 3326 for (i = 10; i > 0; i--) { 3327 if ((ival * 8) >= (1 << i)) 3328 break; 3329 } 3330 ival = i; 3331 } else { 3332 /* Interval = bInterval-1 for SS/HS */ 3333 ival--; 3334 } 3335 3336 return ival; 3337 } 3338 3339 /* ----- */ 3340 3341 static void 3342 xhci_noop(struct usbd_pipe *pipe) 3343 { 3344 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3345 } 3346 3347 /* 3348 * Process root hub request. 3349 */ 3350 static int 3351 xhci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 3352 void *buf, int buflen) 3353 { 3354 struct xhci_softc * const sc = XHCI_BUS2SC(bus); 3355 usb_port_status_t ps; 3356 int l, totlen = 0; 3357 uint16_t len, value, index; 3358 int port, i; 3359 uint32_t v; 3360 3361 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3362 3363 if (sc->sc_dying) 3364 return -1; 3365 3366 size_t bn = bus == &sc->sc_bus ? 0 : 1; 3367 3368 len = UGETW(req->wLength); 3369 value = UGETW(req->wValue); 3370 index = UGETW(req->wIndex); 3371 3372 DPRINTFN(12, "rhreq: %04jx %04jx %04jx %04jx", 3373 req->bmRequestType | (req->bRequest << 8), value, index, len); 3374 3375 #define C(x,y) ((x) | ((y) << 8)) 3376 switch (C(req->bRequest, req->bmRequestType)) { 3377 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3378 DPRINTFN(8, "getdesc: wValue=0x%04jx", value, 0, 0, 0); 3379 if (len == 0) 3380 break; 3381 switch (value) { 3382 #define sd ((usb_string_descriptor_t *)buf) 3383 case C(2, UDESC_STRING): 3384 /* Product */ 3385 totlen = usb_makestrdesc(sd, len, "xHCI Root Hub"); 3386 break; 3387 #undef sd 3388 default: 3389 /* default from usbroothub */ 3390 return buflen; 3391 } 3392 break; 3393 3394 /* Hub requests */ 3395 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3396 break; 3397 /* Clear Port Feature request */ 3398 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): { 3399 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3400 3401 DPRINTFN(4, "UR_CLEAR_PORT_FEAT bp=%jd feat=%jd bus=%jd cp=%jd", 3402 index, value, bn, cp); 3403 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3404 return -1; 3405 } 3406 port = XHCI_PORTSC(cp); 3407 v = xhci_op_read_4(sc, port); 3408 DPRINTFN(4, "portsc=0x%08jx", v, 0, 0, 0); 3409 v &= ~XHCI_PS_CLEAR; 3410 switch (value) { 3411 case UHF_PORT_ENABLE: 3412 xhci_op_write_4(sc, port, v & ~XHCI_PS_PED); 3413 break; 3414 case UHF_PORT_SUSPEND: 3415 return -1; 3416 case UHF_PORT_POWER: 3417 break; 3418 case UHF_PORT_TEST: 3419 case UHF_PORT_INDICATOR: 3420 return -1; 3421 case UHF_C_PORT_CONNECTION: 3422 xhci_op_write_4(sc, port, v | XHCI_PS_CSC); 3423 break; 3424 case UHF_C_PORT_ENABLE: 3425 case UHF_C_PORT_SUSPEND: 3426 case UHF_C_PORT_OVER_CURRENT: 3427 return -1; 3428 case UHF_C_BH_PORT_RESET: 3429 xhci_op_write_4(sc, port, v | XHCI_PS_WRC); 3430 break; 3431 case UHF_C_PORT_RESET: 3432 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3433 break; 3434 case UHF_C_PORT_LINK_STATE: 3435 xhci_op_write_4(sc, port, v | XHCI_PS_PLC); 3436 break; 3437 case UHF_C_PORT_CONFIG_ERROR: 3438 xhci_op_write_4(sc, port, v | XHCI_PS_CEC); 3439 break; 3440 default: 3441 return -1; 3442 } 3443 break; 3444 } 3445 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3446 if (len == 0) 3447 break; 3448 if ((value & 0xff) != 0) { 3449 return -1; 3450 } 3451 usb_hub_descriptor_t hubd; 3452 3453 totlen = min(buflen, sizeof(hubd)); 3454 memcpy(&hubd, buf, totlen); 3455 hubd.bNbrPorts = sc->sc_rhportcount[bn]; 3456 USETW(hubd.wHubCharacteristics, UHD_PWR_NO_SWITCH); 3457 hubd.bPwrOn2PwrGood = 200; 3458 for (i = 0, l = sc->sc_rhportcount[bn]; l > 0; i++, l -= 8) { 3459 /* XXX can't find out? */ 3460 hubd.DeviceRemovable[i++] = 0; 3461 } 3462 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3463 totlen = min(totlen, hubd.bDescLength); 3464 memcpy(buf, &hubd, totlen); 3465 break; 3466 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3467 if (len != 4) { 3468 return -1; 3469 } 3470 memset(buf, 0, len); /* ? XXX */ 3471 totlen = len; 3472 break; 3473 /* Get Port Status request */ 3474 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): { 3475 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3476 3477 DPRINTFN(8, "get port status bn=%jd i=%jd cp=%ju", 3478 bn, index, cp, 0); 3479 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3480 return -1; 3481 } 3482 if (len != 4) { 3483 return -1; 3484 } 3485 v = xhci_op_read_4(sc, XHCI_PORTSC(cp)); 3486 DPRINTFN(4, "getrhportsc %jd %08jx", cp, v, 0, 0); 3487 i = xhci_xspeed2psspeed(XHCI_PS_SPEED_GET(v)); 3488 if (v & XHCI_PS_CCS) i |= UPS_CURRENT_CONNECT_STATUS; 3489 if (v & XHCI_PS_PED) i |= UPS_PORT_ENABLED; 3490 if (v & XHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 3491 //if (v & XHCI_PS_SUSP) i |= UPS_SUSPEND; 3492 if (v & XHCI_PS_PR) i |= UPS_RESET; 3493 if (v & XHCI_PS_PP) { 3494 if (i & UPS_OTHER_SPEED) 3495 i |= UPS_PORT_POWER_SS; 3496 else 3497 i |= UPS_PORT_POWER; 3498 } 3499 if (i & UPS_OTHER_SPEED) 3500 i |= UPS_PORT_LS_SET(XHCI_PS_PLS_GET(v)); 3501 if (sc->sc_vendor_port_status) 3502 i = sc->sc_vendor_port_status(sc, v, i); 3503 USETW(ps.wPortStatus, i); 3504 i = 0; 3505 if (v & XHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 3506 if (v & XHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 3507 if (v & XHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 3508 if (v & XHCI_PS_PRC) i |= UPS_C_PORT_RESET; 3509 if (v & XHCI_PS_WRC) i |= UPS_C_BH_PORT_RESET; 3510 if (v & XHCI_PS_PLC) i |= UPS_C_PORT_LINK_STATE; 3511 if (v & XHCI_PS_CEC) i |= UPS_C_PORT_CONFIG_ERROR; 3512 USETW(ps.wPortChange, i); 3513 totlen = min(len, sizeof(ps)); 3514 memcpy(buf, &ps, totlen); 3515 break; 3516 } 3517 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3518 return -1; 3519 case C(UR_SET_HUB_DEPTH, UT_WRITE_CLASS_DEVICE): 3520 break; 3521 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3522 break; 3523 /* Set Port Feature request */ 3524 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): { 3525 int optval = (index >> 8) & 0xff; 3526 index &= 0xff; 3527 if (index < 1 || index > sc->sc_rhportcount[bn]) { 3528 return -1; 3529 } 3530 3531 const size_t cp = xhci_rhport2ctlrport(sc, bn, index); 3532 3533 port = XHCI_PORTSC(cp); 3534 v = xhci_op_read_4(sc, port); 3535 DPRINTFN(4, "index %jd cp %jd portsc=0x%08jx", index, cp, v, 0); 3536 v &= ~XHCI_PS_CLEAR; 3537 switch (value) { 3538 case UHF_PORT_ENABLE: 3539 xhci_op_write_4(sc, port, v | XHCI_PS_PED); 3540 break; 3541 case UHF_PORT_SUSPEND: 3542 /* XXX suspend */ 3543 break; 3544 case UHF_PORT_RESET: 3545 v &= ~(XHCI_PS_PED | XHCI_PS_PR); 3546 xhci_op_write_4(sc, port, v | XHCI_PS_PR); 3547 /* Wait for reset to complete. */ 3548 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 3549 if (sc->sc_dying) { 3550 return -1; 3551 } 3552 v = xhci_op_read_4(sc, port); 3553 if (v & XHCI_PS_PR) { 3554 xhci_op_write_4(sc, port, v & ~XHCI_PS_PR); 3555 usb_delay_ms(&sc->sc_bus, 10); 3556 /* XXX */ 3557 } 3558 break; 3559 case UHF_PORT_POWER: 3560 /* XXX power control */ 3561 break; 3562 /* XXX more */ 3563 case UHF_C_PORT_RESET: 3564 xhci_op_write_4(sc, port, v | XHCI_PS_PRC); 3565 break; 3566 case UHF_PORT_U1_TIMEOUT: 3567 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3568 return -1; 3569 } 3570 port = XHCI_PORTPMSC(cp); 3571 v = xhci_op_read_4(sc, port); 3572 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 3573 index, cp, v, 0); 3574 v &= ~XHCI_PM3_U1TO_SET(0xff); 3575 v |= XHCI_PM3_U1TO_SET(optval); 3576 xhci_op_write_4(sc, port, v); 3577 break; 3578 case UHF_PORT_U2_TIMEOUT: 3579 if (XHCI_PS_SPEED_GET(v) < XHCI_PS_SPEED_SS) { 3580 return -1; 3581 } 3582 port = XHCI_PORTPMSC(cp); 3583 v = xhci_op_read_4(sc, port); 3584 DPRINTFN(4, "index %jd cp %jd portpmsc=0x%08jx", 3585 index, cp, v, 0); 3586 v &= ~XHCI_PM3_U2TO_SET(0xff); 3587 v |= XHCI_PM3_U2TO_SET(optval); 3588 xhci_op_write_4(sc, port, v); 3589 break; 3590 default: 3591 return -1; 3592 } 3593 } 3594 break; 3595 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3596 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3597 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3598 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3599 break; 3600 default: 3601 /* default from usbroothub */ 3602 return buflen; 3603 } 3604 3605 return totlen; 3606 } 3607 3608 /* root hub interrupt */ 3609 3610 static usbd_status 3611 xhci_root_intr_transfer(struct usbd_xfer *xfer) 3612 { 3613 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3614 usbd_status err; 3615 3616 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3617 3618 /* Insert last in queue. */ 3619 mutex_enter(&sc->sc_lock); 3620 err = usb_insert_transfer(xfer); 3621 mutex_exit(&sc->sc_lock); 3622 if (err) 3623 return err; 3624 3625 /* Pipe isn't running, start first */ 3626 return xhci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3627 } 3628 3629 /* Wait for roothub port status/change */ 3630 static usbd_status 3631 xhci_root_intr_start(struct usbd_xfer *xfer) 3632 { 3633 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3634 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3635 3636 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3637 3638 if (sc->sc_dying) 3639 return USBD_IOERROR; 3640 3641 mutex_enter(&sc->sc_lock); 3642 sc->sc_intrxfer[bn] = xfer; 3643 mutex_exit(&sc->sc_lock); 3644 3645 return USBD_IN_PROGRESS; 3646 } 3647 3648 static void 3649 xhci_root_intr_abort(struct usbd_xfer *xfer) 3650 { 3651 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 3652 3653 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3654 3655 KASSERT(mutex_owned(&sc->sc_lock)); 3656 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3657 3658 xfer->ux_status = USBD_CANCELLED; 3659 usb_transfer_complete(xfer); 3660 } 3661 3662 static void 3663 xhci_root_intr_close(struct usbd_pipe *pipe) 3664 { 3665 struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 3666 const struct usbd_xfer *xfer = pipe->up_intrxfer; 3667 const size_t bn = XHCI_XFER2BUS(xfer) == &sc->sc_bus ? 0 : 1; 3668 3669 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3670 3671 KASSERT(mutex_owned(&sc->sc_lock)); 3672 3673 sc->sc_intrxfer[bn] = NULL; 3674 } 3675 3676 static void 3677 xhci_root_intr_done(struct usbd_xfer *xfer) 3678 { 3679 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3680 3681 } 3682 3683 /* -------------- */ 3684 /* device control */ 3685 3686 static usbd_status 3687 xhci_device_ctrl_transfer(struct usbd_xfer *xfer) 3688 { 3689 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3690 usbd_status err; 3691 3692 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3693 3694 /* Insert last in queue. */ 3695 mutex_enter(&sc->sc_lock); 3696 err = usb_insert_transfer(xfer); 3697 mutex_exit(&sc->sc_lock); 3698 if (err) 3699 return err; 3700 3701 /* Pipe isn't running, start first */ 3702 return xhci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3703 } 3704 3705 static usbd_status 3706 xhci_device_ctrl_start(struct usbd_xfer *xfer) 3707 { 3708 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3709 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3710 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3711 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3712 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3713 usb_device_request_t * const req = &xfer->ux_request; 3714 const int isread = usbd_xfer_isread(xfer); 3715 const uint32_t len = UGETW(req->wLength); 3716 usb_dma_t * const dma = &xfer->ux_dmabuf; 3717 uint64_t parameter; 3718 uint32_t status; 3719 uint32_t control; 3720 u_int i; 3721 3722 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3723 DPRINTFN(12, "req: %04jx %04jx %04jx %04jx", 3724 req->bmRequestType | (req->bRequest << 8), UGETW(req->wValue), 3725 UGETW(req->wIndex), UGETW(req->wLength)); 3726 3727 /* we rely on the bottom bits for extra info */ 3728 KASSERTMSG(((uintptr_t)xfer & 0x3) == 0x0, "xfer %zx", 3729 (uintptr_t) xfer); 3730 3731 KASSERT((xfer->ux_rqflags & URQ_REQUEST) != 0); 3732 3733 i = 0; 3734 3735 /* setup phase */ 3736 memcpy(¶meter, req, sizeof(parameter)); 3737 status = XHCI_TRB_2_IRQ_SET(0) | XHCI_TRB_2_BYTES_SET(sizeof(*req)); 3738 control = ((len == 0) ? XHCI_TRB_3_TRT_NONE : 3739 (isread ? XHCI_TRB_3_TRT_IN : XHCI_TRB_3_TRT_OUT)) | 3740 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 3741 XHCI_TRB_3_IDT_BIT; 3742 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3743 3744 if (len != 0) { 3745 /* data phase */ 3746 parameter = DMAADDR(dma, 0); 3747 KASSERTMSG(len <= 0x10000, "len %d", len); 3748 status = XHCI_TRB_2_IRQ_SET(0) | 3749 XHCI_TRB_2_TDSZ_SET(1) | 3750 XHCI_TRB_2_BYTES_SET(len); 3751 control = (isread ? XHCI_TRB_3_DIR_IN : 0) | 3752 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 3753 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3754 XHCI_TRB_3_IOC_BIT; 3755 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3756 } 3757 3758 parameter = 0; 3759 status = XHCI_TRB_2_IRQ_SET(0); 3760 /* the status stage has inverted direction */ 3761 control = ((isread && (len > 0)) ? 0 : XHCI_TRB_3_DIR_IN) | 3762 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 3763 XHCI_TRB_3_IOC_BIT; 3764 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3765 3766 mutex_enter(&tr->xr_lock); 3767 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3768 mutex_exit(&tr->xr_lock); 3769 3770 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3771 3772 if (xfer->ux_timeout && !xhci_polling_p(sc)) { 3773 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3774 xhci_timeout, xfer); 3775 } 3776 3777 return USBD_IN_PROGRESS; 3778 } 3779 3780 static void 3781 xhci_device_ctrl_done(struct usbd_xfer *xfer) 3782 { 3783 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3784 usb_device_request_t *req = &xfer->ux_request; 3785 int len = UGETW(req->wLength); 3786 int rd = req->bmRequestType & UT_READ; 3787 3788 if (len) 3789 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3790 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3791 } 3792 3793 static void 3794 xhci_device_ctrl_abort(struct usbd_xfer *xfer) 3795 { 3796 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3797 3798 xhci_abort_xfer(xfer, USBD_CANCELLED); 3799 } 3800 3801 static void 3802 xhci_device_ctrl_close(struct usbd_pipe *pipe) 3803 { 3804 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3805 3806 xhci_close_pipe(pipe); 3807 } 3808 3809 /* ------------------ */ 3810 /* device isochronous */ 3811 3812 /* ----------- */ 3813 /* device bulk */ 3814 3815 static usbd_status 3816 xhci_device_bulk_transfer(struct usbd_xfer *xfer) 3817 { 3818 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3819 usbd_status err; 3820 3821 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3822 3823 /* Insert last in queue. */ 3824 mutex_enter(&sc->sc_lock); 3825 err = usb_insert_transfer(xfer); 3826 mutex_exit(&sc->sc_lock); 3827 if (err) 3828 return err; 3829 3830 /* 3831 * Pipe isn't running (otherwise err would be USBD_INPROG), 3832 * so start it first. 3833 */ 3834 return xhci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3835 } 3836 3837 static usbd_status 3838 xhci_device_bulk_start(struct usbd_xfer *xfer) 3839 { 3840 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3841 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3842 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3843 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3844 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3845 const uint32_t len = xfer->ux_length; 3846 usb_dma_t * const dma = &xfer->ux_dmabuf; 3847 uint64_t parameter; 3848 uint32_t status; 3849 uint32_t control; 3850 u_int i = 0; 3851 3852 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3853 3854 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 3855 0); 3856 3857 if (sc->sc_dying) 3858 return USBD_IOERROR; 3859 3860 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3861 3862 parameter = DMAADDR(dma, 0); 3863 /* 3864 * XXX: (dsl) The physical buffer must not cross a 64k boundary. 3865 * If the user supplied buffer crosses such a boundary then 2 3866 * (or more) TRB should be used. 3867 * If multiple TRB are used the td_size field must be set correctly. 3868 * For v1.0 devices (like ivy bridge) this is the number of usb data 3869 * blocks needed to complete the transfer. 3870 * Setting it to 1 in the last TRB causes an extra zero-length 3871 * data block be sent. 3872 * The earlier documentation differs, I don't know how it behaves. 3873 */ 3874 KASSERTMSG(len <= 0x10000, "len %d", len); 3875 status = XHCI_TRB_2_IRQ_SET(0) | 3876 XHCI_TRB_2_TDSZ_SET(1) | 3877 XHCI_TRB_2_BYTES_SET(len); 3878 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3879 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3880 XHCI_TRB_3_IOC_BIT; 3881 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3882 3883 mutex_enter(&tr->xr_lock); 3884 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3885 mutex_exit(&tr->xr_lock); 3886 3887 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3888 3889 if (xfer->ux_timeout && !xhci_polling_p(sc)) { 3890 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3891 xhci_timeout, xfer); 3892 } 3893 3894 return USBD_IN_PROGRESS; 3895 } 3896 3897 static void 3898 xhci_device_bulk_done(struct usbd_xfer *xfer) 3899 { 3900 #ifdef USB_DEBUG 3901 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3902 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3903 #endif 3904 const int isread = usbd_xfer_isread(xfer); 3905 3906 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3907 3908 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 3909 0); 3910 3911 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3912 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3913 } 3914 3915 static void 3916 xhci_device_bulk_abort(struct usbd_xfer *xfer) 3917 { 3918 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3919 3920 xhci_abort_xfer(xfer, USBD_CANCELLED); 3921 } 3922 3923 static void 3924 xhci_device_bulk_close(struct usbd_pipe *pipe) 3925 { 3926 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3927 3928 xhci_close_pipe(pipe); 3929 } 3930 3931 /* ---------------- */ 3932 /* device interrupt */ 3933 3934 static usbd_status 3935 xhci_device_intr_transfer(struct usbd_xfer *xfer) 3936 { 3937 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3938 usbd_status err; 3939 3940 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3941 3942 /* Insert last in queue. */ 3943 mutex_enter(&sc->sc_lock); 3944 err = usb_insert_transfer(xfer); 3945 mutex_exit(&sc->sc_lock); 3946 if (err) 3947 return err; 3948 3949 /* 3950 * Pipe isn't running (otherwise err would be USBD_INPROG), 3951 * so start it first. 3952 */ 3953 return xhci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3954 } 3955 3956 static usbd_status 3957 xhci_device_intr_start(struct usbd_xfer *xfer) 3958 { 3959 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 3960 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 3961 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 3962 struct xhci_ring * const tr = &xs->xs_ep[dci].xe_tr; 3963 struct xhci_xfer * const xx = XHCI_XFER2XXFER(xfer); 3964 const uint32_t len = xfer->ux_length; 3965 usb_dma_t * const dma = &xfer->ux_dmabuf; 3966 uint64_t parameter; 3967 uint32_t status; 3968 uint32_t control; 3969 u_int i = 0; 3970 3971 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 3972 3973 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 3974 0); 3975 3976 if (sc->sc_dying) 3977 return USBD_IOERROR; 3978 3979 KASSERT((xfer->ux_rqflags & URQ_REQUEST) == 0); 3980 3981 parameter = DMAADDR(dma, 0); 3982 KASSERTMSG(len <= 0x10000, "len %d", len); 3983 status = XHCI_TRB_2_IRQ_SET(0) | 3984 XHCI_TRB_2_TDSZ_SET(1) | 3985 XHCI_TRB_2_BYTES_SET(len); 3986 control = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 3987 (usbd_xfer_isread(xfer) ? XHCI_TRB_3_ISP_BIT : 0) | 3988 XHCI_TRB_3_IOC_BIT; 3989 xhci_trb_put(&xx->xx_trb[i++], parameter, status, control); 3990 3991 mutex_enter(&tr->xr_lock); 3992 xhci_ring_put(sc, tr, xfer, xx->xx_trb, i); 3993 mutex_exit(&tr->xr_lock); 3994 3995 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci); 3996 3997 if (xfer->ux_timeout && !xhci_polling_p(sc)) { 3998 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3999 xhci_timeout, xfer); 4000 } 4001 4002 return USBD_IN_PROGRESS; 4003 } 4004 4005 static void 4006 xhci_device_intr_done(struct usbd_xfer *xfer) 4007 { 4008 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4009 #ifdef USB_DEBUG 4010 struct xhci_slot * const xs = xfer->ux_pipe->up_dev->ud_hcpriv; 4011 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc); 4012 #endif 4013 const int isread = usbd_xfer_isread(xfer); 4014 4015 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4016 4017 DPRINTFN(15, "%#jx slot %ju dci %ju", (uintptr_t)xfer, xs->xs_idx, dci, 4018 0); 4019 4020 KASSERT(xhci_polling_p(sc) || mutex_owned(&sc->sc_lock)); 4021 4022 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4023 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4024 } 4025 4026 static void 4027 xhci_device_intr_abort(struct usbd_xfer *xfer) 4028 { 4029 struct xhci_softc * const sc __diagused = XHCI_XFER2SC(xfer); 4030 4031 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4032 4033 KASSERT(mutex_owned(&sc->sc_lock)); 4034 DPRINTFN(15, "%#jx", (uintptr_t)xfer, 0, 0, 0); 4035 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4036 xhci_abort_xfer(xfer, USBD_CANCELLED); 4037 } 4038 4039 static void 4040 xhci_device_intr_close(struct usbd_pipe *pipe) 4041 { 4042 //struct xhci_softc * const sc = XHCI_PIPE2SC(pipe); 4043 4044 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4045 DPRINTFN(15, "%#jx", (uintptr_t)pipe, 0, 0, 0); 4046 4047 xhci_close_pipe(pipe); 4048 } 4049 4050 /* ------------ */ 4051 4052 static void 4053 xhci_timeout(void *addr) 4054 { 4055 struct xhci_xfer * const xx = addr; 4056 struct usbd_xfer * const xfer = &xx->xx_xfer; 4057 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4058 4059 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4060 4061 if (sc->sc_dying) { 4062 return; 4063 } 4064 4065 usb_init_task(&xx->xx_abort_task, xhci_timeout_task, addr, 4066 USB_TASKQ_MPSAFE); 4067 usb_add_task(xx->xx_xfer.ux_pipe->up_dev, &xx->xx_abort_task, 4068 USB_TASKQ_HC); 4069 } 4070 4071 static void 4072 xhci_timeout_task(void *addr) 4073 { 4074 struct usbd_xfer * const xfer = addr; 4075 struct xhci_softc * const sc = XHCI_XFER2SC(xfer); 4076 4077 XHCIHIST_FUNC(); XHCIHIST_CALLED(); 4078 4079 mutex_enter(&sc->sc_lock); 4080 xhci_abort_xfer(xfer, USBD_TIMEOUT); 4081 mutex_exit(&sc->sc_lock); 4082 } 4083
Indexes created Wed Oct 01 18:09:54 GMT 2025