xhcivar.h revision 1.7 1 1.7 skrll /* $NetBSD: xhcivar.h,v 1.7 2017/01/19 16:05:00 skrll Exp $ */
2 1.1 jakllsch
3 1.1 jakllsch /*
4 1.1 jakllsch * Copyright (c) 2013 Jonathan A. Kollasch
5 1.1 jakllsch * All rights reserved.
6 1.1 jakllsch *
7 1.1 jakllsch * Redistribution and use in source and binary forms, with or without
8 1.1 jakllsch * modification, are permitted provided that the following conditions
9 1.1 jakllsch * are met:
10 1.1 jakllsch * 1. Redistributions of source code must retain the above copyright
11 1.1 jakllsch * notice, this list of conditions and the following disclaimer.
12 1.1 jakllsch * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 jakllsch * notice, this list of conditions and the following disclaimer in the
14 1.1 jakllsch * documentation and/or other materials provided with the distribution.
15 1.1 jakllsch *
16 1.1 jakllsch * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 1.1 jakllsch * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 1.1 jakllsch * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 1.1 jakllsch * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
20 1.1 jakllsch * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 1.1 jakllsch * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22 1.1 jakllsch * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23 1.1 jakllsch * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 1.1 jakllsch * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25 1.1 jakllsch * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
26 1.1 jakllsch * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 1.1 jakllsch */
28 1.1 jakllsch
29 1.1 jakllsch #ifndef _DEV_USB_XHCIVAR_H_
30 1.1 jakllsch #define _DEV_USB_XHCIVAR_H_
31 1.1 jakllsch
32 1.1 jakllsch #include <sys/pool.h>
33 1.1 jakllsch
34 1.5 skrll #define XHCI_XFER_NTRB 20
35 1.5 skrll
36 1.1 jakllsch struct xhci_xfer {
37 1.1 jakllsch struct usbd_xfer xx_xfer;
38 1.1 jakllsch struct usb_task xx_abort_task;
39 1.5 skrll struct xhci_trb xx_trb[XHCI_XFER_NTRB];
40 1.1 jakllsch };
41 1.1 jakllsch
42 1.5 skrll #define XHCI_BUS2SC(bus) ((bus)->ub_hcpriv)
43 1.5 skrll #define XHCI_PIPE2SC(pipe) XHCI_BUS2SC((pipe)->up_dev->ud_bus)
44 1.5 skrll #define XHCI_XFER2SC(xfer) XHCI_BUS2SC((xfer)->ux_bus)
45 1.7 skrll #define XHCI_XFER2BUS(xfer) ((xfer)->ux_bus)
46 1.5 skrll #define XHCI_XPIPE2SC(d) XHCI_BUS2SC((d)->xp_pipe.up_dev->ud_bus)
47 1.5 skrll
48 1.5 skrll #define XHCI_XFER2XXFER(xfer) ((struct xhci_xfer *)(xfer))
49 1.5 skrll
50 1.1 jakllsch struct xhci_ring {
51 1.1 jakllsch usb_dma_t xr_dma;
52 1.1 jakllsch kmutex_t xr_lock;
53 1.1 jakllsch struct xhci_trb * xr_trb;
54 1.1 jakllsch void **xr_cookies;
55 1.1 jakllsch u_int xr_ntrb; /* number of elements for above */
56 1.1 jakllsch u_int xr_ep; /* enqueue pointer */
57 1.1 jakllsch u_int xr_cs; /* cycle state */
58 1.1 jakllsch bool is_halted;
59 1.1 jakllsch };
60 1.1 jakllsch
61 1.1 jakllsch struct xhci_endpoint {
62 1.1 jakllsch struct xhci_ring xe_tr; /* transfer ring */
63 1.1 jakllsch };
64 1.1 jakllsch
65 1.1 jakllsch struct xhci_slot {
66 1.1 jakllsch usb_dma_t xs_dc_dma; /* device context page */
67 1.1 jakllsch usb_dma_t xs_ic_dma; /* input context page */
68 1.1 jakllsch struct xhci_endpoint xs_ep[32]; /* endpoints */
69 1.1 jakllsch u_int xs_idx; /* slot index */
70 1.1 jakllsch };
71 1.1 jakllsch
72 1.1 jakllsch struct xhci_softc {
73 1.1 jakllsch device_t sc_dev;
74 1.1 jakllsch device_t sc_child;
75 1.7 skrll device_t sc_child2;
76 1.1 jakllsch bus_size_t sc_ios;
77 1.1 jakllsch bus_space_tag_t sc_iot;
78 1.1 jakllsch bus_space_handle_t sc_ioh; /* Base */
79 1.1 jakllsch bus_space_handle_t sc_cbh; /* Capability Base */
80 1.1 jakllsch bus_space_handle_t sc_obh; /* Operational Base */
81 1.1 jakllsch bus_space_handle_t sc_rbh; /* Runtime Base */
82 1.1 jakllsch bus_space_handle_t sc_dbh; /* Doorbell Registers */
83 1.7 skrll struct usbd_bus sc_bus; /* USB 3 bus */
84 1.7 skrll struct usbd_bus sc_bus2; /* USB 2 bus */
85 1.1 jakllsch
86 1.1 jakllsch kmutex_t sc_lock;
87 1.1 jakllsch kmutex_t sc_intr_lock;
88 1.1 jakllsch kcondvar_t sc_softwake_cv;
89 1.1 jakllsch
90 1.5 skrll char sc_vendor[32]; /* vendor string for root hub */
91 1.5 skrll int sc_id_vendor; /* vendor ID for root hub */
92 1.5 skrll
93 1.1 jakllsch pool_cache_t sc_xferpool;
94 1.1 jakllsch
95 1.1 jakllsch bus_size_t sc_pgsz; /* xHCI page size */
96 1.1 jakllsch uint32_t sc_ctxsz;
97 1.1 jakllsch int sc_maxslots;
98 1.1 jakllsch int sc_maxintrs;
99 1.2 matt int sc_maxspbuf;
100 1.1 jakllsch
101 1.7 skrll /*
102 1.7 skrll * Port routing and root hub - xHCI 4.19.7
103 1.7 skrll */
104 1.7 skrll int sc_maxports; /* number of controller ports */
105 1.7 skrll
106 1.7 skrll uint8_t *sc_ctlrportbus; /* a bus bit per port */
107 1.7 skrll
108 1.7 skrll int *sc_ctlrportmap;
109 1.7 skrll int *sc_rhportmap[2];
110 1.7 skrll int sc_rhportcount[2];
111 1.7 skrll struct usbd_xfer *sc_intrxfer[2];
112 1.7 skrll
113 1.1 jakllsch
114 1.1 jakllsch struct xhci_slot * sc_slots;
115 1.1 jakllsch
116 1.1 jakllsch struct xhci_ring sc_cr; /* command ring */
117 1.1 jakllsch struct xhci_ring sc_er; /* event ring */
118 1.1 jakllsch
119 1.1 jakllsch usb_dma_t sc_eventst_dma;
120 1.1 jakllsch usb_dma_t sc_dcbaa_dma;
121 1.2 matt usb_dma_t sc_spbufarray_dma;
122 1.2 matt usb_dma_t *sc_spbuf_dma;
123 1.1 jakllsch
124 1.7 skrll kcondvar_t sc_cmdbusy_cv;
125 1.1 jakllsch kcondvar_t sc_command_cv;
126 1.1 jakllsch bus_addr_t sc_command_addr;
127 1.1 jakllsch struct xhci_trb sc_result_trb;
128 1.7 skrll bool sc_resultpending;
129 1.1 jakllsch
130 1.1 jakllsch bool sc_ac64;
131 1.1 jakllsch bool sc_dying;
132 1.1 jakllsch
133 1.5 skrll void (*sc_vendor_init)(struct xhci_softc *);
134 1.5 skrll int (*sc_vendor_port_status)(struct xhci_softc *, uint32_t, int);
135 1.5 skrll
136 1.5 skrll int sc_quirks;
137 1.6 skrll #define XHCI_QUIRK_INTEL __BIT(0) /* Intel xhci chip */
138 1.1 jakllsch };
139 1.1 jakllsch
140 1.4 skrll int xhci_init(struct xhci_softc *);
141 1.4 skrll int xhci_intr(void *);
142 1.4 skrll int xhci_detach(struct xhci_softc *, int);
143 1.4 skrll int xhci_activate(device_t, enum devact);
144 1.4 skrll void xhci_childdet(device_t, device_t);
145 1.4 skrll bool xhci_suspend(device_t, const pmf_qual_t *);
146 1.4 skrll bool xhci_resume(device_t, const pmf_qual_t *);
147 1.4 skrll bool xhci_shutdown(device_t, int);
148 1.1 jakllsch
149 1.1 jakllsch #define XHCI_TRANSFER_RING_TRBS 256
150 1.1 jakllsch
151 1.1 jakllsch #endif /* _DEV_USB_XHCIVAR_H_ */
152