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xhcivar.h revision 1.13 
      1 /*	$NetBSD: xhcivar.h,v 1.13 2020/04/02 11:52:41 skrll Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 2013 Jonathan A. Kollasch
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
     17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     18  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     19  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
     20  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
     21  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
     22  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
     23  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
     24  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
     25  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
     26  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _DEV_USB_XHCIVAR_H_
     30 #define _DEV_USB_XHCIVAR_H_
     31 
     32 #include <sys/pool.h>
     33 
     34 #define XHCI_XFER_NTRB	20
     35 #define XHCI_MAX_DCI	31
     36 
     37 struct xhci_soft_trb {
     38 	uint64_t trb_0;
     39 	uint32_t trb_2;
     40 	uint32_t trb_3;
     41 };
     42 
     43 struct xhci_xfer {
     44 	struct usbd_xfer xx_xfer;
     45 	struct xhci_soft_trb xx_trb[XHCI_XFER_NTRB];
     46 };
     47 
     48 #define XHCI_BUS2SC(bus)	((bus)->ub_hcpriv)
     49 #define XHCI_PIPE2SC(pipe)	XHCI_BUS2SC((pipe)->up_dev->ud_bus)
     50 #define XHCI_XFER2SC(xfer)	XHCI_BUS2SC((xfer)->ux_bus)
     51 #define XHCI_XFER2BUS(xfer)	((xfer)->ux_bus)
     52 #define XHCI_XPIPE2SC(d)	XHCI_BUS2SC((d)->xp_pipe.up_dev->ud_bus)
     53 
     54 #define XHCI_XFER2XXFER(xfer)	((struct xhci_xfer *)(xfer))
     55 
     56 struct xhci_ring {
     57 	usb_dma_t xr_dma;
     58 	kmutex_t xr_lock;
     59 	struct xhci_trb * xr_trb;
     60 	void **xr_cookies;
     61 	u_int xr_ntrb;			/* number of elements for above */
     62 	u_int xr_ep;			/* enqueue pointer */
     63 	u_int xr_cs;			/* cycle state */
     64 	bool is_halted;
     65 };
     66 
     67 struct xhci_endpoint {
     68 	struct xhci_ring xe_tr;		/* transfer ring */
     69 };
     70 
     71 struct xhci_slot {
     72 	usb_dma_t xs_dc_dma;		/* device context page */
     73 	usb_dma_t xs_ic_dma;		/* input context page */
     74 	struct xhci_ring *xs_xr[XHCI_MAX_DCI + 1];
     75 					/* transfer rings */
     76 	u_int xs_idx;			/* slot index */
     77 };
     78 
     79 struct xhci_softc {
     80 	device_t sc_dev;
     81 	device_t sc_child;
     82 	device_t sc_child2;
     83 	bus_size_t sc_ios;
     84 	bus_space_tag_t sc_iot;
     85 	bus_space_handle_t sc_ioh;	/* Base */
     86 	bus_space_handle_t sc_cbh;	/* Capability Base */
     87 	bus_space_handle_t sc_obh;	/* Operational Base */
     88 	bus_space_handle_t sc_rbh;	/* Runtime Base */
     89 	bus_space_handle_t sc_dbh;	/* Doorbell Registers */
     90 	struct usbd_bus sc_bus;		/* USB 3 bus */
     91 	struct usbd_bus sc_bus2;	/* USB 2 bus */
     92 
     93 	kmutex_t sc_lock;
     94 	kmutex_t sc_intr_lock;
     95 
     96 	pool_cache_t sc_xferpool;
     97 
     98 	bus_size_t sc_pgsz;		/* xHCI page size */
     99 	uint32_t sc_ctxsz;
    100 	int sc_maxslots;
    101 	int sc_maxintrs;
    102 	int sc_maxspbuf;
    103 
    104 	/*
    105 	 * Port routing and root hub - xHCI 4.19.7
    106 	 */
    107 	int sc_maxports;		/* number of controller ports */
    108 
    109 	uint8_t *sc_ctlrportbus;	/* a bus bit per port */
    110 
    111 	int *sc_ctlrportmap;
    112 	int *sc_rhportmap[2];
    113 	int sc_rhportcount[2];
    114 	struct usbd_xfer *sc_intrxfer[2];
    115 
    116 
    117 	struct xhci_slot * sc_slots;
    118 
    119 	struct xhci_ring *sc_cr;	/* command ring */
    120 	struct xhci_ring *sc_er;	/* event ring */
    121 
    122 	usb_dma_t sc_eventst_dma;
    123 	usb_dma_t sc_dcbaa_dma;
    124 	usb_dma_t sc_spbufarray_dma;
    125 	usb_dma_t *sc_spbuf_dma;
    126 
    127 	kcondvar_t sc_cmdbusy_cv;
    128 	kcondvar_t sc_command_cv;
    129 	bus_addr_t sc_command_addr;
    130 	struct xhci_soft_trb sc_result_trb;
    131 	bool sc_resultpending;
    132 
    133 	bool sc_ac64;
    134 	bool sc_dying;
    135 
    136 	void (*sc_vendor_init)(struct xhci_softc *);
    137 	int (*sc_vendor_port_status)(struct xhci_softc *, uint32_t, int);
    138 
    139 	int sc_quirks;
    140 #define XHCI_QUIRK_INTEL	__BIT(0) /* Intel xhci chip */
    141 #define XHCI_DEFERRED_START	__BIT(1)
    142 };
    143 
    144 int	xhci_init(struct xhci_softc *);
    145 void	xhci_start(struct xhci_softc *);
    146 int	xhci_intr(void *);
    147 int	xhci_detach(struct xhci_softc *, int);
    148 int	xhci_activate(device_t, enum devact);
    149 void	xhci_childdet(device_t, device_t);
    150 bool	xhci_suspend(device_t, const pmf_qual_t *);
    151 bool	xhci_resume(device_t, const pmf_qual_t *);
    152 bool	xhci_shutdown(device_t, int);
    153 
    154 #define XHCI_TRANSFER_RING_TRBS 256
    155 
    156 #endif /* _DEV_USB_XHCIVAR_H_ */
    157