xhcivar.h revision 1.22
1 /* $NetBSD: xhcivar.h,v 1.22 2022/10/11 09:18:22 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2013 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _DEV_USB_XHCIVAR_H_ 30 #define _DEV_USB_XHCIVAR_H_ 31 32 #include <sys/types.h> 33 34 #include <sys/condvar.h> 35 #include <sys/device.h> 36 #include <sys/mutex.h> 37 #include <sys/pmf.h> 38 #include <sys/pool.h> 39 40 #include <dev/usb/usbdi.h> 41 #include <dev/usb/usbdivar.h> 42 43 #define XHCI_MAX_DCI 31 44 45 struct xhci_soft_trb { 46 uint64_t trb_0; 47 uint32_t trb_2; 48 uint32_t trb_3; 49 }; 50 51 struct xhci_xfer { 52 struct usbd_xfer xx_xfer; 53 struct xhci_soft_trb *xx_trb; 54 u_int xx_ntrb; 55 u_int xx_isoc_done; 56 }; 57 58 #define XHCI_BUS2SC(bus) ((bus)->ub_hcpriv) 59 #define XHCI_PIPE2SC(pipe) XHCI_BUS2SC((pipe)->up_dev->ud_bus) 60 #define XHCI_XFER2SC(xfer) XHCI_BUS2SC((xfer)->ux_bus) 61 #define XHCI_XFER2BUS(xfer) ((xfer)->ux_bus) 62 #define XHCI_XPIPE2SC(d) XHCI_BUS2SC((d)->xp_pipe.up_dev->ud_bus) 63 64 #define XHCI_XFER2XXFER(xfer) ((struct xhci_xfer *)(xfer)) 65 66 struct xhci_ring { 67 usb_dma_t xr_dma; 68 kmutex_t xr_lock; 69 struct xhci_trb * xr_trb; 70 void **xr_cookies; 71 u_int xr_ntrb; /* number of elements for above */ 72 u_int xr_ep; /* enqueue pointer */ 73 u_int xr_cs; /* cycle state */ 74 bool is_halted; 75 }; 76 77 struct xhci_slot { 78 usb_dma_t xs_dc_dma; /* device context page */ 79 usb_dma_t xs_ic_dma; /* input context page */ 80 struct xhci_ring *xs_xr[XHCI_MAX_DCI + 1]; 81 /* transfer rings */ 82 u_int xs_idx; /* slot index */ 83 }; 84 85 struct xhci_softc { 86 device_t sc_dev; 87 device_t sc_child; 88 device_t sc_child2; 89 bus_size_t sc_ios; 90 bus_space_tag_t sc_iot; 91 bus_space_handle_t sc_ioh; /* Base */ 92 bus_space_handle_t sc_cbh; /* Capability Base */ 93 bus_space_handle_t sc_obh; /* Operational Base */ 94 bus_space_handle_t sc_rbh; /* Runtime Base */ 95 bus_space_handle_t sc_dbh; /* Doorbell Registers */ 96 struct usbd_bus sc_bus; /* USB 3 bus */ 97 struct usbd_bus sc_bus2; /* USB 2 bus */ 98 99 kmutex_t sc_rhlock; 100 kmutex_t sc_lock; 101 kmutex_t sc_intr_lock; 102 103 pool_cache_t sc_xferpool; 104 105 bus_size_t sc_pgsz; /* xHCI page size */ 106 uint32_t sc_ctxsz; 107 int sc_maxslots; 108 int sc_maxintrs; 109 int sc_maxspbuf; 110 111 /* 112 * Port routing and root hub - xHCI 4.19.7 113 */ 114 int sc_maxports; /* number of controller ports */ 115 int sc_usb3nports; 116 int sc_usb2nports; 117 118 uint8_t *sc_ctlrportbus; /* a bus bit per port */ 119 120 int *sc_ctlrportmap; 121 int *sc_rhportmap[2]; 122 int sc_rhportcount[2]; 123 struct usbd_xfer *sc_intrxfer[2]; 124 125 126 struct xhci_slot * sc_slots; 127 128 struct xhci_ring *sc_cr; /* command ring */ 129 struct xhci_ring *sc_er; /* event ring */ 130 131 usb_dma_t sc_eventst_dma; 132 usb_dma_t sc_dcbaa_dma; 133 usb_dma_t sc_spbufarray_dma; 134 usb_dma_t *sc_spbuf_dma; 135 136 kcondvar_t sc_cmdbusy_cv; 137 kcondvar_t sc_command_cv; 138 bus_addr_t sc_command_addr; 139 struct xhci_soft_trb sc_result_trb; 140 bool sc_resultpending; 141 142 bool sc_dying; 143 struct lwp *sc_suspender; 144 145 void (*sc_vendor_init)(struct xhci_softc *); 146 int (*sc_vendor_port_status)(struct xhci_softc *, uint32_t, int); 147 148 int sc_quirks; 149 #define XHCI_QUIRK_INTEL __BIT(0) /* Intel xhci chip */ 150 #define XHCI_DEFERRED_START __BIT(1) 151 uint32_t sc_hcc; /* copy of HCCPARAMS1 */ 152 uint32_t sc_hcc2; /* copy of HCCPARAMS2 */ 153 154 struct xhci_registers { 155 uint32_t usbcmd; 156 uint32_t dnctrl; 157 uint64_t dcbaap; 158 uint32_t config; 159 uint32_t erstsz0; 160 uint64_t erstba0; 161 uint64_t erdp0; 162 uint32_t iman0; 163 uint32_t imod0; 164 } sc_regs; 165 }; 166 167 int xhci_init(struct xhci_softc *); 168 void xhci_start(struct xhci_softc *); 169 int xhci_intr(void *); 170 int xhci_detach(struct xhci_softc *, int); 171 int xhci_activate(device_t, enum devact); 172 void xhci_childdet(device_t, device_t); 173 bool xhci_suspend(device_t, const pmf_qual_t *); 174 bool xhci_resume(device_t, const pmf_qual_t *); 175 bool xhci_shutdown(device_t, int); 176 177 #define XHCI_TRANSFER_RING_TRBS 256 178 179 #endif /* _DEV_USB_XHCIVAR_H_ */ 180
Indexes created Tue Sep 30 07:10:03 GMT 2025