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si.c revision 1.19.16.2
      1  1.19.16.1       mjf /*	$NetBSD: si.c,v 1.19.16.2 2009/01/17 13:29:10 mjf Exp $	*/
      2        1.1        pk 
      3        1.1        pk /*-
      4        1.1        pk  * Copyright (c) 1996,2000 The NetBSD Foundation, Inc.
      5        1.1        pk  * All rights reserved.
      6        1.1        pk  *
      7        1.1        pk  * This code is derived from software contributed to The NetBSD Foundation
      8        1.1        pk  * by Adam Glass, David Jones, Gordon W. Ross, Jason R. Thorpe and
      9        1.1        pk  * Paul Kranenburg.
     10        1.1        pk  *
     11        1.1        pk  * Redistribution and use in source and binary forms, with or without
     12        1.1        pk  * modification, are permitted provided that the following conditions
     13        1.1        pk  * are met:
     14        1.1        pk  * 1. Redistributions of source code must retain the above copyright
     15        1.1        pk  *    notice, this list of conditions and the following disclaimer.
     16        1.1        pk  * 2. Redistributions in binary form must reproduce the above copyright
     17        1.1        pk  *    notice, this list of conditions and the following disclaimer in the
     18        1.1        pk  *    documentation and/or other materials provided with the distribution.
     19        1.1        pk  *
     20        1.1        pk  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     21        1.1        pk  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     22        1.1        pk  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     23        1.1        pk  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     24        1.1        pk  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     25        1.1        pk  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     26        1.1        pk  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     27        1.1        pk  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     28        1.1        pk  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     29        1.1        pk  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     30        1.1        pk  * POSSIBILITY OF SUCH DAMAGE.
     31        1.1        pk  */
     32        1.1        pk 
     33        1.1        pk /*
     34        1.1        pk  * This file contains VME bus-dependent of the `si' SCSI adapter.
     35        1.1        pk  * This hardware is frequently found on Sun 3 and Sun 4 machines.
     36        1.1        pk  *
     37        1.1        pk  * The SCSI machinery on this adapter is implemented by an NCR5380,
     38        1.1        pk  * which is taken care of by the chipset driver in /sys/dev/ic/ncr5380sbc.c
     39        1.1        pk  *
     40        1.1        pk  * The logic has a bit to enable or disable the DMA engine,
     41        1.1        pk  * but that bit also gates the interrupt line from the NCR5380!
     42        1.1        pk  * Therefore, in order to get any interrupt from the 5380, (i.e.
     43        1.1        pk  * for reselect) one must clear the DMA engine transfer count and
     44        1.1        pk  * then enable DMA.  This has the further complication that you
     45        1.1        pk  * CAN NOT touch the NCR5380 while the DMA enable bit is set, so
     46        1.1        pk  * we have to turn DMA back off before we even look at the 5380.
     47        1.1        pk  *
     48        1.1        pk  * What wonderfully whacky hardware this is!
     49        1.1        pk  *
     50        1.1        pk  */
     51        1.1        pk 
     52        1.1        pk /*
     53        1.1        pk  * This driver originated as an MD implementation for the sun3 and sun4
     54        1.1        pk  * ports. The notes pertaining to that history are included below.
     55        1.1        pk  *
     56        1.1        pk  * David Jones wrote the initial version of this module for NetBSD/sun3,
     57        1.1        pk  * which included support for the VME adapter only. (no reselection).
     58        1.1        pk  *
     59        1.1        pk  * Gordon Ross added support for the Sun 3 OBIO adapter, and re-worked
     60        1.1        pk  * both the VME and OBIO code to support disconnect/reselect.
     61        1.1        pk  * (Required figuring out the hardware "features" noted above.)
     62        1.1        pk  *
     63        1.1        pk  * The autoconfiguration boilerplate came from Adam Glass.
     64        1.1        pk  *
     65        1.1        pk  * Jason R. Thorpe ported the autoconfiguration and VME portions to
     66        1.1        pk  * NetBSD/sparc, and added initial support for the 4/100 "SCSI Weird",
     67        1.1        pk  * a wacky OBIO variant of the VME SCSI-3.  Many thanks to Chuck Cranor
     68        1.1        pk  * for lots of helpful tips and suggestions.  Thanks also to Paul Kranenburg
     69        1.1        pk  * and Chris Torek for bits of insight needed along the way.  Thanks to
     70        1.1        pk  * David Gilbert and Andrew Gillham who risked filesystem life-and-limb
     71        1.1        pk  * for the sake of testing.  Andrew Gillham helped work out the bugs
     72        1.1        pk  * the 4/100 DMA code.
     73        1.1        pk  */
     74        1.6     lukem 
     75        1.6     lukem #include <sys/cdefs.h>
     76  1.19.16.1       mjf __KERNEL_RCSID(0, "$NetBSD: si.c,v 1.19.16.2 2009/01/17 13:29:10 mjf Exp $");
     77        1.1        pk 
     78        1.1        pk #include "opt_ddb.h"
     79        1.1        pk 
     80        1.1        pk #include <sys/param.h>
     81        1.1        pk #include <sys/systm.h>
     82        1.1        pk #include <sys/kernel.h>
     83        1.1        pk #include <sys/malloc.h>
     84        1.1        pk #include <sys/errno.h>
     85        1.1        pk #include <sys/device.h>
     86        1.1        pk #include <sys/buf.h>
     87        1.1        pk 
     88       1.19        ad #include <sys/bus.h>
     89       1.19        ad #include <sys/intr.h>
     90        1.1        pk 
     91        1.1        pk #include <dev/vme/vmereg.h>
     92        1.1        pk #include <dev/vme/vmevar.h>
     93        1.1        pk 
     94        1.1        pk #include <dev/scsipi/scsi_all.h>
     95        1.1        pk #include <dev/scsipi/scsipi_all.h>
     96        1.1        pk #include <dev/scsipi/scsipi_debug.h>
     97        1.1        pk #include <dev/scsipi/scsiconf.h>
     98        1.1        pk 
     99        1.8  fredette #ifndef Debugger
    100        1.1        pk #define	Debugger()
    101        1.1        pk #endif
    102        1.1        pk 
    103        1.1        pk #ifndef DEBUG
    104        1.1        pk #define DEBUG XXX
    105        1.1        pk #endif
    106        1.1        pk 
    107        1.1        pk #include <dev/ic/ncr5380reg.h>
    108        1.1        pk #include <dev/ic/ncr5380var.h>
    109        1.1        pk 
    110        1.2   thorpej #include <dev/vme/sireg.h>
    111        1.1        pk 
    112        1.1        pk /*
    113        1.1        pk  * Transfers smaller than this are done using PIO
    114        1.1        pk  * (on assumption they're not worth DMA overhead)
    115        1.1        pk  */
    116        1.1        pk #define	MIN_DMA_LEN 128
    117        1.1        pk 
    118        1.1        pk #ifdef	DEBUG
    119        1.1        pk int si_debug = 0;
    120        1.1        pk #endif
    121        1.1        pk 
    122        1.1        pk /*
    123        1.1        pk  * This structure is used to keep track of mapped DMA requests.
    124        1.1        pk  */
    125        1.1        pk struct si_dma_handle {
    126        1.1        pk 	int 		dh_flags;
    127        1.1        pk #define	SIDH_BUSY	0x01		/* This DH is in use */
    128        1.1        pk #define	SIDH_OUT	0x02		/* DMA does data out (write) */
    129        1.1        pk 	int 		dh_maplen;	/* Original data length */
    130        1.1        pk 	bus_dmamap_t	dh_dmamap;
    131        1.1        pk #define dh_dvma	dh_dmamap->dm_segs[0].ds_addr /* VA of buffer in DVMA space */
    132        1.1        pk };
    133        1.1        pk 
    134        1.1        pk /*
    135        1.1        pk  * The first structure member has to be the ncr5380_softc
    136        1.1        pk  * so we can just cast to go back and fourth between them.
    137        1.1        pk  */
    138        1.1        pk struct si_softc {
    139        1.1        pk 	struct ncr5380_softc	ncr_sc;
    140        1.1        pk 	bus_space_tag_t		sc_bustag;	/* bus tags */
    141        1.1        pk 	bus_dma_tag_t		sc_dmatag;
    142        1.1        pk 	vme_chipset_tag_t	sc_vctag;
    143        1.1        pk 
    144        1.1        pk 	int		sc_adapter_iv_am; /* int. vec + address modifier */
    145        1.1        pk 	struct si_dma_handle *sc_dma;
    146        1.1        pk 	int		sc_xlen;	/* length of current DMA segment. */
    147        1.1        pk 	int		sc_options;	/* options for this instance. */
    148        1.1        pk };
    149        1.1        pk 
    150        1.1        pk /*
    151        1.1        pk  * Options.  By default, DMA is enabled and DMA completion interrupts
    152        1.1        pk  * and reselect are disabled.  You may enable additional features
    153        1.1        pk  * the `flags' directive in your kernel's configuration file.
    154        1.1        pk  *
    155        1.1        pk  * Alternatively, you can patch your kernel with DDB or some other
    156        1.1        pk  * mechanism.  The sc_options member of the softc is OR'd with
    157        1.1        pk  * the value in si_options.
    158        1.1        pk  *
    159        1.1        pk  * Note, there's a separate sw_options to make life easier.
    160        1.1        pk  */
    161        1.1        pk #define	SI_ENABLE_DMA	0x01	/* Use DMA (maybe polled) */
    162        1.1        pk #define	SI_DMA_INTR	0x02	/* DMA completion interrupts */
    163        1.1        pk #define	SI_DO_RESELECT	0x04	/* Allow disconnect/reselect */
    164        1.1        pk #define	SI_OPTIONS_MASK	(SI_ENABLE_DMA|SI_DMA_INTR|SI_DO_RESELECT)
    165        1.1        pk #define SI_OPTIONS_BITS	"\10\3RESELECT\2DMA_INTR\1DMA"
    166        1.1        pk int si_options = SI_ENABLE_DMA|SI_DMA_INTR|SI_DO_RESELECT;
    167        1.1        pk 
    168  1.19.16.1       mjf static int	si_match(device_t, cfdata_t, void *);
    169  1.19.16.1       mjf static void	si_attach(device_t, device_t, void *);
    170       1.14     perry static int	si_intr(void *);
    171       1.14     perry static void	si_reset_adapter(struct ncr5380_softc *);
    172       1.14     perry 
    173       1.14     perry void	si_dma_alloc(struct ncr5380_softc *);
    174       1.14     perry void	si_dma_free(struct ncr5380_softc *);
    175       1.14     perry void	si_dma_poll(struct ncr5380_softc *);
    176       1.14     perry 
    177       1.14     perry void	si_dma_setup(struct ncr5380_softc *);
    178       1.14     perry void	si_dma_start(struct ncr5380_softc *);
    179       1.14     perry void	si_dma_eop(struct ncr5380_softc *);
    180       1.14     perry void	si_dma_stop(struct ncr5380_softc *);
    181        1.1        pk 
    182       1.14     perry void	si_intr_on (struct ncr5380_softc *);
    183       1.14     perry void	si_intr_off(struct ncr5380_softc *);
    184        1.1        pk 
    185        1.1        pk /*
    186        1.1        pk  * Shorthand bus space access
    187        1.1        pk  * XXX - must look into endian issues here.
    188        1.1        pk  */
    189        1.1        pk #define SIREG_READ(sc, index) \
    190        1.1        pk 	bus_space_read_2((sc)->sc_regt, (sc)->sc_regh, index)
    191        1.1        pk #define SIREG_WRITE(sc, index, v) \
    192        1.1        pk 	bus_space_write_2((sc)->sc_regt, (sc)->sc_regh, index, v)
    193        1.1        pk 
    194        1.1        pk 
    195        1.1        pk /* Auto-configuration glue. */
    196  1.19.16.1       mjf CFATTACH_DECL_NEW(si, sizeof(struct si_softc),
    197       1.12   thorpej     si_match, si_attach, NULL, NULL);
    198        1.1        pk 
    199        1.1        pk static int
    200  1.19.16.1       mjf si_match(device_t parent, cfdata_t cf, void *aux)
    201        1.1        pk {
    202        1.1        pk 	struct vme_attach_args	*va = aux;
    203        1.1        pk 	vme_chipset_tag_t	ct = va->va_vct;
    204       1.15     perry         vme_am_t		mod;
    205        1.1        pk         vme_addr_t		vme_addr;
    206        1.1        pk 
    207        1.1        pk 	/* Make sure there is something there... */
    208        1.1        pk 	mod = VME_AM_A24 | VME_AM_MBO | VME_AM_SUPER | VME_AM_DATA;
    209        1.1        pk 	vme_addr = va->r[0].offset;
    210        1.1        pk 
    211        1.1        pk 	if (vme_probe(ct, vme_addr, 1, mod, VME_D8, NULL, 0) != 0)
    212  1.19.16.1       mjf 		return 0;
    213        1.1        pk 
    214        1.1        pk 	/*
    215        1.1        pk 	 * If this is a VME SCSI board, we have to determine whether
    216        1.1        pk 	 * it is an "sc" (Sun2) or "si" (Sun3) SCSI board.  This can
    217        1.1        pk 	 * be determined using the fact that the "sc" board occupies
    218        1.1        pk 	 * 4K bytes in VME space but the "si" board occupies 2K bytes.
    219        1.1        pk 	 */
    220  1.19.16.1       mjf 	return vme_probe(ct, vme_addr + 0x801, 1, mod, VME_D8, NULL, 0) != 0;
    221        1.1        pk }
    222        1.1        pk 
    223        1.1        pk static void
    224  1.19.16.1       mjf si_attach(device_t parent, device_t self, void *aux)
    225        1.1        pk {
    226  1.19.16.1       mjf 	struct si_softc		*sc = device_private(self);
    227        1.1        pk 	struct ncr5380_softc *ncr_sc = &sc->ncr_sc;
    228        1.1        pk 	struct vme_attach_args	*va = aux;
    229        1.1        pk 	vme_chipset_tag_t	ct = va->va_vct;
    230        1.1        pk 	bus_space_tag_t		bt;
    231        1.1        pk 	bus_space_handle_t	bh;
    232        1.1        pk 	vme_mapresc_t resc;
    233        1.1        pk 	vme_intr_handle_t	ih;
    234        1.1        pk 	vme_am_t		mod;
    235        1.1        pk 	char bits[64];
    236        1.1        pk 	int i;
    237        1.1        pk 
    238  1.19.16.1       mjf 	ncr_sc->sc_dev = self;
    239        1.1        pk 	sc->sc_dmatag = va->va_bdt;
    240        1.1        pk 	sc->sc_vctag = ct;
    241        1.1        pk 
    242        1.1        pk 	mod = VME_AM_A24 | VME_AM_MBO | VME_AM_SUPER | VME_AM_DATA;
    243        1.1        pk 
    244        1.1        pk 	if (vme_space_map(ct, va->r[0].offset, SIREG_BANK_SZ,
    245        1.1        pk 			  mod, VME_D8, 0, &bt, &bh, &resc) != 0)
    246  1.19.16.1       mjf 		panic("%s: vme_space_map", device_xname(self));
    247        1.1        pk 
    248        1.1        pk 	ncr_sc->sc_regt = bt;
    249        1.1        pk 	ncr_sc->sc_regh = bh;
    250        1.1        pk 
    251        1.1        pk 	sc->sc_options = si_options;
    252        1.1        pk 
    253        1.1        pk 	ncr_sc->sc_dma_setup = si_dma_setup;
    254        1.1        pk 	ncr_sc->sc_dma_start = si_dma_start;
    255        1.1        pk 	ncr_sc->sc_dma_eop   = si_dma_stop;
    256        1.1        pk 	ncr_sc->sc_dma_stop  = si_dma_stop;
    257        1.1        pk 
    258        1.1        pk 	vme_intr_map(ct, va->ilevel, va->ivector, &ih);
    259        1.1        pk 	vme_intr_establish(ct, ih, IPL_BIO, si_intr, sc);
    260        1.1        pk 
    261  1.19.16.1       mjf 	aprint_normal("\n");
    262        1.1        pk 
    263        1.1        pk 	sc->sc_adapter_iv_am = (mod << 8) | (va->ivector & 0xFF);
    264        1.1        pk 
    265        1.1        pk 	/*
    266        1.1        pk 	 * Pull in the options flags.  Allow the user to completely
    267        1.1        pk 	 * override the default values.
    268        1.1        pk 	 */
    269  1.19.16.1       mjf 	if ((device_cfdata(self)->cf_flags & SI_OPTIONS_MASK) != 0)
    270        1.1        pk 		sc->sc_options =
    271  1.19.16.1       mjf 		    device_cfdata(self)->cf_flags & SI_OPTIONS_MASK;
    272        1.1        pk 
    273        1.1        pk 	/*
    274        1.1        pk 	 * Initialize fields used by the MI code
    275        1.1        pk 	 */
    276        1.1        pk 
    277        1.1        pk 	/* NCR5380 register bank offsets */
    278        1.1        pk 	ncr_sc->sci_r0 = 0;
    279        1.1        pk 	ncr_sc->sci_r1 = 1;
    280        1.1        pk 	ncr_sc->sci_r2 = 2;
    281        1.1        pk 	ncr_sc->sci_r3 = 3;
    282        1.1        pk 	ncr_sc->sci_r4 = 4;
    283        1.1        pk 	ncr_sc->sci_r5 = 5;
    284        1.1        pk 	ncr_sc->sci_r6 = 6;
    285        1.1        pk 	ncr_sc->sci_r7 = 7;
    286        1.1        pk 
    287        1.1        pk 	ncr_sc->sc_rev = NCR_VARIANT_NCR5380;
    288        1.1        pk 
    289        1.1        pk 	/*
    290        1.1        pk 	 * MD function pointers used by the MI code.
    291        1.1        pk 	 */
    292        1.1        pk 	ncr_sc->sc_pio_out = ncr5380_pio_out;
    293        1.1        pk 	ncr_sc->sc_pio_in =  ncr5380_pio_in;
    294        1.1        pk 	ncr_sc->sc_dma_alloc = si_dma_alloc;
    295        1.1        pk 	ncr_sc->sc_dma_free  = si_dma_free;
    296        1.1        pk 	ncr_sc->sc_dma_poll  = si_dma_poll;
    297        1.1        pk 
    298        1.1        pk 	ncr_sc->sc_flags = 0;
    299        1.1        pk 	if ((sc->sc_options & SI_DO_RESELECT) == 0)
    300        1.1        pk 		ncr_sc->sc_no_disconnect = 0xFF;
    301        1.1        pk 	if ((sc->sc_options & SI_DMA_INTR) == 0)
    302        1.1        pk 		ncr_sc->sc_flags |= NCR5380_FORCE_POLLING;
    303        1.1        pk 	ncr_sc->sc_min_dma_len = MIN_DMA_LEN;
    304        1.1        pk 
    305        1.1        pk 	/*
    306        1.1        pk 	 * Allocate DMA handles.
    307        1.1        pk 	 */
    308        1.1        pk 	i = SCI_OPENINGS * sizeof(struct si_dma_handle);
    309  1.19.16.1       mjf 	sc->sc_dma = malloc(i, M_DEVBUF, M_NOWAIT);
    310        1.1        pk 	if (sc->sc_dma == NULL)
    311       1.13       wiz 		panic("si: DMA handle malloc failed");
    312        1.1        pk 
    313        1.1        pk 	for (i = 0; i < SCI_OPENINGS; i++) {
    314        1.1        pk 		sc->sc_dma[i].dh_flags = 0;
    315        1.1        pk 
    316        1.1        pk 		/* Allocate a DMA handle */
    317        1.1        pk 		if (vme_dmamap_create(
    318        1.1        pk 				sc->sc_vctag,	/* VME chip tag */
    319        1.1        pk 				MAXPHYS,	/* size */
    320        1.1        pk 				VME_AM_A24,	/* address modifier */
    321        1.1        pk 				VME_D16,	/* data size */
    322        1.1        pk 				0,		/* swap */
    323        1.1        pk 				1,		/* nsegments */
    324        1.1        pk 				MAXPHYS,	/* maxsegsz */
    325        1.1        pk 				0,		/* boundary */
    326        1.1        pk 				BUS_DMA_NOWAIT,
    327        1.1        pk 				&sc->sc_dma[i].dh_dmamap) != 0) {
    328        1.1        pk 
    329  1.19.16.1       mjf 			aprint_error_dev(self, "DMA buffer map create error\n");
    330        1.1        pk 			return;
    331        1.1        pk 		}
    332        1.1        pk 	}
    333        1.1        pk 
    334        1.1        pk 	if (sc->sc_options) {
    335  1.19.16.2       mjf 		snprintb(bits, sizeof(bits), SI_OPTIONS_BITS, sc->sc_options);
    336  1.19.16.2       mjf 		aprint_normal_dev(self, "options=%s\n", bits);
    337        1.1        pk 	}
    338        1.1        pk 
    339        1.3    bouyer 	ncr_sc->sc_channel.chan_id = 7;
    340        1.3    bouyer 	ncr_sc->sc_adapter.adapt_minphys = minphys;
    341        1.1        pk 
    342        1.1        pk 	/*
    343        1.1        pk 	 *  Initialize si board itself.
    344        1.1        pk 	 */
    345        1.1        pk 	si_reset_adapter(ncr_sc);
    346        1.1        pk 	ncr5380_attach(ncr_sc);
    347        1.1        pk 
    348        1.1        pk 	if (sc->sc_options & SI_DO_RESELECT) {
    349        1.1        pk 		/*
    350        1.1        pk 		 * Need to enable interrupts (and DMA!)
    351        1.1        pk 		 * on this H/W for reselect to work.
    352        1.1        pk 		 */
    353        1.1        pk 		ncr_sc->sc_intr_on   = si_intr_on;
    354        1.1        pk 		ncr_sc->sc_intr_off  = si_intr_off;
    355        1.1        pk 	}
    356        1.1        pk }
    357        1.1        pk 
    358        1.1        pk #define CSR_WANT (SI_CSR_SBC_IP | SI_CSR_DMA_IP | \
    359        1.1        pk 	SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR )
    360        1.1        pk 
    361        1.1        pk static int
    362        1.1        pk si_intr(void *arg)
    363        1.1        pk {
    364        1.1        pk 	struct si_softc *sc = arg;
    365  1.19.16.1       mjf 	struct ncr5380_softc *ncr_sc = &sc->ncr_sc;
    366        1.1        pk 	int dma_error, claimed;
    367  1.19.16.1       mjf 	uint16_t csr;
    368        1.1        pk 
    369        1.1        pk 	claimed = 0;
    370        1.1        pk 	dma_error = 0;
    371        1.1        pk 
    372        1.1        pk 	/* SBC interrupt? DMA interrupt? */
    373        1.1        pk 	csr = SIREG_READ(ncr_sc, SIREG_CSR);
    374        1.1        pk 
    375        1.1        pk 	NCR_TRACE("si_intr: csr=0x%x\n", csr);
    376        1.1        pk 
    377        1.1        pk 	if (csr & SI_CSR_DMA_CONFLICT) {
    378        1.1        pk 		dma_error |= SI_CSR_DMA_CONFLICT;
    379  1.19.16.1       mjf 		printf("%s: DMA conflict\n", __func__);
    380        1.1        pk 	}
    381        1.1        pk 	if (csr & SI_CSR_DMA_BUS_ERR) {
    382        1.1        pk 		dma_error |= SI_CSR_DMA_BUS_ERR;
    383  1.19.16.1       mjf 		printf("%s: DMA bus error\n", __func__);
    384        1.1        pk 	}
    385        1.1        pk 	if (dma_error) {
    386        1.1        pk 		if (sc->ncr_sc.sc_state & NCR_DOINGDMA)
    387        1.1        pk 			sc->ncr_sc.sc_state |= NCR_ABORTING;
    388        1.1        pk 		/* Make sure we will call the main isr. */
    389        1.1        pk 		csr |= SI_CSR_DMA_IP;
    390        1.1        pk 	}
    391        1.1        pk 
    392        1.1        pk 	if (csr & (SI_CSR_SBC_IP | SI_CSR_DMA_IP)) {
    393        1.1        pk 		claimed = ncr5380_intr(&sc->ncr_sc);
    394        1.1        pk #ifdef DEBUG
    395        1.1        pk 		if (!claimed) {
    396  1.19.16.1       mjf 			printf("%s: spurious from SBC\n", __func__);
    397        1.1        pk 			if (si_debug & 4) {
    398        1.1        pk 				Debugger();	/* XXX */
    399        1.1        pk 			}
    400        1.1        pk 		}
    401        1.1        pk #endif
    402        1.1        pk 	}
    403        1.1        pk 
    404  1.19.16.1       mjf 	return claimed;
    405        1.1        pk }
    406        1.1        pk 
    407        1.1        pk 
    408        1.1        pk static void
    409        1.1        pk si_reset_adapter(struct ncr5380_softc *ncr_sc)
    410        1.1        pk {
    411        1.1        pk 	struct si_softc *sc = (struct si_softc *)ncr_sc;
    412        1.1        pk 
    413        1.1        pk #ifdef	DEBUG
    414        1.1        pk 	if (si_debug) {
    415  1.19.16.1       mjf 		printf("%s\n", __func__);
    416        1.1        pk 	}
    417        1.1        pk #endif
    418        1.1        pk 
    419        1.1        pk 	/*
    420        1.1        pk 	 * The SCSI3 controller has an 8K FIFO to buffer data between the
    421        1.1        pk 	 * 5380 and the DMA.  Make sure it starts out empty.
    422        1.1        pk 	 *
    423        1.1        pk 	 * The reset bits in the CSR are active low.
    424        1.1        pk 	 */
    425        1.1        pk 	SIREG_WRITE(ncr_sc, SIREG_CSR, 0);
    426        1.1        pk 	delay(10);
    427        1.1        pk 	SIREG_WRITE(ncr_sc, SIREG_CSR,
    428  1.19.16.1       mjf 	    SI_CSR_FIFO_RES | SI_CSR_SCSI_RES | SI_CSR_INTR_EN);
    429        1.1        pk 	delay(10);
    430        1.1        pk 
    431        1.1        pk 	SIREG_WRITE(ncr_sc, SIREG_FIFO_CNT, 0);
    432        1.1        pk 	SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRH, 0);
    433        1.1        pk 	SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRL, 0);
    434        1.1        pk 	SIREG_WRITE(ncr_sc, SIREG_DMA_CNTH, 0);
    435        1.1        pk 	SIREG_WRITE(ncr_sc, SIREG_DMA_CNTL, 0);
    436        1.1        pk 	SIREG_WRITE(ncr_sc, SIREG_IV_AM, sc->sc_adapter_iv_am);
    437        1.1        pk 	SIREG_WRITE(ncr_sc, SIREG_FIFO_CNTH, 0);
    438        1.1        pk 
    439        1.1        pk 	SCI_CLR_INTR(ncr_sc);
    440        1.1        pk }
    441        1.1        pk 
    442        1.1        pk /*****************************************************************
    443        1.1        pk  * Common functions for DMA
    444        1.1        pk  ****************************************************************/
    445        1.1        pk 
    446        1.1        pk /*
    447        1.1        pk  * Allocate a DMA handle and put it in sc->sc_dma.  Prepare
    448        1.1        pk  * for DMA transfer.
    449        1.1        pk  */
    450        1.1        pk void
    451  1.19.16.1       mjf si_dma_alloc(struct ncr5380_softc *ncr_sc)
    452        1.1        pk {
    453        1.1        pk 	struct si_softc *sc = (struct si_softc *)ncr_sc;
    454        1.1        pk 	struct sci_req *sr = ncr_sc->sc_current;
    455        1.1        pk 	struct scsipi_xfer *xs = sr->sr_xs;
    456        1.1        pk 	struct si_dma_handle *dh;
    457        1.1        pk 	int i, xlen;
    458        1.1        pk 	u_long addr;
    459        1.1        pk 
    460        1.1        pk #ifdef DIAGNOSTIC
    461        1.1        pk 	if (sr->sr_dma_hand != NULL)
    462  1.19.16.1       mjf 		panic("%s: already have DMA handle", __func__);
    463        1.1        pk #endif
    464        1.1        pk 
    465        1.1        pk #if 1	/* XXX - Temporary */
    466        1.1        pk 	/* XXX - In case we think DMA is completely broken... */
    467        1.1        pk 	if ((sc->sc_options & SI_ENABLE_DMA) == 0)
    468        1.1        pk 		return;
    469        1.1        pk #endif
    470        1.1        pk 
    471  1.19.16.1       mjf 	addr = (u_long)ncr_sc->sc_dataptr;
    472        1.1        pk 	xlen = ncr_sc->sc_datalen;
    473        1.1        pk 
    474        1.1        pk 	/* If the DMA start addr is misaligned then do PIO */
    475        1.1        pk 	if ((addr & 1) || (xlen & 1)) {
    476  1.19.16.1       mjf 		printf("%s: misaligned.\n", __func__);
    477        1.1        pk 		return;
    478        1.1        pk 	}
    479        1.1        pk 
    480        1.1        pk 	/* Make sure our caller checked sc_min_dma_len. */
    481        1.1        pk 	if (xlen < MIN_DMA_LEN)
    482  1.19.16.1       mjf 		panic("%s: xlen=0x%x", __func__, xlen);
    483        1.1        pk 
    484        1.1        pk 	/* Find free DMA handle.  Guaranteed to find one since we have
    485        1.1        pk 	   as many DMA handles as the driver has processes. */
    486        1.1        pk 	for (i = 0; i < SCI_OPENINGS; i++) {
    487        1.1        pk 		if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0)
    488        1.1        pk 			goto found;
    489        1.1        pk 	}
    490        1.1        pk 	panic("si: no free DMA handles.");
    491        1.1        pk 
    492        1.1        pk found:
    493        1.1        pk 	dh = &sc->sc_dma[i];
    494        1.1        pk 	dh->dh_flags = SIDH_BUSY;
    495        1.1        pk 	dh->dh_maplen  = xlen;
    496        1.1        pk 
    497        1.1        pk 	/* Copy the "write" flag for convenience. */
    498        1.1        pk 	if ((xs->xs_control & XS_CTL_DATA_OUT) != 0)
    499        1.1        pk 		dh->dh_flags |= SIDH_OUT;
    500        1.1        pk 
    501        1.1        pk 	/*
    502        1.1        pk 	 * Double-map the buffer into DVMA space.  If we can't re-map
    503        1.1        pk 	 * the buffer, we print a warning and fall back to PIO mode.
    504        1.1        pk 	 *
    505        1.1        pk 	 * NOTE: it is not safe to sleep here!
    506        1.1        pk 	 */
    507        1.1        pk 	if (bus_dmamap_load(sc->sc_dmatag, dh->dh_dmamap,
    508       1.18  christos 			    (void *)addr, xlen, NULL, BUS_DMA_NOWAIT) != 0) {
    509        1.1        pk 		/* Can't remap segment */
    510  1.19.16.1       mjf 		printf("%s: can't remap 0x%lx/0x%x, doing PIO\n",
    511  1.19.16.1       mjf 		    __func__, addr, dh->dh_maplen);
    512        1.1        pk 		dh->dh_flags = 0;
    513        1.1        pk 		return;
    514        1.1        pk 	}
    515        1.1        pk 	bus_dmamap_sync(sc->sc_dmatag, dh->dh_dmamap, addr, xlen,
    516        1.1        pk 			(dh->dh_flags & SIDH_OUT)
    517        1.1        pk 				? BUS_DMASYNC_PREWRITE
    518        1.1        pk 				: BUS_DMASYNC_PREREAD);
    519        1.1        pk 
    520        1.1        pk 	/* success */
    521        1.1        pk 	sr->sr_dma_hand = dh;
    522        1.1        pk }
    523        1.1        pk 
    524        1.1        pk 
    525        1.1        pk void
    526  1.19.16.1       mjf si_dma_free(struct ncr5380_softc *ncr_sc)
    527        1.1        pk {
    528        1.1        pk 	struct si_softc *sc = (struct si_softc *)ncr_sc;
    529        1.1        pk 	struct sci_req *sr = ncr_sc->sc_current;
    530        1.1        pk 	struct si_dma_handle *dh = sr->sr_dma_hand;
    531        1.1        pk 
    532        1.1        pk #ifdef DIAGNOSTIC
    533        1.1        pk 	if (dh == NULL)
    534  1.19.16.1       mjf 		panic("%s: no DMA handle", __func__);
    535        1.1        pk #endif
    536        1.1        pk 
    537        1.1        pk 	if (ncr_sc->sc_state & NCR_DOINGDMA)
    538  1.19.16.1       mjf 		panic("%s: free while in progress", __func__);
    539        1.1        pk 
    540        1.1        pk 	if (dh->dh_flags & SIDH_BUSY) {
    541        1.1        pk 		/* Give back the DVMA space. */
    542        1.1        pk 		bus_dmamap_sync(sc->sc_dmatag, dh->dh_dmamap,
    543        1.1        pk 				dh->dh_dvma, dh->dh_maplen,
    544        1.1        pk 				(dh->dh_flags & SIDH_OUT)
    545        1.1        pk 					? BUS_DMASYNC_POSTWRITE
    546        1.1        pk 					: BUS_DMASYNC_POSTREAD);
    547        1.1        pk 		bus_dmamap_unload(sc->sc_dmatag, dh->dh_dmamap);
    548        1.1        pk 		dh->dh_flags = 0;
    549        1.1        pk 	}
    550        1.1        pk 	sr->sr_dma_hand = NULL;
    551        1.1        pk }
    552        1.1        pk 
    553        1.1        pk 
    554        1.1        pk /*
    555        1.1        pk  * Poll (spin-wait) for DMA completion.
    556        1.1        pk  * Called right after xx_dma_start(), and
    557        1.1        pk  * xx_dma_stop() will be called next.
    558        1.1        pk  * Same for either VME or OBIO.
    559        1.1        pk  */
    560        1.1        pk void
    561  1.19.16.1       mjf si_dma_poll(struct ncr5380_softc *ncr_sc)
    562        1.1        pk {
    563        1.1        pk 	struct sci_req *sr = ncr_sc->sc_current;
    564        1.1        pk 	int tmo, csr_mask, csr;
    565        1.1        pk 
    566        1.1        pk 	/* Make sure DMA started successfully. */
    567        1.1        pk 	if (ncr_sc->sc_state & NCR_ABORTING)
    568        1.1        pk 		return;
    569        1.1        pk 
    570        1.1        pk 	csr_mask = SI_CSR_SBC_IP | SI_CSR_DMA_IP |
    571        1.1        pk 		SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR;
    572        1.1        pk 
    573        1.1        pk 	tmo = 50000;	/* X100 = 5 sec. */
    574        1.1        pk 	for (;;) {
    575        1.1        pk 		csr = SIREG_READ(ncr_sc, SIREG_CSR);
    576        1.1        pk 		if (csr & csr_mask)
    577        1.1        pk 			break;
    578        1.1        pk 		if (--tmo <= 0) {
    579        1.1        pk 			printf("%s: DMA timeout (while polling)\n",
    580  1.19.16.1       mjf 			    device_xname(ncr_sc->sc_dev));
    581        1.1        pk 			/* Indicate timeout as MI code would. */
    582        1.1        pk 			sr->sr_flags |= SR_OVERDUE;
    583        1.1        pk 			break;
    584        1.1        pk 		}
    585        1.1        pk 		delay(100);
    586        1.1        pk 	}
    587        1.1        pk 
    588        1.1        pk #ifdef	DEBUG
    589        1.1        pk 	if (si_debug) {
    590  1.19.16.1       mjf 		printf("%s: done, csr=0x%x\n", __func__, csr);
    591        1.1        pk 	}
    592        1.1        pk #endif
    593        1.1        pk }
    594        1.1        pk 
    595        1.1        pk 
    596        1.1        pk /*****************************************************************
    597        1.1        pk  * VME functions for DMA
    598        1.1        pk  ****************************************************************/
    599        1.1        pk 
    600        1.1        pk 
    601        1.1        pk /*
    602        1.1        pk  * This is called when the bus is going idle,
    603        1.1        pk  * so we want to enable the SBC interrupts.
    604        1.1        pk  * That is controlled by the DMA enable!
    605        1.1        pk  * Who would have guessed!
    606        1.1        pk  * What a NASTY trick!
    607        1.1        pk  */
    608        1.1        pk void
    609  1.19.16.1       mjf si_intr_on(struct ncr5380_softc *ncr_sc)
    610        1.1        pk {
    611  1.19.16.1       mjf 	uint16_t csr;
    612        1.1        pk 
    613        1.5        pk 	/* Clear DMA start address and counters */
    614        1.5        pk 	SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRH, 0);
    615        1.5        pk 	SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRL, 0);
    616        1.5        pk 	SIREG_WRITE(ncr_sc, SIREG_DMA_CNTH, 0);
    617        1.5        pk 	SIREG_WRITE(ncr_sc, SIREG_DMA_CNTL, 0);
    618        1.5        pk 
    619        1.5        pk 	/* Enter receive mode (for safety) and enable DMA engine */
    620        1.1        pk 	csr = SIREG_READ(ncr_sc, SIREG_CSR);
    621        1.5        pk 	csr &= ~SI_CSR_SEND;
    622        1.1        pk 	csr |= SI_CSR_DMA_EN;
    623        1.1        pk 	SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
    624        1.1        pk }
    625        1.1        pk 
    626        1.1        pk /*
    627        1.1        pk  * This is called when the bus is idle and we are
    628        1.1        pk  * about to start playing with the SBC chip.
    629        1.1        pk  */
    630        1.1        pk void
    631  1.19.16.1       mjf si_intr_off(struct ncr5380_softc *ncr_sc)
    632        1.1        pk {
    633  1.19.16.1       mjf 	uint16_t csr;
    634        1.1        pk 
    635        1.1        pk 	csr = SIREG_READ(ncr_sc, SIREG_CSR);
    636        1.1        pk 	csr &= ~SI_CSR_DMA_EN;
    637        1.1        pk 	SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
    638        1.1        pk }
    639        1.1        pk 
    640        1.1        pk /*
    641        1.1        pk  * This function is called during the COMMAND or MSG_IN phase
    642        1.4       wiz  * that precedes a DATA_IN or DATA_OUT phase, in case we need
    643        1.1        pk  * to setup the DMA engine before the bus enters a DATA phase.
    644        1.1        pk  *
    645        1.1        pk  * XXX: The VME adapter appears to suppress SBC interrupts
    646        1.1        pk  * when the FIFO is not empty or the FIFO count is non-zero!
    647        1.1        pk  *
    648        1.1        pk  * On the VME version we just clear the DMA count and address
    649        1.1        pk  * here (to make sure it stays idle) and do the real setup
    650        1.1        pk  * later, in dma_start.
    651        1.1        pk  */
    652        1.1        pk void
    653  1.19.16.1       mjf si_dma_setup(struct ncr5380_softc *ncr_sc)
    654        1.1        pk {
    655        1.5        pk 	struct si_softc *sc = (struct si_softc *)ncr_sc;
    656        1.5        pk 	struct sci_req *sr = ncr_sc->sc_current;
    657        1.5        pk 	struct si_dma_handle *dh = sr->sr_dma_hand;
    658  1.19.16.1       mjf 	uint16_t csr;
    659        1.5        pk 	u_long dva;
    660        1.5        pk 	int xlen;
    661        1.5        pk 
    662        1.5        pk 	/*
    663        1.5        pk 	 * Set up the DMA controller.
    664        1.5        pk 	 * Note that (dh->dh_len < sc_datalen)
    665        1.5        pk 	 */
    666        1.1        pk 
    667        1.1        pk 	csr = SIREG_READ(ncr_sc, SIREG_CSR);
    668        1.1        pk 
    669        1.5        pk 	/* Disable DMA while we're setting up the transfer */
    670        1.5        pk 	csr &= ~SI_CSR_DMA_EN;
    671        1.5        pk 
    672        1.1        pk 	/* Reset the FIFO */
    673        1.1        pk 	csr &= ~SI_CSR_FIFO_RES;		/* active low */
    674        1.1        pk 	SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
    675        1.1        pk 	csr |= SI_CSR_FIFO_RES;
    676        1.1        pk 	SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
    677        1.1        pk 
    678        1.1        pk 	/*
    679        1.1        pk 	 * Get the DVMA mapping for this segment.
    680        1.1        pk 	 */
    681        1.1        pk 	dva = (u_long)(dh->dh_dvma);
    682        1.1        pk 	if (dva & 1)
    683  1.19.16.1       mjf 		panic("%s: bad dmaaddr=0x%lx", __func__, dva);
    684        1.1        pk 	xlen = ncr_sc->sc_datalen;
    685        1.1        pk 	xlen &= ~1;
    686        1.1        pk 	sc->sc_xlen = xlen;	/* XXX: or less... */
    687        1.1        pk 
    688        1.1        pk #ifdef	DEBUG
    689        1.1        pk 	if (si_debug & 2) {
    690  1.19.16.1       mjf 		printf("%s: dh=%p, dmaaddr=0x%lx, xlen=%d\n",
    691  1.19.16.1       mjf 		    __func__, dh, dva, xlen);
    692        1.1        pk 	}
    693        1.1        pk #endif
    694        1.1        pk 	/* Set direction (send/recv) */
    695        1.1        pk 	if (dh->dh_flags & SIDH_OUT) {
    696        1.1        pk 		csr |= SI_CSR_SEND;
    697        1.1        pk 	} else {
    698        1.1        pk 		csr &= ~SI_CSR_SEND;
    699        1.1        pk 	}
    700        1.1        pk 
    701        1.5        pk 	/* Set byte-packing control */
    702        1.1        pk 	if (dva & 2) {
    703        1.1        pk 		csr |= SI_CSR_BPCON;
    704        1.1        pk 	} else {
    705        1.1        pk 		csr &= ~SI_CSR_BPCON;
    706        1.1        pk 	}
    707        1.5        pk 
    708        1.1        pk 	SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
    709        1.1        pk 
    710        1.5        pk 	/* Load start address */
    711  1.19.16.1       mjf 	SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRH, (uint16_t)(dva >> 16));
    712  1.19.16.1       mjf 	SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRL, (uint16_t)(dva & 0xFFFF));
    713        1.5        pk 
    714        1.5        pk 	/* Clear DMA counters; these will be set in si_dma_start() */
    715        1.5        pk 	SIREG_WRITE(ncr_sc, SIREG_DMA_CNTH, 0);
    716        1.5        pk 	SIREG_WRITE(ncr_sc, SIREG_DMA_CNTL, 0);
    717        1.5        pk 
    718        1.5        pk 	/* Clear FIFO counter. (also hits dma_count) */
    719        1.5        pk 	SIREG_WRITE(ncr_sc, SIREG_FIFO_CNTH, 0);
    720        1.5        pk 	SIREG_WRITE(ncr_sc, SIREG_FIFO_CNT, 0);
    721        1.5        pk }
    722        1.5        pk 
    723        1.5        pk 
    724        1.5        pk void
    725  1.19.16.1       mjf si_dma_start(struct ncr5380_softc *ncr_sc)
    726        1.5        pk {
    727        1.5        pk 	struct si_softc *sc = (struct si_softc *)ncr_sc;
    728        1.5        pk 	struct sci_req *sr = ncr_sc->sc_current;
    729        1.5        pk 	struct si_dma_handle *dh = sr->sr_dma_hand;
    730        1.5        pk 	int xlen;
    731        1.5        pk 	u_int mode;
    732  1.19.16.1       mjf 	uint16_t csr;
    733        1.5        pk 
    734        1.5        pk 	xlen = sc->sc_xlen;
    735        1.5        pk 
    736        1.5        pk 	/* Load transfer length */
    737  1.19.16.1       mjf 	SIREG_WRITE(ncr_sc, SIREG_DMA_CNTH, (uint16_t)(xlen >> 16));
    738  1.19.16.1       mjf 	SIREG_WRITE(ncr_sc, SIREG_DMA_CNTL, (uint16_t)(xlen & 0xFFFF));
    739  1.19.16.1       mjf 	SIREG_WRITE(ncr_sc, SIREG_FIFO_CNTH, (uint16_t)(xlen >> 16));
    740  1.19.16.1       mjf 	SIREG_WRITE(ncr_sc, SIREG_FIFO_CNT, (uint16_t)(xlen & 0xFFFF));
    741        1.1        pk 
    742        1.1        pk 	/*
    743        1.1        pk 	 * Acknowledge the phase change.  (After DMA setup!)
    744        1.1        pk 	 * Put the SBIC into DMA mode, and start the transfer.
    745        1.1        pk 	 */
    746        1.1        pk 	if (dh->dh_flags & SIDH_OUT) {
    747        1.1        pk 		NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_OUT);
    748        1.1        pk 		SCI_CLR_INTR(ncr_sc);
    749        1.1        pk 		NCR5380_WRITE(ncr_sc, sci_icmd, SCI_ICMD_DATA);
    750        1.1        pk 
    751        1.1        pk 		mode = NCR5380_READ(ncr_sc, sci_mode);
    752        1.1        pk 		mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE);
    753        1.1        pk 		NCR5380_WRITE(ncr_sc, sci_mode, mode);
    754        1.1        pk 
    755        1.1        pk 		NCR5380_WRITE(ncr_sc, sci_dma_send, 0); /* start it */
    756        1.1        pk 	} else {
    757        1.1        pk 		NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_IN);
    758        1.1        pk 		SCI_CLR_INTR(ncr_sc);
    759        1.1        pk 		NCR5380_WRITE(ncr_sc, sci_icmd, 0);
    760        1.1        pk 
    761        1.1        pk 		mode = NCR5380_READ(ncr_sc, sci_mode);
    762        1.1        pk 		mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE);
    763        1.1        pk 		NCR5380_WRITE(ncr_sc, sci_mode, mode);
    764        1.1        pk 
    765        1.1        pk 		NCR5380_WRITE(ncr_sc, sci_irecv, 0); /* start it */
    766        1.1        pk 	}
    767        1.1        pk 
    768        1.5        pk 	ncr_sc->sc_state |= NCR_DOINGDMA;
    769        1.5        pk 
    770        1.1        pk 	/* Enable DMA engine */
    771        1.5        pk 	csr = SIREG_READ(ncr_sc, SIREG_CSR);
    772        1.1        pk 	csr |= SI_CSR_DMA_EN;
    773        1.1        pk 	SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
    774        1.1        pk 
    775        1.1        pk #ifdef	DEBUG
    776        1.1        pk 	if (si_debug & 2) {
    777  1.19.16.1       mjf 		printf("%s: started, flags=0x%x\n",
    778  1.19.16.1       mjf 		    __func__, ncr_sc->sc_state);
    779        1.1        pk 	}
    780        1.1        pk #endif
    781        1.1        pk }
    782        1.1        pk 
    783        1.1        pk 
    784        1.1        pk void
    785  1.19.16.1       mjf si_dma_eop(struct ncr5380_softc *ncr_sc)
    786        1.1        pk {
    787        1.1        pk 
    788        1.1        pk 	/* Not needed - DMA was stopped prior to examining sci_csr */
    789        1.1        pk }
    790        1.1        pk 
    791        1.1        pk 
    792        1.1        pk void
    793  1.19.16.1       mjf si_dma_stop(struct ncr5380_softc *ncr_sc)
    794        1.1        pk {
    795        1.1        pk 	struct si_softc *sc = (struct si_softc *)ncr_sc;
    796        1.1        pk 	struct sci_req *sr = ncr_sc->sc_current;
    797        1.1        pk 	struct si_dma_handle *dh = sr->sr_dma_hand;
    798        1.1        pk 	int resid, ntrans;
    799  1.19.16.1       mjf 	uint16_t csr;
    800        1.1        pk 	u_int mode;
    801        1.1        pk 
    802        1.1        pk 	if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) {
    803        1.1        pk #ifdef	DEBUG
    804  1.19.16.1       mjf 		printf("%s: DMA not running\n", __func__);
    805        1.1        pk #endif
    806        1.1        pk 		return;
    807        1.1        pk 	}
    808        1.1        pk 
    809        1.1        pk 	ncr_sc->sc_state &= ~NCR_DOINGDMA;
    810        1.1        pk 
    811        1.1        pk 	csr = SIREG_READ(ncr_sc, SIREG_CSR);
    812        1.1        pk 
    813        1.1        pk 	/* First, halt the DMA engine. */
    814        1.1        pk 	csr &= ~SI_CSR_DMA_EN;
    815        1.1        pk 	SIREG_WRITE(ncr_sc, SIREG_CSR, csr);
    816        1.1        pk 
    817        1.1        pk 	if (csr & (SI_CSR_DMA_CONFLICT | SI_CSR_DMA_BUS_ERR)) {
    818        1.1        pk 		printf("si: DMA error, csr=0x%x, reset\n", csr);
    819        1.1        pk 		sr->sr_xs->error = XS_DRIVER_STUFFUP;
    820        1.1        pk 		ncr_sc->sc_state |= NCR_ABORTING;
    821        1.1        pk 		si_reset_adapter(ncr_sc);
    822        1.1        pk 	}
    823        1.1        pk 
    824        1.1        pk 	/* Note that timeout may have set the error flag. */
    825        1.1        pk 	if (ncr_sc->sc_state & NCR_ABORTING)
    826        1.1        pk 		goto out;
    827        1.1        pk 
    828        1.1        pk 	/*
    829        1.1        pk 	 * Now try to figure out how much actually transferred
    830        1.1        pk 	 *
    831        1.1        pk 	 * The fifo_count does not reflect how many bytes were
    832        1.1        pk 	 * actually transferred for VME.
    833        1.1        pk 	 *
    834        1.1        pk 	 * SCSI-3 VME interface is a little funny on writes:
    835       1.13       wiz 	 * if we have a disconnect, the DMA has overshot by
    836        1.1        pk 	 * one byte and the resid needs to be incremented.
    837        1.1        pk 	 * Only happens for partial transfers.
    838        1.1        pk 	 * (Thanks to Matt Jacob)
    839        1.1        pk 	 */
    840        1.1        pk 
    841        1.1        pk 	resid = SIREG_READ(ncr_sc, SIREG_FIFO_CNTH) << 16;
    842        1.1        pk 	resid |= SIREG_READ(ncr_sc, SIREG_FIFO_CNT) & 0xFFFF;
    843        1.1        pk 	if (dh->dh_flags & SIDH_OUT)
    844        1.1        pk 		if ((resid > 0) && (resid < sc->sc_xlen))
    845        1.1        pk 			resid++;
    846        1.1        pk 	ntrans = sc->sc_xlen - resid;
    847        1.1        pk 
    848        1.1        pk #ifdef	DEBUG
    849        1.1        pk 	if (si_debug & 2) {
    850  1.19.16.1       mjf 		printf("%s: resid=0x%x ntrans=0x%x\n",
    851  1.19.16.1       mjf 		    __func__, resid, ntrans);
    852        1.1        pk 	}
    853        1.1        pk #endif
    854        1.1        pk 
    855        1.1        pk 	if (ntrans > ncr_sc->sc_datalen)
    856  1.19.16.1       mjf 		panic("%s: excess transfer", __func__);
    857        1.1        pk 
    858        1.1        pk 	/* Adjust data pointer */
    859        1.1        pk 	ncr_sc->sc_dataptr += ntrans;
    860        1.1        pk 	ncr_sc->sc_datalen -= ntrans;
    861        1.1        pk 
    862        1.1        pk #ifdef	DEBUG
    863        1.1        pk 	if (si_debug & 2) {
    864  1.19.16.1       mjf 		printf("%s: ntrans=0x%x\n", __func__, ntrans);
    865        1.1        pk 	}
    866        1.1        pk #endif
    867        1.1        pk 
    868        1.1        pk 	/*
    869        1.1        pk 	 * After a read, we may need to clean-up
    870        1.1        pk 	 * "Left-over bytes" (yuck!)
    871        1.1        pk 	 */
    872        1.1        pk 	if (((dh->dh_flags & SIDH_OUT) == 0) &&
    873  1.19.16.1       mjf 		((csr & SI_CSR_LOB) != 0)) {
    874  1.19.16.1       mjf 		uint8_t *cp = ncr_sc->sc_dataptr;
    875  1.19.16.1       mjf 		uint16_t bprh, bprl;
    876        1.1        pk 
    877        1.1        pk 		bprh = SIREG_READ(ncr_sc, SIREG_BPRH);
    878        1.1        pk 		bprl = SIREG_READ(ncr_sc, SIREG_BPRL);
    879        1.1        pk 
    880        1.1        pk #ifdef DEBUG
    881        1.1        pk 		printf("si: got left-over bytes: bprh=%x, bprl=%x, csr=%x\n",
    882        1.1        pk 			bprh, bprl, csr);
    883        1.1        pk #endif
    884        1.1        pk 
    885        1.1        pk 		if (csr & SI_CSR_BPCON) {
    886        1.1        pk 			/* have SI_CSR_BPCON */
    887        1.1        pk 			cp[-1] = (bprl & 0xff00) >> 8;
    888        1.1        pk 		} else {
    889        1.1        pk 			switch (csr & SI_CSR_LOB) {
    890        1.1        pk 			case SI_CSR_LOB_THREE:
    891        1.1        pk 				cp[-3] = (bprh & 0xff00) >> 8;
    892        1.1        pk 				cp[-2] = (bprh & 0x00ff);
    893        1.1        pk 				cp[-1] = (bprl & 0xff00) >> 8;
    894        1.1        pk 				break;
    895        1.1        pk 			case SI_CSR_LOB_TWO:
    896        1.1        pk 				cp[-2] = (bprh & 0xff00) >> 8;
    897        1.1        pk 				cp[-1] = (bprh & 0x00ff);
    898        1.1        pk 				break;
    899        1.1        pk 			case SI_CSR_LOB_ONE:
    900        1.1        pk 				cp[-1] = (bprh & 0xff00) >> 8;
    901        1.1        pk 				break;
    902        1.1        pk 			}
    903        1.1        pk 		}
    904        1.1        pk 	}
    905        1.1        pk 
    906        1.1        pk out:
    907        1.1        pk 	SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRH, 0);
    908        1.1        pk 	SIREG_WRITE(ncr_sc, SIREG_DMA_ADDRL, 0);
    909        1.1        pk 
    910        1.1        pk 	SIREG_WRITE(ncr_sc, SIREG_DMA_CNTH, 0);
    911        1.1        pk 	SIREG_WRITE(ncr_sc, SIREG_DMA_CNTL, 0);
    912        1.1        pk 
    913        1.1        pk 	SIREG_WRITE(ncr_sc, SIREG_FIFO_CNTH, 0);
    914        1.1        pk 	SIREG_WRITE(ncr_sc, SIREG_FIFO_CNT, 0);
    915        1.1        pk 
    916        1.1        pk 	mode = NCR5380_READ(ncr_sc, sci_mode);
    917        1.1        pk 	/* Put SBIC back in PIO mode. */
    918        1.1        pk 	mode &= ~(SCI_MODE_DMA | SCI_MODE_DMA_IE);
    919        1.1        pk 	NCR5380_WRITE(ncr_sc, sci_mode, mode);
    920        1.1        pk 	NCR5380_WRITE(ncr_sc, sci_icmd, 0);
    921        1.1        pk }
    922