dmtbinfo2.c revision 1.1.1.12
1 /****************************************************************************** 2 * 3 * Module Name: dmtbinfo2 - Table info for non-AML tables 4 * 5 *****************************************************************************/ 6 7 /* 8 * Copyright (C) 2000 - 2023, Intel Corp. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 */ 43 44 #include "acpi.h" 45 #include "accommon.h" 46 #include "acdisasm.h" 47 #include "actbinfo.h" 48 49 /* This module used for application-level code only */ 50 51 #define _COMPONENT ACPI_CA_DISASSEMBLER 52 ACPI_MODULE_NAME ("dmtbinfo2") 53 54 /* 55 * How to add a new table: 56 * 57 * - Add the C table definition to the actbl1.h or actbl2.h header. 58 * - Add ACPI_xxxx_OFFSET macro(s) for the table (and subtables) to list below. 59 * - Define the table in this file (for the disassembler). If any 60 * new data types are required (ACPI_DMT_*), see below. 61 * - Add an external declaration for the new table definition (AcpiDmTableInfo*) 62 * in acdisam.h 63 * - Add new table definition to the dispatch table in dmtable.c (AcpiDmTableData) 64 * If a simple table (with no subtables), no disassembly code is needed. 65 * Otherwise, create the AcpiDmDump* function for to disassemble the table 66 * and add it to the dmtbdump.c file. 67 * - Add an external declaration for the new AcpiDmDump* function in acdisasm.h 68 * - Add the new AcpiDmDump* function to the dispatch table in dmtable.c 69 * - Create a template for the new table 70 * - Add data table compiler support 71 * 72 * How to add a new data type (ACPI_DMT_*): 73 * 74 * - Add new type at the end of the ACPI_DMT list in acdisasm.h 75 * - Add length and implementation cases in dmtable.c (disassembler) 76 * - Add type and length cases in dtutils.c (DT compiler) 77 */ 78 79 /* 80 * Remaining tables are not consumed directly by the ACPICA subsystem 81 */ 82 83 /******************************************************************************* 84 * 85 * AGDI - Arm Generic Diagnostic Dump and Reset Device Interface 86 * 87 * Conforms to "ACPI for Arm Components 1.1, Platform Design Document" 88 * ARM DEN0093 v1.1 89 * 90 ******************************************************************************/ 91 92 ACPI_DMTABLE_INFO AcpiDmTableInfoAgdi[] = 93 { 94 {ACPI_DMT_UINT8, ACPI_AGDI_OFFSET (Flags), "Flags (decoded below)", 0}, 95 {ACPI_DMT_FLAG0, ACPI_AGDI_FLAG_OFFSET (Flags, 0), "Signalling mode", 0}, 96 {ACPI_DMT_UINT24, ACPI_AGDI_OFFSET (Reserved[0]), "Reserved", 0}, 97 {ACPI_DMT_UINT32, ACPI_AGDI_OFFSET (SdeiEvent), "SdeiEvent", 0}, 98 {ACPI_DMT_UINT32, ACPI_AGDI_OFFSET (Gsiv), "Gsiv", 0}, 99 ACPI_DMT_TERMINATOR 100 }; 101 102 103 /******************************************************************************* 104 * 105 * APMT - ARM Performance Monitoring Unit Table 106 * 107 * Conforms to: 108 * ARM Performance Monitoring Unit Architecture 1.0 Platform Design Document 109 * ARM DEN0117 v1.0 November 25, 2021 110 * 111 ******************************************************************************/ 112 113 ACPI_DMTABLE_INFO AcpiDmTableInfoApmtNode[] = 114 { 115 {ACPI_DMT_UINT16, ACPI_APMTN_OFFSET (Length), "Length of APMT Node", 0}, 116 {ACPI_DMT_UINT8, ACPI_APMTN_OFFSET (Flags), "Node Flags", 0}, 117 {ACPI_DMT_FLAG0, ACPI_APMTN_FLAG_OFFSET (Flags, 0), "Dual Page Extension", 0}, 118 {ACPI_DMT_FLAG1, ACPI_APMTN_FLAG_OFFSET (Flags, 0), "Processor Affinity Type", 0}, 119 {ACPI_DMT_FLAG2, ACPI_APMTN_FLAG_OFFSET (Flags, 0), "64-bit Atomic Support", 0}, 120 {ACPI_DMT_UINT8, ACPI_APMTN_OFFSET (Type), "Node Type", 0}, 121 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (Id), "Unique Node Identifier", 0}, 122 {ACPI_DMT_UINT64, ACPI_APMTN_OFFSET (InstPrimary), "Primary Node Instance", 0}, 123 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (InstSecondary), "Secondary Node Instance", 0}, 124 {ACPI_DMT_UINT64, ACPI_APMTN_OFFSET (BaseAddress0), "Page 0 Base Address", 0}, 125 {ACPI_DMT_UINT64, ACPI_APMTN_OFFSET (BaseAddress1), "Page 1 Base Address", 0}, 126 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (OvflwIrq), "Overflow Interrupt ID", 0}, 127 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (Reserved), "Reserved", 0}, 128 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (OvflwIrqFlags), "Overflow Interrupt Flags", 0}, 129 {ACPI_DMT_FLAG0, ACPI_APMTN_FLAG_OFFSET (OvflwIrqFlags, 0), "Interrupt Mode", 0}, 130 {ACPI_DMT_FLAG1, ACPI_APMTN_FLAG_OFFSET (OvflwIrqFlags, 0), "Interrupt Type", 0}, 131 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (ProcAffinity), "Processor Affinity", 0}, 132 {ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (ImplId), "Implementation ID", 0}, 133 ACPI_DMT_TERMINATOR 134 }; 135 136 137 /******************************************************************************* 138 * 139 * IORT - IO Remapping Table 140 * 141 ******************************************************************************/ 142 143 ACPI_DMTABLE_INFO AcpiDmTableInfoIort[] = 144 { 145 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (NodeCount), "Node Count", 0}, 146 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (NodeOffset), "Node Offset", 0}, 147 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (Reserved), "Reserved", 0}, 148 ACPI_DMT_TERMINATOR 149 }; 150 151 /* Optional padding field */ 152 153 ACPI_DMTABLE_INFO AcpiDmTableInfoIortPad[] = 154 { 155 {ACPI_DMT_RAW_BUFFER, 0, "Optional Padding", DT_OPTIONAL}, 156 ACPI_DMT_TERMINATOR 157 }; 158 159 /* Common Subtable header (one per Subtable) */ 160 161 ACPI_DMTABLE_INFO AcpiDmTableInfoIortHdr[] = 162 { 163 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Type), "Type", 0}, 164 {ACPI_DMT_UINT16, ACPI_IORTH_OFFSET (Length), "Length", DT_LENGTH}, 165 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Revision), "Revision", 0}, 166 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (Identifier), "Reserved", 0}, 167 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingCount), "Mapping Count", 0}, 168 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingOffset), "Mapping Offset", 0}, 169 ACPI_DMT_TERMINATOR 170 }; 171 172 /* Common Subtable header (one per Subtable)- Revision 3 */ 173 174 ACPI_DMTABLE_INFO AcpiDmTableInfoIortHdr3[] = 175 { 176 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Type), "Type", 0}, 177 {ACPI_DMT_UINT16, ACPI_IORTH_OFFSET (Length), "Length", DT_LENGTH}, 178 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Revision), "Revision", 0}, 179 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (Identifier), "Identifier", 0}, 180 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingCount), "Mapping Count", 0}, 181 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingOffset), "Mapping Offset", 0}, 182 ACPI_DMT_TERMINATOR 183 }; 184 185 ACPI_DMTABLE_INFO AcpiDmTableInfoIortMap[] = 186 { 187 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (InputBase), "Input base", DT_OPTIONAL}, 188 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (IdCount), "ID Count", 0}, 189 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (OutputBase), "Output Base", 0}, 190 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (OutputReference), "Output Reference", 0}, 191 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (Flags), "Flags (decoded below)", 0}, 192 {ACPI_DMT_FLAG0, ACPI_IORTM_FLAG_OFFSET (Flags, 0), "Single Mapping", 0}, 193 ACPI_DMT_TERMINATOR 194 }; 195 196 ACPI_DMTABLE_INFO AcpiDmTableInfoIortAcc[] = 197 { 198 {ACPI_DMT_UINT32, ACPI_IORTA_OFFSET (CacheCoherency), "Cache Coherency", 0}, 199 {ACPI_DMT_UINT8, ACPI_IORTA_OFFSET (Hints), "Hints (decoded below)", 0}, 200 {ACPI_DMT_FLAG0, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Transient", 0}, 201 {ACPI_DMT_FLAG1, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Write Allocate", 0}, 202 {ACPI_DMT_FLAG2, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Read Allocate", 0}, 203 {ACPI_DMT_FLAG3, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Override", 0}, 204 {ACPI_DMT_UINT16, ACPI_IORTA_OFFSET (Reserved), "Reserved", 0}, 205 {ACPI_DMT_UINT8, ACPI_IORTA_OFFSET (MemoryFlags), "Memory Flags (decoded below)", 0}, 206 {ACPI_DMT_FLAG0, ACPI_IORTA_FLAG_OFFSET (MemoryFlags, 0), "Coherency", 0}, 207 {ACPI_DMT_FLAG1, ACPI_IORTA_FLAG_OFFSET (MemoryFlags, 0), "Device Attribute", 0}, 208 ACPI_DMT_TERMINATOR 209 }; 210 211 /* IORT subtables */ 212 213 /* 0x00: ITS Group */ 214 215 ACPI_DMTABLE_INFO AcpiDmTableInfoIort0[] = 216 { 217 {ACPI_DMT_UINT32, ACPI_IORT0_OFFSET (ItsCount), "ItsCount", 0}, 218 ACPI_DMT_TERMINATOR 219 }; 220 221 ACPI_DMTABLE_INFO AcpiDmTableInfoIort0a[] = 222 { 223 {ACPI_DMT_UINT32, 0, "Identifiers", DT_OPTIONAL}, 224 ACPI_DMT_TERMINATOR 225 }; 226 227 /* 0x01: Named Component */ 228 229 ACPI_DMTABLE_INFO AcpiDmTableInfoIort1[] = 230 { 231 {ACPI_DMT_UINT32, ACPI_IORT1_OFFSET (NodeFlags), "Node Flags", 0}, 232 {ACPI_DMT_IORTMEM, ACPI_IORT1_OFFSET (MemoryProperties), "Memory Properties", 0}, 233 {ACPI_DMT_UINT8, ACPI_IORT1_OFFSET (MemoryAddressLimit), "Memory Size Limit", 0}, 234 {ACPI_DMT_STRING, ACPI_IORT1_OFFSET (DeviceName[0]), "Device Name", 0}, 235 ACPI_DMT_TERMINATOR 236 }; 237 238 ACPI_DMTABLE_INFO AcpiDmTableInfoIort1a[] = 239 { 240 {ACPI_DMT_RAW_BUFFER, 0, "Padding", DT_OPTIONAL}, 241 ACPI_DMT_TERMINATOR 242 }; 243 244 /* 0x02: PCI Root Complex */ 245 246 ACPI_DMTABLE_INFO AcpiDmTableInfoIort2[] = 247 { 248 {ACPI_DMT_IORTMEM, ACPI_IORT2_OFFSET (MemoryProperties), "Memory Properties", 0}, 249 {ACPI_DMT_UINT32, ACPI_IORT2_OFFSET (AtsAttribute), "ATS Attribute", 0}, 250 {ACPI_DMT_UINT32, ACPI_IORT2_OFFSET (PciSegmentNumber), "PCI Segment Number", 0}, 251 {ACPI_DMT_UINT8, ACPI_IORT2_OFFSET (MemoryAddressLimit), "Memory Size Limit", 0}, 252 {ACPI_DMT_UINT16, ACPI_IORT2_OFFSET (PasidCapabilities), "PASID Capabilities", 0}, 253 {ACPI_DMT_UINT8, ACPI_IORT2_OFFSET (Reserved[0]), "Reserved", 0}, 254 ACPI_DMT_TERMINATOR 255 }; 256 257 /* 0x03: SMMUv1/2 */ 258 259 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3[] = 260 { 261 {ACPI_DMT_UINT64, ACPI_IORT3_OFFSET (BaseAddress), "Base Address", 0}, 262 {ACPI_DMT_UINT64, ACPI_IORT3_OFFSET (Span), "Span", 0}, 263 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (Model), "Model", 0}, 264 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (Flags), "Flags (decoded below)", 0}, 265 {ACPI_DMT_FLAG0, ACPI_IORT3_FLAG_OFFSET (Flags, 0), "DVM Supported", 0}, 266 {ACPI_DMT_FLAG1, ACPI_IORT3_FLAG_OFFSET (Flags, 0), "Coherent Walk", 0}, 267 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (GlobalInterruptOffset), "Global Interrupt Offset", 0}, 268 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (ContextInterruptCount), "Context Interrupt Count", 0}, 269 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (ContextInterruptOffset), "Context Interrupt Offset", 0}, 270 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (PmuInterruptCount), "PMU Interrupt Count", 0}, 271 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (PmuInterruptOffset), "PMU Interrupt Offset", 0}, 272 ACPI_DMT_TERMINATOR 273 }; 274 275 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3a[] = 276 { 277 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgIrpt), "NSgIrpt", 0}, 278 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgIrptFlags), "NSgIrpt Flags (decoded below)", 0}, 279 {ACPI_DMT_FLAG0, ACPI_IORT3a_FLAG_OFFSET (NSgIrptFlags, 0), "Edge Triggered", 0}, 280 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgCfgIrpt), "NSgCfgIrpt", 0}, 281 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgCfgIrptFlags), "NSgCfgIrpt Flags (decoded below)", 0}, 282 {ACPI_DMT_FLAG0, ACPI_IORT3a_FLAG_OFFSET (NSgCfgIrptFlags, 0), "Edge Triggered", 0}, 283 ACPI_DMT_TERMINATOR 284 }; 285 286 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3b[] = 287 { 288 {ACPI_DMT_UINT64, 0, "Context Interrupt", DT_OPTIONAL}, 289 ACPI_DMT_TERMINATOR 290 }; 291 292 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3c[] = 293 { 294 {ACPI_DMT_UINT64, 0, "PMU Interrupt", DT_OPTIONAL}, 295 ACPI_DMT_TERMINATOR 296 }; 297 298 /* 0x04: SMMUv3 */ 299 300 ACPI_DMTABLE_INFO AcpiDmTableInfoIort4[] = 301 { 302 {ACPI_DMT_UINT64, ACPI_IORT4_OFFSET (BaseAddress), "Base Address", 0}, 303 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Flags), "Flags (decoded below)", 0}, 304 {ACPI_DMT_FLAG0, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "COHACC Override", 0}, 305 {ACPI_DMT_FLAG1, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "HTTU Override", 0}, 306 {ACPI_DMT_FLAG3, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "Proximity Domain Valid", 0}, 307 {ACPI_DMT_FLAG4, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "DeviceID Valid", 0}, 308 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Reserved), "Reserved", 0}, 309 {ACPI_DMT_UINT64, ACPI_IORT4_OFFSET (VatosAddress), "VATOS Address", 0}, 310 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Model), "Model", 0}, 311 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (EventGsiv), "Event GSIV", 0}, 312 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (PriGsiv), "PRI GSIV", 0}, 313 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (GerrGsiv), "GERR GSIV", 0}, 314 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (SyncGsiv), "Sync GSIV", 0}, 315 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Pxm), "Proximity Domain", 0}, 316 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (IdMappingIndex), "Device ID Mapping Index", 0}, 317 ACPI_DMT_TERMINATOR 318 }; 319 320 /* 0x05: PMCG */ 321 322 ACPI_DMTABLE_INFO AcpiDmTableInfoIort5[] = 323 { 324 {ACPI_DMT_UINT64, ACPI_IORT5_OFFSET (Page0BaseAddress), "Page 0 Base Address", 0}, 325 {ACPI_DMT_UINT32, ACPI_IORT5_OFFSET (OverflowGsiv), "Overflow Interrupt GSIV", 0}, 326 {ACPI_DMT_UINT32, ACPI_IORT5_OFFSET (NodeReference), "Node Reference", 0}, 327 {ACPI_DMT_UINT64, ACPI_IORT5_OFFSET (Page1BaseAddress), "Page 1 Base Address", 0}, 328 ACPI_DMT_TERMINATOR 329 }; 330 331 332 /* 0x06: RMR */ 333 334 ACPI_DMTABLE_INFO AcpiDmTableInfoIort6[] = 335 { 336 {ACPI_DMT_UINT32, ACPI_IORT6_OFFSET (Flags), "Flags (decoded below)", 0}, 337 {ACPI_DMT_FLAG0, ACPI_IORT6_FLAG_OFFSET (Flags, 0), "Remapping Permitted", 0}, 338 {ACPI_DMT_FLAG1, ACPI_IORT6_FLAG_OFFSET (Flags, 0), "Access Privileged", 0}, 339 {ACPI_DMT_FLAGS8_2, ACPI_IORT6_FLAG_OFFSET (Flags, 0), "Access Attributes", 0}, 340 {ACPI_DMT_UINT32, ACPI_IORT6_OFFSET (RmrCount), "Number of RMR Descriptors", 0}, 341 {ACPI_DMT_UINT32, ACPI_IORT6_OFFSET (RmrOffset), "RMR Descriptor Offset", 0}, 342 ACPI_DMT_TERMINATOR 343 }; 344 345 ACPI_DMTABLE_INFO AcpiDmTableInfoIort6a[] = 346 { 347 {ACPI_DMT_UINT64, ACPI_IORT6A_OFFSET (BaseAddress), "Base Address of RMR", DT_OPTIONAL}, 348 {ACPI_DMT_UINT64, ACPI_IORT6A_OFFSET (Length), "Length of RMR", 0}, 349 {ACPI_DMT_UINT32, ACPI_IORT6A_OFFSET (Reserved), "Reserved", 0}, 350 ACPI_DMT_TERMINATOR 351 }; 352 353 /******************************************************************************* 354 * 355 * IVRS - I/O Virtualization Reporting Structure 356 * 357 ******************************************************************************/ 358 359 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs[] = 360 { 361 {ACPI_DMT_UINT32, ACPI_IVRS_OFFSET (Info), "Virtualization Info", 0}, 362 {ACPI_DMT_UINT64, ACPI_IVRS_OFFSET (Reserved), "Reserved", 0}, 363 ACPI_DMT_TERMINATOR 364 }; 365 366 /* IVRS subtables */ 367 368 /* 0x10: I/O Virtualization Hardware Definition (IVHD) Block */ 369 370 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHware1[] = 371 { 372 {ACPI_DMT_IVRS, ACPI_IVRSH_OFFSET (Type), "Subtable Type", 0}, 373 {ACPI_DMT_UINT8, ACPI_IVRSH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 374 {ACPI_DMT_FLAG0, ACPI_IVRS_FLAG_OFFSET (Flags,0), "HtTunEn", 0}, 375 {ACPI_DMT_FLAG1, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PassPW", 0}, 376 {ACPI_DMT_FLAG2, ACPI_IVRS_FLAG_OFFSET (Flags,0), "ResPassPW", 0}, 377 {ACPI_DMT_FLAG3, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Isoc Control", 0}, 378 {ACPI_DMT_FLAG4, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Iotlb Support", 0}, 379 {ACPI_DMT_FLAG5, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Coherent", 0}, 380 {ACPI_DMT_FLAG6, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Prefetch Support", 0}, 381 {ACPI_DMT_FLAG7, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PPR Support", 0}, 382 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (Length), "Length", DT_LENGTH}, 383 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (DeviceId), "DeviceId", 0}, 384 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (CapabilityOffset), "Capability Offset", 0}, 385 {ACPI_DMT_UINT64, ACPI_IVRS0_OFFSET (BaseAddress), "Base Address", 0}, 386 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (PciSegmentGroup), "PCI Segment Group", 0}, 387 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (Info), "Virtualization Info", 0}, 388 {ACPI_DMT_UINT32, ACPI_IVRS0_OFFSET (FeatureReporting), "Feature Reporting", 0}, 389 ACPI_DMT_TERMINATOR 390 }; 391 392 /* 0x11, 0x40: I/O Virtualization Hardware Definition (IVHD) Block */ 393 394 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHware23[] = 395 { 396 {ACPI_DMT_IVRS, ACPI_IVRSH_OFFSET (Type), "Subtable Type", 0}, 397 {ACPI_DMT_UINT8, ACPI_IVRSH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 398 {ACPI_DMT_FLAG0, ACPI_IVRS_FLAG_OFFSET (Flags,0), "HtTunEn", 0}, 399 {ACPI_DMT_FLAG1, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PassPW", 0}, 400 {ACPI_DMT_FLAG2, ACPI_IVRS_FLAG_OFFSET (Flags,0), "ResPassPW", 0}, 401 {ACPI_DMT_FLAG3, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Isoc Control", 0}, 402 {ACPI_DMT_FLAG4, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Iotlb Support", 0}, 403 {ACPI_DMT_FLAG5, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Coherent", 0}, 404 {ACPI_DMT_FLAG6, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Prefetch Support", 0}, 405 {ACPI_DMT_FLAG7, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PPR Support", 0}, 406 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (Header.Length), "Length", DT_LENGTH}, 407 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (Header.DeviceId), "DeviceId", 0}, 408 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (CapabilityOffset), "Capability Offset", 0}, 409 {ACPI_DMT_UINT64, ACPI_IVRS01_OFFSET (BaseAddress), "Base Address", 0}, 410 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (PciSegmentGroup), "PCI Segment Group", 0}, 411 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (Info), "Virtualization Info", 0}, 412 {ACPI_DMT_UINT32, ACPI_IVRS01_OFFSET (Attributes), "Attributes", 0}, 413 {ACPI_DMT_UINT64, ACPI_IVRS01_OFFSET (EfrRegisterImage), "EFR Image", 0}, 414 {ACPI_DMT_UINT64, ACPI_IVRS01_OFFSET (Reserved), "Reserved", 0}, 415 ACPI_DMT_TERMINATOR 416 }; 417 418 /* 0x20, 0x21, 0x22: I/O Virtualization Memory Definition (IVMD) Device Entry Block */ 419 420 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsMemory[] = 421 { 422 {ACPI_DMT_IVRS, ACPI_IVRSH_OFFSET (Type), "Subtable Type", 0}, 423 {ACPI_DMT_UINT8, ACPI_IVRSH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 424 {ACPI_DMT_FLAG0, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Unity", 0}, 425 {ACPI_DMT_FLAG1, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Readable", 0}, 426 {ACPI_DMT_FLAG2, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Writeable", 0}, 427 {ACPI_DMT_FLAG3, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Exclusion Range", 0}, 428 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (Length), "Length", DT_LENGTH}, 429 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (DeviceId), "DeviceId", 0}, 430 {ACPI_DMT_UINT16, ACPI_IVRS1_OFFSET (AuxData), "Auxiliary Data", 0}, 431 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (Reserved), "Reserved", 0}, 432 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (StartAddress), "Start Address", 0}, 433 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (MemoryLength), "Memory Length", 0}, 434 ACPI_DMT_TERMINATOR 435 }; 436 437 /* Device entry header for IVHD block */ 438 439 #define ACPI_DMT_IVRS_DE_HEADER \ 440 {ACPI_DMT_IVRS_DE, ACPI_IVRSD_OFFSET (Type), "Subtable Type", 0}, \ 441 {ACPI_DMT_UINT16, ACPI_IVRSD_OFFSET (Id), "Device ID", 0}, \ 442 {ACPI_DMT_UINT8, ACPI_IVRSD_OFFSET (DataSetting), "Data Setting (decoded below)", 0}, \ 443 {ACPI_DMT_FLAG0, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "INITPass", 0}, \ 444 {ACPI_DMT_FLAG1, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "EIntPass", 0}, \ 445 {ACPI_DMT_FLAG2, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "NMIPass", 0}, \ 446 {ACPI_DMT_FLAG3, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "Reserved", 0}, \ 447 {ACPI_DMT_FLAGS4, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "System MGMT", 0}, \ 448 {ACPI_DMT_FLAG6, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "LINT0 Pass", 0}, \ 449 {ACPI_DMT_FLAG7, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "LINT1 Pass", 0} 450 451 /* 4-byte device entry (Types 1,2,3,4) */ 452 453 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs4[] = 454 { 455 ACPI_DMT_IVRS_DE_HEADER, 456 ACPI_DMT_TERMINATOR 457 }; 458 459 /* 8-byte device entry (Type Alias Select, Alias Start of Range) */ 460 461 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8a[] = 462 { 463 ACPI_DMT_IVRS_DE_HEADER, 464 {ACPI_DMT_UINT8, ACPI_IVRS8A_OFFSET (Reserved1), "Reserved", 0}, 465 {ACPI_DMT_UINT16, ACPI_IVRS8A_OFFSET (UsedId), "Source Used Device ID", 0}, 466 {ACPI_DMT_UINT8, ACPI_IVRS8A_OFFSET (Reserved2), "Reserved", 0}, 467 ACPI_DMT_TERMINATOR 468 }; 469 470 /* 8-byte device entry (Type Extended Select, Extended Start of Range) */ 471 472 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8b[] = 473 { 474 ACPI_DMT_IVRS_DE_HEADER, 475 {ACPI_DMT_UINT32, ACPI_IVRS8B_OFFSET (ExtendedData), "Extended Data", 0}, 476 ACPI_DMT_TERMINATOR 477 }; 478 479 /* 8-byte device entry (Type Special Device) */ 480 481 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8c[] = 482 { 483 ACPI_DMT_IVRS_DE_HEADER, 484 {ACPI_DMT_UINT8, ACPI_IVRS8C_OFFSET (Handle), "Handle", 0}, 485 {ACPI_DMT_UINT16, ACPI_IVRS8C_OFFSET (UsedId), "Source Used Device ID", 0}, 486 {ACPI_DMT_UINT8, ACPI_IVRS8C_OFFSET (Variety), "Variety", 0}, 487 ACPI_DMT_TERMINATOR 488 }; 489 490 /* Variable-length Device Entry Type 0xF0 */ 491 492 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHid[] = 493 { 494 ACPI_DMT_IVRS_DE_HEADER, 495 ACPI_DMT_TERMINATOR 496 }; 497 498 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsUidString[] = 499 { 500 {ACPI_DMT_UINT8, 0, "UID Format", DT_DESCRIBES_OPTIONAL}, 501 {ACPI_DMT_UINT8, 1, "UID Length", DT_DESCRIBES_OPTIONAL}, 502 {ACPI_DMT_IVRS_UNTERMINATED_STRING, 2, "UID", DT_OPTIONAL}, 503 ACPI_DMT_TERMINATOR 504 }; 505 506 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsUidInteger[] = 507 { 508 {ACPI_DMT_UINT8, 0, "UID Format", DT_DESCRIBES_OPTIONAL}, 509 {ACPI_DMT_UINT8, 1, "UID Length", DT_DESCRIBES_OPTIONAL}, 510 {ACPI_DMT_UINT64, 2, "UID", DT_OPTIONAL}, 511 ACPI_DMT_TERMINATOR 512 }; 513 514 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHidString[] = 515 { 516 {ACPI_DMT_NAME8, 0, "ACPI HID", 0}, 517 ACPI_DMT_TERMINATOR 518 }; 519 520 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHidInteger[] = 521 { 522 {ACPI_DMT_UINT64, 0, "ACPI HID", 0}, 523 ACPI_DMT_TERMINATOR 524 }; 525 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsCidString[] = 526 { 527 {ACPI_DMT_NAME8, 0, "ACPI CID", 0}, 528 ACPI_DMT_TERMINATOR 529 }; 530 531 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsCidInteger[] = 532 { 533 {ACPI_DMT_UINT64, 0, "ACPI CID", 0}, 534 ACPI_DMT_TERMINATOR 535 }; 536 537 538 /******************************************************************************* 539 * 540 * LPIT - Low Power Idle Table 541 * 542 ******************************************************************************/ 543 544 /* Main table consists only of the standard ACPI table header */ 545 546 /* Common Subtable header (one per Subtable) */ 547 548 ACPI_DMTABLE_INFO AcpiDmTableInfoLpitHdr[] = 549 { 550 {ACPI_DMT_LPIT, ACPI_LPITH_OFFSET (Type), "Subtable Type", 0}, 551 {ACPI_DMT_UINT32, ACPI_LPITH_OFFSET (Length), "Length", DT_LENGTH}, 552 {ACPI_DMT_UINT16, ACPI_LPITH_OFFSET (UniqueId), "Unique ID", 0}, 553 {ACPI_DMT_UINT16, ACPI_LPITH_OFFSET (Reserved), "Reserved", 0}, 554 {ACPI_DMT_UINT32, ACPI_LPITH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 555 {ACPI_DMT_FLAG0, ACPI_LPITH_FLAG_OFFSET (Flags, 0), "State Disabled", 0}, 556 {ACPI_DMT_FLAG1, ACPI_LPITH_FLAG_OFFSET (Flags, 0), "No Counter", 0}, 557 ACPI_DMT_TERMINATOR 558 }; 559 560 /* LPIT Subtables */ 561 562 /* 0: Native C-state */ 563 564 ACPI_DMTABLE_INFO AcpiDmTableInfoLpit0[] = 565 { 566 {ACPI_DMT_GAS, ACPI_LPIT0_OFFSET (EntryTrigger), "Entry Trigger", 0}, 567 {ACPI_DMT_UINT32, ACPI_LPIT0_OFFSET (Residency), "Residency", 0}, 568 {ACPI_DMT_UINT32, ACPI_LPIT0_OFFSET (Latency), "Latency", 0}, 569 {ACPI_DMT_GAS, ACPI_LPIT0_OFFSET (ResidencyCounter), "Residency Counter", 0}, 570 {ACPI_DMT_UINT64, ACPI_LPIT0_OFFSET (CounterFrequency), "Counter Frequency", 0}, 571 ACPI_DMT_TERMINATOR 572 }; 573 /******************************************************************************* 574 * 575 * MADT - Multiple APIC Description Table and subtables 576 * 577 ******************************************************************************/ 578 579 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt[] = 580 { 581 {ACPI_DMT_UINT32, ACPI_MADT_OFFSET (Address), "Local Apic Address", 0}, 582 {ACPI_DMT_UINT32, ACPI_MADT_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 583 {ACPI_DMT_FLAG0, ACPI_MADT_FLAG_OFFSET (Flags,0), "PC-AT Compatibility", 0}, 584 ACPI_DMT_TERMINATOR 585 }; 586 587 /* Common Subtable header (one per Subtable) */ 588 589 ACPI_DMTABLE_INFO AcpiDmTableInfoMadtHdr[] = 590 { 591 {ACPI_DMT_MADT, ACPI_MADTH_OFFSET (Type), "Subtable Type", 0}, 592 {ACPI_DMT_UINT8, ACPI_MADTH_OFFSET (Length), "Length", DT_LENGTH}, 593 ACPI_DMT_TERMINATOR 594 }; 595 596 /* MADT Subtables */ 597 598 /* 0: processor APIC */ 599 600 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt0[] = 601 { 602 {ACPI_DMT_UINT8, ACPI_MADT0_OFFSET (ProcessorId), "Processor ID", 0}, 603 {ACPI_DMT_UINT8, ACPI_MADT0_OFFSET (Id), "Local Apic ID", 0}, 604 {ACPI_DMT_UINT32, ACPI_MADT0_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG}, 605 {ACPI_DMT_FLAG0, ACPI_MADT0_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0}, 606 {ACPI_DMT_FLAG1, ACPI_MADT0_FLAG_OFFSET (LapicFlags,0), "Runtime Online Capable", 0}, 607 ACPI_DMT_TERMINATOR 608 }; 609 610 /* 1: IO APIC */ 611 612 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt1[] = 613 { 614 {ACPI_DMT_UINT8, ACPI_MADT1_OFFSET (Id), "I/O Apic ID", 0}, 615 {ACPI_DMT_UINT8, ACPI_MADT1_OFFSET (Reserved), "Reserved", 0}, 616 {ACPI_DMT_UINT32, ACPI_MADT1_OFFSET (Address), "Address", 0}, 617 {ACPI_DMT_UINT32, ACPI_MADT1_OFFSET (GlobalIrqBase), "Interrupt", 0}, 618 ACPI_DMT_TERMINATOR 619 }; 620 621 /* 2: Interrupt Override */ 622 623 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt2[] = 624 { 625 {ACPI_DMT_UINT8, ACPI_MADT2_OFFSET (Bus), "Bus", 0}, 626 {ACPI_DMT_UINT8, ACPI_MADT2_OFFSET (SourceIrq), "Source", 0}, 627 {ACPI_DMT_UINT32, ACPI_MADT2_OFFSET (GlobalIrq), "Interrupt", 0}, 628 {ACPI_DMT_UINT16, ACPI_MADT2_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 629 {ACPI_DMT_FLAGS0, ACPI_MADT2_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 630 {ACPI_DMT_FLAGS2, ACPI_MADT2_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 631 ACPI_DMT_TERMINATOR 632 }; 633 634 /* 3: NMI Sources */ 635 636 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt3[] = 637 { 638 {ACPI_DMT_UINT16, ACPI_MADT3_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 639 {ACPI_DMT_FLAGS0, ACPI_MADT3_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 640 {ACPI_DMT_FLAGS2, ACPI_MADT3_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 641 {ACPI_DMT_UINT32, ACPI_MADT3_OFFSET (GlobalIrq), "Interrupt", 0}, 642 ACPI_DMT_TERMINATOR 643 }; 644 645 /* 4: Local APIC NMI */ 646 647 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt4[] = 648 { 649 {ACPI_DMT_UINT8, ACPI_MADT4_OFFSET (ProcessorId), "Processor ID", 0}, 650 {ACPI_DMT_UINT16, ACPI_MADT4_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 651 {ACPI_DMT_FLAGS0, ACPI_MADT4_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 652 {ACPI_DMT_FLAGS2, ACPI_MADT4_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 653 {ACPI_DMT_UINT8, ACPI_MADT4_OFFSET (Lint), "Interrupt Input LINT", 0}, 654 ACPI_DMT_TERMINATOR 655 }; 656 657 /* 5: Address Override */ 658 659 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt5[] = 660 { 661 {ACPI_DMT_UINT16, ACPI_MADT5_OFFSET (Reserved), "Reserved", 0}, 662 {ACPI_DMT_UINT64, ACPI_MADT5_OFFSET (Address), "APIC Address", 0}, 663 ACPI_DMT_TERMINATOR 664 }; 665 666 /* 6: I/O Sapic */ 667 668 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt6[] = 669 { 670 {ACPI_DMT_UINT8, ACPI_MADT6_OFFSET (Id), "I/O Sapic ID", 0}, 671 {ACPI_DMT_UINT8, ACPI_MADT6_OFFSET (Reserved), "Reserved", 0}, 672 {ACPI_DMT_UINT32, ACPI_MADT6_OFFSET (GlobalIrqBase), "Interrupt Base", 0}, 673 {ACPI_DMT_UINT64, ACPI_MADT6_OFFSET (Address), "Address", 0}, 674 ACPI_DMT_TERMINATOR 675 }; 676 677 /* 7: Local Sapic */ 678 679 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt7[] = 680 { 681 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (ProcessorId), "Processor ID", 0}, 682 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (Id), "Local Sapic ID", 0}, 683 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (Eid), "Local Sapic EID", 0}, 684 {ACPI_DMT_UINT24, ACPI_MADT7_OFFSET (Reserved[0]), "Reserved", 0}, 685 {ACPI_DMT_UINT32, ACPI_MADT7_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG}, 686 {ACPI_DMT_FLAG0, ACPI_MADT7_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0}, 687 {ACPI_DMT_UINT32, ACPI_MADT7_OFFSET (Uid), "Processor UID", 0}, 688 {ACPI_DMT_STRING, ACPI_MADT7_OFFSET (UidString[0]), "Processor UID String", 0}, 689 ACPI_DMT_TERMINATOR 690 }; 691 692 /* 8: Platform Interrupt Source */ 693 694 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt8[] = 695 { 696 {ACPI_DMT_UINT16, ACPI_MADT8_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 697 {ACPI_DMT_FLAGS0, ACPI_MADT8_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 698 {ACPI_DMT_FLAGS2, ACPI_MADT8_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 699 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Type), "InterruptType", 0}, 700 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Id), "Processor ID", 0}, 701 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Eid), "Processor EID", 0}, 702 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (IoSapicVector), "I/O Sapic Vector", 0}, 703 {ACPI_DMT_UINT32, ACPI_MADT8_OFFSET (GlobalIrq), "Interrupt", 0}, 704 {ACPI_DMT_UINT32, ACPI_MADT8_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 705 {ACPI_DMT_FLAG0, ACPI_MADT8_OFFSET (Flags), "CPEI Override", 0}, 706 ACPI_DMT_TERMINATOR 707 }; 708 709 /* 9: Processor Local X2_APIC (ACPI 4.0) */ 710 711 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt9[] = 712 { 713 {ACPI_DMT_UINT16, ACPI_MADT9_OFFSET (Reserved), "Reserved", 0}, 714 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (LocalApicId), "Processor x2Apic ID", 0}, 715 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG}, 716 {ACPI_DMT_FLAG0, ACPI_MADT9_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0}, 717 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (Uid), "Processor UID", 0}, 718 ACPI_DMT_TERMINATOR 719 }; 720 721 /* 10: Local X2_APIC NMI (ACPI 4.0) */ 722 723 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt10[] = 724 { 725 {ACPI_DMT_UINT16, ACPI_MADT10_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 726 {ACPI_DMT_FLAGS0, ACPI_MADT10_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 727 {ACPI_DMT_FLAGS2, ACPI_MADT10_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 728 {ACPI_DMT_UINT32, ACPI_MADT10_OFFSET (Uid), "Processor UID", 0}, 729 {ACPI_DMT_UINT8, ACPI_MADT10_OFFSET (Lint), "Interrupt Input LINT", 0}, 730 {ACPI_DMT_UINT24, ACPI_MADT10_OFFSET (Reserved[0]), "Reserved", 0}, 731 ACPI_DMT_TERMINATOR 732 }; 733 734 /* 11: Generic Interrupt Controller (ACPI 5.0) */ 735 736 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt11[] = 737 { 738 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (Reserved), "Reserved", 0}, 739 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (CpuInterfaceNumber), "CPU Interface Number", 0}, 740 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Uid), "Processor UID", 0}, 741 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 742 {ACPI_DMT_FLAG0, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Processor Enabled", 0}, 743 {ACPI_DMT_FLAG1, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Performance Interrupt Trigger Mode", 0}, 744 {ACPI_DMT_FLAG2, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Virtual GIC Interrupt Trigger Mode", 0}, 745 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (ParkingVersion), "Parking Protocol Version", 0}, 746 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (PerformanceInterrupt), "Performance Interrupt", 0}, 747 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ParkedAddress), "Parked Address", 0}, 748 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (BaseAddress), "Base Address", 0}, 749 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicvBaseAddress), "Virtual GIC Base Address", 0}, 750 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GichBaseAddress), "Hypervisor GIC Base Address", 0}, 751 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (VgicInterrupt), "Virtual GIC Interrupt", 0}, 752 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicrBaseAddress), "Redistributor Base Address", 0}, 753 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ArmMpidr), "ARM MPIDR", 0}, 754 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (EfficiencyClass), "Efficiency Class", 0}, 755 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (Reserved2[0]), "Reserved", 0}, 756 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (SpeInterrupt), "SPE Overflow Interrupt", 0}, 757 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (TrbeInterrupt), "TRBE Interrupt", 0}, 758 ACPI_DMT_TERMINATOR 759 }; 760 761 /* 12: Generic Interrupt Distributor (ACPI 5.0) */ 762 763 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt12[] = 764 { 765 {ACPI_DMT_UINT16, ACPI_MADT12_OFFSET (Reserved), "Reserved", 0}, 766 {ACPI_DMT_UINT32, ACPI_MADT12_OFFSET (GicId), "Local GIC Hardware ID", 0}, 767 {ACPI_DMT_UINT64, ACPI_MADT12_OFFSET (BaseAddress), "Base Address", 0}, 768 {ACPI_DMT_UINT32, ACPI_MADT12_OFFSET (GlobalIrqBase), "Interrupt Base", 0}, 769 {ACPI_DMT_UINT8, ACPI_MADT12_OFFSET (Version), "Version", 0}, 770 {ACPI_DMT_UINT24, ACPI_MADT12_OFFSET (Reserved2[0]), "Reserved", 0}, 771 ACPI_DMT_TERMINATOR 772 }; 773 774 /* 13: Generic MSI Frame (ACPI 5.1) */ 775 776 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt13[] = 777 { 778 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (Reserved), "Reserved", 0}, 779 {ACPI_DMT_UINT32, ACPI_MADT13_OFFSET (MsiFrameId), "MSI Frame ID", 0}, 780 {ACPI_DMT_UINT64, ACPI_MADT13_OFFSET (BaseAddress), "Base Address", 0}, 781 {ACPI_DMT_UINT32, ACPI_MADT13_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 782 {ACPI_DMT_FLAG0, ACPI_MADT13_FLAG_OFFSET (Flags,0), "Select SPI", 0}, 783 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (SpiCount), "SPI Count", 0}, 784 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (SpiBase), "SPI Base", 0}, 785 ACPI_DMT_TERMINATOR 786 }; 787 788 /* 14: Generic Redistributor (ACPI 5.1) */ 789 790 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt14[] = 791 { 792 {ACPI_DMT_UINT16, ACPI_MADT14_OFFSET (Reserved), "Reserved", 0}, 793 {ACPI_DMT_UINT64, ACPI_MADT14_OFFSET (BaseAddress), "Base Address", 0}, 794 {ACPI_DMT_UINT32, ACPI_MADT14_OFFSET (Length), "Length", 0}, 795 ACPI_DMT_TERMINATOR 796 }; 797 798 /* 15: Generic Translator (ACPI 6.0) */ 799 800 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt15[] = 801 { 802 {ACPI_DMT_UINT16, ACPI_MADT15_OFFSET (Reserved), "Reserved", 0}, 803 {ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (TranslationId), "Translation ID", 0}, 804 {ACPI_DMT_UINT64, ACPI_MADT15_OFFSET (BaseAddress), "Base Address", 0}, 805 {ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (Reserved2), "Reserved", 0}, 806 ACPI_DMT_TERMINATOR 807 }; 808 809 /* 16: Multiprocessor wakeup structure (ACPI 6.4) */ 810 811 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt16[] = 812 { 813 {ACPI_DMT_UINT16, ACPI_MADT16_OFFSET (MailboxVersion), "Mailbox Version", 0}, 814 {ACPI_DMT_UINT32, ACPI_MADT16_OFFSET (Reserved), "Reserved", 0}, 815 {ACPI_DMT_UINT64, ACPI_MADT16_OFFSET (BaseAddress), "Mailbox Address", 0}, 816 ACPI_DMT_TERMINATOR 817 }; 818 819 /* 17: core interrupt controller */ 820 821 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt17[] = 822 { 823 {ACPI_DMT_UINT8, ACPI_MADT17_OFFSET (Version), "Version", 0}, 824 {ACPI_DMT_UINT32, ACPI_MADT17_OFFSET (ProcessorId), "ProcessorId", 0}, 825 {ACPI_DMT_UINT32, ACPI_MADT17_OFFSET (CoreId), "CoreId", 0}, 826 {ACPI_DMT_UINT32, ACPI_MADT17_OFFSET (Flags), "Flags", 0}, 827 ACPI_DMT_TERMINATOR 828 }; 829 830 /* 18: Legacy I/O interrupt controller */ 831 832 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt18[] = 833 { 834 {ACPI_DMT_UINT8, ACPI_MADT18_OFFSET (Version), "Version", 0}, 835 {ACPI_DMT_UINT64, ACPI_MADT18_OFFSET (Address), "Address", 0}, 836 {ACPI_DMT_UINT16, ACPI_MADT18_OFFSET (Size), "Size", 0}, 837 {ACPI_DMT_UINT16, ACPI_MADT18_OFFSET (Cascade), "Cascade", 0}, 838 {ACPI_DMT_UINT64, ACPI_MADT18_OFFSET (CascadeMap), "CascadeMap", 0}, 839 ACPI_DMT_TERMINATOR 840 }; 841 842 /* 19: HT interrupt controller */ 843 844 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt19[] = 845 { 846 {ACPI_DMT_UINT8, ACPI_MADT19_OFFSET (Version), "Version", 0}, 847 {ACPI_DMT_UINT64, ACPI_MADT19_OFFSET (Address), "Address", 0}, 848 {ACPI_DMT_UINT16, ACPI_MADT19_OFFSET (Size), "Size", 0}, 849 {ACPI_DMT_UINT64, ACPI_MADT19_OFFSET (Cascade), "Cascade", 0}, 850 ACPI_DMT_TERMINATOR 851 }; 852 853 /* 20: Extend I/O interrupt controller */ 854 855 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt20[] = 856 { 857 {ACPI_DMT_UINT8, ACPI_MADT20_OFFSET (Version), "Version", 0}, 858 {ACPI_DMT_UINT8, ACPI_MADT20_OFFSET (Cascade), "Cascade", 0}, 859 {ACPI_DMT_UINT8, ACPI_MADT20_OFFSET (Node), "Node", 0}, 860 {ACPI_DMT_UINT64, ACPI_MADT20_OFFSET (NodeMap), "NodeMap", 0}, 861 ACPI_DMT_TERMINATOR 862 }; 863 864 /* 21: MSI controller */ 865 866 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt21[] = 867 { 868 {ACPI_DMT_UINT8, ACPI_MADT21_OFFSET (Version), "Version", 0}, 869 {ACPI_DMT_UINT64, ACPI_MADT21_OFFSET (MsgAddress), "MsgAddress", 0}, 870 {ACPI_DMT_UINT32, ACPI_MADT21_OFFSET (Start), "Start", 0}, 871 {ACPI_DMT_UINT32, ACPI_MADT21_OFFSET (Count), "Count", 0}, 872 ACPI_DMT_TERMINATOR 873 }; 874 875 /* 22: BIO interrupt controller */ 876 877 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt22[] = 878 { 879 {ACPI_DMT_UINT8, ACPI_MADT22_OFFSET (Version), "Version", 0}, 880 {ACPI_DMT_UINT64, ACPI_MADT22_OFFSET (Address), "Address", 0}, 881 {ACPI_DMT_UINT16, ACPI_MADT22_OFFSET (Size), "Size", 0}, 882 {ACPI_DMT_UINT16, ACPI_MADT22_OFFSET (Id), "Id", 0}, 883 {ACPI_DMT_UINT16, ACPI_MADT22_OFFSET (GsiBase), "GsiBase", 0}, 884 ACPI_DMT_TERMINATOR 885 }; 886 887 /* 23: LPC interrupt controller */ 888 889 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt23[] = 890 { 891 {ACPI_DMT_UINT8, ACPI_MADT23_OFFSET (Version), "Version", 0}, 892 {ACPI_DMT_UINT64, ACPI_MADT23_OFFSET (Address), "Address", 0}, 893 {ACPI_DMT_UINT16, ACPI_MADT23_OFFSET (Size), "Size", 0}, 894 {ACPI_DMT_UINT8, ACPI_MADT23_OFFSET (Cascade), "Cascade", 0}, 895 ACPI_DMT_TERMINATOR 896 }; 897 898 /* 24: RINTC interrupt controller */ 899 900 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt24[] = 901 { 902 {ACPI_DMT_UINT8, ACPI_MADT24_OFFSET (Version), "Version", 0}, 903 {ACPI_DMT_UINT8, ACPI_MADT24_OFFSET (Reserved), "Reserved", 0}, 904 {ACPI_DMT_UINT32, ACPI_MADT24_OFFSET (Flags), "Flags", 0}, 905 {ACPI_DMT_UINT64, ACPI_MADT24_OFFSET (HartId), "HartId", 0}, 906 {ACPI_DMT_UINT32, ACPI_MADT24_OFFSET (Uid), "Uid", 0}, 907 {ACPI_DMT_UINT32, ACPI_MADT24_OFFSET (ExtIntcId), "ExtIntcId", 0}, 908 {ACPI_DMT_UINT64, ACPI_MADT24_OFFSET (ImsicAddr), "ImsicAddr", 0}, 909 {ACPI_DMT_UINT32, ACPI_MADT24_OFFSET (ImsicSize), "ImsicSize", 0}, 910 ACPI_DMT_TERMINATOR 911 }; 912 913 /* 25: RISC-V IMSIC interrupt controller */ 914 915 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt25[] = 916 { 917 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (Version), "Version", 0}, 918 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (Reserved), "Reserved", 0}, 919 {ACPI_DMT_UINT32, ACPI_MADT25_OFFSET (Flags), "Flags", 0}, 920 {ACPI_DMT_UINT16, ACPI_MADT25_OFFSET (NumIds), "NumIds", 0}, 921 {ACPI_DMT_UINT16, ACPI_MADT25_OFFSET (NumGuestIds), "NumGuestIds", 0}, 922 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (GuestIndexBits), "GuestIndexBits", 0}, 923 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (HartIndexBits), "HartIndexBits", 0}, 924 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (GroupIndexBits), "GroupIndexBits", 0}, 925 {ACPI_DMT_UINT8, ACPI_MADT25_OFFSET (GroupIndexShift), "GroupIndexShift", 0}, 926 ACPI_DMT_TERMINATOR 927 }; 928 929 /* 26: RISC-V APLIC interrupt controller */ 930 931 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt26[] = 932 { 933 {ACPI_DMT_UINT8, ACPI_MADT26_OFFSET (Version), "Version", 0}, 934 {ACPI_DMT_UINT8, ACPI_MADT26_OFFSET (Id), "Id", 0}, 935 {ACPI_DMT_UINT32, ACPI_MADT26_OFFSET (Flags), "Flags", 0}, 936 {ACPI_DMT_UINT64, ACPI_MADT26_OFFSET (HwId), "HwId", 0}, 937 {ACPI_DMT_UINT16, ACPI_MADT26_OFFSET (NumIdcs), "NumIdcs", 0}, 938 {ACPI_DMT_UINT16, ACPI_MADT26_OFFSET (NumSources), "NumSources", 0}, 939 {ACPI_DMT_UINT32, ACPI_MADT26_OFFSET (GsiBase), "GsiBase", 0}, 940 {ACPI_DMT_UINT64, ACPI_MADT26_OFFSET (BaseAddr), "BaseAddr", 0}, 941 {ACPI_DMT_UINT32, ACPI_MADT26_OFFSET (Size), "Size", 0}, 942 ACPI_DMT_TERMINATOR 943 }; 944 945 /* 27: RISC-V PLIC interrupt controller */ 946 947 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt27[] = 948 { 949 {ACPI_DMT_UINT8, ACPI_MADT27_OFFSET (Version), "Version", 0}, 950 {ACPI_DMT_UINT8, ACPI_MADT27_OFFSET (Id), "Id", 0}, 951 {ACPI_DMT_UINT32, ACPI_MADT27_OFFSET (Flags), "Flags", 0}, 952 {ACPI_DMT_UINT64, ACPI_MADT27_OFFSET (HwId), "HwId", 0}, 953 {ACPI_DMT_UINT16, ACPI_MADT27_OFFSET (NumIrqs), "NumIrqs", 0}, 954 {ACPI_DMT_UINT16, ACPI_MADT27_OFFSET (MaxPrio), "MaxPrio", 0}, 955 {ACPI_DMT_UINT32, ACPI_MADT27_OFFSET (Flags), "Flags", 0}, 956 {ACPI_DMT_UINT32, ACPI_MADT27_OFFSET (Size), "Size", 0}, 957 {ACPI_DMT_UINT64, ACPI_MADT27_OFFSET (BaseAddr), "BaseAddr", 0}, 958 {ACPI_DMT_UINT32, ACPI_MADT27_OFFSET (GsiBase), "GsiBase", 0}, 959 ACPI_DMT_TERMINATOR 960 }; 961 962 /* 128: OEM data structure */ 963 964 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt128[] = 965 { 966 {ACPI_DMT_RAW_BUFFER, 0, "OEM Data", 0}, 967 ACPI_DMT_TERMINATOR 968 }; 969 970 /******************************************************************************* 971 * 972 * MCFG - PCI Memory Mapped Configuration table and Subtable 973 * 974 ******************************************************************************/ 975 976 ACPI_DMTABLE_INFO AcpiDmTableInfoMcfg[] = 977 { 978 {ACPI_DMT_UINT64, ACPI_MCFG_OFFSET (Reserved[0]), "Reserved", 0}, 979 ACPI_DMT_TERMINATOR 980 }; 981 982 ACPI_DMTABLE_INFO AcpiDmTableInfoMcfg0[] = 983 { 984 {ACPI_DMT_UINT64, ACPI_MCFG0_OFFSET (Address), "Base Address", 0}, 985 {ACPI_DMT_UINT16, ACPI_MCFG0_OFFSET (PciSegment), "Segment Group Number", 0}, 986 {ACPI_DMT_UINT8, ACPI_MCFG0_OFFSET (StartBusNumber), "Start Bus Number", 0}, 987 {ACPI_DMT_UINT8, ACPI_MCFG0_OFFSET (EndBusNumber), "End Bus Number", 0}, 988 {ACPI_DMT_UINT32, ACPI_MCFG0_OFFSET (Reserved), "Reserved", 0}, 989 ACPI_DMT_TERMINATOR 990 }; 991 992 993 /******************************************************************************* 994 * 995 * MCHI - Management Controller Host Interface table 996 * 997 ******************************************************************************/ 998 999 ACPI_DMTABLE_INFO AcpiDmTableInfoMchi[] = 1000 { 1001 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (InterfaceType), "Interface Type", 0}, 1002 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (Protocol), "Protocol", 0}, 1003 {ACPI_DMT_UINT64, ACPI_MCHI_OFFSET (ProtocolData), "Protocol Data", 0}, 1004 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (InterruptType), "Interrupt Type", 0}, 1005 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (Gpe), "Gpe", 0}, 1006 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciDeviceFlag), "Pci Device Flag", 0}, 1007 {ACPI_DMT_UINT32, ACPI_MCHI_OFFSET (GlobalInterrupt), "Global Interrupt", 0}, 1008 {ACPI_DMT_GAS, ACPI_MCHI_OFFSET (ControlRegister), "Control Register", 0}, 1009 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciSegment), "Pci Segment", 0}, 1010 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciBus), "Pci Bus", 0}, 1011 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciDevice), "Pci Device", 0}, 1012 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciFunction), "Pci Function", 0}, 1013 ACPI_DMT_TERMINATOR 1014 }; 1015 1016 /******************************************************************************* 1017 * 1018 * MPAM - Memory System Resource Partitioning and Monitoring Tables 1019 * Arm's DEN0065 MPAM ACPI 2.0. December 2022. 1020 ******************************************************************************/ 1021 1022 /* MPAM subtables */ 1023 1024 /* 0: MPAM Resource Node Structure - A root MSC table. 1025 * Arm's DEN0065 MPAM ACPI 2.0. Table 4: MPAM MSC node body. 1026 */ 1027 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam0[] = 1028 { 1029 {ACPI_DMT_UINT16, ACPI_MPAM0_OFFSET (Length), "Length", 0}, 1030 {ACPI_DMT_UINT8, ACPI_MPAM0_OFFSET (InterfaceType), "Interface type", 0}, 1031 {ACPI_DMT_UINT8, ACPI_MPAM0_OFFSET (Reserved), "Reserved", 0}, 1032 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (Identifier), "Identifier", 0}, 1033 {ACPI_DMT_UINT64, ACPI_MPAM0_OFFSET (BaseAddress), "Base address", 0}, 1034 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (MMIOSize), "MMIO size", 0}, 1035 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (OverflowInterrupt), "Overflow interrupt", 0}, 1036 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (OverflowInterruptFlags), "Overflow interrupt flags", 0}, 1037 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (Reserved1), "Reserved1", 0}, 1038 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (OverflowInterruptAffinity), "Overflow interrupt affinity", 0}, 1039 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (ErrorInterrupt), "Error interrupt", 0}, 1040 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (ErrorInterruptFlags), "Error interrupt flags", 0}, 1041 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (Reserved2), "Reserved2", 0}, 1042 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (ErrorInterruptAffinity), "Error interrupt affinity", 0}, 1043 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (MaxNrdyUsec), "MAX_NRDY_USEC", 0}, 1044 {ACPI_DMT_NAME8, ACPI_MPAM0_OFFSET (HardwareIdLinkedDevice), "Hardware ID of linked device", 0}, 1045 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (InstanceIdLinkedDevice), "Instance ID of linked device", 0}, 1046 {ACPI_DMT_UINT32, ACPI_MPAM0_OFFSET (NumResouceNodes), "Number of resource nodes", 0}, 1047 1048 ACPI_DMT_TERMINATOR 1049 }; 1050 1051 /* 1: MPAM Resource (RIS) Node Structure - A subtable of MSC Nodes. 1052 * Arm's DEN0065 MPAM ACPI 2.0. Table 9: Resource node. 1053 */ 1054 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1[] = 1055 { 1056 {ACPI_DMT_UINT32, ACPI_MPAM1_OFFSET (Identifier), "Identifier", 0}, 1057 {ACPI_DMT_UINT8, ACPI_MPAM1_OFFSET (RISIndex), "RIS Index", 0}, 1058 {ACPI_DMT_UINT16, ACPI_MPAM1_OFFSET (Reserved1), "Reserved1", 0}, 1059 {ACPI_DMT_MPAM_LOCATOR, ACPI_MPAM1_OFFSET (LocatorType), "Locator type", 0}, 1060 ACPI_DMT_TERMINATOR 1061 }; 1062 1063 /* An RIS field part of the RIS subtable */ 1064 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1Deps[] = 1065 { 1066 {ACPI_DMT_UINT32, 0, "Number of functional dependencies", 0}, 1067 ACPI_DMT_TERMINATOR 1068 }; 1069 1070 /* 1A: MPAM Processor cache locator descriptor. A subtable of RIS. 1071 * Arm's DEN0065 MPAM ACPI 2.0. Table 13. 1072 */ 1073 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1A[] = 1074 { 1075 {ACPI_DMT_UINT64, ACPI_MPAM1A_OFFSET (CacheReference), "Cache reference", 0}, 1076 {ACPI_DMT_UINT32, ACPI_MPAM1A_OFFSET (Reserved), "Reserved", 0}, 1077 }; 1078 1079 /* 1B: MPAM Memory locator descriptor. A subtable of RIS. 1080 * Arm's DEN0065 MPAM ACPI 2.0. Table 14. 1081 */ 1082 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1B[] = 1083 { 1084 {ACPI_DMT_UINT64, ACPI_MPAM1B_OFFSET (ProximityDomain), "Proximity domain", 0}, 1085 {ACPI_DMT_UINT32, ACPI_MPAM1B_OFFSET (Reserved), "Reserved", 0}, 1086 }; 1087 1088 /* 1C: MPAM SMMU locator descriptor. A subtable of RIS. 1089 * Arm's DEN0065 MPAM ACPI 2.0. Table 15. 1090 */ 1091 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1C[] = 1092 { 1093 {ACPI_DMT_UINT64, ACPI_MPAM1C_OFFSET (SmmuInterface), "SMMU Interface", 0}, 1094 {ACPI_DMT_UINT32, ACPI_MPAM1C_OFFSET (Reserved), "Reserved", 0}, 1095 }; 1096 1097 /* 1D: MPAM Memory-side cache locator descriptor. A subtable of RIS. 1098 * Arm's DEN0065 MPAM ACPI 2.0. Table 16. 1099 */ 1100 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1D[] = 1101 { 1102 {ACPI_DMT_UINT56, ACPI_MPAM1D_OFFSET (Level), "Reserved", 0}, 1103 {ACPI_DMT_UINT8, ACPI_MPAM1D_OFFSET (Level), "Level", 0}, 1104 {ACPI_DMT_UINT32, ACPI_MPAM1D_OFFSET (Reference), "Reference", 0}, 1105 }; 1106 1107 /* 1E: MPAM ACPI device locator descriptor. A subtable of RIS. 1108 * Arm's DEN0065 MPAM ACPI 2.0. Table 17. 1109 */ 1110 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1E[] = 1111 { 1112 {ACPI_DMT_UINT64, ACPI_MPAM1E_OFFSET (AcpiHwId), "ACPI Hardware ID", 0}, 1113 {ACPI_DMT_UINT32, ACPI_MPAM1E_OFFSET (AcpiUniqueId), "ACPI Unique ID", 0}, 1114 }; 1115 1116 /* 1F: MPAM Interconnect locator descriptor. A subtable of RIS. 1117 * Arm's DEN0065 MPAM ACPI 2.0. Table 18. 1118 */ 1119 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1F[] = 1120 { 1121 {ACPI_DMT_UINT64, ACPI_MPAM1F_OFFSET (InterConnectDescTblOff), "Interconnect descriptor table offset", 0}, 1122 {ACPI_DMT_UINT32, ACPI_MPAM1F_OFFSET (Reserved), "Reserved", 0}, 1123 }; 1124 1125 /* 1G: MPAM Locator structure. 1126 * Arm's DEN0065 MPAM ACPI 2.0. Table 12. 1127 */ 1128 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam1G[] = 1129 { 1130 {ACPI_DMT_UINT64, ACPI_MPAM1G_OFFSET (Descriptor1), "Descriptor1", 0}, 1131 {ACPI_DMT_UINT32, ACPI_MPAM1G_OFFSET (Descriptor2), "Descriptor2", 0}, 1132 }; 1133 1134 /* 2: MPAM Functional dependency descriptor. 1135 * Arm's DEN0065 MPAM ACPI 2.0. Table 10. 1136 */ 1137 ACPI_DMTABLE_INFO AcpiDmTableInfoMpam2[] = 1138 { 1139 {ACPI_DMT_UINT32, ACPI_MPAM2_OFFSET (Producer), "Producer", 0}, 1140 {ACPI_DMT_UINT32, ACPI_MPAM2_OFFSET (Reserved), "Reserved", 0}, 1141 }; 1142 1143 1144 /******************************************************************************* 1145 * 1146 * MPST - Memory Power State Table 1147 * 1148 ******************************************************************************/ 1149 1150 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst[] = 1151 { 1152 {ACPI_DMT_UINT8, ACPI_MPST_OFFSET (ChannelId), "Channel ID", 0}, 1153 {ACPI_DMT_UINT24, ACPI_MPST_OFFSET (Reserved1[0]), "Reserved", 0}, 1154 {ACPI_DMT_UINT16, ACPI_MPST_OFFSET (PowerNodeCount), "Power Node Count", 0}, 1155 {ACPI_DMT_UINT16, ACPI_MPST_OFFSET (Reserved2), "Reserved", 0}, 1156 ACPI_DMT_TERMINATOR 1157 }; 1158 1159 /* MPST subtables */ 1160 1161 /* 0: Memory Power Node Structure */ 1162 1163 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0[] = 1164 { 1165 {ACPI_DMT_UINT8, ACPI_MPST0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1166 {ACPI_DMT_FLAG0, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Node Enabled", 0}, 1167 {ACPI_DMT_FLAG1, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Power Managed", 0}, 1168 {ACPI_DMT_FLAG2, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Hot Plug Capable", 0}, 1169 1170 {ACPI_DMT_UINT8, ACPI_MPST0_OFFSET (Reserved1), "Reserved", 0}, 1171 {ACPI_DMT_UINT16, ACPI_MPST0_OFFSET (NodeId), "Node ID", 0}, 1172 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (Length), "Length", 0}, 1173 {ACPI_DMT_UINT64, ACPI_MPST0_OFFSET (RangeAddress), "Range Address", 0}, 1174 {ACPI_DMT_UINT64, ACPI_MPST0_OFFSET (RangeLength), "Range Length", 0}, 1175 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (NumPowerStates), "Num Power States", 0}, 1176 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (NumPhysicalComponents), "Num Physical Components", 0}, 1177 ACPI_DMT_TERMINATOR 1178 }; 1179 1180 /* 0A: Sub-subtable - Memory Power State Structure (follows Memory Power Node above) */ 1181 1182 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0A[] = 1183 { 1184 {ACPI_DMT_UINT8, ACPI_MPST0A_OFFSET (PowerState), "Power State", 0}, 1185 {ACPI_DMT_UINT8, ACPI_MPST0A_OFFSET (InfoIndex), "InfoIndex", 0}, 1186 ACPI_DMT_TERMINATOR 1187 }; 1188 1189 /* 0B: Sub-subtable - Physical Component ID Structure (follows Memory Power State(s) above) */ 1190 1191 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0B[] = 1192 { 1193 {ACPI_DMT_UINT16, ACPI_MPST0B_OFFSET (ComponentId), "Component Id", 0}, 1194 ACPI_DMT_TERMINATOR 1195 }; 1196 1197 /* 01: Power Characteristics Count (follows all Power Node(s) above) */ 1198 1199 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst1[] = 1200 { 1201 {ACPI_DMT_UINT16, ACPI_MPST1_OFFSET (CharacteristicsCount), "Characteristics Count", 0}, 1202 {ACPI_DMT_UINT16, ACPI_MPST1_OFFSET (Reserved), "Reserved", 0}, 1203 ACPI_DMT_TERMINATOR 1204 }; 1205 1206 /* 02: Memory Power State Characteristics Structure */ 1207 1208 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst2[] = 1209 { 1210 {ACPI_DMT_UINT8, ACPI_MPST2_OFFSET (StructureId), "Structure ID", 0}, 1211 {ACPI_DMT_UINT8, ACPI_MPST2_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1212 {ACPI_DMT_FLAG0, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Memory Preserved", 0}, 1213 {ACPI_DMT_FLAG1, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Auto Entry", 0}, 1214 {ACPI_DMT_FLAG2, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Auto Exit", 0}, 1215 1216 {ACPI_DMT_UINT16, ACPI_MPST2_OFFSET (Reserved1), "Reserved", 0}, 1217 {ACPI_DMT_UINT32, ACPI_MPST2_OFFSET (AveragePower), "Average Power", 0}, 1218 {ACPI_DMT_UINT32, ACPI_MPST2_OFFSET (PowerSaving), "Power Saving", 0}, 1219 {ACPI_DMT_UINT64, ACPI_MPST2_OFFSET (ExitLatency), "Exit Latency", 0}, 1220 {ACPI_DMT_UINT64, ACPI_MPST2_OFFSET (Reserved2), "Reserved", 0}, 1221 ACPI_DMT_TERMINATOR 1222 }; 1223 1224 1225 /******************************************************************************* 1226 * 1227 * MSCT - Maximum System Characteristics Table (ACPI 4.0) 1228 * 1229 ******************************************************************************/ 1230 1231 ACPI_DMTABLE_INFO AcpiDmTableInfoMsct[] = 1232 { 1233 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (ProximityOffset), "Proximity Offset", 0}, 1234 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (MaxProximityDomains), "Max Proximity Domains", 0}, 1235 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (MaxClockDomains), "Max Clock Domains", 0}, 1236 {ACPI_DMT_UINT64, ACPI_MSCT_OFFSET (MaxAddress), "Max Physical Address", 0}, 1237 ACPI_DMT_TERMINATOR 1238 }; 1239 1240 /* Subtable - Maximum Proximity Domain Information. Version 1 */ 1241 1242 ACPI_DMTABLE_INFO AcpiDmTableInfoMsct0[] = 1243 { 1244 {ACPI_DMT_UINT8, ACPI_MSCT0_OFFSET (Revision), "Revision", 0}, 1245 {ACPI_DMT_UINT8, ACPI_MSCT0_OFFSET (Length), "Length", DT_LENGTH}, 1246 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (RangeStart), "Domain Range Start", 0}, 1247 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (RangeEnd), "Domain Range End", 0}, 1248 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (ProcessorCapacity), "Processor Capacity", 0}, 1249 {ACPI_DMT_UINT64, ACPI_MSCT0_OFFSET (MemoryCapacity), "Memory Capacity", 0}, 1250 ACPI_DMT_TERMINATOR 1251 }; 1252 1253 1254 /******************************************************************************* 1255 * 1256 * NFIT - NVDIMM Firmware Interface Table and Subtables - (ACPI 6.0) 1257 * 1258 ******************************************************************************/ 1259 1260 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit[] = 1261 { 1262 {ACPI_DMT_UINT32, ACPI_NFIT_OFFSET (Reserved), "Reserved", 0}, 1263 ACPI_DMT_TERMINATOR 1264 }; 1265 1266 /* Common Subtable header */ 1267 1268 ACPI_DMTABLE_INFO AcpiDmTableInfoNfitHdr[] = 1269 { 1270 {ACPI_DMT_NFIT, ACPI_NFITH_OFFSET (Type), "Subtable Type", 0}, 1271 {ACPI_DMT_UINT16, ACPI_NFITH_OFFSET (Length), "Length", DT_LENGTH}, 1272 ACPI_DMT_TERMINATOR 1273 }; 1274 1275 /* 0: System Physical Address Range Structure */ 1276 1277 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit0[] = 1278 { 1279 {ACPI_DMT_UINT16, ACPI_NFIT0_OFFSET (RangeIndex), "Range Index", 0}, 1280 {ACPI_DMT_UINT16, ACPI_NFIT0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1281 {ACPI_DMT_FLAG0, ACPI_NFIT0_FLAG_OFFSET (Flags,0), "Add/Online Operation Only", 0}, 1282 {ACPI_DMT_FLAG1, ACPI_NFIT0_FLAG_OFFSET (Flags,0), "Proximity Domain Valid", 0}, 1283 {ACPI_DMT_FLAG2, ACPI_NFIT0_FLAG_OFFSET (Flags,0), "Location Cookie Valid", 0}, 1284 {ACPI_DMT_UINT32, ACPI_NFIT0_OFFSET (Reserved), "Reserved", 0}, 1285 {ACPI_DMT_UINT32, ACPI_NFIT0_OFFSET (ProximityDomain), "Proximity Domain", 0}, 1286 {ACPI_DMT_UUID, ACPI_NFIT0_OFFSET (RangeGuid[0]), "Region Type GUID", 0}, 1287 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (Address), "Address Range Base", 0}, 1288 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (Length), "Address Range Length", 0}, 1289 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (MemoryMapping), "Memory Map Attribute", 0}, 1290 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (LocationCookie), "Location Cookie", 0}, /* ACPI 6.4 */ 1291 ACPI_DMT_TERMINATOR 1292 }; 1293 1294 /* 1: Memory Device to System Address Range Map Structure */ 1295 1296 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit1[] = 1297 { 1298 {ACPI_DMT_UINT32, ACPI_NFIT1_OFFSET (DeviceHandle), "Device Handle", 0}, 1299 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (PhysicalId), "Physical Id", 0}, 1300 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RegionId), "Region Id", 0}, 1301 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RangeIndex), "Range Index", 0}, 1302 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RegionIndex), "Control Region Index", 0}, 1303 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (RegionSize), "Region Size", 0}, 1304 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (RegionOffset), "Region Offset", 0}, 1305 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (Address), "Address Region Base", 0}, 1306 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (InterleaveIndex), "Interleave Index", 0}, 1307 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (InterleaveWays), "Interleave Ways", 0}, 1308 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (Flags), "Flags", DT_FLAG}, 1309 {ACPI_DMT_FLAG0, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Save to device failed", 0}, 1310 {ACPI_DMT_FLAG1, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Restore from device failed", 0}, 1311 {ACPI_DMT_FLAG2, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Platform flush failed", 0}, 1312 {ACPI_DMT_FLAG3, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Device not armed", 0}, 1313 {ACPI_DMT_FLAG4, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Health events observed", 0}, 1314 {ACPI_DMT_FLAG5, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Health events enabled", 0}, 1315 {ACPI_DMT_FLAG6, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Mapping failed", 0}, 1316 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (Reserved), "Reserved", 0}, 1317 ACPI_DMT_TERMINATOR 1318 }; 1319 1320 /* 2: Interleave Structure */ 1321 1322 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit2[] = 1323 { 1324 {ACPI_DMT_UINT16, ACPI_NFIT2_OFFSET (InterleaveIndex), "Interleave Index", 0}, 1325 {ACPI_DMT_UINT16, ACPI_NFIT2_OFFSET (Reserved), "Reserved", 0}, 1326 {ACPI_DMT_UINT32, ACPI_NFIT2_OFFSET (LineCount), "Line Count", 0}, 1327 {ACPI_DMT_UINT32, ACPI_NFIT2_OFFSET (LineSize), "Line Size", 0}, 1328 ACPI_DMT_TERMINATOR 1329 }; 1330 1331 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit2a[] = 1332 { 1333 {ACPI_DMT_UINT32, 0, "Line Offset", DT_OPTIONAL}, 1334 ACPI_DMT_TERMINATOR 1335 }; 1336 1337 /* 3: SMBIOS Management Information Structure */ 1338 1339 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit3[] = 1340 { 1341 {ACPI_DMT_UINT32, ACPI_NFIT3_OFFSET (Reserved), "Reserved", 0}, 1342 ACPI_DMT_TERMINATOR 1343 }; 1344 1345 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit3a[] = 1346 { 1347 {ACPI_DMT_RAW_BUFFER, 0, "SMBIOS Table Entries", DT_OPTIONAL}, 1348 ACPI_DMT_TERMINATOR 1349 }; 1350 1351 /* 4: NVDIMM Control Region Structure */ 1352 1353 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit4[] = 1354 { 1355 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (RegionIndex), "Region Index", 0}, 1356 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (VendorId), "Vendor Id", 0}, 1357 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (DeviceId), "Device Id", 0}, 1358 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (RevisionId), "Revision Id", 0}, 1359 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemVendorId), "Subsystem Vendor Id", 0}, 1360 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemDeviceId), "Subsystem Device Id", 0}, 1361 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemRevisionId), "Subsystem Revision Id", 0}, 1362 {ACPI_DMT_UINT8, ACPI_NFIT4_OFFSET (ValidFields), "Valid Fields", 0}, 1363 {ACPI_DMT_UINT8, ACPI_NFIT4_OFFSET (ManufacturingLocation), "Manufacturing Location", 0}, 1364 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (ManufacturingDate), "Manufacturing Date", 0}, 1365 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Reserved[0]), "Reserved", 0}, 1366 {ACPI_DMT_UINT32, ACPI_NFIT4_OFFSET (SerialNumber), "Serial Number", 0}, 1367 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Code), "Code", 0}, 1368 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Windows), "Window Count", 0}, 1369 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (WindowSize), "Window Size", 0}, 1370 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (CommandOffset), "Command Offset", 0}, 1371 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (CommandSize), "Command Size", 0}, 1372 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (StatusOffset), "Status Offset", 0}, 1373 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (StatusSize), "Status Size", 0}, 1374 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Flags), "Flags", DT_FLAG}, 1375 {ACPI_DMT_FLAG0, ACPI_NFIT4_FLAG_OFFSET (Flags,0), "Windows buffered", 0}, 1376 {ACPI_DMT_UINT48, ACPI_NFIT4_OFFSET (Reserved1[0]), "Reserved1", 0}, 1377 ACPI_DMT_TERMINATOR 1378 }; 1379 1380 /* 5: NVDIMM Block Data Window Region Structure */ 1381 1382 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit5[] = 1383 { 1384 {ACPI_DMT_UINT16, ACPI_NFIT5_OFFSET (RegionIndex), "Region Index", 0}, 1385 {ACPI_DMT_UINT16, ACPI_NFIT5_OFFSET (Windows), "Window Count", 0}, 1386 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Offset), "Offset", 0}, 1387 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Size), "Size", 0}, 1388 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Capacity), "Capacity", 0}, 1389 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (StartAddress), "Start Address", 0}, 1390 ACPI_DMT_TERMINATOR 1391 }; 1392 1393 /* 6: Flush Hint Address Structure */ 1394 1395 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit6[] = 1396 { 1397 {ACPI_DMT_UINT32, ACPI_NFIT6_OFFSET (DeviceHandle), "Device Handle", 0}, 1398 {ACPI_DMT_UINT16, ACPI_NFIT6_OFFSET (HintCount), "Hint Count", 0}, 1399 {ACPI_DMT_UINT48, ACPI_NFIT6_OFFSET (Reserved[0]), "Reserved", 0}, 1400 ACPI_DMT_TERMINATOR 1401 }; 1402 1403 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit6a[] = 1404 { 1405 {ACPI_DMT_UINT64, 0, "Hint Address", DT_OPTIONAL}, 1406 ACPI_DMT_TERMINATOR 1407 }; 1408 1409 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit7[] = 1410 { 1411 {ACPI_DMT_UINT8, ACPI_NFIT7_OFFSET (HighestCapability), "Highest Capability", 0}, 1412 {ACPI_DMT_UINT24, ACPI_NFIT7_OFFSET (Reserved[0]), "Reserved", 0}, 1413 {ACPI_DMT_UINT32, ACPI_NFIT7_OFFSET (Capabilities), "Capabilities (decoded below)", DT_FLAG}, 1414 {ACPI_DMT_FLAG0, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Cache Flush to NVDIMM", 0}, 1415 {ACPI_DMT_FLAG1, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Memory Flush to NVDIMM", 0}, 1416 {ACPI_DMT_FLAG2, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Memory Mirroring", 0}, 1417 {ACPI_DMT_UINT32, ACPI_NFIT7_OFFSET (Reserved2), "Reserved", 0}, 1418 ACPI_DMT_TERMINATOR 1419 }; 1420 1421 1422 /******************************************************************************* 1423 * 1424 * NHLT - Non HD Audio Link Table. Conforms to Intel Smart Sound Technology 1425 * NHLT Specification, January 2020 Revision 0.8.1 1426 * 1427 ******************************************************************************/ 1428 1429 /* Main table */ 1430 1431 ACPI_DMTABLE_INFO AcpiDmTableInfoNhlt[] = 1432 { 1433 {ACPI_DMT_UINT8, ACPI_NHLT_OFFSET (EndpointCount), "Endpoint Count", 0}, 1434 ACPI_DMT_TERMINATOR 1435 }; 1436 1437 /* Endpoint config */ 1438 1439 ACPI_DMTABLE_INFO AcpiDmTableInfoNhlt0[] = 1440 { 1441 {ACPI_DMT_UINT32, ACPI_NHLT0_OFFSET (DescriptorLength), "Descriptor Length", DT_LENGTH}, 1442 {ACPI_DMT_NHLT1, ACPI_NHLT0_OFFSET (LinkType), "Link Type", 0}, 1443 {ACPI_DMT_UINT8, ACPI_NHLT0_OFFSET (InstanceId), "Instance Id", 0}, 1444 {ACPI_DMT_UINT16, ACPI_NHLT0_OFFSET (VendorId), "Vendor Id", 0}, 1445 {ACPI_DMT_NHLT1e, ACPI_NHLT0_OFFSET (DeviceId), "Device Id", 0}, 1446 {ACPI_DMT_UINT16, ACPI_NHLT0_OFFSET (RevisionId), "Revision Id", 0}, 1447 {ACPI_DMT_UINT32, ACPI_NHLT0_OFFSET (SubsystemId), "Subsystem Id", 0}, 1448 {ACPI_DMT_UINT8, ACPI_NHLT0_OFFSET (DeviceType), "Device Type", 0}, 1449 {ACPI_DMT_NHLT1a, ACPI_NHLT0_OFFSET (Direction), "Direction", 0}, 1450 {ACPI_DMT_UINT8, ACPI_NHLT0_OFFSET (VirtualBusId), "Virtual Bus Id", 0}, 1451 ACPI_DMT_TERMINATOR 1452 }; 1453 1454 /* Device_Specific config */ 1455 1456 ACPI_DMTABLE_INFO AcpiDmTableInfoNhlt1[] = 1457 { 1458 {ACPI_DMT_UINT32, ACPI_NHLT1_OFFSET (CapabilitiesSize), "Capabilities Size", 0}, 1459 {ACPI_DMT_UINT8, ACPI_NHLT1_OFFSET (VirtualSlot), "Virtual Slot", 0}, 1460 {ACPI_DMT_NHLT1f, ACPI_NHLT1_OFFSET (ConfigType), "Config Type", 0}, 1461 ACPI_DMT_TERMINATOR 1462 }; 1463 1464 /* Wave Format Extensible */ 1465 1466 ACPI_DMTABLE_INFO AcpiDmTableInfoNhlt2[] = 1467 { 1468 {ACPI_DMT_UINT16, ACPI_NHLT2_OFFSET (FormatTag), "Format Tag", 0}, 1469 {ACPI_DMT_UINT16, ACPI_NHLT2_OFFSET (ChannelCount), "Channel Count", 0}, 1470 {ACPI_DMT_UINT32, ACPI_NHLT2_OFFSET (SamplesPerSec), "Samples Per Second", 0}, 1471 {ACPI_DMT_UINT32, ACPI_NHLT2_OFFSET (AvgBytesPerSec), "Average Bytes Per Second", 0}, 1472 {ACPI_DMT_UINT16, ACPI_NHLT2_OFFSET (BlockAlign), "Block Alignment", 0}, 1473 {ACPI_DMT_UINT16, ACPI_NHLT2_OFFSET (BitsPerSample), "Bits Per Sample", 0}, 1474 {ACPI_DMT_UINT16, ACPI_NHLT2_OFFSET (ExtraFormatSize), "Extra Format Size", 0}, 1475 {ACPI_DMT_UINT16, ACPI_NHLT2_OFFSET (ValidBitsPerSample), "Valid Bits Per Sample", 0}, 1476 {ACPI_DMT_UINT32, ACPI_NHLT2_OFFSET (ChannelMask), "Channel Mask", 0}, 1477 {ACPI_DMT_UUID, ACPI_NHLT2_OFFSET (SubFormatGuid), "SubFormat GUID", 0}, 1478 ACPI_DMT_TERMINATOR 1479 }; 1480 1481 /* Format Config (wave_format_extensible structure) */ 1482 1483 ACPI_DMTABLE_INFO AcpiDmTableInfoNhlt3[] = 1484 { 1485 {ACPI_DMT_UINT16, ACPI_NHLT3_OFFSET (Format.FormatTag), "Format Tag", 0}, 1486 {ACPI_DMT_UINT16, ACPI_NHLT3_OFFSET (Format.ChannelCount), "Channel Count", 0}, 1487 {ACPI_DMT_UINT32, ACPI_NHLT3_OFFSET (Format.SamplesPerSec), "Samples Per Second", 0}, 1488 {ACPI_DMT_UINT32, ACPI_NHLT3_OFFSET (Format.AvgBytesPerSec), "Average Bytes Per Second", 0}, 1489 {ACPI_DMT_UINT16, ACPI_NHLT3_OFFSET (Format.BlockAlign), "Block Alignment", 0}, 1490 {ACPI_DMT_UINT16, ACPI_NHLT3_OFFSET (Format.BitsPerSample), "Bits Per Sample", 0}, 1491 {ACPI_DMT_UINT16, ACPI_NHLT3_OFFSET (Format.ExtraFormatSize), "Extra Format Size", 0}, 1492 {ACPI_DMT_UINT16, ACPI_NHLT3_OFFSET (Format.ValidBitsPerSample), "Valid Bits Per Sample", 0}, 1493 {ACPI_DMT_UINT32, ACPI_NHLT3_OFFSET (Format.ChannelMask), "Channel Mask", 0}, 1494 {ACPI_DMT_UUID, ACPI_NHLT3_OFFSET (Format.SubFormatGuid), "SubFormat GUID", 0}, 1495 {ACPI_DMT_UINT32, ACPI_NHLT3_OFFSET (CapabilitySize), "Capabilities Length", 0}, 1496 ACPI_DMT_TERMINATOR 1497 }; 1498 1499 /* 1500 * We treat the binary Capabilities field as its own subtable (to make 1501 * ACPI_DMT_RAW_BUFFER work properly). 1502 */ 1503 ACPI_DMTABLE_INFO AcpiDmTableInfoNhlt3a[] = 1504 { 1505 {ACPI_DMT_RAW_BUFFER, 0, "Capabilities", 0}, 1506 ACPI_DMT_TERMINATOR 1507 }; 1508 1509 /* Formats Config */ 1510 1511 ACPI_DMTABLE_INFO AcpiDmTableInfoNhlt4[] = 1512 { 1513 {ACPI_DMT_UINT8, ACPI_NHLT4_OFFSET (FormatsCount), "Formats Count", 0}, 1514 ACPI_DMT_TERMINATOR 1515 }; 1516 1517 /* Specific Config, CapabilitiesSize == 2 */ 1518 1519 ACPI_DMTABLE_INFO AcpiDmTableInfoNhlt5[] = 1520 { 1521 {ACPI_DMT_UINT8, ACPI_NHLT5_OFFSET (VirtualSlot), "Virtual Slot", 0}, 1522 {ACPI_DMT_NHLT1f, ACPI_NHLT5_OFFSET (ConfigType), "Config Type", 0}, 1523 ACPI_DMT_TERMINATOR 1524 }; 1525 1526 /* Specific Config, CapabilitiesSize == 3 */ 1527 1528 ACPI_DMTABLE_INFO AcpiDmTableInfoNhlt5a[] = 1529 { 1530 {ACPI_DMT_UINT8, ACPI_NHLT5A_OFFSET (VirtualSlot), "Virtual Slot", 0}, 1531 {ACPI_DMT_NHLT1f, ACPI_NHLT5A_OFFSET (ConfigType), "Config Type", 0}, 1532 {ACPI_DMT_NHLT1d, ACPI_NHLT5A_OFFSET (ArrayType), "Array Type", 0}, 1533 ACPI_DMT_TERMINATOR 1534 }; 1535 1536 /* Specific Config, CapabilitiesSize == 0 */ 1537 1538 ACPI_DMTABLE_INFO AcpiDmTableInfoNhlt5b[] = 1539 { 1540 {ACPI_DMT_UINT32, ACPI_NHLT5B_OFFSET (CapabilitiesSize), "Capabilities Size", 0}, 1541 ACPI_DMT_TERMINATOR 1542 }; 1543 1544 /* Specific Config, CapabilitiesSize == 1 */ 1545 1546 ACPI_DMTABLE_INFO AcpiDmTableInfoNhlt5c[] = 1547 { 1548 {ACPI_DMT_UINT8, ACPI_NHLT5C_OFFSET (VirtualSlot), "Virtual Slot", 0}, 1549 ACPI_DMT_TERMINATOR 1550 }; 1551 1552 /* Microphone array Config */ 1553 1554 ACPI_DMTABLE_INFO AcpiDmTableInfoNhlt6a[] = 1555 { 1556 {ACPI_DMT_UINT8, ACPI_NHLT6A_OFFSET (MicrophoneCount), "Microphone Count", 0}, 1557 ACPI_DMT_TERMINATOR 1558 }; 1559 1560 /* Render Feedback Device Config, CapabilitiesSize == 7 */ 1561 1562 ACPI_DMTABLE_INFO AcpiDmTableInfoNhlt6b[] = 1563 { 1564 {ACPI_DMT_UINT8, ACPI_NHLT6B_OFFSET (FeedbackVirtualSlot), "Feedback Virtual Slot", 0}, 1565 {ACPI_DMT_UINT16, ACPI_NHLT6B_OFFSET (FeedbackChannels), "Feedback Channels", 0}, 1566 {ACPI_DMT_UINT16, ACPI_NHLT6B_OFFSET (FeedbackValidBitsPerSample),"Valid Bits Per Sample", 0}, 1567 ACPI_DMT_TERMINATOR 1568 }; 1569 1570 ACPI_DMTABLE_INFO AcpiDmTableInfoNhlt6[] = 1571 { 1572 {ACPI_DMT_NHLT1b, ACPI_NHLT6_OFFSET (Type), "Type", 0}, 1573 {ACPI_DMT_NHLT1c, ACPI_NHLT6_OFFSET (Panel), "Panel", 0}, 1574 {ACPI_DMT_UINT16, ACPI_NHLT6_OFFSET (SpeakerPositionDistance), "Speaker Position Distance", 0}, 1575 {ACPI_DMT_UINT16, ACPI_NHLT6_OFFSET (HorizontalOffset), "Horizontal Offset", 0}, 1576 {ACPI_DMT_UINT16, ACPI_NHLT6_OFFSET (VerticalOffset), "Vertical Offset", 0}, 1577 {ACPI_DMT_UINT8, ACPI_NHLT6_OFFSET (FrequencyLowBand), "Frequency Low Band", 0}, 1578 {ACPI_DMT_UINT8, ACPI_NHLT6_OFFSET (FrequencyHighBand), "Frequency High Band", 0}, 1579 {ACPI_DMT_UINT16, ACPI_NHLT6_OFFSET (DirectionAngle), "Direction Angle", 0}, 1580 {ACPI_DMT_UINT16, ACPI_NHLT6_OFFSET (ElevationAngle), "Elevation Angle", 0}, 1581 {ACPI_DMT_UINT16, ACPI_NHLT6_OFFSET (WorkVerticalAngleBegin), "Work Vertical Angle Begin", 0}, 1582 {ACPI_DMT_UINT16, ACPI_NHLT6_OFFSET (WorkVerticalAngleEnd), "Work Vertical Angle End", 0}, 1583 {ACPI_DMT_UINT16, ACPI_NHLT6_OFFSET (WorkHorizontalAngleBegin), "Work Horizontal Angle Begin", 0}, 1584 {ACPI_DMT_UINT16, ACPI_NHLT6_OFFSET (WorkHorizontalAngleEnd), "Work Horizontal Angle End", 0}, 1585 ACPI_DMT_TERMINATOR 1586 }; 1587 1588 /* Number of DeviceInfo structures */ 1589 1590 ACPI_DMTABLE_INFO AcpiDmTableInfoNhlt7[] = 1591 { 1592 {ACPI_DMT_UINT8, ACPI_NHLT7_OFFSET (StructureCount), "Device Info struct count", 0}, 1593 ACPI_DMT_TERMINATOR 1594 }; 1595 1596 /* The DeviceInfo structure */ 1597 1598 ACPI_DMTABLE_INFO AcpiDmTableInfoNhlt7a[] = 1599 { 1600 {ACPI_DMT_UUID, ACPI_NHLT7A_OFFSET (DeviceId), "Device ID GUID", 0}, 1601 {ACPI_DMT_UINT8, ACPI_NHLT7A_OFFSET (DeviceInstanceId), "Device Instance ID", 0}, 1602 {ACPI_DMT_UINT8, ACPI_NHLT7A_OFFSET (DevicePortId), "Device Port ID", 0}, 1603 ACPI_DMT_TERMINATOR 1604 }; 1605 1606 ACPI_DMTABLE_INFO AcpiDmTableInfoNhlt7b[] = 1607 { 1608 {ACPI_DMT_RAW_BUFFER, 0, "Bytes", 0}, 1609 ACPI_DMT_TERMINATOR 1610 }; 1611 1612 /* Sensitivity Extension */ 1613 1614 ACPI_DMTABLE_INFO AcpiDmTableInfoNhlt9[] = 1615 { 1616 {ACPI_DMT_UINT32, ACPI_NHLT9_OFFSET (SNR), "Signal-to-noise ratio", 0}, 1617 {ACPI_DMT_UINT32, ACPI_NHLT9_OFFSET (Sensitivity), "Mic Sensitivity", 0}, 1618 ACPI_DMT_TERMINATOR 1619 }; 1620 1621 1622 /******************************************************************************* 1623 * 1624 * PCCT - Platform Communications Channel Table (ACPI 5.0) 1625 * 1626 ******************************************************************************/ 1627 1628 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct[] = 1629 { 1630 {ACPI_DMT_UINT32, ACPI_PCCT_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1631 {ACPI_DMT_FLAG0, ACPI_PCCT_FLAG_OFFSET (Flags,0), "Platform", 0}, 1632 {ACPI_DMT_UINT64, ACPI_PCCT_OFFSET (Reserved), "Reserved", 0}, 1633 ACPI_DMT_TERMINATOR 1634 }; 1635 1636 /* PCCT subtables */ 1637 1638 ACPI_DMTABLE_INFO AcpiDmTableInfoPcctHdr[] = 1639 { 1640 {ACPI_DMT_PCCT, ACPI_PCCT0_OFFSET (Header.Type), "Subtable Type", 0}, 1641 {ACPI_DMT_UINT8, ACPI_PCCT0_OFFSET (Header.Length), "Length", DT_LENGTH}, 1642 ACPI_DMT_TERMINATOR 1643 }; 1644 1645 /* 0: Generic Communications Subspace */ 1646 1647 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct0[] = 1648 { 1649 {ACPI_DMT_UINT48, ACPI_PCCT0_OFFSET (Reserved[0]), "Reserved", 0}, 1650 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (BaseAddress), "Base Address", 0}, 1651 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (Length), "Address Length", 0}, 1652 {ACPI_DMT_GAS, ACPI_PCCT0_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1653 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (PreserveMask), "Preserve Mask", 0}, 1654 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (WriteMask), "Write Mask", 0}, 1655 {ACPI_DMT_UINT32, ACPI_PCCT0_OFFSET (Latency), "Command Latency", 0}, 1656 {ACPI_DMT_UINT32, ACPI_PCCT0_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1657 {ACPI_DMT_UINT16, ACPI_PCCT0_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1658 ACPI_DMT_TERMINATOR 1659 }; 1660 1661 /* 1: HW-reduced Communications Subspace (ACPI 5.1) */ 1662 1663 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct1[] = 1664 { 1665 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1666 {ACPI_DMT_UINT8, ACPI_PCCT1_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1667 {ACPI_DMT_FLAG0, ACPI_PCCT1_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1668 {ACPI_DMT_FLAG1, ACPI_PCCT1_FLAG_OFFSET (Flags,0), "Mode", 0}, 1669 {ACPI_DMT_UINT8, ACPI_PCCT1_OFFSET (Reserved), "Reserved", 0}, 1670 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (BaseAddress), "Base Address", 0}, 1671 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (Length), "Address Length", 0}, 1672 {ACPI_DMT_GAS, ACPI_PCCT1_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1673 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (PreserveMask), "Preserve Mask", 0}, 1674 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (WriteMask), "Write Mask", 0}, 1675 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (Latency), "Command Latency", 0}, 1676 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1677 {ACPI_DMT_UINT16, ACPI_PCCT1_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1678 ACPI_DMT_TERMINATOR 1679 }; 1680 1681 /* 2: HW-reduced Communications Subspace Type 2 (ACPI 6.1) */ 1682 1683 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct2[] = 1684 { 1685 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1686 {ACPI_DMT_UINT8, ACPI_PCCT2_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1687 {ACPI_DMT_FLAG0, ACPI_PCCT2_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1688 {ACPI_DMT_FLAG1, ACPI_PCCT2_FLAG_OFFSET (Flags,0), "Mode", 0}, 1689 {ACPI_DMT_UINT8, ACPI_PCCT2_OFFSET (Reserved), "Reserved", 0}, 1690 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (BaseAddress), "Base Address", 0}, 1691 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (Length), "Address Length", 0}, 1692 {ACPI_DMT_GAS, ACPI_PCCT2_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1693 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (PreserveMask), "Preserve Mask", 0}, 1694 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (WriteMask), "Write Mask", 0}, 1695 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (Latency), "Command Latency", 0}, 1696 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1697 {ACPI_DMT_UINT16, ACPI_PCCT2_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1698 {ACPI_DMT_GAS, ACPI_PCCT2_OFFSET (PlatformAckRegister), "Platform ACK Register", 0}, 1699 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0}, 1700 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (AckWriteMask), "ACK Write Mask", 0}, 1701 ACPI_DMT_TERMINATOR 1702 }; 1703 1704 /* 3: Extended PCC Master Subspace Type 3 (ACPI 6.2) */ 1705 1706 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct3[] = 1707 { 1708 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1709 {ACPI_DMT_UINT8, ACPI_PCCT3_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1710 {ACPI_DMT_FLAG0, ACPI_PCCT3_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1711 {ACPI_DMT_FLAG1, ACPI_PCCT3_FLAG_OFFSET (Flags,0), "Mode", 0}, 1712 {ACPI_DMT_UINT8, ACPI_PCCT3_OFFSET (Reserved1), "Reserved", 0}, 1713 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (BaseAddress), "Base Address", 0}, 1714 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (Length), "Address Length", 0}, 1715 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1716 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (PreserveMask), "Preserve Mask", 0}, 1717 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (WriteMask), "Write Mask", 0}, 1718 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (Latency), "Command Latency", 0}, 1719 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1720 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1721 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (PlatformAckRegister), "Platform ACK Register", 0}, 1722 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0}, 1723 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (AckSetMask), "ACK Set Mask", 0}, 1724 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (Reserved2), "Reserved", 0}, 1725 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (CmdCompleteRegister), "Command Complete Register", 0}, 1726 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdCompleteMask), "Command Complete Check Mask", 0}, 1727 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (CmdUpdateRegister), "Command Update Register", 0}, 1728 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdUpdatePreserveMask), "Command Update Preserve Mask", 0}, 1729 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdUpdateSetMask), "Command Update Set Mask", 0}, 1730 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (ErrorStatusRegister), "Error Status Register", 0}, 1731 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (ErrorStatusMask), "Error Status Mask", 0}, 1732 ACPI_DMT_TERMINATOR 1733 }; 1734 1735 /* 4: Extended PCC Slave Subspace Type 4 (ACPI 6.2) */ 1736 1737 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct4[] = 1738 { 1739 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1740 {ACPI_DMT_UINT8, ACPI_PCCT4_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1741 {ACPI_DMT_FLAG0, ACPI_PCCT4_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1742 {ACPI_DMT_FLAG1, ACPI_PCCT4_FLAG_OFFSET (Flags,0), "Mode", 0}, 1743 {ACPI_DMT_UINT8, ACPI_PCCT4_OFFSET (Reserved1), "Reserved", 0}, 1744 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (BaseAddress), "Base Address", 0}, 1745 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (Length), "Address Length", 0}, 1746 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1747 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (PreserveMask), "Preserve Mask", 0}, 1748 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (WriteMask), "Write Mask", 0}, 1749 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (Latency), "Command Latency", 0}, 1750 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1751 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1752 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (PlatformAckRegister), "Platform ACK Register", 0}, 1753 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0}, 1754 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (AckSetMask), "ACK Set Mask", 0}, 1755 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (Reserved2), "Reserved", 0}, 1756 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (CmdCompleteRegister), "Command Complete Register", 0}, 1757 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdCompleteMask), "Command Complete Check Mask", 0}, 1758 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (CmdUpdateRegister), "Command Update Register", 0}, 1759 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdUpdatePreserveMask), "Command Update Preserve Mask", 0}, 1760 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdUpdateSetMask), "Command Update Set Mask", 0}, 1761 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (ErrorStatusRegister), "Error Status Register", 0}, 1762 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (ErrorStatusMask), "Error Status Mask", 0}, 1763 ACPI_DMT_TERMINATOR 1764 }; 1765 1766 /* 5: HW Registers based Communications Subspace */ 1767 1768 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct5[] = 1769 { 1770 {ACPI_DMT_UINT16, ACPI_PCCT5_OFFSET (Version), "Version", 0}, 1771 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (BaseAddress), "Base Address", 0}, 1772 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (Length), "Length", 0}, 1773 {ACPI_DMT_GAS, ACPI_PCCT5_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1774 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (DoorbellPreserve), "Preserve Mask", 0}, 1775 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (DoorbellWrite), "Write Mask", 0}, 1776 {ACPI_DMT_GAS, ACPI_PCCT5_OFFSET (CmdCompleteRegister), "Command Complete Register", 0}, 1777 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (CmdCompleteMask), "Command Complete Check Mask", 0}, 1778 {ACPI_DMT_GAS, ACPI_PCCT5_OFFSET (ErrorStatusRegister), "Error Status Register", 0}, 1779 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (ErrorStatusMask), "Error Status Mask", 0}, 1780 {ACPI_DMT_UINT32, ACPI_PCCT5_OFFSET (NominalLatency), "Nominal Latency", 0}, 1781 {ACPI_DMT_UINT32, ACPI_PCCT5_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1782 ACPI_DMT_TERMINATOR 1783 }; 1784 1785 1786 /******************************************************************************* 1787 * 1788 * PDTT - Platform Debug Trigger Table (ACPI 6.2) 1789 * 1790 ******************************************************************************/ 1791 1792 ACPI_DMTABLE_INFO AcpiDmTableInfoPdtt[] = 1793 { 1794 {ACPI_DMT_UINT8, ACPI_PDTT_OFFSET (TriggerCount), "Trigger Count", 0}, 1795 {ACPI_DMT_UINT24, ACPI_PDTT_OFFSET (Reserved), "Reserved", 0}, 1796 {ACPI_DMT_UINT32, ACPI_PDTT_OFFSET (ArrayOffset), "Array Offset", 0}, 1797 ACPI_DMT_TERMINATOR 1798 }; 1799 1800 ACPI_DMTABLE_INFO AcpiDmTableInfoPdtt0[] = 1801 { 1802 {ACPI_DMT_UINT8, ACPI_PDTT0_OFFSET (SubchannelId), "Subchannel Id", 0}, 1803 {ACPI_DMT_UINT8, ACPI_PDTT0_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1804 {ACPI_DMT_FLAG0, ACPI_PDTT0_FLAG_OFFSET (Flags,0), "Runtime Trigger", 0}, 1805 {ACPI_DMT_FLAG1, ACPI_PDTT0_FLAG_OFFSET (Flags,0), "Wait for Completion", 0}, 1806 {ACPI_DMT_FLAG2, ACPI_PDTT0_FLAG_OFFSET (Flags,0), "Trigger Order", 0}, 1807 ACPI_DMT_TERMINATOR 1808 }; 1809 1810 1811 /******************************************************************************* 1812 * 1813 * PHAT - Platform Health Assessment Table (ACPI 6.4) 1814 * 1815 ******************************************************************************/ 1816 1817 /* Common subtable header */ 1818 1819 ACPI_DMTABLE_INFO AcpiDmTableInfoPhatHdr[] = 1820 { 1821 {ACPI_DMT_PHAT, ACPI_PHATH_OFFSET (Type), "Subtable Type", 0}, 1822 {ACPI_DMT_UINT16, ACPI_PHATH_OFFSET (Length), "Length", DT_LENGTH}, 1823 {ACPI_DMT_UINT8, ACPI_PHATH_OFFSET (Revision), "Revision", 0}, 1824 ACPI_DMT_TERMINATOR 1825 }; 1826 1827 /* 0: Firmware version table */ 1828 1829 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat0[] = 1830 { 1831 {ACPI_DMT_UINT24, ACPI_PHAT0_OFFSET (Reserved), "Reserved", 0}, 1832 {ACPI_DMT_UINT32, ACPI_PHAT0_OFFSET (ElementCount), "Element Count", 0}, 1833 ACPI_DMT_TERMINATOR 1834 }; 1835 1836 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat0a[] = 1837 { 1838 {ACPI_DMT_UUID, ACPI_PHAT0A_OFFSET (Guid), "GUID", 0}, 1839 {ACPI_DMT_UINT64, ACPI_PHAT0A_OFFSET (VersionValue), "Version Value", 0}, 1840 {ACPI_DMT_UINT32, ACPI_PHAT0A_OFFSET (ProducerId), "Producer ID", 0}, 1841 ACPI_DMT_TERMINATOR 1842 }; 1843 1844 /* 1: Firmware Health Data Record */ 1845 1846 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat1[] = 1847 { 1848 {ACPI_DMT_UINT16, ACPI_PHAT1_OFFSET (Reserved), "Reserved", 0}, 1849 {ACPI_DMT_UINT8, ACPI_PHAT1_OFFSET (Health), "Health", 0}, 1850 {ACPI_DMT_UUID, ACPI_PHAT1_OFFSET (DeviceGuid), "Device GUID", 0}, 1851 {ACPI_DMT_UINT32, ACPI_PHAT1_OFFSET (DeviceSpecificOffset), "Device-Specific Offset", 0}, 1852 ACPI_DMT_TERMINATOR 1853 }; 1854 1855 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat1a[] = 1856 { 1857 {ACPI_DMT_UNICODE, 0, "Device Path", 0}, 1858 ACPI_DMT_TERMINATOR 1859 }; 1860 1861 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat1b[] = 1862 { 1863 {ACPI_DMT_RAW_BUFFER, 0, "Device-Specific Data", DT_OPTIONAL}, 1864 ACPI_DMT_TERMINATOR 1865 }; 1866 1867 1868 /******************************************************************************* 1869 * 1870 * PMTT - Platform Memory Topology Table 1871 * 1872 ******************************************************************************/ 1873 1874 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt[] = 1875 { 1876 {ACPI_DMT_UINT32, ACPI_PMTT_OFFSET (MemoryDeviceCount), "Memory Device Count", 0}, 1877 ACPI_DMT_TERMINATOR 1878 }; 1879 1880 /* Common Subtable header (one per Subtable) */ 1881 1882 #define ACPI_DM_PMTT_HEADER \ 1883 {ACPI_DMT_PMTT, ACPI_PMTTH_OFFSET (Type), "Subtable Type", 0}, \ 1884 {ACPI_DMT_UINT8, ACPI_PMTTH_OFFSET (Reserved1), "Reserved", 0}, \ 1885 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Length), "Length", DT_LENGTH}, \ 1886 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, \ 1887 {ACPI_DMT_FLAG0, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Top-level Device", 0}, \ 1888 {ACPI_DMT_FLAG1, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Physical Element", 0}, \ 1889 {ACPI_DMT_FLAGS2, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Memory Type", 0}, \ 1890 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Reserved2), "Reserved", 0}, \ 1891 {ACPI_DMT_UINT32, ACPI_PMTTH_OFFSET (MemoryDeviceCount), "Memory Device Count", 0} 1892 1893 /* PMTT Subtables */ 1894 1895 /* 0: Socket */ 1896 1897 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt0[] = 1898 { 1899 ACPI_DM_PMTT_HEADER, 1900 {ACPI_DMT_UINT16, ACPI_PMTT0_OFFSET (SocketId), "Socket ID", 0}, 1901 {ACPI_DMT_UINT16, ACPI_PMTT0_OFFSET (Reserved), "Reserved", 0}, 1902 ACPI_DMT_TERMINATOR 1903 }; 1904 1905 /* 1: Memory Controller */ 1906 1907 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt1[] = 1908 { 1909 ACPI_DM_PMTT_HEADER, 1910 {ACPI_DMT_UINT16, ACPI_PMTT1_OFFSET (ControllerId), "Controller ID", 0}, 1911 {ACPI_DMT_UINT16, ACPI_PMTT1_OFFSET (Reserved), "Reserved", 0}, 1912 ACPI_DMT_TERMINATOR 1913 }; 1914 1915 /* 2: Physical Component */ 1916 1917 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt2[] = 1918 { 1919 ACPI_DM_PMTT_HEADER, 1920 {ACPI_DMT_UINT32, ACPI_PMTT2_OFFSET (BiosHandle), "Bios Handle", 0}, 1921 ACPI_DMT_TERMINATOR 1922 }; 1923 1924 /* 0xFF: Vendor Specific */ 1925 1926 ACPI_DMTABLE_INFO AcpiDmTableInfoPmttVendor[] = 1927 { 1928 ACPI_DM_PMTT_HEADER, 1929 {ACPI_DMT_UUID, ACPI_PMTT_VENDOR_OFFSET (TypeUuid), "Type Uuid", 0}, 1930 {ACPI_DMT_PMTT_VENDOR, ACPI_PMTT_VENDOR_OFFSET (Specific), "Vendor Data", 0}, 1931 ACPI_DMT_TERMINATOR 1932 }; 1933 1934 1935 /******************************************************************************* 1936 * 1937 * PPTT - Processor Properties Topology Table (ACPI 6.2) 1938 * 1939 ******************************************************************************/ 1940 1941 /* Main table consists of only the standard ACPI header - subtables follow */ 1942 1943 /* Common Subtable header (one per Subtable) */ 1944 1945 ACPI_DMTABLE_INFO AcpiDmTableInfoPpttHdr[] = 1946 { 1947 {ACPI_DMT_PPTT, ACPI_PPTTH_OFFSET (Type), "Subtable Type", 0}, 1948 {ACPI_DMT_UINT8, ACPI_PPTTH_OFFSET (Length), "Length", 0}, 1949 ACPI_DMT_TERMINATOR 1950 }; 1951 1952 /* 0: Processor hierarchy node */ 1953 1954 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt0[] = 1955 { 1956 {ACPI_DMT_UINT16, ACPI_PPTT0_OFFSET (Reserved), "Reserved", 0}, 1957 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (Flags), "Flags (decoded below)", 0}, 1958 {ACPI_DMT_FLAG0, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Physical package", 0}, 1959 {ACPI_DMT_FLAG1, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "ACPI Processor ID valid", 0}, 1960 {ACPI_DMT_FLAG2, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Processor is a thread", 0}, 1961 {ACPI_DMT_FLAG3, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Node is a leaf", 0}, 1962 {ACPI_DMT_FLAG4, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Identical Implementation", 0}, 1963 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (Parent), "Parent", 0}, 1964 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (AcpiProcessorId), "ACPI Processor ID", 0}, 1965 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (NumberOfPrivResources), "Private Resource Number", 0}, 1966 ACPI_DMT_TERMINATOR 1967 }; 1968 1969 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt0a[] = 1970 { 1971 {ACPI_DMT_UINT32, 0, "Private Resource", DT_OPTIONAL}, 1972 ACPI_DMT_TERMINATOR 1973 }; 1974 1975 /* 1: Cache type */ 1976 1977 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt1[] = 1978 { 1979 {ACPI_DMT_UINT16, ACPI_PPTT1_OFFSET (Reserved), "Reserved", 0}, 1980 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (Flags), "Flags (decoded below)", 0}, 1981 {ACPI_DMT_FLAG0, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Size valid", 0}, 1982 {ACPI_DMT_FLAG1, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Number of Sets valid", 0}, 1983 {ACPI_DMT_FLAG2, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Associativity valid", 0}, 1984 {ACPI_DMT_FLAG3, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Allocation Type valid", 0}, 1985 {ACPI_DMT_FLAG4, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Cache Type valid", 0}, 1986 {ACPI_DMT_FLAG5, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Write Policy valid", 0}, 1987 {ACPI_DMT_FLAG6, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Line Size valid", 0}, 1988 {ACPI_DMT_FLAG7, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Cache ID valid", 0}, 1989 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (NextLevelOfCache), "Next Level of Cache", 0}, 1990 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (Size), "Size", 0}, 1991 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (NumberOfSets), "Number of Sets", 0}, 1992 {ACPI_DMT_UINT8, ACPI_PPTT1_OFFSET (Associativity), "Associativity", 0}, 1993 {ACPI_DMT_UINT8, ACPI_PPTT1_OFFSET (Attributes), "Attributes", 0}, 1994 {ACPI_DMT_FLAGS0, ACPI_PPTT1_OFFSET (Attributes), "Allocation Type", 0}, 1995 {ACPI_DMT_FLAGS2, ACPI_PPTT1_OFFSET (Attributes), "Cache Type", 0}, 1996 {ACPI_DMT_FLAG4, ACPI_PPTT1_OFFSET (Attributes), "Write Policy", 0}, 1997 {ACPI_DMT_UINT16, ACPI_PPTT1_OFFSET (LineSize), "Line Size", 0}, 1998 ACPI_DMT_TERMINATOR 1999 }; 2000 2001 /* 1: cache type v1 */ 2002 2003 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt1a[] = 2004 { 2005 {ACPI_DMT_UINT32, ACPI_PPTT1A_OFFSET (CacheId), "Cache ID", 0}, 2006 ACPI_DMT_TERMINATOR 2007 }; 2008 2009 /* 2: ID */ 2010 2011 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt2[] = 2012 { 2013 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (Reserved), "Reserved", 0}, 2014 {ACPI_DMT_UINT32, ACPI_PPTT2_OFFSET (VendorId), "Vendor ID", 0}, 2015 {ACPI_DMT_UINT64, ACPI_PPTT2_OFFSET (Level1Id), "Level1 ID", 0}, 2016 {ACPI_DMT_UINT64, ACPI_PPTT2_OFFSET (Level2Id), "Level2 ID", 0}, 2017 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (MajorRev), "Major revision", 0}, 2018 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (MinorRev), "Minor revision", 0}, 2019 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (SpinRev), "Spin revision", 0}, 2020 ACPI_DMT_TERMINATOR 2021 }; 2022 2023 2024 /******************************************************************************* 2025 * 2026 * PRMT - Platform Runtime Mechanism Table 2027 * Version 1 2028 * 2029 ******************************************************************************/ 2030 2031 ACPI_DMTABLE_INFO AcpiDmTableInfoPrmtHdr[] = 2032 { 2033 {ACPI_DMT_UUID, ACPI_PRMTH_OFFSET (PlatformGuid[0]), "Platform GUID", 0}, 2034 {ACPI_DMT_UINT32, ACPI_PRMTH_OFFSET (ModuleInfoOffset), "Module info offset", 0}, 2035 {ACPI_DMT_UINT32, ACPI_PRMTH_OFFSET (ModuleInfoCount), "Module info count", 0}, 2036 ACPI_DMT_NEW_LINE, 2037 ACPI_DMT_TERMINATOR 2038 2039 }; 2040 2041 ACPI_DMTABLE_INFO AcpiDmTableInfoPrmtModule[] = 2042 { 2043 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (Revision), "Revision", 0}, 2044 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (Length), "Length", 0}, 2045 {ACPI_DMT_UUID, ACPI_PRMT0_OFFSET (ModuleGuid[0]), "Module GUID", 0}, 2046 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (MajorRev), "Major Revision", 0}, 2047 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (MinorRev), "Minor Revision", 0}, 2048 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (HandlerInfoCount), "Handler Info Count", 0}, 2049 {ACPI_DMT_UINT32, ACPI_PRMT0_OFFSET (HandlerInfoOffset), "Handler Info Offset", 0}, 2050 {ACPI_DMT_UINT64, ACPI_PRMT0_OFFSET (MmioListPointer), "Mmio List pointer", 0}, 2051 ACPI_DMT_NEW_LINE, 2052 ACPI_DMT_TERMINATOR 2053 2054 }; 2055 2056 ACPI_DMTABLE_INFO AcpiDmTableInfoPrmtHandler[] = 2057 { 2058 {ACPI_DMT_UINT16, ACPI_PRMT1_OFFSET (Revision), "Revision", 0}, 2059 {ACPI_DMT_UINT16, ACPI_PRMT1_OFFSET (Length), "Length", 0}, 2060 {ACPI_DMT_UUID, ACPI_PRMT1_OFFSET (HandlerGuid[0]), "Handler GUID", 0}, 2061 {ACPI_DMT_UINT64, ACPI_PRMT1_OFFSET (HandlerAddress), "Handler address", 0}, 2062 {ACPI_DMT_UINT64, ACPI_PRMT1_OFFSET (StaticDataBufferAddress),"Static Data Address", 0}, 2063 {ACPI_DMT_UINT64, ACPI_PRMT1_OFFSET (AcpiParamBufferAddress), "ACPI Parameter Address", 0}, 2064 ACPI_DMT_NEW_LINE, 2065 ACPI_DMT_TERMINATOR 2066 2067 }; 2068 2069 2070 /******************************************************************************* 2071 * 2072 * RASF - RAS Feature table 2073 * 2074 ******************************************************************************/ 2075 2076 ACPI_DMTABLE_INFO AcpiDmTableInfoRasf[] = 2077 { 2078 {ACPI_DMT_BUF12, ACPI_RASF_OFFSET (ChannelId[0]), "Channel ID", 0}, 2079 ACPI_DMT_TERMINATOR 2080 }; 2081 2082 2083 /******************************************************************************* 2084 * 2085 * RGRT - Regulatory Graphics Resource Table 2086 * 2087 ******************************************************************************/ 2088 2089 ACPI_DMTABLE_INFO AcpiDmTableInfoRgrt[] = 2090 { 2091 {ACPI_DMT_UINT16, ACPI_RGRT_OFFSET (Version), "Version", 0}, 2092 {ACPI_DMT_RGRT, ACPI_RGRT_OFFSET (ImageType), "Image Type", 0}, 2093 {ACPI_DMT_UINT8, ACPI_RGRT_OFFSET (Reserved), "Reserved", 0}, 2094 ACPI_DMT_TERMINATOR 2095 }; 2096 2097 /* 2098 * We treat the binary image field as its own subtable (to make 2099 * ACPI_DMT_RAW_BUFFER work properly). 2100 */ 2101 ACPI_DMTABLE_INFO AcpiDmTableInfoRgrt0[] = 2102 { 2103 {ACPI_DMT_RAW_BUFFER, 0, "Image", 0}, 2104 ACPI_DMT_TERMINATOR 2105 }; 2106 2107 2108 /******************************************************************************* 2109 * 2110 * RHCT - RISC-V Hart Capabilities Table 2111 * 2112 ******************************************************************************/ 2113 2114 ACPI_DMTABLE_INFO AcpiDmTableInfoRhct[] = 2115 { 2116 {ACPI_DMT_UINT32, ACPI_RHCT_OFFSET (Flags), "Flags", 0}, 2117 {ACPI_DMT_UINT64, ACPI_RHCT_OFFSET (TimeBaseFreq), "Timer Base Frequency", 0}, 2118 {ACPI_DMT_UINT32, ACPI_RHCT_OFFSET (NodeCount), "Number of nodes", 0}, 2119 {ACPI_DMT_UINT32, ACPI_RHCT_OFFSET (NodeOffset), "Offset to the node array", 0}, 2120 ACPI_DMT_TERMINATOR 2121 }; 2122 2123 2124 /* Common Subtable header (one per Subtable) */ 2125 2126 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctNodeHdr[] = 2127 { 2128 {ACPI_DMT_RHCT, ACPI_RHCTH_OFFSET (Type), "Subtable Type", 0}, 2129 {ACPI_DMT_UINT16, ACPI_RHCTH_OFFSET (Length), "Length", 0}, 2130 {ACPI_DMT_UINT16, ACPI_RHCTH_OFFSET (Revision), "Revision", 0}, 2131 ACPI_DMT_TERMINATOR 2132 }; 2133 2134 /* 0: ISA string type */ 2135 2136 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctIsa1[] = 2137 { 2138 {ACPI_DMT_UINT16, ACPI_RHCT0_OFFSET (IsaLength), "ISA string length", 0}, 2139 {ACPI_DMT_STRING, ACPI_RHCT0_OFFSET (Isa[0]), "ISA string", 0}, 2140 ACPI_DMT_TERMINATOR 2141 }; 2142 2143 2144 /* Optional padding field */ 2145 2146 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctIsaPad[] = 2147 { 2148 {ACPI_DMT_RAW_BUFFER, 0, "Optional Padding", DT_OPTIONAL}, 2149 ACPI_DMT_TERMINATOR 2150 }; 2151 2152 /* 1: CMO node type */ 2153 2154 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctCmo1[] = 2155 { 2156 {ACPI_DMT_UINT8, ACPI_RHCT1_OFFSET (Reserved), "Reserved", 0}, 2157 {ACPI_DMT_UINT8, ACPI_RHCT1_OFFSET (CbomSize), "CBOM Block Size", 0}, 2158 {ACPI_DMT_UINT8, ACPI_RHCT1_OFFSET (CbopSize), "CBOP Block Size", 0}, 2159 {ACPI_DMT_UINT8, ACPI_RHCT1_OFFSET (CbozSize), "CBOZ Block Size", 0}, 2160 ACPI_DMT_TERMINATOR 2161 }; 2162 2163 /* 2: MMU node type */ 2164 2165 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctMmu1[] = 2166 { 2167 {ACPI_DMT_UINT8, ACPI_RHCT2_OFFSET (Reserved), "Reserved", 0}, 2168 {ACPI_DMT_UINT8, ACPI_RHCT2_OFFSET (MmuType), "MMU Type", 0}, 2169 ACPI_DMT_TERMINATOR 2170 }; 2171 2172 /* 0xFFFF: Hart Info type */ 2173 2174 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctHartInfo1[] = 2175 { 2176 {ACPI_DMT_UINT16, ACPI_RHCTFFFF_OFFSET (NumOffsets), "Number of offsets", 0}, 2177 {ACPI_DMT_UINT32, ACPI_RHCTFFFF_OFFSET (Uid), "Processor UID", 0}, 2178 ACPI_DMT_TERMINATOR 2179 }; 2180 2181 2182 ACPI_DMTABLE_INFO AcpiDmTableInfoRhctHartInfo2[] = 2183 { 2184 {ACPI_DMT_UINT32, 0, "Nodes", DT_OPTIONAL}, 2185 ACPI_DMT_TERMINATOR 2186 }; 2187 2188 2189 /******************************************************************************* 2190 * 2191 * S3PT - S3 Performance Table 2192 * 2193 ******************************************************************************/ 2194 2195 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt[] = 2196 { 2197 {ACPI_DMT_SIG, ACPI_S3PT_OFFSET (Signature[0]), "Signature", 0}, 2198 {ACPI_DMT_UINT32, ACPI_S3PT_OFFSET (Length), "Length", DT_LENGTH}, 2199 ACPI_DMT_TERMINATOR 2200 }; 2201 2202 /* S3PT subtable header */ 2203 2204 ACPI_DMTABLE_INFO AcpiDmTableInfoS3ptHdr[] = 2205 { 2206 {ACPI_DMT_UINT16, ACPI_S3PTH_OFFSET (Type), "Type", 0}, 2207 {ACPI_DMT_UINT8, ACPI_S3PTH_OFFSET (Length), "Length", DT_LENGTH}, 2208 {ACPI_DMT_UINT8, ACPI_S3PTH_OFFSET (Revision), "Revision", 0}, 2209 ACPI_DMT_TERMINATOR 2210 }; 2211 2212 /* 0: Basic S3 Resume Performance Record */ 2213 2214 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt0[] = 2215 { 2216 {ACPI_DMT_UINT32, ACPI_S3PT0_OFFSET (ResumeCount), "Resume Count", 0}, 2217 {ACPI_DMT_UINT64, ACPI_S3PT0_OFFSET (FullResume), "Full Resume", 0}, 2218 {ACPI_DMT_UINT64, ACPI_S3PT0_OFFSET (AverageResume), "Average Resume", 0}, 2219 ACPI_DMT_TERMINATOR 2220 }; 2221 2222 /* 1: Basic S3 Suspend Performance Record */ 2223 2224 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt1[] = 2225 { 2226 {ACPI_DMT_UINT64, ACPI_S3PT1_OFFSET (SuspendStart), "Suspend Start", 0}, 2227 {ACPI_DMT_UINT64, ACPI_S3PT1_OFFSET (SuspendEnd), "Suspend End", 0}, 2228 ACPI_DMT_TERMINATOR 2229 }; 2230 2231 2232 /******************************************************************************* 2233 * 2234 * SBST - Smart Battery Specification Table 2235 * 2236 ******************************************************************************/ 2237 2238 ACPI_DMTABLE_INFO AcpiDmTableInfoSbst[] = 2239 { 2240 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (WarningLevel), "Warning Level", 0}, 2241 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (LowLevel), "Low Level", 0}, 2242 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (CriticalLevel), "Critical Level", 0}, 2243 ACPI_DMT_TERMINATOR 2244 }; 2245 2246 2247 /******************************************************************************* 2248 * 2249 * SDEI - Software Delegated Exception Interface Descriptor Table 2250 * 2251 ******************************************************************************/ 2252 2253 ACPI_DMTABLE_INFO AcpiDmTableInfoSdei[] = 2254 { 2255 ACPI_DMT_TERMINATOR 2256 }; 2257 2258 2259 /******************************************************************************* 2260 * 2261 * SDEV - Secure Devices Table (ACPI 6.2) 2262 * 2263 ******************************************************************************/ 2264 2265 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev[] = 2266 { 2267 ACPI_DMT_TERMINATOR 2268 }; 2269 2270 /* Common Subtable header (one per Subtable) */ 2271 2272 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevHdr[] = 2273 { 2274 {ACPI_DMT_SDEV, ACPI_SDEVH_OFFSET (Type), "Subtable Type", 0}, 2275 {ACPI_DMT_UINT8, ACPI_SDEVH_OFFSET (Flags), "Flags (decoded below)", 0}, 2276 {ACPI_DMT_FLAG0, ACPI_SDEVH_FLAG_OFFSET (Flags,0), "Allow handoff to unsecure OS", 0}, 2277 {ACPI_DMT_FLAG1, ACPI_SDEVH_FLAG_OFFSET (Flags,0), "Secure access components present", 0}, 2278 {ACPI_DMT_UINT16, ACPI_SDEVH_OFFSET (Length), "Length", DT_LENGTH}, 2279 ACPI_DMT_TERMINATOR 2280 }; 2281 2282 /* SDEV Subtables */ 2283 2284 /* 0: Namespace Device Based Secure Device Structure */ 2285 2286 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev0[] = 2287 { 2288 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (DeviceIdOffset), "Device ID Offset", 0}, 2289 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (DeviceIdLength), "Device ID Length", 0}, 2290 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (VendorDataOffset), "Vendor Data Offset", 0}, 2291 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (VendorDataLength), "Vendor Data Length", 0}, 2292 ACPI_DMT_TERMINATOR 2293 }; 2294 2295 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev0a[] = 2296 { 2297 {ACPI_DMT_STRING, 0, "Namepath", 0}, 2298 ACPI_DMT_TERMINATOR 2299 }; 2300 2301 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev0b[] = 2302 { 2303 {ACPI_DMT_UINT16, ACPI_SDEV0B_OFFSET (SecureComponentOffset), "Secure Access Components Offset", 0}, 2304 {ACPI_DMT_UINT16, ACPI_SDEV0B_OFFSET (SecureComponentLength), "Secure Access Components Length", 0}, 2305 ACPI_DMT_TERMINATOR 2306 }; 2307 2308 /* Secure access components */ 2309 2310 /* Common secure access components header secure access component */ 2311 2312 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevSecCompHdr[] = 2313 { 2314 {ACPI_DMT_UINT8, ACPI_SDEVCH_OFFSET (Type), "Secure Component Type", 0}, 2315 {ACPI_DMT_UINT8, ACPI_SDEVCH_OFFSET (Flags), "Flags (decoded below)", 0}, 2316 {ACPI_DMT_UINT16, ACPI_SDEVCH_OFFSET (Length), "Length", 0}, 2317 ACPI_DMT_TERMINATOR 2318 }; 2319 2320 /* 0: Identification Based Secure Access Component */ 2321 2322 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevSecCompId[] = 2323 { 2324 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (HardwareIdOffset), "Hardware ID Offset", 0}, 2325 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (HardwareIdLength), "Hardware ID Length", 0}, 2326 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (SubsystemIdOffset), "Subsystem ID Offset", 0}, 2327 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (SubsystemIdLength), "Subsystem ID Length", 0}, 2328 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (HardwareRevision), "Hardware Revision", 0}, 2329 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (HardwareRevPresent), "Hardware Rev Present", 0}, 2330 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (ClassCodePresent), "Class Code Present", 0}, 2331 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (PciBaseClass), "PCI Base Class", 0}, 2332 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (PciSubClass), "PCI SubClass", 0}, 2333 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (PciProgrammingXface), "PCI Programming Xface", 0}, 2334 ACPI_DMT_TERMINATOR 2335 }; 2336 2337 /* 1: Memory Based Secure Access Component */ 2338 2339 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevSecCompMem[] = 2340 { 2341 {ACPI_DMT_UINT32, ACPI_SDEVC1_OFFSET (Reserved), "Reserved", 0}, 2342 {ACPI_DMT_UINT64, ACPI_SDEVC1_OFFSET (MemoryBaseAddress), "Memory Base Address", 0}, 2343 {ACPI_DMT_UINT64, ACPI_SDEVC1_OFFSET (MemoryLength), "Memory Length", 0}, 2344 ACPI_DMT_TERMINATOR 2345 }; 2346 2347 2348 /* 1: PCIe Endpoint Device Based Device Structure */ 2349 2350 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1[] = 2351 { 2352 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (Segment), "Segment", 0}, 2353 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (StartBus), "Start Bus", 0}, 2354 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (PathOffset), "Path Offset", 0}, 2355 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (PathLength), "Path Length", 0}, 2356 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (VendorDataOffset), "Vendor Data Offset", 0}, 2357 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (VendorDataLength), "Vendor Data Length", 0}, 2358 ACPI_DMT_TERMINATOR 2359 }; 2360 2361 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1a[] = 2362 { 2363 {ACPI_DMT_UINT8, ACPI_SDEV1A_OFFSET (Device), "Device", 0}, 2364 {ACPI_DMT_UINT8, ACPI_SDEV1A_OFFSET (Function), "Function", 0}, 2365 ACPI_DMT_TERMINATOR 2366 }; 2367 2368 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1b[] = 2369 { 2370 {ACPI_DMT_RAW_BUFFER, 0, "Vendor Data", 0}, /*, DT_OPTIONAL}, */ 2371 ACPI_DMT_TERMINATOR 2372 }; 2373 2374 /*! [End] no source code translation !*/ 2375
Indexes created Mon Sep 29 21:09:56 GMT 2025